diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index fd84822..1a1e756 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -12,6 +12,9 @@ # # See https://github.com/pre-commit/pre-commit +# Don't re-format vendored files +exclude: "^src/piolib/.*$" + ci: autoupdate_commit_msg: "chore: update pre-commit hooks" autofix_commit_msg: "style: pre-commit fixes" diff --git a/examples/virtualdisplay.py b/examples/virtualdisplay.py index 1fea2ae..be3aed8 100644 --- a/examples/virtualdisplay.py +++ b/examples/virtualdisplay.py @@ -20,14 +20,12 @@ Here's an example for running an emulator using a rom stored in "/tmp/snesrom.sm $ python virtualdisplay.py --pinout AdafruitMatrixHatBGR --scale 2 --backend xvfb --width 128 --height 128 --serpentine --num-address-lines 5 --num-planes 4 -- mednafen -snes.xscalefs 1 -snes.yscalefs 1 -snes.xres 128 -video.fs 1 -video.driver softfb /tmp/snesrom.smc """ -# To run a nice emulator: - - import shlex from subprocess import Popen import click import numpy as np +from PIL import ImageEnhance from pyvirtualdisplay.smartdisplay import SmartDisplay import adafruit_blinka_raspberry_pi5_piomatter as piomatter @@ -40,10 +38,12 @@ from adafruit_blinka_raspberry_pi5_piomatter.pixelmappers import simple_multilan @click.option("--backend", help="The pyvirtualdisplay backend to use", default="xvfb") @click.option("--extra-args", help="Extra arguments to pass to the backend server", default="") @click.option("--rfbport", help="The port number for the --backend xvnc", default=None, type=int) +@click.option("--brightness", help="The brightness factor of the image output to the matrix", + default=1.0, type=click.FloatRange(min=0.1, max=1.0)) @click.option("--use-xauth/--no-use-xauth", help="If a Xauthority file should be created", default=False) @piomatter_click.standard_options @click.argument("command", nargs=-1) -def main(scale, backend, use_xauth, extra_args, rfbport, width, height, serpentine, rotation, pinout, +def main(scale, backend, use_xauth, extra_args, rfbport, brightness, width, height, serpentine, rotation, pinout, n_planes, n_temporal_planes, n_addr_lines, n_lanes, command): kwargs = {} if backend == "xvnc": @@ -64,8 +64,12 @@ def main(scale, backend, use_xauth, extra_args, rfbport, width, height, serpenti with SmartDisplay(backend=backend, use_xauth=use_xauth, size=(round(width*scale),round(height*scale)), manage_global_env=False, **kwargs) as disp, Popen(command, env=disp.env()) as proc: while proc.poll() is None: img = disp.grab(autocrop=False) + if img is None: continue + if brightness != 1.0: + darkener = ImageEnhance.Brightness(img) + img = darkener.enhance(brightness) img = img.resize((width, height)) framebuffer[:, :] = np.array(img) matrix.show() diff --git a/examples/xdisplay_mirror.py b/examples/xdisplay_mirror.py index 16d35a6..1f78c05 100644 --- a/examples/xdisplay_mirror.py +++ b/examples/xdisplay_mirror.py @@ -20,7 +20,7 @@ This example command will mirror a 128x128 pixel square from the top left of the import click import numpy as np -from PIL import Image, ImageGrab +from PIL import Image, ImageEnhance, ImageGrab import adafruit_blinka_raspberry_pi5_piomatter as piomatter import adafruit_blinka_raspberry_pi5_piomatter.click as piomatter_click @@ -38,11 +38,13 @@ RESAMPLE_MAP = { @click.option("--mirror-region", help="Region of X display to mirror. Comma seperated x,y,w,h. " "Default will mirror entire display.", default="") @click.option("--x-display", help="The X display to mirror. Default is :0", default=":0") +@click.option("--brightness", help="The brightness factor of the image output to the matrix", + default=1.0, type=click.FloatRange(min=0.1, max=1.0)) @click.option("--resample-method", type=click.Choice(RESAMPLE_MAP), default="nearest", help="The resample method for PIL to use when resizing the screen image. Default is nearest") @piomatter_click.standard_options(n_lanes=2, n_temporal_planes=0) def main(width, height, serpentine, rotation, pinout, n_planes, - n_temporal_planes, n_addr_lines, n_lanes, mirror_region, x_display, resample_method): + n_temporal_planes, n_addr_lines, n_lanes, mirror_region, x_display, resample_method, brightness): if n_lanes != 2: pixelmap = simple_multilane_mapper(width, height, n_addr_lines, n_lanes) @@ -66,14 +68,16 @@ def main(width, height, serpentine, rotation, pinout, n_planes, while True: img = ImageGrab.grab(xdisplay=x_display) if mirror_region is not None: - img = img.crop((mirror_region[0], mirror_region[1], # left,top - mirror_region[0] + mirror_region[2], # right + img = img.crop((mirror_region[0], mirror_region[1], # left,top + mirror_region[0] + mirror_region[2], # right mirror_region[1] + mirror_region[3])) # bottom + if brightness != 1.0: + darkener = ImageEnhance.Brightness(img) + img = darkener.enhance(brightness) img = img.resize((width, height), RESAMPLE_MAP[resample_method]) framebuffer[:, :] = np.array(img) matrix.show() - if __name__ == '__main__': main() diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt new file mode 100644 index 0000000..ef7bc52 --- /dev/null +++ b/src/CMakeLists.txt @@ -0,0 +1,20 @@ +cmake_minimum_required(VERSION 3.12) + +project(protodemo C CXX) +set(CMAKE_C_STANDARD 11) +set(CMAKE_CXX_STANDARD 20) + +add_compile_options(-Wall -g3 -Og) +add_executable(protodemo + protodemo.cpp + piolib/piolib.c + piolib/pio_rp1.c +) + +add_custom_command( + OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/protomatter.pio.h + COMMAND python ${CMAKE_CURRENT_SOURCE_DIR}/assemble.py ${CMAKE_CURRENT_SOURCE_DIR}/protomatter.pio ${CMAKE_CURRENT_BINARY_DIR}/protomatter.pio.h + DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/assemble.py ${CMAKE_CURRENT_SOURCE_DIR}/protomatter.pio +) + +target_include_directories(protodemo PRIVATE include piolib/include) diff --git a/src/Makefile b/src/Makefile deleted file mode 100644 index 6915960..0000000 --- a/src/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -protodemo: protodemo.c piolib/*.c include/piomatter/*.h include/piomatter/protomatter.pio.h Makefile - g++ -std=c++20 -O3 -ggdb -x c++ -Iinclude -Ipiolib/include -o $@ $(filter %.c, $^) -Wno-narrowing - -matrixmap.h: - -include/piomatter/protomatter.pio.h: protomatter.pio assemble.py - python assemble.py $< $@ diff --git a/src/adafruit_blinka_raspberry_pi5_piomatter/click.py b/src/adafruit_blinka_raspberry_pi5_piomatter/click.py index 9aef1cb..53482e5 100644 --- a/src/adafruit_blinka_raspberry_pi5_piomatter/click.py +++ b/src/adafruit_blinka_raspberry_pi5_piomatter/click.py @@ -27,8 +27,8 @@ class _PybindEnumChoice(click.Choice): return r def _validate_temporal_planes(ctx, param, value): - if value not in (0, 2, 4): - raise click.BadParameter("must be 0, 2, or 4") + if value not in (0, 1, 2, 3, 4, 5): + raise click.BadParameter("must be from 0 to 5 (0 and 1 both disable temporal planes)") return value def standard_options( diff --git a/src/include/piomatter/matrixmap.h b/src/include/piomatter/matrixmap.h index f721a88..2fb9c5c 100644 --- a/src/include/piomatter/matrixmap.h +++ b/src/include/piomatter/matrixmap.h @@ -134,47 +134,27 @@ schedule_sequence make_temporal_dither_schedule(int n_planes, if (n_temporal_planes >= n_planes) { throw std::range_error("n_temporal_planes can't exceed n_planes"); } - if (n_temporal_planes != 2 && n_temporal_planes != 4) { - // the code can generate a schedule for 8 temporal planes, but it - // flickers intolerably - throw std::range_error("n_temporal_planes must be 0, 1, 2, or 4"); - } int n_real_planes = n_planes - n_temporal_planes; - schedule base_sched; - for (int j = 0; j < n_real_planes; j++) { - base_sched.emplace_back( - 9 - j, (1 << (n_temporal_planes + n_real_planes - j - 1)) / - n_temporal_planes); - } - schedule_sequence result; - auto add_sched = [&result, &base_sched](int plane, int count) { - auto sched = base_sched; + auto add_sched = [&result, n_real_planes, + n_temporal_planes](int i, int plane, int count) { + schedule sched; + for (int j = 0; j < n_real_planes; j++) { + int k = 1 << (n_temporal_planes + n_real_planes - j - 1); + sched.emplace_back(9 - j, (k + i) / n_temporal_planes); + } sched.emplace_back(9 - plane, count); result.emplace_back(sched); }; for (int i = 0; i < n_temporal_planes; i++) { - add_sched(n_real_planes + i, 1 << (n_temporal_planes - i - 1)); + add_sched(i, n_real_planes + i, 1 << (n_temporal_planes - i - 1)); } -#if 0 - std::vector counts(10, 0); - for (auto s : result) { - for(auto t: s) { - counts[t.shift] += t.active_time; - } - } - for (auto s : counts) { - printf("%d ", s); - } - printf("\n"); -#endif return rescale_schedule(result, pixels_across); - ; } struct matrix_geometry { diff --git a/src/include/piomatter/pins.h b/src/include/piomatter/pins.h index 9c2435b..3be6675 100644 --- a/src/include/piomatter/pins.h +++ b/src/include/piomatter/pins.h @@ -19,7 +19,7 @@ struct adafruit_matrix_bonnet_pinout { static constexpr uint32_t post_oe_delay = 0; static constexpr uint32_t post_latch_delay = 0; - static constexpr uint32_t post_addr_delay = 500; + static constexpr uint32_t post_addr_delay = 5; }; struct adafruit_matrix_bonnet_pinout_bgr { @@ -37,7 +37,7 @@ struct adafruit_matrix_bonnet_pinout_bgr { static constexpr uint32_t post_oe_delay = 0; static constexpr uint32_t post_latch_delay = 0; - static constexpr uint32_t post_addr_delay = 500; + static constexpr uint32_t post_addr_delay = 5; }; struct active3_pinout { @@ -56,7 +56,7 @@ struct active3_pinout { static constexpr uint32_t post_oe_delay = 0; static constexpr uint32_t post_latch_delay = 0; - static constexpr uint32_t post_addr_delay = 500; + static constexpr uint32_t post_addr_delay = 5; }; struct active3_pinout_bgr { @@ -75,7 +75,7 @@ struct active3_pinout_bgr { static constexpr uint32_t post_oe_delay = 0; static constexpr uint32_t post_latch_delay = 0; - static constexpr uint32_t post_addr_delay = 500; + static constexpr uint32_t post_addr_delay = 5; }; } // namespace piomatter diff --git a/src/include/piomatter/piomatter.h b/src/include/piomatter/piomatter.h index ba9bcae..c43f7ec 100644 --- a/src/include/piomatter/piomatter.h +++ b/src/include/piomatter/piomatter.h @@ -20,20 +20,6 @@ static uint64_t monotonicns64() { constexpr size_t MAX_XFER = 65532; -void pio_sm_xfer_data_large(PIO pio, int sm, int direction, size_t size, - uint32_t *databuf) { - while (size) { - size_t xfersize = std::min(size_t{MAX_XFER}, size); - int r = pio_sm_xfer_data(pio, sm, direction, xfersize, databuf); - if (r) { - throw std::runtime_error( - "pio_sm_xfer_data (reboot may be required)"); - } - size -= xfersize; - databuf += xfersize / sizeof(*databuf); - } -} - struct piomatter_base { piomatter_base() {} piomatter_base(const piomatter_base &) = delete; @@ -106,7 +92,7 @@ struct piomatter : piomatter_base { if (sm < 0) { throw std::runtime_error("pio_claim_unused_sm"); } - int r = pio_sm_config_xfer(pio, sm, PIO_DIR_TO_SM, MAX_XFER, 2); + int r = pio_sm_config_xfer(pio, sm, PIO_DIR_TO_SM, MAX_XFER, 3); if (r) { throw std::runtime_error("pio_sm_config_xfer"); } @@ -188,8 +174,7 @@ struct piomatter : piomatter_base { const auto &data = cur_buf[seq_idx]; auto datasize = sizeof(uint32_t) * data.size(); auto dataptr = const_cast(&data[0]); - pio_sm_xfer_data_large(pio, sm, PIO_DIR_TO_SM, datasize, - dataptr); + pio_sm_xfer_data(pio, sm, PIO_DIR_TO_SM, datasize, dataptr); t1 = monotonicns64(); if (t0 != t1) { fps = 1e9 / (t1 - t0); diff --git a/src/piolib/include/hardware/clocks.h b/src/piolib/include/hardware/clocks.h index c9c6fc1..b01b4be 100644 --- a/src/piolib/include/hardware/clocks.h +++ b/src/piolib/include/hardware/clocks.h @@ -8,16 +8,16 @@ #define _HARDWARE_CLOCKS_H enum clock_index { - clk_gpout0 = 0, ///< GPIO Muxing 0 - clk_gpout1, ///< GPIO Muxing 1 - clk_gpout2, ///< GPIO Muxing 2 - clk_gpout3, ///< GPIO Muxing 3 - clk_ref, ///< Watchdog and timers reference clock - clk_sys, ///< Processors, bus fabric, memory, memory mapped registers - clk_peri, ///< Peripheral clock for UART and SPI - clk_usb, ///< USB clock - clk_adc, ///< ADC clock - clk_rtc, ///< Real time clock + clk_gpout0 = 0, ///< GPIO Muxing 0 + clk_gpout1, ///< GPIO Muxing 1 + clk_gpout2, ///< GPIO Muxing 2 + clk_gpout3, ///< GPIO Muxing 3 + clk_ref, ///< Watchdog and timers reference clock + clk_sys, ///< Processors, bus fabric, memory, memory mapped registers + clk_peri, ///< Peripheral clock for UART and SPI + clk_usb, ///< USB clock + clk_adc, ///< ADC clock + clk_rtc, ///< Real time clock CLK_COUNT }; diff --git a/src/piolib/include/hardware/gpio.h b/src/piolib/include/hardware/gpio.h index 60282f7..47bede1 100644 --- a/src/piolib/include/hardware/gpio.h +++ b/src/piolib/include/hardware/gpio.h @@ -39,16 +39,14 @@ enum gpio_irq_level { }; enum gpio_override { - GPIO_OVERRIDE_NORMAL = - 0, ///< peripheral signal selected via \ref gpio_set_function - GPIO_OVERRIDE_INVERT = - 1, ///< invert peripheral signal selected via \ref gpio_set_function - GPIO_OVERRIDE_LOW = 2, ///< drive low/disable output - GPIO_OVERRIDE_HIGH = 3, ///< drive high/enable output + GPIO_OVERRIDE_NORMAL = 0, ///< peripheral signal selected via \ref gpio_set_function + GPIO_OVERRIDE_INVERT = 1, ///< invert peripheral signal selected via \ref gpio_set_function + GPIO_OVERRIDE_LOW = 2, ///< drive low/disable output + GPIO_OVERRIDE_HIGH = 3, ///< drive high/enable output }; enum gpio_slew_rate { - GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled - GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled + GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled + GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled }; enum gpio_drive_strength { diff --git a/src/piolib/include/hardware/pio_instructions.h b/src/piolib/include/hardware/pio_instructions.h index 4887f28..875b638 100644 --- a/src/piolib/include/hardware/pio_instructions.h +++ b/src/piolib/include/hardware/pio_instructions.h @@ -9,21 +9,18 @@ //#include "pico.h" -/** \brief PIO instruction encoding +/** \brief PIO instruction encoding * \defgroup pio_instructions pio_instructions * \ingroup hardware_pio + * + * Functions for generating PIO instruction encodings programmatically. In debug builds + *`PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` can be set to 1 to enable validation of encoding function + * parameters. * - * Functions for generating PIO instruction encodings programmatically. In debug - *builds `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` can be set to 1 to enable - *validation of encoding function parameters. - * - * For fuller descriptions of the instructions in question see the "RP2040 - *Datasheet" + * For fuller descriptions of the instructions in question see the "RP2040 Datasheet" */ -// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable -// assertions in the PIO instructions, type=bool, default=0, -// group=pio_instructions +// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=pio_instructions #ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS #define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0 #endif @@ -45,48 +42,44 @@ enum pio_instr_bits { }; #ifndef NDEBUG -#define _PIO_INVALID_IN_SRC 0x08u +#define _PIO_INVALID_IN_SRC 0x08u #define _PIO_INVALID_OUT_DEST 0x10u #define _PIO_INVALID_SET_DEST 0x20u -#define _PIO_INVALID_MOV_SRC 0x40u +#define _PIO_INVALID_MOV_SRC 0x40u #define _PIO_INVALID_MOV_DEST 0x80u #else -#define _PIO_INVALID_IN_SRC 0u +#define _PIO_INVALID_IN_SRC 0u #define _PIO_INVALID_OUT_DEST 0u #define _PIO_INVALID_SET_DEST 0u -#define _PIO_INVALID_MOV_SRC 0u +#define _PIO_INVALID_MOV_SRC 0u #define _PIO_INVALID_MOV_DEST 0u #endif -/*! \brief Enumeration of values to pass for source/destination args for - * instruction encoding functions \ingroup pio_instructions +/*! \brief Enumeration of values to pass for source/destination args for instruction encoding functions + * \ingroup pio_instructions * - * \note Not all values are suitable for all functions. Validity is only checked - * in debug mode when `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` is 1 + * \note Not all values are suitable for all functions. Validity is only checked in debug mode when + * `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` is 1 */ enum pio_src_dest { pio_pins = 0u, pio_x = 1u, pio_y = 2u, pio_null = 3u | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, - pio_pindirs = - 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, - pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | - _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, - pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | - _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, - pio_pc = - 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, + pio_pindirs = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, + pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, + pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, + pio_pc = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, pio_isr = 6u | _PIO_INVALID_SET_DEST, pio_osr = 7u | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST, - pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | - _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, + pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, }; -static inline uint _pio_major_instr_bits(uint instr) { return instr & 0xe000u; } +static inline uint _pio_major_instr_bits(uint instr) { + return instr & 0xe000u; +} -static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, - uint arg1, uint arg2) { +static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) { valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7); #if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS) uint32_t major = _pio_major_instr_bits(instr_bits); @@ -99,21 +92,17 @@ static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu); } -static inline uint -_pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, - enum pio_src_dest dest, uint value) { +static inline uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) { return _pio_encode_instr_and_args(instr_bits, dest & 7u, value); } /*! \brief Encode just the delay slot bits of an instruction * \ingroup pio_instructions * - * \note This function does not return a valid instruction encoding; instead it - * returns an encoding of the delay slot suitable for `OR`ing with the result of - * an encoding function for an actual instruction. Care should be taken when - * combining the results of this function with the results of \ref - * pio_encode_sideset and \ref pio_encode_sideset_opt as they share the same - * bits within the instruction encoding. + * \note This function does not return a valid instruction encoding; instead it returns an encoding of the delay + * slot suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when + * combining the results of this function with the results of \ref pio_encode_sideset and \ref pio_encode_sideset_opt + * as they share the same bits within the instruction encoding. * * \param cycles the number of cycles 0-31 (or less if side set is being used) * \return the delay slot bits to be ORed with an instruction encoding @@ -124,42 +113,38 @@ static inline uint pio_encode_delay(uint cycles) { return cycles << 8u; } -/*! \brief Encode just the side set bits of an instruction (in non optional side - * set mode) \ingroup pio_instructions +/*! \brief Encode just the side set bits of an instruction (in non optional side set mode) + * \ingroup pio_instructions * - * \note This function does not return a valid instruction encoding; instead it - * returns an encoding of the side set bits suitable for `OR`ing with the result - * of an encoding function for an actual instruction. Care should be taken when - * combining the results of this function with the results of \ref - * pio_encode_delay as they share the same bits within the instruction encoding. + * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits + * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when + * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits + * within the instruction encoding. * - * \param sideset_bit_count number of side set bits as would be specified via - * `.sideset` in pioasm \param value the value to sideset on the pins \return - * the side set bits to be ORed with an instruction encoding + * \param sideset_bit_count number of side set bits as would be specified via `.sideset` in pioasm + * \param value the value to sideset on the pins + * \return the side set bits to be ORed with an instruction encoding */ static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) { - valid_params_if(PIO_INSTRUCTIONS, - sideset_bit_count >= 1 && sideset_bit_count <= 5); + valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5); valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1)); return value << (13u - sideset_bit_count); } -/*! \brief Encode just the side set bits of an instruction (in optional -`opt` - * side set mode) \ingroup pio_instructions +/*! \brief Encode just the side set bits of an instruction (in optional -`opt` side set mode) + * \ingroup pio_instructions * - * \note This function does not return a valid instruction encoding; instead it - * returns an encoding of the side set bits suitable for `OR`ing with the result - * of an encoding function for an actual instruction. Care should be taken when - * combining the results of this function with the results of \ref - * pio_encode_delay as they share the same bits within the instruction encoding. + * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits + * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when + * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits + * within the instruction encoding. * - * \param sideset_bit_count number of side set bits as would be specified via - * `.sideset opt` in pioasm \param value the value to sideset on the pins + * \param sideset_bit_count number of side set bits as would be specified via `.sideset opt` in pioasm + * \param value the value to sideset on the pins * \return the side set bits to be ORed with an instruction encoding */ static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) { - valid_params_if(PIO_INSTRUCTIONS, - sideset_bit_count >= 1 && sideset_bit_count <= 4); + valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 4); valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1)); return 0x1000u | value << (12u - sideset_bit_count); } @@ -169,9 +154,9 @@ static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) { * * This is the equivalent of `JMP ` * - * \param addr The target address 0-31 (an absolute address within the PIO - * instruction memory) \return The instruction encoding with 0 delay and no side - * set value \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_jmp(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr); @@ -182,22 +167,22 @@ static inline uint pio_encode_jmp(uint addr) { * * This is the equivalent of `JMP !X ` * - * \param addr The target address 0-31 (an absolute address within the PIO - * instruction memory) \return The instruction encoding with 0 delay and no side - * set value \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_jmp_not_x(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 1, addr); } -/*! \brief Encode a conditional JMP if scratch X non-zero (and post-decrement X) - * instruction \ingroup pio_instructions +/*! \brief Encode a conditional JMP if scratch X non-zero (and post-decrement X) instruction + * \ingroup pio_instructions * * This is the equivalent of `JMP X-- ` * - * \param addr The target address 0-31 (an absolute address within the PIO - * instruction memory) \return The instruction encoding with 0 delay and no side - * set value \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_jmp_x_dec(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 2, addr); @@ -208,22 +193,22 @@ static inline uint pio_encode_jmp_x_dec(uint addr) { * * This is the equivalent of `JMP !Y ` * - * \param addr The target address 0-31 (an absolute address within the PIO - * instruction memory) \return The instruction encoding with 0 delay and no side - * set value \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_jmp_not_y(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 3, addr); } -/*! \brief Encode a conditional JMP if scratch Y non-zero (and post-decrement Y) - * instruction \ingroup pio_instructions +/*! \brief Encode a conditional JMP if scratch Y non-zero (and post-decrement Y) instruction + * \ingroup pio_instructions * * This is the equivalent of `JMP Y-- ` * - * \param addr The target address 0-31 (an absolute address within the PIO - * instruction memory) \return The instruction encoding with 0 delay and no side - * set value \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_jmp_y_dec(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 4, addr); @@ -234,9 +219,9 @@ static inline uint pio_encode_jmp_y_dec(uint addr) { * * This is the equivalent of `JMP X!=Y ` * - * \param addr The target address 0-31 (an absolute address within the PIO - * instruction memory) \return The instruction encoding with 0 delay and no side - * set value \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_jmp_x_ne_y(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 5, addr); @@ -247,22 +232,22 @@ static inline uint pio_encode_jmp_x_ne_y(uint addr) { * * This is the equivalent of `JMP PIN ` * - * \param addr The target address 0-31 (an absolute address within the PIO - * instruction memory) \return The instruction encoding with 0 delay and no side - * set value \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_jmp_pin(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 6, addr); } -/*! \brief Encode a conditional JMP if output shift register not empty - * instruction \ingroup pio_instructions +/*! \brief Encode a conditional JMP if output shift register not empty instruction + * \ingroup pio_instructions * * This is the equivalent of `JMP !OSRE ` * - * \param addr The target address 0-31 (an absolute address within the PIO - * instruction memory) \return The instruction encoding with 0 delay and no side - * set value \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt + * \param addr The target address 0-31 (an absolute address within the PIO instruction memory) + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_jmp_not_osre(uint addr) { return _pio_encode_instr_and_args(pio_instr_bits_jmp, 7, addr); @@ -284,8 +269,7 @@ static inline uint _pio_encode_irq(bool relative, uint irq) { * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) { - return _pio_encode_instr_and_args(pio_instr_bits_wait, - 0u | (polarity ? 4u : 0u), gpio); + return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), gpio); } /*! \brief Encode a WAIT for pin instruction @@ -294,13 +278,12 @@ static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) { * This is the equivalent of `WAIT PIN ` * * \param polarity true for `WAIT 1`, false for `WAIT 0` - * \param pin The pin number 0-31 relative to the executing SM's input pin - * mapping \return The instruction encoding with 0 delay and no side set value + * \param pin The pin number 0-31 relative to the executing SM's input pin mapping + * \return The instruction encoding with 0 delay and no side set value * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_wait_pin(bool polarity, uint pin) { - return _pio_encode_instr_and_args(pio_instr_bits_wait, - 1u | (polarity ? 4u : 0u), pin); + return _pio_encode_instr_and_args(pio_instr_bits_wait, 1u | (polarity ? 4u : 0u), pin); } /*! \brief Encode a WAIT for IRQ instruction @@ -309,16 +292,14 @@ static inline uint pio_encode_wait_pin(bool polarity, uint pin) { * This is the equivalent of `WAIT IRQ ` * * \param polarity true for `WAIT 1`, false for `WAIT 0` - * \param relative true for a `WAIT IRQ REL`, false for regular `WAIT IRQ - * ` \param irq the irq number 0-7 \return The instruction encoding with 0 - * delay and no side set value \see pio_encode_delay, pio_encode_sideset, - * pio_encode_sideset_opt + * \param relative true for a `WAIT IRQ REL`, false for regular `WAIT IRQ ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) { valid_params_if(PIO_INSTRUCTIONS, irq <= 7); - return _pio_encode_instr_and_args(pio_instr_bits_wait, - 2u | (polarity ? 4u : 0u), - _pio_encode_irq(relative, irq)); + return _pio_encode_instr_and_args(pio_instr_bits_wait, 2u | (polarity ? 4u : 0u), _pio_encode_irq(relative, irq)); } /*! \brief Encode an IN instruction @@ -362,8 +343,7 @@ static inline uint pio_encode_out(enum pio_src_dest dest, uint count) { * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_push(bool if_full, bool block) { - return _pio_encode_instr_and_args( - pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0); + return _pio_encode_instr_and_args(pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0); } /*! \brief Encode a PULL instruction @@ -377,8 +357,7 @@ static inline uint pio_encode_push(bool if_full, bool block) { * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_pull(bool if_empty, bool block) { - return _pio_encode_instr_and_args( - pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0); + return _pio_encode_instr_and_args(pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0); } /*! \brief Encode a MOV instruction @@ -391,8 +370,7 @@ static inline uint pio_encode_pull(bool if_empty, bool block) { * \return The instruction encoding with 0 delay and no side set value * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ -static inline uint pio_encode_mov(enum pio_src_dest dest, - enum pio_src_dest src) { +static inline uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, src & 7u); @@ -408,12 +386,10 @@ static inline uint pio_encode_mov(enum pio_src_dest dest, * \return The instruction encoding with 0 delay and no side set value * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ -static inline uint pio_encode_mov_not(enum pio_src_dest dest, - enum pio_src_dest src) { +static inline uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, - (1u << 3u) | (src & 7u)); + return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (1u << 3u) | (src & 7u)); } /*! \brief Encode a MOV instruction with bit reverse @@ -426,12 +402,10 @@ static inline uint pio_encode_mov_not(enum pio_src_dest dest, * \return The instruction encoding with 0 delay and no side set value * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ -static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, - enum pio_src_dest src) { +static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) { valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST)); valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC)); - return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, - (2u << 3u) | (src & 7u)); + return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (2u << 3u) | (src & 7u)); } /*! \brief Encode a IRQ SET instruction @@ -439,14 +413,13 @@ static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, * * This is the equivalent of `IRQ SET ` * - * \param relative true for a `IRQ SET REL`, false for regular `IRQ SET - * ` \param irq the irq number 0-7 \return The instruction encoding with 0 - * delay and no side set value \see pio_encode_delay, pio_encode_sideset, - * pio_encode_sideset_opt + * \param relative true for a `IRQ SET REL`, false for regular `IRQ SET ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_irq_set(bool relative, uint irq) { - return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, - _pio_encode_irq(relative, irq)); + return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, _pio_encode_irq(relative, irq)); } /*! \brief Encode a IRQ WAIT instruction @@ -454,14 +427,13 @@ static inline uint pio_encode_irq_set(bool relative, uint irq) { * * This is the equivalent of `IRQ WAIT ` * - * \param relative true for a `IRQ WAIT REL`, false for regular `IRQ WAIT - * ` \param irq the irq number 0-7 \return The instruction encoding with 0 - * delay and no side set value \see pio_encode_delay, pio_encode_sideset, - * pio_encode_sideset_opt + * \param relative true for a `IRQ WAIT REL`, false for regular `IRQ WAIT ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_irq_wait(bool relative, uint irq) { - return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, - _pio_encode_irq(relative, irq)); + return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, _pio_encode_irq(relative, irq)); } /*! \brief Encode a IRQ CLEAR instruction @@ -469,14 +441,13 @@ static inline uint pio_encode_irq_wait(bool relative, uint irq) { * * This is the equivalent of `IRQ CLEAR ` * - * \param relative true for a `IRQ CLEAR REL`, false for regular `IRQ - * CLEAR ` \param irq the irq number 0-7 \return The instruction encoding - * with 0 delay and no side set value \see pio_encode_delay, pio_encode_sideset, - * pio_encode_sideset_opt + * \param relative true for a `IRQ CLEAR REL`, false for regular `IRQ CLEAR ` + * \param irq the irq number 0-7 + * \return The instruction encoding with 0 delay and no side set value + * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ static inline uint pio_encode_irq_clear(bool relative, uint irq) { - return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, - _pio_encode_irq(relative, irq)); + return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, _pio_encode_irq(relative, irq)); } /*! \brief Encode a SET instruction @@ -502,7 +473,9 @@ static inline uint pio_encode_set(enum pio_src_dest dest, uint value) { * \return The instruction encoding with 0 delay and no side set value * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt */ -static inline uint pio_encode_nop(void) { return pio_encode_mov(pio_y, pio_y); } +static inline uint pio_encode_nop(void) { + return pio_encode_mov(pio_y, pio_y); +} #ifdef __cplusplus } diff --git a/src/piolib/include/hardware/regs/proc_pio.h b/src/piolib/include/hardware/regs/proc_pio.h index 9c4cb63..382cef6 100644 --- a/src/piolib/include/hardware/regs/proc_pio.h +++ b/src/piolib/include/hardware/regs/proc_pio.h @@ -15,113 +15,113 @@ // Register : PROC_PIO_CTRL // Description : PIO control register #define PROC_PIO_CTRL_OFFSET _u(0x00000000) -#define PROC_PIO_CTRL_BITS _u(0x00000fff) -#define PROC_PIO_CTRL_RESET _u(0x00000000) -#define PROC_PIO_CTRL_WIDTH _u(32) +#define PROC_PIO_CTRL_BITS _u(0x00000fff) +#define PROC_PIO_CTRL_RESET _u(0x00000000) +#define PROC_PIO_CTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_CTRL_CLKDIV_RESTART // Description : Force clock dividers to restart their count and clear // fractional // accumulators. Restart multiple dividers to synchronise them. -#define PROC_PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0) -#define PROC_PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00) -#define PROC_PIO_CTRL_CLKDIV_RESTART_MSB _u(11) -#define PROC_PIO_CTRL_CLKDIV_RESTART_LSB _u(8) +#define PROC_PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0) +#define PROC_PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00) +#define PROC_PIO_CTRL_CLKDIV_RESTART_MSB _u(11) +#define PROC_PIO_CTRL_CLKDIV_RESTART_LSB _u(8) #define PROC_PIO_CTRL_CLKDIV_RESTART_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PROC_PIO_CTRL_SM_RESTART // Description : Clear internal SM state which is otherwise difficult to access // (e.g. shift counters). Self-clearing. -#define PROC_PIO_CTRL_SM_RESTART_RESET _u(0x0) -#define PROC_PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) -#define PROC_PIO_CTRL_SM_RESTART_MSB _u(7) -#define PROC_PIO_CTRL_SM_RESTART_LSB _u(4) +#define PROC_PIO_CTRL_SM_RESTART_RESET _u(0x0) +#define PROC_PIO_CTRL_SM_RESTART_BITS _u(0x000000f0) +#define PROC_PIO_CTRL_SM_RESTART_MSB _u(7) +#define PROC_PIO_CTRL_SM_RESTART_LSB _u(4) #define PROC_PIO_CTRL_SM_RESTART_ACCESS "SC" // ----------------------------------------------------------------------------- // Field : PROC_PIO_CTRL_SM_ENABLE // Description : Enable state machine -#define PROC_PIO_CTRL_SM_ENABLE_RESET _u(0x0) -#define PROC_PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f) -#define PROC_PIO_CTRL_SM_ENABLE_MSB _u(3) -#define PROC_PIO_CTRL_SM_ENABLE_LSB _u(0) +#define PROC_PIO_CTRL_SM_ENABLE_RESET _u(0x0) +#define PROC_PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f) +#define PROC_PIO_CTRL_SM_ENABLE_MSB _u(3) +#define PROC_PIO_CTRL_SM_ENABLE_LSB _u(0) #define PROC_PIO_CTRL_SM_ENABLE_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_FSTAT // Description : FIFO status register #define PROC_PIO_FSTAT_OFFSET _u(0x00000004) -#define PROC_PIO_FSTAT_BITS _u(0x0f0f0f0f) -#define PROC_PIO_FSTAT_RESET _u(0x0f000f00) -#define PROC_PIO_FSTAT_WIDTH _u(32) +#define PROC_PIO_FSTAT_BITS _u(0x0f0f0f0f) +#define PROC_PIO_FSTAT_RESET _u(0x0f000f00) +#define PROC_PIO_FSTAT_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_FSTAT_TXEMPTY // Description : State machine TX FIFO is empty -#define PROC_PIO_FSTAT_TXEMPTY_RESET _u(0xf) -#define PROC_PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000) -#define PROC_PIO_FSTAT_TXEMPTY_MSB _u(27) -#define PROC_PIO_FSTAT_TXEMPTY_LSB _u(24) +#define PROC_PIO_FSTAT_TXEMPTY_RESET _u(0xf) +#define PROC_PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000) +#define PROC_PIO_FSTAT_TXEMPTY_MSB _u(27) +#define PROC_PIO_FSTAT_TXEMPTY_LSB _u(24) #define PROC_PIO_FSTAT_TXEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FSTAT_TXFULL // Description : State machine TX FIFO is full -#define PROC_PIO_FSTAT_TXFULL_RESET _u(0x0) -#define PROC_PIO_FSTAT_TXFULL_BITS _u(0x000f0000) -#define PROC_PIO_FSTAT_TXFULL_MSB _u(19) -#define PROC_PIO_FSTAT_TXFULL_LSB _u(16) +#define PROC_PIO_FSTAT_TXFULL_RESET _u(0x0) +#define PROC_PIO_FSTAT_TXFULL_BITS _u(0x000f0000) +#define PROC_PIO_FSTAT_TXFULL_MSB _u(19) +#define PROC_PIO_FSTAT_TXFULL_LSB _u(16) #define PROC_PIO_FSTAT_TXFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FSTAT_RXEMPTY // Description : State machine RX FIFO is empty -#define PROC_PIO_FSTAT_RXEMPTY_RESET _u(0xf) -#define PROC_PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00) -#define PROC_PIO_FSTAT_RXEMPTY_MSB _u(11) -#define PROC_PIO_FSTAT_RXEMPTY_LSB _u(8) +#define PROC_PIO_FSTAT_RXEMPTY_RESET _u(0xf) +#define PROC_PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00) +#define PROC_PIO_FSTAT_RXEMPTY_MSB _u(11) +#define PROC_PIO_FSTAT_RXEMPTY_LSB _u(8) #define PROC_PIO_FSTAT_RXEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FSTAT_RXFULL // Description : State machine RX FIFO is full -#define PROC_PIO_FSTAT_RXFULL_RESET _u(0x0) -#define PROC_PIO_FSTAT_RXFULL_BITS _u(0x0000000f) -#define PROC_PIO_FSTAT_RXFULL_MSB _u(3) -#define PROC_PIO_FSTAT_RXFULL_LSB _u(0) +#define PROC_PIO_FSTAT_RXFULL_RESET _u(0x0) +#define PROC_PIO_FSTAT_RXFULL_BITS _u(0x0000000f) +#define PROC_PIO_FSTAT_RXFULL_MSB _u(3) +#define PROC_PIO_FSTAT_RXFULL_LSB _u(0) #define PROC_PIO_FSTAT_RXFULL_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_FDEBUG // Description : FIFO debug register #define PROC_PIO_FDEBUG_OFFSET _u(0x00000008) -#define PROC_PIO_FDEBUG_BITS _u(0x0f0f0f0f) -#define PROC_PIO_FDEBUG_RESET _u(0x00000000) -#define PROC_PIO_FDEBUG_WIDTH _u(32) +#define PROC_PIO_FDEBUG_BITS _u(0x0f0f0f0f) +#define PROC_PIO_FDEBUG_RESET _u(0x00000000) +#define PROC_PIO_FDEBUG_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_FDEBUG_TXSTALL // Description : State machine has stalled on empty TX FIFO. Write 1 to clear. -#define PROC_PIO_FDEBUG_TXSTALL_RESET _u(0x0) -#define PROC_PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000) -#define PROC_PIO_FDEBUG_TXSTALL_MSB _u(27) -#define PROC_PIO_FDEBUG_TXSTALL_LSB _u(24) +#define PROC_PIO_FDEBUG_TXSTALL_RESET _u(0x0) +#define PROC_PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000) +#define PROC_PIO_FDEBUG_TXSTALL_MSB _u(27) +#define PROC_PIO_FDEBUG_TXSTALL_LSB _u(24) #define PROC_PIO_FDEBUG_TXSTALL_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FDEBUG_TXOVER // Description : TX FIFO overflow has occurred. Write 1 to clear. -#define PROC_PIO_FDEBUG_TXOVER_RESET _u(0x0) -#define PROC_PIO_FDEBUG_TXOVER_BITS _u(0x000f0000) -#define PROC_PIO_FDEBUG_TXOVER_MSB _u(19) -#define PROC_PIO_FDEBUG_TXOVER_LSB _u(16) +#define PROC_PIO_FDEBUG_TXOVER_RESET _u(0x0) +#define PROC_PIO_FDEBUG_TXOVER_BITS _u(0x000f0000) +#define PROC_PIO_FDEBUG_TXOVER_MSB _u(19) +#define PROC_PIO_FDEBUG_TXOVER_LSB _u(16) #define PROC_PIO_FDEBUG_TXOVER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FDEBUG_RXUNDER // Description : RX FIFO underflow has occurred. Write 1 to clear. -#define PROC_PIO_FDEBUG_RXUNDER_RESET _u(0x0) -#define PROC_PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00) -#define PROC_PIO_FDEBUG_RXUNDER_MSB _u(11) -#define PROC_PIO_FDEBUG_RXUNDER_LSB _u(8) +#define PROC_PIO_FDEBUG_RXUNDER_RESET _u(0x0) +#define PROC_PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00) +#define PROC_PIO_FDEBUG_RXUNDER_MSB _u(11) +#define PROC_PIO_FDEBUG_RXUNDER_LSB _u(8) #define PROC_PIO_FDEBUG_RXUNDER_ACCESS "WC" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FDEBUG_RXSTALL // Description : State machine has stalled on full RX FIFO. Write 1 to clear. -#define PROC_PIO_FDEBUG_RXSTALL_RESET _u(0x0) -#define PROC_PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f) -#define PROC_PIO_FDEBUG_RXSTALL_MSB _u(3) -#define PROC_PIO_FDEBUG_RXSTALL_LSB _u(0) +#define PROC_PIO_FDEBUG_RXSTALL_RESET _u(0x0) +#define PROC_PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f) +#define PROC_PIO_FDEBUG_RXSTALL_MSB _u(3) +#define PROC_PIO_FDEBUG_RXSTALL_LSB _u(0) #define PROC_PIO_FDEBUG_RXSTALL_ACCESS "WC" // ============================================================================= // Register : PROC_PIO_FLEVEL @@ -129,72 +129,72 @@ // These count up to 15 only. When counting higher the extra bit // is set in flevel2 register and this value saturates #define PROC_PIO_FLEVEL_OFFSET _u(0x0000000c) -#define PROC_PIO_FLEVEL_BITS _u(0xffffffff) -#define PROC_PIO_FLEVEL_RESET _u(0x00000000) -#define PROC_PIO_FLEVEL_WIDTH _u(32) +#define PROC_PIO_FLEVEL_BITS _u(0xffffffff) +#define PROC_PIO_FLEVEL_RESET _u(0x00000000) +#define PROC_PIO_FLEVEL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL_RX3 // Description : None -#define PROC_PIO_FLEVEL_RX3_RESET _u(0x0) -#define PROC_PIO_FLEVEL_RX3_BITS _u(0xf0000000) -#define PROC_PIO_FLEVEL_RX3_MSB _u(31) -#define PROC_PIO_FLEVEL_RX3_LSB _u(28) +#define PROC_PIO_FLEVEL_RX3_RESET _u(0x0) +#define PROC_PIO_FLEVEL_RX3_BITS _u(0xf0000000) +#define PROC_PIO_FLEVEL_RX3_MSB _u(31) +#define PROC_PIO_FLEVEL_RX3_LSB _u(28) #define PROC_PIO_FLEVEL_RX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL_TX3 // Description : None -#define PROC_PIO_FLEVEL_TX3_RESET _u(0x0) -#define PROC_PIO_FLEVEL_TX3_BITS _u(0x0f000000) -#define PROC_PIO_FLEVEL_TX3_MSB _u(27) -#define PROC_PIO_FLEVEL_TX3_LSB _u(24) +#define PROC_PIO_FLEVEL_TX3_RESET _u(0x0) +#define PROC_PIO_FLEVEL_TX3_BITS _u(0x0f000000) +#define PROC_PIO_FLEVEL_TX3_MSB _u(27) +#define PROC_PIO_FLEVEL_TX3_LSB _u(24) #define PROC_PIO_FLEVEL_TX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL_RX2 // Description : None -#define PROC_PIO_FLEVEL_RX2_RESET _u(0x0) -#define PROC_PIO_FLEVEL_RX2_BITS _u(0x00f00000) -#define PROC_PIO_FLEVEL_RX2_MSB _u(23) -#define PROC_PIO_FLEVEL_RX2_LSB _u(20) +#define PROC_PIO_FLEVEL_RX2_RESET _u(0x0) +#define PROC_PIO_FLEVEL_RX2_BITS _u(0x00f00000) +#define PROC_PIO_FLEVEL_RX2_MSB _u(23) +#define PROC_PIO_FLEVEL_RX2_LSB _u(20) #define PROC_PIO_FLEVEL_RX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL_TX2 // Description : None -#define PROC_PIO_FLEVEL_TX2_RESET _u(0x0) -#define PROC_PIO_FLEVEL_TX2_BITS _u(0x000f0000) -#define PROC_PIO_FLEVEL_TX2_MSB _u(19) -#define PROC_PIO_FLEVEL_TX2_LSB _u(16) +#define PROC_PIO_FLEVEL_TX2_RESET _u(0x0) +#define PROC_PIO_FLEVEL_TX2_BITS _u(0x000f0000) +#define PROC_PIO_FLEVEL_TX2_MSB _u(19) +#define PROC_PIO_FLEVEL_TX2_LSB _u(16) #define PROC_PIO_FLEVEL_TX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL_RX1 // Description : None -#define PROC_PIO_FLEVEL_RX1_RESET _u(0x0) -#define PROC_PIO_FLEVEL_RX1_BITS _u(0x0000f000) -#define PROC_PIO_FLEVEL_RX1_MSB _u(15) -#define PROC_PIO_FLEVEL_RX1_LSB _u(12) +#define PROC_PIO_FLEVEL_RX1_RESET _u(0x0) +#define PROC_PIO_FLEVEL_RX1_BITS _u(0x0000f000) +#define PROC_PIO_FLEVEL_RX1_MSB _u(15) +#define PROC_PIO_FLEVEL_RX1_LSB _u(12) #define PROC_PIO_FLEVEL_RX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL_TX1 // Description : None -#define PROC_PIO_FLEVEL_TX1_RESET _u(0x0) -#define PROC_PIO_FLEVEL_TX1_BITS _u(0x00000f00) -#define PROC_PIO_FLEVEL_TX1_MSB _u(11) -#define PROC_PIO_FLEVEL_TX1_LSB _u(8) +#define PROC_PIO_FLEVEL_TX1_RESET _u(0x0) +#define PROC_PIO_FLEVEL_TX1_BITS _u(0x00000f00) +#define PROC_PIO_FLEVEL_TX1_MSB _u(11) +#define PROC_PIO_FLEVEL_TX1_LSB _u(8) #define PROC_PIO_FLEVEL_TX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL_RX0 // Description : None -#define PROC_PIO_FLEVEL_RX0_RESET _u(0x0) -#define PROC_PIO_FLEVEL_RX0_BITS _u(0x000000f0) -#define PROC_PIO_FLEVEL_RX0_MSB _u(7) -#define PROC_PIO_FLEVEL_RX0_LSB _u(4) +#define PROC_PIO_FLEVEL_RX0_RESET _u(0x0) +#define PROC_PIO_FLEVEL_RX0_BITS _u(0x000000f0) +#define PROC_PIO_FLEVEL_RX0_MSB _u(7) +#define PROC_PIO_FLEVEL_RX0_LSB _u(4) #define PROC_PIO_FLEVEL_RX0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL_TX0 // Description : None -#define PROC_PIO_FLEVEL_TX0_RESET _u(0x0) -#define PROC_PIO_FLEVEL_TX0_BITS _u(0x0000000f) -#define PROC_PIO_FLEVEL_TX0_MSB _u(3) -#define PROC_PIO_FLEVEL_TX0_LSB _u(0) +#define PROC_PIO_FLEVEL_TX0_RESET _u(0x0) +#define PROC_PIO_FLEVEL_TX0_BITS _u(0x0000000f) +#define PROC_PIO_FLEVEL_TX0_MSB _u(3) +#define PROC_PIO_FLEVEL_TX0_LSB _u(0) #define PROC_PIO_FLEVEL_TX0_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_FLEVEL2 @@ -202,170 +202,170 @@ // These are only used in double fifo mode, and the fifo has more // than 15 elements #define PROC_PIO_FLEVEL2_OFFSET _u(0x00000010) -#define PROC_PIO_FLEVEL2_BITS _u(0x11111111) -#define PROC_PIO_FLEVEL2_RESET _u(0x00000000) -#define PROC_PIO_FLEVEL2_WIDTH _u(32) +#define PROC_PIO_FLEVEL2_BITS _u(0x11111111) +#define PROC_PIO_FLEVEL2_RESET _u(0x00000000) +#define PROC_PIO_FLEVEL2_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL2_RX3 // Description : None -#define PROC_PIO_FLEVEL2_RX3_RESET _u(0x0) -#define PROC_PIO_FLEVEL2_RX3_BITS _u(0x10000000) -#define PROC_PIO_FLEVEL2_RX3_MSB _u(28) -#define PROC_PIO_FLEVEL2_RX3_LSB _u(28) +#define PROC_PIO_FLEVEL2_RX3_RESET _u(0x0) +#define PROC_PIO_FLEVEL2_RX3_BITS _u(0x10000000) +#define PROC_PIO_FLEVEL2_RX3_MSB _u(28) +#define PROC_PIO_FLEVEL2_RX3_LSB _u(28) #define PROC_PIO_FLEVEL2_RX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL2_TX3 // Description : None -#define PROC_PIO_FLEVEL2_TX3_RESET _u(0x0) -#define PROC_PIO_FLEVEL2_TX3_BITS _u(0x01000000) -#define PROC_PIO_FLEVEL2_TX3_MSB _u(24) -#define PROC_PIO_FLEVEL2_TX3_LSB _u(24) +#define PROC_PIO_FLEVEL2_TX3_RESET _u(0x0) +#define PROC_PIO_FLEVEL2_TX3_BITS _u(0x01000000) +#define PROC_PIO_FLEVEL2_TX3_MSB _u(24) +#define PROC_PIO_FLEVEL2_TX3_LSB _u(24) #define PROC_PIO_FLEVEL2_TX3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL2_RX2 // Description : None -#define PROC_PIO_FLEVEL2_RX2_RESET _u(0x0) -#define PROC_PIO_FLEVEL2_RX2_BITS _u(0x00100000) -#define PROC_PIO_FLEVEL2_RX2_MSB _u(20) -#define PROC_PIO_FLEVEL2_RX2_LSB _u(20) +#define PROC_PIO_FLEVEL2_RX2_RESET _u(0x0) +#define PROC_PIO_FLEVEL2_RX2_BITS _u(0x00100000) +#define PROC_PIO_FLEVEL2_RX2_MSB _u(20) +#define PROC_PIO_FLEVEL2_RX2_LSB _u(20) #define PROC_PIO_FLEVEL2_RX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL2_TX2 // Description : None -#define PROC_PIO_FLEVEL2_TX2_RESET _u(0x0) -#define PROC_PIO_FLEVEL2_TX2_BITS _u(0x00010000) -#define PROC_PIO_FLEVEL2_TX2_MSB _u(16) -#define PROC_PIO_FLEVEL2_TX2_LSB _u(16) +#define PROC_PIO_FLEVEL2_TX2_RESET _u(0x0) +#define PROC_PIO_FLEVEL2_TX2_BITS _u(0x00010000) +#define PROC_PIO_FLEVEL2_TX2_MSB _u(16) +#define PROC_PIO_FLEVEL2_TX2_LSB _u(16) #define PROC_PIO_FLEVEL2_TX2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL2_RX1 // Description : None -#define PROC_PIO_FLEVEL2_RX1_RESET _u(0x0) -#define PROC_PIO_FLEVEL2_RX1_BITS _u(0x00001000) -#define PROC_PIO_FLEVEL2_RX1_MSB _u(12) -#define PROC_PIO_FLEVEL2_RX1_LSB _u(12) +#define PROC_PIO_FLEVEL2_RX1_RESET _u(0x0) +#define PROC_PIO_FLEVEL2_RX1_BITS _u(0x00001000) +#define PROC_PIO_FLEVEL2_RX1_MSB _u(12) +#define PROC_PIO_FLEVEL2_RX1_LSB _u(12) #define PROC_PIO_FLEVEL2_RX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL2_TX1 // Description : None -#define PROC_PIO_FLEVEL2_TX1_RESET _u(0x0) -#define PROC_PIO_FLEVEL2_TX1_BITS _u(0x00000100) -#define PROC_PIO_FLEVEL2_TX1_MSB _u(8) -#define PROC_PIO_FLEVEL2_TX1_LSB _u(8) +#define PROC_PIO_FLEVEL2_TX1_RESET _u(0x0) +#define PROC_PIO_FLEVEL2_TX1_BITS _u(0x00000100) +#define PROC_PIO_FLEVEL2_TX1_MSB _u(8) +#define PROC_PIO_FLEVEL2_TX1_LSB _u(8) #define PROC_PIO_FLEVEL2_TX1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL2_RX0 // Description : None -#define PROC_PIO_FLEVEL2_RX0_RESET _u(0x0) -#define PROC_PIO_FLEVEL2_RX0_BITS _u(0x00000010) -#define PROC_PIO_FLEVEL2_RX0_MSB _u(4) -#define PROC_PIO_FLEVEL2_RX0_LSB _u(4) +#define PROC_PIO_FLEVEL2_RX0_RESET _u(0x0) +#define PROC_PIO_FLEVEL2_RX0_BITS _u(0x00000010) +#define PROC_PIO_FLEVEL2_RX0_MSB _u(4) +#define PROC_PIO_FLEVEL2_RX0_LSB _u(4) #define PROC_PIO_FLEVEL2_RX0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_FLEVEL2_TX0 // Description : None -#define PROC_PIO_FLEVEL2_TX0_RESET _u(0x0) -#define PROC_PIO_FLEVEL2_TX0_BITS _u(0x00000001) -#define PROC_PIO_FLEVEL2_TX0_MSB _u(0) -#define PROC_PIO_FLEVEL2_TX0_LSB _u(0) +#define PROC_PIO_FLEVEL2_TX0_RESET _u(0x0) +#define PROC_PIO_FLEVEL2_TX0_BITS _u(0x00000001) +#define PROC_PIO_FLEVEL2_TX0_MSB _u(0) +#define PROC_PIO_FLEVEL2_TX0_LSB _u(0) #define PROC_PIO_FLEVEL2_TX0_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_TXF0 // Description : Direct write access to the TX FIFO for this state machine. Each // write pushes one word to the FIFO. #define PROC_PIO_TXF0_OFFSET _u(0x00000014) -#define PROC_PIO_TXF0_BITS _u(0xffffffff) -#define PROC_PIO_TXF0_RESET _u(0x00000000) -#define PROC_PIO_TXF0_WIDTH _u(32) -#define PROC_PIO_TXF0_MSB _u(31) -#define PROC_PIO_TXF0_LSB _u(0) +#define PROC_PIO_TXF0_BITS _u(0xffffffff) +#define PROC_PIO_TXF0_RESET _u(0x00000000) +#define PROC_PIO_TXF0_WIDTH _u(32) +#define PROC_PIO_TXF0_MSB _u(31) +#define PROC_PIO_TXF0_LSB _u(0) #define PROC_PIO_TXF0_ACCESS "WF" // ============================================================================= // Register : PROC_PIO_TXF1 // Description : Direct write access to the TX FIFO for this state machine. Each // write pushes one word to the FIFO. #define PROC_PIO_TXF1_OFFSET _u(0x00000018) -#define PROC_PIO_TXF1_BITS _u(0xffffffff) -#define PROC_PIO_TXF1_RESET _u(0x00000000) -#define PROC_PIO_TXF1_WIDTH _u(32) -#define PROC_PIO_TXF1_MSB _u(31) -#define PROC_PIO_TXF1_LSB _u(0) +#define PROC_PIO_TXF1_BITS _u(0xffffffff) +#define PROC_PIO_TXF1_RESET _u(0x00000000) +#define PROC_PIO_TXF1_WIDTH _u(32) +#define PROC_PIO_TXF1_MSB _u(31) +#define PROC_PIO_TXF1_LSB _u(0) #define PROC_PIO_TXF1_ACCESS "WF" // ============================================================================= // Register : PROC_PIO_TXF2 // Description : Direct write access to the TX FIFO for this state machine. Each // write pushes one word to the FIFO. #define PROC_PIO_TXF2_OFFSET _u(0x0000001c) -#define PROC_PIO_TXF2_BITS _u(0xffffffff) -#define PROC_PIO_TXF2_RESET _u(0x00000000) -#define PROC_PIO_TXF2_WIDTH _u(32) -#define PROC_PIO_TXF2_MSB _u(31) -#define PROC_PIO_TXF2_LSB _u(0) +#define PROC_PIO_TXF2_BITS _u(0xffffffff) +#define PROC_PIO_TXF2_RESET _u(0x00000000) +#define PROC_PIO_TXF2_WIDTH _u(32) +#define PROC_PIO_TXF2_MSB _u(31) +#define PROC_PIO_TXF2_LSB _u(0) #define PROC_PIO_TXF2_ACCESS "WF" // ============================================================================= // Register : PROC_PIO_TXF3 // Description : Direct write access to the TX FIFO for this state machine. Each // write pushes one word to the FIFO. #define PROC_PIO_TXF3_OFFSET _u(0x00000020) -#define PROC_PIO_TXF3_BITS _u(0xffffffff) -#define PROC_PIO_TXF3_RESET _u(0x00000000) -#define PROC_PIO_TXF3_WIDTH _u(32) -#define PROC_PIO_TXF3_MSB _u(31) -#define PROC_PIO_TXF3_LSB _u(0) +#define PROC_PIO_TXF3_BITS _u(0xffffffff) +#define PROC_PIO_TXF3_RESET _u(0x00000000) +#define PROC_PIO_TXF3_WIDTH _u(32) +#define PROC_PIO_TXF3_MSB _u(31) +#define PROC_PIO_TXF3_LSB _u(0) #define PROC_PIO_TXF3_ACCESS "WF" // ============================================================================= // Register : PROC_PIO_RXF0 // Description : Direct read access to the RX FIFO for this state machine. Each // read pops one word from the FIFO. #define PROC_PIO_RXF0_OFFSET _u(0x00000024) -#define PROC_PIO_RXF0_BITS _u(0xffffffff) -#define PROC_PIO_RXF0_RESET "-" -#define PROC_PIO_RXF0_WIDTH _u(32) -#define PROC_PIO_RXF0_MSB _u(31) -#define PROC_PIO_RXF0_LSB _u(0) +#define PROC_PIO_RXF0_BITS _u(0xffffffff) +#define PROC_PIO_RXF0_RESET "-" +#define PROC_PIO_RXF0_WIDTH _u(32) +#define PROC_PIO_RXF0_MSB _u(31) +#define PROC_PIO_RXF0_LSB _u(0) #define PROC_PIO_RXF0_ACCESS "RF" // ============================================================================= // Register : PROC_PIO_RXF1 // Description : Direct read access to the RX FIFO for this state machine. Each // read pops one word from the FIFO. #define PROC_PIO_RXF1_OFFSET _u(0x00000028) -#define PROC_PIO_RXF1_BITS _u(0xffffffff) -#define PROC_PIO_RXF1_RESET "-" -#define PROC_PIO_RXF1_WIDTH _u(32) -#define PROC_PIO_RXF1_MSB _u(31) -#define PROC_PIO_RXF1_LSB _u(0) +#define PROC_PIO_RXF1_BITS _u(0xffffffff) +#define PROC_PIO_RXF1_RESET "-" +#define PROC_PIO_RXF1_WIDTH _u(32) +#define PROC_PIO_RXF1_MSB _u(31) +#define PROC_PIO_RXF1_LSB _u(0) #define PROC_PIO_RXF1_ACCESS "RF" // ============================================================================= // Register : PROC_PIO_RXF2 // Description : Direct read access to the RX FIFO for this state machine. Each // read pops one word from the FIFO. #define PROC_PIO_RXF2_OFFSET _u(0x0000002c) -#define PROC_PIO_RXF2_BITS _u(0xffffffff) -#define PROC_PIO_RXF2_RESET "-" -#define PROC_PIO_RXF2_WIDTH _u(32) -#define PROC_PIO_RXF2_MSB _u(31) -#define PROC_PIO_RXF2_LSB _u(0) +#define PROC_PIO_RXF2_BITS _u(0xffffffff) +#define PROC_PIO_RXF2_RESET "-" +#define PROC_PIO_RXF2_WIDTH _u(32) +#define PROC_PIO_RXF2_MSB _u(31) +#define PROC_PIO_RXF2_LSB _u(0) #define PROC_PIO_RXF2_ACCESS "RF" // ============================================================================= // Register : PROC_PIO_RXF3 // Description : Direct read access to the RX FIFO for this state machine. Each // read pops one word from the FIFO. #define PROC_PIO_RXF3_OFFSET _u(0x00000030) -#define PROC_PIO_RXF3_BITS _u(0xffffffff) -#define PROC_PIO_RXF3_RESET "-" -#define PROC_PIO_RXF3_WIDTH _u(32) -#define PROC_PIO_RXF3_MSB _u(31) -#define PROC_PIO_RXF3_LSB _u(0) +#define PROC_PIO_RXF3_BITS _u(0xffffffff) +#define PROC_PIO_RXF3_RESET "-" +#define PROC_PIO_RXF3_WIDTH _u(32) +#define PROC_PIO_RXF3_MSB _u(31) +#define PROC_PIO_RXF3_LSB _u(0) #define PROC_PIO_RXF3_ACCESS "RF" // ============================================================================= // Register : PROC_PIO_IRQ // Description : Interrupt request register. Write 1 to clear #define PROC_PIO_IRQ_OFFSET _u(0x00000034) -#define PROC_PIO_IRQ_BITS _u(0x000000ff) -#define PROC_PIO_IRQ_RESET _u(0x00000000) -#define PROC_PIO_IRQ_WIDTH _u(32) -#define PROC_PIO_IRQ_MSB _u(7) -#define PROC_PIO_IRQ_LSB _u(0) +#define PROC_PIO_IRQ_BITS _u(0x000000ff) +#define PROC_PIO_IRQ_RESET _u(0x00000000) +#define PROC_PIO_IRQ_WIDTH _u(32) +#define PROC_PIO_IRQ_MSB _u(7) +#define PROC_PIO_IRQ_LSB _u(0) #define PROC_PIO_IRQ_ACCESS "WC" // ============================================================================= // Register : PROC_PIO_IRQ_FORCE @@ -377,11 +377,11 @@ // testing ISRs, // and is not visible to the state machines. #define PROC_PIO_IRQ_FORCE_OFFSET _u(0x00000038) -#define PROC_PIO_IRQ_FORCE_BITS _u(0x000000ff) -#define PROC_PIO_IRQ_FORCE_RESET _u(0x00000000) -#define PROC_PIO_IRQ_FORCE_WIDTH _u(32) -#define PROC_PIO_IRQ_FORCE_MSB _u(7) -#define PROC_PIO_IRQ_FORCE_LSB _u(0) +#define PROC_PIO_IRQ_FORCE_BITS _u(0x000000ff) +#define PROC_PIO_IRQ_FORCE_RESET _u(0x00000000) +#define PROC_PIO_IRQ_FORCE_WIDTH _u(32) +#define PROC_PIO_IRQ_FORCE_MSB _u(7) +#define PROC_PIO_IRQ_FORCE_LSB _u(0) #define PROC_PIO_IRQ_FORCE_ACCESS "WF" // ============================================================================= // Register : PROC_PIO_INPUT_SYNC_BYPASS @@ -396,33 +396,33 @@ // 1 -> synchronizer is bypassed // If in doubt, leave this register as all zeroes. #define PROC_PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x0000003c) -#define PROC_PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff) -#define PROC_PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000) -#define PROC_PIO_INPUT_SYNC_BYPASS_WIDTH _u(32) -#define PROC_PIO_INPUT_SYNC_BYPASS_MSB _u(31) -#define PROC_PIO_INPUT_SYNC_BYPASS_LSB _u(0) +#define PROC_PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff) +#define PROC_PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000) +#define PROC_PIO_INPUT_SYNC_BYPASS_WIDTH _u(32) +#define PROC_PIO_INPUT_SYNC_BYPASS_MSB _u(31) +#define PROC_PIO_INPUT_SYNC_BYPASS_LSB _u(0) #define PROC_PIO_INPUT_SYNC_BYPASS_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_DBG_PADOUT // Description : Read to sample the pad output values PIO is currently driving // to the GPIOs. #define PROC_PIO_DBG_PADOUT_OFFSET _u(0x00000040) -#define PROC_PIO_DBG_PADOUT_BITS _u(0xffffffff) -#define PROC_PIO_DBG_PADOUT_RESET _u(0x00000000) -#define PROC_PIO_DBG_PADOUT_WIDTH _u(32) -#define PROC_PIO_DBG_PADOUT_MSB _u(31) -#define PROC_PIO_DBG_PADOUT_LSB _u(0) +#define PROC_PIO_DBG_PADOUT_BITS _u(0xffffffff) +#define PROC_PIO_DBG_PADOUT_RESET _u(0x00000000) +#define PROC_PIO_DBG_PADOUT_WIDTH _u(32) +#define PROC_PIO_DBG_PADOUT_MSB _u(31) +#define PROC_PIO_DBG_PADOUT_LSB _u(0) #define PROC_PIO_DBG_PADOUT_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_DBG_PADOE // Description : Read to sample the pad output enables (direction) PIO is // currently driving to the GPIOs. #define PROC_PIO_DBG_PADOE_OFFSET _u(0x00000044) -#define PROC_PIO_DBG_PADOE_BITS _u(0xffffffff) -#define PROC_PIO_DBG_PADOE_RESET _u(0x00000000) -#define PROC_PIO_DBG_PADOE_WIDTH _u(32) -#define PROC_PIO_DBG_PADOE_MSB _u(31) -#define PROC_PIO_DBG_PADOE_LSB _u(0) +#define PROC_PIO_DBG_PADOE_BITS _u(0xffffffff) +#define PROC_PIO_DBG_PADOE_RESET _u(0x00000000) +#define PROC_PIO_DBG_PADOE_WIDTH _u(32) +#define PROC_PIO_DBG_PADOE_MSB _u(31) +#define PROC_PIO_DBG_PADOE_LSB _u(0) #define PROC_PIO_DBG_PADOE_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_DBG_CFGINFO @@ -431,398 +431,398 @@ // These should be provided in the chip datasheet, but are also // exposed here. #define PROC_PIO_DBG_CFGINFO_OFFSET _u(0x00000048) -#define PROC_PIO_DBG_CFGINFO_BITS _u(0x003f0f3f) -#define PROC_PIO_DBG_CFGINFO_RESET _u(0x00000000) -#define PROC_PIO_DBG_CFGINFO_WIDTH _u(32) +#define PROC_PIO_DBG_CFGINFO_BITS _u(0x003f0f3f) +#define PROC_PIO_DBG_CFGINFO_RESET _u(0x00000000) +#define PROC_PIO_DBG_CFGINFO_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_DBG_CFGINFO_IMEM_SIZE // Description : The size of the instruction memory, measured in units of one // instruction -#define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" -#define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000) -#define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21) -#define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16) +#define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-" +#define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000) +#define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21) +#define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16) #define PROC_PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_DBG_CFGINFO_SM_COUNT // Description : The number of state machines this PIO instance is equipped // with. -#define PROC_PIO_DBG_CFGINFO_SM_COUNT_RESET "-" -#define PROC_PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00) -#define PROC_PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11) -#define PROC_PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8) +#define PROC_PIO_DBG_CFGINFO_SM_COUNT_RESET "-" +#define PROC_PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00) +#define PROC_PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11) +#define PROC_PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8) #define PROC_PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_DBG_CFGINFO_FIFO_DEPTH // Description : The depth of the state machine TX/RX FIFOs, measured in words. // Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double // this depth. -#define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" -#define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f) -#define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5) -#define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0) +#define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-" +#define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f) +#define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5) +#define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0) #define PROC_PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM0 // Description : Write-only access to instruction memory location 0 #define PROC_PIO_INSTR_MEM0_OFFSET _u(0x0000004c) -#define PROC_PIO_INSTR_MEM0_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM0_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM0_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM0_MSB _u(15) -#define PROC_PIO_INSTR_MEM0_LSB _u(0) +#define PROC_PIO_INSTR_MEM0_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM0_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM0_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM0_MSB _u(15) +#define PROC_PIO_INSTR_MEM0_LSB _u(0) #define PROC_PIO_INSTR_MEM0_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM1 // Description : Write-only access to instruction memory location 1 #define PROC_PIO_INSTR_MEM1_OFFSET _u(0x00000050) -#define PROC_PIO_INSTR_MEM1_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM1_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM1_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM1_MSB _u(15) -#define PROC_PIO_INSTR_MEM1_LSB _u(0) +#define PROC_PIO_INSTR_MEM1_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM1_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM1_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM1_MSB _u(15) +#define PROC_PIO_INSTR_MEM1_LSB _u(0) #define PROC_PIO_INSTR_MEM1_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM2 // Description : Write-only access to instruction memory location 2 #define PROC_PIO_INSTR_MEM2_OFFSET _u(0x00000054) -#define PROC_PIO_INSTR_MEM2_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM2_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM2_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM2_MSB _u(15) -#define PROC_PIO_INSTR_MEM2_LSB _u(0) +#define PROC_PIO_INSTR_MEM2_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM2_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM2_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM2_MSB _u(15) +#define PROC_PIO_INSTR_MEM2_LSB _u(0) #define PROC_PIO_INSTR_MEM2_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM3 // Description : Write-only access to instruction memory location 3 #define PROC_PIO_INSTR_MEM3_OFFSET _u(0x00000058) -#define PROC_PIO_INSTR_MEM3_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM3_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM3_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM3_MSB _u(15) -#define PROC_PIO_INSTR_MEM3_LSB _u(0) +#define PROC_PIO_INSTR_MEM3_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM3_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM3_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM3_MSB _u(15) +#define PROC_PIO_INSTR_MEM3_LSB _u(0) #define PROC_PIO_INSTR_MEM3_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM4 // Description : Write-only access to instruction memory location 4 #define PROC_PIO_INSTR_MEM4_OFFSET _u(0x0000005c) -#define PROC_PIO_INSTR_MEM4_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM4_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM4_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM4_MSB _u(15) -#define PROC_PIO_INSTR_MEM4_LSB _u(0) +#define PROC_PIO_INSTR_MEM4_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM4_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM4_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM4_MSB _u(15) +#define PROC_PIO_INSTR_MEM4_LSB _u(0) #define PROC_PIO_INSTR_MEM4_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM5 // Description : Write-only access to instruction memory location 5 #define PROC_PIO_INSTR_MEM5_OFFSET _u(0x00000060) -#define PROC_PIO_INSTR_MEM5_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM5_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM5_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM5_MSB _u(15) -#define PROC_PIO_INSTR_MEM5_LSB _u(0) +#define PROC_PIO_INSTR_MEM5_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM5_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM5_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM5_MSB _u(15) +#define PROC_PIO_INSTR_MEM5_LSB _u(0) #define PROC_PIO_INSTR_MEM5_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM6 // Description : Write-only access to instruction memory location 6 #define PROC_PIO_INSTR_MEM6_OFFSET _u(0x00000064) -#define PROC_PIO_INSTR_MEM6_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM6_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM6_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM6_MSB _u(15) -#define PROC_PIO_INSTR_MEM6_LSB _u(0) +#define PROC_PIO_INSTR_MEM6_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM6_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM6_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM6_MSB _u(15) +#define PROC_PIO_INSTR_MEM6_LSB _u(0) #define PROC_PIO_INSTR_MEM6_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM7 // Description : Write-only access to instruction memory location 7 #define PROC_PIO_INSTR_MEM7_OFFSET _u(0x00000068) -#define PROC_PIO_INSTR_MEM7_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM7_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM7_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM7_MSB _u(15) -#define PROC_PIO_INSTR_MEM7_LSB _u(0) +#define PROC_PIO_INSTR_MEM7_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM7_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM7_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM7_MSB _u(15) +#define PROC_PIO_INSTR_MEM7_LSB _u(0) #define PROC_PIO_INSTR_MEM7_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM8 // Description : Write-only access to instruction memory location 8 #define PROC_PIO_INSTR_MEM8_OFFSET _u(0x0000006c) -#define PROC_PIO_INSTR_MEM8_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM8_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM8_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM8_MSB _u(15) -#define PROC_PIO_INSTR_MEM8_LSB _u(0) +#define PROC_PIO_INSTR_MEM8_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM8_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM8_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM8_MSB _u(15) +#define PROC_PIO_INSTR_MEM8_LSB _u(0) #define PROC_PIO_INSTR_MEM8_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM9 // Description : Write-only access to instruction memory location 9 #define PROC_PIO_INSTR_MEM9_OFFSET _u(0x00000070) -#define PROC_PIO_INSTR_MEM9_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM9_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM9_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM9_MSB _u(15) -#define PROC_PIO_INSTR_MEM9_LSB _u(0) +#define PROC_PIO_INSTR_MEM9_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM9_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM9_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM9_MSB _u(15) +#define PROC_PIO_INSTR_MEM9_LSB _u(0) #define PROC_PIO_INSTR_MEM9_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM10 // Description : Write-only access to instruction memory location 10 #define PROC_PIO_INSTR_MEM10_OFFSET _u(0x00000074) -#define PROC_PIO_INSTR_MEM10_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM10_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM10_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM10_MSB _u(15) -#define PROC_PIO_INSTR_MEM10_LSB _u(0) +#define PROC_PIO_INSTR_MEM10_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM10_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM10_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM10_MSB _u(15) +#define PROC_PIO_INSTR_MEM10_LSB _u(0) #define PROC_PIO_INSTR_MEM10_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM11 // Description : Write-only access to instruction memory location 11 #define PROC_PIO_INSTR_MEM11_OFFSET _u(0x00000078) -#define PROC_PIO_INSTR_MEM11_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM11_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM11_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM11_MSB _u(15) -#define PROC_PIO_INSTR_MEM11_LSB _u(0) +#define PROC_PIO_INSTR_MEM11_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM11_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM11_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM11_MSB _u(15) +#define PROC_PIO_INSTR_MEM11_LSB _u(0) #define PROC_PIO_INSTR_MEM11_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM12 // Description : Write-only access to instruction memory location 12 #define PROC_PIO_INSTR_MEM12_OFFSET _u(0x0000007c) -#define PROC_PIO_INSTR_MEM12_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM12_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM12_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM12_MSB _u(15) -#define PROC_PIO_INSTR_MEM12_LSB _u(0) +#define PROC_PIO_INSTR_MEM12_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM12_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM12_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM12_MSB _u(15) +#define PROC_PIO_INSTR_MEM12_LSB _u(0) #define PROC_PIO_INSTR_MEM12_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM13 // Description : Write-only access to instruction memory location 13 #define PROC_PIO_INSTR_MEM13_OFFSET _u(0x00000080) -#define PROC_PIO_INSTR_MEM13_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM13_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM13_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM13_MSB _u(15) -#define PROC_PIO_INSTR_MEM13_LSB _u(0) +#define PROC_PIO_INSTR_MEM13_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM13_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM13_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM13_MSB _u(15) +#define PROC_PIO_INSTR_MEM13_LSB _u(0) #define PROC_PIO_INSTR_MEM13_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM14 // Description : Write-only access to instruction memory location 14 #define PROC_PIO_INSTR_MEM14_OFFSET _u(0x00000084) -#define PROC_PIO_INSTR_MEM14_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM14_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM14_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM14_MSB _u(15) -#define PROC_PIO_INSTR_MEM14_LSB _u(0) +#define PROC_PIO_INSTR_MEM14_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM14_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM14_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM14_MSB _u(15) +#define PROC_PIO_INSTR_MEM14_LSB _u(0) #define PROC_PIO_INSTR_MEM14_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM15 // Description : Write-only access to instruction memory location 15 #define PROC_PIO_INSTR_MEM15_OFFSET _u(0x00000088) -#define PROC_PIO_INSTR_MEM15_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM15_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM15_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM15_MSB _u(15) -#define PROC_PIO_INSTR_MEM15_LSB _u(0) +#define PROC_PIO_INSTR_MEM15_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM15_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM15_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM15_MSB _u(15) +#define PROC_PIO_INSTR_MEM15_LSB _u(0) #define PROC_PIO_INSTR_MEM15_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM16 // Description : Write-only access to instruction memory location 16 #define PROC_PIO_INSTR_MEM16_OFFSET _u(0x0000008c) -#define PROC_PIO_INSTR_MEM16_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM16_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM16_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM16_MSB _u(15) -#define PROC_PIO_INSTR_MEM16_LSB _u(0) +#define PROC_PIO_INSTR_MEM16_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM16_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM16_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM16_MSB _u(15) +#define PROC_PIO_INSTR_MEM16_LSB _u(0) #define PROC_PIO_INSTR_MEM16_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM17 // Description : Write-only access to instruction memory location 17 #define PROC_PIO_INSTR_MEM17_OFFSET _u(0x00000090) -#define PROC_PIO_INSTR_MEM17_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM17_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM17_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM17_MSB _u(15) -#define PROC_PIO_INSTR_MEM17_LSB _u(0) +#define PROC_PIO_INSTR_MEM17_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM17_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM17_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM17_MSB _u(15) +#define PROC_PIO_INSTR_MEM17_LSB _u(0) #define PROC_PIO_INSTR_MEM17_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM18 // Description : Write-only access to instruction memory location 18 #define PROC_PIO_INSTR_MEM18_OFFSET _u(0x00000094) -#define PROC_PIO_INSTR_MEM18_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM18_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM18_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM18_MSB _u(15) -#define PROC_PIO_INSTR_MEM18_LSB _u(0) +#define PROC_PIO_INSTR_MEM18_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM18_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM18_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM18_MSB _u(15) +#define PROC_PIO_INSTR_MEM18_LSB _u(0) #define PROC_PIO_INSTR_MEM18_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM19 // Description : Write-only access to instruction memory location 19 #define PROC_PIO_INSTR_MEM19_OFFSET _u(0x00000098) -#define PROC_PIO_INSTR_MEM19_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM19_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM19_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM19_MSB _u(15) -#define PROC_PIO_INSTR_MEM19_LSB _u(0) +#define PROC_PIO_INSTR_MEM19_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM19_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM19_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM19_MSB _u(15) +#define PROC_PIO_INSTR_MEM19_LSB _u(0) #define PROC_PIO_INSTR_MEM19_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM20 // Description : Write-only access to instruction memory location 20 #define PROC_PIO_INSTR_MEM20_OFFSET _u(0x0000009c) -#define PROC_PIO_INSTR_MEM20_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM20_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM20_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM20_MSB _u(15) -#define PROC_PIO_INSTR_MEM20_LSB _u(0) +#define PROC_PIO_INSTR_MEM20_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM20_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM20_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM20_MSB _u(15) +#define PROC_PIO_INSTR_MEM20_LSB _u(0) #define PROC_PIO_INSTR_MEM20_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM21 // Description : Write-only access to instruction memory location 21 #define PROC_PIO_INSTR_MEM21_OFFSET _u(0x000000a0) -#define PROC_PIO_INSTR_MEM21_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM21_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM21_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM21_MSB _u(15) -#define PROC_PIO_INSTR_MEM21_LSB _u(0) +#define PROC_PIO_INSTR_MEM21_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM21_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM21_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM21_MSB _u(15) +#define PROC_PIO_INSTR_MEM21_LSB _u(0) #define PROC_PIO_INSTR_MEM21_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM22 // Description : Write-only access to instruction memory location 22 #define PROC_PIO_INSTR_MEM22_OFFSET _u(0x000000a4) -#define PROC_PIO_INSTR_MEM22_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM22_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM22_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM22_MSB _u(15) -#define PROC_PIO_INSTR_MEM22_LSB _u(0) +#define PROC_PIO_INSTR_MEM22_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM22_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM22_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM22_MSB _u(15) +#define PROC_PIO_INSTR_MEM22_LSB _u(0) #define PROC_PIO_INSTR_MEM22_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM23 // Description : Write-only access to instruction memory location 23 #define PROC_PIO_INSTR_MEM23_OFFSET _u(0x000000a8) -#define PROC_PIO_INSTR_MEM23_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM23_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM23_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM23_MSB _u(15) -#define PROC_PIO_INSTR_MEM23_LSB _u(0) +#define PROC_PIO_INSTR_MEM23_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM23_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM23_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM23_MSB _u(15) +#define PROC_PIO_INSTR_MEM23_LSB _u(0) #define PROC_PIO_INSTR_MEM23_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM24 // Description : Write-only access to instruction memory location 24 #define PROC_PIO_INSTR_MEM24_OFFSET _u(0x000000ac) -#define PROC_PIO_INSTR_MEM24_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM24_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM24_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM24_MSB _u(15) -#define PROC_PIO_INSTR_MEM24_LSB _u(0) +#define PROC_PIO_INSTR_MEM24_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM24_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM24_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM24_MSB _u(15) +#define PROC_PIO_INSTR_MEM24_LSB _u(0) #define PROC_PIO_INSTR_MEM24_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM25 // Description : Write-only access to instruction memory location 25 #define PROC_PIO_INSTR_MEM25_OFFSET _u(0x000000b0) -#define PROC_PIO_INSTR_MEM25_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM25_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM25_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM25_MSB _u(15) -#define PROC_PIO_INSTR_MEM25_LSB _u(0) +#define PROC_PIO_INSTR_MEM25_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM25_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM25_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM25_MSB _u(15) +#define PROC_PIO_INSTR_MEM25_LSB _u(0) #define PROC_PIO_INSTR_MEM25_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM26 // Description : Write-only access to instruction memory location 26 #define PROC_PIO_INSTR_MEM26_OFFSET _u(0x000000b4) -#define PROC_PIO_INSTR_MEM26_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM26_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM26_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM26_MSB _u(15) -#define PROC_PIO_INSTR_MEM26_LSB _u(0) +#define PROC_PIO_INSTR_MEM26_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM26_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM26_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM26_MSB _u(15) +#define PROC_PIO_INSTR_MEM26_LSB _u(0) #define PROC_PIO_INSTR_MEM26_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM27 // Description : Write-only access to instruction memory location 27 #define PROC_PIO_INSTR_MEM27_OFFSET _u(0x000000b8) -#define PROC_PIO_INSTR_MEM27_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM27_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM27_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM27_MSB _u(15) -#define PROC_PIO_INSTR_MEM27_LSB _u(0) +#define PROC_PIO_INSTR_MEM27_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM27_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM27_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM27_MSB _u(15) +#define PROC_PIO_INSTR_MEM27_LSB _u(0) #define PROC_PIO_INSTR_MEM27_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM28 // Description : Write-only access to instruction memory location 28 #define PROC_PIO_INSTR_MEM28_OFFSET _u(0x000000bc) -#define PROC_PIO_INSTR_MEM28_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM28_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM28_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM28_MSB _u(15) -#define PROC_PIO_INSTR_MEM28_LSB _u(0) +#define PROC_PIO_INSTR_MEM28_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM28_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM28_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM28_MSB _u(15) +#define PROC_PIO_INSTR_MEM28_LSB _u(0) #define PROC_PIO_INSTR_MEM28_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM29 // Description : Write-only access to instruction memory location 29 #define PROC_PIO_INSTR_MEM29_OFFSET _u(0x000000c0) -#define PROC_PIO_INSTR_MEM29_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM29_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM29_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM29_MSB _u(15) -#define PROC_PIO_INSTR_MEM29_LSB _u(0) +#define PROC_PIO_INSTR_MEM29_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM29_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM29_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM29_MSB _u(15) +#define PROC_PIO_INSTR_MEM29_LSB _u(0) #define PROC_PIO_INSTR_MEM29_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM30 // Description : Write-only access to instruction memory location 30 #define PROC_PIO_INSTR_MEM30_OFFSET _u(0x000000c4) -#define PROC_PIO_INSTR_MEM30_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM30_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM30_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM30_MSB _u(15) -#define PROC_PIO_INSTR_MEM30_LSB _u(0) +#define PROC_PIO_INSTR_MEM30_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM30_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM30_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM30_MSB _u(15) +#define PROC_PIO_INSTR_MEM30_LSB _u(0) #define PROC_PIO_INSTR_MEM30_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_INSTR_MEM31 // Description : Write-only access to instruction memory location 31 #define PROC_PIO_INSTR_MEM31_OFFSET _u(0x000000c8) -#define PROC_PIO_INSTR_MEM31_BITS _u(0x0000ffff) -#define PROC_PIO_INSTR_MEM31_RESET _u(0x00000000) -#define PROC_PIO_INSTR_MEM31_WIDTH _u(32) -#define PROC_PIO_INSTR_MEM31_MSB _u(15) -#define PROC_PIO_INSTR_MEM31_LSB _u(0) +#define PROC_PIO_INSTR_MEM31_BITS _u(0x0000ffff) +#define PROC_PIO_INSTR_MEM31_RESET _u(0x00000000) +#define PROC_PIO_INSTR_MEM31_WIDTH _u(32) +#define PROC_PIO_INSTR_MEM31_MSB _u(15) +#define PROC_PIO_INSTR_MEM31_LSB _u(0) #define PROC_PIO_INSTR_MEM31_ACCESS "WO" // ============================================================================= // Register : PROC_PIO_SM0_CLKDIV // Description : Clock divider register for state machine 0 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) #define PROC_PIO_SM0_CLKDIV_OFFSET _u(0x000000cc) -#define PROC_PIO_SM0_CLKDIV_BITS _u(0xffffff00) -#define PROC_PIO_SM0_CLKDIV_RESET _u(0x00010000) -#define PROC_PIO_SM0_CLKDIV_WIDTH _u(32) +#define PROC_PIO_SM0_CLKDIV_BITS _u(0xffffff00) +#define PROC_PIO_SM0_CLKDIV_RESET _u(0x00010000) +#define PROC_PIO_SM0_CLKDIV_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_CLKDIV_INT // Description : Effective frequency is sysclk/int. // Value of 0 is interpreted as max possible value -#define PROC_PIO_SM0_CLKDIV_INT_RESET _u(0x0001) -#define PROC_PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000) -#define PROC_PIO_SM0_CLKDIV_INT_MSB _u(31) -#define PROC_PIO_SM0_CLKDIV_INT_LSB _u(16) +#define PROC_PIO_SM0_CLKDIV_INT_RESET _u(0x0001) +#define PROC_PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000) +#define PROC_PIO_SM0_CLKDIV_INT_MSB _u(31) +#define PROC_PIO_SM0_CLKDIV_INT_LSB _u(16) #define PROC_PIO_SM0_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_CLKDIV_FRAC // Description : Fractional part of clock divider -#define PROC_PIO_SM0_CLKDIV_FRAC_RESET _u(0x00) -#define PROC_PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PROC_PIO_SM0_CLKDIV_FRAC_MSB _u(15) -#define PROC_PIO_SM0_CLKDIV_FRAC_LSB _u(8) +#define PROC_PIO_SM0_CLKDIV_FRAC_RESET _u(0x00) +#define PROC_PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PROC_PIO_SM0_CLKDIV_FRAC_MSB _u(15) +#define PROC_PIO_SM0_CLKDIV_FRAC_LSB _u(8) #define PROC_PIO_SM0_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM0_EXECCTRL // Description : Execution/behavioural settings for state machine 0 #define PROC_PIO_SM0_EXECCTRL_OFFSET _u(0x000000d0) -#define PROC_PIO_SM0_EXECCTRL_BITS _u(0xffffffbf) -#define PROC_PIO_SM0_EXECCTRL_RESET _u(0x0001f000) -#define PROC_PIO_SM0_EXECCTRL_WIDTH _u(32) +#define PROC_PIO_SM0_EXECCTRL_BITS _u(0xffffffbf) +#define PROC_PIO_SM0_EXECCTRL_RESET _u(0x0001f000) +#define PROC_PIO_SM0_EXECCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_EXEC_STALLED // Description : An instruction written to SMx_INSTR is stalled, and latched by // the // state machine. Will clear once the instruction completes. -#define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PROC_PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_SIDE_EN @@ -830,35 +830,35 @@ // side-set data bit. This allows instructions to perform side-set // optionally, // rather than on every instruction. -#define PROC_PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PROC_PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PROC_PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30) -#define PROC_PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30) +#define PROC_PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PROC_PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PROC_PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30) +#define PROC_PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30) #define PROC_PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR // Description : Side-set data is asserted to pin OEs instead of pin values -#define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PROC_PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PROC_PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PROC_PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28) -#define PROC_PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24) +#define PROC_PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PROC_PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PROC_PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28) +#define PROC_PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24) #define PROC_PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN @@ -869,18 +869,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17) #define PROC_PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_WRAP_TOP @@ -888,47 +888,47 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12) #define PROC_PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) -#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(5) -#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(5) -#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) +#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(5) +#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PROC_PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PROC_PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x00) -#define PROC_PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000001f) -#define PROC_PIO_SM0_EXECCTRL_STATUS_N_MSB _u(4) -#define PROC_PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0) +#define PROC_PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PROC_PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PROC_PIO_SM0_EXECCTRL_STATUS_N_MSB _u(4) +#define PROC_PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0) #define PROC_PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM0_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 0 #define PROC_PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d4) -#define PROC_PIO_SM0_SHIFTCTRL_BITS _u(0xffff0000) -#define PROC_PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000) -#define PROC_PIO_SM0_SHIFTCTRL_WIDTH _u(32) +#define PROC_PIO_SM0_SHIFTCTRL_BITS _u(0xffff0000) +#define PROC_PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000) +#define PROC_PIO_SM0_SHIFTCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -936,10 +936,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX @@ -948,73 +948,73 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH // Description : Number of bits shifted out of TXSR before autopull or // conditional pull. // Write 0 for value of 32. -#define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH // Description : Number of bits shifted into RXSR before autopush or conditional // push. // Write 0 for value of 32. -#define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_SHIFTCTRL_AUTOPULL // Description : Pull automatically when the output shift register is emptied -#define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH // Description : Push automatically when the input shift register is filled -#define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM0_ADDR // Description : Current instruction address of state machine 0 #define PROC_PIO_SM0_ADDR_OFFSET _u(0x000000d8) -#define PROC_PIO_SM0_ADDR_BITS _u(0x0000001f) -#define PROC_PIO_SM0_ADDR_RESET _u(0x00000000) -#define PROC_PIO_SM0_ADDR_WIDTH _u(32) -#define PROC_PIO_SM0_ADDR_MSB _u(4) -#define PROC_PIO_SM0_ADDR_LSB _u(0) +#define PROC_PIO_SM0_ADDR_BITS _u(0x0000001f) +#define PROC_PIO_SM0_ADDR_RESET _u(0x00000000) +#define PROC_PIO_SM0_ADDR_WIDTH _u(32) +#define PROC_PIO_SM0_ADDR_MSB _u(4) +#define PROC_PIO_SM0_ADDR_LSB _u(0) #define PROC_PIO_SM0_ADDR_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_SM0_INSTR @@ -1022,102 +1022,102 @@ // Write to execute an instruction immediately (including jumps) // and then resume execution. #define PROC_PIO_SM0_INSTR_OFFSET _u(0x000000dc) -#define PROC_PIO_SM0_INSTR_BITS _u(0x0000ffff) -#define PROC_PIO_SM0_INSTR_RESET "-" -#define PROC_PIO_SM0_INSTR_WIDTH _u(32) -#define PROC_PIO_SM0_INSTR_MSB _u(15) -#define PROC_PIO_SM0_INSTR_LSB _u(0) +#define PROC_PIO_SM0_INSTR_BITS _u(0x0000ffff) +#define PROC_PIO_SM0_INSTR_RESET "-" +#define PROC_PIO_SM0_INSTR_WIDTH _u(32) +#define PROC_PIO_SM0_INSTR_MSB _u(15) +#define PROC_PIO_SM0_INSTR_LSB _u(0) #define PROC_PIO_SM0_INSTR_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM0_PINCTRL // Description : State machine pin control #define PROC_PIO_SM0_PINCTRL_OFFSET _u(0x000000e0) -#define PROC_PIO_SM0_PINCTRL_BITS _u(0xffffffff) -#define PROC_PIO_SM0_PINCTRL_RESET _u(0x14000000) -#define PROC_PIO_SM0_PINCTRL_WIDTH _u(32) +#define PROC_PIO_SM0_PINCTRL_BITS _u(0xffffffff) +#define PROC_PIO_SM0_PINCTRL_RESET _u(0x14000000) +#define PROC_PIO_SM0_PINCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_PINCTRL_SIDESET_COUNT // Description : The number of delay bits co-opted for side-set. Inclusive of // the enable bit, if present. -#define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_PINCTRL_SET_COUNT // Description : The number of pins asserted by a SET. Max of 5 -#define PROC_PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PROC_PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PROC_PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28) -#define PROC_PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26) +#define PROC_PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PROC_PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PROC_PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28) +#define PROC_PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26) #define PROC_PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_PINCTRL_OUT_COUNT // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PROC_PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PROC_PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PROC_PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25) -#define PROC_PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20) +#define PROC_PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PROC_PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PROC_PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25) +#define PROC_PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20) #define PROC_PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_PINCTRL_IN_BASE // Description : The virtual pin corresponding to IN bit 0 -#define PROC_PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00) -#define PROC_PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PROC_PIO_SM0_PINCTRL_IN_BASE_MSB _u(19) -#define PROC_PIO_SM0_PINCTRL_IN_BASE_LSB _u(15) +#define PROC_PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00) +#define PROC_PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PROC_PIO_SM0_PINCTRL_IN_BASE_MSB _u(19) +#define PROC_PIO_SM0_PINCTRL_IN_BASE_LSB _u(15) #define PROC_PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_PINCTRL_SIDESET_BASE // Description : The virtual pin corresponding to delay field bit 0 -#define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10) #define PROC_PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_PINCTRL_SET_BASE // Description : The virtual pin corresponding to SET bit 0 -#define PROC_PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00) -#define PROC_PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PROC_PIO_SM0_PINCTRL_SET_BASE_MSB _u(9) -#define PROC_PIO_SM0_PINCTRL_SET_BASE_LSB _u(5) +#define PROC_PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00) +#define PROC_PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PROC_PIO_SM0_PINCTRL_SET_BASE_MSB _u(9) +#define PROC_PIO_SM0_PINCTRL_SET_BASE_LSB _u(5) #define PROC_PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_PINCTRL_OUT_BASE // Description : The virtual pin corresponding to OUT bit 0 -#define PROC_PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PROC_PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PROC_PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4) -#define PROC_PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0) +#define PROC_PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PROC_PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PROC_PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4) +#define PROC_PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0) #define PROC_PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM0_DMACTRL_TX // Description : State machine DMA control #define PROC_PIO_SM0_DMACTRL_TX_OFFSET _u(0x000000e4) -#define PROC_PIO_SM0_DMACTRL_TX_BITS _u(0xc0000f9f) -#define PROC_PIO_SM0_DMACTRL_TX_RESET _u(0x00000104) -#define PROC_PIO_SM0_DMACTRL_TX_WIDTH _u(32) +#define PROC_PIO_SM0_DMACTRL_TX_BITS _u(0xc0000f9f) +#define PROC_PIO_SM0_DMACTRL_TX_RESET _u(0x00000104) +#define PROC_PIO_SM0_DMACTRL_TX_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_DMACTRL_TX_DREQ_EN // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_RESET _u(0x0) -#define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) -#define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_MSB _u(31) -#define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_LSB _u(31) +#define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_RESET _u(0x0) +#define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) +#define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_MSB _u(31) +#define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_LSB _u(31) #define PROC_PIO_SM0_DMACTRL_TX_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_DMACTRL_TX_ACTIVE // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_RESET "-" -#define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) -#define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_MSB _u(30) -#define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_LSB _u(30) +#define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_RESET "-" +#define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) +#define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_MSB _u(30) +#define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_LSB _u(30) #define PROC_PIO_SM0_DMACTRL_TX_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME @@ -1125,46 +1125,46 @@ // generated. // Used to account for system bus latency in write data arriving // at the FIFO. -#define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) -#define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) -#define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_MSB _u(11) -#define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_LSB _u(7) +#define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) +#define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) +#define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_MSB _u(11) +#define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_LSB _u(7) #define PROC_PIO_SM0_DMACTRL_TX_DWELL_TIME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD // Description : Threshold control. If there are no more than THRESHOLD items in // the TX FIFO, DMA dreq and/or the interrupt line is asserted. -#define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) -#define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) -#define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) -#define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) +#define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) +#define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) +#define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) +#define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) #define PROC_PIO_SM0_DMACTRL_TX_FIFO_THRESHOLD_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM0_DMACTRL_RX // Description : State machine DMA control #define PROC_PIO_SM0_DMACTRL_RX_OFFSET _u(0x000000e8) -#define PROC_PIO_SM0_DMACTRL_RX_BITS _u(0xc0000f9f) -#define PROC_PIO_SM0_DMACTRL_RX_RESET _u(0x00000104) -#define PROC_PIO_SM0_DMACTRL_RX_WIDTH _u(32) +#define PROC_PIO_SM0_DMACTRL_RX_BITS _u(0xc0000f9f) +#define PROC_PIO_SM0_DMACTRL_RX_RESET _u(0x00000104) +#define PROC_PIO_SM0_DMACTRL_RX_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_DMACTRL_RX_DREQ_EN // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_RESET _u(0x0) -#define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) -#define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_MSB _u(31) -#define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_LSB _u(31) +#define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_RESET _u(0x0) +#define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) +#define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_MSB _u(31) +#define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_LSB _u(31) #define PROC_PIO_SM0_DMACTRL_RX_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_DMACTRL_RX_ACTIVE // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_RESET "-" -#define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) -#define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_MSB _u(30) -#define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_LSB _u(30) +#define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_RESET "-" +#define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) +#define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_MSB _u(30) +#define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_LSB _u(30) #define PROC_PIO_SM0_DMACTRL_RX_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME @@ -1172,61 +1172,61 @@ // generated. // Used to account for system bus latency in write data arriving // at the FIFO. -#define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) -#define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) -#define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_MSB _u(11) -#define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_LSB _u(7) +#define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) +#define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) +#define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_MSB _u(11) +#define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_LSB _u(7) #define PROC_PIO_SM0_DMACTRL_RX_DWELL_TIME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD // Description : Threshold control. If there are at least THRESHOLD items in the // RX FIFO, DMA dreq and/or the interrupt line is asserted. -#define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) -#define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) -#define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) -#define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) +#define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) +#define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) +#define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) +#define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) #define PROC_PIO_SM0_DMACTRL_RX_FIFO_THRESHOLD_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM1_CLKDIV // Description : Clock divider register for state machine 1 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) #define PROC_PIO_SM1_CLKDIV_OFFSET _u(0x000000ec) -#define PROC_PIO_SM1_CLKDIV_BITS _u(0xffffff00) -#define PROC_PIO_SM1_CLKDIV_RESET _u(0x00010000) -#define PROC_PIO_SM1_CLKDIV_WIDTH _u(32) +#define PROC_PIO_SM1_CLKDIV_BITS _u(0xffffff00) +#define PROC_PIO_SM1_CLKDIV_RESET _u(0x00010000) +#define PROC_PIO_SM1_CLKDIV_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_CLKDIV_INT // Description : Effective frequency is sysclk/int. // Value of 0 is interpreted as max possible value -#define PROC_PIO_SM1_CLKDIV_INT_RESET _u(0x0001) -#define PROC_PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000) -#define PROC_PIO_SM1_CLKDIV_INT_MSB _u(31) -#define PROC_PIO_SM1_CLKDIV_INT_LSB _u(16) +#define PROC_PIO_SM1_CLKDIV_INT_RESET _u(0x0001) +#define PROC_PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000) +#define PROC_PIO_SM1_CLKDIV_INT_MSB _u(31) +#define PROC_PIO_SM1_CLKDIV_INT_LSB _u(16) #define PROC_PIO_SM1_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_CLKDIV_FRAC // Description : Fractional part of clock divider -#define PROC_PIO_SM1_CLKDIV_FRAC_RESET _u(0x00) -#define PROC_PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PROC_PIO_SM1_CLKDIV_FRAC_MSB _u(15) -#define PROC_PIO_SM1_CLKDIV_FRAC_LSB _u(8) +#define PROC_PIO_SM1_CLKDIV_FRAC_RESET _u(0x00) +#define PROC_PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PROC_PIO_SM1_CLKDIV_FRAC_MSB _u(15) +#define PROC_PIO_SM1_CLKDIV_FRAC_LSB _u(8) #define PROC_PIO_SM1_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM1_EXECCTRL // Description : Execution/behavioural settings for state machine 1 #define PROC_PIO_SM1_EXECCTRL_OFFSET _u(0x000000f0) -#define PROC_PIO_SM1_EXECCTRL_BITS _u(0xffffffbf) -#define PROC_PIO_SM1_EXECCTRL_RESET _u(0x0001f000) -#define PROC_PIO_SM1_EXECCTRL_WIDTH _u(32) +#define PROC_PIO_SM1_EXECCTRL_BITS _u(0xffffffbf) +#define PROC_PIO_SM1_EXECCTRL_RESET _u(0x0001f000) +#define PROC_PIO_SM1_EXECCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_EXEC_STALLED // Description : An instruction written to SMx_INSTR is stalled, and latched by // the // state machine. Will clear once the instruction completes. -#define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PROC_PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_SIDE_EN @@ -1234,35 +1234,35 @@ // side-set data bit. This allows instructions to perform side-set // optionally, // rather than on every instruction. -#define PROC_PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PROC_PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PROC_PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30) -#define PROC_PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30) +#define PROC_PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PROC_PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PROC_PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30) +#define PROC_PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30) #define PROC_PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR // Description : Side-set data is asserted to pin OEs instead of pin values -#define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PROC_PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PROC_PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PROC_PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PROC_PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28) -#define PROC_PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24) +#define PROC_PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PROC_PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PROC_PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28) +#define PROC_PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24) #define PROC_PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PROC_PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN @@ -1273,18 +1273,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PROC_PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17) #define PROC_PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_WRAP_TOP @@ -1292,47 +1292,47 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12) #define PROC_PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PROC_PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) -#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(5) -#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(5) -#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) +#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(5) +#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PROC_PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PROC_PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x00) -#define PROC_PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000001f) -#define PROC_PIO_SM1_EXECCTRL_STATUS_N_MSB _u(4) -#define PROC_PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0) +#define PROC_PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PROC_PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PROC_PIO_SM1_EXECCTRL_STATUS_N_MSB _u(4) +#define PROC_PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0) #define PROC_PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM1_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 1 #define PROC_PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000f4) -#define PROC_PIO_SM1_SHIFTCTRL_BITS _u(0xffff0000) -#define PROC_PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000) -#define PROC_PIO_SM1_SHIFTCTRL_WIDTH _u(32) +#define PROC_PIO_SM1_SHIFTCTRL_BITS _u(0xffff0000) +#define PROC_PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000) +#define PROC_PIO_SM1_SHIFTCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -1340,10 +1340,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX @@ -1352,73 +1352,73 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PROC_PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH // Description : Number of bits shifted out of TXSR before autopull or // conditional pull. // Write 0 for value of 32. -#define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PROC_PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH // Description : Number of bits shifted into RXSR before autopush or conditional // push. // Write 0 for value of 32. -#define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PROC_PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PROC_PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PROC_PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_SHIFTCTRL_AUTOPULL // Description : Pull automatically when the output shift register is emptied -#define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PROC_PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH // Description : Push automatically when the input shift register is filled -#define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PROC_PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM1_ADDR // Description : Current instruction address of state machine 1 #define PROC_PIO_SM1_ADDR_OFFSET _u(0x000000f8) -#define PROC_PIO_SM1_ADDR_BITS _u(0x0000001f) -#define PROC_PIO_SM1_ADDR_RESET _u(0x00000000) -#define PROC_PIO_SM1_ADDR_WIDTH _u(32) -#define PROC_PIO_SM1_ADDR_MSB _u(4) -#define PROC_PIO_SM1_ADDR_LSB _u(0) +#define PROC_PIO_SM1_ADDR_BITS _u(0x0000001f) +#define PROC_PIO_SM1_ADDR_RESET _u(0x00000000) +#define PROC_PIO_SM1_ADDR_WIDTH _u(32) +#define PROC_PIO_SM1_ADDR_MSB _u(4) +#define PROC_PIO_SM1_ADDR_LSB _u(0) #define PROC_PIO_SM1_ADDR_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_SM1_INSTR @@ -1426,102 +1426,102 @@ // Write to execute an instruction immediately (including jumps) // and then resume execution. #define PROC_PIO_SM1_INSTR_OFFSET _u(0x000000fc) -#define PROC_PIO_SM1_INSTR_BITS _u(0x0000ffff) -#define PROC_PIO_SM1_INSTR_RESET "-" -#define PROC_PIO_SM1_INSTR_WIDTH _u(32) -#define PROC_PIO_SM1_INSTR_MSB _u(15) -#define PROC_PIO_SM1_INSTR_LSB _u(0) +#define PROC_PIO_SM1_INSTR_BITS _u(0x0000ffff) +#define PROC_PIO_SM1_INSTR_RESET "-" +#define PROC_PIO_SM1_INSTR_WIDTH _u(32) +#define PROC_PIO_SM1_INSTR_MSB _u(15) +#define PROC_PIO_SM1_INSTR_LSB _u(0) #define PROC_PIO_SM1_INSTR_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM1_PINCTRL // Description : State machine pin control #define PROC_PIO_SM1_PINCTRL_OFFSET _u(0x00000100) -#define PROC_PIO_SM1_PINCTRL_BITS _u(0xffffffff) -#define PROC_PIO_SM1_PINCTRL_RESET _u(0x14000000) -#define PROC_PIO_SM1_PINCTRL_WIDTH _u(32) +#define PROC_PIO_SM1_PINCTRL_BITS _u(0xffffffff) +#define PROC_PIO_SM1_PINCTRL_RESET _u(0x14000000) +#define PROC_PIO_SM1_PINCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_PINCTRL_SIDESET_COUNT // Description : The number of delay bits co-opted for side-set. Inclusive of // the enable bit, if present. -#define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PROC_PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_PINCTRL_SET_COUNT // Description : The number of pins asserted by a SET. Max of 5 -#define PROC_PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PROC_PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PROC_PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28) -#define PROC_PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26) +#define PROC_PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PROC_PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PROC_PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28) +#define PROC_PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26) #define PROC_PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_PINCTRL_OUT_COUNT // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PROC_PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PROC_PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PROC_PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25) -#define PROC_PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20) +#define PROC_PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PROC_PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PROC_PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25) +#define PROC_PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20) #define PROC_PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_PINCTRL_IN_BASE // Description : The virtual pin corresponding to IN bit 0 -#define PROC_PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00) -#define PROC_PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PROC_PIO_SM1_PINCTRL_IN_BASE_MSB _u(19) -#define PROC_PIO_SM1_PINCTRL_IN_BASE_LSB _u(15) +#define PROC_PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00) +#define PROC_PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PROC_PIO_SM1_PINCTRL_IN_BASE_MSB _u(19) +#define PROC_PIO_SM1_PINCTRL_IN_BASE_LSB _u(15) #define PROC_PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_PINCTRL_SIDESET_BASE // Description : The virtual pin corresponding to delay field bit 0 -#define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10) #define PROC_PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_PINCTRL_SET_BASE // Description : The virtual pin corresponding to SET bit 0 -#define PROC_PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00) -#define PROC_PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PROC_PIO_SM1_PINCTRL_SET_BASE_MSB _u(9) -#define PROC_PIO_SM1_PINCTRL_SET_BASE_LSB _u(5) +#define PROC_PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00) +#define PROC_PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PROC_PIO_SM1_PINCTRL_SET_BASE_MSB _u(9) +#define PROC_PIO_SM1_PINCTRL_SET_BASE_LSB _u(5) #define PROC_PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_PINCTRL_OUT_BASE // Description : The virtual pin corresponding to OUT bit 0 -#define PROC_PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PROC_PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PROC_PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4) -#define PROC_PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0) +#define PROC_PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PROC_PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PROC_PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4) +#define PROC_PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0) #define PROC_PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM1_DMACTRL_TX // Description : State machine DMA control #define PROC_PIO_SM1_DMACTRL_TX_OFFSET _u(0x00000104) -#define PROC_PIO_SM1_DMACTRL_TX_BITS _u(0xc0000f9f) -#define PROC_PIO_SM1_DMACTRL_TX_RESET _u(0x00000104) -#define PROC_PIO_SM1_DMACTRL_TX_WIDTH _u(32) +#define PROC_PIO_SM1_DMACTRL_TX_BITS _u(0xc0000f9f) +#define PROC_PIO_SM1_DMACTRL_TX_RESET _u(0x00000104) +#define PROC_PIO_SM1_DMACTRL_TX_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_DMACTRL_TX_DREQ_EN // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_RESET _u(0x0) -#define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) -#define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_MSB _u(31) -#define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_LSB _u(31) +#define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_RESET _u(0x0) +#define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) +#define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_MSB _u(31) +#define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_LSB _u(31) #define PROC_PIO_SM1_DMACTRL_TX_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_DMACTRL_TX_ACTIVE // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_RESET "-" -#define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) -#define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_MSB _u(30) -#define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_LSB _u(30) +#define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_RESET "-" +#define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) +#define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_MSB _u(30) +#define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_LSB _u(30) #define PROC_PIO_SM1_DMACTRL_TX_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME @@ -1529,46 +1529,46 @@ // generated. // Used to account for system bus latency in write data arriving // at the FIFO. -#define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) -#define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) -#define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_MSB _u(11) -#define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_LSB _u(7) +#define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) +#define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) +#define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_MSB _u(11) +#define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_LSB _u(7) #define PROC_PIO_SM1_DMACTRL_TX_DWELL_TIME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD // Description : Threshold control. If there are no more than THRESHOLD items in // the TX FIFO, DMA dreq and/or the interrupt line is asserted. -#define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) -#define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) -#define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) -#define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) +#define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) +#define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) +#define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) +#define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) #define PROC_PIO_SM1_DMACTRL_TX_FIFO_THRESHOLD_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM1_DMACTRL_RX // Description : State machine DMA control #define PROC_PIO_SM1_DMACTRL_RX_OFFSET _u(0x00000108) -#define PROC_PIO_SM1_DMACTRL_RX_BITS _u(0xc0000f9f) -#define PROC_PIO_SM1_DMACTRL_RX_RESET _u(0x00000104) -#define PROC_PIO_SM1_DMACTRL_RX_WIDTH _u(32) +#define PROC_PIO_SM1_DMACTRL_RX_BITS _u(0xc0000f9f) +#define PROC_PIO_SM1_DMACTRL_RX_RESET _u(0x00000104) +#define PROC_PIO_SM1_DMACTRL_RX_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_DMACTRL_RX_DREQ_EN // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_RESET _u(0x0) -#define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) -#define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_MSB _u(31) -#define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_LSB _u(31) +#define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_RESET _u(0x0) +#define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) +#define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_MSB _u(31) +#define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_LSB _u(31) #define PROC_PIO_SM1_DMACTRL_RX_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_DMACTRL_RX_ACTIVE // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_RESET "-" -#define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) -#define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_MSB _u(30) -#define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_LSB _u(30) +#define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_RESET "-" +#define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) +#define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_MSB _u(30) +#define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_LSB _u(30) #define PROC_PIO_SM1_DMACTRL_RX_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME @@ -1576,61 +1576,61 @@ // generated. // Used to account for system bus latency in write data arriving // at the FIFO. -#define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) -#define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) -#define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_MSB _u(11) -#define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_LSB _u(7) +#define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) +#define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) +#define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_MSB _u(11) +#define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_LSB _u(7) #define PROC_PIO_SM1_DMACTRL_RX_DWELL_TIME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD // Description : Threshold control. If there are at least THRESHOLD items in the // RX FIFO, DMA dreq and/or the interrupt line is asserted. -#define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) -#define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) -#define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) -#define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) +#define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) +#define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) +#define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) +#define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) #define PROC_PIO_SM1_DMACTRL_RX_FIFO_THRESHOLD_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM2_CLKDIV // Description : Clock divider register for state machine 2 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) #define PROC_PIO_SM2_CLKDIV_OFFSET _u(0x0000010c) -#define PROC_PIO_SM2_CLKDIV_BITS _u(0xffffff00) -#define PROC_PIO_SM2_CLKDIV_RESET _u(0x00010000) -#define PROC_PIO_SM2_CLKDIV_WIDTH _u(32) +#define PROC_PIO_SM2_CLKDIV_BITS _u(0xffffff00) +#define PROC_PIO_SM2_CLKDIV_RESET _u(0x00010000) +#define PROC_PIO_SM2_CLKDIV_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_CLKDIV_INT // Description : Effective frequency is sysclk/int. // Value of 0 is interpreted as max possible value -#define PROC_PIO_SM2_CLKDIV_INT_RESET _u(0x0001) -#define PROC_PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000) -#define PROC_PIO_SM2_CLKDIV_INT_MSB _u(31) -#define PROC_PIO_SM2_CLKDIV_INT_LSB _u(16) +#define PROC_PIO_SM2_CLKDIV_INT_RESET _u(0x0001) +#define PROC_PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000) +#define PROC_PIO_SM2_CLKDIV_INT_MSB _u(31) +#define PROC_PIO_SM2_CLKDIV_INT_LSB _u(16) #define PROC_PIO_SM2_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_CLKDIV_FRAC // Description : Fractional part of clock divider -#define PROC_PIO_SM2_CLKDIV_FRAC_RESET _u(0x00) -#define PROC_PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PROC_PIO_SM2_CLKDIV_FRAC_MSB _u(15) -#define PROC_PIO_SM2_CLKDIV_FRAC_LSB _u(8) +#define PROC_PIO_SM2_CLKDIV_FRAC_RESET _u(0x00) +#define PROC_PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PROC_PIO_SM2_CLKDIV_FRAC_MSB _u(15) +#define PROC_PIO_SM2_CLKDIV_FRAC_LSB _u(8) #define PROC_PIO_SM2_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM2_EXECCTRL // Description : Execution/behavioural settings for state machine 2 #define PROC_PIO_SM2_EXECCTRL_OFFSET _u(0x00000110) -#define PROC_PIO_SM2_EXECCTRL_BITS _u(0xffffffbf) -#define PROC_PIO_SM2_EXECCTRL_RESET _u(0x0001f000) -#define PROC_PIO_SM2_EXECCTRL_WIDTH _u(32) +#define PROC_PIO_SM2_EXECCTRL_BITS _u(0xffffffbf) +#define PROC_PIO_SM2_EXECCTRL_RESET _u(0x0001f000) +#define PROC_PIO_SM2_EXECCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_EXEC_STALLED // Description : An instruction written to SMx_INSTR is stalled, and latched by // the // state machine. Will clear once the instruction completes. -#define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PROC_PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_SIDE_EN @@ -1638,35 +1638,35 @@ // side-set data bit. This allows instructions to perform side-set // optionally, // rather than on every instruction. -#define PROC_PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PROC_PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PROC_PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30) -#define PROC_PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30) +#define PROC_PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PROC_PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PROC_PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30) +#define PROC_PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30) #define PROC_PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR // Description : Side-set data is asserted to pin OEs instead of pin values -#define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PROC_PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PROC_PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PROC_PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PROC_PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28) -#define PROC_PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24) +#define PROC_PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PROC_PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PROC_PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28) +#define PROC_PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24) #define PROC_PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PROC_PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN @@ -1677,18 +1677,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PROC_PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17) #define PROC_PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_WRAP_TOP @@ -1696,47 +1696,47 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12) #define PROC_PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PROC_PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) -#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(5) -#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(5) -#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) +#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(5) +#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PROC_PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PROC_PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x00) -#define PROC_PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000001f) -#define PROC_PIO_SM2_EXECCTRL_STATUS_N_MSB _u(4) -#define PROC_PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0) +#define PROC_PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PROC_PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PROC_PIO_SM2_EXECCTRL_STATUS_N_MSB _u(4) +#define PROC_PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0) #define PROC_PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM2_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 2 #define PROC_PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000114) -#define PROC_PIO_SM2_SHIFTCTRL_BITS _u(0xffff0000) -#define PROC_PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000) -#define PROC_PIO_SM2_SHIFTCTRL_WIDTH _u(32) +#define PROC_PIO_SM2_SHIFTCTRL_BITS _u(0xffff0000) +#define PROC_PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000) +#define PROC_PIO_SM2_SHIFTCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -1744,10 +1744,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX @@ -1756,73 +1756,73 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PROC_PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH // Description : Number of bits shifted out of TXSR before autopull or // conditional pull. // Write 0 for value of 32. -#define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PROC_PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH // Description : Number of bits shifted into RXSR before autopush or conditional // push. // Write 0 for value of 32. -#define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PROC_PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PROC_PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PROC_PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_SHIFTCTRL_AUTOPULL // Description : Pull automatically when the output shift register is emptied -#define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PROC_PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH // Description : Push automatically when the input shift register is filled -#define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PROC_PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM2_ADDR // Description : Current instruction address of state machine 2 #define PROC_PIO_SM2_ADDR_OFFSET _u(0x00000118) -#define PROC_PIO_SM2_ADDR_BITS _u(0x0000001f) -#define PROC_PIO_SM2_ADDR_RESET _u(0x00000000) -#define PROC_PIO_SM2_ADDR_WIDTH _u(32) -#define PROC_PIO_SM2_ADDR_MSB _u(4) -#define PROC_PIO_SM2_ADDR_LSB _u(0) +#define PROC_PIO_SM2_ADDR_BITS _u(0x0000001f) +#define PROC_PIO_SM2_ADDR_RESET _u(0x00000000) +#define PROC_PIO_SM2_ADDR_WIDTH _u(32) +#define PROC_PIO_SM2_ADDR_MSB _u(4) +#define PROC_PIO_SM2_ADDR_LSB _u(0) #define PROC_PIO_SM2_ADDR_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_SM2_INSTR @@ -1830,102 +1830,102 @@ // Write to execute an instruction immediately (including jumps) // and then resume execution. #define PROC_PIO_SM2_INSTR_OFFSET _u(0x0000011c) -#define PROC_PIO_SM2_INSTR_BITS _u(0x0000ffff) -#define PROC_PIO_SM2_INSTR_RESET "-" -#define PROC_PIO_SM2_INSTR_WIDTH _u(32) -#define PROC_PIO_SM2_INSTR_MSB _u(15) -#define PROC_PIO_SM2_INSTR_LSB _u(0) +#define PROC_PIO_SM2_INSTR_BITS _u(0x0000ffff) +#define PROC_PIO_SM2_INSTR_RESET "-" +#define PROC_PIO_SM2_INSTR_WIDTH _u(32) +#define PROC_PIO_SM2_INSTR_MSB _u(15) +#define PROC_PIO_SM2_INSTR_LSB _u(0) #define PROC_PIO_SM2_INSTR_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM2_PINCTRL // Description : State machine pin control #define PROC_PIO_SM2_PINCTRL_OFFSET _u(0x00000120) -#define PROC_PIO_SM2_PINCTRL_BITS _u(0xffffffff) -#define PROC_PIO_SM2_PINCTRL_RESET _u(0x14000000) -#define PROC_PIO_SM2_PINCTRL_WIDTH _u(32) +#define PROC_PIO_SM2_PINCTRL_BITS _u(0xffffffff) +#define PROC_PIO_SM2_PINCTRL_RESET _u(0x14000000) +#define PROC_PIO_SM2_PINCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_PINCTRL_SIDESET_COUNT // Description : The number of delay bits co-opted for side-set. Inclusive of // the enable bit, if present. -#define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PROC_PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_PINCTRL_SET_COUNT // Description : The number of pins asserted by a SET. Max of 5 -#define PROC_PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PROC_PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PROC_PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28) -#define PROC_PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26) +#define PROC_PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PROC_PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PROC_PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28) +#define PROC_PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26) #define PROC_PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_PINCTRL_OUT_COUNT // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PROC_PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PROC_PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PROC_PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25) -#define PROC_PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20) +#define PROC_PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PROC_PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PROC_PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25) +#define PROC_PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20) #define PROC_PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_PINCTRL_IN_BASE // Description : The virtual pin corresponding to IN bit 0 -#define PROC_PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00) -#define PROC_PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PROC_PIO_SM2_PINCTRL_IN_BASE_MSB _u(19) -#define PROC_PIO_SM2_PINCTRL_IN_BASE_LSB _u(15) +#define PROC_PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00) +#define PROC_PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PROC_PIO_SM2_PINCTRL_IN_BASE_MSB _u(19) +#define PROC_PIO_SM2_PINCTRL_IN_BASE_LSB _u(15) #define PROC_PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_PINCTRL_SIDESET_BASE // Description : The virtual pin corresponding to delay field bit 0 -#define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10) #define PROC_PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_PINCTRL_SET_BASE // Description : The virtual pin corresponding to SET bit 0 -#define PROC_PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00) -#define PROC_PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PROC_PIO_SM2_PINCTRL_SET_BASE_MSB _u(9) -#define PROC_PIO_SM2_PINCTRL_SET_BASE_LSB _u(5) +#define PROC_PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00) +#define PROC_PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PROC_PIO_SM2_PINCTRL_SET_BASE_MSB _u(9) +#define PROC_PIO_SM2_PINCTRL_SET_BASE_LSB _u(5) #define PROC_PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_PINCTRL_OUT_BASE // Description : The virtual pin corresponding to OUT bit 0 -#define PROC_PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PROC_PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PROC_PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4) -#define PROC_PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0) +#define PROC_PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PROC_PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PROC_PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4) +#define PROC_PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0) #define PROC_PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM2_DMACTRL_TX // Description : State machine DMA control #define PROC_PIO_SM2_DMACTRL_TX_OFFSET _u(0x00000124) -#define PROC_PIO_SM2_DMACTRL_TX_BITS _u(0xc0000f9f) -#define PROC_PIO_SM2_DMACTRL_TX_RESET _u(0x00000104) -#define PROC_PIO_SM2_DMACTRL_TX_WIDTH _u(32) +#define PROC_PIO_SM2_DMACTRL_TX_BITS _u(0xc0000f9f) +#define PROC_PIO_SM2_DMACTRL_TX_RESET _u(0x00000104) +#define PROC_PIO_SM2_DMACTRL_TX_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_DMACTRL_TX_DREQ_EN // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_RESET _u(0x0) -#define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) -#define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_MSB _u(31) -#define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_LSB _u(31) +#define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_RESET _u(0x0) +#define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) +#define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_MSB _u(31) +#define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_LSB _u(31) #define PROC_PIO_SM2_DMACTRL_TX_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_DMACTRL_TX_ACTIVE // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_RESET "-" -#define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) -#define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_MSB _u(30) -#define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_LSB _u(30) +#define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_RESET "-" +#define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) +#define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_MSB _u(30) +#define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_LSB _u(30) #define PROC_PIO_SM2_DMACTRL_TX_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME @@ -1933,46 +1933,46 @@ // generated. // Used to account for system bus latency in write data arriving // at the FIFO. -#define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) -#define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) -#define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_MSB _u(11) -#define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_LSB _u(7) +#define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) +#define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) +#define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_MSB _u(11) +#define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_LSB _u(7) #define PROC_PIO_SM2_DMACTRL_TX_DWELL_TIME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD // Description : Threshold control. If there are no more than THRESHOLD items in // the TX FIFO, DMA dreq and/or the interrupt line is asserted. -#define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) -#define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) -#define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) -#define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) +#define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) +#define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) +#define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) +#define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) #define PROC_PIO_SM2_DMACTRL_TX_FIFO_THRESHOLD_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM2_DMACTRL_RX // Description : State machine DMA control #define PROC_PIO_SM2_DMACTRL_RX_OFFSET _u(0x00000128) -#define PROC_PIO_SM2_DMACTRL_RX_BITS _u(0xc0000f9f) -#define PROC_PIO_SM2_DMACTRL_RX_RESET _u(0x00000104) -#define PROC_PIO_SM2_DMACTRL_RX_WIDTH _u(32) +#define PROC_PIO_SM2_DMACTRL_RX_BITS _u(0xc0000f9f) +#define PROC_PIO_SM2_DMACTRL_RX_RESET _u(0x00000104) +#define PROC_PIO_SM2_DMACTRL_RX_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_DMACTRL_RX_DREQ_EN // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_RESET _u(0x0) -#define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) -#define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_MSB _u(31) -#define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_LSB _u(31) +#define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_RESET _u(0x0) +#define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) +#define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_MSB _u(31) +#define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_LSB _u(31) #define PROC_PIO_SM2_DMACTRL_RX_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_DMACTRL_RX_ACTIVE // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_RESET "-" -#define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) -#define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_MSB _u(30) -#define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_LSB _u(30) +#define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_RESET "-" +#define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) +#define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_MSB _u(30) +#define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_LSB _u(30) #define PROC_PIO_SM2_DMACTRL_RX_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME @@ -1980,61 +1980,61 @@ // generated. // Used to account for system bus latency in write data arriving // at the FIFO. -#define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) -#define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) -#define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_MSB _u(11) -#define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_LSB _u(7) +#define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) +#define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) +#define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_MSB _u(11) +#define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_LSB _u(7) #define PROC_PIO_SM2_DMACTRL_RX_DWELL_TIME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD // Description : Threshold control. If there are at least THRESHOLD items in the // RX FIFO, DMA dreq and/or the interrupt line is asserted. -#define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) -#define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) -#define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) -#define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) +#define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) +#define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) +#define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) +#define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) #define PROC_PIO_SM2_DMACTRL_RX_FIFO_THRESHOLD_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM3_CLKDIV // Description : Clock divider register for state machine 3 // Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) #define PROC_PIO_SM3_CLKDIV_OFFSET _u(0x0000012c) -#define PROC_PIO_SM3_CLKDIV_BITS _u(0xffffff00) -#define PROC_PIO_SM3_CLKDIV_RESET _u(0x00010000) -#define PROC_PIO_SM3_CLKDIV_WIDTH _u(32) +#define PROC_PIO_SM3_CLKDIV_BITS _u(0xffffff00) +#define PROC_PIO_SM3_CLKDIV_RESET _u(0x00010000) +#define PROC_PIO_SM3_CLKDIV_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_CLKDIV_INT // Description : Effective frequency is sysclk/int. // Value of 0 is interpreted as max possible value -#define PROC_PIO_SM3_CLKDIV_INT_RESET _u(0x0001) -#define PROC_PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000) -#define PROC_PIO_SM3_CLKDIV_INT_MSB _u(31) -#define PROC_PIO_SM3_CLKDIV_INT_LSB _u(16) +#define PROC_PIO_SM3_CLKDIV_INT_RESET _u(0x0001) +#define PROC_PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000) +#define PROC_PIO_SM3_CLKDIV_INT_MSB _u(31) +#define PROC_PIO_SM3_CLKDIV_INT_LSB _u(16) #define PROC_PIO_SM3_CLKDIV_INT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_CLKDIV_FRAC // Description : Fractional part of clock divider -#define PROC_PIO_SM3_CLKDIV_FRAC_RESET _u(0x00) -#define PROC_PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00) -#define PROC_PIO_SM3_CLKDIV_FRAC_MSB _u(15) -#define PROC_PIO_SM3_CLKDIV_FRAC_LSB _u(8) +#define PROC_PIO_SM3_CLKDIV_FRAC_RESET _u(0x00) +#define PROC_PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00) +#define PROC_PIO_SM3_CLKDIV_FRAC_MSB _u(15) +#define PROC_PIO_SM3_CLKDIV_FRAC_LSB _u(8) #define PROC_PIO_SM3_CLKDIV_FRAC_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM3_EXECCTRL // Description : Execution/behavioural settings for state machine 3 #define PROC_PIO_SM3_EXECCTRL_OFFSET _u(0x00000130) -#define PROC_PIO_SM3_EXECCTRL_BITS _u(0xffffffbf) -#define PROC_PIO_SM3_EXECCTRL_RESET _u(0x0001f000) -#define PROC_PIO_SM3_EXECCTRL_WIDTH _u(32) +#define PROC_PIO_SM3_EXECCTRL_BITS _u(0xffffffbf) +#define PROC_PIO_SM3_EXECCTRL_RESET _u(0x0001f000) +#define PROC_PIO_SM3_EXECCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_EXEC_STALLED // Description : An instruction written to SMx_INSTR is stalled, and latched by // the // state machine. Will clear once the instruction completes. -#define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0) -#define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) -#define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31) -#define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31) +#define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0) +#define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000) +#define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31) +#define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31) #define PROC_PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_SIDE_EN @@ -2042,35 +2042,35 @@ // side-set data bit. This allows instructions to perform side-set // optionally, // rather than on every instruction. -#define PROC_PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0) -#define PROC_PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000) -#define PROC_PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30) -#define PROC_PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30) +#define PROC_PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0) +#define PROC_PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000) +#define PROC_PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30) +#define PROC_PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30) #define PROC_PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR // Description : Side-set data is asserted to pin OEs instead of pin values -#define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) -#define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) -#define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29) -#define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29) +#define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0) +#define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000) +#define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29) +#define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29) #define PROC_PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_JMP_PIN // Description : The GPIO number to use as condition for JMP PIN. Unaffected by // input mapping. -#define PROC_PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00) -#define PROC_PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) -#define PROC_PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28) -#define PROC_PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24) +#define PROC_PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00) +#define PROC_PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000) +#define PROC_PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28) +#define PROC_PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24) #define PROC_PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL // Description : Which data bit to use for inline OUT enable -#define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) -#define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) -#define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23) -#define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19) +#define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00) +#define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000) +#define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23) +#define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19) #define PROC_PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN @@ -2081,18 +2081,18 @@ // masking/override behaviour // due to the priority ordering of state machine pin writes (SM0 < // SM1 < ...) -#define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) -#define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) -#define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18) -#define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18) +#define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0) +#define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000) +#define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18) +#define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18) #define PROC_PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_OUT_STICKY // Description : Continuously assert the most recent OUT/SET to the pins -#define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0) -#define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) -#define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17) -#define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17) +#define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0) +#define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000) +#define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17) +#define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17) #define PROC_PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_WRAP_TOP @@ -2100,47 +2100,47 @@ // wrap_bottom. // If the instruction is a jump, and the jump condition is true, // the jump takes priority. -#define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f) -#define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) -#define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16) -#define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12) +#define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f) +#define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000) +#define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16) +#define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12) #define PROC_PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM // Description : After reaching wrap_top, execution is wrapped to this address. -#define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) -#define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) -#define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11) -#define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7) +#define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00) +#define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80) +#define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11) +#define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7) #define PROC_PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_STATUS_SEL // Description : Comparison used for the MOV x, STATUS instruction. // 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes // 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes -#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) -#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) -#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(5) -#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(5) -#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" +#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0) +#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000020) +#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(5) +#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(5) +#define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW" #define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0) #define PROC_PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_EXECCTRL_STATUS_N // Description : Comparison level for the MOV x, STATUS instruction -#define PROC_PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x00) -#define PROC_PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000001f) -#define PROC_PIO_SM3_EXECCTRL_STATUS_N_MSB _u(4) -#define PROC_PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0) +#define PROC_PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x00) +#define PROC_PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000001f) +#define PROC_PIO_SM3_EXECCTRL_STATUS_N_MSB _u(4) +#define PROC_PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0) #define PROC_PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM3_SHIFTCTRL // Description : Control behaviour of the input/output shift registers for state // machine 3 #define PROC_PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000134) -#define PROC_PIO_SM3_SHIFTCTRL_BITS _u(0xffff0000) -#define PROC_PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000) -#define PROC_PIO_SM3_SHIFTCTRL_WIDTH _u(32) +#define PROC_PIO_SM3_SHIFTCTRL_BITS _u(0xffff0000) +#define PROC_PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000) +#define PROC_PIO_SM3_SHIFTCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX // Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice @@ -2148,10 +2148,10 @@ // TX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) -#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) -#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31) -#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31) +#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0) +#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000) +#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31) +#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31) #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX @@ -2160,73 +2160,73 @@ // RX FIFO is disabled as a result (always reads as both full and // empty). // FIFOs are flushed when this bit is changed. -#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) -#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) -#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30) -#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30) +#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0) +#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000) +#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30) +#define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30) #define PROC_PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH // Description : Number of bits shifted out of TXSR before autopull or // conditional pull. // Write 0 for value of 32. -#define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) -#define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) -#define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29) -#define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25) +#define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00) +#define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000) +#define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29) +#define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25) #define PROC_PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH // Description : Number of bits shifted into RXSR before autopush or conditional // push. // Write 0 for value of 32. -#define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) -#define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) -#define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24) -#define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20) +#define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00) +#define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000) +#define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24) +#define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20) #define PROC_PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR // Description : 1 = shift out of output shift register to right. 0 = to left. -#define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) -#define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) -#define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) -#define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) +#define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1) +#define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000) +#define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19) +#define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19) #define PROC_PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR // Description : 1 = shift input shift register to right (data enters from // left). 0 = to left. -#define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) -#define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) -#define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) -#define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) +#define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1) +#define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000) +#define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18) +#define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18) #define PROC_PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_SHIFTCTRL_AUTOPULL // Description : Pull automatically when the output shift register is emptied -#define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0) -#define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) -#define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17) -#define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17) +#define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0) +#define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000) +#define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17) +#define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17) #define PROC_PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH // Description : Push automatically when the input shift register is filled -#define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) -#define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) -#define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16) -#define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16) +#define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0) +#define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000) +#define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16) +#define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16) #define PROC_PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM3_ADDR // Description : Current instruction address of state machine 3 #define PROC_PIO_SM3_ADDR_OFFSET _u(0x00000138) -#define PROC_PIO_SM3_ADDR_BITS _u(0x0000001f) -#define PROC_PIO_SM3_ADDR_RESET _u(0x00000000) -#define PROC_PIO_SM3_ADDR_WIDTH _u(32) -#define PROC_PIO_SM3_ADDR_MSB _u(4) -#define PROC_PIO_SM3_ADDR_LSB _u(0) +#define PROC_PIO_SM3_ADDR_BITS _u(0x0000001f) +#define PROC_PIO_SM3_ADDR_RESET _u(0x00000000) +#define PROC_PIO_SM3_ADDR_WIDTH _u(32) +#define PROC_PIO_SM3_ADDR_MSB _u(4) +#define PROC_PIO_SM3_ADDR_LSB _u(0) #define PROC_PIO_SM3_ADDR_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_SM3_INSTR @@ -2234,102 +2234,102 @@ // Write to execute an instruction immediately (including jumps) // and then resume execution. #define PROC_PIO_SM3_INSTR_OFFSET _u(0x0000013c) -#define PROC_PIO_SM3_INSTR_BITS _u(0x0000ffff) -#define PROC_PIO_SM3_INSTR_RESET "-" -#define PROC_PIO_SM3_INSTR_WIDTH _u(32) -#define PROC_PIO_SM3_INSTR_MSB _u(15) -#define PROC_PIO_SM3_INSTR_LSB _u(0) +#define PROC_PIO_SM3_INSTR_BITS _u(0x0000ffff) +#define PROC_PIO_SM3_INSTR_RESET "-" +#define PROC_PIO_SM3_INSTR_WIDTH _u(32) +#define PROC_PIO_SM3_INSTR_MSB _u(15) +#define PROC_PIO_SM3_INSTR_LSB _u(0) #define PROC_PIO_SM3_INSTR_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM3_PINCTRL // Description : State machine pin control #define PROC_PIO_SM3_PINCTRL_OFFSET _u(0x00000140) -#define PROC_PIO_SM3_PINCTRL_BITS _u(0xffffffff) -#define PROC_PIO_SM3_PINCTRL_RESET _u(0x14000000) -#define PROC_PIO_SM3_PINCTRL_WIDTH _u(32) +#define PROC_PIO_SM3_PINCTRL_BITS _u(0xffffffff) +#define PROC_PIO_SM3_PINCTRL_RESET _u(0x14000000) +#define PROC_PIO_SM3_PINCTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_PINCTRL_SIDESET_COUNT // Description : The number of delay bits co-opted for side-set. Inclusive of // the enable bit, if present. -#define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0) -#define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) -#define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31) -#define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29) +#define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0) +#define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000) +#define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31) +#define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29) #define PROC_PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_PINCTRL_SET_COUNT // Description : The number of pins asserted by a SET. Max of 5 -#define PROC_PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5) -#define PROC_PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000) -#define PROC_PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28) -#define PROC_PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26) +#define PROC_PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5) +#define PROC_PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000) +#define PROC_PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28) +#define PROC_PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26) #define PROC_PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_PINCTRL_OUT_COUNT // Description : The number of pins asserted by an OUT. Value of 0 -> 32 pins -#define PROC_PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00) -#define PROC_PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) -#define PROC_PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25) -#define PROC_PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20) +#define PROC_PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00) +#define PROC_PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000) +#define PROC_PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25) +#define PROC_PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20) #define PROC_PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_PINCTRL_IN_BASE // Description : The virtual pin corresponding to IN bit 0 -#define PROC_PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00) -#define PROC_PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000) -#define PROC_PIO_SM3_PINCTRL_IN_BASE_MSB _u(19) -#define PROC_PIO_SM3_PINCTRL_IN_BASE_LSB _u(15) +#define PROC_PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00) +#define PROC_PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000) +#define PROC_PIO_SM3_PINCTRL_IN_BASE_MSB _u(19) +#define PROC_PIO_SM3_PINCTRL_IN_BASE_LSB _u(15) #define PROC_PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_PINCTRL_SIDESET_BASE // Description : The virtual pin corresponding to delay field bit 0 -#define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) -#define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) -#define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) -#define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10) +#define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00) +#define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00) +#define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14) +#define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10) #define PROC_PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_PINCTRL_SET_BASE // Description : The virtual pin corresponding to SET bit 0 -#define PROC_PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00) -#define PROC_PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0) -#define PROC_PIO_SM3_PINCTRL_SET_BASE_MSB _u(9) -#define PROC_PIO_SM3_PINCTRL_SET_BASE_LSB _u(5) +#define PROC_PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00) +#define PROC_PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0) +#define PROC_PIO_SM3_PINCTRL_SET_BASE_MSB _u(9) +#define PROC_PIO_SM3_PINCTRL_SET_BASE_LSB _u(5) #define PROC_PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_PINCTRL_OUT_BASE // Description : The virtual pin corresponding to OUT bit 0 -#define PROC_PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00) -#define PROC_PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f) -#define PROC_PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4) -#define PROC_PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0) +#define PROC_PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00) +#define PROC_PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f) +#define PROC_PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4) +#define PROC_PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0) #define PROC_PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM3_DMACTRL_TX // Description : State machine DMA control #define PROC_PIO_SM3_DMACTRL_TX_OFFSET _u(0x00000144) -#define PROC_PIO_SM3_DMACTRL_TX_BITS _u(0xc0000f9f) -#define PROC_PIO_SM3_DMACTRL_TX_RESET _u(0x00000104) -#define PROC_PIO_SM3_DMACTRL_TX_WIDTH _u(32) +#define PROC_PIO_SM3_DMACTRL_TX_BITS _u(0xc0000f9f) +#define PROC_PIO_SM3_DMACTRL_TX_RESET _u(0x00000104) +#define PROC_PIO_SM3_DMACTRL_TX_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_DMACTRL_TX_DREQ_EN // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_RESET _u(0x0) -#define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) -#define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_MSB _u(31) -#define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_LSB _u(31) +#define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_RESET _u(0x0) +#define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_BITS _u(0x80000000) +#define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_MSB _u(31) +#define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_LSB _u(31) #define PROC_PIO_SM3_DMACTRL_TX_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_DMACTRL_TX_ACTIVE // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_RESET "-" -#define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) -#define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_MSB _u(30) -#define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_LSB _u(30) +#define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_RESET "-" +#define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_BITS _u(0x40000000) +#define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_MSB _u(30) +#define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_LSB _u(30) #define PROC_PIO_SM3_DMACTRL_TX_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME @@ -2337,46 +2337,46 @@ // generated. // Used to account for system bus latency in write data arriving // at the FIFO. -#define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) -#define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) -#define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_MSB _u(11) -#define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_LSB _u(7) +#define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_RESET _u(0x02) +#define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_BITS _u(0x00000f80) +#define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_MSB _u(11) +#define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_LSB _u(7) #define PROC_PIO_SM3_DMACTRL_TX_DWELL_TIME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD // Description : Threshold control. If there are no more than THRESHOLD items in // the TX FIFO, DMA dreq and/or the interrupt line is asserted. -#define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) -#define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) -#define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) -#define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) +#define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_RESET _u(0x04) +#define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_BITS _u(0x0000001f) +#define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_MSB _u(4) +#define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_LSB _u(0) #define PROC_PIO_SM3_DMACTRL_TX_FIFO_THRESHOLD_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_SM3_DMACTRL_RX // Description : State machine DMA control #define PROC_PIO_SM3_DMACTRL_RX_OFFSET _u(0x00000148) -#define PROC_PIO_SM3_DMACTRL_RX_BITS _u(0xc0000f9f) -#define PROC_PIO_SM3_DMACTRL_RX_RESET _u(0x00000104) -#define PROC_PIO_SM3_DMACTRL_RX_WIDTH _u(32) +#define PROC_PIO_SM3_DMACTRL_RX_BITS _u(0xc0000f9f) +#define PROC_PIO_SM3_DMACTRL_RX_RESET _u(0x00000104) +#define PROC_PIO_SM3_DMACTRL_RX_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_DMACTRL_RX_DREQ_EN // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_RESET _u(0x0) -#define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) -#define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_MSB _u(31) -#define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_LSB _u(31) +#define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_RESET _u(0x0) +#define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_BITS _u(0x80000000) +#define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_MSB _u(31) +#define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_LSB _u(31) #define PROC_PIO_SM3_DMACTRL_RX_DREQ_EN_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_DMACTRL_RX_ACTIVE // Description : 1 - Assert DREQ to DMA when fewer than fifo_threshold spaces // are available // 0 - Don't assert DREQ -#define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_RESET "-" -#define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) -#define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_MSB _u(30) -#define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_LSB _u(30) +#define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_RESET "-" +#define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_BITS _u(0x40000000) +#define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_MSB _u(30) +#define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_LSB _u(30) #define PROC_PIO_SM3_DMACTRL_RX_ACTIVE_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME @@ -2384,839 +2384,839 @@ // generated. // Used to account for system bus latency in write data arriving // at the FIFO. -#define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) -#define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) -#define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_MSB _u(11) -#define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_LSB _u(7) +#define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_RESET _u(0x02) +#define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_BITS _u(0x00000f80) +#define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_MSB _u(11) +#define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_LSB _u(7) #define PROC_PIO_SM3_DMACTRL_RX_DWELL_TIME_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD // Description : Threshold control. If there are at least THRESHOLD items in the // RX FIFO, DMA dreq and/or the interrupt line is asserted. -#define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) -#define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) -#define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) -#define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) +#define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_RESET _u(0x04) +#define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_BITS _u(0x0000001f) +#define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_MSB _u(4) +#define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_LSB _u(0) #define PROC_PIO_SM3_DMACTRL_RX_FIFO_THRESHOLD_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_INTR // Description : Raw Interrupts #define PROC_PIO_INTR_OFFSET _u(0x0000014c) -#define PROC_PIO_INTR_BITS _u(0x00000fff) -#define PROC_PIO_INTR_RESET _u(0x00000000) -#define PROC_PIO_INTR_WIDTH _u(32) +#define PROC_PIO_INTR_BITS _u(0x00000fff) +#define PROC_PIO_INTR_RESET _u(0x00000000) +#define PROC_PIO_INTR_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM3 // Description : None -#define PROC_PIO_INTR_SM3_RESET _u(0x0) -#define PROC_PIO_INTR_SM3_BITS _u(0x00000800) -#define PROC_PIO_INTR_SM3_MSB _u(11) -#define PROC_PIO_INTR_SM3_LSB _u(11) +#define PROC_PIO_INTR_SM3_RESET _u(0x0) +#define PROC_PIO_INTR_SM3_BITS _u(0x00000800) +#define PROC_PIO_INTR_SM3_MSB _u(11) +#define PROC_PIO_INTR_SM3_LSB _u(11) #define PROC_PIO_INTR_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM2 // Description : None -#define PROC_PIO_INTR_SM2_RESET _u(0x0) -#define PROC_PIO_INTR_SM2_BITS _u(0x00000400) -#define PROC_PIO_INTR_SM2_MSB _u(10) -#define PROC_PIO_INTR_SM2_LSB _u(10) +#define PROC_PIO_INTR_SM2_RESET _u(0x0) +#define PROC_PIO_INTR_SM2_BITS _u(0x00000400) +#define PROC_PIO_INTR_SM2_MSB _u(10) +#define PROC_PIO_INTR_SM2_LSB _u(10) #define PROC_PIO_INTR_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM1 // Description : None -#define PROC_PIO_INTR_SM1_RESET _u(0x0) -#define PROC_PIO_INTR_SM1_BITS _u(0x00000200) -#define PROC_PIO_INTR_SM1_MSB _u(9) -#define PROC_PIO_INTR_SM1_LSB _u(9) +#define PROC_PIO_INTR_SM1_RESET _u(0x0) +#define PROC_PIO_INTR_SM1_BITS _u(0x00000200) +#define PROC_PIO_INTR_SM1_MSB _u(9) +#define PROC_PIO_INTR_SM1_LSB _u(9) #define PROC_PIO_INTR_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM0 // Description : None -#define PROC_PIO_INTR_SM0_RESET _u(0x0) -#define PROC_PIO_INTR_SM0_BITS _u(0x00000100) -#define PROC_PIO_INTR_SM0_MSB _u(8) -#define PROC_PIO_INTR_SM0_LSB _u(8) +#define PROC_PIO_INTR_SM0_RESET _u(0x0) +#define PROC_PIO_INTR_SM0_BITS _u(0x00000100) +#define PROC_PIO_INTR_SM0_MSB _u(8) +#define PROC_PIO_INTR_SM0_LSB _u(8) #define PROC_PIO_INTR_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM3_TXNFULL // Description : None -#define PROC_PIO_INTR_SM3_TXNFULL_RESET _u(0x0) -#define PROC_PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) -#define PROC_PIO_INTR_SM3_TXNFULL_MSB _u(7) -#define PROC_PIO_INTR_SM3_TXNFULL_LSB _u(7) +#define PROC_PIO_INTR_SM3_TXNFULL_RESET _u(0x0) +#define PROC_PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080) +#define PROC_PIO_INTR_SM3_TXNFULL_MSB _u(7) +#define PROC_PIO_INTR_SM3_TXNFULL_LSB _u(7) #define PROC_PIO_INTR_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM2_TXNFULL // Description : None -#define PROC_PIO_INTR_SM2_TXNFULL_RESET _u(0x0) -#define PROC_PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) -#define PROC_PIO_INTR_SM2_TXNFULL_MSB _u(6) -#define PROC_PIO_INTR_SM2_TXNFULL_LSB _u(6) +#define PROC_PIO_INTR_SM2_TXNFULL_RESET _u(0x0) +#define PROC_PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040) +#define PROC_PIO_INTR_SM2_TXNFULL_MSB _u(6) +#define PROC_PIO_INTR_SM2_TXNFULL_LSB _u(6) #define PROC_PIO_INTR_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM1_TXNFULL // Description : None -#define PROC_PIO_INTR_SM1_TXNFULL_RESET _u(0x0) -#define PROC_PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) -#define PROC_PIO_INTR_SM1_TXNFULL_MSB _u(5) -#define PROC_PIO_INTR_SM1_TXNFULL_LSB _u(5) +#define PROC_PIO_INTR_SM1_TXNFULL_RESET _u(0x0) +#define PROC_PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020) +#define PROC_PIO_INTR_SM1_TXNFULL_MSB _u(5) +#define PROC_PIO_INTR_SM1_TXNFULL_LSB _u(5) #define PROC_PIO_INTR_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM0_TXNFULL // Description : None -#define PROC_PIO_INTR_SM0_TXNFULL_RESET _u(0x0) -#define PROC_PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) -#define PROC_PIO_INTR_SM0_TXNFULL_MSB _u(4) -#define PROC_PIO_INTR_SM0_TXNFULL_LSB _u(4) +#define PROC_PIO_INTR_SM0_TXNFULL_RESET _u(0x0) +#define PROC_PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010) +#define PROC_PIO_INTR_SM0_TXNFULL_MSB _u(4) +#define PROC_PIO_INTR_SM0_TXNFULL_LSB _u(4) #define PROC_PIO_INTR_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM3_RXNEMPTY // Description : None -#define PROC_PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PROC_PIO_INTR_SM3_RXNEMPTY_MSB _u(3) -#define PROC_PIO_INTR_SM3_RXNEMPTY_LSB _u(3) +#define PROC_PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PROC_PIO_INTR_SM3_RXNEMPTY_MSB _u(3) +#define PROC_PIO_INTR_SM3_RXNEMPTY_LSB _u(3) #define PROC_PIO_INTR_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM2_RXNEMPTY // Description : None -#define PROC_PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PROC_PIO_INTR_SM2_RXNEMPTY_MSB _u(2) -#define PROC_PIO_INTR_SM2_RXNEMPTY_LSB _u(2) +#define PROC_PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PROC_PIO_INTR_SM2_RXNEMPTY_MSB _u(2) +#define PROC_PIO_INTR_SM2_RXNEMPTY_LSB _u(2) #define PROC_PIO_INTR_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM1_RXNEMPTY // Description : None -#define PROC_PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PROC_PIO_INTR_SM1_RXNEMPTY_MSB _u(1) -#define PROC_PIO_INTR_SM1_RXNEMPTY_LSB _u(1) +#define PROC_PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PROC_PIO_INTR_SM1_RXNEMPTY_MSB _u(1) +#define PROC_PIO_INTR_SM1_RXNEMPTY_LSB _u(1) #define PROC_PIO_INTR_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_INTR_SM0_RXNEMPTY // Description : None -#define PROC_PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PROC_PIO_INTR_SM0_RXNEMPTY_MSB _u(0) -#define PROC_PIO_INTR_SM0_RXNEMPTY_LSB _u(0) +#define PROC_PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PROC_PIO_INTR_SM0_RXNEMPTY_MSB _u(0) +#define PROC_PIO_INTR_SM0_RXNEMPTY_LSB _u(0) #define PROC_PIO_INTR_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_IRQ0_INTE // Description : Interrupt Enable for irq0 #define PROC_PIO_IRQ0_INTE_OFFSET _u(0x00000150) -#define PROC_PIO_IRQ0_INTE_BITS _u(0x00000fff) -#define PROC_PIO_IRQ0_INTE_RESET _u(0x00000000) -#define PROC_PIO_IRQ0_INTE_WIDTH _u(32) +#define PROC_PIO_IRQ0_INTE_BITS _u(0x00000fff) +#define PROC_PIO_IRQ0_INTE_RESET _u(0x00000000) +#define PROC_PIO_IRQ0_INTE_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM3 // Description : None -#define PROC_PIO_IRQ0_INTE_SM3_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) -#define PROC_PIO_IRQ0_INTE_SM3_MSB _u(11) -#define PROC_PIO_IRQ0_INTE_SM3_LSB _u(11) +#define PROC_PIO_IRQ0_INTE_SM3_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM3_BITS _u(0x00000800) +#define PROC_PIO_IRQ0_INTE_SM3_MSB _u(11) +#define PROC_PIO_IRQ0_INTE_SM3_LSB _u(11) #define PROC_PIO_IRQ0_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM2 // Description : None -#define PROC_PIO_IRQ0_INTE_SM2_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) -#define PROC_PIO_IRQ0_INTE_SM2_MSB _u(10) -#define PROC_PIO_IRQ0_INTE_SM2_LSB _u(10) +#define PROC_PIO_IRQ0_INTE_SM2_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM2_BITS _u(0x00000400) +#define PROC_PIO_IRQ0_INTE_SM2_MSB _u(10) +#define PROC_PIO_IRQ0_INTE_SM2_LSB _u(10) #define PROC_PIO_IRQ0_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM1 // Description : None -#define PROC_PIO_IRQ0_INTE_SM1_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) -#define PROC_PIO_IRQ0_INTE_SM1_MSB _u(9) -#define PROC_PIO_IRQ0_INTE_SM1_LSB _u(9) +#define PROC_PIO_IRQ0_INTE_SM1_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM1_BITS _u(0x00000200) +#define PROC_PIO_IRQ0_INTE_SM1_MSB _u(9) +#define PROC_PIO_IRQ0_INTE_SM1_LSB _u(9) #define PROC_PIO_IRQ0_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM0 // Description : None -#define PROC_PIO_IRQ0_INTE_SM0_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) -#define PROC_PIO_IRQ0_INTE_SM0_MSB _u(8) -#define PROC_PIO_IRQ0_INTE_SM0_LSB _u(8) +#define PROC_PIO_IRQ0_INTE_SM0_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM0_BITS _u(0x00000100) +#define PROC_PIO_IRQ0_INTE_SM0_MSB _u(8) +#define PROC_PIO_IRQ0_INTE_SM0_LSB _u(8) #define PROC_PIO_IRQ0_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM3_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) -#define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) -#define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7) +#define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7) +#define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7) #define PROC_PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM2_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) -#define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) -#define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6) +#define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6) +#define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6) #define PROC_PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM1_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) -#define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) -#define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5) +#define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5) +#define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5) #define PROC_PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM0_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) -#define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) -#define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4) +#define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4) +#define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4) #define PROC_PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) -#define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3) +#define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3) #define PROC_PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) -#define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2) +#define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2) #define PROC_PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) -#define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1) +#define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1) #define PROC_PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) -#define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0) +#define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0) #define PROC_PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_IRQ0_INTF // Description : Interrupt Force for irq0 #define PROC_PIO_IRQ0_INTF_OFFSET _u(0x00000154) -#define PROC_PIO_IRQ0_INTF_BITS _u(0x00000fff) -#define PROC_PIO_IRQ0_INTF_RESET _u(0x00000000) -#define PROC_PIO_IRQ0_INTF_WIDTH _u(32) +#define PROC_PIO_IRQ0_INTF_BITS _u(0x00000fff) +#define PROC_PIO_IRQ0_INTF_RESET _u(0x00000000) +#define PROC_PIO_IRQ0_INTF_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM3 // Description : None -#define PROC_PIO_IRQ0_INTF_SM3_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) -#define PROC_PIO_IRQ0_INTF_SM3_MSB _u(11) -#define PROC_PIO_IRQ0_INTF_SM3_LSB _u(11) +#define PROC_PIO_IRQ0_INTF_SM3_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM3_BITS _u(0x00000800) +#define PROC_PIO_IRQ0_INTF_SM3_MSB _u(11) +#define PROC_PIO_IRQ0_INTF_SM3_LSB _u(11) #define PROC_PIO_IRQ0_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM2 // Description : None -#define PROC_PIO_IRQ0_INTF_SM2_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) -#define PROC_PIO_IRQ0_INTF_SM2_MSB _u(10) -#define PROC_PIO_IRQ0_INTF_SM2_LSB _u(10) +#define PROC_PIO_IRQ0_INTF_SM2_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM2_BITS _u(0x00000400) +#define PROC_PIO_IRQ0_INTF_SM2_MSB _u(10) +#define PROC_PIO_IRQ0_INTF_SM2_LSB _u(10) #define PROC_PIO_IRQ0_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM1 // Description : None -#define PROC_PIO_IRQ0_INTF_SM1_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) -#define PROC_PIO_IRQ0_INTF_SM1_MSB _u(9) -#define PROC_PIO_IRQ0_INTF_SM1_LSB _u(9) +#define PROC_PIO_IRQ0_INTF_SM1_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM1_BITS _u(0x00000200) +#define PROC_PIO_IRQ0_INTF_SM1_MSB _u(9) +#define PROC_PIO_IRQ0_INTF_SM1_LSB _u(9) #define PROC_PIO_IRQ0_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM0 // Description : None -#define PROC_PIO_IRQ0_INTF_SM0_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) -#define PROC_PIO_IRQ0_INTF_SM0_MSB _u(8) -#define PROC_PIO_IRQ0_INTF_SM0_LSB _u(8) +#define PROC_PIO_IRQ0_INTF_SM0_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM0_BITS _u(0x00000100) +#define PROC_PIO_IRQ0_INTF_SM0_MSB _u(8) +#define PROC_PIO_IRQ0_INTF_SM0_LSB _u(8) #define PROC_PIO_IRQ0_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM3_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) -#define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) -#define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7) +#define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7) +#define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7) #define PROC_PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM2_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) -#define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) -#define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6) +#define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6) +#define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6) #define PROC_PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM1_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) -#define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) -#define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5) +#define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5) +#define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5) #define PROC_PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM0_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) -#define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) -#define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4) +#define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4) +#define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4) #define PROC_PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) -#define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3) +#define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3) #define PROC_PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) -#define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2) +#define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2) #define PROC_PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) -#define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1) +#define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1) #define PROC_PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) -#define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0) +#define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0) #define PROC_PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_IRQ0_INTS // Description : Interrupt status after masking & forcing for irq0 #define PROC_PIO_IRQ0_INTS_OFFSET _u(0x00000158) -#define PROC_PIO_IRQ0_INTS_BITS _u(0x00000fff) -#define PROC_PIO_IRQ0_INTS_RESET _u(0x00000000) -#define PROC_PIO_IRQ0_INTS_WIDTH _u(32) +#define PROC_PIO_IRQ0_INTS_BITS _u(0x00000fff) +#define PROC_PIO_IRQ0_INTS_RESET _u(0x00000000) +#define PROC_PIO_IRQ0_INTS_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM3 // Description : None -#define PROC_PIO_IRQ0_INTS_SM3_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) -#define PROC_PIO_IRQ0_INTS_SM3_MSB _u(11) -#define PROC_PIO_IRQ0_INTS_SM3_LSB _u(11) +#define PROC_PIO_IRQ0_INTS_SM3_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM3_BITS _u(0x00000800) +#define PROC_PIO_IRQ0_INTS_SM3_MSB _u(11) +#define PROC_PIO_IRQ0_INTS_SM3_LSB _u(11) #define PROC_PIO_IRQ0_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM2 // Description : None -#define PROC_PIO_IRQ0_INTS_SM2_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) -#define PROC_PIO_IRQ0_INTS_SM2_MSB _u(10) -#define PROC_PIO_IRQ0_INTS_SM2_LSB _u(10) +#define PROC_PIO_IRQ0_INTS_SM2_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM2_BITS _u(0x00000400) +#define PROC_PIO_IRQ0_INTS_SM2_MSB _u(10) +#define PROC_PIO_IRQ0_INTS_SM2_LSB _u(10) #define PROC_PIO_IRQ0_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM1 // Description : None -#define PROC_PIO_IRQ0_INTS_SM1_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) -#define PROC_PIO_IRQ0_INTS_SM1_MSB _u(9) -#define PROC_PIO_IRQ0_INTS_SM1_LSB _u(9) +#define PROC_PIO_IRQ0_INTS_SM1_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM1_BITS _u(0x00000200) +#define PROC_PIO_IRQ0_INTS_SM1_MSB _u(9) +#define PROC_PIO_IRQ0_INTS_SM1_LSB _u(9) #define PROC_PIO_IRQ0_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM0 // Description : None -#define PROC_PIO_IRQ0_INTS_SM0_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) -#define PROC_PIO_IRQ0_INTS_SM0_MSB _u(8) -#define PROC_PIO_IRQ0_INTS_SM0_LSB _u(8) +#define PROC_PIO_IRQ0_INTS_SM0_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM0_BITS _u(0x00000100) +#define PROC_PIO_IRQ0_INTS_SM0_MSB _u(8) +#define PROC_PIO_IRQ0_INTS_SM0_LSB _u(8) #define PROC_PIO_IRQ0_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM3_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) -#define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) -#define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7) +#define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7) +#define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7) #define PROC_PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM2_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) -#define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) -#define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6) +#define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6) +#define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6) #define PROC_PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM1_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) -#define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) -#define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5) +#define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5) +#define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5) #define PROC_PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM0_TXNFULL // Description : None -#define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) -#define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) -#define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4) +#define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4) +#define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4) #define PROC_PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) -#define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3) +#define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3) #define PROC_PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) -#define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2) +#define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2) #define PROC_PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) -#define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1) +#define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1) #define PROC_PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY // Description : None -#define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) -#define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0) +#define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0) #define PROC_PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_IRQ1_INTE // Description : Interrupt Enable for irq1 #define PROC_PIO_IRQ1_INTE_OFFSET _u(0x0000015c) -#define PROC_PIO_IRQ1_INTE_BITS _u(0x00000fff) -#define PROC_PIO_IRQ1_INTE_RESET _u(0x00000000) -#define PROC_PIO_IRQ1_INTE_WIDTH _u(32) +#define PROC_PIO_IRQ1_INTE_BITS _u(0x00000fff) +#define PROC_PIO_IRQ1_INTE_RESET _u(0x00000000) +#define PROC_PIO_IRQ1_INTE_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM3 // Description : None -#define PROC_PIO_IRQ1_INTE_SM3_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) -#define PROC_PIO_IRQ1_INTE_SM3_MSB _u(11) -#define PROC_PIO_IRQ1_INTE_SM3_LSB _u(11) +#define PROC_PIO_IRQ1_INTE_SM3_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM3_BITS _u(0x00000800) +#define PROC_PIO_IRQ1_INTE_SM3_MSB _u(11) +#define PROC_PIO_IRQ1_INTE_SM3_LSB _u(11) #define PROC_PIO_IRQ1_INTE_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM2 // Description : None -#define PROC_PIO_IRQ1_INTE_SM2_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) -#define PROC_PIO_IRQ1_INTE_SM2_MSB _u(10) -#define PROC_PIO_IRQ1_INTE_SM2_LSB _u(10) +#define PROC_PIO_IRQ1_INTE_SM2_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM2_BITS _u(0x00000400) +#define PROC_PIO_IRQ1_INTE_SM2_MSB _u(10) +#define PROC_PIO_IRQ1_INTE_SM2_LSB _u(10) #define PROC_PIO_IRQ1_INTE_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM1 // Description : None -#define PROC_PIO_IRQ1_INTE_SM1_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) -#define PROC_PIO_IRQ1_INTE_SM1_MSB _u(9) -#define PROC_PIO_IRQ1_INTE_SM1_LSB _u(9) +#define PROC_PIO_IRQ1_INTE_SM1_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM1_BITS _u(0x00000200) +#define PROC_PIO_IRQ1_INTE_SM1_MSB _u(9) +#define PROC_PIO_IRQ1_INTE_SM1_LSB _u(9) #define PROC_PIO_IRQ1_INTE_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM0 // Description : None -#define PROC_PIO_IRQ1_INTE_SM0_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) -#define PROC_PIO_IRQ1_INTE_SM0_MSB _u(8) -#define PROC_PIO_IRQ1_INTE_SM0_LSB _u(8) +#define PROC_PIO_IRQ1_INTE_SM0_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM0_BITS _u(0x00000100) +#define PROC_PIO_IRQ1_INTE_SM0_MSB _u(8) +#define PROC_PIO_IRQ1_INTE_SM0_LSB _u(8) #define PROC_PIO_IRQ1_INTE_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM3_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) -#define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) -#define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7) +#define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080) +#define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7) +#define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7) #define PROC_PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM2_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) -#define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) -#define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6) +#define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040) +#define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6) +#define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6) #define PROC_PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM1_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) -#define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) -#define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5) +#define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020) +#define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5) +#define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5) #define PROC_PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM0_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) -#define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) -#define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4) +#define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010) +#define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4) +#define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4) #define PROC_PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) -#define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3) +#define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3) +#define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3) #define PROC_PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) -#define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2) +#define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2) +#define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2) #define PROC_PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) -#define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1) +#define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1) +#define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1) #define PROC_PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) -#define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0) +#define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0) +#define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0) #define PROC_PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_IRQ1_INTF // Description : Interrupt Force for irq1 #define PROC_PIO_IRQ1_INTF_OFFSET _u(0x00000160) -#define PROC_PIO_IRQ1_INTF_BITS _u(0x00000fff) -#define PROC_PIO_IRQ1_INTF_RESET _u(0x00000000) -#define PROC_PIO_IRQ1_INTF_WIDTH _u(32) +#define PROC_PIO_IRQ1_INTF_BITS _u(0x00000fff) +#define PROC_PIO_IRQ1_INTF_RESET _u(0x00000000) +#define PROC_PIO_IRQ1_INTF_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM3 // Description : None -#define PROC_PIO_IRQ1_INTF_SM3_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) -#define PROC_PIO_IRQ1_INTF_SM3_MSB _u(11) -#define PROC_PIO_IRQ1_INTF_SM3_LSB _u(11) +#define PROC_PIO_IRQ1_INTF_SM3_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM3_BITS _u(0x00000800) +#define PROC_PIO_IRQ1_INTF_SM3_MSB _u(11) +#define PROC_PIO_IRQ1_INTF_SM3_LSB _u(11) #define PROC_PIO_IRQ1_INTF_SM3_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM2 // Description : None -#define PROC_PIO_IRQ1_INTF_SM2_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) -#define PROC_PIO_IRQ1_INTF_SM2_MSB _u(10) -#define PROC_PIO_IRQ1_INTF_SM2_LSB _u(10) +#define PROC_PIO_IRQ1_INTF_SM2_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM2_BITS _u(0x00000400) +#define PROC_PIO_IRQ1_INTF_SM2_MSB _u(10) +#define PROC_PIO_IRQ1_INTF_SM2_LSB _u(10) #define PROC_PIO_IRQ1_INTF_SM2_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM1 // Description : None -#define PROC_PIO_IRQ1_INTF_SM1_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) -#define PROC_PIO_IRQ1_INTF_SM1_MSB _u(9) -#define PROC_PIO_IRQ1_INTF_SM1_LSB _u(9) +#define PROC_PIO_IRQ1_INTF_SM1_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM1_BITS _u(0x00000200) +#define PROC_PIO_IRQ1_INTF_SM1_MSB _u(9) +#define PROC_PIO_IRQ1_INTF_SM1_LSB _u(9) #define PROC_PIO_IRQ1_INTF_SM1_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM0 // Description : None -#define PROC_PIO_IRQ1_INTF_SM0_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) -#define PROC_PIO_IRQ1_INTF_SM0_MSB _u(8) -#define PROC_PIO_IRQ1_INTF_SM0_LSB _u(8) +#define PROC_PIO_IRQ1_INTF_SM0_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM0_BITS _u(0x00000100) +#define PROC_PIO_IRQ1_INTF_SM0_MSB _u(8) +#define PROC_PIO_IRQ1_INTF_SM0_LSB _u(8) #define PROC_PIO_IRQ1_INTF_SM0_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM3_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) -#define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) -#define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7) +#define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080) +#define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7) +#define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7) #define PROC_PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM2_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) -#define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) -#define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6) +#define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040) +#define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6) +#define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6) #define PROC_PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM1_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) -#define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) -#define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5) +#define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020) +#define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5) +#define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5) #define PROC_PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM0_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) -#define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) -#define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4) +#define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010) +#define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4) +#define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4) #define PROC_PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) -#define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3) +#define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3) +#define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3) #define PROC_PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) -#define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2) +#define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2) +#define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2) #define PROC_PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) -#define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1) +#define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1) +#define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1) #define PROC_PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) -#define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0) +#define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0) +#define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0) #define PROC_PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_IRQ1_INTS // Description : Interrupt status after masking & forcing for irq1 #define PROC_PIO_IRQ1_INTS_OFFSET _u(0x00000164) -#define PROC_PIO_IRQ1_INTS_BITS _u(0x00000fff) -#define PROC_PIO_IRQ1_INTS_RESET _u(0x00000000) -#define PROC_PIO_IRQ1_INTS_WIDTH _u(32) +#define PROC_PIO_IRQ1_INTS_BITS _u(0x00000fff) +#define PROC_PIO_IRQ1_INTS_RESET _u(0x00000000) +#define PROC_PIO_IRQ1_INTS_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM3 // Description : None -#define PROC_PIO_IRQ1_INTS_SM3_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) -#define PROC_PIO_IRQ1_INTS_SM3_MSB _u(11) -#define PROC_PIO_IRQ1_INTS_SM3_LSB _u(11) +#define PROC_PIO_IRQ1_INTS_SM3_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM3_BITS _u(0x00000800) +#define PROC_PIO_IRQ1_INTS_SM3_MSB _u(11) +#define PROC_PIO_IRQ1_INTS_SM3_LSB _u(11) #define PROC_PIO_IRQ1_INTS_SM3_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM2 // Description : None -#define PROC_PIO_IRQ1_INTS_SM2_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) -#define PROC_PIO_IRQ1_INTS_SM2_MSB _u(10) -#define PROC_PIO_IRQ1_INTS_SM2_LSB _u(10) +#define PROC_PIO_IRQ1_INTS_SM2_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM2_BITS _u(0x00000400) +#define PROC_PIO_IRQ1_INTS_SM2_MSB _u(10) +#define PROC_PIO_IRQ1_INTS_SM2_LSB _u(10) #define PROC_PIO_IRQ1_INTS_SM2_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM1 // Description : None -#define PROC_PIO_IRQ1_INTS_SM1_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) -#define PROC_PIO_IRQ1_INTS_SM1_MSB _u(9) -#define PROC_PIO_IRQ1_INTS_SM1_LSB _u(9) +#define PROC_PIO_IRQ1_INTS_SM1_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM1_BITS _u(0x00000200) +#define PROC_PIO_IRQ1_INTS_SM1_MSB _u(9) +#define PROC_PIO_IRQ1_INTS_SM1_LSB _u(9) #define PROC_PIO_IRQ1_INTS_SM1_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM0 // Description : None -#define PROC_PIO_IRQ1_INTS_SM0_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) -#define PROC_PIO_IRQ1_INTS_SM0_MSB _u(8) -#define PROC_PIO_IRQ1_INTS_SM0_LSB _u(8) +#define PROC_PIO_IRQ1_INTS_SM0_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM0_BITS _u(0x00000100) +#define PROC_PIO_IRQ1_INTS_SM0_MSB _u(8) +#define PROC_PIO_IRQ1_INTS_SM0_LSB _u(8) #define PROC_PIO_IRQ1_INTS_SM0_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM3_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) -#define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) -#define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7) +#define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080) +#define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7) +#define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7) #define PROC_PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM2_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) -#define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) -#define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6) +#define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040) +#define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6) +#define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6) #define PROC_PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM1_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) -#define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) -#define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5) +#define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020) +#define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5) +#define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5) #define PROC_PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM0_TXNFULL // Description : None -#define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) -#define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) -#define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4) +#define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010) +#define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4) +#define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4) #define PROC_PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) -#define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) -#define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3) +#define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008) +#define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3) +#define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3) #define PROC_PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) -#define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) -#define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2) +#define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004) +#define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2) +#define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2) #define PROC_PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) -#define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) -#define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1) +#define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002) +#define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1) +#define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1) #define PROC_PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO" // ----------------------------------------------------------------------------- // Field : PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY // Description : None -#define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) -#define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) -#define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) -#define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) +#define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0) +#define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001) +#define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0) +#define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0) #define PROC_PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_BLOCK_ID // Description : Block Identifier // Hexadecimal representation of "pio2" #define PROC_PIO_BLOCK_ID_OFFSET _u(0x00000168) -#define PROC_PIO_BLOCK_ID_BITS _u(0xffffffff) -#define PROC_PIO_BLOCK_ID_RESET _u(0x70696f32) -#define PROC_PIO_BLOCK_ID_WIDTH _u(32) -#define PROC_PIO_BLOCK_ID_MSB _u(31) -#define PROC_PIO_BLOCK_ID_LSB _u(0) +#define PROC_PIO_BLOCK_ID_BITS _u(0xffffffff) +#define PROC_PIO_BLOCK_ID_RESET _u(0x70696f32) +#define PROC_PIO_BLOCK_ID_WIDTH _u(32) +#define PROC_PIO_BLOCK_ID_MSB _u(31) +#define PROC_PIO_BLOCK_ID_LSB _u(0) #define PROC_PIO_BLOCK_ID_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_INSTANCE_ID // Description : Block Instance Identifier #define PROC_PIO_INSTANCE_ID_OFFSET _u(0x0000016c) -#define PROC_PIO_INSTANCE_ID_BITS _u(0x0000000f) -#define PROC_PIO_INSTANCE_ID_RESET _u(0x00000000) -#define PROC_PIO_INSTANCE_ID_WIDTH _u(32) -#define PROC_PIO_INSTANCE_ID_MSB _u(3) -#define PROC_PIO_INSTANCE_ID_LSB _u(0) +#define PROC_PIO_INSTANCE_ID_BITS _u(0x0000000f) +#define PROC_PIO_INSTANCE_ID_RESET _u(0x00000000) +#define PROC_PIO_INSTANCE_ID_WIDTH _u(32) +#define PROC_PIO_INSTANCE_ID_MSB _u(3) +#define PROC_PIO_INSTANCE_ID_LSB _u(0) #define PROC_PIO_INSTANCE_ID_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_RSTSEQ_AUTO // Description : None #define PROC_PIO_RSTSEQ_AUTO_OFFSET _u(0x00000170) -#define PROC_PIO_RSTSEQ_AUTO_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_AUTO_RESET _u(0x00000001) -#define PROC_PIO_RSTSEQ_AUTO_WIDTH _u(32) +#define PROC_PIO_RSTSEQ_AUTO_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_AUTO_RESET _u(0x00000001) +#define PROC_PIO_RSTSEQ_AUTO_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_RSTSEQ_AUTO_BUSADAPTER // Description : 1 = reset is controlled by the sequencer // 0 = reset is controlled by rstseq_ctrl -#define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_RESET _u(0x1) -#define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_MSB _u(0) -#define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_LSB _u(0) +#define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_RESET _u(0x1) +#define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_MSB _u(0) +#define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_LSB _u(0) #define PROC_PIO_RSTSEQ_AUTO_BUSADAPTER_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_RSTSEQ_PARALLEL // Description : None #define PROC_PIO_RSTSEQ_PARALLEL_OFFSET _u(0x00000174) -#define PROC_PIO_RSTSEQ_PARALLEL_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_PARALLEL_RESET _u(0x00000000) -#define PROC_PIO_RSTSEQ_PARALLEL_WIDTH _u(32) +#define PROC_PIO_RSTSEQ_PARALLEL_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_PARALLEL_RESET _u(0x00000000) +#define PROC_PIO_RSTSEQ_PARALLEL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER // Description : Is this reset parallel (i.e. not part of the sequence) -#define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_RESET _u(0x0) -#define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_MSB _u(0) -#define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_LSB _u(0) +#define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_RESET _u(0x0) +#define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_MSB _u(0) +#define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_LSB _u(0) #define PROC_PIO_RSTSEQ_PARALLEL_BUSADAPTER_ACCESS "RO" // ============================================================================= // Register : PROC_PIO_RSTSEQ_CTRL // Description : None #define PROC_PIO_RSTSEQ_CTRL_OFFSET _u(0x00000178) -#define PROC_PIO_RSTSEQ_CTRL_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_CTRL_RESET _u(0x00000000) -#define PROC_PIO_RSTSEQ_CTRL_WIDTH _u(32) +#define PROC_PIO_RSTSEQ_CTRL_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_CTRL_RESET _u(0x00000000) +#define PROC_PIO_RSTSEQ_CTRL_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_RSTSEQ_CTRL_BUSADAPTER // Description : 1 = keep the reset asserted // 0 = keep the reset deasserted // This is ignored if rstseq_auto=1 -#define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_RESET _u(0x0) -#define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_MSB _u(0) -#define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_LSB _u(0) +#define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_RESET _u(0x0) +#define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_MSB _u(0) +#define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_LSB _u(0) #define PROC_PIO_RSTSEQ_CTRL_BUSADAPTER_ACCESS "RW" // ============================================================================= // Register : PROC_PIO_RSTSEQ_TRIG // Description : None #define PROC_PIO_RSTSEQ_TRIG_OFFSET _u(0x0000017c) -#define PROC_PIO_RSTSEQ_TRIG_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_TRIG_RESET _u(0x00000000) -#define PROC_PIO_RSTSEQ_TRIG_WIDTH _u(32) +#define PROC_PIO_RSTSEQ_TRIG_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_TRIG_RESET _u(0x00000000) +#define PROC_PIO_RSTSEQ_TRIG_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_RSTSEQ_TRIG_BUSADAPTER // Description : Pulses the reset output -#define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_RESET _u(0x0) -#define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_MSB _u(0) -#define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_LSB _u(0) +#define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_RESET _u(0x0) +#define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_MSB _u(0) +#define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_LSB _u(0) #define PROC_PIO_RSTSEQ_TRIG_BUSADAPTER_ACCESS "SC" // ============================================================================= // Register : PROC_PIO_RSTSEQ_DONE // Description : None #define PROC_PIO_RSTSEQ_DONE_OFFSET _u(0x00000180) -#define PROC_PIO_RSTSEQ_DONE_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_DONE_RESET _u(0x00000000) -#define PROC_PIO_RSTSEQ_DONE_WIDTH _u(32) +#define PROC_PIO_RSTSEQ_DONE_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_DONE_RESET _u(0x00000000) +#define PROC_PIO_RSTSEQ_DONE_WIDTH _u(32) // ----------------------------------------------------------------------------- // Field : PROC_PIO_RSTSEQ_DONE_BUSADAPTER // Description : Indicates the current state of the reset -#define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_RESET _u(0x0) -#define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_BITS _u(0x00000001) -#define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_MSB _u(0) -#define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_LSB _u(0) +#define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_RESET _u(0x0) +#define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_BITS _u(0x00000001) +#define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_MSB _u(0) +#define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_LSB _u(0) #define PROC_PIO_RSTSEQ_DONE_BUSADAPTER_ACCESS "RO" // ============================================================================= #endif // HARDWARE_REGS_PROC_PIO_DEFINED diff --git a/src/piolib/include/hardware/timer.h b/src/piolib/include/hardware/timer.h new file mode 100644 index 0000000..06c485b --- /dev/null +++ b/src/piolib/include/hardware/timer.h @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Raspberry Pi Ltd. + * All rights reserved. + */ +#ifndef _HARDWARE_TIMER_H +#define _HARDWARE_TIMER_H + +#include "piolib.h" + +#endif diff --git a/src/piolib/include/pio_platform.h b/src/piolib/include/pio_platform.h index f9ad303..ac35fec 100644 --- a/src/piolib/include/pio_platform.h +++ b/src/piolib/include/pio_platform.h @@ -25,27 +25,17 @@ #define PARAM_ASSERTIONS_DISABLE_ALL 0 #endif -#define PARAM_ASSERTIONS_ENABLED(x) \ - ((PARAM_ASSERTIONS_ENABLED_##x || PARAM_ASSERTIONS_ENABLE_ALL) && \ - !PARAM_ASSERTIONS_DISABLE_ALL) -#define invalid_params_if(x, test) \ - ({ \ - if (PARAM_ASSERTIONS_ENABLED(x)) \ - assert(!(test)); \ - }) -#define valid_params_if(x, test) \ - ({ \ - if (PARAM_ASSERTIONS_ENABLED(x)) \ - assert(test); \ - }) +#define PARAM_ASSERTIONS_ENABLED(x) ((PARAM_ASSERTIONS_ENABLED_ ## x || PARAM_ASSERTIONS_ENABLE_ALL) && !PARAM_ASSERTIONS_DISABLE_ALL) +#define invalid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test));}) +#define valid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(test);}) #define STATIC_ASSERT(cond) static_assert(cond, #cond) #define _u(x) ((uint)(x)) -#define bool_to_bit(x) ((uint) !!(x)) +#define bool_to_bit(x) ((uint)!!(x)) #ifndef count_of -#define count_of(a) (sizeof(a) / sizeof((a)[0])) +#define count_of(a) (sizeof(a)/sizeof((a)[0])) #endif typedef unsigned int uint; diff --git a/src/piolib/include/piolib.h b/src/piolib/include/piolib.h index e03cb7a..c274a53 100644 --- a/src/piolib/include/piolib.h +++ b/src/piolib/include/piolib.h @@ -11,32 +11,39 @@ extern "C" { #endif +#include "pio_platform.h" #include "hardware/clocks.h" #include "hardware/gpio.h" -#include "pio_platform.h" #ifndef PARAM_ASSERTIONS_ENABLED_PIO #define PARAM_ASSERTIONS_ENABLED_PIO 0 #endif -#define PIO_ERR(x) ((PIO)(uintptr_t)(x)) -#define PIO_IS_ERR(x) (((uintptr_t)(x) >= (uintptr_t)-200)) -#define PIO_ERR_VAL(x) ((int)(uintptr_t)(x)) +#define PIO_ERR(x)((PIO)(uintptr_t)(x)) +#define PIO_IS_ERR(x)(((uintptr_t)(x) >= (uintptr_t)-200)) +#define PIO_ERR_VAL(x)((int)(uintptr_t)(x)) -#define PIO_ORIGIN_ANY ((uint)(~0)) -#define PIO_ORIGIN_INVALID PIO_ORIGIN_ANY +#define PIO_ORIGIN_ANY ((uint)(~0)) +#define PIO_ORIGIN_INVALID PIO_ORIGIN_ANY #define pio0 pio_open_helper(0) enum pio_fifo_join { - PIO_FIFO_JOIN_NONE = 0, - PIO_FIFO_JOIN_TX = 1, - PIO_FIFO_JOIN_RX = 2, + PIO_FIFO_JOIN_NONE = 0, + PIO_FIFO_JOIN_TX = 1, + PIO_FIFO_JOIN_RX = 2, }; -enum pio_mov_status_type { STATUS_TX_LESSTHAN = 0, STATUS_RX_LESSTHAN = 1 }; +enum pio_mov_status_type { + STATUS_TX_LESSTHAN = 0, + STATUS_RX_LESSTHAN = 1 +}; -enum pio_xfer_dir { PIO_DIR_TO_SM, PIO_DIR_FROM_SM, PIO_DIR_COUNT }; +enum pio_xfer_dir { + PIO_DIR_TO_SM, + PIO_DIR_FROM_SM, + PIO_DIR_COUNT +}; #ifndef PIOLIB_INTERNALS @@ -53,16 +60,16 @@ enum pio_instr_bits { }; #ifndef NDEBUG -#define _PIO_INVALID_IN_SRC 0x08u +#define _PIO_INVALID_IN_SRC 0x08u #define _PIO_INVALID_OUT_DEST 0x10u #define _PIO_INVALID_SET_DEST 0x20u -#define _PIO_INVALID_MOV_SRC 0x40u +#define _PIO_INVALID_MOV_SRC 0x40u #define _PIO_INVALID_MOV_DEST 0x80u #else -#define _PIO_INVALID_IN_SRC 0u +#define _PIO_INVALID_IN_SRC 0u #define _PIO_INVALID_OUT_DEST 0u #define _PIO_INVALID_SET_DEST 0u -#define _PIO_INVALID_MOV_SRC 0u +#define _PIO_INVALID_MOV_SRC 0u #define _PIO_INVALID_MOV_DEST 0u #endif @@ -71,18 +78,13 @@ enum pio_src_dest { pio_x = 1u, pio_y = 2u, pio_null = 3u | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, - pio_pindirs = - 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, - pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | - _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, - pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | - _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, - pio_pc = - 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, + pio_pindirs = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, + pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, + pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST, + pio_pc = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC, pio_isr = 6u | _PIO_INVALID_SET_DEST, pio_osr = 7u | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST, - pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | - _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, + pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST, }; #endif @@ -113,17 +115,12 @@ struct pio_chip { int (*open_instance)(PIO pio); void (*close_instance)(PIO pio); - int (*pio_sm_config_xfer)(PIO pio, uint sm, uint dir, uint buf_size, - uint buf_count); - int (*pio_sm_xfer_data)(PIO pio, uint sm, uint dir, uint data_bytes, - void *data); + int (*pio_sm_config_xfer)(PIO pio, uint sm, uint dir, uint buf_size, uint buf_count); + int (*pio_sm_xfer_data)(PIO pio, uint sm, uint dir, uint data_bytes, void *data); - bool (*pio_can_add_program_at_offset)(PIO pio, const pio_program_t *program, - uint offset); - uint (*pio_add_program_at_offset)(PIO pio, const pio_program_t *program, - uint offset); - bool (*pio_remove_program)(PIO pio, const pio_program_t *program, - uint loaded_offset); + bool (*pio_can_add_program_at_offset)(PIO pio, const pio_program_t *program, uint offset); + uint (*pio_add_program_at_offset)(PIO pio, const pio_program_t *program, uint offset); + bool (*pio_remove_program)(PIO pio, const pio_program_t *program, uint loaded_offset); bool (*pio_clear_instruction_memory)(PIO pio); uint (*pio_encode_delay)(PIO pio, uint cycles); uint (*pio_encode_sideset)(PIO pio, uint sideset_bit_count, uint value); @@ -138,18 +135,14 @@ struct pio_chip { uint (*pio_encode_jmp_not_osre)(PIO pio, uint addr); uint (*pio_encode_wait_gpio)(PIO pio, bool polarity, uint gpio); uint (*pio_encode_wait_pin)(PIO pio, bool polarity, uint pin); - uint (*pio_encode_wait_irq)(PIO pio, bool polarity, bool relative, - uint irq); + uint (*pio_encode_wait_irq)(PIO pio, bool polarity, bool relative, uint irq); uint (*pio_encode_in)(PIO pio, enum pio_src_dest src, uint count); uint (*pio_encode_out)(PIO pio, enum pio_src_dest dest, uint count); uint (*pio_encode_push)(PIO pio, bool if_full, bool block); uint (*pio_encode_pull)(PIO pio, bool if_empty, bool block); - uint (*pio_encode_mov)(PIO pio, enum pio_src_dest dest, - enum pio_src_dest src); - uint (*pio_encode_mov_not)(PIO pio, enum pio_src_dest dest, - enum pio_src_dest src); - uint (*pio_encode_mov_reverse)(PIO pio, enum pio_src_dest dest, - enum pio_src_dest src); + uint (*pio_encode_mov)(PIO pio, enum pio_src_dest dest, enum pio_src_dest src); + uint (*pio_encode_mov_not)(PIO pio, enum pio_src_dest dest, enum pio_src_dest src); + uint (*pio_encode_mov_reverse)(PIO pio, enum pio_src_dest dest, enum pio_src_dest src); uint (*pio_encode_irq_set)(PIO pio, bool relative, uint irq); uint (*pio_encode_irq_wait)(PIO pio, bool relative, uint irq); uint (*pio_encode_irq_clear)(PIO pio, bool relative, uint irq); @@ -162,21 +155,16 @@ struct pio_chip { bool (*pio_sm_unclaim)(PIO pio, uint sm); bool (*pio_sm_is_claimed)(PIO pio, uint sm); - void (*pio_sm_init)(PIO pio, uint sm, uint initial_pc, - const pio_sm_config *config); + void (*pio_sm_init)(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config); void (*pio_sm_set_config)(PIO pio, uint sm, const pio_sm_config *config); void (*pio_sm_exec)(PIO pio, uint sm, uint instr, bool blocking); void (*pio_sm_clear_fifos)(PIO pio, uint sm); - void (*pio_sm_set_clkdiv_int_frac)(PIO pio, uint sm, uint16_t div_int, - uint8_t div_frac); + void (*pio_sm_set_clkdiv_int_frac)(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac); void (*pio_sm_set_clkdiv)(PIO pio, uint sm, float div); void (*pio_sm_set_pins)(PIO pio, uint sm, uint32_t pin_values); - void (*pio_sm_set_pins_with_mask)(PIO pio, uint sm, uint32_t pin_values, - uint32_t pin_mask); - void (*pio_sm_set_pindirs_with_mask)(PIO pio, uint sm, uint32_t pin_dirs, - uint32_t pin_mask); - void (*pio_sm_set_consecutive_pindirs)(PIO pio, uint sm, uint pin_base, - uint pin_count, bool is_out); + void (*pio_sm_set_pins_with_mask)(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask); + void (*pio_sm_set_pindirs_with_mask)(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask); + void (*pio_sm_set_consecutive_pindirs)(PIO pio, uint sm, uint pin_base, uint pin_count, bool is_out); void (*pio_sm_set_enabled)(PIO pio, uint sm, bool enabled); void (*pio_sm_set_enabled_mask)(PIO pio, uint32_t mask, bool enabled); void (*pio_sm_restart)(PIO pio, uint sm); @@ -196,34 +184,23 @@ struct pio_chip { void (*pio_sm_drain_tx_fifo)(PIO pio, uint sm); pio_sm_config (*pio_get_default_sm_config)(PIO pio); - void (*smc_set_out_pins)(PIO pio, pio_sm_config *c, uint out_base, - uint out_count); - void (*smc_set_set_pins)(PIO pio, pio_sm_config *c, uint set_base, - uint set_count); + void (*smc_set_out_pins)(PIO pio, pio_sm_config *c, uint out_base, uint out_count); + void (*smc_set_set_pins)(PIO pio, pio_sm_config *c, uint set_base, uint set_count); void (*smc_set_in_pins)(PIO pio, pio_sm_config *c, uint in_base); void (*smc_set_sideset_pins)(PIO pio, pio_sm_config *c, uint sideset_base); - void (*smc_set_sideset)(PIO pio, pio_sm_config *c, uint bit_count, - bool optional, bool pindirs); - void (*smc_set_clkdiv_int_frac)(PIO pio, pio_sm_config *c, uint16_t div_int, - uint8_t div_frac); + void (*smc_set_sideset)(PIO pio, pio_sm_config *c, uint bit_count, bool optional, bool pindirs); + void (*smc_set_clkdiv_int_frac)(PIO pio, pio_sm_config *c, uint16_t div_int, uint8_t div_frac); void (*smc_set_clkdiv)(PIO pio, pio_sm_config *c, float div); - void (*smc_set_wrap)(PIO pio, pio_sm_config *c, uint wrap_target, - uint wrap); + void (*smc_set_wrap)(PIO pio, pio_sm_config *c, uint wrap_target, uint wrap); void (*smc_set_jmp_pin)(PIO pio, pio_sm_config *c, uint pin); - void (*smc_set_in_shift)(PIO pio, pio_sm_config *c, bool shift_right, - bool autopush, uint push_threshold); - void (*smc_set_out_shift)(PIO pio, pio_sm_config *c, bool shift_right, - bool autopull, uint pull_threshold); - void (*smc_set_fifo_join)(PIO pio, pio_sm_config *c, - enum pio_fifo_join join); - void (*smc_set_out_special)(PIO pio, pio_sm_config *c, bool sticky, - bool has_enable_pin, uint enable_pin_index); - void (*smc_set_mov_status)(PIO pio, pio_sm_config *c, - enum pio_mov_status_type status_sel, - uint status_n); + void (*smc_set_in_shift)(PIO pio, pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold); + void (*smc_set_out_shift)(PIO pio, pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold); + void (*smc_set_fifo_join)(PIO pio, pio_sm_config *c, enum pio_fifo_join join); + void (*smc_set_out_special)(PIO pio, pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index); + void (*smc_set_mov_status)(PIO pio, pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n); uint32_t (*clock_get_hz)(PIO pio, enum clock_index clk_index); - void (*pio_gpio_init)(PIO pio, uint pin); + void (*pio_gpio_init)(PIO, uint pin); void (*gpio_init)(PIO pio, uint gpio); void (*gpio_set_function)(PIO pio, uint gpio, enum gpio_function fn); void (*gpio_set_pulls)(PIO pio, uint gpio, bool up, bool down); @@ -231,8 +208,7 @@ struct pio_chip { void (*gpio_set_inover)(PIO pio, uint gpio, uint value); void (*gpio_set_oeover)(PIO pio, uint gpio, uint value); void (*gpio_set_input_enabled)(PIO pio, uint gpio, bool enabled); - void (*gpio_set_drive_strength)(PIO pio, uint gpio, - enum gpio_drive_strength drive); + void (*gpio_set_drive_strength)(PIO pio, uint gpio, enum gpio_drive_strength drive); }; struct pio_instance { @@ -252,58 +228,74 @@ int pio_get_index(PIO pio); void pio_select(PIO pio); PIO pio_get_current(void); -static inline void pio_error(PIO pio, const char *msg) { +static inline void pio_error(PIO pio, const char *msg) +{ pio->error = true; if (pio->errors_are_fatal) pio_panic(msg); } -static inline bool pio_get_error(PIO pio) { return pio->error; } +static inline bool pio_get_error(PIO pio) +{ + return pio->error; +} -static inline void pio_clear_error(PIO pio) { pio->error = false; } +static inline void pio_clear_error(PIO pio) +{ + pio->error = false; +} -static inline void pio_enable_fatal_errors(PIO pio, bool enable) { +static inline void pio_enable_fatal_errors(PIO pio, bool enable) +{ pio->errors_are_fatal = enable; } -static inline uint pio_get_sm_count(PIO pio) { return pio->chip->sm_count; } +static inline uint pio_get_sm_count(PIO pio) +{ + return pio->chip->sm_count; +} -static inline uint pio_get_instruction_count(PIO pio) { +static inline uint pio_get_instruction_count(PIO pio) +{ return pio->chip->instr_count; } -static inline uint pio_get_fifo_depth(PIO pio) { return pio->chip->fifo_depth; } +static inline uint pio_get_fifo_depth(PIO pio) +{ + return pio->chip->fifo_depth; +} -static inline void check_pio_param(__unused PIO pio) { +static inline void check_pio_param(__unused PIO pio) +{ valid_params_if(PIO, pio_get_index(pio) >= 0); } -static inline int pio_sm_config_xfer(PIO pio, uint sm, uint dir, uint buf_size, - uint buf_count) { +static inline int pio_sm_config_xfer(PIO pio, uint sm, uint dir, uint buf_size, uint buf_count) +{ check_pio_param(pio); return pio->chip->pio_sm_config_xfer(pio, sm, dir, buf_size, buf_count); } -static inline int pio_sm_xfer_data(PIO pio, uint sm, uint dir, uint data_bytes, - void *data) { +static inline int pio_sm_xfer_data(PIO pio, uint sm, uint dir, uint data_bytes, void *data) +{ check_pio_param(pio); return pio->chip->pio_sm_xfer_data(pio, sm, dir, data_bytes, data); } -static inline bool pio_can_add_program(PIO pio, const pio_program_t *program) { +static inline bool pio_can_add_program(PIO pio, const pio_program_t *program) +{ check_pio_param(pio); - return pio->chip->pio_can_add_program_at_offset(pio, program, - PIO_ORIGIN_ANY); + return pio->chip->pio_can_add_program_at_offset(pio, program, PIO_ORIGIN_ANY); } -static inline bool pio_can_add_program_at_offset(PIO pio, - const pio_program_t *program, - uint offset) { +static inline bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) +{ check_pio_param(pio); return pio->chip->pio_can_add_program_at_offset(pio, program, offset); } -static inline uint pio_add_program(PIO pio, const pio_program_t *program) { +static inline uint pio_add_program(PIO pio, const pio_program_t *program) +{ uint offset; check_pio_param(pio); offset = pio->chip->pio_add_program_at_offset(pio, program, PIO_ORIGIN_ANY); @@ -312,492 +304,548 @@ static inline uint pio_add_program(PIO pio, const pio_program_t *program) { return offset; } -static inline void -pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) { +static inline void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) +{ check_pio_param(pio); - if (pio->chip->pio_add_program_at_offset(pio, program, offset) == - PIO_ORIGIN_INVALID) + if (pio->chip->pio_add_program_at_offset(pio, program, offset) == PIO_ORIGIN_INVALID) pio_error(pio, "No program space"); } -static inline void pio_remove_program(PIO pio, const pio_program_t *program, - uint loaded_offset) { +static inline void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset) +{ check_pio_param(pio); if (!pio->chip->pio_remove_program(pio, program, loaded_offset)) pio_error(pio, "Failed to remove program"); } -static inline void pio_clear_instruction_memory(PIO pio) { +static inline void pio_clear_instruction_memory(PIO pio) +{ check_pio_param(pio); if (!pio->chip->pio_clear_instruction_memory(pio)) pio_error(pio, "Failed to clear instruction memory"); } -static inline uint pio_encode_delay(uint cycles) { +static inline uint pio_encode_delay(uint cycles) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_delay(pio, cycles); } -static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) { +static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_sideset(pio, sideset_bit_count, value); } -static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) { +static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_sideset_opt(pio, sideset_bit_count, value); } -static inline uint pio_encode_jmp(uint addr) { +static inline uint pio_encode_jmp(uint addr) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_jmp(pio, addr); } -static inline uint pio_encode_jmp_not_x(uint addr) { +static inline uint pio_encode_jmp_not_x(uint addr) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_jmp_not_x(pio, addr); } -static inline uint pio_encode_jmp_x_dec(uint addr) { +static inline uint pio_encode_jmp_x_dec(uint addr) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_jmp_x_dec(pio, addr); } -static inline uint pio_encode_jmp_not_y(uint addr) { +static inline uint pio_encode_jmp_not_y(uint addr) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_jmp_not_y(pio, addr); } -static inline uint pio_encode_jmp_y_dec(uint addr) { +static inline uint pio_encode_jmp_y_dec(uint addr) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_jmp_y_dec(pio, addr); } -static inline uint pio_encode_jmp_x_ne_y(uint addr) { +static inline uint pio_encode_jmp_x_ne_y(uint addr) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_jmp_x_ne_y(pio, addr); } -static inline uint pio_encode_jmp_pin(uint addr) { +static inline uint pio_encode_jmp_pin(uint addr) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_jmp_pin(pio, addr); } -static inline uint pio_encode_jmp_not_osre(uint addr) { +static inline uint pio_encode_jmp_not_osre(uint addr) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_jmp_not_osre(pio, addr); } -static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) { +static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_wait_gpio(pio, polarity, gpio); } -static inline uint pio_encode_wait_pin(bool polarity, uint pin) { +static inline uint pio_encode_wait_pin(bool polarity, uint pin) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_wait_pin(pio, polarity, pin); } -static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) { +static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_wait_irq(pio, polarity, relative, irq); } -static inline uint pio_encode_in(enum pio_src_dest src, uint count) { +static inline uint pio_encode_in(enum pio_src_dest src, uint count) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_in(pio, src, count); } -static inline uint pio_encode_out(enum pio_src_dest dest, uint count) { +static inline uint pio_encode_out(enum pio_src_dest dest, uint count) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_out(pio, dest, count); } -static inline uint pio_encode_push(bool if_full, bool block) { +static inline uint pio_encode_push(bool if_full, bool block) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_push(pio, if_full, block); } -static inline uint pio_encode_pull(bool if_empty, bool block) { +static inline uint pio_encode_pull(bool if_empty, bool block) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_pull(pio, if_empty, block); } -static inline uint pio_encode_mov(enum pio_src_dest dest, - enum pio_src_dest src) { +static inline uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_mov(pio, dest, src); } -static inline uint pio_encode_mov_not(enum pio_src_dest dest, - enum pio_src_dest src) { +static inline uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_mov_not(pio, dest, src); } -static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, - enum pio_src_dest src) { +static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_mov_reverse(pio, dest, src); } -static inline uint pio_encode_irq_set(bool relative, uint irq) { +static inline uint pio_encode_irq_set(bool relative, uint irq) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_irq_set(pio, relative, irq); } -static inline uint pio_encode_irq_wait(bool relative, uint irq) { +static inline uint pio_encode_irq_wait(bool relative, uint irq) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_irq_wait(pio, relative, irq); } -static inline uint pio_encode_irq_clear(bool relative, uint irq) { +static inline uint pio_encode_irq_clear(bool relative, uint irq) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_irq_clear(pio, relative, irq); } -static inline uint pio_encode_set(enum pio_src_dest dest, uint value) { +static inline uint pio_encode_set(enum pio_src_dest dest, uint value) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_set(pio, dest, value); } -static inline uint pio_encode_nop(void) { +static inline uint pio_encode_nop(void) +{ PIO pio = pio_get_current(); return pio->chip->pio_encode_nop(pio); } -static inline void pio_sm_claim(PIO pio, uint sm) { +static inline void pio_sm_claim(PIO pio, uint sm) +{ check_pio_param(pio); if (!pio->chip->pio_sm_claim(pio, sm)) pio_error(pio, "Failed to claim SM"); } -static inline void pio_claim_sm_mask(PIO pio, uint mask) { +static inline void pio_claim_sm_mask(PIO pio, uint mask) +{ check_pio_param(pio); if (!pio->chip->pio_sm_claim_mask(pio, mask)) pio_error(pio, "Failed to claim masked SMs"); } -static inline void pio_sm_unclaim(PIO pio, uint sm) { +static inline void pio_sm_unclaim(PIO pio, uint sm) +{ check_pio_param(pio); pio->chip->pio_sm_unclaim(pio, sm); } -static inline int pio_claim_unused_sm(PIO pio, bool required) { +static inline int pio_claim_unused_sm(PIO pio, bool required) +{ check_pio_param(pio); return pio->chip->pio_sm_claim_unused(pio, required); } -static inline bool pio_sm_is_claimed(PIO pio, uint sm) { +static inline bool pio_sm_is_claimed(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_is_claimed(pio, sm); } -static inline void pio_sm_init(PIO pio, uint sm, uint initial_pc, - const pio_sm_config *config) { +static inline void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) +{ check_pio_param(pio); pio->chip->pio_sm_init(pio, sm, initial_pc, config); } -static inline void pio_sm_set_config(PIO pio, uint sm, - const pio_sm_config *config) { +static inline void pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) +{ check_pio_param(pio); pio->chip->pio_sm_set_config(pio, sm, config); } -static inline void pio_sm_exec(PIO pio, uint sm, uint instr) { +static inline void pio_sm_exec(PIO pio, uint sm, uint instr) +{ check_pio_param(pio); pio->chip->pio_sm_exec(pio, sm, instr, false); } -static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) { +static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) +{ check_pio_param(pio); pio->chip->pio_sm_exec(pio, sm, instr, true); } -static inline void pio_sm_clear_fifos(PIO pio, uint sm) { +static inline void pio_sm_clear_fifos(PIO pio, uint sm) +{ check_pio_param(pio); pio->chip->pio_sm_clear_fifos(pio, sm); } -static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, - uint16_t div_int, - uint8_t div_frac) { +static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) +{ check_pio_param(pio); pio->chip->pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac); } -static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) { +static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) +{ check_pio_param(pio); pio->chip->pio_sm_set_clkdiv(pio, sm, div); } -static inline void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values) { +static inline void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values) +{ check_pio_param(pio); pio->chip->pio_sm_set_pins(pio, sm, pin_values); } -static inline void pio_sm_set_pins_with_mask(PIO pio, uint sm, - uint32_t pin_values, - uint32_t pin_mask) { +static inline void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask) +{ check_pio_param(pio); pio->chip->pio_sm_set_pins_with_mask(pio, sm, pin_values, pin_mask); } -static inline void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, - uint32_t pin_dirs, - uint32_t pin_mask) { +static inline void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask) +{ check_pio_param(pio); pio->chip->pio_sm_set_pindirs_with_mask(pio, sm, pin_dirs, pin_mask); } -static inline void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, - uint pin_base, uint pin_count, - bool is_out) { +static inline void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin_base, uint pin_count, bool is_out) +{ check_pio_param(pio); - pio->chip->pio_sm_set_consecutive_pindirs(pio, sm, pin_base, pin_count, - is_out); + pio->chip->pio_sm_set_consecutive_pindirs(pio, sm, pin_base, pin_count, is_out); } -static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { +static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) +{ check_pio_param(pio); pio->chip->pio_sm_set_enabled(pio, sm, enabled); } -static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, - bool enabled) { +static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) +{ check_pio_param(pio); pio->chip->pio_sm_set_enabled_mask(pio, mask, enabled); } -static inline void pio_sm_restart(PIO pio, uint sm) { +static inline void pio_sm_restart(PIO pio, uint sm) +{ check_pio_param(pio); pio->chip->pio_sm_restart(pio, sm); } -static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) { +static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) +{ check_pio_param(pio); pio->chip->pio_sm_restart_mask(pio, mask); } -static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) { +static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) +{ check_pio_param(pio); pio->chip->pio_sm_clkdiv_restart(pio, sm); } -static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) { +static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) +{ check_pio_param(pio); pio->chip->pio_sm_clkdiv_restart_mask(pio, mask); } -static inline void pio_enable_sm_in_sync_mask(PIO pio, uint32_t mask) { +static inline void pio_enable_sm_in_sync_mask(PIO pio, uint32_t mask) +{ check_pio_param(pio); pio->chip->pio_sm_enable_sync(pio, mask); }; -static inline void pio_sm_set_dmactrl(PIO pio, uint sm, bool is_tx, - uint32_t ctrl) { +static inline void pio_sm_set_dmactrl(PIO pio, uint sm, bool is_tx, uint32_t ctrl) +{ check_pio_param(pio); pio->chip->pio_sm_set_dmactrl(pio, sm, is_tx, ctrl); }; -static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) { +static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_is_rx_fifo_empty(pio, sm); } -static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) { +static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_is_rx_fifo_full(pio, sm); } -static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) { +static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_get_rx_fifo_level(pio, sm); } -static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) { +static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_is_tx_fifo_empty(pio, sm); } -static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) { +static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_is_tx_fifo_full(pio, sm); } -static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) { +static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_get_tx_fifo_level(pio, sm); } -static inline void pio_sm_drain_tx_fifo(PIO pio, uint sm) { +static inline void pio_sm_drain_tx_fifo(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_drain_tx_fifo(pio, sm); } -static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) { +static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) +{ check_pio_param(pio); pio->chip->pio_sm_put(pio, sm, data, false); } -static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) { +static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) +{ check_pio_param(pio); pio->chip->pio_sm_put(pio, sm, data, true); } -static inline uint32_t pio_sm_get(PIO pio, uint sm) { +static inline uint32_t pio_sm_get(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_get(pio, sm, false); } -static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) { +static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) +{ check_pio_param(pio); return pio->chip->pio_sm_get(pio, sm, true); } -static inline pio_sm_config pio_get_default_sm_config_for_pio(PIO pio) { +static inline pio_sm_config pio_get_default_sm_config_for_pio(PIO pio) +{ check_pio_param(pio); return pio->chip->pio_get_default_sm_config(pio); } -static inline pio_sm_config pio_get_default_sm_config(void) { +static inline pio_sm_config pio_get_default_sm_config(void) +{ PIO pio = pio_get_current(); return pio->chip->pio_get_default_sm_config(pio); } -static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, - uint out_count) { +static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) +{ PIO pio = pio_get_current(); pio->chip->smc_set_out_pins(pio, c, out_base, out_count); } -static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, - uint set_count) { +static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) +{ PIO pio = pio_get_current(); pio->chip->smc_set_set_pins(pio, c, set_base, set_count); } -static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) { +static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) +{ PIO pio = pio_get_current(); pio->chip->smc_set_in_pins(pio, c, in_base); } -static inline void sm_config_set_sideset_pins(pio_sm_config *c, - uint sideset_base) { +static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) +{ PIO pio = pio_get_current(); pio->chip->smc_set_sideset_pins(pio, c, sideset_base); } -static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, - bool optional, bool pindirs) { +static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) +{ PIO pio = pio_get_current(); pio->chip->smc_set_sideset(pio, c, bit_count, optional, pindirs); } -static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, - uint16_t div_int, - uint8_t div_frac) { +static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) +{ PIO pio = pio_get_current(); pio->chip->smc_set_clkdiv_int_frac(pio, c, div_int, div_frac); } -static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) { +static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) +{ PIO pio = pio_get_current(); pio->chip->smc_set_clkdiv(pio, c, div); } -static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, - uint wrap) { +static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) +{ PIO pio = pio_get_current(); pio->chip->smc_set_wrap(pio, c, wrap_target, wrap); } -static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) { +static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) +{ PIO pio = pio_get_current(); pio->chip->smc_set_jmp_pin(pio, c, pin); } -static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, - bool autopush, uint push_threshold) { +static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) +{ PIO pio = pio_get_current(); pio->chip->smc_set_in_shift(pio, c, shift_right, autopush, push_threshold); } -static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, - bool autopull, uint pull_threshold) { +static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) +{ PIO pio = pio_get_current(); pio->chip->smc_set_out_shift(pio, c, shift_right, autopull, pull_threshold); } -static inline void sm_config_set_fifo_join(pio_sm_config *c, - enum pio_fifo_join join) { +static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) +{ PIO pio = pio_get_current(); pio->chip->smc_set_fifo_join(pio, c, join); } -static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, - bool has_enable_pin, - uint enable_pin_index) { +static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index) +{ PIO pio = pio_get_current(); - pio->chip->smc_set_out_special(pio, c, sticky, has_enable_pin, - enable_pin_index); + pio->chip->smc_set_out_special(pio, c, sticky, has_enable_pin, enable_pin_index); } -static inline void sm_config_set_mov_status(pio_sm_config *c, - enum pio_mov_status_type status_sel, - uint status_n) { +static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) +{ PIO pio = pio_get_current(); pio->chip->smc_set_mov_status(pio, c, status_sel, status_n); } -static inline void pio_gpio_init(PIO pio, uint pin) { +static inline void pio_gpio_init(PIO pio, uint pin) +{ check_pio_param(pio); pio->chip->pio_gpio_init(pio, pin); } -static inline uint32_t clock_get_hz(enum clock_index clk_index) { +static inline uint32_t clock_get_hz(enum clock_index clk_index) +{ PIO pio = pio_get_current(); return pio->chip->clock_get_hz(pio, clk_index); } -static inline void gpio_init(uint gpio) { +static inline void gpio_init(uint gpio) +{ PIO pio = pio_get_current(); pio->chip->gpio_init(pio, gpio); } -static inline void gpio_set_function(uint gpio, enum gpio_function fn) { +static inline void gpio_set_function(uint gpio, enum gpio_function fn) +{ PIO pio = pio_get_current(); pio->chip->gpio_set_function(pio, gpio, fn); } -static inline void gpio_set_pulls(uint gpio, bool up, bool down) { + +static inline void gpio_set_pulls(uint gpio, bool up, bool down) +{ PIO pio = pio_get_current(); pio->chip->gpio_set_pulls(pio, gpio, up, down); } -static inline void gpio_set_outover(uint gpio, uint value) { +static inline void gpio_set_outover(uint gpio, uint value) +{ PIO pio = pio_get_current(); pio->chip->gpio_set_outover(pio, gpio, value); } -static inline void gpio_set_inover(uint gpio, uint value) { +static inline void gpio_set_inover(uint gpio, uint value) +{ PIO pio = pio_get_current(); pio->chip->gpio_set_inover(pio, gpio, value); } -static inline void gpio_set_oeover(uint gpio, uint value) { +static inline void gpio_set_oeover(uint gpio, uint value) +{ PIO pio = pio_get_current(); pio->chip->gpio_set_oeover(pio, gpio, value); } -static inline void gpio_set_input_enabled(uint gpio, bool enabled) { +static inline void gpio_set_input_enabled(uint gpio, bool enabled) +{ PIO pio = pio_get_current(); pio->chip->gpio_set_input_enabled(pio, gpio, enabled); } -static inline void gpio_set_drive_strength(uint gpio, - enum gpio_drive_strength drive) { +static inline void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) +{ PIO pio = pio_get_current(); pio->chip->gpio_set_drive_strength(pio, gpio, drive); } @@ -814,7 +862,9 @@ static inline void gpio_disable_pulls(uint gpio) { gpio_set_pulls(gpio, false, false); } -static inline void stdio_init_all(void) {} +static inline void stdio_init_all(void) +{ +} void sleep_us(uint64_t us); diff --git a/src/piolib/include/piolib_priv.h b/src/piolib/include/piolib_priv.h index 45be81b..9d13b4b 100644 --- a/src/piolib/include/piolib_priv.h +++ b/src/piolib/include/piolib_priv.h @@ -9,8 +9,8 @@ #include "pio_platform.h" -#define DECLARE_PIO_CHIP(chip) \ - const PIO_CHIP_T *__ptr_##chip __attribute__((section("piochips"))) \ - __attribute__((used)) = &chip +#define DECLARE_PIO_CHIP(chip) \ + const PIO_CHIP_T *__ptr_ ## chip __attribute__ ((section ("piochips"))) __attribute__ ((used)) = \ + &chip #endif diff --git a/src/piolib/include/rp1_pio_if.h b/src/piolib/include/rp1_pio_if.h index eceb4ab..224b4f8 100644 --- a/src/piolib/include/rp1_pio_if.h +++ b/src/piolib/include/rp1_pio_if.h @@ -8,16 +8,16 @@ #include -#define RP1_PIO_INSTRUCTION_COUNT 32 -#define RP1_PIO_SM_COUNT 4 -#define RP1_PIO_GPIO_COUNT 28 -#define RP1_GPIO_FUNC_PIO 7 +#define RP1_PIO_INSTRUCTION_COUNT 32 +#define RP1_PIO_SM_COUNT 4 +#define RP1_PIO_GPIO_COUNT 28 +#define RP1_GPIO_FUNC_PIO 7 -#define RP1_PIO_ORIGIN_ANY ((uint16_t)(~0)) +#define RP1_PIO_ORIGIN_ANY ((uint16_t)(~0)) -#define RP1_PIO_DIR_TO_SM 0 -#define RP1_PIO_DIR_FROM_SM 1 -#define RP1_PIO_DIR_COUNT 2 +#define RP1_PIO_DIR_TO_SM 0 +#define RP1_PIO_DIR_FROM_SM 1 +#define RP1_PIO_DIR_COUNT 2 typedef struct { uint32_t clkdiv; @@ -125,12 +125,12 @@ struct rp1_pio_sm_set_dmactrl_args { }; struct rp1_pio_sm_fifo_state_args { - uint16_t sm; - uint8_t tx; - uint8_t rsvd; - uint16_t level; /* OUT */ - uint8_t empty; /* OUT */ - uint8_t full; /* OUT */ + uint16_t sm; + uint8_t tx; + uint8_t rsvd; + uint16_t level; /* OUT */ + uint8_t empty; /* OUT */ + uint8_t full; /* OUT */ }; struct rp1_gpio_init_args { @@ -160,10 +160,25 @@ struct rp1_pio_sm_config_xfer_args { uint16_t buf_count; }; +struct rp1_pio_sm_config_xfer32_args { + uint16_t sm; + uint16_t dir; + uint32_t buf_size; + uint32_t buf_count; +}; + struct rp1_pio_sm_xfer_data_args { uint16_t sm; uint16_t dir; uint16_t data_bytes; + uint16_t rsvd; + void *data; +}; + +struct rp1_pio_sm_xfer_data32_args { + uint16_t sm; + uint16_t dir; + uint32_t data_bytes; void *data; }; @@ -175,75 +190,47 @@ struct rp1_access_hw_args { #define PIO_IOC_MAGIC 102 -#define PIO_IOC_SM_CONFIG_XFER \ - _IOW(PIO_IOC_MAGIC, 0, struct rp1_pio_sm_config_xfer_args) -#define PIO_IOC_SM_XFER_DATA \ - _IOW(PIO_IOC_MAGIC, 1, struct rp1_pio_sm_xfer_data_args) - -#ifdef CONFIG_COMPAT -// XXX #define PIO_IOC_SM_XFER_DATA32 _IOW(PIO_IOC_MAGIC, 2, struct -// pio_sm_xfer_data_args) -#endif +#define PIO_IOC_SM_CONFIG_XFER _IOW(PIO_IOC_MAGIC, 0, struct rp1_pio_sm_config_xfer_args) +#define PIO_IOC_SM_XFER_DATA _IOW(PIO_IOC_MAGIC, 1, struct rp1_pio_sm_xfer_data_args) +#define PIO_IOC_SM_XFER_DATA32 _IOW(PIO_IOC_MAGIC, 2, struct rp1_pio_sm_xfer_data32_args) +#define PIO_IOC_SM_CONFIG_XFER32 _IOW(PIO_IOC_MAGIC, 3, struct rp1_pio_sm_config_xfer32_args) #define PIO_IOC_READ_HW _IOW(PIO_IOC_MAGIC, 8, struct rp1_access_hw_args) #define PIO_IOC_WRITE_HW _IOW(PIO_IOC_MAGIC, 9, struct rp1_access_hw_args) -#define PIO_IOC_CAN_ADD_PROGRAM \ - _IOW(PIO_IOC_MAGIC, 10, struct rp1_pio_add_program_args) -#define PIO_IOC_ADD_PROGRAM \ - _IOW(PIO_IOC_MAGIC, 11, struct rp1_pio_add_program_args) -#define PIO_IOC_REMOVE_PROGRAM \ - _IOW(PIO_IOC_MAGIC, 12, struct rp1_pio_remove_program_args) +#define PIO_IOC_CAN_ADD_PROGRAM _IOW(PIO_IOC_MAGIC, 10, struct rp1_pio_add_program_args) +#define PIO_IOC_ADD_PROGRAM _IOW(PIO_IOC_MAGIC, 11, struct rp1_pio_add_program_args) +#define PIO_IOC_REMOVE_PROGRAM _IOW(PIO_IOC_MAGIC, 12, struct rp1_pio_remove_program_args) #define PIO_IOC_CLEAR_INSTR_MEM _IO(PIO_IOC_MAGIC, 13) #define PIO_IOC_SM_CLAIM _IOW(PIO_IOC_MAGIC, 20, struct rp1_pio_sm_claim_args) #define PIO_IOC_SM_UNCLAIM _IOW(PIO_IOC_MAGIC, 21, struct rp1_pio_sm_claim_args) -#define PIO_IOC_SM_IS_CLAIMED \ - _IOW(PIO_IOC_MAGIC, 22, struct rp1_pio_sm_claim_args) +#define PIO_IOC_SM_IS_CLAIMED _IOW(PIO_IOC_MAGIC, 22, struct rp1_pio_sm_claim_args) #define PIO_IOC_SM_INIT _IOW(PIO_IOC_MAGIC, 30, struct rp1_pio_sm_init_args) -#define PIO_IOC_SM_SET_CONFIG \ - _IOW(PIO_IOC_MAGIC, 31, struct rp1_pio_sm_set_config_args) +#define PIO_IOC_SM_SET_CONFIG _IOW(PIO_IOC_MAGIC, 31, struct rp1_pio_sm_set_config_args) #define PIO_IOC_SM_EXEC _IOW(PIO_IOC_MAGIC, 32, struct rp1_pio_sm_exec_args) -#define PIO_IOC_SM_CLEAR_FIFOS \ - _IOW(PIO_IOC_MAGIC, 33, struct rp1_pio_sm_clear_fifos_args) -#define PIO_IOC_SM_SET_CLKDIV \ - _IOW(PIO_IOC_MAGIC, 34, struct rp1_pio_sm_set_clkdiv_args) -#define PIO_IOC_SM_SET_PINS \ - _IOW(PIO_IOC_MAGIC, 35, struct rp1_pio_sm_set_pins_args) -#define PIO_IOC_SM_SET_PINDIRS \ - _IOW(PIO_IOC_MAGIC, 36, struct rp1_pio_sm_set_pindirs_args) -#define PIO_IOC_SM_SET_ENABLED \ - _IOW(PIO_IOC_MAGIC, 37, struct rp1_pio_sm_set_enabled_args) -#define PIO_IOC_SM_RESTART \ - _IOW(PIO_IOC_MAGIC, 38, struct rp1_pio_sm_restart_args) -#define PIO_IOC_SM_CLKDIV_RESTART \ - _IOW(PIO_IOC_MAGIC, 39, struct rp1_pio_sm_restart_args) -#define PIO_IOC_SM_ENABLE_SYNC \ - _IOW(PIO_IOC_MAGIC, 40, struct rp1_pio_sm_enable_sync_args) +#define PIO_IOC_SM_CLEAR_FIFOS _IOW(PIO_IOC_MAGIC, 33, struct rp1_pio_sm_clear_fifos_args) +#define PIO_IOC_SM_SET_CLKDIV _IOW(PIO_IOC_MAGIC, 34, struct rp1_pio_sm_set_clkdiv_args) +#define PIO_IOC_SM_SET_PINS _IOW(PIO_IOC_MAGIC, 35, struct rp1_pio_sm_set_pins_args) +#define PIO_IOC_SM_SET_PINDIRS _IOW(PIO_IOC_MAGIC, 36, struct rp1_pio_sm_set_pindirs_args) +#define PIO_IOC_SM_SET_ENABLED _IOW(PIO_IOC_MAGIC, 37, struct rp1_pio_sm_set_enabled_args) +#define PIO_IOC_SM_RESTART _IOW(PIO_IOC_MAGIC, 38, struct rp1_pio_sm_restart_args) +#define PIO_IOC_SM_CLKDIV_RESTART _IOW(PIO_IOC_MAGIC, 39, struct rp1_pio_sm_restart_args) +#define PIO_IOC_SM_ENABLE_SYNC _IOW(PIO_IOC_MAGIC, 40, struct rp1_pio_sm_enable_sync_args) #define PIO_IOC_SM_PUT _IOW(PIO_IOC_MAGIC, 41, struct rp1_pio_sm_put_args) #define PIO_IOC_SM_GET _IOWR(PIO_IOC_MAGIC, 42, struct rp1_pio_sm_get_args) -#define PIO_IOC_SM_SET_DMACTRL \ - _IOW(PIO_IOC_MAGIC, 43, struct rp1_pio_sm_set_dmactrl_args) -#define PIO_IOC_SM_FIFO_STATE \ - _IOW(PIO_IOC_MAGIC, 44, struct rp1_pio_sm_fifo_state_args) -#define PIO_IOC_SM_DRAIN_TX \ - _IOW(PIO_IOC_MAGIC, 45, struct rp1_pio_sm_clear_fifos_args) +#define PIO_IOC_SM_SET_DMACTRL _IOW(PIO_IOC_MAGIC, 43, struct rp1_pio_sm_set_dmactrl_args) +#define PIO_IOC_SM_FIFO_STATE _IOW(PIO_IOC_MAGIC, 44, struct rp1_pio_sm_fifo_state_args) +#define PIO_IOC_SM_DRAIN_TX _IOW(PIO_IOC_MAGIC, 45, struct rp1_pio_sm_clear_fifos_args) #define PIO_IOC_GPIO_INIT _IOW(PIO_IOC_MAGIC, 50, struct rp1_gpio_init_args) -#define PIO_IOC_GPIO_SET_FUNCTION \ - _IOW(PIO_IOC_MAGIC, 51, struct rp1_gpio_set_function_args) -#define PIO_IOC_GPIO_SET_PULLS \ - _IOW(PIO_IOC_MAGIC, 52, struct rp1_gpio_set_pulls_args) -#define PIO_IOC_GPIO_SET_OUTOVER \ - _IOW(PIO_IOC_MAGIC, 53, struct rp1_gpio_set_args) -#define PIO_IOC_GPIO_SET_INOVER \ - _IOW(PIO_IOC_MAGIC, 54, struct rp1_gpio_set_args) -#define PIO_IOC_GPIO_SET_OEOVER \ - _IOW(PIO_IOC_MAGIC, 55, struct rp1_gpio_set_args) -#define PIO_IOC_GPIO_SET_INPUT_ENABLED \ - _IOW(PIO_IOC_MAGIC, 56, struct rp1_gpio_set_args) -#define PIO_IOC_GPIO_SET_DRIVE_STRENGTH \ - _IOW(PIO_IOC_MAGIC, 57, struct rp1_gpio_set_args) +#define PIO_IOC_GPIO_SET_FUNCTION _IOW(PIO_IOC_MAGIC, 51, struct rp1_gpio_set_function_args) +#define PIO_IOC_GPIO_SET_PULLS _IOW(PIO_IOC_MAGIC, 52, struct rp1_gpio_set_pulls_args) +#define PIO_IOC_GPIO_SET_OUTOVER _IOW(PIO_IOC_MAGIC, 53, struct rp1_gpio_set_args) +#define PIO_IOC_GPIO_SET_INOVER _IOW(PIO_IOC_MAGIC, 54, struct rp1_gpio_set_args) +#define PIO_IOC_GPIO_SET_OEOVER _IOW(PIO_IOC_MAGIC, 55, struct rp1_gpio_set_args) +#define PIO_IOC_GPIO_SET_INPUT_ENABLED _IOW(PIO_IOC_MAGIC, 56, struct rp1_gpio_set_args) +#define PIO_IOC_GPIO_SET_DRIVE_STRENGTH _IOW(PIO_IOC_MAGIC, 57, struct rp1_gpio_set_args) #endif diff --git a/src/piolib/pio_rp1.c b/src/piolib/pio_rp1.c index 88cd366..108a50c 100644 --- a/src/piolib/pio_rp1.c +++ b/src/piolib/pio_rp1.c @@ -69,36 +69,38 @@ #undef pio_encode_set #undef pio_encode_nop +#include "piolib.h" +#include "piolib_priv.h" #include "hardware/gpio.h" #include "hardware/pio.h" #include "hardware/regs/proc_pio.h" -#include "piolib.h" -#include "piolib_priv.h" #include "rp1_pio_if.h" typedef struct rp1_pio_handle { struct pio_instance base; const char *devname; int fd; -} * RP1_PIO; +} *RP1_PIO; -#define smc_to_rp1(_config, _c) \ - rp1_pio_sm_config *_c = (rp1_pio_sm_config *)_config +#define smc_to_rp1(_config, _c) rp1_pio_sm_config *_c = (rp1_pio_sm_config*)_config #define GPIOS_MASK ((1 << RP1_PIO_GPIO_COUNT) - 1) STATIC_ASSERT(sizeof(rp1_pio_sm_config) <= sizeof(pio_sm_config)); -static inline void check_sm_param(__unused uint sm) { +static inline void check_sm_param(__unused uint sm) +{ valid_params_if(PIO, sm < RP1_PIO_SM_COUNT); } -static inline void check_sm_mask(__unused uint mask) { +static inline void check_sm_mask(__unused uint mask) +{ valid_params_if(PIO, mask < (1u << RP1_PIO_SM_COUNT)); } -static pio_sm_config rp1_pio_get_default_sm_config(PIO pio) { - pio_sm_config c = {{0}}; +static pio_sm_config rp1_pio_get_default_sm_config(PIO) +{ + pio_sm_config c = { { 0 } }; sm_config_set_clkdiv_int_frac(&c, 1, 0); sm_config_set_wrap(&c, 0, 31); sm_config_set_in_shift(&c, true, false, 32); @@ -106,115 +108,138 @@ static pio_sm_config rp1_pio_get_default_sm_config(PIO pio) { return c; } -static uint rp1_pio_encode_delay(PIO pio, uint cycles) { +static uint rp1_pio_encode_delay(PIO, uint cycles) +{ return _pio_encode_delay(cycles); } -static uint rp1_pio_encode_sideset(PIO pio, uint sideset_bit_count, - uint value) { +static uint rp1_pio_encode_sideset(PIO, uint sideset_bit_count, uint value) +{ return _pio_encode_sideset(sideset_bit_count, value); } -static uint rp1_pio_encode_sideset_opt(PIO pio, uint sideset_bit_count, - uint value) { +static uint rp1_pio_encode_sideset_opt(PIO, uint sideset_bit_count, uint value) +{ return _pio_encode_sideset_opt(sideset_bit_count, value); } -static uint rp1_pio_encode_jmp(PIO pio, uint addr) { +static uint rp1_pio_encode_jmp(PIO, uint addr) +{ return _pio_encode_jmp(addr); } -static uint rp1_pio_encode_jmp_not_x(PIO pio, uint addr) { +static uint rp1_pio_encode_jmp_not_x(PIO, uint addr) +{ return _pio_encode_jmp_not_x(addr); } -static uint rp1_pio_encode_jmp_x_dec(PIO pio, uint addr) { +static uint rp1_pio_encode_jmp_x_dec(PIO, uint addr) +{ return _pio_encode_jmp_x_dec(addr); } -static uint rp1_pio_encode_jmp_not_y(PIO pio, uint addr) { +static uint rp1_pio_encode_jmp_not_y(PIO, uint addr) +{ return _pio_encode_jmp_not_y(addr); } -static uint rp1_pio_encode_jmp_y_dec(PIO pio, uint addr) { +static uint rp1_pio_encode_jmp_y_dec(PIO, uint addr) +{ return _pio_encode_jmp_y_dec(addr); } -static uint rp1_pio_encode_jmp_x_ne_y(PIO pio, uint addr) { +static uint rp1_pio_encode_jmp_x_ne_y(PIO, uint addr) +{ return _pio_encode_jmp_x_ne_y(addr); } -static uint rp1_pio_encode_jmp_pin(PIO pio, uint addr) { +static uint rp1_pio_encode_jmp_pin(PIO, uint addr) +{ return _pio_encode_jmp_pin(addr); } -static uint rp1_pio_encode_jmp_not_osre(PIO pio, uint addr) { +static uint rp1_pio_encode_jmp_not_osre(PIO, uint addr) +{ return _pio_encode_jmp_not_osre(addr); } -static uint rp1_pio_encode_wait_gpio(PIO pio, bool polarity, uint gpio) { +static uint rp1_pio_encode_wait_gpio(PIO, bool polarity, uint gpio) +{ return _pio_encode_wait_gpio(polarity, gpio); } -static uint rp1_pio_encode_wait_pin(PIO pio, bool polarity, uint pin) { +static uint rp1_pio_encode_wait_pin(PIO, bool polarity, uint pin) +{ return _pio_encode_wait_pin(polarity, pin); } -static uint rp1_pio_encode_wait_irq(PIO pio, bool polarity, bool relative, - uint irq) { +static uint rp1_pio_encode_wait_irq(PIO, bool polarity, bool relative, uint irq) +{ return _pio_encode_wait_irq(polarity, relative, irq); } -static uint rp1_pio_encode_in(PIO pio, enum pio_src_dest src, uint count) { +static uint rp1_pio_encode_in(PIO, enum pio_src_dest src, uint count) +{ return _pio_encode_in(src, count); } -static uint rp1_pio_encode_out(PIO pio, enum pio_src_dest dest, uint count) { +static uint rp1_pio_encode_out(PIO, enum pio_src_dest dest, uint count) +{ return _pio_encode_out(dest, count); } -static uint rp1_pio_encode_push(PIO pio, bool if_full, bool block) { +static uint rp1_pio_encode_push(PIO, bool if_full, bool block) +{ return _pio_encode_push(if_full, block); } -static uint rp1_pio_encode_pull(PIO pio, bool if_empty, bool block) { +static uint rp1_pio_encode_pull(PIO, bool if_empty, bool block) +{ return _pio_encode_pull(if_empty, block); } -static uint rp1_pio_encode_mov(PIO pio, enum pio_src_dest dest, - enum pio_src_dest src) { +static uint rp1_pio_encode_mov(PIO, enum pio_src_dest dest, enum pio_src_dest src) +{ return _pio_encode_mov(dest, src); } -static uint rp1_pio_encode_mov_not(PIO pio, enum pio_src_dest dest, - enum pio_src_dest src) { +static uint rp1_pio_encode_mov_not(PIO, enum pio_src_dest dest, enum pio_src_dest src) +{ return _pio_encode_mov_not(dest, src); } -static uint rp1_pio_encode_mov_reverse(PIO pio, enum pio_src_dest dest, - enum pio_src_dest src) { +static uint rp1_pio_encode_mov_reverse(PIO, enum pio_src_dest dest, enum pio_src_dest src) +{ return _pio_encode_mov_reverse(dest, src); } -static uint rp1_pio_encode_irq_set(PIO pio, bool relative, uint irq) { +static uint rp1_pio_encode_irq_set(PIO, bool relative, uint irq) +{ return _pio_encode_irq_set(relative, irq); } -static uint rp1_pio_encode_irq_wait(PIO pio, bool relative, uint irq) { +static uint rp1_pio_encode_irq_wait(PIO, bool relative, uint irq) +{ return _pio_encode_irq_wait(relative, irq); } -static uint rp1_pio_encode_irq_clear(PIO pio, bool relative, uint irq) { +static uint rp1_pio_encode_irq_clear(PIO, bool relative, uint irq) +{ return _pio_encode_irq_clear(relative, irq); } -static uint rp1_pio_encode_set(PIO pio, enum pio_src_dest dest, uint value) { +static uint rp1_pio_encode_set(PIO, enum pio_src_dest dest, uint value) +{ return _pio_encode_set(dest, value); } -static uint rp1_pio_encode_nop(PIO pio) { return _pio_encode_nop(); } +static uint rp1_pio_encode_nop(PIO) +{ + return _pio_encode_nop(); +} -static int rp1_ioctl(PIO pio, int request, void *args) { +static int rp1_ioctl(PIO pio, int request, void *args) +{ RP1_PIO rp = (RP1_PIO)pio; int err = ioctl(rp->fd, request, args); switch (err) { @@ -228,148 +253,148 @@ static int rp1_ioctl(PIO pio, int request, void *args) { return err; } -static int rp1_pio_sm_config_xfer(PIO pio, uint sm, uint dir, uint buf_size, - uint buf_count) { - struct rp1_pio_sm_config_xfer_args args = { - .sm = sm, .dir = dir, .buf_size = buf_size, .buf_count = buf_count}; +static int rp1_pio_sm_config_xfer(PIO pio, uint sm, uint dir, uint buf_size, uint buf_count) +{ + struct rp1_pio_sm_config_xfer_args args = { .sm = sm, .dir = dir, .buf_size = buf_size, .buf_count = buf_count }; + struct rp1_pio_sm_config_xfer32_args args32 = { .sm = sm, .dir = dir, .buf_size = buf_size, .buf_count = buf_count }; int err; check_sm_param(sm); - err = rp1_ioctl(pio, PIO_IOC_SM_CONFIG_XFER, &args); - return (err > 0); + if (buf_size > 0xffff || buf_count > 0xffff) + err = rp1_ioctl(pio, PIO_IOC_SM_CONFIG_XFER32, &args32); + else + err = rp1_ioctl(pio, PIO_IOC_SM_CONFIG_XFER, &args); + return err; } -static int rp1_pio_sm_xfer_data(PIO pio, uint sm, uint dir, uint data_bytes, - void *data) { - struct rp1_pio_sm_xfer_data_args args = { - .sm = sm, .dir = dir, .data_bytes = data_bytes, .data = data}; +static int rp1_pio_sm_xfer_data(PIO pio, uint sm, uint dir, uint data_bytes, void *data) +{ + struct rp1_pio_sm_xfer_data_args args = { .sm = sm, .dir = dir, .data_bytes = data_bytes, .rsvd = 0, .data = data }; + struct rp1_pio_sm_xfer_data32_args args32 = { .sm = sm, .dir = dir, .data_bytes = data_bytes, .data = data }; int err; check_sm_param(sm); - err = rp1_ioctl(pio, PIO_IOC_SM_XFER_DATA, &args); - return (err > 0); + if (data_bytes > 0xffff) + err = rp1_ioctl(pio, PIO_IOC_SM_XFER_DATA32, &args32); + else + err = rp1_ioctl(pio, PIO_IOC_SM_XFER_DATA, &args); + return err; } -static bool rp1_pio_can_add_program_at_offset(PIO pio, - const pio_program_t *program, - uint offset) { - struct rp1_pio_add_program_args args = {.num_instrs = program->length, - .origin = program->origin}; +static bool rp1_pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) +{ + struct rp1_pio_add_program_args args = { .num_instrs = program->length, .origin = program->origin }; int err; - valid_params_if(PIO, offset < RP1_PIO_INSTRUCTION_COUNT || - offset == PIO_ORIGIN_ANY); + valid_params_if(PIO, offset < RP1_PIO_INSTRUCTION_COUNT || offset == PIO_ORIGIN_ANY); valid_params_if(PIO, program->length <= RP1_PIO_INSTRUCTION_COUNT); - valid_params_if(PIO, - offset + program->length <= RP1_PIO_INSTRUCTION_COUNT || - offset == PIO_ORIGIN_ANY); + valid_params_if(PIO, offset + program->length <= RP1_PIO_INSTRUCTION_COUNT || offset == PIO_ORIGIN_ANY); if (program->origin >= 0 && (uint)program->origin != offset) return false; if (offset != PIO_ORIGIN_ANY) args.origin = offset; - memcpy(args.instrs, program->instructions, - program->length * sizeof(uint16_t)); + memcpy(args.instrs, program->instructions, program->length * sizeof(uint16_t)); err = rp1_ioctl(pio, PIO_IOC_CAN_ADD_PROGRAM, &args); return (err > 0); } -static uint rp1_pio_add_program_at_offset(PIO pio, const pio_program_t *program, - uint offset) { - struct rp1_pio_add_program_args args = {.num_instrs = program->length, - .origin = program->origin}; - valid_params_if(PIO, offset < RP1_PIO_INSTRUCTION_COUNT || - offset == PIO_ORIGIN_ANY); +static uint rp1_pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) +{ + struct rp1_pio_add_program_args args = { .num_instrs = program->length, .origin = program->origin }; + valid_params_if(PIO, offset < RP1_PIO_INSTRUCTION_COUNT || offset == PIO_ORIGIN_ANY); valid_params_if(PIO, program->length <= RP1_PIO_INSTRUCTION_COUNT); - valid_params_if(PIO, - offset + program->length <= RP1_PIO_INSTRUCTION_COUNT || - offset == PIO_ORIGIN_ANY); + valid_params_if(PIO, offset + program->length <= RP1_PIO_INSTRUCTION_COUNT || offset == PIO_ORIGIN_ANY); if (offset != PIO_ORIGIN_ANY) args.origin = offset; - memcpy(args.instrs, program->instructions, - program->length * sizeof(uint16_t)); + memcpy(args.instrs, program->instructions, program->length * sizeof(uint16_t)); return rp1_ioctl(pio, PIO_IOC_ADD_PROGRAM, &args); } -static bool rp1_pio_remove_program(PIO pio, const pio_program_t *program, - uint offset) { - struct rp1_pio_remove_program_args args = {.num_instrs = program->length, - .origin = offset}; +static bool rp1_pio_remove_program(PIO pio, const pio_program_t *program, uint offset) +{ + struct rp1_pio_remove_program_args args = { .num_instrs = program->length, .origin = offset }; valid_params_if(PIO, offset < RP1_PIO_INSTRUCTION_COUNT); valid_params_if(PIO, offset + program->length <= RP1_PIO_INSTRUCTION_COUNT); return !rp1_ioctl(pio, PIO_IOC_REMOVE_PROGRAM, &args); } -static bool rp1_pio_clear_instruction_memory(PIO pio) { +static bool rp1_pio_clear_instruction_memory(PIO pio) +{ return !rp1_ioctl(pio, PIO_IOC_CLEAR_INSTR_MEM, NULL); } -static bool rp1_pio_sm_claim(PIO pio, uint sm) { - struct rp1_pio_sm_claim_args args = {.mask = (1 << sm)}; +static bool rp1_pio_sm_claim(PIO pio, uint sm) +{ + struct rp1_pio_sm_claim_args args = { .mask = (1 << sm) }; check_sm_param(sm); return (rp1_ioctl(pio, PIO_IOC_SM_CLAIM, &args) >= 0); } -static bool rp1_pio_sm_claim_mask(PIO pio, uint mask) { - struct rp1_pio_sm_claim_args args = {.mask = mask}; +static bool rp1_pio_sm_claim_mask(PIO pio, uint mask) +{ + struct rp1_pio_sm_claim_args args = { .mask = mask }; valid_params_if(PIO, !!mask); check_sm_mask(mask); return (rp1_ioctl(pio, PIO_IOC_SM_CLAIM, &args) >= 0); } -static bool rp1_pio_sm_unclaim(PIO pio, uint sm) { - struct rp1_pio_sm_claim_args args = {.mask = (1 << sm)}; +static bool rp1_pio_sm_unclaim(PIO pio, uint sm) +{ + struct rp1_pio_sm_claim_args args = { .mask = (1 << sm) }; check_sm_param(sm); return !rp1_ioctl(pio, PIO_IOC_SM_UNCLAIM, &args); } -static int rp1_pio_sm_claim_unused(PIO pio, bool required) { - struct rp1_pio_sm_claim_args args = {.mask = 0}; +static int rp1_pio_sm_claim_unused(PIO pio, bool required) +{ + struct rp1_pio_sm_claim_args args = { .mask = 0 }; int sm = rp1_ioctl(pio, PIO_IOC_SM_CLAIM, &args); if (sm < 0 && required) pio_panic("No PIO state machines are available"); return sm; } -static bool rp1_pio_sm_is_claimed(PIO pio, uint sm) { - struct rp1_pio_sm_claim_args args = {.mask = (1 << sm)}; +static bool rp1_pio_sm_is_claimed(PIO pio, uint sm) +{ + struct rp1_pio_sm_claim_args args = { .mask = (1 << sm) }; check_sm_param(sm); int err = rp1_ioctl(pio, PIO_IOC_SM_IS_CLAIMED, &args); return (err > 0); } -static void rp1_pio_sm_init(PIO pio, uint sm, uint initial_pc, - const pio_sm_config *config) { +static void rp1_pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) +{ smc_to_rp1(config, c); - struct rp1_pio_sm_init_args args = { - .sm = sm, .initial_pc = initial_pc, .config = *c}; + struct rp1_pio_sm_init_args args = { .sm = sm, .initial_pc = initial_pc, .config = *c }; valid_params_if(PIO, initial_pc < RP1_PIO_INSTRUCTION_COUNT); (void)rp1_ioctl(pio, PIO_IOC_SM_INIT, &args); } -static void rp1_pio_sm_set_config(PIO pio, uint sm, - const pio_sm_config *config) { +static void rp1_pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) +{ smc_to_rp1(config, c); - struct rp1_pio_sm_init_args args = {.sm = sm, .config = *c}; + struct rp1_pio_sm_init_args args = { .sm = sm, .config = *c }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_SET_CONFIG, &args); } -static void rp1_pio_sm_exec(PIO pio, uint sm, uint instr, bool blocking) { - struct rp1_pio_sm_exec_args args = { - .sm = sm, .instr = instr, .blocking = blocking}; +static void rp1_pio_sm_exec(PIO pio, uint sm, uint instr, bool blocking) +{ + struct rp1_pio_sm_exec_args args = { .sm = sm, .instr = instr, .blocking = blocking }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_EXEC, &args); } -static void rp1_pio_sm_clear_fifos(PIO pio, uint sm) { - struct rp1_pio_sm_clear_fifos_args args = {.sm = sm}; +static void rp1_pio_sm_clear_fifos(PIO pio, uint sm) +{ + struct rp1_pio_sm_clear_fifos_args args = { .sm = sm }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_CLEAR_FIFOS, &args); } -static void rp1_pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, - uint8_t *div_frac) { +static void rp1_pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) +{ valid_params_if(PIO, div >= 1 && div <= 65536); *div_int = (uint16_t)div; if (*div_int == 0) { @@ -379,17 +404,17 @@ static void rp1_pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, } } -static void rp1_pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, - uint8_t div_frac) { - struct rp1_pio_sm_set_clkdiv_args args = { - .sm = sm, .div_int = div_int, .div_frac = div_frac}; +static void rp1_pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) +{ + struct rp1_pio_sm_set_clkdiv_args args = { .sm = sm, .div_int = div_int, .div_frac = div_frac }; check_sm_param(sm); invalid_params_if(PIO, div_int == 0 && div_frac != 0); (void)rp1_ioctl(pio, PIO_IOC_SM_SET_CLKDIV, &args); } -static void rp1_pio_sm_set_clkdiv(PIO pio, uint sm, float div) { +static void rp1_pio_sm_set_clkdiv(PIO pio, uint sm, float div) +{ uint16_t div_int; uint8_t div_frac; @@ -398,28 +423,25 @@ static void rp1_pio_sm_set_clkdiv(PIO pio, uint sm, float div) { rp1_pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac); } -static void rp1_pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values) { - struct rp1_pio_sm_set_pins_args args = { - .sm = sm, .values = pin_values, .mask = GPIOS_MASK}; +static void rp1_pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values) +{ + struct rp1_pio_sm_set_pins_args args = { .sm = sm, .values = pin_values, .mask = GPIOS_MASK }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_SET_PINS, &args); } -static void rp1_pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, - uint32_t pin_mask) { - struct rp1_pio_sm_set_pins_args args = { - .sm = sm, .values = pin_values, .mask = pin_mask}; +static void rp1_pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask) +{ + struct rp1_pio_sm_set_pins_args args = { .sm = sm, .values = pin_values, .mask = pin_mask }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_SET_PINS, &args); } -static void rp1_pio_sm_set_pindirs_with_mask(PIO pio, uint sm, - uint32_t pin_dirs, - uint32_t pin_mask) { - struct rp1_pio_sm_set_pindirs_args args = { - .sm = sm, .dirs = pin_dirs, .mask = pin_mask}; +static void rp1_pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask) +{ + struct rp1_pio_sm_set_pindirs_args args = { .sm = sm, .dirs = pin_dirs, .mask = pin_mask }; check_sm_param(sm); valid_params_if(PIO, (pin_dirs & GPIOS_MASK) == pin_dirs); @@ -427,302 +449,298 @@ static void rp1_pio_sm_set_pindirs_with_mask(PIO pio, uint sm, (void)rp1_ioctl(pio, PIO_IOC_SM_SET_PINDIRS, &args); } -static void rp1_pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin_base, - uint pin_count, bool is_out) { +static void rp1_pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin_base, uint pin_count, bool is_out) +{ uint32_t mask = ((1 << pin_count) - 1) << pin_base; - struct rp1_pio_sm_set_pindirs_args args = { - .sm = sm, .dirs = is_out ? mask : 0, .mask = mask}; + struct rp1_pio_sm_set_pindirs_args args = { .sm = sm, .dirs = is_out ? mask : 0, .mask = mask }; check_sm_param(sm); valid_params_if(PIO, pin_base < RP1_PIO_GPIO_COUNT && - pin_count < RP1_PIO_GPIO_COUNT && - (pin_base + pin_count) < RP1_PIO_GPIO_COUNT); + pin_count < RP1_PIO_GPIO_COUNT && + (pin_base + pin_count) < RP1_PIO_GPIO_COUNT); (void)rp1_ioctl(pio, PIO_IOC_SM_SET_PINDIRS, &args); } -static void rp1_pio_sm_set_enabled(PIO pio, uint sm, bool enabled) { - struct rp1_pio_sm_set_enabled_args args = {.mask = (1 << sm), - .enable = enabled}; +static void rp1_pio_sm_set_enabled(PIO pio, uint sm, bool enabled) +{ + struct rp1_pio_sm_set_enabled_args args = { .mask = (1 << sm), .enable = enabled }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_SET_ENABLED, &args); } -static void rp1_pio_sm_set_enabled_mask(PIO pio, uint32_t mask, bool enabled) { - struct rp1_pio_sm_set_enabled_args args = {.mask = (uint16_t)mask, - .enable = enabled}; +static void rp1_pio_sm_set_enabled_mask(PIO pio, uint32_t mask, bool enabled) +{ + struct rp1_pio_sm_set_enabled_args args = { .mask = (uint16_t)mask, .enable = enabled }; check_sm_mask(mask); (void)rp1_ioctl(pio, PIO_IOC_SM_SET_ENABLED, &args); } -static void rp1_pio_sm_restart(PIO pio, uint sm) { - struct rp1_pio_sm_restart_args args = {.mask = (1 << sm)}; +static void rp1_pio_sm_restart(PIO pio, uint sm) +{ + struct rp1_pio_sm_restart_args args = { .mask = (1 << sm) }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_RESTART, &args); } -static void rp1_pio_sm_restart_mask(PIO pio, uint32_t mask) { - struct rp1_pio_sm_restart_args args = {.mask = (uint16_t)mask}; +static void rp1_pio_sm_restart_mask(PIO pio, uint32_t mask) +{ + struct rp1_pio_sm_restart_args args = { .mask = (uint16_t)mask }; check_sm_mask(mask); (void)rp1_ioctl(pio, PIO_IOC_SM_RESTART, &args); } -static void rp1_pio_sm_clkdiv_restart(PIO pio, uint sm) { - struct rp1_pio_sm_restart_args args = {.mask = (1 << sm)}; +static void rp1_pio_sm_clkdiv_restart(PIO pio, uint sm) +{ + struct rp1_pio_sm_restart_args args = { .mask = (1 << sm) }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_CLKDIV_RESTART, &args); } -static void rp1_pio_sm_clkdiv_restart_mask(PIO pio, uint32_t mask) { - struct rp1_pio_sm_restart_args args = {.mask = (uint16_t)mask}; +static void rp1_pio_sm_clkdiv_restart_mask(PIO pio, uint32_t mask) +{ + struct rp1_pio_sm_restart_args args = { .mask = (uint16_t)mask }; check_sm_mask(mask); (void)rp1_ioctl(pio, PIO_IOC_SM_CLKDIV_RESTART, &args); } -static void rp1_pio_sm_enable_sync(PIO pio, uint32_t mask) { - struct rp1_pio_sm_enable_sync_args args = {.mask = (uint16_t)mask}; +static void rp1_pio_sm_enable_sync(PIO pio, uint32_t mask) +{ + struct rp1_pio_sm_enable_sync_args args = { .mask = (uint16_t)mask }; check_sm_mask(mask); (void)rp1_ioctl(pio, PIO_IOC_SM_ENABLE_SYNC, &args); } -static void rp1_pio_sm_put(PIO pio, uint sm, uint32_t data, bool blocking) { - struct rp1_pio_sm_put_args args = { - .sm = (uint16_t)sm, .blocking = blocking, .data = data}; +static void rp1_pio_sm_put(PIO pio, uint sm, uint32_t data, bool blocking) +{ + struct rp1_pio_sm_put_args args = { .sm = (uint16_t)sm, .blocking = blocking, .data = data }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_PUT, &args); } -static uint32_t rp1_pio_sm_get(PIO pio, uint sm, bool blocking) { - struct rp1_pio_sm_get_args args = {.sm = (uint16_t)sm, - .blocking = blocking}; +static uint32_t rp1_pio_sm_get(PIO pio, uint sm, bool blocking) +{ + struct rp1_pio_sm_get_args args = { .sm = (uint16_t)sm, .blocking = blocking }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_GET, &args); return args.data; } -static void rp1_pio_sm_set_dmactrl(PIO pio, uint sm, bool is_tx, - uint32_t ctrl) { - struct rp1_pio_sm_set_dmactrl_args args = { - .sm = sm, .is_tx = is_tx, .ctrl = ctrl}; +static void rp1_pio_sm_set_dmactrl(PIO pio, uint sm, bool is_tx, uint32_t ctrl) +{ + struct rp1_pio_sm_set_dmactrl_args args = { .sm = sm, .is_tx = is_tx, .ctrl = ctrl }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_SET_DMACTRL, &args); } -static bool rp1_pio_sm_is_rx_fifo_empty(PIO pio, uint sm) { - struct rp1_pio_sm_fifo_state_args args = {.sm = sm, .tx = false}; +static bool rp1_pio_sm_is_rx_fifo_empty(PIO pio, uint sm) +{ + struct rp1_pio_sm_fifo_state_args args = { .sm = sm, .tx = false }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_FIFO_STATE, &args); return args.empty; } -static bool rp1_pio_sm_is_rx_fifo_full(PIO pio, uint sm) { - struct rp1_pio_sm_fifo_state_args args = {.sm = sm, .tx = false}; +static bool rp1_pio_sm_is_rx_fifo_full(PIO pio, uint sm) +{ + struct rp1_pio_sm_fifo_state_args args = { .sm = sm, .tx = false }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_FIFO_STATE, &args); return args.full; } -static uint rp1_pio_sm_get_rx_fifo_level(PIO pio, uint sm) { - struct rp1_pio_sm_fifo_state_args args = {.sm = sm, .tx = false}; +static uint rp1_pio_sm_get_rx_fifo_level(PIO pio, uint sm) +{ + struct rp1_pio_sm_fifo_state_args args = { .sm = sm, .tx = false }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_FIFO_STATE, &args); return args.level; } -static bool rp1_pio_sm_is_tx_fifo_empty(PIO pio, uint sm) { - struct rp1_pio_sm_fifo_state_args args = {.sm = sm, .tx = true}; +static bool rp1_pio_sm_is_tx_fifo_empty(PIO pio, uint sm) +{ + struct rp1_pio_sm_fifo_state_args args = { .sm = sm, .tx = true }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_FIFO_STATE, &args); return args.empty; } -static bool rp1_pio_sm_is_tx_fifo_full(PIO pio, uint sm) { - struct rp1_pio_sm_fifo_state_args args = {.sm = sm, .tx = true}; +static bool rp1_pio_sm_is_tx_fifo_full(PIO pio, uint sm) +{ + struct rp1_pio_sm_fifo_state_args args = { .sm = sm, .tx = true }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_FIFO_STATE, &args); return args.full; } -static uint rp1_pio_sm_get_tx_fifo_level(PIO pio, uint sm) { - struct rp1_pio_sm_fifo_state_args args = {.sm = sm, .tx = true}; +static uint rp1_pio_sm_get_tx_fifo_level(PIO pio, uint sm) +{ + struct rp1_pio_sm_fifo_state_args args = { .sm = sm, .tx = true }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_FIFO_STATE, &args); return args.level; } -static void rp1_pio_sm_drain_tx_fifo(PIO pio, uint sm) { - struct rp1_pio_sm_clear_fifos_args args = {.sm = sm}; +static void rp1_pio_sm_drain_tx_fifo(PIO pio, uint sm) +{ + struct rp1_pio_sm_clear_fifos_args args = { .sm = sm }; check_sm_param(sm); (void)rp1_ioctl(pio, PIO_IOC_SM_DRAIN_TX, &args); } -static void rp1_smc_set_out_pins(PIO pio, pio_sm_config *config, uint out_base, - uint out_count) { +static void rp1_smc_set_out_pins(PIO, pio_sm_config *config, uint out_base, uint out_count) +{ smc_to_rp1(config, c); valid_params_if(PIO, out_base < RP1_PIO_GPIO_COUNT); valid_params_if(PIO, out_count <= RP1_PIO_GPIO_COUNT); - c->pinctrl = (c->pinctrl & ~(PROC_PIO_SM0_PINCTRL_OUT_BASE_BITS | - PROC_PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | + c->pinctrl = (c->pinctrl & ~(PROC_PIO_SM0_PINCTRL_OUT_BASE_BITS | PROC_PIO_SM0_PINCTRL_OUT_COUNT_BITS)) | (out_base << PROC_PIO_SM0_PINCTRL_OUT_BASE_LSB) | (out_count << PROC_PIO_SM0_PINCTRL_OUT_COUNT_LSB); } -static void rp1_smc_set_set_pins(PIO pio, pio_sm_config *config, uint set_base, - uint set_count) { +static void rp1_smc_set_set_pins(PIO, pio_sm_config *config, uint set_base, uint set_count) +{ smc_to_rp1(config, c); valid_params_if(PIO, set_base < RP1_PIO_GPIO_COUNT); valid_params_if(PIO, set_count <= 5); - c->pinctrl = (c->pinctrl & ~(PROC_PIO_SM0_PINCTRL_SET_BASE_BITS | - PROC_PIO_SM0_PINCTRL_SET_COUNT_BITS)) | + c->pinctrl = (c->pinctrl & ~(PROC_PIO_SM0_PINCTRL_SET_BASE_BITS | PROC_PIO_SM0_PINCTRL_SET_COUNT_BITS)) | (set_base << PROC_PIO_SM0_PINCTRL_SET_BASE_LSB) | (set_count << PROC_PIO_SM0_PINCTRL_SET_COUNT_LSB); } -static void rp1_smc_set_in_pins(PIO pio, pio_sm_config *config, uint in_base) { + +static void rp1_smc_set_in_pins(PIO, pio_sm_config *config, uint in_base) +{ smc_to_rp1(config, c); valid_params_if(PIO, in_base < RP1_PIO_GPIO_COUNT); c->pinctrl = (c->pinctrl & ~PROC_PIO_SM0_PINCTRL_IN_BASE_BITS) | (in_base << PROC_PIO_SM0_PINCTRL_IN_BASE_LSB); } -static void rp1_smc_set_sideset_pins(PIO pio, pio_sm_config *config, - uint sideset_base) { +static void rp1_smc_set_sideset_pins(PIO, pio_sm_config *config, uint sideset_base) +{ smc_to_rp1(config, c); valid_params_if(PIO, sideset_base < RP1_PIO_GPIO_COUNT); c->pinctrl = (c->pinctrl & ~PROC_PIO_SM0_PINCTRL_SIDESET_BASE_BITS) | (sideset_base << PROC_PIO_SM0_PINCTRL_SIDESET_BASE_LSB); } -static void rp1_smc_set_sideset(PIO pio, pio_sm_config *config, uint bit_count, - bool optional, bool pindirs) { +static void rp1_smc_set_sideset(PIO, pio_sm_config *config, uint bit_count, bool optional, bool pindirs) +{ smc_to_rp1(config, c); valid_params_if(PIO, bit_count <= 5); valid_params_if(PIO, !optional || bit_count >= 1); c->pinctrl = (c->pinctrl & ~PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) | (bit_count << PROC_PIO_SM0_PINCTRL_SIDESET_COUNT_LSB); - c->execctrl = - (c->execctrl & ~(PROC_PIO_SM0_EXECCTRL_SIDE_EN_BITS | - PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) | - (bool_to_bit(optional) << PROC_PIO_SM0_EXECCTRL_SIDE_EN_LSB) | - (bool_to_bit(pindirs) << PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB); + c->execctrl = (c->execctrl & ~(PROC_PIO_SM0_EXECCTRL_SIDE_EN_BITS | PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) | + (bool_to_bit(optional) << PROC_PIO_SM0_EXECCTRL_SIDE_EN_LSB) | + (bool_to_bit(pindirs) << PROC_PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB); } -static void rp1_smc_set_clkdiv_int_frac(PIO pio, pio_sm_config *config, - uint16_t div_int, uint8_t div_frac) { +static void rp1_smc_set_clkdiv_int_frac(PIO, pio_sm_config *config, uint16_t div_int, uint8_t div_frac) +{ smc_to_rp1(config, c); invalid_params_if(PIO, div_int == 0 && div_frac != 0); - c->clkdiv = (((uint)div_frac) << PROC_PIO_SM0_CLKDIV_FRAC_LSB) | - (((uint)div_int) << PROC_PIO_SM0_CLKDIV_INT_LSB); + c->clkdiv = + (((uint)div_frac) << PROC_PIO_SM0_CLKDIV_FRAC_LSB) | + (((uint)div_int) << PROC_PIO_SM0_CLKDIV_INT_LSB); } -static void rp1_smc_set_clkdiv(PIO pio, pio_sm_config *config, float div) { +static void rp1_smc_set_clkdiv(PIO, pio_sm_config *config, float div) +{ uint16_t div_int; uint8_t div_frac; rp1_pio_calculate_clkdiv_from_float(div, &div_int, &div_frac); sm_config_set_clkdiv_int_frac(config, div_int, div_frac); } -static void rp1_smc_set_wrap(PIO pio, pio_sm_config *config, uint wrap_target, - uint wrap) { +static void rp1_smc_set_wrap(PIO, pio_sm_config *config, uint wrap_target, uint wrap) +{ smc_to_rp1(config, c); valid_params_if(PIO, wrap < RP1_PIO_INSTRUCTION_COUNT); valid_params_if(PIO, wrap_target < RP1_PIO_INSTRUCTION_COUNT); - c->execctrl = (c->execctrl & ~(PROC_PIO_SM0_EXECCTRL_WRAP_TOP_BITS | - PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | + c->execctrl = (c->execctrl & ~(PROC_PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) | (wrap_target << PROC_PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) | (wrap << PROC_PIO_SM0_EXECCTRL_WRAP_TOP_LSB); } -static void rp1_smc_set_jmp_pin(PIO pio, pio_sm_config *config, uint pin) { +static void rp1_smc_set_jmp_pin(PIO, pio_sm_config *config, uint pin) +{ smc_to_rp1(config, c); valid_params_if(PIO, pin < RP1_PIO_GPIO_COUNT); c->execctrl = (c->execctrl & ~PROC_PIO_SM0_EXECCTRL_JMP_PIN_BITS) | (pin << PROC_PIO_SM0_EXECCTRL_JMP_PIN_LSB); } -static void rp1_smc_set_in_shift(PIO pio, pio_sm_config *config, - bool shift_right, bool autopush, - uint push_threshold) { +static void rp1_smc_set_in_shift(PIO, pio_sm_config *config, bool shift_right, bool autopush, uint push_threshold) +{ smc_to_rp1(config, c); valid_params_if(PIO, push_threshold <= 32); - c->shiftctrl = - (c->shiftctrl & ~(PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS | - PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS | - PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) | - (bool_to_bit(shift_right) << PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) | - (bool_to_bit(autopush) << PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) | - ((push_threshold & 0x1fu) << PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB); + c->shiftctrl = (c->shiftctrl & + ~(PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS | + PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS | + PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) | + (bool_to_bit(shift_right) << PROC_PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) | + (bool_to_bit(autopush) << PROC_PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) | + ((push_threshold & 0x1fu) << PROC_PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB); } -static void rp1_smc_set_out_shift(PIO pio, pio_sm_config *config, - bool shift_right, bool autopull, - uint pull_threshold) { +static void rp1_smc_set_out_shift(PIO, pio_sm_config *config, bool shift_right, bool autopull, uint pull_threshold) +{ smc_to_rp1(config, c); valid_params_if(PIO, pull_threshold <= 32); - c->shiftctrl = - (c->shiftctrl & ~(PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS | - PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_BITS | - PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) | - (bool_to_bit(shift_right) << PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) | - (bool_to_bit(autopull) << PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) | - ((pull_threshold & 0x1fu) << PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB); + c->shiftctrl = (c->shiftctrl & + ~(PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS | + PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_BITS | + PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) | + (bool_to_bit(shift_right) << PROC_PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) | + (bool_to_bit(autopull) << PROC_PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) | + ((pull_threshold & 0x1fu) << PROC_PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB); } -static void rp1_smc_set_fifo_join(PIO pio, pio_sm_config *config, - enum pio_fifo_join join) { +static void rp1_smc_set_fifo_join(PIO, pio_sm_config *config, enum pio_fifo_join join) +{ smc_to_rp1(config, c); - valid_params_if(PIO, join == PIO_FIFO_JOIN_NONE || - join == PIO_FIFO_JOIN_TX || - join == PIO_FIFO_JOIN_RX); - c->shiftctrl = - (c->shiftctrl & (uint) ~(PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | - PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) | - (((uint)join) << PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB); + valid_params_if(PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX); + c->shiftctrl = (c->shiftctrl & (uint)~(PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PROC_PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) | + (((uint)join) << PROC_PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB); } -static void rp1_smc_set_out_special(PIO pio, pio_sm_config *config, bool sticky, - bool has_enable_pin, - uint enable_pin_index) { +static void rp1_smc_set_out_special(PIO, pio_sm_config *config, bool sticky, bool has_enable_pin, uint enable_pin_index) +{ smc_to_rp1(config, c); - c->execctrl = - (c->execctrl & (uint) ~(PROC_PIO_SM0_EXECCTRL_OUT_STICKY_BITS | - PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS | - PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) | - (bool_to_bit(sticky) << PROC_PIO_SM0_EXECCTRL_OUT_STICKY_LSB) | - (bool_to_bit(has_enable_pin) - << PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) | - ((enable_pin_index << PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & - PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS); + c->execctrl = (c->execctrl & + (uint)~(PROC_PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS | + PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) | + (bool_to_bit(sticky) << PROC_PIO_SM0_EXECCTRL_OUT_STICKY_LSB) | + (bool_to_bit(has_enable_pin) << PROC_PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) | + ((enable_pin_index << PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PROC_PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS); } -static void rp1_smc_set_mov_status(PIO pio, pio_sm_config *config, - enum pio_mov_status_type status_sel, - uint status_n) { +static void rp1_smc_set_mov_status(PIO, pio_sm_config *config, enum pio_mov_status_type status_sel, uint status_n) +{ smc_to_rp1(config, c); - valid_params_if(PIO, status_sel == STATUS_TX_LESSTHAN || - status_sel == STATUS_RX_LESSTHAN); - c->execctrl = - (c->execctrl & ~(PROC_PIO_SM0_EXECCTRL_STATUS_SEL_BITS | - PROC_PIO_SM0_EXECCTRL_STATUS_N_BITS)) | - ((((uint)status_sel) << PROC_PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & - PROC_PIO_SM0_EXECCTRL_STATUS_SEL_BITS) | - ((status_n << PROC_PIO_SM0_EXECCTRL_STATUS_N_LSB) & - PROC_PIO_SM0_EXECCTRL_STATUS_N_BITS); + valid_params_if(PIO, status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN); + c->execctrl = (c->execctrl + & ~(PROC_PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PROC_PIO_SM0_EXECCTRL_STATUS_N_BITS)) + | ((((uint)status_sel) << PROC_PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PROC_PIO_SM0_EXECCTRL_STATUS_SEL_BITS) + | ((status_n << PROC_PIO_SM0_EXECCTRL_STATUS_N_LSB) & PROC_PIO_SM0_EXECCTRL_STATUS_N_BITS); } -static uint32_t rp1_clock_get_hz(PIO pio, enum clock_index clk_index) { +static uint32_t rp1_clock_get_hz(PIO, enum clock_index clk_index) +{ const uint32_t MHZ = 1000000; switch (clk_index) { @@ -734,70 +752,78 @@ static uint32_t rp1_clock_get_hz(PIO pio, enum clock_index clk_index) { return PIO_ORIGIN_ANY; } -static void rp1_gpio_init(PIO pio, uint gpio) { - struct rp1_gpio_init_args args = {.gpio = gpio}; +static void rp1_gpio_init(PIO pio, uint gpio) +{ + struct rp1_gpio_init_args args = { .gpio = gpio }; valid_params_if(PIO, gpio < RP1_PIO_GPIO_COUNT); (void)rp1_ioctl(pio, PIO_IOC_GPIO_INIT, &args); } -static void rp1_gpio_set_function(PIO pio, uint gpio, enum gpio_function fn) { - struct rp1_gpio_set_function_args args = {.gpio = gpio, .fn = fn}; +static void rp1_gpio_set_function(PIO pio, uint gpio, enum gpio_function fn) +{ + struct rp1_gpio_set_function_args args = { .gpio = gpio, .fn = fn }; valid_params_if(PIO, gpio < RP1_PIO_GPIO_COUNT); (void)rp1_ioctl(pio, PIO_IOC_GPIO_SET_FUNCTION, &args); } -static void rp1_gpio_set_pulls(PIO pio, uint gpio, bool up, bool down) { - struct rp1_gpio_set_pulls_args args = { - .gpio = gpio, .up = up, .down = down}; +static void rp1_gpio_set_pulls(PIO pio, uint gpio, bool up, bool down) +{ + struct rp1_gpio_set_pulls_args args = { .gpio = gpio, .up = up, .down = down }; valid_params_if(PIO, gpio < RP1_PIO_GPIO_COUNT); (void)rp1_ioctl(pio, PIO_IOC_GPIO_SET_PULLS, &args); } -static void rp1_gpio_set_outover(PIO pio, uint gpio, uint value) { - struct rp1_gpio_set_args args = {.gpio = gpio, .value = value}; +static void rp1_gpio_set_outover(PIO pio, uint gpio, uint value) +{ + struct rp1_gpio_set_args args = { .gpio = gpio, .value = value }; valid_params_if(PIO, gpio < RP1_PIO_GPIO_COUNT); (void)rp1_ioctl(pio, PIO_IOC_GPIO_SET_OUTOVER, &args); } -static void rp1_gpio_set_inover(PIO pio, uint gpio, uint value) { - struct rp1_gpio_set_args args = {.gpio = gpio, .value = value}; +static void rp1_gpio_set_inover(PIO pio, uint gpio, uint value) +{ + struct rp1_gpio_set_args args = { .gpio = gpio, .value = value }; valid_params_if(PIO, gpio < RP1_PIO_GPIO_COUNT); (void)rp1_ioctl(pio, PIO_IOC_GPIO_SET_INOVER, &args); } -static void rp1_gpio_set_oeover(PIO pio, uint gpio, uint value) { - struct rp1_gpio_set_args args = {.gpio = gpio, .value = value}; +static void rp1_gpio_set_oeover(PIO pio, uint gpio, uint value) +{ + struct rp1_gpio_set_args args = { .gpio = gpio, .value = value }; valid_params_if(PIO, gpio < RP1_PIO_GPIO_COUNT); (void)rp1_ioctl(pio, PIO_IOC_GPIO_SET_OEOVER, &args); } -static void rp1_gpio_set_input_enabled(PIO pio, uint gpio, bool enabled) { - struct rp1_gpio_set_args args = {.gpio = gpio, .value = enabled}; +static void rp1_gpio_set_input_enabled(PIO pio, uint gpio, bool enabled) +{ + struct rp1_gpio_set_args args = { .gpio = gpio, .value = enabled }; valid_params_if(PIO, gpio < RP1_PIO_GPIO_COUNT); (void)rp1_ioctl(pio, PIO_IOC_GPIO_SET_INPUT_ENABLED, &args); } -static void rp1_gpio_set_drive_strength(PIO pio, uint gpio, - enum gpio_drive_strength drive) { - struct rp1_gpio_set_args args = {.gpio = gpio, .value = drive}; +static void rp1_gpio_set_drive_strength(PIO pio, uint gpio, enum gpio_drive_strength drive) +{ + struct rp1_gpio_set_args args = { .gpio = gpio, .value = drive }; valid_params_if(PIO, gpio < RP1_PIO_GPIO_COUNT); (void)rp1_ioctl(pio, PIO_IOC_GPIO_SET_DRIVE_STRENGTH, &args); } -static void rp1_pio_gpio_init(PIO pio, uint pin) { +static void rp1_pio_gpio_init(PIO pio, uint pin) +{ valid_params_if(PIO, pin < RP1_PIO_GPIO_COUNT); - rp1_gpio_set_function(pio, pin, (enum gpio_function)RP1_GPIO_FUNC_PIO); + rp1_gpio_set_function(pio, pin, RP1_GPIO_FUNC_PIO); } -PIO rp1_create_instance(PIO_CHIP_T *chip, uint index) { +PIO rp1_create_instance(PIO_CHIP_T *chip, uint index) +{ char pathbuf[20]; RP1_PIO pio = NULL; @@ -806,7 +832,7 @@ PIO rp1_create_instance(PIO_CHIP_T *chip, uint index) { if (access(pathbuf, F_OK) != 0) return NULL; - pio = (RP1_PIO)calloc(1, sizeof(*pio)); + pio = calloc(1, sizeof(*pio)); if (!pio) return PIO_ERR(-ENOMEM); @@ -819,7 +845,8 @@ PIO rp1_create_instance(PIO_CHIP_T *chip, uint index) { return &pio->base; } -int rp1_open_instance(PIO pio) { +int rp1_open_instance(PIO pio) +{ RP1_PIO rp = (RP1_PIO)pio; int fd; @@ -830,7 +857,8 @@ int rp1_open_instance(PIO pio) { return 0; } -void rp1_close_instance(PIO pio) { +void rp1_close_instance(PIO pio) +{ RP1_PIO rp = (RP1_PIO)pio; close(rp->fd); } @@ -839,7 +867,7 @@ static const PIO_CHIP_T rp1_pio_chip = { .name = "rp1", .compatible = "raspberrypi,rp1-pio", .instr_count = RP1_PIO_INSTRUCTION_COUNT, - .sm_count = RP1_PIO_SM_COUNT, + .sm_count = RP1_PIO_SM_COUNT, .fifo_depth = 8, .create_instance = rp1_create_instance, diff --git a/src/piolib/piolib.c b/src/piolib/piolib.c index 8047068..87fe68e 100644 --- a/src/piolib/piolib.c +++ b/src/piolib/piolib.c @@ -28,26 +28,33 @@ static PIO pio_instances[PIO_MAX_INSTANCES]; static uint num_instances; static pthread_mutex_t pio_handle_lock; -void pio_select(PIO pio) { __pio = pio; } +void pio_select(PIO pio) +{ + __pio = pio; +} -PIO pio_get_current(void) { +PIO pio_get_current(void) +{ PIO pio = __pio; check_pio_param(pio); return pio; } -int pio_get_index(PIO pio) { +int pio_get_index(PIO pio) +{ int i; - for (i = 0; i < PIO_MAX_INSTANCES; i++) { + for (i = 0; i < PIO_MAX_INSTANCES; i++) + { if (pio == pio_instances[i]) return i; } return -1; } -int pio_init(void) { +int pio_init(void) +{ static bool initialised; - const PIO_CHIP_T *const *p; + const PIO_CHIP_T * const *p; uint i = 0; int err; @@ -55,7 +62,8 @@ int pio_init(void) { return 0; num_instances = 0; p = &__start_piochips; - while (p < &__stop_piochips && num_instances < PIO_MAX_INSTANCES) { + while (p < &__stop_piochips && num_instances < PIO_MAX_INSTANCES) + { PIO_CHIP_T *chip = *p; PIO pio = chip->create_instance(chip, i); if (pio && !PIO_IS_ERR(pio)) { @@ -75,7 +83,8 @@ int pio_init(void) { return 0; } -PIO pio_open(uint idx) { +PIO pio_open(uint idx) +{ PIO pio = NULL; int err; @@ -112,7 +121,8 @@ PIO pio_open(uint idx) { return pio; } -PIO pio_open_by_name(const char *name) { +PIO pio_open_by_name(const char *name) +{ int err = -ENOENT; uint i; @@ -132,33 +142,38 @@ PIO pio_open_by_name(const char *name) { return pio_open(i); } -PIO pio_open_helper(uint idx) { +PIO pio_open_helper(uint idx) +{ PIO pio = pio_instances[idx]; if (!pio || !pio->in_use) { pio = pio_open(idx); if (PIO_IS_ERR(pio)) { - printf("* Failed to open PIO device %d (error %d)\n", idx, - PIO_ERR_VAL(pio)); + printf("* Failed to open PIO device %d (error %d)\n", + idx, PIO_ERR_VAL(pio)); exit(1); } } return pio; } -void pio_close(PIO pio) { +void pio_close(PIO pio) +{ pio->chip->close_instance(pio); pthread_mutex_lock(&pio_handle_lock); pio->in_use = 0; pthread_mutex_unlock(&pio_handle_lock); } -void pio_panic(const char *msg) { +void pio_panic(const char *msg) +{ fprintf(stderr, "PANIC: %s\n", msg); exit(1); } void sleep_us(uint64_t us) { - const struct timespec tv = {.tv_sec = (us / 1000000), - .tv_nsec = 1000ull * (us % 1000000)}; + const struct timespec tv = { + .tv_sec = (us / 1000000), + .tv_nsec = 1000ull * (us % 1000000) + }; nanosleep(&tv, NULL); } diff --git a/src/protodemo.c b/src/protodemo.cpp similarity index 87% rename from src/protodemo.c rename to src/protodemo.cpp index b5899b3..6660bfd 100644 --- a/src/protodemo.c +++ b/src/protodemo.cpp @@ -4,6 +4,7 @@ #include #include #include +#include #include #include "piomatter/piomatter.h" @@ -61,7 +62,7 @@ uint32_t pixels[height][width] = { #undef w #undef _ -#define rgb(r, g, b) ((r << 16) | (g << 8) | b) +#define rgb(r, g, b) (((r) << 16) | ((g) << 8) | (b)) uint32_t colorwheel(int i) { i = i & 0xff; @@ -102,28 +103,42 @@ static void print_dither_schedule(const piomatter::schedule_sequence &ss) { } printf("\n"); } + printf(" -> "); + std::map sums; + for (auto s : ss) { + for (auto i : s) { + sums[-i.shift] += i.active_time; + } + } + for (auto const &i : sums) { + printf("{%d %d} ", -i.first, i.second); + } printf("\n"); } static void test_simple_dither_schedule(int n_planes, int pixels_across) { auto ss = piomatter::make_simple_schedule(n_planes, pixels_across); print_dither_schedule(ss); + printf("\n"); } static void test_temporal_dither_schedule(int n_planes, int pixels_across, int n_temporal_frames) { auto ss = piomatter::make_temporal_dither_schedule(n_planes, pixels_across, n_temporal_frames); print_dither_schedule(ss); + printf("\n"); } int main(int argc, char **argv) { int n = argc > 1 ? atoi(argv[1]) : 0; - test_simple_dither_schedule(5, 1); - test_temporal_dither_schedule(5, 1, 0); - test_temporal_dither_schedule(5, 1, 2); - test_temporal_dither_schedule(5, 1, 4); + test_simple_dither_schedule(7, 1); + test_temporal_dither_schedule(7, 1, 2); + test_temporal_dither_schedule(7, 1, 3); + test_temporal_dither_schedule(7, 1, 4); + test_temporal_dither_schedule(7, 1, 5); + return 0; test_simple_dither_schedule(6, 1); test_temporal_dither_schedule(6, 1, 0); test_temporal_dither_schedule(6, 1, 2); @@ -131,6 +146,7 @@ int main(int argc, char **argv) { test_simple_dither_schedule(5, 16); test_temporal_dither_schedule(5, 16, 2); + test_temporal_dither_schedule(5, 16, 3); test_temporal_dither_schedule(5, 16, 4); test_simple_dither_schedule(5, 24); @@ -140,6 +156,8 @@ int main(int argc, char **argv) { test_simple_dither_schedule(10, 24); test_temporal_dither_schedule(10, 24, 8); + test_temporal_dither_schedule(5, 128, 3); + test_temporal_dither_schedule(5, 192, 3); test_temporal_dither_schedule(5, 128, 4); test_temporal_dither_schedule(5, 192, 4); return 0; diff --git a/src/pymain.cpp b/src/pymain.cpp index 4793471..483b2dc 100644 --- a/src/pymain.cpp +++ b/src/pymain.cpp @@ -166,9 +166,11 @@ The number of pixels in the shift register is automatically computed from these layout. Decreasing ``n_planes`` can increase FPS at the cost of reduced color fidelity. The default, 10, is the maximum value. -``n_temporal_planes`` controls temporal dithering of the panel. The acceptable values -are 0 (the default), 2, and 4. A higher setting can increase FPS at the cost of -slightly increasing the variation of brightness across subsequent frames. +``n_temporal_planes`` controls temporal dithering of the panel. +0 or 1 behave the same: All `n_planes` are transmitted every time. +A higher value sets the number of planes that are only transmitted every `1/n_temporal_frames` times. +A higher setting can increase FPS at the cost of slightly increasing the variation of brightness across subsequent frames. +Settings above 4 are allowed, but generally do not give good results. For simple panels with just 1 connector (2 color lanes), the following constructor arguments are available: