audio out
neopixel out
4 x Power Out
(1 x Stepper)
2 x DC Motor
(1 x Stepper)
7
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
<p>HTSSOP 16 (5x4.4mm 0.65mm Pitch)</p>
<p>Source: http://www.ti.com/lit/ds/slvsar1b/slvsar1b.pdf</p>
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
PCB EDGE
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
A
C
DJ Jack 2.0mm PTH Right-Angle
>NAME
>VALUE
DC 2.0/2.1
>NAME
>VALUE
>NAME
>VALUE
<b>Small Outline Transistor</b> - 5 Pin
>NAME
>VALUE
>NAME
>VALUE
<b>Source: http://www.intersil.com/data/fn/fn7833.pdf</b>
>NAME
>VALUE
<p>Bourns 3303W 3MM SMT Trimpot</p>
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
<b>Panasonic Aluminium Electrolytic Capacitor VS-Serie Package C</b>
>NAME
>VALUE
>NAME
>VALUE
<b>SOD-123</b>
<p>Source: http://www.diodes.com/datasheets/ds30139.pdf</p>
>NAME
>VALUE
>NAME
>VALUE
1
3
<b>SOD323</b> (2.5x1.2mm)
>NAME
>VALUE
<b>Revision Level Field</b> - 40 mil<p>
Set version with global board attribute '>REV'
>REV
>NAME
>VALUE
>NAME
>VALUE
>NAME
>VALUE
<b>Driver Arrays</b><p>
ULN and UDN Series<p>
<author>Created by librarian@cadsoft.de</author>
<b>Small Outline Package</b>
>VALUE
>NAME
Small Outline Package
<b>Single and Dual Gates Family, US symbols</b><p>
Little logic devices from Texas Instruments<br>
TinyLogic(R) from FAIRCHILD Semiconductor TM
<p>
<author>Created by evgeni@eniks.com</author><br>
<author>Extended by librarian@cadsoft.de</author>
<b>Small Outline Transistor</b><p>
SOT753 - Philips Semiconductors<br>
Source: http://www.semiconductors.philips.com/acrobat_download/datasheets/74HC_HCT1G66_3.pdf
>NAME
>VALUE
Small Outline Transistor
SOT753 - Philips Semiconductors
Source: http://www.semiconductors.philips.com/acrobat_download/datasheets/74HC_HCT1G66_3.pdf
<b>Test Pins/Pads</b><p>
Cream on SMD OFF.<br>
new: Attribute TP_SIGNAL_NAME<br>
<author>Created by librarian@cadsoft.de</author>
<b>TEST PAD</b>
>NAME
>VALUE
>TP_SIGNAL_NAME
TEST PAD
<b>EAGLE Design Rules</b>
<p>
Die Standard-Design-Rules sind so gewählt, dass sie für
die meisten Anwendungen passen. Sollte ihre Platine
besondere Anforderungen haben, treffen Sie die erforderlichen
Einstellungen hier und speichern die Design Rules unter
einem neuen Namen ab.
<b>Adafruit board design rules</b>
<p>
<ul>
<li>Smallest drill: 16mm</li>
<li>Min trace: 10mil</li>
<li>Min spacing: 8mil</li>
<li>Dimension spacing: 10mil</li>
<li>Tenting for vias</li>
<li>Angle check on</li>
</ul>
Since Version 6.2.2 text objects can contain more than one line,
which will not be processed correctly with this version.
Since Version 8.2, EAGLE supports online libraries. The ids
of those online libraries will not be understood (or retained)
with this version.
Since Version 8.3, EAGLE supports URNs for individual library
assets (packages, symbols, and devices). The URNs of those assets
will not be understood (or retained) with this version.
Since Version 8.3, EAGLE supports the association of 3D packages
with devices in libraries, schematics, and board files. Those 3D
packages will not be understood (or retained) with this version.