Teensy 4 getting closer
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3e64c1e127
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60414a4d0d
3 changed files with 85 additions and 4 deletions
3
arch.h
3
arch.h
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@ -1138,6 +1138,9 @@ uint32_t _PM_timerStop(void *tptr) {
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return _PM_timerGetCount(tptr);
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}
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#define _PM_clockHoldHigh asm("nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop");
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#define _PM_clockHoldLow asm("nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop");
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#elif defined(CIRCUITPY)
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// Teensy 4 CircuitPython magic goes here.
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84
core.c
84
core.c
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@ -241,7 +241,7 @@ ProtomatterStatus _PM_begin(Protomatter_core *core) {
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// Figure out clockMask and rgbAndClockMask, clear matrix buffers
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if (core->bytesPerElement == 1) {
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core->portOffset = _PM_byteOffset(core->rgbPins[0]);
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#if defined(_PM_portToggleRegister)
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#if defined(_PM_portToggleRegister) && !defined(_PM_STRICT_32BIT_IO)
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// Clock and rgbAndClockMask are 8-bit values
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core->clockMask = _PM_portBitMask(core->clockPin) >> (core->portOffset * 8);
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core->rgbAndClockMask =
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@ -258,7 +258,7 @@ ProtomatterStatus _PM_begin(Protomatter_core *core) {
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}
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} else if (core->bytesPerElement == 2) {
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core->portOffset = _PM_wordOffset(core->rgbPins[0]);
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#if defined(_PM_portToggleRegister)
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#if defined(_PM_portToggleRegister) && !defined(_PM_STRICT_32BIT_IO)
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// Clock and rgbAndClockMask are 16-bit values
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core->clockMask =
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_PM_portBitMask(core->clockPin) >> (core->portOffset * 16);
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@ -563,6 +563,9 @@ IRAM_ATTR void _PM_row_handler(Protomatter_core *core) {
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// before setting the clock back low. If undefined, nothing goes there.
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#if !defined(PEW) // arch.h can define a custom PEW if needed (e.g. ESP32)
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#if !defined(_PM_STRICT_32BIT_IO) // Partial access to 32-bit GPIO OK
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#if defined(_PM_portToggleRegister)
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#define PEW \
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*toggle = *data++; /* Toggle in new data + toggle clock low */ \
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@ -578,7 +581,28 @@ IRAM_ATTR void _PM_row_handler(Protomatter_core *core) {
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*clear_full = rgbclock; /* Clear RGB data + clock */ \
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///< Bitbang one set of RGB data bits to matrix
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#endif
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#endif // PEW
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#else // ONLY 32-bit GPIO
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#if defined(_PM_portToggleRegister)
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#define PEW \
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*toggle = *data++ << shift; /* Toggle in new data + toggle clock low */ \
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_PM_clockHoldLow; \
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*toggle = clock; /* Toggle clock high */ \
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_PM_clockHoldHigh;
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#else
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#define PEW \
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*set = *data++ << shift; /* Set RGB data high */ \
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_PM_clockHoldLow; \
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*set = clock; /* Set clock high */ \
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_PM_clockHoldHigh; \
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*clear = rgbclock; /* Clear RGB data + clock */ \
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///< Bitbang one set of RGB data bits to matrix
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#endif
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#endif // end 32-bit GPIO
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#endif // end PEW
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#if _PM_chunkSize == 1
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#define PEW_UNROLL PEW
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@ -608,6 +632,8 @@ IRAM_ATTR void _PM_row_handler(Protomatter_core *core) {
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// three-function maintenance then.)
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IRAM_ATTR static void blast_byte(Protomatter_core *core, uint8_t *data) {
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#if !defined(_PM_STRICT_32BIT_IO) // Partial access to 32-bit GPIO OK
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#if defined(_PM_portToggleRegister)
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// If here, it was established in begin() that the RGB data bits and
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// clock are all within the same byte of a PORT register, else we'd be
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@ -645,9 +671,37 @@ IRAM_ATTR static void blast_byte(Protomatter_core *core, uint8_t *data) {
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*((volatile uint8_t *)core->clearReg + core->portOffset) =
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core->rgbAndClockMask;
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#endif
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#else // ONLY 32-bit GPIO
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#if defined(_PM_portToggleRegister)
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volatile _PM_PORT_TYPE *toggle = (volatile _PM_PORT_TYPE *)core->toggleReg;
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#else
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volatile _PM_PORT_TYPE *set = (volatile _PM_PORT_TYPE *)core->setReg;
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volatile _PM_PORT_TYPE *clear = (volatile _PM_PORT_TYPE *)core->clearReg;
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_PM_PORT_TYPE rgbclock = core->rgbAndClockMask; // RGB + clock bit
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#endif
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_PM_PORT_TYPE clock = core->clockMask; // Clock bit
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uint8_t shift = core->portOffset * 8;
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uint8_t chunks = (core->width + (_PM_chunkSize - 1)) / _PM_chunkSize;
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// PORT has already been initialized with RGB data + clock bits
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// all LOW, so we don't need to initialize that state here.
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while (chunks--) {
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PEW_UNROLL // _PM_chunkSize RGB+clock writes
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}
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#if defined(_PM_portToggleRegister)
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*((volatile uint32_t *)core->clearReg) = core->rgbAndClockMask;
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#endif
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#endif // 32-bit GPIO
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}
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IRAM_ATTR static void blast_word(Protomatter_core *core, uint16_t *data) {
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#if !defined(_PM_STRICT_32BIT_IO) // Partial access to 32-bit GPIO OK
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#if defined(_PM_portToggleRegister)
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// See notes above -- except now 16-bit word in PORT.
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volatile uint16_t *toggle =
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@ -671,6 +725,27 @@ IRAM_ATTR static void blast_word(Protomatter_core *core, uint16_t *data) {
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*((volatile uint16_t *)core->clearReg + core->portOffset) =
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core->rgbAndClockMask;
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#endif
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#else // ONLY 32-bit GPIO
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#if defined(_PM_portToggleRegister)
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volatile _PM_PORT_TYPE *toggle = (volatile _PM_PORT_TYPE *)core->toggleReg;
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#else
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volatile _PM_PORT_TYPE *set = (volatile _PM_PORT_TYPE *)core->setReg;
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volatile _PM_PORT_TYPE *clear = (volatile _PM_PORT_TYPE *)core->clearReg;
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_PM_PORT_TYPE rgbclock = core->rgbAndClockMask; // RGB + clock bit
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#endif
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_PM_PORT_TYPE clock = core->clockMask; // Clock bit
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uint8_t shift = core->portOffset * 16;
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uint8_t chunks = (core->width + (_PM_chunkSize - 1)) / _PM_chunkSize;
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while (chunks--) {
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PEW_UNROLL // _PM_chunkSize RGB+clock writes
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}
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#if defined(_PM_portToggleRegister)
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*((volatile _PM_PORT_TYPE *)core->clearReg) = core->rgbAndClockMask;
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#endif
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#endif // 32-bit GPIO
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}
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IRAM_ATTR static void blast_long(Protomatter_core *core, uint32_t *data) {
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@ -690,6 +765,9 @@ IRAM_ATTR static void blast_long(Protomatter_core *core, uint32_t *data) {
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_PM_PORT_TYPE rgbclock = core->rgbAndClockMask; // RGB + clock bit
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#endif
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_PM_PORT_TYPE clock = core->clockMask; // Clock bit
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#if defined(_PM_STRICT_32BIT_IO)
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uint8_t shift = 0;
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#endif
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uint8_t chunks = (core->width + (_PM_chunkSize - 1)) / _PM_chunkSize;
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while (chunks--) {
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PEW_UNROLL // _PM_chunkSize RGB+clock writes
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@ -108,7 +108,7 @@ RGB+clock are on different PORTs on nRF52840.
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uint8_t latchPin = 32;
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uint8_t oePin = 33;
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#elif defined(ARDUINO_TEENSY40)
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uint8_t rgbPins[] = {15, 16, 17, 20, 21, 22}; // A1-2, A6-8 (skip SDA, SCL)
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uint8_t rgbPins[] = {15, 16, 17, 20, 21, 22}; // A1-A3, A6-A8, skips SDA,SCL
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uint8_t addrPins[] = {2, 3, 4, 5};
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uint8_t clockPin = 23; // A9
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uint8_t latchPin = 6;
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