updates to support esp-idf v5.0 on circuitpython

src/arch/esp32-c3.h

@@ -29,6 +29,8 @@
 #define _PM_portSetRegister(pin) (volatile uint32_t *)&GPIO.out_w1ts
 #define _PM_portClearRegister(pin) (volatile uint32_t *)&GPIO.out_w1tc
 
+#define _PM_portBitMask(pin) (1U << ((pin)&31))
+
 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
 #define _PM_byteOffset(pin) ((pin & 31) / 8)
 #define _PM_wordOffset(pin) ((pin & 31) / 16)

src/arch/esp32-common.h

@@ -26,6 +26,7 @@
 // see if the same should be applied!
 
 #include "driver/timer.h"
+#include "soc/gpio_periph.h"
 
 // As currently written, only one instance of the Protomatter_core struct
 // is allowed, set up when calling begin()...so it's just a global here:
@@ -106,6 +107,7 @@ void _PM_esp32commonTimerInit(Protomatter_core *core) {
 // here and into the variant-specific headers.
 
 #include "driver/gpio.h"
+#include "esp_idf_version.h"
 #include "hal/timer_ll.h"
 #include "peripherals/timer.h"
 
@@ -113,7 +115,6 @@ void _PM_esp32commonTimerInit(Protomatter_core *core) {
 #define _PM_pinOutput(pin) gpio_set_direction((pin), GPIO_MODE_OUTPUT)
 #define _PM_pinLow(pin) gpio_set_level((pin), false)
 #define _PM_pinHigh(pin) gpio_set_level((pin), true)
-#define _PM_portBitMask(pin) (1U << ((pin)&31))
 
 // Timer interrupt handler. This, _PM_row_handler() and any functions
 // called by _PM_row_handler() should all have the IRAM_ATTR attribute
@@ -128,6 +129,17 @@ IRAM_ATTR bool _PM_esp32timerCallback(void *unused) {
 };
 
 // Set timer period, initialize count value to zero, enable timer.
+#if (ESP_IDF_VERSION_MAJOR == 5)
+IRAM_ATTR void _PM_timerStart(Protomatter_core *core, uint32_t period) {
+  timer_index_t *timer = (timer_index_t *)core->timer;
+  timer_ll_enable_counter(timer->hw, timer->idx, false);
+  timer_ll_set_reload_value(timer->hw, timer->idx, 0);
+  timer_ll_trigger_soft_reload(timer->hw, timer->idx);
+  timer_ll_set_alarm_value(timer->hw, timer->idx, period);
+  timer_ll_enable_alarm(timer->hw, timer->idx, true);
+  timer_ll_enable_counter(timer->hw, timer->idx, true);
+}
+#else
 IRAM_ATTR void _PM_timerStart(Protomatter_core *core, uint32_t period) {
   timer_index_t *timer = (timer_index_t *)core->timer;
   timer_ll_set_counter_enable(timer->hw, timer->idx, false);
@@ -136,15 +148,31 @@ IRAM_ATTR void _PM_timerStart(Protomatter_core *core, uint32_t period) {
   timer_ll_set_alarm_enable(timer->hw, timer->idx, true);
   timer_ll_set_counter_enable(timer->hw, timer->idx, true);
 }
+#endif
 
 // Disable timer and return current count value.
 // Timer must be previously initialized.
 IRAM_ATTR uint32_t _PM_timerStop(Protomatter_core *core) {
   timer_index_t *timer = (timer_index_t *)core->timer;
+#if (ESP_IDF_VERSION_MAJOR == 5)
+  timer_ll_enable_counter(timer->hw, timer->idx, false);
+#else
   timer_ll_set_counter_enable(timer->hw, timer->idx, false);
+#endif
   return _PM_timerGetCount(core);
 }
 
+IRAM_ATTR uint32_t _PM_timerGetCount(Protomatter_core *core) {
+  timer_index_t *timer = (timer_index_t *)core->timer;
+#ifdef CONFIG_IDF_TARGET_ESP32S3
+  timer->hw->hw_timer[timer->idx].update.tn_update = 1;
+  return timer->hw->hw_timer[timer->idx].lo.tn_lo;
+#else
+  timer->hw->hw_timer[timer->idx].update.tx_update = 1;
+  return timer->hw->hw_timer[timer->idx].lo.tx_lo;
+#endif
+}
+
 // Initialize, but do not start, timer. This function contains timer setup
 // that's common to all ESP32 variants; code in variant-specific files might
 // set up its own special peripherals, then call this.

src/arch/esp32-s3.h

@@ -46,7 +46,11 @@
 #define _PM_byteOffset(pin) 0
 #define _PM_wordOffset(pin) 0
 
+#if (ESP_IDF_VERSION_MAJOR == 5)
+#include <esp_private/periph_ctrl.h>
+#else
 #include <driver/periph_ctrl.h>
+#endif
 #include <esp_private/gdma.h>
 #include <esp_rom_gpio.h>
 #include <hal/dma_types.h>
@@ -284,7 +288,7 @@ void _PM_timerInit(Protomatter_core *core) {
       .sibling_chan = NULL,
       .direction = GDMA_CHANNEL_DIRECTION_TX,
       .flags = {.reserve_sibling = 0}};
-  esp_err_t ret = gdma_new_channel(&dma_chan_config, &dma_chan);
+  gdma_new_channel(&dma_chan_config, &dma_chan);
   gdma_connect(dma_chan, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_LCD, 0));
   gdma_strategy_config_t strategy_config = {.owner_check = false,
                                             .auto_update_desc = false};

src/arch/esp32.h

@@ -32,6 +32,8 @@
 #define _PM_portClearRegister(pin)                                             \
   (volatile uint32_t *)((pin < 32) ? &GPIO.out_w1tc : &GPIO.out1_w1tc.val)
 
+#define _PM_portBitMask(pin) (1U << ((pin)&31))
+
 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
 #define _PM_byteOffset(pin) ((pin & 31) / 8)
 #define _PM_wordOffset(pin) ((pin & 31) / 16)
@@ -63,6 +65,8 @@
 
 #elif defined(CIRCUITPY) // COMPILING FOR CIRCUITPYTHON --------------------
 
+#define _PM_STRICT_32BIT_IO (1)
+
 // ESP32 requires a custom PEW declaration (issues one set of RGB color bits
 // followed by clock pulse). Turns out the bit set/clear registers are not
 // actually atomic. If two writes are made in quick succession, the second