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Author SHA1 Message Date
Phillip Burgess
69f26bbc7f Fix typo in example 2021-11-29 13:26:26 -08:00
Phillip Burgess
d72a7838b8 ESP32-S2 WIP 2021-11-29 09:19:02 -08:00
2 changed files with 32 additions and 5 deletions

View file

@ -137,7 +137,7 @@ void setup(void) {
// Set up the colors of the bouncy balls.
ballcolor[0] = matrix.color565(0, 20, 0); // Dark green
ballcolor[1] = matrix.color565(0, 0, 20); // Dark blue
ballcolor[2] = matrix.color565(20, 0, 0); // ark red
ballcolor[2] = matrix.color565(20, 0, 0); // Dark red
}
// LOOP - RUNS REPEATEDLY AFTER SETUP --------------------------------------

View file

@ -21,14 +21,18 @@
#include "driver/timer.h"
#ifdef CONFIG_IDF_TARGET_ESP32C3
#define _PM_portOutRegister(pin) (volatile uint32_t *)&GPIO.out
#define _PM_portSetRegister(pin) (volatile uint32_t *)&GPIO.out_w1ts
#define _PM_portClearRegister(pin) (volatile uint32_t *)&GPIO.out_w1tc
#else
#define _PM_portOutRegister(pin) \
(volatile uint32_t *)((pin < 32) ? &GPIO.out : &GPIO.out1.val)
#define _PM_portSetRegister(pin) \
(volatile uint32_t *)((pin < 32) ? &GPIO.out_w1ts : &GPIO.out1_w1ts.val)
#define _PM_portClearRegister(pin) \
(volatile uint32_t *)((pin < 32) ? &GPIO.out_w1tc : &GPIO.out1_w1tc.val)
#endif
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define _PM_byteOffset(pin) ((pin & 31) / 8)
@ -47,17 +51,35 @@ void *_PM_protoPtr = NULL;
#if defined(ARDUINO) // COMPILING FOR ARDUINO ------------------------------
// Not sure yet if 32-bit IO is required on the C3, but is definitely the
// case on S2. Seems probable and there's little harm in going that way
// (one extra shift instruction per RGB out, and the sync'd GPIO writes
// might be blocking anyway and no loss). 'Classic' ESP32 still allows
// byte/word GPIO access, was fun while it lasted.
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#define _PM_STRICT_32BIT_IO
#endif
// ESP32 requires a custom PEW declaration (issues one set of RGB color bits
// followed by clock pulse). Turns out the bit set/clear registers are not
// actually atomic. If two writes are made in quick succession, the second
// has no effect. One option is NOPs, other is to write a 0 (no effect) to
// the opposing register (set vs clear) to synchronize the next write.
#ifdef _PM_STRICT_32BIT_IO
#define PEW \
*set = (*data++) << shift; /* Set RGB data high */ \
*clear_full = 0; /* ESP32 MUST sync before 2nd 'set' */ \
*set = clock; /* Set clock high */ \
*clear_full = rgbclock; /* Clear RGB data + clock */ \
///< Bitbang one set of RGB data bits to matrix
#else
#define PEW \
*set = *data++; /* Set RGB data high */ \
*clear_full = 0; /* ESP32 MUST sync before 2nd 'set' */ \
*set_full = clock; /* Set clock high */ \
*clear_full = rgbclock; /* Clear RGB data + clock */ \
///< Bitbang one set of RGB data bits to matrix
#endif
#define _PM_timerNum 0 // Timer #0 (can be 0-3)
@ -189,8 +211,13 @@ IRAM_ATTR void _PM_timerStart(void *tptr, uint32_t period) {
IRAM_ATTR uint32_t _PM_timerGetCount(void *tptr) {
timer_index_t *timer = (timer_index_t *)tptr;
timer->hw->hw_timer[timer->idx].update.update = 1;
return timer->hw->hw_timer[timer->idx].cnt_low;
#ifdef CONFIG_IDF_TARGET_ESP32S3
timer->hw->hw_timer[timer->idx].update.tn_update = 1;
return timer->hw->hw_timer[timer->idx].lo.tn_lo;
#else
timer->hw->hw_timer[timer->idx].update.tx_update = 1;
return timer->hw->hw_timer[timer->idx].lo.tx_lo;
#endif
}
// Disable timer and return current count value.