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update tinyusb to commit 46f7cf4da2959b96d3af6b7f23d0d02ff7187f2f

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This commit is contained in:
hathach 2023-09-12 19:23:26 +07:00
parent b16bbbf5bb
commit 336f2378e9
11 changed files with 1035 additions and 116 deletions
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6
src/common/tusb_common.h
View file

@ -122,13 +122,11 @@ TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, c
//------------- Bytes -------------//
TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0)
{
TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) {
return ( ((uint32_t) b3) << 24) | ( ((uint32_t) b2) << 16) | ( ((uint32_t) b1) << 8) | b0;
}
TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low)
{
TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) {
return (uint16_t) ((((uint16_t) high) << 8) | low);
}

42
src/common/tusb_debug.h
View file

@ -58,16 +58,14 @@ void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
#define tu_printf printf
#endif
static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
{
static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
}
// Log with Level
#define TU_LOG(n, ...) TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
#define TU_LOG_MEM(n, ...) TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
#define TU_LOG_ARR(n, ...) TU_XSTRCAT3(TU_LOG, n, _ARR)(__VA_ARGS__)
#define TU_LOG_PTR(n, ...) TU_XSTRCAT3(TU_LOG, n, _PTR)(__VA_ARGS__)
#define TU_LOG_BUF(n, ...) TU_XSTRCAT3(TU_LOG, n, _BUF)(__VA_ARGS__)
#define TU_LOG_INT(n, ...) TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
#define TU_LOG_HEX(n, ...) TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
#define TU_LOG_LOCATION() tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
@ -76,8 +74,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
// Log Level 1: Error
#define TU_LOG1 tu_printf
#define TU_LOG1_MEM tu_print_mem
#define TU_LOG1_ARR(_x, _n) tu_print_arr((uint8_t const*)(_x), _n)
#define TU_LOG1_PTR(_x) tu_print_arr((uint8_t const*)(_x), sizeof(*(_x)))
#define TU_LOG1_BUF(_x, _n) tu_print_buf((uint8_t const*)(_x), _n)
#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (unsigned long) (_x) )
#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (unsigned long) (_x) )
@ -85,8 +82,7 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
#if CFG_TUSB_DEBUG >= 2
#define TU_LOG2 TU_LOG1
#define TU_LOG2_MEM TU_LOG1_MEM
#define TU_LOG2_ARR TU_LOG1_ARR
#define TU_LOG2_PTR TU_LOG1_PTR
#define TU_LOG2_BUF TU_LOG1_BUF
#define TU_LOG2_INT TU_LOG1_INT
#define TU_LOG2_HEX TU_LOG1_HEX
#endif
@ -95,30 +91,25 @@ static inline void tu_print_arr(uint8_t const* buf, uint32_t bufsize)
#if CFG_TUSB_DEBUG >= 3
#define TU_LOG3 TU_LOG1
#define TU_LOG3_MEM TU_LOG1_MEM
#define TU_LOG3_ARR TU_LOG1_ARR
#define TU_LOG3_PTR TU_LOG1_PTR
#define TU_LOG3_BUF TU_LOG1_BUF
#define TU_LOG3_INT TU_LOG1_INT
#define TU_LOG3_HEX TU_LOG1_HEX
#endif
typedef struct
{
typedef struct {
uint32_t key;
const char* data;
} tu_lookup_entry_t;
typedef struct
{
typedef struct {
uint16_t count;
tu_lookup_entry_t const* items;
} tu_lookup_table_t;
static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
{
static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) {
tu_static char not_found[11];
for(uint16_t i=0; i<p_table->count; i++)
{
for(uint16_t i=0; i<p_table->count; i++) {
if (p_table->items[i].key == key) return p_table->items[i].data;
}
@ -133,8 +124,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
#ifndef TU_LOG
#define TU_LOG(n, ...)
#define TU_LOG_MEM(n, ...)
#define TU_LOG_ARR(n, ...)
#define TU_LOG_PTR(n, ...)
#define TU_LOG_BUF(n, ...)
#define TU_LOG_INT(n, ...)
#define TU_LOG_HEX(n, ...)
#define TU_LOG_LOCATION()
@ -145,16 +135,14 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
#define TU_LOG0(...)
#define TU_LOG0_MEM(...)
#define TU_LOG0_ARR(...)
#define TU_LOG0_PTR(...)
#define TU_LOG0_BUF(...)
#define TU_LOG0_INT(...)
#define TU_LOG0_HEX(...)
#ifndef TU_LOG1
#define TU_LOG1(...)
#define TU_LOG1_MEM(...)
#define TU_LOG1_ARR(...)
#define TU_LOG1_PTR(...)
#define TU_LOG1_BUF(...)
#define TU_LOG1_INT(...)
#define TU_LOG1_HEX(...)
#endif
@ -162,8 +150,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
#ifndef TU_LOG2
#define TU_LOG2(...)
#define TU_LOG2_MEM(...)
#define TU_LOG2_ARR(...)
#define TU_LOG2_PTR(...)
#define TU_LOG2_BUF(...)
#define TU_LOG2_INT(...)
#define TU_LOG2_HEX(...)
#endif
@ -171,8 +158,7 @@ static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint3
#ifndef TU_LOG3
#define TU_LOG3(...)
#define TU_LOG3_MEM(...)
#define TU_LOG3_ARR(...)
#define TU_LOG3_PTR(...)
#define TU_LOG3_BUF(...)
#define TU_LOG3_INT(...)
#define TU_LOG3_HEX(...)
#endif

12
src/common/tusb_mcu.h
View file

@ -385,6 +385,18 @@
#define TUP_RHPORT_HIGHSPEED 1
#endif
//--------------------------------------------------------------------+
// External USB controller
//--------------------------------------------------------------------+
#if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
#ifndef CFG_TUH_MAX3421_ENDPOINT_TOTAL
#define CFG_TUH_MAX3421_ENDPOINT_TOTAL (8 + 4*(CFG_TUH_DEVICE_MAX-1))
#endif
#endif
//--------------------------------------------------------------------+
// Default Values
//--------------------------------------------------------------------+

42
src/device/usbd.c
View file

@ -35,17 +35,6 @@
#include "device/usbd.h"
#include "device/usbd_pvt.h"
//--------------------------------------------------------------------+
// ESP32 out-of-sync
//--------------------------------------------------------------------+
#if defined(ARDUINO_ARCH_ESP32) && !defined(tu_static)
#define tu_static static
static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count) { if (count > destsz) { return -1; } memset(dest, ch, count); return 0; }
static inline int tu_memcpy_s(void *dest, size_t destsz, const void * src, size_t count ) { if (count > destsz) { return -1; } memcpy(dest, src, count); return 0; }
TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
#endif
#ifndef CFG_TUD_MEM_SECTION
#define CFG_TUD_MEM_SECTION CFG_TUSB_MEM_SECTION
#endif
@ -58,6 +47,32 @@ TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t co
#define TU_LOG_USBD(...) TU_LOG(CFG_TUD_LOG_LEVEL, __VA_ARGS__)
#endif
//--------------------------------------------------------------------+
// ESP32 out-of-sync
//--------------------------------------------------------------------+
#if defined(ARDUINO_ARCH_ESP32)
#ifndef tu_static
#define tu_static static
static inline int tu_memset_s(void *dest, size_t destsz, int ch, size_t count) { if (count > destsz) { return -1; } memset(dest, ch, count); return 0; }
static inline int tu_memcpy_s(void *dest, size_t destsz, const void * src, size_t count ) { if (count > destsz) { return -1; } memcpy(dest, src, count); return 0; }
TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size);
TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc);
#endif
#ifndef TU_LOG_BUF
#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
static inline void tu_print_buf(uint8_t const* buf, uint32_t bufsize) {
for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
}
#define TU_LOG_BUF(lvl, _buf, _bufsize) tu_print_buf(_buf, _bufsize)
#else
#define TU_LOG_BUF(lvl, _buf, _bufsize)
#endif
#endif
#endif
//--------------------------------------------------------------------+
// USBD Configuration
//--------------------------------------------------------------------+
@ -529,11 +544,8 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr)
break;
case DCD_EVENT_SETUP_RECEIVED:
#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
//TU_LOG_ARR(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
tu_print_arr(&event.setup_received, 8);
TU_LOG_BUF(CFG_TUD_LOG_LEVEL, &event.setup_received, 8);
TU_LOG_USBD("\r\n");
#endif
// Mark as connected after receiving 1st setup packet.
// But it is easier to set it every time instead of wasting time to check then set

6
src/device/usbd.h
View file

@ -50,8 +50,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr);
// Task function should be called in main/rtos loop
TU_ATTR_ALWAYS_INLINE static inline
void tud_task (void)
{
void tud_task (void) {
tud_task_ext(UINT32_MAX, false);
}
@ -80,8 +79,7 @@ bool tud_suspended(void);
// Check if device is ready to transfer
TU_ATTR_ALWAYS_INLINE static inline
bool tud_ready(void)
{
bool tud_ready(void) {
return tud_mounted() && !tud_suspended();
}

15
src/device/usbd_pvt.h
View file

@ -23,8 +23,8 @@
*
* This file is part of the TinyUSB stack.
*/
#ifndef USBD_PVT_H_
#define USBD_PVT_H_
#ifndef _TUSB_USBD_PVT_H_
#define _TUSB_USBD_PVT_H_
#include "osal/osal.h"
#include "common/tusb_fifo.h"
@ -44,8 +44,7 @@
// Class Driver API
//--------------------------------------------------------------------+
typedef struct
{
typedef struct {
#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
char const* name;
#endif
@ -111,8 +110,7 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endp
// Check if endpoint is ready (not busy and not stalled)
TU_ATTR_ALWAYS_INLINE static inline
bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr)
{
bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr) {
return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr);
}
@ -124,11 +122,10 @@ void usbd_sof_enable(uint8_t rhport, bool en);
*------------------------------------------------------------------*/
bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in);
void usbd_defer_func( osal_task_func_t func, void* param, bool in_isr );
void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr);
#ifdef __cplusplus
}
#endif
#endif /* USBD_PVT_H_ */
#endif

20
src/host/hcd.h
View file

@ -39,7 +39,7 @@
// Configuration
//--------------------------------------------------------------------+
// Max number of endpoints per device
// Max number of endpoints pair per device
// TODO optimize memory usage
#ifndef CFG_TUH_ENDPOINT_MAX
#define CFG_TUH_ENDPOINT_MAX 16
@ -167,17 +167,17 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
//--------------------------------------------------------------------+
// Open an endpoint
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc);
// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
// Abort a queued transfer. Note: it can only abort transfer that has not been started
// Return true if a queued transfer is aborted, false if there is no transfer to abort
bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]);
// clear stall, data toggle is also reset to DATA0
bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
@ -198,8 +198,7 @@ extern void hcd_event_handler(hcd_event_t const* event, bool in_isr);
// Helper to send device attach event
TU_ATTR_ALWAYS_INLINE static inline
void hcd_event_device_attach(uint8_t rhport, bool in_isr)
{
void hcd_event_device_attach(uint8_t rhport, bool in_isr) {
hcd_event_t event;
event.rhport = rhport;
event.event_id = HCD_EVENT_DEVICE_ATTACH;
@ -211,8 +210,7 @@ void hcd_event_device_attach(uint8_t rhport, bool in_isr)
// Helper to send device removal event
TU_ATTR_ALWAYS_INLINE static inline
void hcd_event_device_remove(uint8_t rhport, bool in_isr)
{
void hcd_event_device_remove(uint8_t rhport, bool in_isr) {
hcd_event_t event;
event.rhport = rhport;
event.event_id = HCD_EVENT_DEVICE_REMOVE;
@ -224,10 +222,8 @@ void hcd_event_device_remove(uint8_t rhport, bool in_isr)
// Helper to send USB transfer event
TU_ATTR_ALWAYS_INLINE static inline
void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
{
hcd_event_t event =
{
void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr) {
hcd_event_t event = {
.rhport = 0, // TODO correct rhport
.event_id = HCD_EVENT_XFER_COMPLETE,
.dev_addr = dev_addr,

67
src/host/usbh.c
View file

@ -552,8 +552,7 @@ static void _control_blocking_complete_cb(tuh_xfer_t* xfer)
}
// TODO timeout_ms is not supported yet
bool tuh_control_xfer (tuh_xfer_t* xfer)
{
bool tuh_control_xfer (tuh_xfer_t* xfer) {
// EP0 with setup packet
TU_VERIFY(xfer->ep_addr == 0 && xfer->setup);
@ -565,8 +564,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
(void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE);
if (is_idle)
{
if (is_idle) {
_ctrl_xfer.stage = CONTROL_STAGE_SETUP;
_ctrl_xfer.daddr = daddr;
_ctrl_xfer.actual_len = 0;
@ -585,14 +583,12 @@ bool tuh_control_xfer (tuh_xfer_t* xfer)
TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr,
(xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ?
tu_str_std_request[xfer->setup->bRequest] : "Class Request");
TU_LOG_ARR(CFG_TUH_LOG_LEVEL, xfer->setup, 8);
TU_LOG_BUF(CFG_TUH_LOG_LEVEL, xfer->setup, 8);
TU_LOG_USBH("\r\n");
if (xfer->complete_cb)
{
if (xfer->complete_cb) {
TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
}else
{
}else {
// blocking if complete callback is not provided
// change callback to internal blocking, and result as user argument
volatile xfer_result_t result = XFER_RESULT_INVALID;
@ -656,30 +652,23 @@ static void _xfer_complete(uint8_t daddr, xfer_result_t result)
}
}
static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
{
static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) {
(void) ep_addr;
const uint8_t rhport = usbh_get_rhport(dev_addr);
tusb_control_request_t const * request = &_ctrl_xfer.request;
if (XFER_RESULT_SUCCESS != result)
{
if (XFER_RESULT_SUCCESS != result) {
TU_LOG1("[%u:%u] Control %s, xferred_bytes = %lu\r\n", rhport, dev_addr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
#if CFG_TUSB_DEBUG == 1
TU_LOG1_PTR(request);
TU_LOG1_BUF(request, 8);
TU_LOG1("\r\n");
#endif
// terminate transfer if any stage failed
_xfer_complete(dev_addr, result);
}else
{
switch(_ctrl_xfer.stage)
{
}else {
switch(_ctrl_xfer.stage) {
case CONTROL_STAGE_SETUP:
if (request->wLength)
{
if (request->wLength) {
// DATA stage: initial data toggle is always 1
_set_control_xfer_stage(CONTROL_STAGE_DATA);
TU_ASSERT( hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) );
@ -688,8 +677,7 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
TU_ATTR_FALLTHROUGH;
case CONTROL_STAGE_DATA:
if (request->wLength)
{
if (request->wLength) {
TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, dev_addr);
TU_LOG_MEM(CFG_TUH_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2);
}
@ -765,29 +753,33 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) {
// USBH API For Class Driver
//--------------------------------------------------------------------+
uint8_t usbh_get_rhport(uint8_t dev_addr)
{
usbh_device_t* dev = get_device(dev_addr);
uint8_t usbh_get_rhport(uint8_t dev_addr) {
usbh_device_t *dev = get_device(dev_addr);
return dev ? dev->rhport : _dev0.rhport;
}
uint8_t* usbh_get_enum_buf(void)
{
uint8_t *usbh_get_enum_buf(void) {
return _usbh_ctrl_buf;
}
void usbh_int_set(bool enabled)
{
void usbh_int_set(bool enabled) {
// TODO all host controller if multiple are used since they shared the same event queue
if (enabled)
{
if (enabled) {
hcd_int_enable(_usbh_controller);
}else
{
} else {
hcd_int_disable(_usbh_controller);
}
}
void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) {
hcd_event_t event = { 0 };
event.event_id = USBH_EVENT_FUNC_CALL;
event.func_call.func = func;
event.func_call.param = param;
osal_queue_send(_usbh_q, &event, in_isr);
}
//--------------------------------------------------------------------+
// Endpoint API
//--------------------------------------------------------------------+
@ -862,7 +854,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
ep_state->busy = 0;
ep_state->claimed = 0;
TU_LOG1("Failed\r\n");
TU_BREAKPOINT();
// TU_BREAKPOINT();
return false;
}
}
@ -929,6 +921,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr)
switch (event->event_id)
{
// case HCD_EVENT_DEVICE_REMOVE:
// // FIXME device remove from a hub need an HCD API for hcd to free up endpoint
// // mark device as removing to prevent further xfer before the event is processed in usbh task
// break;
@ -1538,9 +1531,7 @@ static bool enum_new_device(hcd_event_t* event)
xfer.result = XFER_RESULT_SUCCESS;
xfer.user_data = ENUM_ADDR0_DEVICE_DESC;
process_enumeration(&xfer);
}
#if CFG_TUH_HUB
else

10
src/host/usbh_pvt.h
View file

@ -24,8 +24,8 @@
* This file is part of the TinyUSB stack.
*/
#ifndef _TUSB_USBH_CLASSDRIVER_H_
#define _TUSB_USBH_CLASSDRIVER_H_
#ifndef _TUSB_USBH_PVT_H_
#define _TUSB_USBH_PVT_H_
#include "osal/osal.h"
#include "common/tusb_fifo.h"
@ -76,6 +76,8 @@ uint8_t* usbh_get_enum_buf(void);
void usbh_int_set(bool enabled);
void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr);
//--------------------------------------------------------------------+
// USBH Endpoint API
//--------------------------------------------------------------------+
@ -85,12 +87,10 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t * b
tuh_xfer_cb_t complete_cb, uintptr_t user_data);
TU_ATTR_ALWAYS_INLINE
static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
{
static inline bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) {
return usbh_edpt_xfer_with_callback(dev_addr, ep_addr, buffer, total_bytes, NULL, 0);
}
// Claim an endpoint before submitting a transfer.
// If caller does not make any transfer, it must release endpoint for others.
bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);

922
src/portable/analog/max3421/hcd_max3421.c Normal file
View file

@ -0,0 +1,922 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2023 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "tusb_option.h"
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
#include <stdatomic.h>
#include "host/hcd.h"
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
// Command format is
// Reg [7:3] | 0 [2] | Dir [1] | Ack [0]
enum {
CMDBYTE_WRITE = 0x02,
};
enum {
RCVVFIFO_ADDR = 1u << 3, // 0x08
SNDFIFO_ADDR = 2u << 3, // 0x10
SUDFIFO_ADDR = 4u << 3, // 0x20
RCVBC_ADDR = 6u << 3, // 0x30
SNDBC_ADDR = 7u << 3, // 0x38
USBIRQ_ADDR = 13u << 3, // 0x68
USBIEN_ADDR = 14u << 3, // 0x70
USBCTL_ADDR = 15u << 3, // 0x78
CPUCTL_ADDR = 16u << 3, // 0x80
PINCTL_ADDR = 17u << 3, // 0x88
REVISION_ADDR = 18u << 3, // 0x90
HIRQ_ADDR = 25u << 3, // 0xC8
HIEN_ADDR = 26u << 3, // 0xD0
MODE_ADDR = 27u << 3, // 0xD8
PERADDR_ADDR = 28u << 3, // 0xE0
HCTL_ADDR = 29u << 3, // 0xE8
HXFR_ADDR = 30u << 3, // 0xF0
HRSL_ADDR = 31u << 3, // 0xF8
};
enum {
USBIRQ_OSCOK_IRQ = 1u << 0,
USBIRQ_NOVBUS_IRQ = 1u << 5,
USBIRQ_VBUS_IRQ = 1u << 6,
};
enum {
USBCTL_PWRDOWN = 1u << 4,
USBCTL_CHIPRES = 1u << 5,
};
enum {
CPUCTL_IE = 1u << 0,
CPUCTL_PULSEWID0 = 1u << 6,
CPUCTL_PULSEWID1 = 1u << 7,
};
enum {
PINCTL_GPXA = 1u << 0,
PINCTL_GPXB = 1u << 1,
PINCTL_POSINT = 1u << 2,
PINCTL_INTLEVEL = 1u << 3,
PINCTL_FDUPSPI = 1u << 4,
};
enum {
HIRQ_BUSEVENT_IRQ = 1u << 0,
HIRQ_RWU_IRQ = 1u << 1,
HIRQ_RCVDAV_IRQ = 1u << 2,
HIRQ_SNDBAV_IRQ = 1u << 3,
HIRQ_SUSDN_IRQ = 1u << 4,
HIRQ_CONDET_IRQ = 1u << 5,
HIRQ_FRAME_IRQ = 1u << 6,
HIRQ_HXFRDN_IRQ = 1u << 7,
};
enum {
MODE_HOST = 1u << 0,
MODE_LOWSPEED = 1u << 1,
MODE_HUBPRE = 1u << 2,
MODE_SOFKAENAB = 1u << 3,
MODE_SEPIRQ = 1u << 4,
MODE_DELAYISO = 1u << 5,
MODE_DMPULLDN = 1u << 6,
MODE_DPPULLDN = 1u << 7,
};
enum {
HCTL_BUSRST = 1u << 0,
HCTL_FRMRST = 1u << 1,
HCTL_SAMPLEBUS = 1u << 2,
HCTL_SIGRSM = 1u << 3,
HCTL_RCVTOG0 = 1u << 4,
HCTL_RCVTOG1 = 1u << 5,
HCTL_SNDTOG0 = 1u << 6,
HCTL_SNDTOG1 = 1u << 7,
};
enum {
HXFR_EPNUM_MASK = 0x0f,
HXFR_SETUP = 1u << 4,
HXFR_OUT_NIN = 1u << 5,
HXFR_ISO = 1u << 6,
HXFR_HS = 1u << 7,
};
enum {
HRSL_RESULT_MASK = 0x0f,
HRSL_RCVTOGRD = 1u << 4,
HRSL_SNDTOGRD = 1u << 5,
HRSL_KSTATUS = 1u << 6,
HRSL_JSTATUS = 1u << 7,
};
enum {
HRSL_SUCCESS = 0,
HRSL_BUSY,
HRSL_BAD_REQ,
HRSL_UNDEF,
HRSL_NAK,
HRSL_STALL,
HRSL_TOG_ERR,
HRSL_WRONG_PID,
HRSL_BAD_BYTECOUNT,
HRSL_PID_ERR,
HRSL_PKT_ERR,
HRSL_CRC_ERR,
HRSL_K_ERR,
HRSL_J_ERR,
HRSL_TIMEOUT,
HRSL_BABBLE,
};
enum {
DEFAULT_HIEN = HIRQ_CONDET_IRQ | HIRQ_FRAME_IRQ | HIRQ_HXFRDN_IRQ | HIRQ_RCVDAV_IRQ
};
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
typedef struct {
struct TU_ATTR_PACKED {
uint8_t ep_dir : 1;
uint8_t is_iso : 1;
uint8_t is_setup : 1;
uint8_t data_toggle : 1;
uint8_t xfer_pending : 1;
uint8_t xfer_complete : 1;
};
struct TU_ATTR_PACKED {
uint8_t daddr : 4;
uint8_t ep_num : 4;
};
uint16_t packet_size;
uint16_t total_len;
uint16_t xferred_len;
uint8_t* buf;
} max3421_ep_t;
typedef struct {
// cached register
uint8_t sndbc;
uint8_t hirq;
uint8_t hien;
uint8_t mode;
uint8_t peraddr;
uint8_t hxfr;
atomic_flag busy; // busy transferring
volatile uint16_t frame_count;
max3421_ep_t ep[CFG_TUH_MAX3421_ENDPOINT_TOTAL]; // [0] is reserved for addr0
OSAL_MUTEX_DEF(spi_mutexdef);
#if OSAL_MUTEX_REQUIRED
osal_mutex_t spi_mutex;
#endif
} max3421_data_t;
static max3421_data_t _hcd_data;
//--------------------------------------------------------------------+
// API: SPI transfer with MAX3421E, must be implemented by application
//--------------------------------------------------------------------+
void tuh_max3421_spi_cs_api(uint8_t rhport, bool active);
bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const * tx_buf, size_t tx_len, uint8_t * rx_buf, size_t rx_len);
void tuh_max3421_int_api(uint8_t rhport, bool enabled);
static void handle_connect_irq(uint8_t rhport, bool in_isr);
static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr);
//--------------------------------------------------------------------+
// SPI Helper
//--------------------------------------------------------------------+
static void max3421_spi_lock(uint8_t rhport, bool in_isr) {
// disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr
if (!in_isr) {
(void) osal_mutex_lock(_hcd_data.spi_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
tuh_max3421_int_api(rhport, false);
}
// assert CS
tuh_max3421_spi_cs_api(rhport, true);
}
static void max3421_spi_unlock(uint8_t rhport, bool in_isr) {
// de-assert CS
tuh_max3421_spi_cs_api(rhport, false);
// mutex unlock and re-enable interrupt
if (!in_isr) {
tuh_max3421_int_api(rhport, true);
(void) osal_mutex_unlock(_hcd_data.spi_mutex);
}
}
static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) {
uint8_t hirq;
reg |= CMDBYTE_WRITE;
max3421_spi_lock(rhport, in_isr);
tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 1);
_hcd_data.hirq = hirq;
tuh_max3421_spi_xfer_api(rhport, buffer, len, NULL, 0);
max3421_spi_unlock(rhport, in_isr);
}
static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) {
uint8_t hirq;
uint8_t const reg = RCVVFIFO_ADDR;
max3421_spi_lock(rhport, in_isr);
tuh_max3421_spi_xfer_api(rhport, &reg, 1, &hirq, 0);
_hcd_data.hirq = hirq;
tuh_max3421_spi_xfer_api(rhport, NULL, 0, buffer, len);
max3421_spi_unlock(rhport, in_isr);
}
static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) {
uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data};
uint8_t rx_buf[2] = {0, 0};
max3421_spi_lock(rhport, in_isr);
tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
max3421_spi_unlock(rhport, in_isr);
// HIRQ register since we are in full-duplex mode
_hcd_data.hirq = rx_buf[0];
}
static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) {
uint8_t tx_buf[2] = {reg, 0};
uint8_t rx_buf[2] = {0, 0};
max3421_spi_lock(rhport, in_isr);
bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, 2, rx_buf, 2);
max3421_spi_unlock(rhport, in_isr);
_hcd_data.hirq = rx_buf[0];
return ret ? rx_buf[1] : 0;
}
static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) {
reg_write(rhport, HIRQ_ADDR, data, in_isr);
// HIRQ write 1 is clear
_hcd_data.hirq &= ~data;
}
static inline void hien_write(uint8_t rhport, uint8_t data, bool in_isr) {
_hcd_data.hien = data;
reg_write(rhport, HIEN_ADDR, data, in_isr);
}
static inline void mode_write(uint8_t rhport, uint8_t data, bool in_isr) {
_hcd_data.mode = data;
reg_write(rhport, MODE_ADDR, data, in_isr);
}
static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) {
if ( _hcd_data.peraddr == data ) return; // no need to change address
_hcd_data.peraddr = data;
reg_write(rhport, PERADDR_ADDR, data, in_isr);
}
static inline void hxfr_write(uint8_t rhport, uint8_t data, bool in_isr) {
_hcd_data.hxfr = data;
reg_write(rhport, HXFR_ADDR, data, in_isr);
}
static inline void sndbc_write(uint8_t rhport, uint8_t data, bool in_isr) {
_hcd_data.sndbc = data;
reg_write(rhport, SNDBC_ADDR, data, in_isr);
}
//--------------------------------------------------------------------+
// Endpoint helper
//--------------------------------------------------------------------+
static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
for(size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
max3421_ep_t* ep = &_hcd_data.ep[i];
// for control endpoint, skip direction check
if (daddr == ep->daddr && ep_num == ep->ep_num && (ep_dir == ep->ep_dir || ep_num == 0)) {
return ep;
}
}
return NULL;
}
// daddr = 0 and ep_num = 0 means find a free (allocate) endpoint
TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * allocate_ep(void) {
return find_ep_not_addr0(0, 0, 0);
}
TU_ATTR_ALWAYS_INLINE static inline max3421_ep_t * find_opened_ep(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) {
if (daddr == 0 && ep_num == 0) {
return &_hcd_data.ep[0];
}else{
return find_ep_not_addr0(daddr, ep_num, ep_dir);
}
}
// free all endpoints belong to device address
static void free_ep(uint8_t daddr) {
for (size_t i=1; i<CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
max3421_ep_t* ep = &_hcd_data.ep[i];
if (ep->daddr == daddr) {
tu_memclr(ep, sizeof(max3421_ep_t));
}
}
}
static max3421_ep_t * find_next_pending_ep(max3421_ep_t * cur_ep) {
size_t const idx = cur_ep - _hcd_data.ep;
// starting from next endpoint
for (size_t i = idx + 1; i < CFG_TUH_MAX3421_ENDPOINT_TOTAL; i++) {
max3421_ep_t* ep = &_hcd_data.ep[i];
if (ep->xfer_pending && ep->packet_size) {
// TU_LOG3("next pending i = %u\n", i);
return ep;
}
}
// wrap around including current endpoint
for (size_t i = 0; i <= idx; i++) {
max3421_ep_t* ep = &_hcd_data.ep[i];
if (ep->xfer_pending && ep->packet_size) {
// TU_LOG3("next pending i = %u\n", i);
return ep;
}
}
return NULL;
}
//--------------------------------------------------------------------+
// Controller API
//--------------------------------------------------------------------+
// optional hcd configuration, called by tuh_configure()
bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
(void) rhport;
(void) cfg_id;
(void) cfg_param;
return false;
}
// Initialize controller to host mode
bool hcd_init(uint8_t rhport) {
(void) rhport;
tuh_max3421_int_api(rhport, false);
tuh_max3421_spi_cs_api(rhport, false);
TU_LOG2_INT(sizeof(max3421_ep_t));
TU_LOG2_INT(sizeof(max3421_data_t));
tu_memclr(&_hcd_data, sizeof(_hcd_data));
_hcd_data.peraddr = 0xff; // invalid
#if OSAL_MUTEX_REQUIRED
_hcd_data.spi_mutex = osal_mutex_create(&_hcd_data.spi_mutexdef);
#endif
// full duplex, interrupt negative edge
reg_write(rhport, PINCTL_ADDR, PINCTL_FDUPSPI, false);
// V1 is 0x01, V2 is 0x12, V3 is 0x13
// uint8_t const revision = reg_read(rhport, REVISION_ADDR, false);
// TU_LOG2_HEX(revision);
// reset
reg_write(rhport, USBCTL_ADDR, USBCTL_CHIPRES, false);
reg_write(rhport, USBCTL_ADDR, 0, false);
while( !(reg_read(rhport, USBIRQ_ADDR, false) & USBIRQ_OSCOK_IRQ) ) {
// wait for oscillator to stabilize
}
// Mode: Host and DP/DM pull down
mode_write(rhport, MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST, false);
// frame reset & bus reset, this will trigger CONDET IRQ if device is already connected
reg_write(rhport, HCTL_ADDR, HCTL_BUSRST | HCTL_FRMRST, false);
// clear all previously pending IRQ
hirq_write(rhport, 0xff, false);
// Enable IRQ
hien_write(rhport, DEFAULT_HIEN, false);
tuh_max3421_int_api(rhport, true);
// Enable Interrupt pin
reg_write(rhport, CPUCTL_ADDR, CPUCTL_IE, false);
return true;
}
// Enable USB interrupt
// Not actually enable GPIO interrupt, just set variable to prevent handler to process
void hcd_int_enable (uint8_t rhport) {
tuh_max3421_int_api(rhport, true);
}
// Disable USB interrupt
// Not actually disable GPIO interrupt, just set variable to prevent handler to process
void hcd_int_disable(uint8_t rhport) {
tuh_max3421_int_api(rhport, false);
}
// Get frame number (1ms)
uint32_t hcd_frame_number(uint8_t rhport) {
(void) rhport;
return (uint32_t ) _hcd_data.frame_count;
}
//--------------------------------------------------------------------+
// Port API
//--------------------------------------------------------------------+
// Get the current connect status of roothub port
bool hcd_port_connect_status(uint8_t rhport) {
(void) rhport;
return (_hcd_data.mode & MODE_SOFKAENAB) ? true : false;
}
// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
void hcd_port_reset(uint8_t rhport) {
reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, false);
}
// Complete bus reset sequence, may be required by some controllers
void hcd_port_reset_end(uint8_t rhport) {
reg_write(rhport, HCTL_ADDR, 0, false);
}
// Get port link speed
tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
(void) rhport;
return (_hcd_data.mode & MODE_LOWSPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
}
// HCD closes all opened endpoints belong to this device
void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
(void) rhport;
(void) dev_addr;
}
//--------------------------------------------------------------------+
// Endpoints API
//--------------------------------------------------------------------+
// Open an endpoint
bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc) {
(void) rhport;
(void) daddr;
uint8_t ep_num = tu_edpt_number(ep_desc->bEndpointAddress);
uint8_t ep_dir = tu_edpt_dir(ep_desc->bEndpointAddress);
max3421_ep_t * ep;
if (daddr == 0 && ep_num == 0) {
ep = &_hcd_data.ep[0];
}else {
ep = allocate_ep();
TU_ASSERT(ep);
ep->daddr = daddr;
ep->ep_num = ep_num;
ep->ep_dir = ep_dir;
}
if ( TUSB_XFER_ISOCHRONOUS == ep_desc->bmAttributes.xfer ) {
ep->is_iso = 1;
}
ep->packet_size = tu_edpt_packet_size(ep_desc);
return true;
}
void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
// Page 12: Programming BULK-OUT Transfers
// TODO double buffered
if (switch_ep) {
peraddr_write(rhport, ep->daddr, in_isr);
uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0);
reg_write(rhport, HCTL_ADDR, hctl, in_isr);
}
uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size);
TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,);
if (xact_len) {
fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr);
}
sndbc_write(rhport, xact_len, in_isr);
uint8_t hxfr = ep->ep_num | HXFR_OUT_NIN | (ep->is_iso ? HXFR_ISO : 0);
hxfr_write(rhport, hxfr, in_isr);
}
void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
// Page 13: Programming BULK-IN Transfers
if (switch_ep) {
peraddr_write(rhport, ep->daddr, in_isr);
uint8_t const hctl = (ep->data_toggle ? HCTL_RCVTOG1 : HCTL_RCVTOG0);
reg_write(rhport, HCTL_ADDR, hctl, in_isr);
}
uint8_t hxfr = ep->ep_num | (ep->is_iso ? HXFR_ISO : 0);
hxfr_write(rhport, hxfr, in_isr);
}
TU_ATTR_ALWAYS_INLINE static inline void xact_inout(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) {
if (ep->ep_num == 0 ) {
// setup
if (ep->is_setup) {
peraddr_write(rhport, ep->daddr, in_isr);
fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr);
hxfr_write(rhport, HXFR_SETUP, in_isr);
return;
}
// status
if (ep->buf == NULL || ep->total_len == 0) {
uint8_t const hxfr = HXFR_HS | (ep->ep_dir ? 0 : HXFR_OUT_NIN);
peraddr_write(rhport, ep->daddr, in_isr);
hxfr_write(rhport, hxfr, in_isr);
return;
}
}
if (ep->ep_dir) {
xact_in(rhport, ep, switch_ep, in_isr);
}else {
xact_out(rhport, ep, switch_ep, in_isr);
}
}
// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
uint8_t const ep_num = tu_edpt_number(ep_addr);
uint8_t const ep_dir = tu_edpt_dir(ep_addr);
max3421_ep_t* ep = find_opened_ep(daddr, ep_num, ep_dir);
TU_VERIFY(ep);
// control transfer can switch direction
ep->ep_dir = ep_dir;
ep->buf = buffer;
ep->total_len = buflen;
ep->xferred_len = 0;
ep->xfer_complete = 0;
ep->xfer_pending = 1;
if ( ep_num == 0 ) {
ep->is_setup = 0;
ep->data_toggle = 1;
}
// carry out transfer if not busy
if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
xact_inout(rhport, ep, true, false);
} else {
return true;
}
return true;
}
// Abort a queued transfer. Note: it can only abort transfer that has not been started
// Return true if a queued transfer is aborted, false if there is no transfer to abort
bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
(void) rhport;
(void) dev_addr;
(void) ep_addr;
return false;
}
// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8]) {
(void) rhport;
max3421_ep_t* ep = find_opened_ep(daddr, 0, 0);
TU_ASSERT(ep);
ep->ep_dir = 0;
ep->is_setup = 1;
ep->buf = (uint8_t*)(uintptr_t) setup_packet;
ep->total_len = 8;
ep->xferred_len = 0;
ep->xfer_complete = 0;
ep->xfer_pending = 1;
// carry out transfer if not busy
if ( !atomic_flag_test_and_set(&_hcd_data.busy) ) {
xact_inout(rhport, ep, true, false);
}
return true;
}
// clear stall, data toggle is also reset to DATA0
bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
(void) rhport;
(void) dev_addr;
(void) ep_addr;
return false;
}
//--------------------------------------------------------------------+
// Interrupt Handler
//--------------------------------------------------------------------+
static void handle_connect_irq(uint8_t rhport, bool in_isr) {
uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr);
uint8_t const jk = hrsl & (HRSL_JSTATUS | HRSL_KSTATUS);
uint8_t new_mode = MODE_DPPULLDN | MODE_DMPULLDN | MODE_HOST;
TU_LOG2_HEX(jk);
switch(jk) {
case 0x00: // SEO is disconnected
case (HRSL_JSTATUS | HRSL_KSTATUS): // SE1 is illegal
mode_write(rhport, new_mode, in_isr);
// port reset anyway, this will help to stable bus signal for next connection
reg_write(rhport, HCTL_ADDR, HCTL_BUSRST, in_isr);
hcd_event_device_remove(rhport, in_isr);
reg_write(rhport, HCTL_ADDR, 0, in_isr);
break;
default: {
// Bus Reset also cause CONDET IRQ, skip if we are already connected and doing bus reset
if ((_hcd_data.hirq & HIRQ_BUSEVENT_IRQ) && (_hcd_data.mode & MODE_SOFKAENAB)) {
break;
}
// Low speed if (LS = 1 and J-state) or (LS = 0 and K-State)
// However, since we are always in full speed mode, we can just check J-state
if (jk == HRSL_KSTATUS) {
new_mode |= MODE_LOWSPEED;
TU_LOG3("Low speed\n");
}else {
TU_LOG3("Full speed\n");
}
new_mode |= MODE_SOFKAENAB;
mode_write(rhport, new_mode, in_isr);
// FIXME multiple MAX3421 rootdevice address is not 1
uint8_t const daddr = 1;
free_ep(daddr);
hcd_event_device_attach(rhport, in_isr);
break;
}
}
}
static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl) {
uint8_t const ep_addr = tu_edpt_addr(ep->ep_num, ep->ep_dir);
// save data toggle
if (ep->ep_dir) {
ep->data_toggle = (hrsl & HRSL_RCVTOGRD) ? 1 : 0;
}else {
ep->data_toggle = (hrsl & HRSL_SNDTOGRD) ? 1 : 0;
}
ep->xfer_pending = 0;
hcd_event_xfer_complete(ep->daddr, ep_addr, ep->xferred_len, result, true);
// Find next pending endpoint
max3421_ep_t *next_ep = find_next_pending_ep(ep);
if (next_ep) {
xact_inout(rhport, next_ep, true, true);
}else {
// no more pending
atomic_flag_clear(&_hcd_data.busy);
}
}
static void handle_xfer_done(uint8_t rhport) {
uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, true);
uint8_t const hresult = hrsl & HRSL_RESULT_MASK;
uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0;
uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1;
max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir);
TU_VERIFY(ep, );
xfer_result_t xfer_result;
switch(hresult) {
case HRSL_SUCCESS:
xfer_result = XFER_RESULT_SUCCESS;
break;
case HRSL_STALL:
xfer_result = XFER_RESULT_STALLED;
break;
case HRSL_NAK:
if (ep_num == 0) {
// NAK on control, retry immediately
hxfr_write(rhport, _hcd_data.hxfr, true);
}else {
// NAK on non-control, find next pending to switch
max3421_ep_t *next_ep = find_next_pending_ep(ep);
if (ep == next_ep) {
// this endpoint is only one pending, retry immediately
hxfr_write(rhport, _hcd_data.hxfr, true);
}else if (next_ep) {
// switch to next pending TODO could have issue with double buffered if not clear previously out data
xact_inout(rhport, next_ep, true, true);
}else {
TU_ASSERT(false,);
}
}
return;
case HRSL_BAD_REQ:
// occurred when initialized without any pending transfer. Skip for now
return;
default:
TU_LOG3("HRSL: %02X\r\n", hrsl);
xfer_result = XFER_RESULT_FAILED;
break;
}
if (xfer_result != XFER_RESULT_SUCCESS) {
xfer_complete_isr(rhport, ep, xfer_result, hrsl);
return;
}
if (ep_dir) {
// IN transfer: fifo data is already received in RCVDAV IRQ
if ( hxfr_type & HXFR_HS ) {
ep->xfer_complete = 1;
}
// short packet or all bytes transferred
if ( ep->xfer_complete ) {
xfer_complete_isr(rhport, ep, xfer_result, hrsl);
}else {
// more to transfer
hxfr_write(rhport, _hcd_data.hxfr, true);
}
} else {
// SETUP or OUT transfer
uint8_t xact_len;
if (hxfr_type & HXFR_SETUP) {
xact_len = 8;
} else if (hxfr_type & HXFR_HS) {
xact_len = 0;
} else {
xact_len = _hcd_data.sndbc;
}
ep->xferred_len += xact_len;
ep->buf += xact_len;
if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) {
xfer_complete_isr(rhport, ep, xfer_result, hrsl);
} else {
// more to transfer
xact_out(rhport, ep, false, true);
}
}
}
#if CFG_TUSB_DEBUG >= 3
void print_hirq(uint8_t hirq) {
TU_LOG3_HEX(hirq);
if (hirq & HIRQ_HXFRDN_IRQ) TU_LOG3(" HXFRDN");
if (hirq & HIRQ_FRAME_IRQ) TU_LOG3(" FRAME");
if (hirq & HIRQ_CONDET_IRQ) TU_LOG3(" CONDET");
if (hirq & HIRQ_SUSDN_IRQ) TU_LOG3(" SUSDN");
if (hirq & HIRQ_SNDBAV_IRQ) TU_LOG3(" SNDBAV");
if (hirq & HIRQ_RCVDAV_IRQ) TU_LOG3(" RCVDAV");
if (hirq & HIRQ_RWU_IRQ) TU_LOG3(" RWU");
if (hirq & HIRQ_BUSEVENT_IRQ) TU_LOG3(" BUSEVENT");
TU_LOG3("\r\n");
}
#else
#define print_hirq(hirq)
#endif
// Interrupt Handler
void hcd_int_handler(uint8_t rhport) {
uint8_t hirq = reg_read(rhport, HIRQ_ADDR, true) & _hcd_data.hien;
if (!hirq) return;
// print_hirq(hirq);
if (hirq & HIRQ_FRAME_IRQ) {
_hcd_data.frame_count++;
}
if (hirq & HIRQ_CONDET_IRQ) {
handle_connect_irq(rhport, true);
}
// queue more transfer in handle_xfer_done() can cause hirq to be set again while external IRQ may not catch and/or
// not call this handler again. So we need to loop until all IRQ are cleared
while ( hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ) ) {
if ( hirq & HIRQ_RCVDAV_IRQ ) {
uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK;
max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1);
uint8_t xact_len;
// RCVDAV_IRQ can trigger 2 times (dual buffered)
while ( hirq & HIRQ_RCVDAV_IRQ ) {
uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, true);
xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len);
if ( xact_len ) {
fifo_read(rhport, ep->buf, xact_len, true);
ep->buf += xact_len;
ep->xferred_len += xact_len;
}
// ack RCVDVAV IRQ
hirq_write(rhport, HIRQ_RCVDAV_IRQ, true);
hirq = reg_read(rhport, HIRQ_ADDR, true);
}
if ( xact_len < ep->packet_size || ep->xferred_len >= ep->total_len ) {
ep->xfer_complete = 1;
}
}
if ( hirq & HIRQ_HXFRDN_IRQ ) {
hirq_write(rhport, HIRQ_HXFRDN_IRQ, true);
handle_xfer_done(rhport);
}
hirq = reg_read(rhport, HIRQ_ADDR, true);
}
// clear all interrupt except SNDBAV_IRQ (never clear by us). Note RCVDAV_IRQ, HXFRDN_IRQ already clear while processing
hirq &= ~HIRQ_SNDBAV_IRQ;
if ( hirq ) {
hirq_write(rhport, hirq, true);
}
}
#endif

9
src/tusb.h
View file

@ -64,7 +64,10 @@
#if CFG_TUH_VENDOR
#include "class/vendor/vendor_host.h"
#endif
#else
#ifndef tuh_int_handler
#define tuh_int_handler(_x)
#endif
#endif
//------------- DEVICE -------------//
@ -118,6 +121,10 @@
#if CFG_TUD_BTH
#include "class/bth/bth_device.h"
#endif
#else
#ifndef tud_int_handler
#define tud_int_handler(_x)
#endif
#endif