adafruit-mirror/ArduinoCore-samd
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Import Arduino M0 bootloader

Browse source
This commit is contained in:
Martino Facchin 2016-11-22 12:15:39 +01:00
parent 59cdbd5c68
commit 62dc740a8b
171 changed files with 78897 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
bootloaders/mzero/Bootloader_D21/Bootloader_D21.atsln Normal file
View file

@ -0,0 +1,20 @@

Microsoft Visual Studio Solution File, Format Version 11.00
# Atmel Studio Solution File, Format Version 11.00
Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "Bootloader_D21", "Bootloader_D21.cproj", "{7ABD2862-543D-4184-845E-8DC3E340E2CC}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
Debug|ARM = Debug|ARM
Release|ARM = Release|ARM
EndGlobalSection
GlobalSection(ProjectConfigurationPlatforms) = postSolution
{7ABD2862-543D-4184-845E-8DC3E340E2CC}.Debug|ARM.ActiveCfg = Debug|ARM
{7ABD2862-543D-4184-845E-8DC3E340E2CC}.Debug|ARM.Build.0 = Debug|ARM
{7ABD2862-543D-4184-845E-8DC3E340E2CC}.Release|ARM.ActiveCfg = Release|ARM
{7ABD2862-543D-4184-845E-8DC3E340E2CC}.Release|ARM.Build.0 = Release|ARM
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
EndGlobalSection
EndGlobal

BIN
bootloaders/mzero/Bootloader_D21/Bootloader_D21.atsuo Normal file
View file

Binary file not shown.

1033
bootloaders/mzero/Bootloader_D21/Bootloader_D21.cproj Normal file
View file

File diff suppressed because it is too large Load diff

BIN
bootloaders/mzero/Bootloader_D21/atmel_devices_cdc.cat Normal file
View file

Binary file not shown.

182
bootloaders/mzero/Bootloader_D21/atmel_devices_cdc.inf Normal file
View file

@ -0,0 +1,182 @@
; Windows 2000, XP, Vista, 7 and 8 (x32 and x64) setup file for Atmel CDC Devices
; Copyright (c) 2000-2013 ATMEL, Inc.
[Version]
Signature = "$Windows NT$"
Class = Ports
ClassGuid = {4D36E978-E325-11CE-BFC1-08002BE10318}
Provider = %Manufacturer%
LayoutFile = layout.inf
CatalogFile = atmel_devices_cdc.cat
DriverVer = 01/08/2013,6.0.0.0
;----------------------------------------------------------
; Targets
;----------------------------------------------------------
[Manufacturer]
%Manufacturer%=DeviceList, NTAMD64, NTIA64, NT
[DeviceList]
%ATMEL_CDC_XPLAINED%=DriverInstall, USB\VID_03EB&PID_2122
%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall, USB\VID_03EB&PID_214B
%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall, USB\VID_03EB&PID_214A
%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall, USB\VID_03EB&PID_2307
%ATMEL_CDC_EVK1XXX%=DriverInstall, USB\VID_03EB&PID_2310
%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall, USB\VID_03EB&PID_2404
%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall, USB\VID_03EB&PID_2421&MI_00
%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall, USB\VID_03EB&PID_2424&MI_00
%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall, USB\VID_03EB&PID_2425&MI_00
%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall, USB\VID_03EB&PID_2425&MI_02
%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall, USB\VID_03EB&PID_2426&MI_00
%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall, USB\VID_03EB&PID_2426&MI_02
%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall, USB\VID_03EB&PID_2426&MI_04
%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall, USB\VID_03EB&PID_2426&MI_06
%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall, USB\VID_03EB&PID_2426&MI_08
%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall, USB\VID_03EB&PID_2426&MI_0A
%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall, USB\VID_03EB&PID_2426&MI_0C
[DeviceList.NTAMD64]
%ATMEL_CDC_XPLAINED%=DriverInstall.NTamd64, USB\VID_03EB&PID_2122
%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NTamd64, USB\VID_03EB&PID_214B
%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NTamd64, USB\VID_03EB&PID_214A
%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2307
%ATMEL_CDC_EVK1XXX%=DriverInstall.NTamd64, USB\VID_03EB&PID_2310
%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2404
%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2421&MI_00
%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2424&MI_00
%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_00
%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_02
%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_00
%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_02
%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_04
%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_06
%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_08
%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0A
%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0C
[DeviceList.NTIA64]
%ATMEL_CDC_XPLAINED%=DriverInstall.NTamd64, USB\VID_03EB&PID_2122
%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NTamd64, USB\VID_03EB&PID_214B
%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NTamd64, USB\VID_03EB&PID_214A
%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2307
%ATMEL_CDC_EVK1XXX%=DriverInstall.NTamd64, USB\VID_03EB&PID_2310
%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2404
%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2421&MI_00
%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2424&MI_00
%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_00
%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_02
%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_00
%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_02
%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_04
%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_06
%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_08
%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0A
%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0C
[DeviceList.NT]
%ATMEL_CDC_XPLAINED%=DriverInstall.NT, USB\VID_03EB&PID_2122
%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NT, USB\VID_03EB&PID_214B
%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NT, USB\VID_03EB&PID_214A
%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NT, USB\VID_03EB&PID_2307
%ATMEL_CDC_EVK1XXX%=DriverInstall.NT, USB\VID_03EB&PID_2310
%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NT, USB\VID_03EB&PID_2404
%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NT, USB\VID_03EB&PID_2421&MI_00
%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NT, USB\VID_03EB&PID_2424&MI_00
%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NT, USB\VID_03EB&PID_2425&MI_00
%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NT, USB\VID_03EB&PID_2425&MI_02
%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_00
%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_02
%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_04
%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_06
%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_08
%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_0A
%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_0C
;----------------------------------------------------------
; Windows 2000, XP, Vista, Windows 7, Windows 8 - 32bit
;----------------------------------------------------------
[Reader_Install.NTx86]
[DestinationDirs]
DefaultDestDir=12
DriverInstall.NT.Copy=12
[DriverInstall.NT]
include=mdmcpq.inf
CopyFiles=DriverInstall.NT.Copy
AddReg=DriverInstall.NT.AddReg
[DriverInstall.NT.Copy]
usbser.sys
[DriverInstall.NT.AddReg]
HKR,,DevLoader,,*ntkern
HKR,,NTMPDriver,,usbser.sys
HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
[DriverInstall.NT.Services]
AddService = usbser, 0x00000002, DriverService.NT
[DriverService.NT]
DisplayName = %Serial.SvcDesc%
ServiceType = 1 ; SERVICE_KERNEL_DRIVER
StartType = 3 ; SERVICE_DEMAND_START
ErrorControl = 1 ; SERVICE_ERROR_NORMAL
ServiceBinary = %12%\usbser.sys
LoadOrderGroup = Base
;----------------------------------------------------------
; Windows XP, Vista, Windows 7, Windows 8 - 64bit
;----------------------------------------------------------
[DriverInstall.NTamd64]
include=mdmcpq.inf
CopyFiles=DriverCopyFiles.NTamd64
AddReg=DriverInstall.NTamd64.AddReg
[DriverCopyFiles.NTamd64]
usbser.sys,,,0x20
[DriverInstall.NTamd64.AddReg]
HKR,,DevLoader,,*ntkern
HKR,,NTMPDriver,,usbser.sys
HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
[DriverInstall.NTamd64.Services]
AddService=usbser, 0x00000002, DriverService.NTamd64
[DriverService.NTamd64]
DisplayName=%Serial.SvcDesc%
ServiceType=1
StartType=3
ErrorControl=1
ServiceBinary=%12%\usbser.sys
;----------------------------------------------------------
; String
;----------------------------------------------------------
[Strings]
Manufacturer = "ATMEL, Inc."
ATMEL_CDC_XPLAINED = "XPLAINED Virtual Com Port"
ATMEL_CDC_USB_ZIGBIT_Sub = "ZigBit SubGHz USBstick Com Port"
ATMEL_CDC_USB_ZIGBIT_2_4 = "ZigBit 2.4GHz USBstick Com Port"
ATMEL_CDC_SFW_EXAMPLE = "Communication Device Class SFW example"
ATMEL_CDC_EVK1XXX = "EVK1XXX Virtual Com Port"
ATMEL_CDC_ASF_EXAMPLE = "Communication Device Class ASF example"
ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2 = "Communication Device Class ASF composite example 2"
ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4 = "Communication Device Class ASF composite example 4"
ATMEL_CDC_ASF_EXAMPLE2_COM1 = "Communication Device Class ASF example2, COM1"
ATMEL_CDC_ASF_EXAMPLE2_COM2 = "Communication Device Class ASF example2, COM2"
ATMEL_CDC_ASF_EXAMPLE3_COM1 = "Communication Device Class ASF example3, COM1"
ATMEL_CDC_ASF_EXAMPLE3_COM2 = "Communication Device Class ASF example3, COM2"
ATMEL_CDC_ASF_EXAMPLE3_COM3 = "Communication Device Class ASF example3, COM3"
ATMEL_CDC_ASF_EXAMPLE3_COM4 = "Communication Device Class ASF example3, COM4"
ATMEL_CDC_ASF_EXAMPLE3_COM5 = "Communication Device Class ASF example3, COM5"
ATMEL_CDC_ASF_EXAMPLE3_COM6 = "Communication Device Class ASF example3, COM6"
ATMEL_CDC_ASF_EXAMPLE3_COM7 = "Communication Device Class ASF example3, COM7"
Serial.SvcDesc = "USB Serial emulation driver"

383
bootloaders/mzero/Bootloader_D21/src/ASF/common/boards/board.h Normal file
View file

@ -0,0 +1,383 @@
/**
* \file
*
* \brief Standard board header file.
*
* This file includes the appropriate board header file according to the
* defined board (parameter BOARD).
*
* Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/**
* \defgroup group_common_boards Generic board support
*
* The generic board support module includes board-specific definitions
* and function prototypes, such as the board initialization function.
*
* \{
*/
#include "compiler.h"
#ifdef __cplusplus
extern "C" {
#endif
/*! \name Base Boards
*/
//! @{
#define EVK1100 1 //!< AT32UC3A EVK1100 board.
#define EVK1101 2 //!< AT32UC3B EVK1101 board.
#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board.
#define EVK1104 4 //!< AT32UC3A3 EVK1104 board.
#define EVK1105 5 //!< AT32UC3A EVK1105 board.
#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board.
#define UC3L_EK 7 //!< AT32UC3L-EK board.
#define XPLAIN 8 //!< ATxmega128A1 Xplain board.
#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board.
#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board.
#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board.
#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board.
#define STK600_RCUC3D 16 //!< STK600 RCUC3D board.
#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board.
#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board.
#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board.
#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board.
#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board
#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board
#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board
#define STK600_RC044X 24 //!< STK600 with RC044X routing card board.
#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board.
#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board.
#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board.
#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board.
#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board.
#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards
#define RZ600 31 //!< AT32UC3A RZ600 MCU board
#define SAM3S_EK 32 //!< SAM3S-EK board.
#define SAM3U_EK 33 //!< SAM3U-EK board.
#define SAM3X_EK 34 //!< SAM3X-EK board.
#define SAM3N_EK 35 //!< SAM3N-EK board.
#define SAM3S_EK2 36 //!< SAM3S-EK2 board.
#define SAM4S_EK 37 //!< SAM4S-EK board.
#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board.
#define STK600_MEGA 39 //!< STK600 MEGA board.
#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board.
#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board.
#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board.
#define ARDUINO_DUE_X 43 //!< Arduino Due/X board.
#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board
#define SAM4L_EK 45 //!< SAM4L-EK board.
#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board.
#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board.
#define STK600_RC032X 48 //!< STK600 with RC032X routing card board.
#define SAM4S_EK2 49 //!< SAM4S-EK2 board.
#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board.
#define SAM4E_EK 51 //!< SAM4E-EK board.
#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board.
#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board.
#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board.
#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit
#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit
#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit
#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board.
#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board
#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board.
#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board.
#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board.
#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB
#define SAM4C_EK 64 //!< SAM4C-EK board.
#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board.
#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board.
#define SAM4CP16BMB 67 //!< SAM4CP16BMB board.
#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board.
#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board.
#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board.
#define SAM4CMP_DB 71 //!< SAM4CMP demo board.
#define SAM4CMS_DB 72 //!< SAM4CMS demo board.
#define ATPL230AMB 73 //!< ATPL230AMB board.
#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board.
#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices
#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family.
#define USER_BOARD 99 //!< User-reserved board (if any).
#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader)
//! @}
/*! \name Extension Boards
*/
//! @{
#define EXT1102 1 //!< AT32UC3B EXT1102 board
#define MC300 2 //!< AT32UC3 MC300 board
#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1
#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2
#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board
#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board
#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A"
#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600
#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600
#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600
#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard
#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board
#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any).
//! @}
#if BOARD == EVK1100
# include "evk1100/evk1100.h"
#elif BOARD == EVK1101
# include "evk1101/evk1101.h"
#elif BOARD == UC3C_EK
# include "uc3c_ek/uc3c_ek.h"
#elif BOARD == EVK1104
# include "evk1104/evk1104.h"
#elif BOARD == EVK1105
# include "evk1105/evk1105.h"
#elif BOARD == STK600_RCUC3L0
# include "stk600/rcuc3l0/stk600_rcuc3l0.h"
#elif BOARD == UC3L_EK
# include "uc3l_ek/uc3l_ek.h"
#elif BOARD == STK600_RCUC3L4
# include "stk600/rcuc3l4/stk600_rcuc3l4.h"
#elif BOARD == XPLAIN
# include "xplain/xplain.h"
#elif BOARD == STK600_MEGA
/*No header-file to include*/
#elif BOARD == STK600_MEGA_RF
# include "stk600.h"
#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO
# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h"
#elif BOARD == ATMEGA256RFR2_ZIGBIT
# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h"
#elif BOARD == STK600_RC032X
# include "stk600/rc032x/stk600_rc032x.h"
#elif BOARD == STK600_RC044X
# include "stk600/rc044x/stk600_rc044x.h"
#elif BOARD == STK600_RC064X
# include "stk600/rc064x/stk600_rc064x.h"
#elif BOARD == STK600_RC100X
# include "stk600/rc100x/stk600_rc100x.h"
#elif BOARD == UC3_A3_XPLAINED
# include "uc3_a3_xplained/uc3_a3_xplained.h"
#elif BOARD == UC3_L0_XPLAINED
# include "uc3_l0_xplained/uc3_l0_xplained.h"
#elif BOARD == STK600_RCUC3B0
# include "stk600/rcuc3b0/stk600_rcuc3b0.h"
#elif BOARD == STK600_RCUC3D
# include "stk600/rcuc3d/stk600_rcuc3d.h"
#elif BOARD == STK600_RCUC3C0
# include "stk600/rcuc3c0/stk600_rcuc3c0.h"
#elif BOARD == SAMG53_XPLAINED_PRO
# include "samg53_xplained_pro/samg53_xplained_pro.h"
#elif BOARD == XMEGA_B1_XPLAINED
# include "xmega_b1_xplained/xmega_b1_xplained.h"
#elif BOARD == STK600_RC064X_LCDX
# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h"
#elif BOARD == STK600_RC100X_LCDX
# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h"
#elif BOARD == XMEGA_A1_XPLAINED
# include "xmega_a1_xplained/xmega_a1_xplained.h"
#elif BOARD == XMEGA_A1U_XPLAINED_PRO
# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h"
#elif BOARD == UC3_L0_XPLAINED_BC
# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h"
#elif BOARD == SAM3S_EK
# include "sam3s_ek/sam3s_ek.h"
# include "system_sam3s.h"
#elif BOARD == SAM3S_EK2
# include "sam3s_ek2/sam3s_ek2.h"
# include "system_sam3sd8.h"
#elif BOARD == SAM3U_EK
# include "sam3u_ek/sam3u_ek.h"
# include "system_sam3u.h"
#elif BOARD == SAM3X_EK
# include "sam3x_ek/sam3x_ek.h"
# include "system_sam3x.h"
#elif BOARD == SAM3N_EK
# include "sam3n_ek/sam3n_ek.h"
# include "system_sam3n.h"
#elif BOARD == SAM4S_EK
# include "sam4s_ek/sam4s_ek.h"
# include "system_sam4s.h"
#elif BOARD == SAM4S_WPIR_RD
# include "sam4s_wpir_rd/sam4s_wpir_rd.h"
# include "system_sam4s.h"
#elif BOARD == SAM4S_XPLAINED
# include "sam4s_xplained/sam4s_xplained.h"
# include "system_sam4s.h"
#elif BOARD == SAM4S_EK2
# include "sam4s_ek2/sam4s_ek2.h"
# include "system_sam4s.h"
#elif BOARD == MEGA_1284P_XPLAINED
/*No header-file to include*/
#elif BOARD == ARDUINO_DUE_X
# include "arduino_due_x/arduino_due_x.h"
# include "system_sam3x.h"
#elif BOARD == SAM4L_EK
# include "sam4l_ek/sam4l_ek.h"
#elif BOARD == SAM4E_EK
# include "sam4e_ek/sam4e_ek.h"
#elif BOARD == SAMD20_XPLAINED_PRO
# include "samd20_xplained_pro/samd20_xplained_pro.h"
#elif BOARD == SAMD21_XPLAINED_PRO
# include "samd21_xplained_pro/samd21_xplained_pro.h"
#elif BOARD == SAMR21_XPLAINED_PRO
# include "samr21_xplained_pro/samr21_xplained_pro.h"
#elif BOARD == SAMD11_XPLAINED_PRO
# include "samd11_xplained_pro/samd11_xplained_pro.h"
#elif BOARD == SAM4N_XPLAINED_PRO
# include "sam4n_xplained_pro/sam4n_xplained_pro.h"
#elif BOARD == MEGA1284P_XPLAINED_BC
# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h"
#elif BOARD == UC3_L0_QT600
# include "uc3_l0_qt600/uc3_l0_qt600.h"
#elif BOARD == XMEGA_A3BU_XPLAINED
# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h"
#elif BOARD == XMEGA_E5_XPLAINED
# include "xmega_e5_xplained/xmega_e5_xplained.h"
#elif BOARD == UC3B_BOARD_CONTROLLER
# include "uc3b_board_controller/uc3b_board_controller.h"
#elif BOARD == RZ600
# include "rz600/rz600.h"
#elif BOARD == STK600_RCUC3A0
# include "stk600/rcuc3a0/stk600_rcuc3a0.h"
#elif BOARD == ATXMEGA128A1_QT600
# include "atxmega128a1_qt600/atxmega128a1_qt600.h"
#elif BOARD == STK600_RCUC3L3
# include "stk600/rcuc3l3/stk600_rcuc3l3.h"
#elif BOARD == SAM4S_XPLAINED_PRO
# include "sam4s_xplained_pro/sam4s_xplained_pro.h"
#elif BOARD == SAM4L_XPLAINED_PRO
# include "sam4l_xplained_pro/sam4l_xplained_pro.h"
#elif BOARD == SAM4L8_XPLAINED_PRO
# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h"
#elif BOARD == SAM4C_EK
# include "sam4c_ek/sam4c_ek.h"
#elif BOARD == SAM4CMP_DB
# include "sam4cmp_db/sam4cmp_db.h"
#elif BOARD == SAM4CMS_DB
# include "sam4cms_db/sam4cms_db.h"
#elif BOARD == SAM4CP16BMB
# include "sam4cp16bmb/sam4cp16bmb.h"
#elif BOARD == ATPL230AMB
# include "atpl230amb/atpl230amb.h"
#elif BOARD == SIMULATOR_XMEGA_A1
# include "simulator/xmega_a1/simulator_xmega_a1.h"
#elif BOARD == XMEGA_C3_XPLAINED
# include "xmega_c3_xplained/xmega_c3_xplained.h"
#elif BOARD == XMEGA_RF233_ZIGBIT
# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h"
#elif BOARD == XMEGA_A3_REB_CBB
# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h"
#elif BOARD == ATMEGARFX_RCB
# include "atmegarfx_rcb/atmegarfx_rcb.h"
#elif BOARD == RCB256RFR2_XPRO
# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h"
#elif BOARD == XMEGA_RF212B_ZIGBIT
# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h"
#elif BOARD == SAM4E_XPLAINED_PRO
# include "sam4e_xplained_pro/sam4e_xplained_pro.h"
#elif BOARD == AVR_SIMULATOR_UC3
# include "avr_simulator_uc3/avr_simulator_uc3.h"
#elif BOARD == USER_BOARD
// User-reserved area: #include the header file of your board here (if any).
# include "user_board.h"
#elif BOARD == DUMMY_BOARD
# include "dummy/dummy_board.h"
#else
# error No known Atmel board defined
#endif
#if (defined EXT_BOARD)
# if EXT_BOARD == MC300
# include "mc300/mc300.h"
# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \
(EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \
(EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \
(EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \
(EXT_BOARD == SENSORS_XPLAINED_BREADBOARD)
# include "sensors_xplained/sensors_xplained.h"
# elif EXT_BOARD == RZ600_AT86RF231
# include "at86rf231/at86rf231.h"
# elif EXT_BOARD == RZ600_AT86RF230B
# include "at86rf230b/at86rf230b.h"
# elif EXT_BOARD == RZ600_AT86RF212
# include "at86rf212/at86rf212.h"
# elif EXT_BOARD == SECURITY_XPLAINED
# include "security_xplained.h"
# elif EXT_BOARD == USER_EXT_BOARD
// User-reserved area: #include the header file of your extension board here
// (if any).
# endif
#endif
#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__))
#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
/*! \brief This function initializes the board target resources
*
* This function should be called to ensure proper initialization of the target
* board hardware connected to the part.
*/
extern void board_init(void);
#endif // #ifdef __AVR32_ABI_COMPILER__
#else
/*! \brief This function initializes the board target resources
*
* This function should be called to ensure proper initialization of the target
* board hardware connected to the part.
*/
extern void board_init(void);
#endif
#ifdef __cplusplus
}
#endif
/**
* \}
*/
#endif // _BOARD_H_

50
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/sleepmgr/samd/sleepmgr.c Normal file
View file

@ -0,0 +1,50 @@
/**
* \file
*
* \brief Chip-specific sleep manager configuration
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include <sleepmgr.h>
#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES];
#endif /* CONFIG_SLEEPMGR_ENABLE */

125
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/sleepmgr/samd/sleepmgr.h Normal file
View file

@ -0,0 +1,125 @@
/**
* \file
*
* \brief Chip-specific sleep manager configuration
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SAM_SLEEPMGR_INCLUDED
#define SAM_SLEEPMGR_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include <compiler.h>
#include <conf_sleepmgr.h>
#include <interrupt.h>
#include "system.h"
/**
* \weakgroup sleepmgr_group
* @{
*/
enum sleepmgr_mode {
/** Active mode. */
SLEEPMGR_ACTIVE = 0,
/**
* Idle 0 mode.
* Potential Wake Up sources: Synchronous(APB, AHB), asynchronous.
*/
SLEEPMGR_IDLE_0,
/**
* Idle 1 mode.
* Potential Wake Up sources: Synchronous (APB), asynchronous
*/
SLEEPMGR_IDLE_1,
/**
* Idle 2 mode.
* Potential Wake Up sources: Asynchronous
*/
SLEEPMGR_IDLE_2,
/**
* Standby mode.
* Potential Wake Up sources: Asynchronous
*/
SLEEPMGR_STANDBY,
SLEEPMGR_NR_OF_MODES,
};
/**
* \internal
* \name Internal arrays
* @{
*/
#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__)
/** Sleep mode lock counters */
extern uint8_t sleepmgr_locks[];
#endif /* CONFIG_SLEEPMGR_ENABLE */
/** @} */
static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode)
{
Assert(sleep_mode != SLEEPMGR_ACTIVE);
#ifdef CONFIG_SLEEPMGR_ENABLE
cpu_irq_disable();
/* Enter the sleep mode. */
system_set_sleepmode((enum system_sleepmode)(sleep_mode - 1));
cpu_irq_enable();
system_sleep();
#else
UNUSED(sleep_mode);
cpu_irq_enable();
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* SAM_SLEEPMGR_INCLUDED */

256
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/sleepmgr/sleepmgr.h Normal file
View file

@ -0,0 +1,256 @@
/**
* \file
*
* \brief Sleep manager
*
* Copyright (c) 2010 - 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SLEEPMGR_H
#define SLEEPMGR_H
#include <compiler.h>
#include <parts.h>
#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM)
# include "sam/sleepmgr.h"
#elif XMEGA
# include "xmega/sleepmgr.h"
#elif UC3
# include "uc3/sleepmgr.h"
#elif SAM4L
# include "sam4l/sleepmgr.h"
#elif MEGA
# include "mega/sleepmgr.h"
#elif (SAMD20 || SAMD21 || SAMR21 || SAMD11)
# include "samd/sleepmgr.h"
#else
# error Unsupported device.
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup sleepmgr_group Sleep manager
*
* The sleep manager is a service for ensuring that the device is not put to
* sleep in deeper sleep modes than the system (e.g., peripheral drivers,
* services or the application) allows at any given time.
*
* It is based on the use of lock counting for the individual sleep modes, and
* will put the device to sleep in the shallowest sleep mode that has a non-zero
* lock count. The drivers/services/application can change these counts by use
* of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode.
* Refer to \ref sleepmgr_mode for a list of the sleep modes available for
* locking, and the device datasheet for information on their effect.
*
* The application must supply the file \ref conf_sleepmgr.h.
*
* For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE
* must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not
* defined, the functions are replaced with dummy functions and no RAM is used.
*
* @{
*/
/**
* \def CONFIG_SLEEPMGR_ENABLE
* \brief Configuration symbol for enabling the sleep manager
*
* If this symbol is not defined, the functions of this service are replaced
* with dummy functions. This is useful for reducing code size and execution
* time if the sleep manager is not needed in the application.
*
* This symbol may be defined in \ref conf_sleepmgr.h.
*/
#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE)
# define CONFIG_SLEEPMGR_ENABLE
#endif
/**
* \enum sleepmgr_mode
* \brief Sleep mode locks
*
* Identifiers for the different sleep mode locks.
*/
/**
* \brief Initialize the lock counts
*
* Sets all lock counts to 0, except the very last one, which is set to 1. This
* is done to simplify the algorithm for finding the deepest allowable sleep
* mode in \ref sleepmgr_enter_sleep.
*/
static inline void sleepmgr_init(void)
{
#ifdef CONFIG_SLEEPMGR_ENABLE
uint8_t i;
for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) {
sleepmgr_locks[i] = 0;
}
sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1;
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
/**
* \brief Increase lock count for a sleep mode
*
* Increases the lock count for \a mode to ensure that the sleep manager does
* not put the device to sleep in the deeper sleep modes.
*
* \param mode Sleep mode to lock.
*/
static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode)
{
#ifdef CONFIG_SLEEPMGR_ENABLE
irqflags_t flags;
Assert(sleepmgr_locks[mode] < 0xff);
// Enter a critical section
flags = cpu_irq_save();
++sleepmgr_locks[mode];
// Leave the critical section
cpu_irq_restore(flags);
#else
UNUSED(mode);
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
/**
* \brief Decrease lock count for a sleep mode
*
* Decreases the lock count for \a mode. If the lock count reaches 0, the sleep
* manager can put the device to sleep in the deeper sleep modes.
*
* \param mode Sleep mode to unlock.
*/
static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode)
{
#ifdef CONFIG_SLEEPMGR_ENABLE
irqflags_t flags;
Assert(sleepmgr_locks[mode]);
// Enter a critical section
flags = cpu_irq_save();
--sleepmgr_locks[mode];
// Leave the critical section
cpu_irq_restore(flags);
#else
UNUSED(mode);
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
/**
* \brief Retrieves the deepest allowable sleep mode
*
* Searches through the sleep mode lock counts, starting at the shallowest sleep
* mode, until the first non-zero lock count is found. The deepest allowable
* sleep mode is then returned.
*/
static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void)
{
enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE;
#ifdef CONFIG_SLEEPMGR_ENABLE
uint8_t *lock_ptr = sleepmgr_locks;
// Find first non-zero lock count, starting with the shallowest modes.
while (!(*lock_ptr)) {
lock_ptr++;
sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1);
}
// Catch the case where one too many sleepmgr_unlock_mode() call has been
// performed on the deepest sleep mode.
Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES);
#endif /* CONFIG_SLEEPMGR_ENABLE */
return sleep_mode;
}
/**
* \fn sleepmgr_enter_sleep
* \brief Go to sleep in the deepest allowed mode
*
* Searches through the sleep mode lock counts, starting at the shallowest sleep
* mode, until the first non-zero lock count is found. The device is then put to
* sleep in the sleep mode that corresponds to the lock.
*
* \note This function enables interrupts before going to sleep, and will leave
* them enabled upon return. This also applies if sleep is skipped due to ACTIVE
* mode being locked.
*/
static inline void sleepmgr_enter_sleep(void)
{
#ifdef CONFIG_SLEEPMGR_ENABLE
enum sleepmgr_mode sleep_mode;
cpu_irq_disable();
// Find the deepest allowable sleep mode
sleep_mode = sleepmgr_get_sleep_mode();
// Return right away if first mode (ACTIVE) is locked.
if (sleep_mode==SLEEPMGR_ACTIVE) {
cpu_irq_enable();
return;
}
// Enter the deepest allowable sleep mode with interrupts enabled
sleepmgr_sleep(sleep_mode);
#else
cpu_irq_enable();
#endif /* CONFIG_SLEEPMGR_ENABLE */
}
//! @}
#ifdef __cplusplus
}
#endif
#endif /* SLEEPMGR_H */

1100
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/class/cdc/device/udi_cdc.c Normal file
View file

File diff suppressed because it is too large Load diff

796
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/class/cdc/device/udi_cdc.h Normal file
View file

@ -0,0 +1,796 @@
/**
* \file
*
* \brief USB Device Communication Device Class (CDC) interface definitions.
*
* Copyright (c) 2009 - 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _UDI_CDC_H_
#define _UDI_CDC_H_
#include "conf_usb.h"
#include "usb_protocol.h"
#include "usb_protocol_cdc.h"
#include "udd.h"
#include "udc_desc.h"
#include "udi.h"
// Check the number of port
#ifndef UDI_CDC_PORT_NB
# define UDI_CDC_PORT_NB 1
#endif
#if (UDI_CDC_PORT_NB < 1) || (UDI_CDC_PORT_NB > 7)
# error UDI_CDC_PORT_NB must be between 1 and 7
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup udi_cdc_group_udc
* @{
*/
//! Global structure which contains standard UDI API for UDC
extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm;
extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_data;
//@}
/**
* \ingroup udi_cdc_group
* \defgroup udi_cdc_group_desc USB interface descriptors
*
* The following structures provide predefined USB interface descriptors.
* It must be used to define the final USB descriptors.
*/
//@{
/**
* \brief Communication Class interface descriptor
*
* Interface descriptor with associated functional and endpoint
* descriptors for the CDC Communication Class interface.
*/
typedef struct {
//! Standard interface descriptor
usb_iface_desc_t iface;
//! CDC Header functional descriptor
usb_cdc_hdr_desc_t header;
//! CDC Abstract Control Model functional descriptor
usb_cdc_acm_desc_t acm;
//! CDC Union functional descriptor
usb_cdc_union_desc_t union_desc;
//! CDC Call Management functional descriptor
usb_cdc_call_mgmt_desc_t call_mgmt;
//! Notification endpoint descriptor
usb_ep_desc_t ep_notify;
} udi_cdc_comm_desc_t;
/**
* \brief Data Class interface descriptor
*
* Interface descriptor with associated endpoint descriptors for the
* CDC Data Class interface.
*/
typedef struct {
//! Standard interface descriptor
usb_iface_desc_t iface;
//! Data IN/OUT endpoint descriptors
usb_ep_desc_t ep_in;
usb_ep_desc_t ep_out;
} udi_cdc_data_desc_t;
//! CDC communication endpoints size for all speeds
#define UDI_CDC_COMM_EP_SIZE 64
//! CDC data endpoints size for FS speed (8B, 16B, 32B, 64B)
#define UDI_CDC_DATA_EPS_FS_SIZE 64
//! CDC data endpoints size for HS speed (512B only)
#define UDI_CDC_DATA_EPS_HS_SIZE 512
/**
* \name Content of interface descriptors
* Up to 7 CDC interfaces can be implemented on a USB device.
*/
//@{
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_0
#define UDI_CDC_IAD_STRING_ID_0 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_0
#define UDI_CDC_COMM_STRING_ID_0 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_0
#define UDI_CDC_DATA_STRING_ID_0 0
#endif
#define UDI_CDC_IAD_DESC_0 UDI_CDC_IAD_DESC(0)
#define UDI_CDC_COMM_DESC_0 UDI_CDC_COMM_DESC(0)
#define UDI_CDC_DATA_DESC_0_FS UDI_CDC_DATA_DESC_FS(0)
#define UDI_CDC_DATA_DESC_0_HS UDI_CDC_DATA_DESC_HS(0)
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_1
#define UDI_CDC_IAD_STRING_ID_1 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_1
#define UDI_CDC_COMM_STRING_ID_1 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_1
#define UDI_CDC_DATA_STRING_ID_1 0
#endif
#define UDI_CDC_IAD_DESC_1 UDI_CDC_IAD_DESC(1)
#define UDI_CDC_COMM_DESC_1 UDI_CDC_COMM_DESC(1)
#define UDI_CDC_DATA_DESC_1_FS UDI_CDC_DATA_DESC_FS(1)
#define UDI_CDC_DATA_DESC_1_HS UDI_CDC_DATA_DESC_HS(1)
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_2
#define UDI_CDC_IAD_STRING_ID_2 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_2
#define UDI_CDC_COMM_STRING_ID_2 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_2
#define UDI_CDC_DATA_STRING_ID_2 0
#endif
#define UDI_CDC_IAD_DESC_2 UDI_CDC_IAD_DESC(2)
#define UDI_CDC_COMM_DESC_2 UDI_CDC_COMM_DESC(2)
#define UDI_CDC_DATA_DESC_2_FS UDI_CDC_DATA_DESC_FS(2)
#define UDI_CDC_DATA_DESC_2_HS UDI_CDC_DATA_DESC_HS(2)
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_3
#define UDI_CDC_IAD_STRING_ID_3 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_3
#define UDI_CDC_COMM_STRING_ID_3 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_3
#define UDI_CDC_DATA_STRING_ID_3 0
#endif
#define UDI_CDC_IAD_DESC_3 UDI_CDC_IAD_DESC(3)
#define UDI_CDC_COMM_DESC_3 UDI_CDC_COMM_DESC(3)
#define UDI_CDC_DATA_DESC_3_FS UDI_CDC_DATA_DESC_FS(3)
#define UDI_CDC_DATA_DESC_3_HS UDI_CDC_DATA_DESC_HS(3)
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_4
#define UDI_CDC_IAD_STRING_ID_4 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_4
#define UDI_CDC_COMM_STRING_ID_4 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_4
#define UDI_CDC_DATA_STRING_ID_4 0
#endif
#define UDI_CDC_IAD_DESC_4 UDI_CDC_IAD_DESC(4)
#define UDI_CDC_COMM_DESC_4 UDI_CDC_COMM_DESC(4)
#define UDI_CDC_DATA_DESC_4_FS UDI_CDC_DATA_DESC_FS(4)
#define UDI_CDC_DATA_DESC_4_HS UDI_CDC_DATA_DESC_HS(4)
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_5
#define UDI_CDC_IAD_STRING_ID_5 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_5
#define UDI_CDC_COMM_STRING_ID_5 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_5
#define UDI_CDC_DATA_STRING_ID_5 0
#endif
#define UDI_CDC_IAD_DESC_5 UDI_CDC_IAD_DESC(5)
#define UDI_CDC_COMM_DESC_5 UDI_CDC_COMM_DESC(5)
#define UDI_CDC_DATA_DESC_5_FS UDI_CDC_DATA_DESC_FS(5)
#define UDI_CDC_DATA_DESC_5_HS UDI_CDC_DATA_DESC_HS(5)
//! By default no string associated to these interfaces
#ifndef UDI_CDC_IAD_STRING_ID_6
#define UDI_CDC_IAD_STRING_ID_6 0
#endif
#ifndef UDI_CDC_COMM_STRING_ID_6
#define UDI_CDC_COMM_STRING_ID_6 0
#endif
#ifndef UDI_CDC_DATA_STRING_ID_6
#define UDI_CDC_DATA_STRING_ID_6 0
#endif
#define UDI_CDC_IAD_DESC_6 UDI_CDC_IAD_DESC(6)
#define UDI_CDC_COMM_DESC_6 UDI_CDC_COMM_DESC(6)
#define UDI_CDC_DATA_DESC_6_FS UDI_CDC_DATA_DESC_FS(6)
#define UDI_CDC_DATA_DESC_6_HS UDI_CDC_DATA_DESC_HS(6)
//@}
//! Content of CDC IAD interface descriptor for all speeds
#define UDI_CDC_IAD_DESC(port) { \
.bLength = sizeof(usb_iad_desc_t),\
.bDescriptorType = USB_DT_IAD,\
.bInterfaceCount = 2,\
.bFunctionClass = CDC_CLASS_COMM,\
.bFunctionSubClass = CDC_SUBCLASS_ACM,\
.bFunctionProtocol = CDC_PROTOCOL_V25TER,\
.bFirstInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\
.iFunction = UDI_CDC_IAD_STRING_ID_##port,\
}
//! Content of CDC COMM interface descriptor for all speeds
#define UDI_CDC_COMM_DESC(port) { \
.iface.bLength = sizeof(usb_iface_desc_t),\
.iface.bDescriptorType = USB_DT_INTERFACE,\
.iface.bAlternateSetting = 0,\
.iface.bNumEndpoints = 1,\
.iface.bInterfaceClass = CDC_CLASS_COMM,\
.iface.bInterfaceSubClass = CDC_SUBCLASS_ACM,\
.iface.bInterfaceProtocol = CDC_PROTOCOL_V25TER,\
.header.bFunctionLength = sizeof(usb_cdc_hdr_desc_t),\
.header.bDescriptorType = CDC_CS_INTERFACE,\
.header.bDescriptorSubtype = CDC_SCS_HEADER,\
.header.bcdCDC = LE16(0x0110),\
.call_mgmt.bFunctionLength = sizeof(usb_cdc_call_mgmt_desc_t),\
.call_mgmt.bDescriptorType = CDC_CS_INTERFACE,\
.call_mgmt.bDescriptorSubtype = CDC_SCS_CALL_MGMT,\
.call_mgmt.bmCapabilities = \
CDC_CALL_MGMT_SUPPORTED | CDC_CALL_MGMT_OVER_DCI,\
.acm.bFunctionLength = sizeof(usb_cdc_acm_desc_t),\
.acm.bDescriptorType = CDC_CS_INTERFACE,\
.acm.bDescriptorSubtype = CDC_SCS_ACM,\
.acm.bmCapabilities = CDC_ACM_SUPPORT_LINE_REQUESTS,\
.union_desc.bFunctionLength = sizeof(usb_cdc_union_desc_t),\
.union_desc.bDescriptorType = CDC_CS_INTERFACE,\
.union_desc.bDescriptorSubtype= CDC_SCS_UNION,\
.ep_notify.bLength = sizeof(usb_ep_desc_t),\
.ep_notify.bDescriptorType = USB_DT_ENDPOINT,\
.ep_notify.bmAttributes = USB_EP_TYPE_INTERRUPT,\
.ep_notify.wMaxPacketSize = LE16(UDI_CDC_COMM_EP_SIZE),\
.ep_notify.bInterval = 0x10,\
.ep_notify.bEndpointAddress = UDI_CDC_COMM_EP_##port,\
.iface.bInterfaceNumber = UDI_CDC_COMM_IFACE_NUMBER_##port,\
.call_mgmt.bDataInterface = UDI_CDC_DATA_IFACE_NUMBER_##port,\
.union_desc.bMasterInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\
.union_desc.bSlaveInterface0 = UDI_CDC_DATA_IFACE_NUMBER_##port,\
.iface.iInterface = UDI_CDC_COMM_STRING_ID_##port,\
}
//! Content of CDC DATA interface descriptors
#define UDI_CDC_DATA_DESC_COMMON \
.iface.bLength = sizeof(usb_iface_desc_t),\
.iface.bDescriptorType = USB_DT_INTERFACE,\
.iface.bAlternateSetting = 0,\
.iface.bNumEndpoints = 2,\
.iface.bInterfaceClass = CDC_CLASS_DATA,\
.iface.bInterfaceSubClass = 0,\
.iface.bInterfaceProtocol = 0,\
.ep_in.bLength = sizeof(usb_ep_desc_t),\
.ep_in.bDescriptorType = USB_DT_ENDPOINT,\
.ep_in.bmAttributes = USB_EP_TYPE_BULK,\
.ep_in.bInterval = 0,\
.ep_out.bLength = sizeof(usb_ep_desc_t),\
.ep_out.bDescriptorType = USB_DT_ENDPOINT,\
.ep_out.bmAttributes = USB_EP_TYPE_BULK,\
.ep_out.bInterval = 0,
#define UDI_CDC_DATA_DESC_FS(port) { \
UDI_CDC_DATA_DESC_COMMON \
.ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\
.ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\
.ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\
.ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\
.iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\
.iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\
}
#define UDI_CDC_DATA_DESC_HS(port) { \
UDI_CDC_DATA_DESC_COMMON \
.ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\
.ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\
.ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\
.ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\
.iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\
.iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\
}
//@}
/**
* \ingroup udi_group
* \defgroup udi_cdc_group USB Device Interface (UDI) for Communication Class Device (CDC)
*
* Common APIs used by high level application to use this USB class.
*
* These routines are used to transfer and control data
* to/from USB CDC endpoint.
*
* See \ref udi_cdc_quickstart.
* @{
*/
/**
* \name Interface for application with single CDC interface support
*/
//@{
/**
* \brief Notify a state change of DCD signal
*
* \param b_set DCD is enabled if true, else disabled
*/
void udi_cdc_ctrl_signal_dcd(bool b_set);
/**
* \brief Notify a state change of DSR signal
*
* \param b_set DSR is enabled if true, else disabled
*/
void udi_cdc_ctrl_signal_dsr(bool b_set);
/**
* \brief Notify a framing error
*/
void udi_cdc_signal_framing_error(void);
/**
* \brief Notify a parity error
*/
void udi_cdc_signal_parity_error(void);
/**
* \brief Notify a overrun
*/
void udi_cdc_signal_overrun(void);
/**
* \brief Gets the number of byte received
*
* \return the number of data available
*/
iram_size_t udi_cdc_get_nb_received_data(void);
/**
* \brief This function checks if a character has been received on the CDC line
*
* \return \c 1 if a byte is ready to be read.
*/
bool udi_cdc_is_rx_ready(void);
/**
* \brief Waits and gets a value on CDC line
*
* \return value read on CDC line
*/
int udi_cdc_getc(void);
/**
* \brief Reads a RAM buffer on CDC line
*
* \param buf Values read
* \param size Number of value read
*
* \return the number of data remaining
*/
iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size);
/**
* \brief Gets the number of free byte in TX buffer
*
* \return the number of free byte in TX buffer
*/
iram_size_t udi_cdc_get_free_tx_buffer(void);
/**
* \brief This function checks if a new character sent is possible
* The type int is used to support scanf redirection from compiler LIB.
*
* \return \c 1 if a new character can be sent
*/
bool udi_cdc_is_tx_ready(void);
/**
* \brief Puts a byte on CDC line
* The type int is used to support printf redirection from compiler LIB.
*
* \param value Value to put
*
* \return \c 1 if function was successfully done, otherwise \c 0.
*/
int udi_cdc_putc(int value);
/**
* \brief Writes a RAM buffer on CDC line
*
* \param buf Values to write
* \param size Number of value to write
*
* \return the number of data remaining
*/
iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size);
//@}
/**
* \name Interface for application with multi CDC interfaces support
*/
//@{
/**
* \brief Notify a state change of DCD signal
*
* \param port Communication port number to manage
* \param b_set DCD is enabled if true, else disabled
*/
void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set);
/**
* \brief Notify a state change of DSR signal
*
* \param port Communication port number to manage
* \param b_set DSR is enabled if true, else disabled
*/
void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set);
/**
* \brief Notify a framing error
*
* \param port Communication port number to manage
*/
void udi_cdc_multi_signal_framing_error(uint8_t port);
/**
* \brief Notify a parity error
*
* \param port Communication port number to manage
*/
void udi_cdc_multi_signal_parity_error(uint8_t port);
/**
* \brief Notify a overrun
*
* \param port Communication port number to manage
*/
void udi_cdc_multi_signal_overrun(uint8_t port);
/**
* \brief Gets the number of byte received
*
* \param port Communication port number to manage
*
* \return the number of data available
*/
iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port);
/**
* \brief This function checks if a character has been received on the CDC line
*
* \param port Communication port number to manage
*
* \return \c 1 if a byte is ready to be read.
*/
bool udi_cdc_multi_is_rx_ready(uint8_t port);
/**
* \brief Waits and gets a value on CDC line
*
* \param port Communication port number to manage
*
* \return value read on CDC line
*/
int udi_cdc_multi_getc(uint8_t port);
/**
* \brief Reads a RAM buffer on CDC line
*
* \param port Communication port number to manage
* \param buf Values read
* \param size Number of values read
*
* \return the number of data remaining
*/
iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size);
/**
* \brief Gets the number of free byte in TX buffer
*
* \param port Communication port number to manage
*
* \return the number of free byte in TX buffer
*/
iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port);
/**
* \brief This function checks if a new character sent is possible
* The type int is used to support scanf redirection from compiler LIB.
*
* \param port Communication port number to manage
*
* \return \c 1 if a new character can be sent
*/
bool udi_cdc_multi_is_tx_ready(uint8_t port);
/**
* \brief Puts a byte on CDC line
* The type int is used to support printf redirection from compiler LIB.
*
* \param port Communication port number to manage
* \param value Value to put
*
* \return \c 1 if function was successfully done, otherwise \c 0.
*/
int udi_cdc_multi_putc(uint8_t port, int value);
/**
* \brief Writes a RAM buffer on CDC line
*
* \param port Communication port number to manage
* \param buf Values to write
* \param size Number of value to write
*
* \return the number of data remaining
*/
iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size);
//@}
//@}
/**
* \page udi_cdc_quickstart Quick start guide for USB device Communication Class Device module (UDI CDC)
*
* This is the quick start guide for the \ref udi_cdc_group
* "USB device interface CDC module (UDI CDC)" with step-by-step instructions on
* how to configure and use the modules in a selection of use cases.
*
* The use cases contain several code fragments. The code fragments in the
* steps for setup can be copied into a custom initialization function, while
* the steps for usage can be copied into, e.g., the main application function.
*
* \section udi_cdc_basic_use_case Basic use case
* In this basic use case, the "USB CDC (Single Interface Device)" module is used
* with only one communication port.
* The "USB CDC (Composite Device)" module usage is described in \ref udi_cdc_use_cases
* "Advanced use cases".
*
* \section udi_cdc_basic_use_case_setup Setup steps
* \subsection udi_cdc_basic_use_case_setup_prereq Prerequisites
* \copydetails udc_basic_use_case_setup_prereq
* \subsection udi_cdc_basic_use_case_setup_code Example code
* \copydetails udc_basic_use_case_setup_code
* \subsection udi_cdc_basic_use_case_setup_flow Workflow
* \copydetails udc_basic_use_case_setup_flow
*
* \section udi_cdc_basic_use_case_usage Usage steps
*
* \subsection udi_cdc_basic_use_case_usage_code Example code
* Content of conf_usb.h:
* \code
#define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable()
extern bool my_callback_cdc_enable(void);
#define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable()
extern void my_callback_cdc_disable(void);
#define UDI_CDC_LOW_RATE
#define UDI_CDC_DEFAULT_RATE 115200
#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1
#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE
#define UDI_CDC_DEFAULT_DATABITS 8
#include "udi_cdc_conf.h" // At the end of conf_usb.h file
\endcode
*
* Add to application C-file:
* \code
static bool my_flag_autorize_cdc_transfert = false;
bool my_callback_cdc_enable(void)
{
my_flag_autorize_cdc_transfert = true;
return true;
}
void my_callback_cdc_disable(void)
{
my_flag_autorize_cdc_transfert = false;
}
void task(void)
{
if (my_flag_autorize_cdc_transfert) {
udi_cdc_putc('A');
udi_cdc_getc();
}
}
\endcode
*
* \subsection udi_cdc_basic_use_case_setup_flow Workflow
* -# Ensure that conf_usb.h is available and contains the following configuration
* which is the USB device CDC configuration:
* - \code #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for CDC \endcode
* \note The USB serial number is mandatory when a CDC interface is used.
* - \code #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable()
extern bool my_callback_cdc_enable(void); \endcode
* \note After the device enumeration (detecting and identifying USB devices),
* the USB host starts the device configuration. When the USB CDC interface
* from the device is accepted by the host, the USB host enables this interface and the
* UDI_CDC_ENABLE_EXT() callback function is called and return true.
* Thus, when this event is received, the data transfer on CDC interface are authorized.
* - \code #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable()
extern void my_callback_cdc_disable(void); \endcode
* \note When the USB device is unplugged or is reset by the USB host, the USB
* interface is disabled and the UDI_CDC_DISABLE_EXT() callback function
* is called. Thus, the data transfer must be stopped on CDC interface.
* - \code #define UDI_CDC_LOW_RATE \endcode
* \note Define it when the transfer CDC Device to Host is a low rate
* (<512000 bauds) to reduce CDC buffers size.
* - \code #define UDI_CDC_DEFAULT_RATE 115200
#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1
#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE
#define UDI_CDC_DEFAULT_DATABITS 8 \endcode
* \note Default configuration of communication port at startup.
* -# Send or wait data on CDC line:
* - \code // Waits and gets a value on CDC line
int udi_cdc_getc(void);
// Reads a RAM buffer on CDC line
iram_size_t udi_cdc_read_buf(int* buf, iram_size_t size);
// Puts a byte on CDC line
int udi_cdc_putc(int value);
// Writes a RAM buffer on CDC line
iram_size_t udi_cdc_write_buf(const int* buf, iram_size_t size); \endcode
*
* \section udi_cdc_use_cases Advanced use cases
* For more advanced use of the UDI CDC module, see the following use cases:
* - \subpage udi_cdc_use_case_composite
* - \subpage udc_use_case_1
* - \subpage udc_use_case_2
* - \subpage udc_use_case_3
* - \subpage udc_use_case_4
* - \subpage udc_use_case_5
* - \subpage udc_use_case_6
*/
/**
* \page udi_cdc_use_case_composite CDC in a composite device
*
* A USB Composite Device is a USB Device which uses more than one USB class.
* In this use case, the "USB CDC (Composite Device)" module is used to
* create a USB composite device. Thus, this USB module can be associated with
* another "Composite Device" module, like "USB HID Mouse (Composite Device)".
*
* Also, you can refer to application note
* <A href="http://www.atmel.com/dyn/resources/prod_documents/doc8445.pdf">
* AVR4902 ASF - USB Composite Device</A>.
*
* \section udi_cdc_use_case_composite_setup Setup steps
* For the setup code of this use case to work, the
* \ref udi_cdc_basic_use_case "basic use case" must be followed.
*
* \section udi_cdc_use_case_composite_usage Usage steps
*
* \subsection udi_cdc_use_case_composite_usage_code Example code
* Content of conf_usb.h:
* \code
#define USB_DEVICE_EP_CTRL_SIZE 64
#define USB_DEVICE_NB_INTERFACE (X+2)
#define USB_DEVICE_MAX_EP (X+3)
#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_COMM_IFACE_NUMBER_0 X+0
#define UDI_CDC_DATA_IFACE_NUMBER_0 X+1
#define UDI_COMPOSITE_DESC_T \
usb_iad_desc_t udi_cdc_iad; \
udi_cdc_comm_desc_t udi_cdc_comm; \
udi_cdc_data_desc_t udi_cdc_data; \
...
#define UDI_COMPOSITE_DESC_FS \
.udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
.udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
.udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \
...
#define UDI_COMPOSITE_DESC_HS \
.udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
.udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
.udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \
...
#define UDI_COMPOSITE_API \
&udi_api_cdc_comm, \
&udi_api_cdc_data, \
...
\endcode
*
* \subsection udi_cdc_use_case_composite_usage_flow Workflow
* -# Ensure that conf_usb.h is available and contains the following parameters
* required for a USB composite device configuration:
* - \code // Endpoint control size, This must be:
// - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM)
// - 64 for a high speed device
#define USB_DEVICE_EP_CTRL_SIZE 64
// Total Number of interfaces on this USB device.
// Add 2 for CDC.
#define USB_DEVICE_NB_INTERFACE (X+2)
// Total number of endpoints on this USB device.
// This must include each endpoint for each interface.
// Add 3 for CDC.
#define USB_DEVICE_MAX_EP (X+3) \endcode
* -# Ensure that conf_usb.h contains the description of
* composite device:
* - \code // The endpoint numbers chosen by you for the CDC.
// The endpoint numbers starting from 1.
#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint
// The interface index of an interface starting from 0
#define UDI_CDC_COMM_IFACE_NUMBER_0 X+0
#define UDI_CDC_DATA_IFACE_NUMBER_0 X+1 \endcode
* -# Ensure that conf_usb.h contains the following parameters
* required for a USB composite device configuration:
* - \code // USB Interfaces descriptor structure
#define UDI_COMPOSITE_DESC_T \
...
usb_iad_desc_t udi_cdc_iad; \
udi_cdc_comm_desc_t udi_cdc_comm; \
udi_cdc_data_desc_t udi_cdc_data; \
...
// USB Interfaces descriptor value for Full Speed
#define UDI_COMPOSITE_DESC_FS \
...
.udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
.udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
.udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \
...
// USB Interfaces descriptor value for High Speed
#define UDI_COMPOSITE_DESC_HS \
...
.udi_cdc_iad = UDI_CDC_IAD_DESC_0, \
.udi_cdc_comm = UDI_CDC_COMM_DESC_0, \
.udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \
...
// USB Interface APIs
#define UDI_COMPOSITE_API \
...
&udi_api_cdc_comm, \
&udi_api_cdc_data, \
... \endcode
* - \note The descriptors order given in the four lists above must be the
* same as the order defined by all interface indexes. The interface index
* orders are defined through UDI_X_IFACE_NUMBER defines.\n
* Also, the CDC requires a USB Interface Association Descriptor (IAD) for
* composite device.
*/
#ifdef __cplusplus
}
#endif
#endif // _UDI_CDC_H_

152
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/class/cdc/device/udi_cdc_conf.h Normal file
View file

@ -0,0 +1,152 @@
/**
* \file
*
* \brief Default CDC configuration for a USB Device with a single interface
*
* Copyright (c) 2009 - 2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _UDI_CDC_CONF_H_
#define _UDI_CDC_CONF_H_
#include "usb_protocol_cdc.h"
#include "conf_usb.h"
#ifndef UDI_CDC_PORT_NB
# define UDI_CDC_PORT_NB 1
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup udi_cdc_group_single_desc
* @{
*/
//! Control endpoint size (Endpoint 0)
#define USB_DEVICE_EP_CTRL_SIZE 64
#if XMEGA
/**
* \name Endpoint configuration on XMEGA
* The XMEGA supports a IN and OUT endpoint with the same number endpoint,
* thus XMEGA can support up to 7 CDC interfaces.
*/
//@{
#define UDI_CDC_DATA_EP_IN_0 ( 1 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_0 ( 2 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_0 ( 2 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_DATA_EP_IN_1 ( 3 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_1 ( 4 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_1 ( 4 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_DATA_EP_IN_2 ( 5 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_2 ( 6 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_2 ( 6 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_DATA_EP_IN_3 ( 7 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_3 ( 8 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_3 ( 8 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_DATA_EP_IN_4 ( 9 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_4 (10 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_4 (10 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_DATA_EP_IN_5 (11 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_5 (12 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_5 (12 | USB_EP_DIR_IN) // Notify endpoint
#define UDI_CDC_DATA_EP_IN_6 (13 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_6 (14 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_6 (14 | USB_EP_DIR_IN) // Notify endpoint
//! 2 endpoints numbers used per CDC interface
#define USB_DEVICE_MAX_EP (2*UDI_CDC_PORT_NB)
//@}
#else
/**
* \name Default endpoint configuration
* The USBB, UDP, UDPHS and UOTGHS interfaces can support up to 2 CDC interfaces.
*/
//@{
# if UDI_CDC_PORT_NB > 2
# error USBB, UDP, UDPHS and UOTGHS interfaces have not enought endpoints.
# endif
#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX
#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX
#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint
# if SAM3U
/* For 3U max endpoint size of 4 is 64, use 5 and 6 as bulk tx and rx */
# define UDI_CDC_DATA_EP_IN_1 (6 | USB_EP_DIR_IN) // TX
# define UDI_CDC_DATA_EP_OUT_1 (5 | USB_EP_DIR_OUT) // RX
# define UDI_CDC_COMM_EP_1 (4 | USB_EP_DIR_IN) // Notify
# else
# define UDI_CDC_DATA_EP_IN_1 (4 | USB_EP_DIR_IN) // TX
# define UDI_CDC_DATA_EP_OUT_1 (5 | USB_EP_DIR_OUT) // RX
# define UDI_CDC_COMM_EP_1 (6 | USB_EP_DIR_IN) // Notify
# endif
//! 3 endpoints used per CDC interface
#define USB_DEVICE_MAX_EP (3*UDI_CDC_PORT_NB)
//@}
#endif
/**
* \name Default Interface numbers
*/
//@{
#define UDI_CDC_COMM_IFACE_NUMBER_0 0
#define UDI_CDC_DATA_IFACE_NUMBER_0 1
#define UDI_CDC_COMM_IFACE_NUMBER_1 2
#define UDI_CDC_DATA_IFACE_NUMBER_1 3
#define UDI_CDC_COMM_IFACE_NUMBER_2 4
#define UDI_CDC_DATA_IFACE_NUMBER_2 5
#define UDI_CDC_COMM_IFACE_NUMBER_3 6
#define UDI_CDC_DATA_IFACE_NUMBER_3 7
#define UDI_CDC_COMM_IFACE_NUMBER_4 8
#define UDI_CDC_DATA_IFACE_NUMBER_4 9
#define UDI_CDC_COMM_IFACE_NUMBER_5 10
#define UDI_CDC_DATA_IFACE_NUMBER_5 11
#define UDI_CDC_COMM_IFACE_NUMBER_6 12
#define UDI_CDC_DATA_IFACE_NUMBER_6 13
//@}
//@}
#ifdef __cplusplus
}
#endif
#endif // _UDI_CDC_CONF_H_

251
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/class/cdc/device/udi_cdc_desc.c Normal file
View file

@ -0,0 +1,251 @@
/**
* \file
*
* \brief Default descriptors for a USB Device with a single interface CDC
*
* Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "conf_usb.h"
#include "udd.h"
#include "udc_desc.h"
#include "udi_cdc.h"
/**
* \defgroup udi_cdc_group_single_desc USB device descriptors for a single interface
*
* The following structures provide the USB device descriptors required for
* USB Device with a single interface CDC.
*
* It is ready to use and do not require more definition.
*
* @{
*/
//! Two interfaces for a CDC device
#define USB_DEVICE_NB_INTERFACE (2*UDI_CDC_PORT_NB)
#ifdef USB_DEVICE_LPM_SUPPORT
# define USB_VERSION USB_V2_1
#else
# define USB_VERSION USB_V2_0
#endif
//! USB Device Descriptor
COMPILER_WORD_ALIGNED
UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = {
.bLength = sizeof(usb_dev_desc_t),
.bDescriptorType = USB_DT_DEVICE,
.bcdUSB = LE16(USB_VERSION),
#if UDI_CDC_PORT_NB > 1
.bDeviceClass = 0,
#else
.bDeviceClass = CDC_CLASS_DEVICE,
#endif
.bDeviceSubClass = 0,
.bDeviceProtocol = 0,
.bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE,
.idVendor = LE16(USB_DEVICE_VENDOR_ID),
.idProduct = LE16(USB_DEVICE_PRODUCT_ID),
.bcdDevice = LE16((USB_DEVICE_MAJOR_VERSION << 8)
| USB_DEVICE_MINOR_VERSION),
#ifdef USB_DEVICE_MANUFACTURE_NAME
.iManufacturer = 1,
#else
.iManufacturer = 0, // No manufacture string
#endif
#ifdef USB_DEVICE_PRODUCT_NAME
.iProduct = 2,
#else
.iProduct = 0, // No product string
#endif
#ifdef USB_DEVICE_SERIAL_NAME
.iSerialNumber = 3,
#else
.iSerialNumber = 0, // No serial string
#endif
.bNumConfigurations = 1
};
#ifdef USB_DEVICE_HS_SUPPORT
//! USB Device Qualifier Descriptor for HS
COMPILER_WORD_ALIGNED
UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = {
.bLength = sizeof(usb_dev_qual_desc_t),
.bDescriptorType = USB_DT_DEVICE_QUALIFIER,
.bcdUSB = LE16(USB_VERSION),
#if UDI_CDC_PORT_NB > 1
.bDeviceClass = 0,
#else
.bDeviceClass = CDC_CLASS_DEVICE,
#endif
.bDeviceSubClass = 0,
.bDeviceProtocol = 0,
.bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE,
.bNumConfigurations = 1
};
#endif
#ifdef USB_DEVICE_LPM_SUPPORT
//! USB Device Qualifier Descriptor
COMPILER_WORD_ALIGNED
UDC_DESC_STORAGE usb_dev_lpm_desc_t udc_device_lpm = {
.bos.bLength = sizeof(usb_dev_bos_desc_t),
.bos.bDescriptorType = USB_DT_BOS,
.bos.wTotalLength = LE16(sizeof(usb_dev_bos_desc_t) + sizeof(usb_dev_capa_ext_desc_t)),
.bos.bNumDeviceCaps = 1,
.capa_ext.bLength = sizeof(usb_dev_capa_ext_desc_t),
.capa_ext.bDescriptorType = USB_DT_DEVICE_CAPABILITY,
.capa_ext.bDevCapabilityType = USB_DC_USB20_EXTENSION,
.capa_ext.bmAttributes = USB_DC_EXT_LPM, // alfran: modified to fix ASF USB 3.0 incompatibility
};
#endif
//! Structure for USB Device Configuration Descriptor
COMPILER_PACK_SET(1)
typedef struct {
usb_conf_desc_t conf;
#if UDI_CDC_PORT_NB == 1
udi_cdc_comm_desc_t udi_cdc_comm_0;
udi_cdc_data_desc_t udi_cdc_data_0;
#else
# define UDI_CDC_DESC_STRUCTURE(index, unused) \
usb_iad_desc_t udi_cdc_iad_##index; \
udi_cdc_comm_desc_t udi_cdc_comm_##index; \
udi_cdc_data_desc_t udi_cdc_data_##index;
MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_STRUCTURE, ~)
# undef UDI_CDC_DESC_STRUCTURE
#endif
} udc_desc_t;
COMPILER_PACK_RESET()
//! USB Device Configuration Descriptor filled for full and high speed
COMPILER_WORD_ALIGNED
UDC_DESC_STORAGE udc_desc_t udc_desc_fs = {
.conf.bLength = sizeof(usb_conf_desc_t),
.conf.bDescriptorType = USB_DT_CONFIGURATION,
.conf.wTotalLength = LE16(sizeof(udc_desc_t)),
.conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE,
.conf.bConfigurationValue = 1,
.conf.iConfiguration = 0,
.conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR,
.conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER),
#if UDI_CDC_PORT_NB == 1
.udi_cdc_comm_0 = UDI_CDC_COMM_DESC_0,
.udi_cdc_data_0 = UDI_CDC_DATA_DESC_0_FS,
#else
# define UDI_CDC_DESC_FS(index, unused) \
.udi_cdc_iad_##index = UDI_CDC_IAD_DESC_##index,\
.udi_cdc_comm_##index = UDI_CDC_COMM_DESC_##index,\
.udi_cdc_data_##index = UDI_CDC_DATA_DESC_##index##_FS,
MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_FS, ~)
# undef UDI_CDC_DESC_FS
#endif
};
#ifdef USB_DEVICE_HS_SUPPORT
COMPILER_WORD_ALIGNED
UDC_DESC_STORAGE udc_desc_t udc_desc_hs = {
.conf.bLength = sizeof(usb_conf_desc_t),
.conf.bDescriptorType = USB_DT_CONFIGURATION,
.conf.wTotalLength = LE16(sizeof(udc_desc_t)),
.conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE,
.conf.bConfigurationValue = 1,
.conf.iConfiguration = 0,
.conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR,
.conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER),
#if UDI_CDC_PORT_NB == 1
.udi_cdc_comm_0 = UDI_CDC_COMM_DESC_0,
.udi_cdc_data_0 = UDI_CDC_DATA_DESC_0_HS,
#else
# define UDI_CDC_DESC_HS(index, unused) \
.udi_cdc_iad_##index = UDI_CDC_IAD_DESC_##index, \
.udi_cdc_comm_##index = UDI_CDC_COMM_DESC_##index, \
.udi_cdc_data_##index = UDI_CDC_DATA_DESC_##index##_HS,
MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_HS, ~)
# undef UDI_CDC_DESC_HS
#endif
};
#endif
/**
* \name UDC structures which content all USB Device definitions
*/
//@{
//! Associate an UDI for each USB interface
UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = {
# define UDI_CDC_API(index, unused) \
&udi_api_cdc_comm, \
&udi_api_cdc_data,
MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_API, ~)
# undef UDI_CDC_API
};
//! Add UDI with USB Descriptors FS & HS
UDC_DESC_STORAGE udc_config_speed_t udc_config_fs[1] = { {
.desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_fs,
.udi_apis = udi_apis,
}};
#ifdef USB_DEVICE_HS_SUPPORT
UDC_DESC_STORAGE udc_config_speed_t udc_config_hs[1] = { {
.desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_hs,
.udi_apis = udi_apis,
}};
#endif
//! Add all information about USB Device in global structure for UDC
UDC_DESC_STORAGE udc_config_t udc_config = {
.confdev_lsfs = &udc_device_desc,
.conf_lsfs = udc_config_fs,
#ifdef USB_DEVICE_HS_SUPPORT
.confdev_hs = &udc_device_desc,
.qualifier = &udc_device_qual,
.conf_hs = udc_config_hs,
#endif
#ifdef USB_DEVICE_LPM_SUPPORT
.conf_bos = &udc_device_lpm.bos,
#else
.conf_bos = NULL,
#endif
};
//@}
//@}

315
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/class/cdc/usb_protocol_cdc.h Normal file
View file

@ -0,0 +1,315 @@
/**
* \file
*
* \brief USB Communication Device Class (CDC) protocol definitions
*
* Copyright (c) 2009-2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _USB_PROTOCOL_CDC_H_
#define _USB_PROTOCOL_CDC_H_
#include "compiler.h"
/**
* \ingroup usb_protocol_group
* \defgroup cdc_protocol_group Communication Device Class Definitions
* @{
*/
/**
* \name Possible values of class
*/
//@{
#define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class
#define CDC_CLASS_COMM 0x02 //!< CDC Communication Class Interface
#define CDC_CLASS_DATA 0x0A //!< CDC Data Class Interface
//@}
//! \name USB CDC Subclass IDs
//@{
#define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model
#define CDC_SUBCLASS_ACM 0x02 //!< Abstract Control Model
#define CDC_SUBCLASS_TCM 0x03 //!< Telephone Control Model
#define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model
#define CDC_SUBCLASS_CCM 0x05 //!< CAPI Control Model
#define CDC_SUBCLASS_ETH 0x06 //!< Ethernet Networking Control Model
#define CDC_SUBCLASS_ATM 0x07 //!< ATM Networking Control Model
//@}
//! \name USB CDC Communication Interface Protocol IDs
//@{
#define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands
//@}
//! \name USB CDC Data Interface Protocol IDs
//@{
#define CDC_PROTOCOL_I430 0x30 //!< ISDN BRI
#define CDC_PROTOCOL_HDLC 0x31 //!< HDLC
#define CDC_PROTOCOL_TRANS 0x32 //!< Transparent
#define CDC_PROTOCOL_Q921M 0x50 //!< Q.921 management protocol
#define CDC_PROTOCOL_Q921 0x51 //!< Q.931 [sic] Data link protocol
#define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor
#define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures
#define CDC_PROTOCOL_Q931 0x91 //!< Euro-ISDN protocol control
#define CDC_PROTOCOL_V120 0x92 //!< V.24 rate adaption to ISDN
#define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands
#define CDC_PROTOCOL_HOST 0xFD //!< Host based driver
/**
* \brief Describes the Protocol Unit Functional Descriptors [sic]
* on Communication Class Interface
*/
#define CDC_PROTOCOL_PUFD 0xFE
//@}
//! \name USB CDC Functional Descriptor Types
//@{
#define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor
#define CDC_CS_ENDPOINT 0x25 //!< Endpoint Functional Descriptor
//@}
//! \name USB CDC Functional Descriptor Subtypes
//@{
#define CDC_SCS_HEADER 0x00 //!< Header Functional Descriptor
#define CDC_SCS_CALL_MGMT 0x01 //!< Call Management
#define CDC_SCS_ACM 0x02 //!< Abstract Control Management
#define CDC_SCS_UNION 0x06 //!< Union Functional Descriptor
//@}
//! \name USB CDC Request IDs
//@{
#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00
#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01
#define USB_REQ_CDC_SET_COMM_FEATURE 0x02
#define USB_REQ_CDC_GET_COMM_FEATURE 0x03
#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04
#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10
#define USB_REQ_CDC_SET_HOOK_STATE 0x11
#define USB_REQ_CDC_PULSE_SETUP 0x12
#define USB_REQ_CDC_SEND_PULSE 0x13
#define USB_REQ_CDC_SET_PULSE_TIME 0x14
#define USB_REQ_CDC_RING_AUX_JACK 0x15
#define USB_REQ_CDC_SET_LINE_CODING 0x20
#define USB_REQ_CDC_GET_LINE_CODING 0x21
#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22
#define USB_REQ_CDC_SEND_BREAK 0x23
#define USB_REQ_CDC_SET_RINGER_PARMS 0x30
#define USB_REQ_CDC_GET_RINGER_PARMS 0x31
#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32
#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33
#define USB_REQ_CDC_SET_LINE_PARMS 0x34
#define USB_REQ_CDC_GET_LINE_PARMS 0x35
#define USB_REQ_CDC_DIAL_DIGITS 0x36
#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37
#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38
#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39
#define USB_REQ_CDC_GET_PROFILE 0x3A
#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41
#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42
#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43
#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44
#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50
#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51
#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52
#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53
// Added bNotification codes according cdc spec 1.1 chapter 6.3
#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09
#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20
#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28
#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29
//@}
/*
* Need to pack structures tightly, or the compiler might insert padding
* and violate the spec-mandated layout.
*/
COMPILER_PACK_SET(1)
//! \name USB CDC Descriptors
//@{
//! CDC Header Functional Descriptor
typedef struct {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
le16_t bcdCDC;
} usb_cdc_hdr_desc_t;
//! CDC Call Management Functional Descriptor
typedef struct {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
uint8_t bDataInterface;
} usb_cdc_call_mgmt_desc_t;
//! CDC ACM Functional Descriptor
typedef struct {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bmCapabilities;
} usb_cdc_acm_desc_t;
//! CDC Union Functional Descriptor
typedef struct {
uint8_t bFunctionLength;
uint8_t bDescriptorType;
uint8_t bDescriptorSubtype;
uint8_t bMasterInterface;
uint8_t bSlaveInterface0;
} usb_cdc_union_desc_t;
//! \name USB CDC Call Management Capabilities
//@{
//! Device handles call management itself
#define CDC_CALL_MGMT_SUPPORTED (1 << 0)
//! Device can send/receive call management info over a Data Class interface
#define CDC_CALL_MGMT_OVER_DCI (1 << 1)
//@}
//! \name USB CDC ACM Capabilities
//@{
//! Device supports the request combination of
//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature.
#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0)
//! Device supports the request combination of
//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding,
//! and the notification Serial_State.
#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1)
//! Device supports the request Send_Break
#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2)
//! Device supports the notification Network_Connection.
#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3)
//@}
//@}
//! \name USB CDC line control
//@{
//! \name USB CDC line coding
//@{
//! Line Coding structure
typedef struct {
le32_t dwDTERate;
uint8_t bCharFormat;
uint8_t bParityType;
uint8_t bDataBits;
} usb_cdc_line_coding_t;
//! Possible values of bCharFormat
enum cdc_char_format {
CDC_STOP_BITS_1 = 0, //!< 1 stop bit
CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits
CDC_STOP_BITS_2 = 2, //!< 2 stop bits
};
//! Possible values of bParityType
enum cdc_parity {
CDC_PAR_NONE = 0, //!< No parity
CDC_PAR_ODD = 1, //!< Odd parity
CDC_PAR_EVEN = 2, //!< Even parity
CDC_PAR_MARK = 3, //!< Parity forced to 0 (space)
CDC_PAR_SPACE = 4, //!< Parity forced to 1 (mark)
};
//@}
//! \name USB CDC control signals
//! spec 1.1 chapter 6.2.14
//@{
//! Control signal structure
typedef struct {
uint16_t value;
} usb_cdc_control_signal_t;
//! \name Possible values in usb_cdc_control_signal_t
//@{
//! Carrier control for half duplex modems.
//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS.
//! The device ignores the value of this bit
//! when operating in full duplex mode.
#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1)
//! Indicates to DCE if DTE is present or not.
//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR.
#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0)
//@}
//@}
//! \name USB CDC notification message
//@{
typedef struct {
uint8_t bmRequestType;
uint8_t bNotification;
le16_t wValue;
le16_t wIndex;
le16_t wLength;
} usb_cdc_notify_msg_t;
//! \name USB CDC serial state
//@{*
//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5)
typedef struct {
usb_cdc_notify_msg_t header;
le16_t value;
} usb_cdc_notify_serial_state_t;
//! \name Possible values in usb_cdc_notify_serial_state_t
//@{
#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1<<0))
#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1<<1))
#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1<<2))
#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1<<3))
#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1<<4))
#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1<<5))
#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1<<6))
//@}
//! @}
//! @}
COMPILER_PACK_RESET()
//! @}
#endif // _USB_PROTOCOL_CDC_H_

1138
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/udc/udc.c Normal file
View file

File diff suppressed because it is too large Load diff

694
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/udc/udc.h Normal file
View file

@ -0,0 +1,694 @@
/**
* \file
*
* \brief Interface of the USB Device Controller (UDC)
*
* Copyright (c) 2009 - 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _UDC_H_
#define _UDC_H_
#include "conf_usb.h"
#include "usb_protocol.h"
#include "udc_desc.h"
#include "udd.h"
#if USB_DEVICE_VENDOR_ID == 0
# error USB_DEVICE_VENDOR_ID cannot be equal to 0
#endif
#if USB_DEVICE_PRODUCT_ID == 0
# error USB_DEVICE_PRODUCT_ID cannot be equal to 0
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup usb_device_group
* \defgroup udc_group USB Device Controller (UDC)
*
* The UDC provides a high-level abstraction of the usb device.
* You can use these functions to control the main device state
* (start/attach/wakeup).
*
* \section USB_DEVICE_CONF USB Device Custom configuration
* The following USB Device configuration must be included in the conf_usb.h
* file of the application.
*
* USB_DEVICE_VENDOR_ID (Word)<br>
* Vendor ID provided by USB org (ATMEL 0x03EB).
*
* USB_DEVICE_PRODUCT_ID (Word)<br>
* Product ID (Referenced in usb_atmel.h).
*
* USB_DEVICE_MAJOR_VERSION (Byte)<br>
* Major version of the device
*
* USB_DEVICE_MINOR_VERSION (Byte)<br>
* Minor version of the device
*
* USB_DEVICE_MANUFACTURE_NAME (string)<br>
* ASCII name for the manufacture
*
* USB_DEVICE_PRODUCT_NAME (string)<br>
* ASCII name for the product
*
* USB_DEVICE_SERIAL_NAME (string)<br>
* ASCII name to enable and set a serial number
*
* USB_DEVICE_POWER (Numeric)<br>
* (unit mA) Maximum device power
*
* USB_DEVICE_ATTR (Byte)<br>
* USB attributes available:
* - USB_CONFIG_ATTR_SELF_POWERED
* - USB_CONFIG_ATTR_REMOTE_WAKEUP
* Note: if remote wake enabled then defines remotewakeup callbacks,
* see Table 5-2. External API from UDC - Callback
*
* USB_DEVICE_LOW_SPEED (Only defined)<br>
* Force the USB Device to run in low speed
*
* USB_DEVICE_HS_SUPPORT (Only defined)<br>
* Authorize the USB Device to run in high speed
*
* USB_DEVICE_MAX_EP (Byte)<br>
* Define the maximum endpoint number used by the USB Device.<br>
* This one is already defined in UDI default configuration.
* Ex:
* - When endpoint control 0x00, endpoint 0x01 and
* endpoint 0x82 is used then USB_DEVICE_MAX_EP=2
* - When only endpoint control 0x00 is used then USB_DEVICE_MAX_EP=0
* - When endpoint 0x01 and endpoint 0x81 is used then USB_DEVICE_MAX_EP=1<br>
* (configuration not possible on USBB interface)
* @{
*/
/**
* \brief Authorizes the VBUS event
*
* \return true, if the VBUS monitoring is possible.
*
* \section udc_vbus_monitoring VBus monitoring used cases
*
* The VBus monitoring is used only for USB SELF Power application.
*
* - By default the USB device is automatically attached when Vbus is high
* or when USB is start for devices without internal Vbus monitoring.
* conf_usb.h file does not contains define USB_DEVICE_ATTACH_AUTO_DISABLE.
* \code //#define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
*
* - Add custom VBUS monitoring. conf_usb.h file contains define
* USB_DEVICE_ATTACH_AUTO_DISABLE:
* \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
* User C file contains:
* \code
// Authorize VBUS monitoring
if (!udc_include_vbus_monitoring()) {
// Implement custom VBUS monitoring via GPIO or other
}
Event_VBUS_present() // VBUS interrupt or GPIO interrupt or other
{
// Attach USB Device
udc_attach();
}
\endcode
*
* - Case of battery charging. conf_usb.h file contains define
* USB_DEVICE_ATTACH_AUTO_DISABLE:
* \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode
* User C file contains:
* \code
Event VBUS present() // VBUS interrupt or GPIO interrupt or ..
{
// Authorize battery charging, but wait key press to start USB.
}
Event Key press()
{
// Stop batteries charging
// Start USB
udc_attach();
}
\endcode
*/
static inline bool udc_include_vbus_monitoring(void)
{
return udd_include_vbus_monitoring();
}
/*! \brief Start the USB Device stack
*/
void udc_start(void);
/*! \brief Stop the USB Device stack
*/
void udc_stop(void);
/**
* \brief Attach device to the bus when possible
*
* \warning If a VBus control is included in driver,
* then it will attach device when an acceptable Vbus
* level from the host is detected.
*/
static inline void udc_attach(void)
{
udd_attach();
}
/**
* \brief Detaches the device from the bus
*
* The driver must remove pull-up on USB line D- or D+.
*/
static inline void udc_detach(void)
{
udd_detach();
}
/*! \brief The USB driver sends a resume signal called \e "Upstream Resume"
* This is authorized only when the remote wakeup feature is enabled by host.
*/
static inline void udc_remotewakeup(void)
{
udd_send_remotewakeup();
}
/**
* \brief Returns a pointer on the current interface descriptor
*
* \return pointer on the current interface descriptor.
*/
usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void);
//@}
/**
* \ingroup usb_group
* \defgroup usb_device_group USB Stack Device
*
* This module includes USB Stack Device implementation.
* The stack is divided in three parts:
* - USB Device Controller (UDC) provides USB chapter 9 compliance
* - USB Device Interface (UDI) provides USB Class compliance
* - USB Device Driver (UDD) provides USB Driver for each Atmel MCU
* Many USB Device applications can be implemented on Atmel MCU.
* Atmel provides many application notes for different applications:
* - AVR4900, provides general information about Device Stack
* - AVR4901, explains how to create a new class
* - AVR4902, explains how to create a composite device
* - AVR49xx, all device classes provided in ASF have an application note
*
* A basic USB knowledge is required to understand the USB Device
* Class application notes (HID,MS,CDC,PHDC,...).
* Then, to create an USB device with
* only one class provided by ASF, refer directly to the application note
* corresponding to this USB class. The USB Device application note for
* New Class and Composite is dedicated to advanced USB users.
*
* @{
*/
//! @}
#ifdef __cplusplus
}
#endif
/**
* \ingroup udc_group
* \defgroup udc_basic_use_case_setup_prereq USB Device Controller (UDC) - Prerequisites
* Common prerequisites for all USB devices.
*
* This module is based on USB device stack full interrupt driven, and supporting
* \ref sleepmgr_group sleepmgr. For AVR and SAM3/4 devices the \ref clk_group clock services
* is supported. For SAMD devices the \ref asfdoc_sam0_system_clock_group clock driver is supported.
*
* The following procedure must be executed to setup the project correctly:
* - Specify the clock configuration:
* - XMEGA USB devices need 48MHz clock input.\n
* XMEGA USB devices need CPU frequency higher than 12MHz.\n
* You can use either an internal RC48MHz auto calibrated by Start of Frames
* or an external OSC.
* - UC3 and SAM3/4 devices without USB high speed support need 48MHz clock input.\n
* You must use a PLL and an external OSC.
* - UC3 and SAM3/4 devices with USB high speed support need 12MHz clock input.\n
* You must use an external OSC.
* - UC3 devices with USBC hardware need CPU frequency higher than 25MHz.
* - SAMD devices without USB high speed support need 48MHz clock input.\n
* You should use DFLL with USBCRM.
* - In conf_board.h, the define CONF_BOARD_USB_PORT must be added to enable USB lines.
* (Not mandatory for all boards)
* - Enable interrupts
* - Initialize the clock service
*
* The usage of \ref sleepmgr_group sleepmgr service is optional, but recommended to reduce power
* consumption:
* - Initialize the sleep manager service
* - Activate sleep mode when the application is in IDLE state
*
* \subpage udc_conf_clock.
*
* for AVR and SAM3/4 devices, add to the initialization code:
* \code
sysclk_init();
irq_initialize_vectors();
cpu_irq_enable();
board_init();
sleepmgr_init(); // Optional
\endcode
*
* For SAMD devices, add to the initialization code:
* \code
system_init();
irq_initialize_vectors();
cpu_irq_enable();
sleepmgr_init(); // Optional
\endcode
* Add to the main IDLE loop:
* \code
sleepmgr_enter_sleep(); // Optional
\endcode
*
*/
/**
* \ingroup udc_group
* \defgroup udc_basic_use_case_setup_code USB Device Controller (UDC) - Example code
* Common example code for all USB devices.
*
* Content of conf_usb.h:
* \code
#define USB_DEVICE_VENDOR_ID 0x03EB
#define USB_DEVICE_PRODUCT_ID 0xXXXX
#define USB_DEVICE_MAJOR_VERSION 1
#define USB_DEVICE_MINOR_VERSION 0
#define USB_DEVICE_POWER 100
#define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED
\endcode
*
* Add to application C-file:
* \code
void usb_init(void)
{
udc_start();
}
\endcode
*/
/**
* \ingroup udc_group
* \defgroup udc_basic_use_case_setup_flow USB Device Controller (UDC) - Workflow
* Common workflow for all USB devices.
*
* -# Ensure that conf_usb.h is available and contains the following configuration
* which is the main USB device configuration:
* - \code // Vendor ID provided by USB org (ATMEL 0x03EB)
#define USB_DEVICE_VENDOR_ID 0x03EB // Type Word
// Product ID (Atmel PID referenced in usb_atmel.h)
#define USB_DEVICE_PRODUCT_ID 0xXXXX // Type Word
// Major version of the device
#define USB_DEVICE_MAJOR_VERSION 1 // Type Byte
// Minor version of the device
#define USB_DEVICE_MINOR_VERSION 0 // Type Byte
// Maximum device power (mA)
#define USB_DEVICE_POWER 100 // Type 9-bits
// USB attributes to enable features
#define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED // Flags \endcode
* -# Call the USB device stack start function to enable stack and start USB:
* - \code udc_start(); \endcode
* \note In case of USB dual roles (Device and Host) managed through USB OTG connector
* (USB ID pin), the call of udc_start() must be removed and replaced by uhc_start().
* SeRefer to "AVR4950 section 6.1 Dual roles" for further information about dual roles.
*/
/**
* \page udc_conf_clock conf_clock.h examples with USB support
*
* Content of XMEGA conf_clock.h:
* \code
// Configuration based on internal RC:
// USB clock need of 48Mhz
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_RCOSC
#define CONFIG_OSC_RC32_CAL 48000000UL
#define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC OSC_ID_USBSOF
// CPU clock need of clock > 12MHz to run with USB (Here 24MHz)
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC32MHZ
#define CONFIG_SYSCLK_PSADIV SYSCLK_PSADIV_2
#define CONFIG_SYSCLK_PSBCDIV SYSCLK_PSBCDIV_1_1
\endcode
*
* Content of conf_clock.h for AT32UC3A0, AT32UC3A1, AT32UC3B devices (USBB):
* \code
// Configuration based on 12MHz external OSC:
#define CONFIG_PLL1_SOURCE PLL_SRC_OSC0
#define CONFIG_PLL1_MUL 8
#define CONFIG_PLL1_DIV 2
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
#define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div)
\endcode
*
* Content of conf_clock.h for AT32UC3A3, AT32UC3A4 devices (USBB with high speed support):
* \code
// Configuration based on 12MHz external OSC:
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0
#define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div)
\endcode
*
* Content of conf_clock.h for AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U devices (USBC):
* \code
// Configuration based on 12MHz external OSC:
#define CONFIG_PLL1_SOURCE PLL_SRC_OSC0
#define CONFIG_PLL1_MUL 8
#define CONFIG_PLL1_DIV 2
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
#define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div)
// CPU clock need of clock > 25MHz to run with USBC
#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL1
\endcode
*
* Content of conf_clock.h for SAM3S, SAM3SD, SAM4S devices (UPD: USB Peripheral Device):
* \code
// PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
#define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL
#define CONFIG_PLL1_MUL 16
#define CONFIG_PLL1_DIV 2
// USB Clock Source Options (Fusb = FpllX / USB_div)
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1
#define CONFIG_USBCLK_DIV 2
\endcode
*
* Content of conf_clock.h for SAM3U device (UPDHS: USB Peripheral Device High Speed):
* \code
// USB Clock Source fixed at UPLL.
\endcode
*
* Content of conf_clock.h for SAM3X, SAM3A devices (UOTGHS: USB OTG High Speed):
* \code
// USB Clock Source fixed at UPLL.
#define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL
#define CONFIG_USBCLK_DIV 1
\endcode
*
* Content of conf_clocks.h for SAMD devices (USB):
* \code
// System clock bus configuration
# define CONF_CLOCK_FLASH_WAIT_STATES 2
// USB Clock Source fixed at DFLL.
// SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop
# define CONF_CLOCK_DFLL_ENABLE true
# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY
# define CONF_CLOCK_DFLL_ON_DEMAND true
// Set this to true to configure the GCLK when running clocks_init.
// If set to false, none of the GCLK generators will be configured in clocks_init().
# define CONF_CLOCK_CONFIGURE_GCLK true
// Configure GCLK generator 0 (Main Clock)
# define CONF_CLOCK_GCLK_0_ENABLE true
# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY true
# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL
# define CONF_CLOCK_GCLK_0_PRESCALER 1
# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
\endcode
*/
/**
* \page udc_use_case_1 Change USB speed
*
* In this use case, the USB device is used with different USB speeds.
*
* \section udc_use_case_1_setup Setup steps
*
* Prior to implement this use case, be sure to have already
* apply the UDI module "basic use case".
*
* \section udc_use_case_1_usage Usage steps
*
* \subsection udc_use_case_1_usage_code Example code
* Content of conf_usb.h:
* \code
#if // Low speed
#define USB_DEVICE_LOW_SPEED
// #define USB_DEVICE_HS_SUPPORT
#elif // Full speed
// #define USB_DEVICE_LOW_SPEED
// #define USB_DEVICE_HS_SUPPORT
#elif // High speed
// #define USB_DEVICE_LOW_SPEED
#define USB_DEVICE_HS_SUPPORT
#endif
\endcode
*
* \subsection udc_use_case_1_usage_flow Workflow
* -# Ensure that conf_usb.h is available and contains the following parameters
* required for a USB device low speed (1.5Mbit/s):
* - \code #define USB_DEVICE_LOW_SPEED
//#define USB_DEVICE_HS_SUPPORT \endcode
* -# Ensure that conf_usb.h contains the following parameters
* required for a USB device full speed (12Mbit/s):
* - \code //#define USB_DEVICE_LOW_SPEED
//#define USB_DEVICE_HS_SUPPORT \endcode
* -# Ensure that conf_usb.h contains the following parameters
* required for a USB device high speed (480Mbit/s):
* - \code //#define USB_DEVICE_LOW_SPEED
#define USB_DEVICE_HS_SUPPORT \endcode
*/
/**
* \page udc_use_case_2 Use USB strings
*
* In this use case, the usual USB strings is added in the USB device.
*
* \section udc_use_case_2_setup Setup steps
* Prior to implement this use case, be sure to have already
* apply the UDI module "basic use case".
*
* \section udc_use_case_2_usage Usage steps
*
* \subsection udc_use_case_2_usage_code Example code
* Content of conf_usb.h:
* \code
#define USB_DEVICE_MANUFACTURE_NAME "Manufacture name"
#define USB_DEVICE_PRODUCT_NAME "Product name"
#define USB_DEVICE_SERIAL_NAME "12...EF"
\endcode
*
* \subsection udc_use_case_2_usage_flow Workflow
* -# Ensure that conf_usb.h is available and contains the following parameters
* required to enable different USB strings:
* - \code // Static ASCII name for the manufacture
#define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" \endcode
* - \code // Static ASCII name for the product
#define USB_DEVICE_PRODUCT_NAME "Product name" \endcode
* - \code // Static ASCII name to enable and set a serial number
#define USB_DEVICE_SERIAL_NAME "12...EF" \endcode
*/
/**
* \page udc_use_case_3 Use USB remote wakeup feature
*
* In this use case, the USB remote wakeup feature is enabled.
*
* \section udc_use_case_3_setup Setup steps
* Prior to implement this use case, be sure to have already
* apply the UDI module "basic use case".
*
* \section udc_use_case_3_usage Usage steps
*
* \subsection udc_use_case_3_usage_code Example code
* Content of conf_usb.h:
* \code
#define USB_DEVICE_ATTR \
(USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED)
#define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable()
extern void my_callback_remotewakeup_enable(void);
#define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable()
extern void my_callback_remotewakeup_disable(void);
\endcode
*
* Add to application C-file:
* \code
void my_callback_remotewakeup_enable(void)
{
// Enable application wakeup events (e.g. enable GPIO interrupt)
}
void my_callback_remotewakeup_disable(void)
{
// Disable application wakeup events (e.g. disable GPIO interrupt)
}
void my_interrupt_event(void)
{
udc_remotewakeup();
}
\endcode
*
* \subsection udc_use_case_3_usage_flow Workflow
* -# Ensure that conf_usb.h is available and contains the following parameters
* required to enable remote wakeup feature:
* - \code // Authorizes the remote wakeup feature
#define USB_DEVICE_ATTR (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED) \endcode
* - \code // Define callback called when the host enables the remotewakeup feature
#define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable()
extern void my_callback_remotewakeup_enable(void); \endcode
* - \code // Define callback called when the host disables the remotewakeup feature
#define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable()
extern void my_callback_remotewakeup_disable(void); \endcode
* -# Send a remote wakeup (USB upstream):
* - \code udc_remotewakeup(); \endcode
*/
/**
* \page udc_use_case_5 Bus power application recommendations
*
* In this use case, the USB device BUS power feature is enabled.
* This feature requires a correct power consumption management.
*
* \section udc_use_case_5_setup Setup steps
* Prior to implement this use case, be sure to have already
* apply the UDI module "basic use case".
*
* \section udc_use_case_5_usage Usage steps
*
* \subsection udc_use_case_5_usage_code Example code
* Content of conf_usb.h:
* \code
#define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED)
#define UDC_SUSPEND_EVENT() user_callback_suspend_action()
extern void user_callback_suspend_action(void)
#define UDC_RESUME_EVENT() user_callback_resume_action()
extern void user_callback_resume_action(void)
\endcode
*
* Add to application C-file:
* \code
void user_callback_suspend_action(void)
{
// Disable hardware component to reduce power consumption
}
void user_callback_resume_action(void)
{
// Re-enable hardware component
}
\endcode
*
* \subsection udc_use_case_5_usage_flow Workflow
* -# Ensure that conf_usb.h is available and contains the following parameters:
* - \code // Authorizes the BUS power feature
#define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) \endcode
* - \code // Define callback called when the host suspend the USB line
#define UDC_SUSPEND_EVENT() user_callback_suspend_action()
extern void user_callback_suspend_action(void); \endcode
* - \code // Define callback called when the host or device resume the USB line
#define UDC_RESUME_EVENT() user_callback_resume_action()
extern void user_callback_resume_action(void); \endcode
* -# Reduce power consumption in suspend mode (max. 2.5mA on Vbus):
* - \code void user_callback_suspend_action(void)
{
turn_off_components();
} \endcode
*/
/**
* \page udc_use_case_6 USB dynamic serial number
*
* In this use case, the USB serial strings is dynamic.
* For a static serial string refer to \ref udc_use_case_2.
*
* \section udc_use_case_6_setup Setup steps
* Prior to implement this use case, be sure to have already
* apply the UDI module "basic use case".
*
* \section udc_use_case_6_usage Usage steps
*
* \subsection udc_use_case_6_usage_code Example code
* Content of conf_usb.h:
* \code
#define USB_DEVICE_SERIAL_NAME
#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number
#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12
extern uint8_t serial_number[];
\endcode
*
* Add to application C-file:
* \code
uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH];
void init_build_usb_serial_number(void)
{
serial_number[0] = 'A';
serial_number[1] = 'B';
...
serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C';
} \endcode
*
* \subsection udc_use_case_6_usage_flow Workflow
* -# Ensure that conf_usb.h is available and contains the following parameters
* required to enable a USB serial number strings dynamically:
* - \code #define USB_DEVICE_SERIAL_NAME // Define this empty
#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number // Give serial array pointer
#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12 // Give size of serial array
extern uint8_t serial_number[]; // Declare external serial array \endcode
* -# Before start USB stack, initialize the serial array
* - \code
uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH];
void init_build_usb_serial_number(void)
{
serial_number[0] = 'A';
serial_number[1] = 'B';
...
serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C';
} \endcode
*/
#endif // _UDC_H_

132
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/udc/udc_desc.h Normal file
View file

@ -0,0 +1,132 @@
/**
* \file
*
* \brief Common API for USB Device Interface
*
* Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _UDC_DESC_H_
#define _UDC_DESC_H_
#include "conf_usb.h"
#include "usb_protocol.h"
#include "udi.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup udc_group
* \defgroup udc_desc_group USB Device Descriptor
*
* @{
*/
/**
* \brief Defines the memory's location of USB descriptors
*
* By default the Descriptor is stored in RAM
* (UDC_DESC_STORAGE is defined empty).
*
* If you have need to free RAM space,
* it is possible to put descriptor in flash in following case:
* - USB driver authorize flash transfer (USBB on UC3 and USB on Mega)
* - USB Device is not high speed (UDC no need to change USB descriptors)
*
* For UC3 application used "const".
*
* For Mega application used "code".
*/
#define UDC_DESC_STORAGE
// Descriptor storage in internal RAM
#if (defined UDC_DATA_USE_HRAM_SUPPORT)
# if defined(__GNUC__)
# define UDC_DATA(x) COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0")))
# define UDC_BSS(x) COMPILER_ALIGNED(x) __attribute__((__section__(".bss_hram0")))
# elif defined(__ICCAVR32__)
# define UDC_DATA(x) COMPILER_ALIGNED(x) __data32
# define UDC_BSS(x) COMPILER_ALIGNED(x) __data32
# endif
#else
# define UDC_DATA(x) COMPILER_ALIGNED(x)
# define UDC_BSS(x) COMPILER_ALIGNED(x)
#endif
/**
* \brief Configuration descriptor and UDI link for one USB speed
*/
typedef struct {
//! USB configuration descriptor
usb_conf_desc_t UDC_DESC_STORAGE *desc;
//! Array of UDI API pointer
udi_api_t UDC_DESC_STORAGE *UDC_DESC_STORAGE * udi_apis;
} udc_config_speed_t;
/**
* \brief All information about the USB Device
*/
typedef struct {
//! USB device descriptor for low or full speed
usb_dev_desc_t UDC_DESC_STORAGE *confdev_lsfs;
//! USB configuration descriptor and UDI API pointers for low or full speed
udc_config_speed_t UDC_DESC_STORAGE *conf_lsfs;
#ifdef USB_DEVICE_HS_SUPPORT
//! USB device descriptor for high speed
usb_dev_desc_t UDC_DESC_STORAGE *confdev_hs;
//! USB device qualifier, only use in high speed mode
usb_dev_qual_desc_t UDC_DESC_STORAGE *qualifier;
//! USB configuration descriptor and UDI API pointers for high speed
udc_config_speed_t UDC_DESC_STORAGE *conf_hs;
#endif
usb_dev_bos_desc_t UDC_DESC_STORAGE *conf_bos;
} udc_config_t;
//! Global variables of USB Device Descriptor and UDI links
extern UDC_DESC_STORAGE udc_config_t udc_config;
//@}
#ifdef __cplusplus
}
#endif
#endif // _UDC_DESC_H_

393
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/udc/udd.h Normal file
View file

@ -0,0 +1,393 @@
/**
* \file
*
* \brief Common API for USB Device Drivers (UDD)
*
* Copyright (c) 2009 - 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _UDD_H_
#define _UDD_H_
#include "usb_protocol.h"
#include "udc_desc.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup usb_device_group
* \defgroup udd_group USB Device Driver (UDD)
*
* The UDD driver provides a low-level abstraction of the device
* controller hardware. Most events coming from the hardware such as
* interrupts, which may cause the UDD to call into the UDC and UDI.
*
* @{
*/
//! \brief Endpoint identifier
typedef uint8_t udd_ep_id_t;
//! \brief Endpoint transfer status
//! Returned in parameters of callback register via udd_ep_run routine.
typedef enum {
UDD_EP_TRANSFER_OK = 0,
UDD_EP_TRANSFER_ABORT = 1,
} udd_ep_status_t;
/**
* \brief Global variable to give and record information of the setup request management
*
* This global variable allows to decode and response a setup request.
* It can be updated by udc_process_setup() from UDC or *setup() from UDIs.
*/
typedef struct {
//! Data received in USB SETUP packet
//! Note: The swap of "req.wValues" from uin16_t to le16_t is done by UDD.
usb_setup_req_t req;
//! Point to buffer to send or fill with data following SETUP packet
//! This buffer must be word align for DATA IN phase (use prefix COMPILER_WORD_ALIGNED for buffer)
uint8_t *payload;
//! Size of buffer to send or fill, and content the number of byte transfered
uint16_t payload_size;
//! Callback called after reception of ZLP from setup request
void (*callback) (void);
//! Callback called when the buffer given (.payload) is full or empty.
//! This one return false to abort data transfer, or true with a new buffer in .payload.
bool(*over_under_run) (void);
} udd_ctrl_request_t;
extern udd_ctrl_request_t udd_g_ctrlreq;
//! Return true if the setup request \a udd_g_ctrlreq indicates IN data transfer
#define Udd_setup_is_in() \
(USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
//! Return true if the setup request \a udd_g_ctrlreq indicates OUT data transfer
#define Udd_setup_is_out() \
(USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK))
//! Return the type of the SETUP request \a udd_g_ctrlreq. \see usb_reqtype.
#define Udd_setup_type() \
(udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK)
//! Return the recipient of the SETUP request \a udd_g_ctrlreq. \see usb_recipient
#define Udd_setup_recipient() \
(udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK)
/**
* \brief End of halt callback function type.
* Registered by routine udd_ep_wait_stall_clear()
* Callback called when endpoint stall is cleared.
*/
typedef void (*udd_callback_halt_cleared_t) (void);
/**
* \brief End of transfer callback function type.
* Registered by routine udd_ep_run()
* Callback called by USB interrupt after data transfer or abort (reset,...).
*
* \param status UDD_EP_TRANSFER_OK, if transfer is complete
* \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted
* \param n number of data transfered
*/
typedef void (*udd_callback_trans_t) (udd_ep_status_t status,
iram_size_t nb_transfered, udd_ep_id_t ep);
/**
* \brief Authorizes the VBUS event
*
* \return true, if the VBUS monitoring is possible.
*/
bool udd_include_vbus_monitoring(void);
/**
* \brief Enables the USB Device mode
*/
void udd_enable(void);
/**
* \brief Disables the USB Device mode
*/
void udd_disable(void);
/**
* \brief Attach device to the bus when possible
*
* \warning If a VBus control is included in driver,
* then it will attach device when an acceptable Vbus
* level from the host is detected.
*/
void udd_attach(void);
/**
* \brief Detaches the device from the bus
*
* The driver must remove pull-up on USB line D- or D+.
*/
void udd_detach(void);
/**
* \brief Test whether the USB Device Controller is running at high
* speed or not.
*
* \return \c true if the Device is running at high speed mode, otherwise \c false.
*/
bool udd_is_high_speed(void);
/**
* \brief Changes the USB address of device
*
* \param address New USB address
*/
void udd_set_address(uint8_t address);
/**
* \brief Returns the USB address of device
*
* \return USB address
*/
uint8_t udd_getaddress(void);
/**
* \brief Returns the current start of frame number
*
* \return current start of frame number.
*/
uint16_t udd_get_frame_number(void);
/**
* \brief Returns the current micro start of frame number
*
* \return current micro start of frame number required in high speed mode.
*/
uint16_t udd_get_micro_frame_number(void);
/*! \brief The USB driver sends a resume signal called Upstream Resume
*/
void udd_send_remotewakeup(void);
/**
* \brief Load setup payload
*
* \param payload Pointer on payload
* \param payload_size Size of payload
*/
void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size );
/**
* \name Endpoint Management
*
* The following functions allow drivers to create and remove
* endpoints, as well as set, clear and query their "halted" and
* "wedged" states.
*/
//@{
#if (USB_DEVICE_MAX_EP != 0)
/**
* \brief Configures and enables an endpoint
*
* \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT).
* \param bmAttributes Attributes of endpoint declared in the descriptor.
* \param MaxEndpointSize Endpoint maximum size
*
* \return \c 1 if the endpoint is enabled, otherwise \c 0.
*/
bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes,
uint16_t MaxEndpointSize);
/**
* \brief Disables an endpoint
*
* \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT).
*/
void udd_ep_free(udd_ep_id_t ep);
/**
* \brief Check if the endpoint \a ep is halted.
*
* \param ep The ID of the endpoint to check.
*
* \return \c 1 if \a ep is halted, otherwise \c 0.
*/
bool udd_ep_is_halted(udd_ep_id_t ep);
/**
* \brief Set the halted state of the endpoint \a ep
*
* After calling this function, any transaction on \a ep will result
* in a STALL handshake being sent. Any pending transactions will be
* performed first, however.
*
* \param ep The ID of the endpoint to be halted
*
* \return \c 1 if \a ep is halted, otherwise \c 0.
*/
bool udd_ep_set_halt(udd_ep_id_t ep);
/**
* \brief Clear the halted state of the endpoint \a ep
*
* After calling this function, any transaction on \a ep will
* be handled normally, i.e. a STALL handshake will not be sent, and
* the data toggle sequence will start at DATA0.
*
* \param ep The ID of the endpoint to be un-halted
*
* \return \c 1 if function was successfully done, otherwise \c 0.
*/
bool udd_ep_clear_halt(udd_ep_id_t ep);
/**
* \brief Registers a callback to call when endpoint halt is cleared
*
* \param ep The ID of the endpoint to use
* \param callback NULL or function to call when endpoint halt is cleared
*
* \warning if the endpoint is not halted then the \a callback is called immediately.
*
* \return \c 1 if the register is accepted, otherwise \c 0.
*/
bool udd_ep_wait_stall_clear(udd_ep_id_t ep,
udd_callback_halt_cleared_t callback);
/**
* \brief Allows to receive or send data on an endpoint
*
* The driver uses a specific DMA USB to transfer data
* from internal RAM to endpoint, if this one is available.
* When the transfer is finished or aborted (stall, reset, ...), the \a callback is called.
* The \a callback returns the transfer status and eventually the number of byte transfered.
* Note: The control endpoint is not authorized.
*
* \param ep The ID of the endpoint to use
* \param b_shortpacket Enabled automatic short packet
* \param buf Buffer on Internal RAM to send or fill.
* It must be align, then use COMPILER_WORD_ALIGNED.
* \param buf_size Buffer size to send or fill
* \param callback NULL or function to call at the end of transfer
*
* \warning About \a b_shortpacket, for IN endpoint it means that a short packet
* (or a Zero Length Packet) will be sent to the USB line to properly close the usb
* transfer at the end of the data transfer.
* For Bulk and Interrupt OUT endpoint, it will automatically stop the transfer
* at the end of the data transfer (received short packet).
*
* \return \c 1 if function was successfully done, otherwise \c 0.
*/
bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket,
uint8_t * buf, iram_size_t buf_size,
udd_callback_trans_t callback);
/**
* \brief Aborts transfer on going on endpoint
*
* If a transfer is on going, then it is stopped and
* the callback registered is called to signal the end of transfer.
* Note: The control endpoint is not authorized.
*
* \param ep Endpoint to abort
*/
void udd_ep_abort(udd_ep_id_t ep);
#endif
//@}
/**
* \name High speed test mode management
*
* The following functions allow the device to jump to a specific test mode required in high speed mode.
*/
//@{
void udd_test_mode_j(void);
void udd_test_mode_k(void);
void udd_test_mode_se0_nak(void);
void udd_test_mode_packet(void);
//@}
/**
* \name UDC callbacks to provide for UDD
*
* The following callbacks are used by UDD.
*/
//@{
/**
* \brief Decodes and manages a setup request
*
* The driver call it when a SETUP packet is received.
* The \c udd_g_ctrlreq contains the data of SETUP packet.
* If this callback accepts the setup request then it must
* return \c 1 and eventually update \c udd_g_ctrlreq to send or receive data.
*
* \return \c 1 if the request is accepted, otherwise \c 0.
*/
extern bool udc_process_setup(void);
/**
* \brief Reset the UDC
*
* The UDC must reset all configuration.
*/
extern void udc_reset(void);
/**
* \brief To signal that a SOF is occurred
*
* The UDC must send the signal to all UDIs enabled
*/
extern void udc_sof_notify(void);
//@}
//@}
#ifdef __cplusplus
}
#endif
#endif // _UDD_H_

130
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/udc/udi.h Normal file
View file

@ -0,0 +1,130 @@
/**
* \file
*
* \brief Common API for USB Device Interface
*
* Copyright (c) 2009 - 2012 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _UDI_H_
#define _UDI_H_
#include "conf_usb.h"
#include "usb_protocol.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup usb_device_group
* \defgroup udi_group USB Device Interface (UDI)
* The UDI provides a common API for all classes,
* and this is used by UDC for the main control of USB Device interface.
* @{
*/
/**
* \brief UDI API.
*
* The callbacks within this structure are called only by
* USB Device Controller (UDC)
*
* The udc_get_interface_desc() can be use by UDI to know the interface descriptor
* selected by UDC.
*/
typedef struct {
/**
* \brief Enable the interface.
*
* This function is called when the host selects a configuration
* to which this interface belongs through a Set Configuration
* request, and when the host selects an alternate setting of
* this interface through a Set Interface request.
*
* \return \c 1 if function was successfully done, otherwise \c 0.
*/
bool(*enable) (void);
/**
* \brief Disable the interface.
*
* This function is called when this interface is currently
* active, and
* - the host selects any configuration through a Set
* Configuration request, or
* - the host issues a USB reset, or
* - the device is detached from the host (i.e. Vbus is no
* longer present)
*/
void (*disable) (void);
/**
* \brief Handle a control request directed at an interface.
*
* This function is called when this interface is currently
* active and the host sends a SETUP request
* with this interface as the recipient.
*
* Use udd_g_ctrlreq to decode and response to SETUP request.
*
* \return \c 1 if this interface supports the SETUP request, otherwise \c 0.
*/
bool(*setup) (void);
/**
* \brief Returns the current setting of the selected interface.
*
* This function is called when UDC when know alternate setting of selected interface.
*
* \return alternate setting of selected interface
*/
uint8_t(*getsetting) (void);
/**
* \brief To signal that a SOF is occurred
*/
void(*sof_notify) (void);
} udi_api_t;
//@}
#ifdef __cplusplus
}
#endif
#endif // _UDI_H_

187
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/usb_atmel.h Normal file
View file

@ -0,0 +1,187 @@
/**
* \file
*
* \brief All USB VIDs and PIDs from Atmel USB applications
*
* Copyright (c) 2009-2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _USB_ATMEL_H_
#define _USB_ATMEL_H_
/**
* \defgroup usb_group USB Stack
*
* This stack includes the USB Device Stack, USB Host Stack and common
* definitions.
* @{
*/
//! @}
/**
* \ingroup usb_group
* \defgroup usb_atmel_ids_group Atmel USB Identifiers
*
* This module defines Atmel PID and VIDs constants.
*
* @{
*/
//! \name Vendor Identifier assigned by USB org to ATMEL
#define USB_VID_ATMEL 0x03EB
//! \name Product Identifier assigned by ATMEL to AVR applications
//! @{
//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others.
//! @{
#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013
#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017
#define USB_PID_ATMEL_MEGA_CDC 0x2018
#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019
#define USB_PID_ATMEL_MEGA_MS 0x201A
#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B
#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C
#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D
#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E
#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022
#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023
#define USB_PID_ATMEL_MEGA_MS_2 0x2029
#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A
#define USB_PID_ATMEL_MEGA_MS_3 0x2032
#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050
//! @}
//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools.
//! @{
#define USB_PID_ATMEL_XPLAINED 0x2122
#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A
#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B
//! @}
//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=>
//! @{
#define USB_PID_ATMEL_UC3_ENUM 0x2300
#define USB_PID_ATMEL_UC3_MS 0x2301
#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302
#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303
#define USB_PID_ATMEL_UC3_HID 0x2304
#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305
#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306
#define USB_PID_ATMEL_UC3_CDC 0x2307
#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308
#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx
#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311
#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312
//! @}
//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications
//! @{
#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400
#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401
#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402
#define USB_PID_ATMEL_ASF_MSC 0x2403
#define USB_PID_ATMEL_ASF_CDC 0x2404
#define USB_PID_ATMEL_ASF_PHDC 0x2405
#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420
#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421
#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422
#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423
#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424
#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425
#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426
#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430
#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431
#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432
#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433
#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434
//! @}
//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders
//! Note, !!!! don't use this range for demos or examples !!!!
//! @{
#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6
#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7
#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8
#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9
#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA
#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB
#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC
#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD
#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE
#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF
#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0
#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1
#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2
#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3
#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4
#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5
#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6
#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7
#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8
#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9
#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA
#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB
#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC
#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED
#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE
#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF
#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0
#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1
#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2
#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3
#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4
#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5
#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6
#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7
#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8
#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9
#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA
#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB
// 2FFCh to 2FFFh used by C51 family products
//! @}
//! @}
//! @}
#endif // _USB_ATMEL_H_

502
bootloaders/mzero/Bootloader_D21/src/ASF/common/services/usb/usb_protocol.h Normal file
View file

@ -0,0 +1,502 @@
/**
* \file
*
* \brief USB protocol definitions.
*
* This file contains the USB definitions and data structures provided by the
* USB 2.0 specification.
*
* Copyright (c) 2009-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _USB_PROTOCOL_H_
#define _USB_PROTOCOL_H_
#include "usb_atmel.h"
/**
* \ingroup usb_group
* \defgroup usb_protocol_group USB Protocol Definitions
*
* This module defines constants and data structures provided by the USB
* 2.0 specification.
*
* @{
*/
//! Value for field bcdUSB
#define USB_V2_0 0x0200 //!< USB Specification version 2.00
#define USB_V2_1 0x0201 //!< USB Specification version 2.01
/*! \name Generic definitions (Class, subclass and protocol)
*/
//! @{
#define NO_CLASS 0x00
#define CLASS_VENDOR_SPECIFIC 0xFF
#define NO_SUBCLASS 0x00
#define NO_PROTOCOL 0x00
//! @}
//! \name IAD (Interface Association Descriptor) constants
//! @{
#define CLASS_IAD 0xEF
#define SUB_CLASS_IAD 0x02
#define PROTOCOL_IAD 0x01
//! @}
/**
* \brief USB request data transfer direction (bmRequestType)
*/
#define USB_REQ_DIR_OUT (0<<7) //!< Host to device
#define USB_REQ_DIR_IN (1<<7) //!< Device to host
#define USB_REQ_DIR_MASK (1<<7) //!< Mask
/**
* \brief USB request types (bmRequestType)
*/
#define USB_REQ_TYPE_STANDARD (0<<5) //!< Standard request
#define USB_REQ_TYPE_CLASS (1<<5) //!< Class-specific request
#define USB_REQ_TYPE_VENDOR (2<<5) //!< Vendor-specific request
#define USB_REQ_TYPE_MASK (3<<5) //!< Mask
/**
* \brief USB recipient codes (bmRequestType)
*/
#define USB_REQ_RECIP_DEVICE (0<<0) //!< Recipient device
#define USB_REQ_RECIP_INTERFACE (1<<0) //!< Recipient interface
#define USB_REQ_RECIP_ENDPOINT (2<<0) //!< Recipient endpoint
#define USB_REQ_RECIP_OTHER (3<<0) //!< Recipient other
#define USB_REQ_RECIP_MASK (0x1F) //!< Mask
/**
* \brief Standard USB requests (bRequest)
*/
enum usb_reqid {
USB_REQ_GET_STATUS = 0,
USB_REQ_CLEAR_FEATURE = 1,
USB_REQ_SET_FEATURE = 3,
USB_REQ_SET_ADDRESS = 5,
USB_REQ_GET_DESCRIPTOR = 6,
USB_REQ_SET_DESCRIPTOR = 7,
USB_REQ_GET_CONFIGURATION = 8,
USB_REQ_SET_CONFIGURATION = 9,
USB_REQ_GET_INTERFACE = 10,
USB_REQ_SET_INTERFACE = 11,
USB_REQ_SYNCH_FRAME = 12,
};
/**
* \brief Standard USB device status flags
*
*/
enum usb_device_status {
USB_DEV_STATUS_BUS_POWERED = 0,
USB_DEV_STATUS_SELF_POWERED = 1,
USB_DEV_STATUS_REMOTEWAKEUP = 2
};
/**
* \brief Standard USB Interface status flags
*
*/
enum usb_interface_status {
USB_IFACE_STATUS_RESERVED = 0
};
/**
* \brief Standard USB endpoint status flags
*
*/
enum usb_endpoint_status {
USB_EP_STATUS_HALTED = 1,
};
/**
* \brief Standard USB device feature flags
*
* \note valid for SetFeature request.
*/
enum usb_device_feature {
USB_DEV_FEATURE_REMOTE_WAKEUP = 1, //!< Remote wakeup enabled
USB_DEV_FEATURE_TEST_MODE = 2, //!< USB test mode
USB_DEV_FEATURE_OTG_B_HNP_ENABLE = 3,
USB_DEV_FEATURE_OTG_A_HNP_SUPPORT = 4,
USB_DEV_FEATURE_OTG_A_ALT_HNP_SUPPORT = 5
};
/**
* \brief Test Mode possible on HS USB device
*
* \note valid for USB_DEV_FEATURE_TEST_MODE request.
*/
enum usb_device_hs_test_mode {
USB_DEV_TEST_MODE_J = 1,
USB_DEV_TEST_MODE_K = 2,
USB_DEV_TEST_MODE_SE0_NAK = 3,
USB_DEV_TEST_MODE_PACKET = 4,
USB_DEV_TEST_MODE_FORCE_ENABLE = 5,
};
/**
* \brief Standard USB endpoint feature/status flags
*/
enum usb_endpoint_feature {
USB_EP_FEATURE_HALT = 0,
};
/**
* \brief Standard USB Test Mode Selectors
*/
enum usb_test_mode_selector {
USB_TEST_J = 0x01,
USB_TEST_K = 0x02,
USB_TEST_SE0_NAK = 0x03,
USB_TEST_PACKET = 0x04,
USB_TEST_FORCE_ENABLE = 0x05,
};
/**
* \brief Standard USB descriptor types
*/
enum usb_descriptor_type {
USB_DT_DEVICE = 1,
USB_DT_CONFIGURATION = 2,
USB_DT_STRING = 3,
USB_DT_INTERFACE = 4,
USB_DT_ENDPOINT = 5,
USB_DT_DEVICE_QUALIFIER = 6,
USB_DT_OTHER_SPEED_CONFIGURATION = 7,
USB_DT_INTERFACE_POWER = 8,
USB_DT_OTG = 9,
USB_DT_IAD = 0x0B,
USB_DT_BOS = 0x0F,
USB_DT_DEVICE_CAPABILITY = 0x10,
};
/**
* \brief USB Device Capability types
*/
enum usb_capability_type {
USB_DC_USB20_EXTENSION = 0x02,
};
/**
* \brief USB Device Capability - USB 2.0 Extension
* To fill bmAttributes field of usb_capa_ext_desc_t structure.
*/
enum usb_capability_extension_attr {
USB_DC_EXT_LPM = 0x00000002,
USB_DC_EXT_BESL = 0x00000004,
USB_DC_EXT_BESL_BASELINE_VALID = 0x00000008,
USB_DC_EXT_BESL_DEEP_VALID = 0x00000010,
};
#define USB_DC_EXT_BESL_DEEP_OFFSET 8
#define USB_DC_EXT_BESL_DEEP(besl) ((besl & 0xF) << USB_DC_EXT_BESL_DEEP_OFFSET)
#define USB_DC_EXT_BESL_BASELINE_OFFSET 12
#define USB_DC_EXT_BESL_BASELINE(besl) ((besl & 0xF) << USB_DC_EXT_BESL_BASELINE_OFFSET)
#define BESL_125_US 0
#define BESL_150_US 1
#define BESL_200_US 2
#define BESL_300_US 3
#define BESL_400_US 4
#define BESL_500_US 5
#define BESL_1000_US 6
#define BESL_2000_US 7
#define BESL_3000_US 8
#define BESL_4000_US 9
#define BESL_5000_US 10
#define BESL_6000_US 11
#define BESL_7000_US 12
#define BESL_8000_US 13
#define BESL_9000_US 14
#define BESL_10000_US 15
/** Fields definition from a LPM TOKEN */
#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0)
#define USB_LPM_ATTRIBUT_BESL_MASK (0xF << 4)
#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8)
#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0)
#define USB_LPM_ATTRIBUT_BESL(value) ((value & 0xF) << 4)
#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8)
#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1)
/**
* \brief Standard USB endpoint transfer types
*/
enum usb_ep_type {
USB_EP_TYPE_CONTROL = 0x00,
USB_EP_TYPE_ISOCHRONOUS = 0x01,
USB_EP_TYPE_BULK = 0x02,
USB_EP_TYPE_INTERRUPT = 0x03,
USB_EP_TYPE_MASK = 0x03,
};
/**
* \brief Standard USB language IDs for string descriptors
*/
enum usb_langid {
USB_LANGID_EN_US = 0x0409, //!< English (United States)
};
/**
* \brief Mask selecting the index part of an endpoint address
*/
#define USB_EP_ADDR_MASK 0x0f
//! \brief USB address identifier
typedef uint8_t usb_add_t;
/**
* \brief Endpoint transfer direction is IN
*/
#define USB_EP_DIR_IN 0x80
/**
* \brief Endpoint transfer direction is OUT
*/
#define USB_EP_DIR_OUT 0x00
//! \brief Endpoint identifier
typedef uint8_t usb_ep_t;
/**
* \brief Maximum length in bytes of a USB descriptor
*
* The maximum length of a USB descriptor is limited by the 8-bit
* bLength field.
*/
#define USB_MAX_DESC_LEN 255
/*
* 2-byte alignment requested for all USB structures.
*/
COMPILER_PACK_SET(1)
/**
* \brief A USB Device SETUP request
*
* The data payload of SETUP packets always follows this structure.
*/
typedef struct {
uint8_t bmRequestType;
uint8_t bRequest;
le16_t wValue;
le16_t wIndex;
le16_t wLength;
} usb_setup_req_t;
/**
* \brief Standard USB device descriptor structure
*/
typedef struct {
uint8_t bLength;
uint8_t bDescriptorType;
le16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
le16_t idVendor;
le16_t idProduct;
le16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
} usb_dev_desc_t;
/**
* \brief Standard USB device qualifier descriptor structure
*
* This descriptor contains information about the device when running at
* the "other" speed (i.e. if the device is currently operating at high
* speed, this descriptor can be used to determine what would change if
* the device was operating at full speed.)
*/
typedef struct {
uint8_t bLength;
uint8_t bDescriptorType;
le16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint8_t bNumConfigurations;
uint8_t bReserved;
} usb_dev_qual_desc_t;
/**
* \brief USB Device BOS descriptor structure
*
* The BOS descriptor (Binary device Object Store) defines a root
* descriptor that is similar to the configuration descriptor, and is
* the base descriptor for accessing a family of related descriptors.
* A host can read a BOS descriptor and learn from the wTotalLength field
* the entire size of the device-level descriptor set, or it can read in
* the entire BOS descriptor set of device capabilities.
* The host accesses this descriptor using the GetDescriptor() request.
* The descriptor type in the GetDescriptor() request is set to BOS.
*/
typedef struct {
uint8_t bLength;
uint8_t bDescriptorType;
le16_t wTotalLength;
uint8_t bNumDeviceCaps;
} usb_dev_bos_desc_t;
/**
* \brief USB Device Capabilities - USB 2.0 Extension Descriptor structure
*
* Defines the set of USB 1.1-specific device level capabilities.
*/
typedef struct {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bDevCapabilityType;
le32_t bmAttributes;
} usb_dev_capa_ext_desc_t;
/**
* \brief USB Device LPM Descriptor structure
*
* The BOS descriptor and capabilities descriptors for LPM.
*/
typedef struct {
usb_dev_bos_desc_t bos;
usb_dev_capa_ext_desc_t capa_ext;
} usb_dev_lpm_desc_t;
/**
* \brief Standard USB Interface Association Descriptor structure
*/
typedef struct {
uint8_t bLength; //!< size of this descriptor in bytes
uint8_t bDescriptorType; //!< INTERFACE descriptor type
uint8_t bFirstInterface; //!< Number of interface
uint8_t bInterfaceCount; //!< value to select alternate setting
uint8_t bFunctionClass; //!< Class code assigned by the USB
uint8_t bFunctionSubClass;//!< Sub-class code assigned by the USB
uint8_t bFunctionProtocol;//!< Protocol code assigned by the USB
uint8_t iFunction; //!< Index of string descriptor
} usb_association_desc_t;
/**
* \brief Standard USB configuration descriptor structure
*/
typedef struct {
uint8_t bLength;
uint8_t bDescriptorType;
le16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t bMaxPower;
} usb_conf_desc_t;
#define USB_CONFIG_ATTR_MUST_SET (1 << 7) //!< Must always be set
#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) //!< Bus-powered
#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) //!< Self-powered
#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) //!< remote wakeup supported
#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) //!< Max power in mA
/**
* \brief Standard USB association descriptor structure
*/
typedef struct {
uint8_t bLength; //!< Size of this descriptor in bytes
uint8_t bDescriptorType; //!< Interface descriptor type
uint8_t bFirstInterface; //!< Number of interface
uint8_t bInterfaceCount; //!< value to select alternate setting
uint8_t bFunctionClass; //!< Class code assigned by the USB
uint8_t bFunctionSubClass; //!< Sub-class code assigned by the USB
uint8_t bFunctionProtocol; //!< Protocol code assigned by the USB
uint8_t iFunction; //!< Index of string descriptor
} usb_iad_desc_t;
/**
* \brief Standard USB interface descriptor structure
*/
typedef struct {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
} usb_iface_desc_t;
/**
* \brief Standard USB endpoint descriptor structure
*/
typedef struct {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
le16_t wMaxPacketSize;
uint8_t bInterval;
} usb_ep_desc_t;
/**
* \brief A standard USB string descriptor structure
*/
typedef struct {
uint8_t bLength;
uint8_t bDescriptorType;
} usb_str_desc_t;
typedef struct {
usb_str_desc_t desc;
le16_t string[1];
} usb_str_lgid_desc_t;
COMPILER_PACK_RESET()
//! @}
#endif /* _USB_PROTOCOL_H_ */

139
bootloaders/mzero/Bootloader_D21/src/ASF/common/utils/interrupt.h Normal file
View file

@ -0,0 +1,139 @@
/**
* \file
*
* \brief Global interrupt management for 8- and 32-bit AVR
*
* Copyright (c) 2010-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef UTILS_INTERRUPT_H
#define UTILS_INTERRUPT_H
#include <parts.h>
#if XMEGA || MEGA || TINY
# include "interrupt/interrupt_avr8.h"
#elif UC3
# include "interrupt/interrupt_avr32.h"
#elif SAM
# include "interrupt/interrupt_sam_nvic.h"
#else
# error Unsupported device.
#endif
/**
* \defgroup interrupt_group Global interrupt management
*
* This is a driver for global enabling and disabling of interrupts.
*
* @{
*/
#if defined(__DOXYGEN__)
/**
* \def CONFIG_INTERRUPT_FORCE_INTC
* \brief Force usage of the ASF INTC driver
*
* Predefine this symbol when preprocessing to force the use of the ASF INTC driver.
* This is useful to ensure compatibility across compilers and shall be used only when required
* by the application needs.
*/
# define CONFIG_INTERRUPT_FORCE_INTC
#endif
//! \name Global interrupt flags
//@{
/**
* \typedef irqflags_t
* \brief Type used for holding state of interrupt flag
*/
/**
* \def cpu_irq_enable
* \brief Enable interrupts globally
*/
/**
* \def cpu_irq_disable
* \brief Disable interrupts globally
*/
/**
* \fn irqflags_t cpu_irq_save(void)
* \brief Get and clear the global interrupt flags
*
* Use in conjunction with \ref cpu_irq_restore.
*
* \return Current state of interrupt flags.
*
* \note This function leaves interrupts disabled.
*/
/**
* \fn void cpu_irq_restore(irqflags_t flags)
* \brief Restore global interrupt flags
*
* Use in conjunction with \ref cpu_irq_save.
*
* \param flags State to set interrupt flag to.
*/
/**
* \fn bool cpu_irq_is_enabled_flags(irqflags_t flags)
* \brief Check if interrupts are globally enabled in supplied flags
*
* \param flags Currents state of interrupt flags.
*
* \return True if interrupts are enabled.
*/
/**
* \def cpu_irq_is_enabled
* \brief Check if interrupts are globally enabled
*
* \return True if interrupts are enabled.
*/
//@}
//! @}
/**
* \ingroup interrupt_group
* \defgroup interrupt_deprecated_group Deprecated interrupt definitions
*/
#endif /* UTILS_INTERRUPT_H */

83
bootloaders/mzero/Bootloader_D21/src/ASF/common/utils/interrupt/interrupt_sam_nvic.c Normal file
View file

@ -0,0 +1,83 @@
/**
* \file
*
* \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
*
* Copyright (c) 2012-2013 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "interrupt_sam_nvic.h"
#if !defined(__DOXYGEN__)
/* Deprecated - global flag to determine the global interrupt state. Required by
* QTouch library, however new applications should use cpu_irq_is_enabled()
* which probes the true global interrupt state from the CPU special registers.
*/
volatile bool g_interrupt_enabled = true;
#endif
void cpu_irq_enter_critical(void)
{
if (cpu_irq_critical_section_counter == 0) {
if (cpu_irq_is_enabled()) {
cpu_irq_disable();
cpu_irq_prev_interrupt_state = true;
} else {
/* Make sure the to save the prev state as false */
cpu_irq_prev_interrupt_state = false;
}
}
cpu_irq_critical_section_counter++;
}
void cpu_irq_leave_critical(void)
{
/* Check if the user is trying to leave a critical section when not in a critical section */
Assert(cpu_irq_critical_section_counter > 0);
cpu_irq_critical_section_counter--;
/* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag
was enabled when entering critical state */
if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) {
cpu_irq_enable();
}
}

186
bootloaders/mzero/Bootloader_D21/src/ASF/common/utils/interrupt/interrupt_sam_nvic.h Normal file
View file

@ -0,0 +1,186 @@
/**
* \file
*
* \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based)
*
* Copyright (c) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef UTILS_INTERRUPT_INTERRUPT_H
#define UTILS_INTERRUPT_INTERRUPT_H
#include <compiler.h>
#include <parts.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \weakgroup interrupt_group
*
* @{
*/
/**
* \name Interrupt Service Routine definition
*
* @{
*/
/**
* \brief Define service routine
*
* \note For NVIC devices the interrupt service routines are predefined to
* add to vector table in binary generation, so there is no service
* register at run time. The routine collections are in exceptions.h.
*
* Usage:
* \code
ISR(foo_irq_handler)
{
// Function definition
...
}
\endcode
*
* \param func Name for the function.
*/
# define ISR(func) \
void func (void)
/**
* \brief Initialize interrupt vectors
*
* For NVIC the interrupt vectors are put in vector table. So nothing
* to do to initialize them, except defined the vector function with
* right name.
*
* This must be called prior to \ref irq_register_handler.
*/
# define irq_initialize_vectors() \
do { \
} while(0)
/**
* \brief Register handler for interrupt
*
* For NVIC the interrupt vectors are put in vector table. So nothing
* to do to register them, except defined the vector function with
* right name.
*
* Usage:
* \code
irq_initialize_vectors();
irq_register_handler(foo_irq_handler);
\endcode
*
* \note The function \a func must be defined with the \ref ISR macro.
* \note The functions prototypes can be found in the device exception header
* files (exceptions.h).
*/
# define irq_register_handler(int_num, int_prio) \
NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \
NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \
NVIC_EnableIRQ( (IRQn_Type)int_num); \
//@}
# define cpu_irq_enable() \
do { \
g_interrupt_enabled = true; \
__DMB(); \
__enable_irq(); \
} while (0)
# define cpu_irq_disable() \
do { \
__disable_irq(); \
__DMB(); \
g_interrupt_enabled = false; \
} while (0)
typedef uint32_t irqflags_t;
#if !defined(__DOXYGEN__)
extern volatile bool g_interrupt_enabled;
#endif
#define cpu_irq_is_enabled() (__get_PRIMASK() == 0)
static volatile uint32_t cpu_irq_critical_section_counter;
static volatile bool cpu_irq_prev_interrupt_state;
static inline irqflags_t cpu_irq_save(void)
{
irqflags_t flags = cpu_irq_is_enabled();
cpu_irq_disable();
return flags;
}
static inline bool cpu_irq_is_enabled_flags(irqflags_t flags)
{
return (flags);
}
static inline void cpu_irq_restore(irqflags_t flags)
{
if (cpu_irq_is_enabled_flags(flags))
cpu_irq_enable();
}
void cpu_irq_enter_critical(void);
void cpu_irq_leave_critical(void);
/**
* \weakgroup interrupt_deprecated_group
* @{
*/
#define Enable_global_interrupt() cpu_irq_enable()
#define Disable_global_interrupt() cpu_irq_disable()
#define Is_global_interrupt_enabled() cpu_irq_is_enabled()
//@}
//@}
#ifdef __cplusplus
}
#endif
#endif /* UTILS_INTERRUPT_INTERRUPT_H */

1242
bootloaders/mzero/Bootloader_D21/src/ASF/common/utils/parts.h Normal file
View file

File diff suppressed because it is too large Load diff

99
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/boards/samd21_xplained_pro/board_init.c Normal file
View file

@ -0,0 +1,99 @@
/**
* \file
*
* \brief SAM D21 Xplained Pro board initialization
*
* Copyright (c) 2013-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include <board.h>
#include <conf_board.h>
#include <port.h>
#if defined(__GNUC__)
void board_init(void) WEAK __attribute__((alias("system_board_init")));
#elif defined(__ICCARM__)
void board_init(void);
# pragma weak board_init=system_board_init
#endif
void system_board_init(void)
{
struct port_config pin_conf;
port_get_config_defaults(&pin_conf);
/* Configure LEDs as outputs, turn them off */
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(LED_0_PIN, &pin_conf);
port_pin_set_output_level(LED_0_PIN, LED_0_INACTIVE);
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(LED_L_PIN, &pin_conf);
port_pin_set_output_level(LED_L_PIN, LED_0_INACTIVE);
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(LED_RX_PIN, &pin_conf);
port_pin_set_output_level(LED_RX_PIN, LED_RX_INACTIVE);
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(LED_TX_PIN, &pin_conf);
port_pin_set_output_level(LED_RX_PIN, LED_RX_INACTIVE);
/* Set buttons as inputs */
pin_conf.direction = PORT_PIN_DIR_INPUT;
pin_conf.input_pull = PORT_PIN_PULL_UP;
port_pin_set_config(BUTTON_0_PIN, &pin_conf);
#ifdef CONF_BOARD_AT86RFX
port_get_config_defaults(&pin_conf);
pin_conf.direction = PORT_PIN_DIR_OUTPUT;
port_pin_set_config(AT86RFX_SPI_SCK, &pin_conf);
port_pin_set_config(AT86RFX_SPI_MOSI, &pin_conf);
port_pin_set_config(AT86RFX_SPI_CS, &pin_conf);
port_pin_set_config(AT86RFX_RST_PIN, &pin_conf);
port_pin_set_config(AT86RFX_SLP_PIN, &pin_conf);
port_pin_set_output_level(AT86RFX_SPI_SCK, true);
port_pin_set_output_level(AT86RFX_SPI_MOSI, true);
port_pin_set_output_level(AT86RFX_SPI_CS, true);
port_pin_set_output_level(AT86RFX_RST_PIN, true);
port_pin_set_output_level(AT86RFX_SLP_PIN, true);
pin_conf.direction = PORT_PIN_DIR_INPUT;
port_pin_set_config(AT86RFX_SPI_MISO, &pin_conf);
#endif
}

756
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/boards/samd21_xplained_pro/samd21_xplained_pro.h Normal file
View file

@ -0,0 +1,756 @@
/**
* \file
*
* \brief SAM D21 Xplained Pro board definition
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
#define SAMD21_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup samd21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAMD21_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED definitions
* @{ */
#define LED0_PIN PIN_PA17 // only for compatibility, this pin is used also by L LED
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
#define LEDL_PIN PIN_PA17 //defining LED L PORT PIN
#define LEDL_ACTIVE false
#define LEDL_INACTIVE !LEDL_ACTIVE
#define LEDRX_PIN PIN_PB03 //defining LED RX PORT PIN
#define LEDRX_ACTIVE false
#define LEDRX_INACTIVE !LEDL_ACTIVE
#define LEDTX_PIN PIN_PA27 //defining LED TX PORT PIN
#define LEDTX_ACTIVE false
#define LEDTX_INACTIVE !LEDL_ACTIVE
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PA15
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PA15A_EIC_EXTINT15
#define SW0_EIC_MUX MUX_PA15A_EIC_EXTINT15
#define SW0_EIC_PINMUX PINMUX_PA15A_EIC_EXTINT15
#define SW0_EIC_LINE 15
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* LED L, LED RX and LED TX are used by Arduino srl SAM D21 based boards. LED 0 remain only for compatibility.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED0 LED0_PIN
#define LED_L_NAME "LED L"
#define LED_L_PIN LEDL_PIN
#define LED_L_ACTIVE LEDL_ACTIVE
#define LED_L_INACTIVE LEDL_INACTIVE
#define LEDL_GPIO LEDL_PIN
#define LEDL LEDL_PIN
#define LED_RX_NAME "LED RX"
#define LED_RX_PIN LEDRX_PIN
#define LED_RX_ACTIVE LEDRX_ACTIVE
#define LED_RX_INACTIVE LEDRX_INACTIVE
#define LEDRX_GPIO LEDRX_PIN
#define LEDRX LEDRX_PIN
#define LED_TX_NAME "LED L"
#define LED_TX_PIN LEDTX_PIN
#define LED_TX_ACTIVE LEDTX_ACTIVE
#define LED_TX_INACTIVE LEDTX_INACTIVE
#define LEDTX_GPIO LEDTX_PIN
#define LEDTX LEDTX_PIN
#define LED_0_PWM4CTRL_MODULE TCC0
#define LED_0_PWM4CTRL_CHANNEL 0
#define LED_0_PWM4CTRL_OUTPUT 0
#define LED_0_PWM4CTRL_PIN PIN_PB30E_TCC0_WO0
#define LED_0_PWM4CTRL_MUX MUX_PB30E_TCC0_WO0
#define LED_0_PWM4CTRL_PINMUX PINMUX_PB30E_TCC0_WO0
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Serialflash definitions
*
* On board Serialflash definitions.
*
* @{ */
#define SERIALFLASH_SPI_MODULE SERCOM5
#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define SERIALFLASH_SPI_CS PIN_PA13
/** @} */
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* button 0 is used only for compatibility purpose, and are not used in Arduino srl SAM D21 Based Boards.
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PB00
#define EXT1_PIN_4 PIN_PB01
#define EXT1_PIN_5 PIN_PB06
#define EXT1_PIN_6 PIN_PB07
#define EXT1_PIN_7 PIN_PB02
#define EXT1_PIN_8 PIN_PB03
#define EXT1_PIN_9 PIN_PB04
#define EXT1_PIN_10 PIN_PB05
#define EXT1_PIN_11 PIN_PA08
#define EXT1_PIN_12 PIN_PA09
#define EXT1_PIN_13 PIN_PB09
#define EXT1_PIN_14 PIN_PB08
#define EXT1_PIN_15 PIN_PA05
#define EXT1_PIN_16 PIN_PA06
#define EXT1_PIN_17 PIN_PA04
#define EXT1_PIN_18 PIN_PA07
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_IRQ EXT1_PIN_9
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_0_CHANNEL 8
#define EXT1_ADC_0_PIN PIN_PB00B_ADC_AIN8
#define EXT1_ADC_0_MUX MUX_PB00B_ADC_AIN8
#define EXT1_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8
#define EXT1_ADC_1_CHANNEL 9
#define EXT1_ADC_1_PIN PIN_PB01B_ADC_AIN9
#define EXT1_ADC_1_MUX MUX_PB01B_ADC_AIN9
#define EXT1_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TC6
#define EXT1_PWM_0_CHANNEL 0
#define EXT1_PWM_0_PIN PIN_PB02E_TC6_WO0
#define EXT1_PWM_0_MUX MUX_PB02E_TC6_WO0
#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC6_WO0
#define EXT1_PWM_1_CHANNEL 1
#define EXT1_PWM_1_PIN PIN_PB03E_TC6_WO1
#define EXT1_PWM_1_MUX MUX_PB03E_TC6_WO1
#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC6_WO1
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 4
#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4
#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4
#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM2
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM4
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM0
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
/** \name Extension header #2 pin definitions
* @{
*/
#define EXT2_PIN_3 PIN_PA10
#define EXT2_PIN_4 PIN_PA11
#define EXT2_PIN_5 PIN_PA20
#define EXT2_PIN_6 PIN_PA21
#define EXT2_PIN_7 PIN_PB12
#define EXT2_PIN_8 PIN_PB13
#define EXT2_PIN_9 PIN_PB14
#define EXT2_PIN_10 PIN_PB15
#define EXT2_PIN_11 PIN_PA08
#define EXT2_PIN_12 PIN_PA09
#define EXT2_PIN_13 PIN_PB11
#define EXT2_PIN_14 PIN_PB10
#define EXT2_PIN_15 PIN_PA17
#define EXT2_PIN_16 PIN_PA18
#define EXT2_PIN_17 PIN_PA16
#define EXT2_PIN_18 PIN_PA19
/** @} */
/** \name Extension header #2 pin definitions by function
* @{
*/
#define EXT2_PIN_ADC_0 EXT2_PIN_3
#define EXT2_PIN_ADC_1 EXT2_PIN_4
#define EXT2_PIN_GPIO_0 EXT2_PIN_5
#define EXT2_PIN_GPIO_1 EXT2_PIN_6
#define EXT2_PIN_PWM_0 EXT2_PIN_7
#define EXT2_PIN_PWM_1 EXT2_PIN_8
#define EXT2_PIN_IRQ EXT2_PIN_9
#define EXT2_PIN_I2C_SDA EXT2_PIN_11
#define EXT2_PIN_I2C_SCL EXT2_PIN_12
#define EXT2_PIN_UART_RX EXT2_PIN_13
#define EXT2_PIN_UART_TX EXT2_PIN_14
#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10
#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15
#define EXT2_PIN_SPI_MOSI EXT2_PIN_16
#define EXT2_PIN_SPI_MISO EXT2_PIN_17
#define EXT2_PIN_SPI_SCK EXT2_PIN_18
/** @} */
/** \name Extension header #2 ADC definitions
* @{
*/
#define EXT2_ADC_MODULE ADC
#define EXT2_ADC_0_CHANNEL 18
#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18
#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18
#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18
#define EXT2_ADC_1_CHANNEL 19
#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19
#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19
#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19
/** @} */
/** \name Extension header #2 PWM definitions
* @{
*/
#define EXT2_PWM_MODULE TC4
#define EXT2_PWM_0_CHANNEL 0
#define EXT2_PWM_0_PIN PIN_PB12E_TC4_WO0
#define EXT2_PWM_0_MUX MUX_PB12E_TC4_WO0
#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC4_WO0
#define EXT2_PWM_1_CHANNEL 1
#define EXT2_PWM_1_PIN PIN_PB13E_TC4_WO1
#define EXT2_PWM_1_MUX MUX_PB13E_TC4_WO1
#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC4_WO1
/** @} */
/** \name Extension header #2 PWM for Control definitions
* @{
*/
#define EXT2_PWM4CTRL_MODULE TCC0
#define EXT2_PWM4CTRL_0_CHANNEL 2
#define EXT2_PWM4CTRL_0_OUTPUT 6
#define EXT2_PWM4CTRL_0_PIN PIN_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_0_MUX MUX_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_0_PINMUX PINMUX_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_1_CHANNEL 3
#define EXT2_PWM4CTRL_1_OUTPUT 7
#define EXT2_PWM4CTRL_1_PIN PIN_PB13F_TCC0_WO7
#define EXT2_PWM4CTRL_1_MUX MUX_PB13F_TCC0_WO7
#define EXT2_PWM4CTRL_1_PINMUX PINMUX_PB13F_TCC0_WO7
/** @} */
/** \name Extension header #2 IRQ/External interrupt definitions
* @{
*/
#define EXT2_IRQ_MODULE EIC
#define EXT2_IRQ_INPUT 14
#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14
#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14
#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
/** @} */
/** \name Extension header #2 I2C definitions
* @{
*/
#define EXT2_I2C_MODULE SERCOM2
#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #2 UART definitions
* @{
*/
#define EXT2_UART_MODULE SERCOM4
#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_PB12C_SERCOM4_PAD0
#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_PB13C_SERCOM4_PAD1
#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #2 SPI definitions
* @{
*/
#define EXT2_SPI_MODULE SERCOM1
#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_3 PIN_PA02
#define EXT3_PIN_4 PIN_PA03
#define EXT3_PIN_5 PIN_PB30
#define EXT3_PIN_6 PIN_PA15
#define EXT3_PIN_7 PIN_PA12
#define EXT3_PIN_8 PIN_PA13
#define EXT3_PIN_9 PIN_PA28
#define EXT3_PIN_10 PIN_PA27
#define EXT3_PIN_11 PIN_PA08
#define EXT3_PIN_12 PIN_PA09
#define EXT3_PIN_13 PIN_PB11
#define EXT3_PIN_14 PIN_PB10
#define EXT3_PIN_15 PIN_PB17
#define EXT3_PIN_16 PIN_PB22
#define EXT3_PIN_17 PIN_PB16
#define EXT3_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_ADC_0 EXT3_PIN_3
#define EXT3_PIN_ADC_1 EXT3_PIN_4
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_6
#define EXT3_PIN_PWM_0 EXT3_PIN_7
#define EXT3_PIN_PWM_1 EXT3_PIN_8
#define EXT3_PIN_IRQ EXT3_PIN_9
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_UART_RX EXT3_PIN_13
#define EXT3_PIN_UART_TX EXT3_PIN_14
#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 ADC definitions
* @{
*/
#define EXT3_ADC_MODULE ADC
#define EXT3_ADC_0_CHANNEL 0
#define EXT3_ADC_0_PIN PIN_PA02B_ADC_AIN0
#define EXT3_ADC_0_MUX MUX_PA02B_ADC_AIN0
#define EXT3_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0
#define EXT3_ADC_1_CHANNEL 1
#define EXT3_ADC_1_PIN PIN_PA03B_ADC_AIN1
#define EXT3_ADC_1_MUX MUX_PA03B_ADC_AIN1
#define EXT3_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
/** @} */
/** \name Extension header #3 PWM for Control definitions
* @{
*/
#define EXT3_PWM4CTRL_MODULE TCC2
#define EXT3_PWM4CTRL_0_CHANNEL 0
#define EXT3_PWM4CTRL_0_OUTPUT 0
#define EXT3_PWM4CTRL_0_PIN PIN_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_0_MUX MUX_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_0_PINMUX PINMUX_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_1_CHANNEL 1
#define EXT3_PWM4CTRL_1_OUTPUT 1
#define EXT3_PWM4CTRL_1_PIN PIN_PA13E_TCC2_WO1
#define EXT3_PWM4CTRL_1_MUX MUX_PA13E_TCC2_WO1
#define EXT3_PWM4CTRL_1_PINMUX PINMUX_PA13E_TCC2_WO1
/** @} */
/** \name Extension header #3 IRQ/External interrupt definitions
* @{
*/
#define EXT3_IRQ_MODULE EIC
#define EXT3_IRQ_INPUT 8
#define EXT3_IRQ_PIN PIN_PA28A_EIC_EXTINT8
#define EXT3_IRQ_MUX MUX_PA28A_EIC_EXTINT8
#define EXT3_IRQ_PINMUX PINMUX_PA28A_EIC_EXTINT8
/** @} */
/** \name Extension header #3 I2C definitions
* @{
*/
#define EXT3_I2C_MODULE SERCOM2
#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #3 UART definitions
* @{
*/
#define EXT3_UART_MODULE SERCOM4
#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_MODULE SERCOM5
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 Dataflash
* @{
*/
#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA14
#define USB_VBUS_EIC_LINE 14
#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14
#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14
//#define USB_ID_PIN PIN_PA03
#define USB_ID_EIC_LINE 3
#define USB_ID_EIC_MUX MUX_PA03A_EIC_EXTINT3
#define USB_ID_EIC_PINMUX PINMUX_PA03A_EIC_EXTINT3
/** @} */
/** \name Embedded debugger GPIO interface definitions
* @{
*/
#define EDBG_GPIO0_PIN PIN_PA27
#define EDBG_GPIO1_PIN PIN_PA28
#define EDBG_GPIO2_PIN PIN_PA20
#define EDBG_GPIO3_PIN PIN_PA21
/** @} */
/** \name Embedded debugger USART interface definitions
* @{
*/
#define EDBG_UART_MODULE -1 /* Not available on this board */
#define EDBG_UART_RX_PIN -1 /* Not available on this board */
#define EDBG_UART_RX_MUX -1 /* Not available on this board */
#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
#define EDBG_UART_TX_PIN -1 /* Not available on this board */
#define EDBG_UART_TX_MUX -1 /* Not available on this board */
#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM2
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_MODULE SERCOM5
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM3
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX
#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX
/** @} */
/** @} */
/** \name 802.15.4 TRX Interface definitions
* @{
*/
#define AT86RFX_SPI EXT1_SPI_MODULE
#define AT86RFX_RST_PIN EXT1_PIN_7
#define AT86RFX_MISC_PIN EXT1_PIN_12
#define AT86RFX_IRQ_PIN EXT1_PIN_9
#define AT86RFX_SLP_PIN EXT1_PIN_10
#define AT86RFX_SPI_CS EXT1_PIN_15
#define AT86RFX_SPI_MOSI EXT1_PIN_16
#define AT86RFX_SPI_MISO EXT1_PIN_17
#define AT86RFX_SPI_SCK EXT1_PIN_18
#define AT86RFX_CSD EXT1_PIN_5
#define AT86RFX_CPS EXT1_PIN_8
#define AT86RFX_SPI_CONFIG(config) \
config.mux_setting = EXT1_SPI_SERCOM_MUX_SETTING; \
config.mode_specific.master.baudrate = AT86RFX_SPI_BAUDRATE; \
config.pinmux_pad0 = EXT1_SPI_SERCOM_PINMUX_PAD0; \
config.pinmux_pad1 = PINMUX_UNUSED; \
config.pinmux_pad2 = EXT1_SPI_SERCOM_PINMUX_PAD2; \
config.pinmux_pad3 = EXT1_SPI_SERCOM_PINMUX_PAD3;
#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT
#define AT86RFX_INTC_INIT() \
struct extint_chan_conf eint_chan_conf; \
extint_chan_get_config_defaults(&eint_chan_conf); \
eint_chan_conf.gpio_pin = AT86RFX_IRQ_PIN; \
eint_chan_conf.gpio_pin_mux = EXT1_IRQ_PINMUX; \
eint_chan_conf.gpio_pin_pull = EXTINT_PULL_NONE; \
eint_chan_conf.wake_if_sleeping = true; \
eint_chan_conf.filter_input_signal = false; \
eint_chan_conf.detection_criteria = EXTINT_DETECT_RISING; \
extint_chan_set_config(AT86RFX_IRQ_CHAN, &eint_chan_conf); \
extint_register_callback(AT86RFX_ISR, AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT);\
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT);
/** Enables the transceiver main interrupt. */
#define ENABLE_TRX_IRQ() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Disables the transceiver main interrupt. */
#define DISABLE_TRX_IRQ() \
extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Clears the transceiver main interrupt. */
#define CLEAR_TRX_IRQ() \
extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
/*
* This macro saves the trx interrupt status and disables the trx interrupt.
*/
#define ENTER_TRX_REGION() \
{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/*
* This macro restores the transceiver interrupt status
*/
#define LEAVE_TRX_REGION() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* SAMD21_XPLAINED_PRO_H_INCLUDED */

106
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/port/port.c Normal file
View file

@ -0,0 +1,106 @@
/**
* \file
*
* \brief SAM GPIO Port Driver
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <port.h>
/**
* \brief Writes a Port pin configuration to the hardware module.
*
* Writes out a given configuration of a Port pin configuration to the hardware
* module.
*
* \note If the pin direction is set as an output, the pull-up/pull-down input
* configuration setting is ignored.
*
* \param[in] gpio_pin Index of the GPIO pin to configure.
* \param[in] config Configuration settings for the pin.
*/
void port_pin_set_config(
const uint8_t gpio_pin,
const struct port_config *const config)
{
/* Sanity check arguments */
Assert(config);
struct system_pinmux_config pinmux_config;
system_pinmux_get_config_defaults(&pinmux_config);
pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
pinmux_config.powersave = config->powersave;
system_pinmux_pin_set_config(gpio_pin, &pinmux_config);
}
/**
* \brief Writes a Port group configuration group to the hardware module.
*
* Writes out a given configuration of a Port group configuration to the
* hardware module.
*
* \note If the pin direction is set as an output, the pull-up/pull-down input
* configuration setting is ignored.
*
* \param[out] port Base of the PORT module to write to.
* \param[in] mask Mask of the port pin(s) to configure.
* \param[in] config Configuration settings for the pin group.
*/
void port_group_set_config(
PortGroup *const port,
const uint32_t mask,
const struct port_config *const config)
{
/* Sanity check arguments */
Assert(port);
Assert(config);
struct system_pinmux_config pinmux_config;
system_pinmux_get_config_defaults(&pinmux_config);
pinmux_config.mux_position = SYSTEM_PINMUX_GPIO;
pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction;
pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull;
pinmux_config.powersave = config->powersave;
system_pinmux_group_set_config(port, mask, &pinmux_config);
}

564
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/port/port.h Normal file
View file

@ -0,0 +1,564 @@
/**
* \file
*
* \brief SAM GPIO Port Driver
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef PORT_H_INCLUDED
#define PORT_H_INCLUDED
/**
* \defgroup asfdoc_sam0_port_group SAM Port Driver (PORT)
*
* This driver for SAM devices provides an interface for the configuration
* and management of the device's General Purpose Input/Output (GPIO) pin
* functionality, for manual pin state reading and writing.
*
* The following peripherals are used by this module:
* - PORT (GPIO Management)
*
* The following devices can use this module:
* - SAM D20/D21
* - SAM R21
* - SAM D10/D11
*
* The outline of this documentation is as follows:
* - \ref asfdoc_sam0_port_prerequisites
* - \ref asfdoc_sam0_port_module_overview
* - \ref asfdoc_sam0_port_special_considerations
* - \ref asfdoc_sam0_port_extra_info
* - \ref asfdoc_sam0_port_examples
* - \ref asfdoc_sam0_port_api_overview
*
*
* \section asfdoc_sam0_port_prerequisites Prerequisites
*
* There are no prerequisites for this module.
*
*
* \section asfdoc_sam0_port_module_overview Module Overview
*
* The device GPIO (PORT) module provides an interface between the user
* application logic and external hardware peripherals, when general pin state
* manipulation is required. This driver provides an easy-to-use interface to
* the physical pin input samplers and output drivers, so that pins can be read
* from or written to for general purpose external hardware control.
*
* \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins
* SAM devices use two naming conventions for the I/O pins in the device; one
* physical, and one logical. Each physical pin on a device package is assigned
* both a physical port and pin identifier (e.g. "PORTA.0") as well as a
* monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
* former is used to map physical pins to their physical internal device module
* counterparts, for simplicity the design of this driver uses the logical GPIO
* numbers instead.
*
* \subsection asfdoc_sam0_port_module_overview_physical Physical Connection
*
* \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how
* this module is interconnected within the device.
*
* \anchor asfdoc_sam0_port_module_int_connections
* \dot
* digraph overview {
* node [label="Port Pad" shape=square] pad;
*
* subgraph driver {
* node [label="Peripheral Mux" shape=trapezium] pinmux;
* node [label="GPIO Module" shape=ellipse] gpio;
* node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
* }
*
* pinmux -> gpio;
* pad -> pinmux;
* pinmux -> peripherals;
* }
* \enddot
*
*
* \section asfdoc_sam0_port_special_considerations Special Considerations
*
* The SAM port pin input sampler can be disabled when the pin is configured
* in pure output mode to save power; reading the pin state of a pin configured
* in output-only mode will read the logical output state that was last set.
*
* \section asfdoc_sam0_port_extra_info Extra Information
*
* For extra information see \ref asfdoc_sam0_port_extra. This includes:
* - \ref asfdoc_sam0_port_extra_acronyms
* - \ref asfdoc_sam0_port_extra_dependencies
* - \ref asfdoc_sam0_port_extra_errata
* - \ref asfdoc_sam0_port_extra_history
*
*
* \section asfdoc_sam0_port_examples Examples
*
* For a list of examples related to this driver, see
* \ref asfdoc_sam0_port_exqsg.
*
*
* \section asfdoc_sam0_port_api_overview API Overview
* @{
*/
#include <compiler.h>
#include <pinmux.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \name PORT Alias Macros
* @{
*/
/** Convenience definition for GPIO module group A on the device (if
* available). */
#if (PORT_GROUPS > 0) || defined(__DOXYGEN__)
# define PORTA PORT->Group[0]
#endif
#if (PORT_GROUPS > 1) || defined(__DOXYGEN__)
/** Convenience definition for GPIO module group B on the device (if
* available). */
# define PORTB PORT->Group[1]
#endif
#if (PORT_GROUPS > 2) || defined(__DOXYGEN__)
/** Convenience definition for GPIO module group C on the device (if
* available). */
# define PORTC PORT->Group[2]
#endif
#if (PORT_GROUPS > 3) || defined(__DOXYGEN__)
/** Convenience definition for GPIO module group D on the device (if
* available). */
# define PORTD PORT->Group[3]
#endif
/** @} */
/**
* \brief Port pin direction configuration enum.
*
* Enum for the possible pin direction settings of the port pin configuration
* structure, to indicate the direction the pin should use.
*/
enum port_pin_dir {
/** The pin's input buffer should be enabled, so that the pin state can
* be read. */
PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT,
/** The pin's output buffer should be enabled, so that the pin state can
* be set. */
PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT,
/** The pin's output and input buffers should be enabled, so that the pin
* state can be set and read back. */
PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
};
/**
* \brief Port pin input pull configuration enum.
*
* Enum for the possible pin pull settings of the port pin configuration
* structure, to indicate the type of logic level pull the pin should use.
*/
enum port_pin_pull {
/** No logical pull should be applied to the pin. */
PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE,
/** Pin should be pulled up when idle. */
PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP,
/** Pin should be pulled down when idle. */
PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN,
};
/**
* \brief Port pin configuration structure.
*
* Configuration structure for a port pin instance. This structure should be
* initialized by the \ref port_get_config_defaults() function before being
* modified by the user application.
*/
struct port_config {
/** Port buffer input/output direction. */
enum port_pin_dir direction;
/** Port pull-up/pull-down for input pins. */
enum port_pin_pull input_pull;
/** Enable lowest possible powerstate on the pin
*
* \note All other configurations will be ignored, the pin will be disabled
*/
bool powersave;
};
/** \name State reading/writing (physical group orientated)
* @{
*/
/**
* \brief Retrieves the PORT module group instance from a given GPIO pin number.
*
* Retrieves the PORT module group instance associated with a given logical
* GPIO pin number.
*
* \param[in] gpio_pin Index of the GPIO pin to convert.
*
* \return Base address of the associated PORT module.
*/
static inline PortGroup* port_get_group_from_gpio_pin(
const uint8_t gpio_pin)
{
return system_pinmux_get_group_from_gpio_pin(gpio_pin);
}
/**
* \brief Retrieves the state of a group of port pins that are configured as inputs.
*
* Reads the current logic level of a port module's pins and returns the
* current levels as a bitmask.
*
* \param[in] port Base of the PORT module to read from.
* \param[in] mask Mask of the port pin(s) to read.
*
* \return Status of the port pin(s) input buffers.
*/
static inline uint32_t port_group_get_input_level(
const PortGroup *const port,
const uint32_t mask)
{
/* Sanity check arguments */
Assert(port);
return (port->IN.reg & mask);
}
/**
* \brief Retrieves the state of a group of port pins that are configured as outputs.
*
* Reads the current logical output level of a port module's pins and returns
* the current levels as a bitmask.
*
* \param[in] port Base of the PORT module to read from.
* \param[in] mask Mask of the port pin(s) to read.
*
* \return Status of the port pin(s) output buffers.
*/
static inline uint32_t port_group_get_output_level(
const PortGroup *const port,
const uint32_t mask)
{
/* Sanity check arguments */
Assert(port);
return (port->OUT.reg & mask);
}
/**
* \brief Sets the state of a group of port pins that are configured as outputs.
*
* Sets the current output level of a port module's pins to a given logic
* level.
*
* \param[out] port Base of the PORT module to write to.
* \param[in] mask Mask of the port pin(s) to change.
* \param[in] level_mask Mask of the port level(s) to set.
*/
static inline void port_group_set_output_level(
PortGroup *const port,
const uint32_t mask,
const uint32_t level_mask)
{
/* Sanity check arguments */
Assert(port);
port->OUTSET.reg = (mask & level_mask);
port->OUTCLR.reg = (mask & ~level_mask);
}
/**
* \brief Toggles the state of a group of port pins that are configured as an outputs.
*
* Toggles the current output levels of a port module's pins.
*
* \param[out] port Base of the PORT module to write to.
* \param[in] mask Mask of the port pin(s) to toggle.
*/
static inline void port_group_toggle_output_level(
PortGroup *const port,
const uint32_t mask)
{
/* Sanity check arguments */
Assert(port);
port->OUTTGL.reg = mask;
}
/** @} */
/** \name Configuration and initialization
* @{
*/
/**
* \brief Initializes a Port pin/group configuration structure to defaults.
*
* Initializes a given Port pin/group configuration structure to a set of
* known default values. This function should be called on all new
* instances of these configuration structures before being modified by the
* user application.
*
* The default configuration is as follows:
* \li Input mode with internal pullup enabled
*
* \param[out] config Configuration structure to initialize to default values.
*/
static inline void port_get_config_defaults(
struct port_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->direction = PORT_PIN_DIR_INPUT;
config->input_pull = PORT_PIN_PULL_UP;
config->powersave = false;
}
void port_pin_set_config(
const uint8_t gpio_pin,
const struct port_config *const config);
void port_group_set_config(
PortGroup *const port,
const uint32_t mask,
const struct port_config *const config);
/** @} */
/** \name State reading/writing (logical pin orientated)
* @{
*/
/**
* \brief Retrieves the state of a port pin that is configured as an input.
*
* Reads the current logic level of a port pin and returns the current
* level as a boolean value.
*
* \param[in] gpio_pin Index of the GPIO pin to read.
*
* \return Status of the port pin's input buffer.
*/
static inline bool port_pin_get_input_level(
const uint8_t gpio_pin)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
return (port_base->IN.reg & pin_mask);
}
/**
* \brief Retrieves the state of a port pin that is configured as an output.
*
* Reads the current logical output level of a port pin and returns the current
* level as a boolean value.
*
* \param[in] gpio_pin Index of the GPIO pin to read.
*
* \return Status of the port pin's output buffer.
*/
static inline bool port_pin_get_output_level(
const uint8_t gpio_pin)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
return (port_base->OUT.reg & pin_mask);
}
/**
* \brief Sets the state of a port pin that is configured as an output.
*
* Sets the current output level of a port pin to a given logic level.
*
* \param[in] gpio_pin Index of the GPIO pin to write to.
* \param[in] level Logical level to set the given pin to.
*/
static inline void port_pin_set_output_level(
const uint8_t gpio_pin,
const bool level)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
/* Set the pin to high or low atomically based on the requested level */
if (level) {
port_base->OUTSET.reg = pin_mask;
} else {
port_base->OUTCLR.reg = pin_mask;
}
}
/**
* \brief Toggles the state of a port pin that is configured as an output.
*
* Toggles the current output level of a port pin.
*
* \param[in] gpio_pin Index of the GPIO pin to toggle.
*/
static inline void port_pin_toggle_output_level(
const uint8_t gpio_pin)
{
PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
/* Toggle pin output level */
port_base->OUTTGL.reg = pin_mask;
}
/** @} */
#ifdef __cplusplus
}
#endif
/** @} */
/**
* \page asfdoc_sam0_port_extra Extra Information for PORT Driver
*
* \section asfdoc_sam0_port_extra_acronyms Acronyms
* Below is a table listing the acronyms used in this module, along with their
* intended meanings.
*
* <table>
* <tr>
* <th>Acronym</th>
* <th>Description</th>
* </tr>
* <tr>
* <td>GPIO</td>
* <td>General Purpose Input/Output</td>
* </tr>
* <tr>
* <td>MUX</td>
* <td>Multiplexer</td>
* </tr>
* </table>
*
*
* \section asfdoc_sam0_port_extra_dependencies Dependencies
* This driver has the following dependencies:
*
* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
*
*
* \section asfdoc_sam0_port_extra_errata Errata
* There are no errata related to this driver.
*
*
* \section asfdoc_sam0_port_extra_history Module History
* An overview of the module history is presented in the table below, with
* details on the enhancements and fixes made to the module since its first
* release. The current version of this corresponds to the newest version in
* the table.
*
* <table>
* <tr>
* <th>Changelog</th>
* </tr>
* <tr>
* <td>Added support for SAMD21</td>
* </tr>
* <tr>
* <td>Initial Release</td>
* </tr>
* </table>
*/
/**
* \page asfdoc_sam0_port_exqsg Examples for PORT Driver
*
* This is a list of the available Quick Start guides (QSGs) and example
* applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with
* step-by-step instructions to configure and use this driver in a selection of
* use cases. Note that QSGs can be compiled as a standalone application or be
* added to the user application.
*
* - \subpage asfdoc_sam0_port_basic_use_case
*
* \page asfdoc_sam0_port_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>E</td>
* <td>04/2014</td>
* <td>Added support for SAMD10/D11.</td>
* </tr>
* <tr>
* <td>D</td>
* <td>02/2014</td>
* <td>Added support for SAMR21.</td>
* </tr>
* <tr>
* <td>C</td>
* <td>01/2014</td>
* <td>Added support for SAMD21.</td>
* </tr>
* <tr>
* <td>B</td>
* <td>06/2013</td>
* <td>Corrected documentation typos.</td>
* </tr>
* <tr>
* <td>A</td>
* <td>06/2013</td>
* <td>Initial release</td>
* </tr>
* </table>
*/
#endif

105
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/port/quick_start/qs_port_basic.h Normal file
View file

@ -0,0 +1,105 @@
/**
* \file
*
* \brief SAM GPIO Port Driver Quick Start
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_port_basic_use_case Quick Start Guide for PORT - Basic
*
* In this use case, the PORT module is configured for:
* \li One pin in input mode, with pull-up enabled
* \li One pin in output mode
*
* This use case sets up the PORT to read the current state of a GPIO pin set as
* an input, and mirrors the opposite logical state on a pin configured as an
* output.
*
* \section asfdoc_sam0_port_basic_use_case_setup Setup
*
* \subsection asfdoc_sam0_port_basic_use_case_setup_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \subsection asfdoc_sam0_port_basic_use_case_setup_code Code
* Copy-paste the following setup code to your user application:
* \snippet qs_port_basic.c setup
*
* Add to user application initialization (typically the start of \c main()):
* \snippet qs_port_basic.c setup_init
*
* \subsection asfdoc_sam0_port_basic_use_case_setup_flow Workflow
* -# Create a PORT module pin configuration struct, which can be filled out to
* adjust the configuration of a single port pin.
* \snippet qs_port_basic.c setup_1
* -# Initialize the pin configuration struct with the module's default values.
* \snippet qs_port_basic.c setup_2
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Adjust the configuration struct to request an input pin.
* \snippet qs_port_basic.c setup_3
* -# Configure push button pin with the initialized pin configuration struct, to enable
* the input sampler on the pin.
* \snippet qs_port_basic.c setup_4
* -# Adjust the configuration struct to request an output pin.
* \snippet qs_port_basic.c setup_5
* \note The existing configuration struct may be re-used, as long as any
* values that have been altered from the default settings are taken
* into account by the user application.
*
* -# Configure LED pin with the initialized pin configuration struct, to enable
* the output driver on the pin.
* \snippet qs_port_basic.c setup_6
*
* \section asfdoc_sam0_port_basic_use_case_use_main Use Case
*
* \subsection asfdoc_sam0_port_basic_use_case_code Code
* Copy-paste the following code to your user application:
* \snippet qs_port_basic.c main
*
* \subsection asfdoc_sam0_port_basic_use_case_flow Workflow
* -# Read in the current input sampler state of push button pin, which has been
* configured as an input in the use-case setup code.
* \snippet qs_port_basic.c main_1
* -# Write the inverted pin level state to LED pin, which has been configured as
* an output in the use-case setup code.
* \snippet qs_port_basic.c main_2
*/

117
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/rtc/quick_start_count/qs_rtc_count_basic.h Normal file
View file

@ -0,0 +1,117 @@
/**
* \file
*
* \brief SAM RTC Count Quick Start
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_rtc_count_basic_use_case Quick Start Guide for RTC (COUNT) - Basic
* In this use case, the RTC is set up in count mode. The example configures the
* RTC in 16 bit mode, with continuous updates to the COUNT register, together
* with a set compare register value. Every 2000ms a LED on the board is
* toggled.
*
* \section asfdoc_sam0_rtc_count_basic_use_case_prereq Prerequisites
* The Generic Clock Generator for the RTC should be configured and enabled; if
* you are using the System Clock driver, this may be done via \c conf_clocks.h.
*
* \subsection asfdoc_sam0_rtc_count_basic_use_case_setup_clocks Clocks and Oscillators
* The \c conf_clock.h file needs to be changed with the following values to
* configure the clocks and oscillators for the module.
*
* The following oscillator settings are needed:
* \snippet conf_clocks.h oscillator_settings
* The following generic clock settings are needed:
* \snippet conf_clocks.h gclk_settings
*
* \section asfdoc_sam0_rtc_count_basic_use_case_setup Setup
*
* \subsection asfdoc_sam0_rtc_count_basic_use_case_init_code Initialization Code
* Create a rtc_module struct and add to the main application source file,
* outside of any functions:
* \snippet qs_rtc_count_basic.c rtc_module_instance
*
* Copy-paste the following setup code to your applications \c main():
* \snippet qs_rtc_count_basic.c initiate
*
* \subsection asfdoc_sam0_rtc_count_basic_use_case_main_code Add to Main
* Add the following to your \c main().
* \snippet qs_rtc_count_basic.c add_main
*
* \subsection rtc_count_basic_use_workflow Workflow
* -# Create a RTC configuration structure to hold the desired RTC driver
* settings.
* \snippet qs_rtc_count_basic.c set_conf
* -# Fill the configuration structure with the default driver configuration.
* \snippet qs_rtc_count_basic.c get_default
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Alter the RTC driver configuration to run in 16-bit counting mode, with
* continuous counter register updates.
* \snippet qs_rtc_count_basic.c set_config
* -# Initialize the RTC module.
* \snippet qs_rtc_count_basic.c init_rtc
* -# Enable the RTC module, so that it may begin counting.
* \snippet qs_rtc_count_basic.c enable
*
* \section asfdoc_sam0_rtc_count_basic_use_case_implement Implementation
* Code used to implement the initialized module.
*
* \subsection asfdoc_sam0_rtc_count_basic_use_case_imp_code Code
* Add after initialization in main().
* \snippet qs_rtc_count_basic.c implementation_code
*
* \subsection asfdoc_sam0_rtc_count_basic_use_case_imp_workflow Workflow
* -# Set RTC period to 2000ms (2 seconds) so that it will overflow and reset
* back to zero every two seconds.
* \snippet qs_rtc_count_basic.c period
* -# Enter an infinite loop to poll the RTC driver to check when a comparison
* match occurs.
* \snippet qs_rtc_count_basic.c main_loop
* -# Check if the RTC driver has found a match on compare channel 0 against the
* current RTC count value.
* \snippet qs_rtc_count_basic.c check_match
* -# Once a compare match occurs, perform the desired user action.
* \snippet qs_rtc_count_basic.c compare_match_action
* -# Clear the compare match, so that future matches may occur.
* \snippet qs_rtc_count_basic.c clear_compare_match
*/

128
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/rtc/quick_start_count_callback/qs_rtc_count_callback.h Normal file
View file

@ -0,0 +1,128 @@
/**
* \file
*
* \brief SAM RTC Count Quick Start
*
* Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_rtc_count_callback_use_case Quick Start Guide for RTC (COUNT) - Callback
*
* In this use case, the RTC is set up in count mode. The quick start
* configures the RTC in 16 bit mode and to continuously update COUNT register.
* The rest of the configuration is according to the
* \ref rtc_count_get_config_defaults "default".
* A callback is implemented for when the RTC overflows.
*
* \section asfdoc_sam0_rtc_count_callback_use_case_prereq Prerequisites
* The Generic Clock Generator for the RTC should be configured and enabled; if
* you are using the System Clock driver, this may be done via \c conf_clocks.h.
*
* \subsection asfdoc_sam0_rtc_count_callback_use_case_setup_clocks Clocks and Oscillators
* The \c conf_clock.h file needs to be changed with the following values to
* configure the clocks and oscillators for the module.
*
* The following oscillator settings are needed:
* \snippet conf_clocks.h oscillator_settings
* The following generic clock settings are needed:
* \snippet conf_clocks.h gclk_settings
*
* \section asfdoc_sam0_rtc_count_callback_use_case_setup Setup
*
* \subsection asfdoc_sam0_rtc_count_callback_use_case_setup_code Code
* Create a rtc_module struct and add to the main application source file,
* outside of any functions:
* \snippet qs_rtc_count_callback.c rtc_module_instance
* The following must be added to the user application:
*
* Function for setting up the module:
* \snippet qs_rtc_count_callback.c initialize_rtc
*
* Callback function:
* \snippet qs_rtc_count_callback.c callback
*
* Function for setting up the callback functionality of the driver:
* \snippet qs_rtc_count_callback.c setup_callback
*
* Add to user application main():
* \snippet qs_rtc_count_callback.c run_initialize_rtc
*
* \subsection asfdoc_sam0_rtc_count_callback_use_case_setup_workflow Workflow
* -# Initialize system.
* \snippet qs_rtc_count_callback.c system_init
* -# Configure and enable module.
* \snippet qs_rtc_count_callback.c run_conf
* -# Create a RTC configuration structure to hold the desired RTC driver
* settings and fill it with the default driver configuration values.
* \snippet qs_rtc_count_callback.c init_conf
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Alter the RTC driver configuration to run in 16-bit counting mode, with
* continuous counter register updates and a compare value of 1000ms.
* \snippet qs_rtc_count_callback.c set_config
* -# Initialize the RTC module.
* \snippet qs_rtc_count_callback.c init_rtc
* -# Enable the RTC module, so that it may begin counting.
* \snippet qs_rtc_count_callback.c enable
* -# Configure callback functionality.
* \snippet qs_rtc_count_callback.c run_callback
* -# Register overflow callback.
* \snippet qs_rtc_count_callback.c reg_callback
* -# Enable overflow callback.
* \snippet qs_rtc_count_callback.c en_callback
* -# Set period.
* \snippet qs_rtc_count_callback.c period
*
* \section asfdoc_sam0_rtc_count_callback_use_case_implementation Implementation
*
* \subsection asfdoc_sam0_rtc_count_callback_use_case_implementation_code Code
* Add to user application main:
* \snippet qs_rtc_count_callback.c while
* \subsection asfdoc_sam0_rtc_count_callback_use_case_implementation_workflow Workflow
* -# Infinite while loop while waiting for callbacks.
* \snippet qs_rtc_count_callback.c while
*
* \section asfdoc_sam0_rtc_count_callback_use_case_callback Callback
* Each time the RTC counter overflows, the callback function will be called.
* \subsection asfdoc_sam0_rtc_count_callback_use_case_callback_workflow Workflow
* -# Perform the desired user action for each RTC overflow:
* \snippet qs_rtc_count_callback.c overflow_act
*/

684
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/rtc/rtc_count.c Normal file
View file

@ -0,0 +1,684 @@
/**
* \file
*
* \brief SAM RTC Driver (Count Mode)
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "rtc_count.h"
#include <gclk.h>
#if !defined(__DOXYGEN__)
struct rtc_module *_rtc_instance[RTC_INST_NUM];
#endif
/**
* \brief Resets the RTC module.
* Resets the RTC to hardware defaults.
*
* \param[in,out] module Pointer to the software instance struct
*/
void rtc_count_reset(struct rtc_module *const module)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Disable module before reset. */
rtc_count_disable(module);
#if RTC_COUNT_ASYNC == true
module->registered_callback = 0;
module->enabled_callback = 0;
#endif
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
/* Initiate software reset. */
rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST;
}
/**
* \internal Applies the given configuration.
*
* Sets the configurations given from the configuration structure to the
* hardware module
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] config Pointer to the configuration structure.
*
* \return Status of the configuration procedure.
* \retval STATUS_OK RTC configurations was set successfully.
* \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given.
*/
static enum status_code _rtc_count_set_config(
struct rtc_module *const module,
const struct rtc_count_config *const config)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
rtc_module->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE(0) | config->prescaler;
/* Set mode and clear on match if applicable. */
switch (config->mode) {
case RTC_COUNT_MODE_32BIT:
/* Set 32bit mode and clear on match if applicable. */
rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(0);
/* Check if clear on compare match should be set. */
if (config->clear_on_match) {
/* Set clear on match. */
rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR;
}
/* Set compare values. */
for (uint8_t i = 0; i < RTC_NUM_OF_COMP32; i++) {
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
rtc_count_set_compare(module, config->compare_values[i],
(enum rtc_count_compare)i);
}
break;
case RTC_COUNT_MODE_16BIT:
/* Set 16bit mode. */
rtc_module->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(1);
/* Check if match on clear is set, and return invalid
* argument if set. */
if (config->clear_on_match) {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
/* Set compare values. */
for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
rtc_count_set_compare(module, config->compare_values[i],
(enum rtc_count_compare)i);
}
break;
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
/* Check to set continuously clock read update mode. */
if (config->continuously_update) {
/* Set continuously mode. */
rtc_module->MODE0.READREQ.reg |= RTC_READREQ_RCONT;
}
/* Return status OK if everything was configured. */
return STATUS_OK;
}
/**
* \brief Initializes the RTC module with given configurations.
*
* Initializes the module, setting up all given configurations to provide
* the desired functionality of the RTC.
*
* \param[out] module Pointer to the software instance struct
* \param[in] hw Pointer to hardware instance
* \param[in] config Pointer to the configuration structure.
*
* \return Status of the initialization procedure.
* \retval STATUS_OK If the initialization was run stressfully.
* \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were given.
*/
enum status_code rtc_count_init(
struct rtc_module *const module,
Rtc *const hw,
const struct rtc_count_config *const config)
{
/* Sanity check arguments */
Assert(module);
Assert(hw);
Assert(config);
/* Initialize device instance */
module->hw = hw;
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_RTC);
/* Set up GCLK */
struct system_gclk_chan_config gclk_chan_conf;
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
gclk_chan_conf.source_generator = GCLK_GENERATOR_2;
system_gclk_chan_set_config(RTC_GCLK_ID, &gclk_chan_conf);
system_gclk_chan_enable(RTC_GCLK_ID);
/* Reset module to hardware defaults. */
rtc_count_reset(module);
/* Save conf_struct internally for continued use. */
module->mode = config->mode;
module->continuously_update = config->continuously_update;
# if (RTC_INST_NUM == 1)
_rtc_instance[0] = module;
# else
/* Register this instance for callbacks*/
_rtc_instance[_rtc_get_inst_index(hw)] = module;
# endif
/* Set config and return status. */
return _rtc_count_set_config(module, config);
}
/**
* \brief Set the current count value to desired value.
*
* Sets the value of the counter to the specified value.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] count_value The value to be set in count register.
*
* \return Status of setting the register.
* \retval STATUS_OK If everything was executed correctly.
* \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
*/
enum status_code rtc_count_set_count(
struct rtc_module *const module,
const uint32_t count_value)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
/* Set count according to mode */
switch(module->mode){
case RTC_COUNT_MODE_32BIT:
/* Write value to register. */
rtc_module->MODE0.COUNT.reg = count_value;
break;
case RTC_COUNT_MODE_16BIT:
/* Check if 16 bit value is provided. */
if(count_value > 0xffff){
return STATUS_ERR_INVALID_ARG;
}
/* Write value to register. */
rtc_module->MODE1.COUNT.reg = (uint32_t)count_value;
break;
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
return STATUS_OK;
}
/**
* \brief Get the current count value.
*
* \param[in,out] module Pointer to the software instance struct
*
* Returns the current count value.
*
* \return The current counter value as a 32 bit unsigned integer.
*/
uint32_t rtc_count_get_count(struct rtc_module *const module)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Initialize return value. */
uint32_t ret_val;
/* Change of read method based on value of continuously_update value in
* the configuration structure. */
if(!(module->continuously_update)) {
/* Request read on count register. */
rtc_module->MODE0.READREQ.reg = RTC_READREQ_RREQ;
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
}
/* Read value based on mode. */
switch (module->mode) {
case RTC_COUNT_MODE_32BIT:
/* Return count value in 32 bit mode. */
ret_val = rtc_module->MODE0.COUNT.reg;
break;
case RTC_COUNT_MODE_16BIT:
/* Return count value in 16 bit mode. */
ret_val = (uint32_t)rtc_module->MODE1.COUNT.reg;
break;
default:
Assert(false);
/* Counter not initialized. Assume counter value 0.*/
ret_val = 0;
break;
}
return ret_val;
}
/**
* \brief Set the compare value for the specified compare.
*
* Sets the value specified by the implementer to the requested compare.
*
* \note Compare 4 and 5 are only available in 16 bit mode.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] comp_value The value to be written to the compare.
* \param[in] comp_index Index of the compare to set.
*
* \return Status indicating if compare was successfully set.
* \retval STATUS_OK If compare was successfully set.
* \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
* \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode.
*/
enum status_code rtc_count_set_compare(
struct rtc_module *const module,
const uint32_t comp_value,
const enum rtc_count_compare comp_index)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
/* Set compare values based on operation mode. */
switch (module->mode) {
case RTC_COUNT_MODE_32BIT:
/* Check sanity of comp_index. */
if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) {
return STATUS_ERR_INVALID_ARG;
}
/* Set compare value for COMP. */
rtc_module->MODE0.COMP[comp_index].reg = comp_value;
break;
case RTC_COUNT_MODE_16BIT:
/* Check sanity of comp_index. */
if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
return STATUS_ERR_INVALID_ARG;
}
/* Check that 16 bit value is provided. */
if (comp_value > 0xffff) {
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
/* Set compare value for COMP. */
rtc_module->MODE1.COMP[comp_index].reg = comp_value & 0xffff;
break;
default:
Assert(false);
return STATUS_ERR_BAD_FORMAT;
}
/* Return status if everything is OK. */
return STATUS_OK;
}
/**
* \brief Get the current compare value of specified compare.
*
* Retrieves the current value of the specified compare.
*
* \note Compare 4 and 5 are only available in 16 bit mode.
*
* \param[in,out] module Pointer to the software instance struct
* \param[out] comp_value Pointer to 32 bit integer that will be populated with
* the current compare value.
* \param[in] comp_index Index of compare to check.
*
* \return Status of the reading procedure.
* \retval STATUS_OK If the value was read correctly.
* \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
* \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode.
*/
enum status_code rtc_count_get_compare(
struct rtc_module *const module,
uint32_t *const comp_value,
const enum rtc_count_compare comp_index)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
switch (module->mode) {
case RTC_COUNT_MODE_32BIT:
/* Check sanity of comp_index. */
if ((uint32_t)comp_index > RTC_NUM_OF_COMP32) {
return STATUS_ERR_INVALID_ARG;
}
/* Get compare value for COMP. */
*comp_value = rtc_module->MODE0.COMP[comp_index].reg;
break;
case RTC_COUNT_MODE_16BIT:
/* Check sanity of comp_index. */
if ((uint32_t)comp_index > RTC_NUM_OF_COMP16) {
return STATUS_ERR_INVALID_ARG;
}
/* Get compare value for COMP. */
*comp_value = (uint32_t)rtc_module->MODE1.COMP[comp_index].reg;
break;
default:
Assert(false);
return STATUS_ERR_BAD_FORMAT;
}
/* Return status showing everything is OK. */
return STATUS_OK;
}
/**
* \brief Retrieves the value of period.
*
* Retrieves the value of the period for the 16 bit mode counter.
*
* \note Only available in 16 bit mode.
*
* \param[in,out] module Pointer to the software instance struct
* \param[out] period_value Pointer to value for return argument.
*
* \return Status of getting the period value.
* \retval STATUS_OK If the period value was read correctly.
* \retval STATUS_ERR_UNSUPPORTED_DEV If incorrect mode was set.
*/
enum status_code rtc_count_get_period(
struct rtc_module *const module,
uint16_t *const period_value)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Check that correct mode is set. */
if (module->mode != RTC_COUNT_MODE_16BIT) {
return STATUS_ERR_UNSUPPORTED_DEV;
}
/* Returns the value. */
*period_value = rtc_module->MODE1.PER.reg;
return STATUS_OK;
}
/**
* \brief Set the given value to the period.
*
* Sets the given value to the period.
*
* \note Only available in 16 bit mode.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] period_value The value to set to the period.
*
* \return Status of setting the period value.
* \retval STATUS_OK If the period was set correctly.
* \retval STATUS_ERR_UNSUPPORTED_DEV If module is not operated in 16 bit mode.
*/
enum status_code rtc_count_set_period(
struct rtc_module *const module,
const uint16_t period_value)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Check that correct mode is set. */
if (module->mode != RTC_COUNT_MODE_16BIT) {
return STATUS_ERR_UNSUPPORTED_DEV;
}
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
/* Write value to register. */
rtc_module->MODE1.PER.reg = period_value;
return STATUS_OK;
}
/**
* \brief Check if RTC compare match has occurred.
*
* Checks the compare flag to see if a match has occurred. The compare flag is
* set when there is a compare match between counter and the compare.
*
* \note Compare 4 and 5 are only available in 16 bit mode.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] comp_index Index of compare to check current flag.
*/
bool rtc_count_is_compare_match(
struct rtc_module *const module,
const enum rtc_count_compare comp_index)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Check sanity. */
switch (module->mode) {
case RTC_COUNT_MODE_32BIT:
/* Check sanity for 32 bit mode. */
if (comp_index > RTC_NUM_OF_COMP32) {
return false;
}
break;
case RTC_COUNT_MODE_16BIT:
/* Check sanity for 16 bit mode. */
if (comp_index > RTC_NUM_OF_COMP16) {
return false;
}
break;
default:
Assert(false);
return false;
}
/* Set status of INTFLAG as return argument. */
return (rtc_module->MODE0.INTFLAG.reg & (1 << comp_index));
}
/**
* \brief Clears RTC compare match flag.
*
* Clears the compare flag. The compare flag is set when there is a compare
* match between the counter and the compare.
*
* \note Compare 4 and 5 are only available in 16 bit mode.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] comp_index Index of compare to check current flag.
*
* \return Status indicating if flag was successfully cleared.
* \retval STATUS_OK If flag was successfully cleared.
* \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
* \retval STATUS_ERR_BAD_FORMAT If the module was not initialized in a mode.
*/
enum status_code rtc_count_clear_compare_match(
struct rtc_module *const module,
const enum rtc_count_compare comp_index)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Check sanity. */
switch (module->mode){
case RTC_COUNT_MODE_32BIT:
/* Check sanity for 32 bit mode. */
if (comp_index > RTC_NUM_OF_COMP32) {
return STATUS_ERR_INVALID_ARG;
}
break;
case RTC_COUNT_MODE_16BIT:
/* Check sanity for 16 bit mode. */
if (comp_index > RTC_NUM_OF_COMP16) {
return STATUS_ERR_INVALID_ARG;
}
break;
default:
Assert(false);
return STATUS_ERR_BAD_FORMAT;
}
/* Clear INTFLAG. */
rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << comp_index);
return STATUS_OK;
}
/**
* \brief Calibrate for too-slow or too-fast oscillator.
*
* When used, the RTC will compensate for an inaccurate oscillator. The
* RTC module will add or subtract cycles from the RTC prescaler to adjust the
* frequency in approximately 1 PPM steps. The provided correction value should
* be between 0 and 127, allowing for a maximum 127 PPM correction.
*
* If no correction is needed, set value to zero.
*
* \note Can only be used when the RTC is operated in 1Hz.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] value Ranging from -127 to 127 used for the correction.
*
* \return Status of the calibration procedure.
* \retval STATUS_OK If calibration was executed correctly.
* \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided.
*/
enum status_code rtc_count_frequency_correction(
struct rtc_module *const module,
const int8_t value)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Check if valid argument. */
if (abs(value) > 0x7F) {
/* Value bigger than allowed, return invalid argument. */
return STATUS_ERR_INVALID_ARG;
}
uint32_t new_correction_value;
/* Load the new correction value as a positive value, sign added later */
new_correction_value = abs(value);
/* Convert to positive value and adjust register sign bit. */
if (value < 0) {
new_correction_value |= RTC_FREQCORR_SIGN;
}
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
/* Set value. */
rtc_module->MODE0.FREQCORR.reg = new_correction_value;
return STATUS_OK;
}

935
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/rtc/rtc_count.h Normal file
View file

@ -0,0 +1,935 @@
/**
* \file
*
* \brief SAM RTC Driver (Count Mode)
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef RTC_COUNT_H_INCLUDED
#define RTC_COUNT_H_INCLUDED
/**
* \defgroup asfdoc_sam0_rtc_count_group SAM RTC Count Driver (RTC COUNT)
*
* This driver for SAM devices provides an interface for the configuration
* and management of the device's Real Time Clock functionality in Count
* operating mode, for the configuration and retrieval of the current RTC
* counter value. The following driver API modes are covered by this
* manual:
*
* - Polled APIs
* \if RTC_COUNT_CALLBACK_MODE
* - Callback APIs
* \endif
*
* The following peripherals are used by this module:
* - RTC (Real Time Clock)
*
* The following devices can use this module:
* - SAM D20/D21
* - SAM R21
* - SAM D10/D11
*
* The outline of this documentation is as follows:
* - \ref asfdoc_sam0_rtc_count_prerequisites
* - \ref asfdoc_sam0_rtc_count_module_overview
* - \ref asfdoc_sam0_rtc_count_special_considerations
* - \ref asfdoc_sam0_rtc_count_extra_info
* - \ref asfdoc_sam0_rtc_count_examples
* - \ref asfdoc_sam0_rtc_count_api_overview
*
*
* \section asfdoc_sam0_rtc_count_prerequisites Prerequisites
*
* There are no prerequisites for this module.
*
*
* \section asfdoc_sam0_rtc_count_module_overview Module Overview
*
* The RTC module in the SAM devices is a 32-bit counter, with a 10-bit
* programmable prescaler. Typically, the RTC clock is run continuously,
* including in the device's low-power sleep modes, to track the current time
* and date information. The RTC can be used as a source to wake up the system
* at a scheduled time or periodically using the alarm functions.
*
* In this driver, the RTC is operated in Count mode. This allows for an
* easy integration of an asynchronous counter into a user application, which is
* capable of operating while the device is in sleep mode.
*
* Whilst operating in Count mode, the RTC features:
* - 16-bit counter mode
* - Selectable counter period
* - Up to 6 configurable compare values
* - 32-bit counter mode
* - Clear counter value on match
* - Up to 4 configurable compare values
*
*
* \section asfdoc_sam0_rtc_count_module_overview_compares Compare and Overflow
* The RTC can be used with up to 4/6 compare values (depending on selected
* operation mode). These compare values will trigger on match with the current
* RTC counter value, and can be set up to trigger an interrupt, event, or both.
* The RTC can also be configured to clear the counter value on compare match
* in 32-bit mode, resetting the count value back to zero.
*
* If the RTC is operated without the Clear on Match option enabled, or in
* 16-bit mode, the RTC counter value will instead be cleared on overflow once
* the maximum count value has been reached:
*
* \f[ COUNT_{MAX} = 2^{32}-1 \f] for 32-bit counter mode, and
* \f[ COUNT_{MAX} = 2^{16}-1 \f] for 16-bit counter mode.
*
* When running in 16-bit mode, the overflow value is selectable with a period
* value. The counter overflow will then occur when the counter value reaches
* the specified period value.
*
* \subsection asfdoc_sam0_rtc_count_module_overview_periodic Periodic Events
* The RTC can generate events at periodic intervals, allowing for direct
* peripheral actions without CPU intervention. The periodic events can be
* generated on the upper 8 bits of the RTC prescaler, and will be generated on
* the rising edge transition of the specified bit. The resulting periodic
* frequency can be calculated by the following formula:
*
* \f[ f_{PERIODIC}=\frac{f_{ASY}}{2^{n+3}} \f]
*
* Where \f$f_{ASY}\f$ refers to the \e asynchronous clock set up in the RTC
* module configuration. The \b n parameter is the event source generator index
* of the RTC module. If the asynchronous clock is operated at the recommended
* frequency of 1 KHz, the formula results in the values shown in
* \ref asfdoc_sam0_rtc_count_module_rtc_hz "the table below".
*
* \anchor asfdoc_sam0_rtc_count_module_rtc_hz
* <table>
* <caption>RTC event frequencies for each prescaler bit using a 1KHz clock</caption>
* <tr>
* <th>n</th> <th>Periodic event</th>
* </tr>
* <tr>
* <td>7</td> <td>1 Hz</td>
* </tr>
* <tr>
* <td>6</td> <td>2 Hz</td>
* </tr>
* <tr>
* <td>5</td> <td>4 Hz</td>
* </tr>
* <tr>
* <td>4</td> <td>8 Hz</td>
* </tr>
* <tr>
* <td>3</td> <td>16 Hz</td>
* </tr>
* <tr>
* <td>2</td> <td>32 Hz</td>
* </tr>
* <tr>
* <td>1</td> <td>64 Hz</td>
* </tr>
* <tr>
* <td>0</td> <td>128 Hz</td>
* </tr>
* </table>
*
* \note The connection of events between modules requires the use of the
* \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
* to route output event of one module to the the input event of another.
* For more information on event routing, refer to the event driver
* documentation.
*
* \subsection asfdoc_sam0_rtc_count_module_overview_correction Digital Frequency Correction
* The RTC module contains Digital Frequency Correction logic to compensate for
* inaccurate source clock frequencies which would otherwise result in skewed
* time measurements. The correction scheme requires that at least two bits
* in the RTC module prescaler are reserved by the correction logic. As a
* result of this implementation, frequency correction is only available when
* the RTC is running from a 1 Hz reference clock.
*
* The correction procedure is implemented by subtracting or adding a single
* cycle from the RTC prescaler every 1024 RTC GCLK cycles. The adjustment is
* applied the specified number of time (max 127) over 976 of these periods. The
* corresponding correction in PPM will be given by:
*
* \f[ Correction(PPM) = \frac{VALUE}{999424}10^6 \f]
*
* The RTC clock will tick faster if provided with a positive correction value,
* and slower when given a negative correction value.
*
*
* \section asfdoc_sam0_rtc_count_special_considerations Special Considerations
*
* \subsection asfdoc_sam0_rtc_count_special_considerations_clock Clock Setup
* The RTC is typically clocked by a specialized GCLK generator that has a
* smaller prescaler than the others. By default the RTC clock is on, selected
* to use the internal 32 KHz RC-oscillator with a prescaler of 32, giving a
* resulting clock frequency of 1 KHz to the RTC. When the internal RTC
* prescaler is set to 1024, this yields an end-frequency of 1 Hz.
*
* The implementer also has the option to set other end-frequencies.
* \ref asfdoc_sam0_rtc_count_rtc_out_freq "The table below" lists the
* available RTC frequencies for each possible GCLK and RTC input prescaler
* options.
*
* \anchor asfdoc_sam0_rtc_count_rtc_out_freq
* <table>
* <caption>RTC output frequencies from allowable input clocks</caption>
* <tr>
* <th>End-frequency</th>
* <th>GCLK prescaler</th>
* <th>RTC Prescaler</th>
* </tr>
* <tr>
* <td>32 KHz</td>
* <td>1</td>
* <td>1</td>
* </tr>
* <tr>
* <td>1 KHz</td>
* <td>32</td>
* <td>1</td>
* </tr>
* <tr>
* <td>1 Hz</td>
* <td>32</td>
* <td>1024</td>
* </tr>
* </table>
*
* The overall RTC module clocking scheme is shown in
* \ref asfdoc_sam0_rtc_count_rtc_clock_fig "the figure below".
*
* \anchor asfdoc_sam0_rtc_count_rtc_clock_fig
* \dot
* digraph clocking_scheme {
* rankdir=LR;
* GCLK [shape="record", label="<f0> GCLK | <f1> RTC_GCLK",
* bgcolor="lightgray", style="filled"];
* RTCPRE [shape="record" label="<f0> RTC | <f1> RTC PRESCALER"];
* RTC [shape="record", label="<f0> RTC | <f1> RTC CLOCK"];
*
* GCLK:f1 -> RTCPRE:f1;
* RTCPRE:f1 -> RTC:f1;
* }
* \enddot
*
*
* \section asfdoc_sam0_rtc_count_extra_info Extra Information
*
* For extra information see \ref asfdoc_sam0_rtc_count_extra. This includes:
* - \ref asfdoc_sam0_rtc_count_extra_acronyms
* - \ref asfdoc_sam0_rtc_count_extra_dependencies
* - \ref asfdoc_sam0_rtc_count_extra_errata
* - \ref asfdoc_sam0_rtc_count_extra_history
*
*
* \section asfdoc_sam0_rtc_count_examples Examples
*
* For a list of examples related to this driver, see
* \ref asfdoc_sam0_rtc_count_exqsg.
*
*
* \section asfdoc_sam0_rtc_count_api_overview API Overview
* @{
*/
#include <compiler.h>
#include <conf_clocks.h>
#if RTC_COUNT_ASYNC == true
# include <system_interrupt.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Available operation modes for the RTC.
*
* RTC Count operating modes, to select the counting width and associated module
* operation.
*/
enum rtc_count_mode {
/** RTC Count module operates in 16-bit mode. */
RTC_COUNT_MODE_16BIT = 0,
/** RTC Count module operates in 32-bit mode. */
RTC_COUNT_MODE_32BIT = 1,
};
/**
* \brief Available compare channels.
*
* \note Not all compare channels are available in all devices and modes.
*/
enum rtc_count_compare {
/** Compare channel 0. */
RTC_COUNT_COMPARE_0 = 0,
#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
/** Compare channel 1. */
RTC_COUNT_COMPARE_1 = 1,
#endif
#if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
/** Compare channel 2. */
RTC_COUNT_COMPARE_2 = 2,
#endif
#if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
/** Compare channel 3. */
RTC_COUNT_COMPARE_3 = 3,
#endif
#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
/** Compare channel 4. */
RTC_COUNT_COMPARE_4 = 4,
#endif
#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
/** Compare channel 5. */
RTC_COUNT_COMPARE_5 = 5,
#endif
};
#if RTC_COUNT_ASYNC == true
/**
* \brief Callback types
*
* The available callback types for the RTC count module.
*/
enum rtc_count_callback {
/** Callback for compare channel 0 */
RTC_COUNT_CALLBACK_COMPARE_0 = 0,
# if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
/** Callback for compare channel 1 */
RTC_COUNT_CALLBACK_COMPARE_1,
# endif
# if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
/** Callback for compare channel 2 */
RTC_COUNT_CALLBACK_COMPARE_2,
# endif
# if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
/** Callback for compare channel 3 */
RTC_COUNT_CALLBACK_COMPARE_3,
# endif
# if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
/** Callback for compare channel 4 */
RTC_COUNT_CALLBACK_COMPARE_4,
# endif
# if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
/** Callback for compare channel 5 */
RTC_COUNT_CALLBACK_COMPARE_5,
# endif
/** Callback for overflow */
RTC_COUNT_CALLBACK_OVERFLOW,
# if !defined(__DOXYGEN__)
/** Total number of callbacks */
_RTC_COUNT_CALLBACK_N
# endif
};
# if !defined(__DOXYGEN__)
typedef void (*rtc_count_callback_t)(void);
# endif
#endif
/**
* \brief RTC input clock prescaler settings
*
* The available input clock prescaler values for the RTC count module.
*/
enum rtc_count_prescaler {
/** RTC input clock frequency is prescaled by a factor of 1. */
RTC_COUNT_PRESCALER_DIV_1 = RTC_MODE0_CTRL_PRESCALER_DIV1,
/** RTC input clock frequency is prescaled by a factor of 2. */
RTC_COUNT_PRESCALER_DIV_2 = RTC_MODE0_CTRL_PRESCALER_DIV2,
/** RTC input clock frequency is prescaled by a factor of 4. */
RTC_COUNT_PRESCALER_DIV_4 = RTC_MODE0_CTRL_PRESCALER_DIV4,
/** RTC input clock frequency is prescaled by a factor of 8. */
RTC_COUNT_PRESCALER_DIV_8 = RTC_MODE0_CTRL_PRESCALER_DIV8,
/** RTC input clock frequency is prescaled by a factor of 16. */
RTC_COUNT_PRESCALER_DIV_16 = RTC_MODE0_CTRL_PRESCALER_DIV16,
/** RTC input clock frequency is prescaled by a factor of 32. */
RTC_COUNT_PRESCALER_DIV_32 = RTC_MODE0_CTRL_PRESCALER_DIV32,
/** RTC input clock frequency is prescaled by a factor of 64. */
RTC_COUNT_PRESCALER_DIV_64 = RTC_MODE0_CTRL_PRESCALER_DIV64,
/** RTC input clock frequency is prescaled by a factor of 128. */
RTC_COUNT_PRESCALER_DIV_128 = RTC_MODE0_CTRL_PRESCALER_DIV128,
/** RTC input clock frequency is prescaled by a factor of 256. */
RTC_COUNT_PRESCALER_DIV_256 = RTC_MODE0_CTRL_PRESCALER_DIV256,
/** RTC input clock frequency is prescaled by a factor of 512. */
RTC_COUNT_PRESCALER_DIV_512 = RTC_MODE0_CTRL_PRESCALER_DIV512,
/** RTC input clock frequency is prescaled by a factor of 1024. */
RTC_COUNT_PRESCALER_DIV_1024 = RTC_MODE0_CTRL_PRESCALER_DIV1024,
};
/**
* \brief RTC Count event enable/disable structure.
*
* Event flags for the \ref rtc_count_enable_events() and
* \ref rtc_count_disable_events().
*/
struct rtc_count_events {
/** Generate an output event on each overflow of the RTC count. */
bool generate_event_on_overflow;
/** Generate an output event on a compare channel match against the RTC
* count. */
bool generate_event_on_compare[RTC_NUM_OF_COMP16];
/** Generate an output event periodically at a binary division of the RTC
* counter frequency (see
* \ref asfdoc_sam0_rtc_count_module_overview_periodic).
*/
bool generate_event_on_periodic[8];
};
#if !defined(__DOXYGEN__)
/**
* \brief Device structure.
*/
struct rtc_module {
/** RTC hardware module */
Rtc *hw;
/** Operation mode of count. */
enum rtc_count_mode mode;
/** Set if counter value should be continuously updated. */
bool continuously_update;
# if RTC_COUNT_ASYNC == true
/** Pointers to callback functions */
volatile rtc_count_callback_t callbacks[_RTC_COUNT_CALLBACK_N];
/** Mask for registered callbacks */
volatile uint8_t registered_callback;
/** Mask for enabled callbacks */
volatile uint8_t enabled_callback;
# endif
};
#endif
/**
* \brief RTC Count configuration structure
*
* Configuration structure for the RTC instance. This structure should
* be initialized using the \ref rtc_count_get_config_defaults() before any
* user configurations are set.
*/
struct rtc_count_config {
/** Input clock prescaler for the RTC module. */
enum rtc_count_prescaler prescaler;
/** Select the operation mode of the RTC.*/
enum rtc_count_mode mode;
/** If true, clears the counter value on compare match. Only available
* whilst running in 32-bit mode. */
bool clear_on_match;
/** Continuously update the counter value so no synchronization is
* needed for reading. */
bool continuously_update;
/** Array of Compare values. Not all Compare values are available in 32-bit
* mode. */
uint32_t compare_values[RTC_NUM_OF_COMP16];
};
/**
* \name Configuration and initialization
* @{
*/
/**
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
*
* Checks to see if the underlying hardware peripheral module(s) are currently
* synchronizing across multiple clock domains to the hardware bus, This
* function can be used to delay further operations on a module until such time
* that it is ready, to prevent blocking delays for synchronization in the
* user application.
*
* \param[in] module RTC hardware module
*
* \return Synchronization status of the underlying hardware module(s).
*
* \retval true if the module has completed synchronization
* \retval false if the module synchronization is ongoing
*/
static inline bool rtc_count_is_syncing(struct rtc_module *const module)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
if (rtc_module->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) {
return true;
}
return false;
}
/**
* \brief Gets the RTC default configurations.
*
* Initializes the configuration structure to default values. This
* function should be called at the start of any RTC initialization.
*
* The default configuration is as follows:
* - Input clock divided by a factor of 1024.
* - RTC in 32 bit mode.
* - Clear on compare match off.
* - Continuously sync count register off.
* - No event source on.
* - All compare values equal 0.
*
* \param[out] config Configuration structure to be initialized to default
* values.
*/
static inline void rtc_count_get_config_defaults(
struct rtc_count_config *const config)
{
/* Sanity check argument */
Assert(config);
/* Set default into configuration structure */
config->prescaler = RTC_COUNT_PRESCALER_DIV_1024;
config->mode = RTC_COUNT_MODE_32BIT;
config->clear_on_match = false;
config->continuously_update = false;
for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
config->compare_values[i] = 0;
}
}
void rtc_count_reset(struct rtc_module *const module);
/**
* \brief Enables the RTC module.
*
* Enables the RTC module once it has been configured, ready for use. Most
* module configuration parameters cannot be altered while the module is enabled.
*
* \param[in,out] module RTC hardware module
*/
static inline void rtc_count_enable(struct rtc_module *const module)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
#if RTC_COUNT_ASYNC == true
system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_RTC);
#endif
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
/* Enable RTC module. */
rtc_module->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
}
/**
* \brief Disables the RTC module.
*
* Disables the RTC module.
*
* \param[in,out] module RTC hardware module
*/
static inline void rtc_count_disable(struct rtc_module *const module)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
#if RTC_COUNT_ASYNC == true
system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_RTC);
#endif
while (rtc_count_is_syncing(module)) {
/* Wait for synchronization */
}
/* Disable RTC module. */
rtc_module->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
}
#if (RTC_INST_NUM > 1) && !defined(__DOXYGEN__)
/**
* \internal Find the index of given RTC module instance.
*
* \param[in] RTC module instance pointer.
*
* \return Index of the given AC module instance.
*/
uint8_t _rtc_get_inst_index(
Rtc *const hw)
{
/* List of available RTC modules. */
static Rtc *const rtc_modules[RTC_INST_NUM] = RTC_INSTS;
/* Find index for RTC instance. */
for (uint32_t i = 0; i < RTC_INST_NUM; i++) {
if (hw == rtc_modules[i]) {
return i;
}
}
/* Invalid data given. */
Assert(false);
return 0;
}
#endif /* (RTC_INST_NUM > 1) && !defined(__DOXYGEN__) */
enum status_code rtc_count_init(
struct rtc_module *const module,
Rtc *const hw,
const struct rtc_count_config *const config);
enum status_code rtc_count_frequency_correction(
struct rtc_module *const module,
const int8_t value);
/** @} */
/** \name Count and compare value management
* @{
*/
enum status_code rtc_count_set_count(
struct rtc_module *const module,
const uint32_t count_value);
uint32_t rtc_count_get_count(struct rtc_module *const module);
enum status_code rtc_count_set_compare(
struct rtc_module *const module,
const uint32_t comp_value,
const enum rtc_count_compare comp_index);
enum status_code rtc_count_get_compare(
struct rtc_module *const module,
uint32_t *const comp_value,
const enum rtc_count_compare comp_index);
enum status_code rtc_count_set_period(
struct rtc_module *const module,
uint16_t period_value);
enum status_code rtc_count_get_period(
struct rtc_module *const module,
uint16_t *const period_value);
/** @} */
/** \name Status management
* @{
*/
/**
* \brief Check if an RTC overflow has occurred.
*
* Checks the overflow flag in the RTC. The flag is set when there
* is an overflow in the clock.
*
* \param[in,out] module RTC hardware module
*
* \return Overflow state of the RTC module.
*
* \retval true If the RTC count value has overflowed
* \retval false If the RTC count value has not overflowed
*/
static inline bool rtc_count_is_overflow(struct rtc_module *const module)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Return status of flag */
return (rtc_module->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF);
}
/**
* \brief Clears the RTC overflow flag.
*
* Clears the RTC module counter overflow flag, so that new overflow conditions
* can be detected.
*
* \param[in,out] module RTC hardware module
*/
static inline void rtc_count_clear_overflow(struct rtc_module *const module)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Clear OVF flag */
rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
}
bool rtc_count_is_compare_match(
struct rtc_module *const module,
const enum rtc_count_compare comp_index);
enum status_code rtc_count_clear_compare_match(
struct rtc_module *const module,
const enum rtc_count_compare comp_index);
/** @} */
/**
* \name Event management
* @{
*/
/**
* \brief Enables a RTC event output.
*
* Enables one or more output events from the RTC module. See
* \ref rtc_count_events for a list of events this module supports.
*
* \note Events cannot be altered while the module is enabled.
*
* \param[in,out] module RTC hardware module
* \param[in] events Struct containing flags of events to enable
*/
static inline void rtc_count_enable_events(
struct rtc_module *const module,
struct rtc_count_events *const events)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
uint32_t event_mask = 0;
/* Check if the user has requested an overflow event. */
if (events->generate_event_on_overflow) {
event_mask |= RTC_MODE0_EVCTRL_OVFEO;
}
/* Check if the user has requested any compare events. */
for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
if (events->generate_event_on_compare[i]) {
event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
}
}
/* Check if the user has requested any periodic events. */
for (uint8_t i = 0; i < 8; i++) {
if (events->generate_event_on_periodic[i]) {
event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
}
}
/* Enable given event(s). */
rtc_module->MODE0.EVCTRL.reg |= event_mask;
}
/**
* \brief Disables a RTC event output.
*
* Disabled one or more output events from the RTC module. See
* \ref rtc_count_events for a list of events this module supports.
*
* \note Events cannot be altered while the module is enabled.
*
* \param[in,out] module RTC hardware module
* \param[in] events Struct containing flags of events to disable
*/
static inline void rtc_count_disable_events(
struct rtc_module *const module,
struct rtc_count_events *const events)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
uint32_t event_mask = 0;
/* Check if the user has requested an overflow event. */
if (events->generate_event_on_overflow) {
event_mask |= RTC_MODE0_EVCTRL_OVFEO;
}
/* Check if the user has requested any compare events. */
for (uint8_t i = 0; i < RTC_NUM_OF_COMP16; i++) {
if (events->generate_event_on_compare[i]) {
event_mask |= RTC_MODE0_EVCTRL_CMPEO(1 << i);
}
}
/* Check if the user has requested any periodic events. */
for (uint8_t i = 0; i < 8; i++) {
if (events->generate_event_on_periodic[i]) {
event_mask |= RTC_MODE0_EVCTRL_PEREO(1 << i);
}
}
/* Disable given event(s). */
rtc_module->MODE0.EVCTRL.reg &= ~event_mask;
}
/** @} */
/** @} */
#ifdef __cplusplus
}
#endif
/**
* \page asfdoc_sam0_rtc_count_extra Extra Information for RTC COUNT Driver
*
* \section asfdoc_sam0_rtc_count_extra_acronyms Acronyms
* Below is a table listing the acronyms used in this module, along with their
* intended meanings.
*
* <table>
* <tr>
* <th>Acronym</td>
* <th>Description</td>
* </tr>
* <tr>
* <td>RTC</td>
* <td>Real Time Counter</td>
* </tr>
* <tr>
* <td>PPM</td>
* <td>Part Per Million</td>
* </tr>
* <tr>
* <td>RC</td>
* <td>Resistor/Capacitor</td>
* </tr>
* </table>
*
*
* \section asfdoc_sam0_rtc_count_extra_dependencies Dependencies
* This driver has the following dependencies:
*
* - None
*
*
* \section asfdoc_sam0_rtc_count_extra_errata Errata
* There are no errata related to this driver.
*
*
* \section asfdoc_sam0_rtc_count_extra_history Module History
* An overview of the module history is presented in the table below, with
* details on the enhancements and fixes made to the module since its first
* release. The current version of this corresponds to the newest version in
* the table.
*
* <table>
* <tr>
* <th>Changelog</th>
* </tr>
* <tr>
* <td>
* Added support for SAMD21 and added driver instance parameter to all
* API function calls, except get_config_defaults.
* </td>
* </tr>
* <tr>
* <td>Updated initialization function to also enable the digital interface
* clock to the module if it is disabled.</td>
* </tr>
* <tr>
* <td>Initial Release</td>
* </tr>
* </table>
*/
/**
* \page asfdoc_sam0_rtc_count_exqsg Examples for RTC (COUNT) Driver
*
* This is a list of the available Quick Start guides (QSGs) and example
* applications for \ref asfdoc_sam0_rtc_count_group. QSGs are simple
* examples with step-by-step instructions to configure and use this driver in a
* selection of use cases. Note that QSGs can be compiled as a standalone
* application or be added to the user application.
*
* - \subpage asfdoc_sam0_rtc_count_basic_use_case
* \if RTC_COUNT_CALLBACK_MODE
* - \subpage asfdoc_sam0_rtc_count_callback_use_case
* \endif
*
* \page asfdoc_sam0_rtc_count_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>E</td>
* <td>05/2014</td>
* <td>Added support for SAMD10/D11.</td>
* </tr>
* <tr>
* <td>D</td>
* <td>03/2014</td>
* <td>Added support for SAMR21.</td>
* </tr>
* <tr>
* <td>C</td>
* <td>01/2014</td>
* <td>Added support for SAMD21.</td>
* </tr>
* <tr>
* <td>B</td>
* <td>06/2013</td>
* <td>Added additional documentation on the event system. Corrected
* documentation typos.</td>
* </tr>
* <tr>
* <td>A</td>
* <td>06/2013</td>
* <td>Initial release</td>
* </tr>
* </table>
*/
#endif /* RTC_COUNT_H_INCLUDED */

317
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/rtc/rtc_count_interrupt.c Normal file
View file

@ -0,0 +1,317 @@
/**
* \file
*
* \brief SAM RTC Driver (Count Interrupt Mode)
*
* Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "rtc_count_interrupt.h"
extern struct rtc_module *_rtc_instance[RTC_INST_NUM];
/**
* \brief Registers callback for the specified callback type
*
* Associates the given callback function with the
* specified callback type.
* To enable the callback, the \ref rtc_count_enable_callback function
* must be used.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] callback Pointer to the function desired for the specified
* callback
* \param[in] callback_type Callback type to register
*
* \return Status of registering callback
* \retval STATUS_OK Registering was done successfully
* \retval STATUS_ERR_INVALID_ARG If trying to register a callback not available
*/
enum status_code rtc_count_register_callback(
struct rtc_module *const module,
rtc_count_callback_t callback,
enum rtc_count_callback callback_type)
{
enum status_code status = STATUS_OK;
/* Overflow callback */
if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
status = STATUS_OK;
} else {
/* Make sure callback type can be registered */
switch (module->mode) {
case RTC_COUNT_MODE_32BIT:
/* Check sanity for 32-bit mode. */
if (callback_type > RTC_NUM_OF_COMP32) {
status = STATUS_ERR_INVALID_ARG;
}
break;
case RTC_COUNT_MODE_16BIT:
/* Check sanity for 16-bit mode. */
if (callback_type > RTC_NUM_OF_COMP16) {
status = STATUS_ERR_INVALID_ARG;
}
break;
default:
status = STATUS_ERR_INVALID_ARG;
}
}
if (status == STATUS_OK) {
/* Register callback */
module->callbacks[callback_type] = callback;
/* Set corresponding bit to set callback as registered */
module->registered_callback |= (1 << callback_type);
}
return status;
}
/**
* \brief Unregisters callback for the specified callback type
*
* When called, the currently registered callback for the given callback type
* will be removed.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] callback_type Specifies the callback type to unregister
*
* \return Status of unregistering callback
* \retval STATUS_OK Unregistering was done successfully
* \retval STATUS_ERR_INVALID_ARG If trying to unregister a callback not available
*/
enum status_code rtc_count_unregister_callback(
struct rtc_module *const module,
enum rtc_count_callback callback_type)
{
enum status_code status = STATUS_OK;
/* Overflow callback */
if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
status = STATUS_OK;
} else {
/* Make sure callback type can be unregistered */
switch (module->mode) {
case RTC_COUNT_MODE_32BIT:
/* Check sanity for 32-bit mode. */
if (callback_type > RTC_NUM_OF_COMP32) {
status = STATUS_ERR_INVALID_ARG;
}
break;
case RTC_COUNT_MODE_16BIT:
/* Check sanity for 16-bit mode. */
if (callback_type > RTC_NUM_OF_COMP16) {
status = STATUS_ERR_INVALID_ARG;
}
break;
default:
status = STATUS_ERR_INVALID_ARG;
}
}
if (status == STATUS_OK) {
/* Unregister callback */
module->callbacks[callback_type] = NULL;
/* Clear corresponding bit to set callback as unregistered */
module->registered_callback &= ~(1 << callback_type);
}
return status;
}
/**
* \brief Enables callback
*
* Enables the callback specified by the callback_type.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] callback_type Callback type to enable
*/
void rtc_count_enable_callback(
struct rtc_module *const module,
enum rtc_count_callback callback_type)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
rtc_module->MODE0.INTENSET.reg = RTC_MODE0_INTFLAG_OVF;
} else {
rtc_module->MODE0.INTENSET.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
}
/* Mark callback as enabled. */
module->enabled_callback |= (1 << callback_type);
}
/**
* \brief Disables callback
*
* Disables the callback specified by the callback_type.
*
* \param[in,out] module Pointer to the software instance struct
* \param[in] callback_type Callback type to disable
*/
void rtc_count_disable_callback(
struct rtc_module *const module,
enum rtc_count_callback callback_type)
{
/* Sanity check arguments */
Assert(module);
Assert(module->hw);
Rtc *const rtc_module = module->hw;
/* Disable interrupt */
if (callback_type == RTC_COUNT_CALLBACK_OVERFLOW) {
rtc_module->MODE0.INTENCLR.reg = RTC_MODE0_INTFLAG_OVF;
} else {
rtc_module->MODE0.INTENCLR.reg = RTC_MODE1_INTFLAG_CMP(1 << callback_type);
}
/* Mark callback as disabled. */
module->enabled_callback &= ~(1 << callback_type);
}
/**
* \internal Interrupt handler for RTC
*
* \param [in] instance_index Default value 0
*/
static void _rtc_interrupt_handler(const uint32_t instance_index)
{
struct rtc_module *module = _rtc_instance[instance_index];
Rtc *const rtc_module = module->hw;
/* Combine callback registered and enabled masks */
uint8_t callback_mask = module->enabled_callback;
callback_mask &= module->registered_callback;
/* Read and mask interrupt flag register */
uint16_t interrupt_status = rtc_module->MODE0.INTFLAG.reg;
interrupt_status &= rtc_module->MODE0.INTENSET.reg;
if (interrupt_status & RTC_MODE0_INTFLAG_OVF) {
/* Overflow interrupt */
if (callback_mask & (1 << RTC_COUNT_CALLBACK_OVERFLOW)) {
module->callbacks[RTC_COUNT_CALLBACK_OVERFLOW]();
}
/* Clear interrupt flag */
rtc_module->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF;
} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 0)) {
/* Compare 0 interrupt */
if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_0)) {
module->callbacks[RTC_COUNT_CALLBACK_COMPARE_0]();
}
/* Clear interrupt flag */
rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 0);
} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 1)) {
#if (RTC_NUM_OF_COMP16 > 1) || defined(__DOXYGEN__)
/* Compare 1 interrupt */
if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_1)) {
module->callbacks[RTC_COUNT_CALLBACK_COMPARE_1]();
}
/* Clear interrupt flag */
rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 1);
#endif
} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 2)) {
#if (RTC_NUM_OF_COMP16 > 2) || defined(__DOXYGEN__)
/* Compare 2 interrupt */
if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_2)) {
module->callbacks[RTC_COUNT_CALLBACK_COMPARE_2]();
}
/* Clear interrupt flag */
rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 2);
#endif
} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 3)) {
#if (RTC_NUM_OF_COMP16 > 3) || defined(__DOXYGEN__)
/* Compare 3 interrupt */
if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_3)) {
module->callbacks[RTC_COUNT_CALLBACK_COMPARE_3]();
}
/* Clear interrupt flag */
rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 3);
#endif
} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 4)) {
#if (RTC_NUM_OF_COMP16 > 4) || defined(__DOXYGEN__)
/* Compare 4 interrupt */
if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_4)) {
module->callbacks[RTC_COUNT_CALLBACK_COMPARE_4]();
}
/* Clear interrupt flag */
rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 4);
#endif
} else if (interrupt_status & RTC_MODE1_INTFLAG_CMP(1 << 5)) {
#if (RTC_NUM_OF_COMP16 > 5) || defined(__DOXYGEN__)
/* Compare 5 interrupt */
if (callback_mask & (1 << RTC_COUNT_CALLBACK_COMPARE_5)) {
module->callbacks[RTC_COUNT_CALLBACK_COMPARE_5]();
}
/* Clear interrupt flag */
rtc_module->MODE0.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP(1 << 5);
#endif
}
}
/**
* \internal ISR handler for RTC
*/
#if (RTC_INST_NUM == 1)
void RTC_Handler(void)
{
_rtc_interrupt_handler(0);
}
#elif (RTC_INST_NUM > 1)
# define _RTC_INTERRUPT_HANDLER(n, unused) \
void RTC##n##_Handler(void) \
{ \
_rtc_interrupt_handler(n); \
}
MREPEAT(RTC_INST_NUM, _RTC_INTERRUPT_HANDLER, ~)
#endif /* (RTC_INST_NUM > 1) */

87
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/rtc/rtc_count_interrupt.h Normal file
View file

@ -0,0 +1,87 @@
/**
* \file
*
* \brief SAM RTC Driver (Count Interrupt Mode)
*
* Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef RTC_COUNT_INTERRUPT_H_INCLUDED
#define RTC_COUNT_INTERRUPT_H_INCLUDED
#include "rtc_count.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup asfdoc_sam0_rtc_count_group
* @{
*/
/**
* \name Callbacks
* @{
*/
enum status_code rtc_count_register_callback(
struct rtc_module *const module,
rtc_count_callback_t callback,
enum rtc_count_callback callback_type);
enum status_code rtc_count_unregister_callback(
struct rtc_module *const module,
enum rtc_count_callback callback_type);
void rtc_count_enable_callback(
struct rtc_module *const module,
enum rtc_count_callback callback_type);
void rtc_count_disable_callback(
struct rtc_module *const module,
enum rtc_count_callback callback_type);
/** @} */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* RTC_COUNT_INTERRUPT_H_INCLUDED */

1526
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/clock/clock.h Normal file
View file

File diff suppressed because it is too large Load diff

963
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock.c Normal file
View file

@ -0,0 +1,963 @@
/**
* \file
*
* \brief SAM D21/R21 Clock Driver
*
* Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <clock.h>
#include <conf_clocks.h>
#include <system.h>
#ifndef SYSCTRL_FUSES_OSC32K_ADDR
# define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR
# define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos
#endif
/**
* \internal
* \brief DFLL-specific data container
*/
struct _system_clock_dfll_config {
uint32_t control;
uint32_t val;
uint32_t mul;
};
/**
* \internal
* \brief DPLL-specific data container
*/
struct _system_clock_dpll_config {
uint32_t frequency;
};
/**
* \internal
* \brief XOSC-specific data container
*/
struct _system_clock_xosc_config {
uint32_t frequency;
};
/**
* \internal
* \brief System clock module data container
*/
struct _system_clock_module {
volatile struct _system_clock_dfll_config dfll;
#ifdef FEATURE_SYSTEM_CLOCK_DPLL
volatile struct _system_clock_dpll_config dpll;
#endif
volatile struct _system_clock_xosc_config xosc;
volatile struct _system_clock_xosc_config xosc32k;
};
/**
* \internal
* \brief Internal module instance to cache configuration values
*/
static struct _system_clock_module _system_clock_inst = {
.dfll = {
.control = 0,
.val = 0,
.mul = 0,
},
#ifdef FEATURE_SYSTEM_CLOCK_DPLL
.dpll = {
.frequency = 0,
},
#endif
.xosc = {
.frequency = 0,
},
.xosc32k = {
.frequency = 0,
},
};
/**
* \internal
* \brief Wait for sync to the DFLL control registers
*/
static inline void _system_dfll_wait_for_sync(void)
{
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) {
/* Wait for DFLL sync */
}
}
/**
* \internal
* \brief Wait for sync to the OSC32K control registers
*/
static inline void _system_osc32k_wait_for_sync(void)
{
while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) {
/* Wait for OSC32K sync */
}
}
static inline void _system_clock_source_dfll_set_config_errata_9905(void)
{
/* Disable ONDEMAND mode while writing configurations */
SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control & ~SYSCTRL_DFLLCTRL_ONDEMAND;
_system_dfll_wait_for_sync();
SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul;
SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val;
/* Write full configuration to DFLL control register */
SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
}
/**
* \brief Retrieve the frequency of a clock source
*
* Determines the current operating frequency of a given clock source.
*
* \param[in] clock_source Clock source to get the frequency of
*
* \returns Frequency of the given clock source, in Hz
*/
uint32_t system_clock_source_get_hz(
const enum system_clock_source clock_source)
{
switch (clock_source) {
case SYSTEM_CLOCK_SOURCE_XOSC:
return _system_clock_inst.xosc.frequency;
case SYSTEM_CLOCK_SOURCE_OSC8M:
return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC;
case SYSTEM_CLOCK_SOURCE_OSC32K:
return 32768UL;
case SYSTEM_CLOCK_SOURCE_ULP32K:
return 32768UL;
case SYSTEM_CLOCK_SOURCE_XOSC32K:
return _system_clock_inst.xosc32k.frequency;
case SYSTEM_CLOCK_SOURCE_DFLL:
/* Check if the DFLL has been configured */
if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE))
return 0;
/* Make sure that the DFLL module is ready */
_system_dfll_wait_for_sync();
/* Check if operating in closed loop mode */
if (_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) {
return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) *
(_system_clock_inst.dfll.mul & 0xffff);
}
return 48000000UL;
#ifdef FEATURE_SYSTEM_CLOCK_DPLL
case SYSTEM_CLOCK_SOURCE_DPLL:
if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) {
return 0;
}
return _system_clock_inst.dpll.frequency;
#endif
default:
return 0;
}
}
/**
* \brief Configure the internal OSC8M oscillator clock source
*
* Configures the 8MHz (nominal) internal RC oscillator with the given
* configuration settings.
*
* \param[in] config OSC8M configuration structure containing the new config
*/
void system_clock_source_osc8m_set_config(
struct system_clock_source_osc8m_config *const config)
{
SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M;
/* Use temporary struct to reduce register access */
temp.bit.PRESC = config->prescaler;
temp.bit.ONDEMAND = config->on_demand;
temp.bit.RUNSTDBY = config->run_in_standby;
SYSCTRL->OSC8M = temp;
}
/**
* \brief Configure the internal OSC32K oscillator clock source
*
* Configures the 32KHz (nominal) internal RC oscillator with the given
* configuration settings.
*
* \param[in] config OSC32K configuration structure containing the new config
*/
void system_clock_source_osc32k_set_config(
struct system_clock_source_osc32k_config *const config)
{
SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K;
/* Update settings via a temporary struct to reduce register access */
temp.bit.EN1K = config->enable_1khz_output;
temp.bit.EN32K = config->enable_32khz_output;
temp.bit.STARTUP = config->startup_time;
temp.bit.ONDEMAND = config->on_demand;
temp.bit.RUNSTDBY = config->run_in_standby;
temp.bit.WRTLOCK = config->write_once;
SYSCTRL->OSC32K = temp;
}
/**
* \brief Configure the external oscillator clock source
*
* Configures the external oscillator clock source with the given configuration
* settings.
*
* \param[in] config External oscillator configuration structure containing
* the new config
*/
void system_clock_source_xosc_set_config(
struct system_clock_source_xosc_config *const config)
{
SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC;
temp.bit.STARTUP = config->startup_time;
if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
temp.bit.XTALEN = 1;
} else {
temp.bit.XTALEN = 0;
}
temp.bit.AMPGC = config->auto_gain_control;
/* Set gain if automatic gain control is not selected */
if (!config->auto_gain_control) {
if (config->frequency <= 2000000) {
temp.bit.GAIN = 0;
} else if (config->frequency <= 4000000) {
temp.bit.GAIN = 1;
} else if (config->frequency <= 8000000) {
temp.bit.GAIN = 2;
} else if (config->frequency <= 16000000) {
temp.bit.GAIN = 3;
} else if (config->frequency <= 30000000) {
temp.bit.GAIN = 4;
}
}
temp.bit.ONDEMAND = config->on_demand;
temp.bit.RUNSTDBY = config->run_in_standby;
/* Store XOSC frequency for internal use */
_system_clock_inst.xosc.frequency = config->frequency;
SYSCTRL->XOSC = temp;
}
/**
* \brief Configure the XOSC32K external 32KHz oscillator clock source
*
* Configures the external 32KHz oscillator clock source with the given
* configuration settings.
*
* \param[in] config XOSC32K configuration structure containing the new config
*/
void system_clock_source_xosc32k_set_config(
struct system_clock_source_xosc32k_config *const config)
{
SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K;
temp.bit.STARTUP = config->startup_time;
if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) {
temp.bit.XTALEN = 1;
} else {
temp.bit.XTALEN = 0;
}
temp.bit.AAMPEN = config->auto_gain_control;
temp.bit.EN1K = config->enable_1khz_output;
temp.bit.EN32K = config->enable_32khz_output;
temp.bit.ONDEMAND = config->on_demand;
temp.bit.RUNSTDBY = config->run_in_standby;
temp.bit.WRTLOCK = config->write_once;
/* Cache the new frequency in case the user needs to check the current
* operating frequency later */
_system_clock_inst.xosc32k.frequency = config->frequency;
SYSCTRL->XOSC32K = temp;
}
/**
* \brief Configure the DFLL clock source
*
* Configures the Digital Frequency Locked Loop clock source with the given
* configuration settings.
*
* \note The DFLL will be running when this function returns, as the DFLL module
* needs to be enabled in order to perform the module configuration.
*
* \param[in] config DFLL configuration structure containing the new config
*/
void system_clock_source_dfll_set_config(
struct system_clock_source_dfll_config *const config)
{
_system_clock_inst.dfll.val =
SYSCTRL_DFLLVAL_COARSE(config->coarse_value) |
SYSCTRL_DFLLVAL_FINE(config->fine_value);
_system_clock_inst.dfll.control =
(uint32_t)config->wakeup_lock |
(uint32_t)config->stable_tracking |
(uint32_t)config->quick_lock |
(uint32_t)config->chill_cycle |
((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos);
if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
_system_clock_inst.dfll.mul =
SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) |
SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) |
SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
/* Enable the closed loop mode */
_system_clock_inst.dfll.control |= config->loop_mode;
}
if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
_system_clock_inst.dfll.mul =
SYSCTRL_DFLLMUL_MUL(config->multiply_factor);
/* Enable the USB recovery mode */
_system_clock_inst.dfll.control |= config->loop_mode |
SYSCTRL_DFLLCTRL_BPLCKC;
}
}
#ifdef FEATURE_SYSTEM_CLOCK_DPLL
/**
* \brief Configure the DPLL clock source
*
* Configures the Digital Phase-Locked Loop clock source with the given
* configuration settings.
*
* \note The DPLL will be running when this function returns, as the DPLL module
* needs to be enabled in order to perform the module configuration.
*
* \param[in] config DPLL configuration structure containing the new config
*/
void system_clock_source_dpll_set_config(
struct system_clock_source_dpll_config *const config)
{
uint32_t tmpldr;
uint8_t tmpldrfrac;
uint32_t refclk;
refclk = config->reference_frequency;
/* Only reference clock REF1 can be divided */
if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF1) {
refclk = refclk / config->reference_divider;
}
/* Calculate LDRFRAC and LDR */
tmpldr = (config->output_frequency << 4) / refclk;
tmpldrfrac = tmpldr & 0x0f;
tmpldr = (tmpldr >> 4) - 1;
SYSCTRL->DPLLCTRLA.reg =
((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) |
((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos);
SYSCTRL->DPLLRATIO.reg =
SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) |
SYSCTRL_DPLLRATIO_LDR(tmpldr);
SYSCTRL->DPLLCTRLB.reg =
SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) |
((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) |
SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) |
SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) |
((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) |
((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) |
SYSCTRL_DPLLCTRLB_FILTER(config->filter);
/*
* Fck = Fckrx * (LDR + 1 + LDRFRAC / 16)
*/
_system_clock_inst.dpll.frequency =
(config->reference_frequency *
(((tmpldr + 1) << 4) + tmpldrfrac)
) >> 4;
}
#endif
/**
* \brief Writes the calibration values for a given oscillator clock source
*
* Writes an oscillator calibration value to the given oscillator control
* registers. The acceptable ranges are:
*
* For OSC32K:
* - 7 bits (max value 128)
* For OSC8MHZ:
* - 8 bits (Max value 255)
* For OSCULP:
* - 5 bits (Max value 32)
*
* \note The frequency range parameter applies only when configuring the 8MHz
* oscillator and will be ignored for the other oscillators.
*
* \param[in] clock_source Clock source to calibrate
* \param[in] calibration_value Calibration value to write
* \param[in] freq_range Frequency range (8MHz oscillator only)
*
* \retval STATUS_OK The calibration value was written
* successfully.
* \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock
* source.
*/
enum status_code system_clock_source_write_calibration(
const enum system_clock_source clock_source,
const uint16_t calibration_value,
const uint8_t freq_range)
{
switch (clock_source) {
case SYSTEM_CLOCK_SOURCE_OSC8M:
if (calibration_value > 0xfff || freq_range > 4) {
return STATUS_ERR_INVALID_ARG;
}
SYSCTRL->OSC8M.bit.CALIB = calibration_value;
SYSCTRL->OSC8M.bit.FRANGE = freq_range;
break;
case SYSTEM_CLOCK_SOURCE_OSC32K:
if (calibration_value > 128) {
return STATUS_ERR_INVALID_ARG;
}
_system_osc32k_wait_for_sync();
SYSCTRL->OSC32K.bit.CALIB = calibration_value;
break;
case SYSTEM_CLOCK_SOURCE_ULP32K:
if (calibration_value > 32) {
return STATUS_ERR_INVALID_ARG;
}
SYSCTRL->OSCULP32K.bit.CALIB = calibration_value;
break;
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
break;
}
return STATUS_OK;
}
/**
* \brief Enables a clock source
*
* Enables a clock source which has been previously configured.
*
* \param[in] clock_source Clock source to enable
*
* \retval STATUS_OK Clock source was enabled successfully and
* is ready
* \retval STATUS_ERR_INVALID_ARG The clock source is not available on this
* device
*/
enum status_code system_clock_source_enable(
const enum system_clock_source clock_source)
{
switch (clock_source) {
case SYSTEM_CLOCK_SOURCE_OSC8M:
SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
return STATUS_OK;
case SYSTEM_CLOCK_SOURCE_OSC32K:
SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE;
break;
case SYSTEM_CLOCK_SOURCE_XOSC:
SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE;
break;
case SYSTEM_CLOCK_SOURCE_XOSC32K:
SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
break;
case SYSTEM_CLOCK_SOURCE_DFLL:
_system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE;
_system_clock_source_dfll_set_config_errata_9905();
break;
#ifdef FEATURE_SYSTEM_CLOCK_DPLL
case SYSTEM_CLOCK_SOURCE_DPLL:
SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE;
break;
#endif
case SYSTEM_CLOCK_SOURCE_ULP32K:
/* Always enabled */
return STATUS_OK;
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
return STATUS_OK;
}
/**
* \brief Disables a clock source
*
* Disables a clock source that was previously enabled.
*
* \param[in] clock_source Clock source to disable
*
* \retval STATUS_OK Clock source was disabled successfully
* \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was
* given
*/
enum status_code system_clock_source_disable(
const enum system_clock_source clock_source)
{
switch (clock_source) {
case SYSTEM_CLOCK_SOURCE_OSC8M:
SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE;
break;
case SYSTEM_CLOCK_SOURCE_OSC32K:
SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE;
break;
case SYSTEM_CLOCK_SOURCE_XOSC:
SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE;
break;
case SYSTEM_CLOCK_SOURCE_XOSC32K:
SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE;
break;
case SYSTEM_CLOCK_SOURCE_DFLL:
_system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE;
SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control;
break;
#ifdef FEATURE_SYSTEM_CLOCK_DPLL
case SYSTEM_CLOCK_SOURCE_DPLL:
SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE;
break;
#endif
case SYSTEM_CLOCK_SOURCE_ULP32K:
/* Not possible to disable */
default:
Assert(false);
return STATUS_ERR_INVALID_ARG;
}
return STATUS_OK;
}
/**
* \brief Checks if a clock source is ready
*
* Checks if a given clock source is ready to be used.
*
* \param[in] clock_source Clock source to check if ready
*
* \returns Ready state of the given clock source.
*
* \retval true Clock source is enabled and ready
* \retval false Clock source is disabled or not yet ready
*/
bool system_clock_source_is_ready(
const enum system_clock_source clock_source)
{
uint32_t mask = 0;
switch (clock_source) {
case SYSTEM_CLOCK_SOURCE_OSC8M:
mask = SYSCTRL_PCLKSR_OSC8MRDY;
break;
case SYSTEM_CLOCK_SOURCE_OSC32K:
mask = SYSCTRL_PCLKSR_OSC32KRDY;
break;
case SYSTEM_CLOCK_SOURCE_XOSC:
mask = SYSCTRL_PCLKSR_XOSCRDY;
break;
case SYSTEM_CLOCK_SOURCE_XOSC32K:
mask = SYSCTRL_PCLKSR_XOSC32KRDY;
break;
case SYSTEM_CLOCK_SOURCE_DFLL:
if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
mask = (SYSCTRL_PCLKSR_DFLLRDY |
SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC);
} else {
mask = SYSCTRL_PCLKSR_DFLLRDY;
}
break;
#ifdef FEATURE_SYSTEM_CLOCK_DPLL
case SYSTEM_CLOCK_SOURCE_DPLL:
return ((SYSCTRL->DPLLSTATUS.reg &
(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) ==
(SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK));
#endif
case SYSTEM_CLOCK_SOURCE_ULP32K:
/* Not possible to disable */
return true;
default:
return false;
}
return ((SYSCTRL->PCLKSR.reg & mask) == mask);
}
/* Include some checks for conf_clocks.h validation */
#include "clock_config_check.h"
#if !defined(__DOXYGEN__)
/** \internal
*
* Configures a Generic Clock Generator with the configuration from \c conf_clocks.h.
*/
# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \
if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \
struct system_gclk_gen_config gclk_conf; \
system_gclk_gen_get_config_defaults(&gclk_conf); \
gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \
gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \
gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \
gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \
system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \
system_gclk_gen_enable(GCLK_GENERATOR_##n); \
}
/** \internal
*
* Configures a Generic Clock Generator with the configuration from \c conf_clocks.h,
* provided that it is not the main Generic Clock Generator channel.
*/
# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \
if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); }
#endif
/**
* \brief Initialize clock system based on the configuration in conf_clocks.h
*
* This function will apply the settings in conf_clocks.h when run from the user
* application. All clock sources and GCLK generators are running when this function
* returns.
*/
void system_clock_init(void)
{
/* Various bits in the INTFLAG register can be set to one at startup.
This will ensure that these bits are cleared */
SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET |
SYSCTRL_INTFLAG_DFLLRDY;
system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES);
/* XOSC */
#if CONF_CLOCK_XOSC_ENABLE == true
struct system_clock_source_xosc_config xosc_conf;
system_clock_source_xosc_get_config_defaults(&xosc_conf);
xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL;
xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME;
xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL;
xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY;
xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND;
xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY;
system_clock_source_xosc_set_config(&xosc_conf);
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC);
#endif
/* XOSC32K */
#if CONF_CLOCK_XOSC32K_ENABLE == true
struct system_clock_source_xosc32k_config xosc32k_conf;
system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf);
xosc32k_conf.frequency = 32768UL;
xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL;
xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME;
xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL;
xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT;
xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT;
xosc32k_conf.on_demand = false;
xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY;
system_clock_source_xosc32k_set_config(&xosc32k_conf);
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
if (CONF_CLOCK_XOSC32K_ON_DEMAND) {
SYSCTRL->XOSC32K.bit.ONDEMAND = 1;
}
#endif
/* OSCK32K */
#if CONF_CLOCK_OSC32K_ENABLE == true
SYSCTRL->OSC32K.bit.CALIB =
(*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> SYSCTRL_FUSES_OSC32K_Pos);
struct system_clock_source_osc32k_config osc32k_conf;
system_clock_source_osc32k_get_config_defaults(&osc32k_conf);
osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME;
osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT;
osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT;
osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND;
osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY;
system_clock_source_osc32k_set_config(&osc32k_conf);
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K);
#endif
/* DFLL Config (Open and Closed Loop) */
#if CONF_CLOCK_DFLL_ENABLE == true
struct system_clock_source_dfll_config dfll_conf;
system_clock_source_dfll_get_config_defaults(&dfll_conf);
dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE;
dfll_conf.on_demand = false;
if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) {
dfll_conf.coarse_value = CONF_CLOCK_DFLL_COARSE_VALUE;
dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE;
}
# if CONF_CLOCK_DFLL_QUICK_LOCK == true
dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
# else
dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE;
# endif
# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true
dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK;
# else
dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
# endif
# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true
dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
# else
dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE;
# endif
# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true
dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE;
# else
dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
# endif
if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR;
}
dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE;
dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE;
if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) {
#define NVM_DFLL_COARSE_POS 58
#define NVM_DFLL_COARSE_SIZE 6
#define NVM_DFLL_FINE_POS 64
#define NVM_DFLL_FINE_SIZE 10
uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4)
+ (NVM_DFLL_COARSE_POS / 32))
>> (NVM_DFLL_COARSE_POS % 32))
& ((1 << NVM_DFLL_COARSE_SIZE) - 1);
if (coarse == 0x3f) {
coarse = 0x1f;
}
uint32_t fine =( *((uint32_t *)(NVMCTRL_OTP4)
+ (NVM_DFLL_FINE_POS / 32))
>> (NVM_DFLL_FINE_POS % 32))
& ((1 << NVM_DFLL_FINE_SIZE) - 1);
if (fine == 0x3ff) {
fine = 0x1ff;
}
dfll_conf.coarse_value = coarse;
dfll_conf.fine_value = fine;
dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE;
dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK;
dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP;
dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE;
dfll_conf.multiply_factor = 48000;
}
system_clock_source_dfll_set_config(&dfll_conf);
#endif
/* OSC8M */
struct system_clock_source_osc8m_config osc8m_conf;
system_clock_source_osc8m_get_config_defaults(&osc8m_conf);
osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER;
osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND;
osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY;
system_clock_source_osc8m_set_config(&osc8m_conf);
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M);
/* GCLK */
#if CONF_CLOCK_CONFIGURE_GCLK == true
system_gclk_init();
/* Configure all GCLK generators except for the main generator, which
* is configured later after all other clock systems are set up */
MREPEAT(8, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~);
# if CONF_CLOCK_DFLL_ENABLE == true
/* Enable DFLL reference clock if in closed loop mode */
if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) {
struct system_gclk_chan_config dfll_gclk_chan_conf;
system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf);
dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR;
system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf);
system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48);
}
# endif
#endif
/* DFLL Enable (Open and Closed Loop) */
#if CONF_CLOCK_DFLL_ENABLE == true
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
if (CONF_CLOCK_DFLL_ON_DEMAND) {
SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
}
#endif
/* DPLL */
#ifdef FEATURE_SYSTEM_CLOCK_DPLL
# if (CONF_CLOCK_DPLL_ENABLE == true)
/* Enable DPLL reference clock */
if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_REF0) {
/* XOSC32K should have been enabled for DPLL_REF0 */
Assert(CONF_CLOCK_XOSC32K_ENABLE);
}
struct system_clock_source_dpll_config dpll_config;
system_clock_source_dpll_get_config_defaults(&dpll_config);
dpll_config.on_demand = false;
dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY;
dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS;
dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST;
dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE;
dpll_config.filter = CONF_CLOCK_DPLL_FILTER;
dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK;
dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY;
dpll_config.reference_divider = CONF_CLOCK_DPLL_REFEREMCE_DIVIDER;
dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY;
system_clock_source_dpll_set_config(&dpll_config);
system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL);
while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL));
if (CONF_CLOCK_DPLL_ON_DEMAND) {
SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1;
}
# endif
#endif
/* CPU and BUS clocks */
system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER);
#ifdef FEATURE_SYSTEM_CLOCK_FAILURE_DETECT
system_main_clock_set_failure_detect(CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT);
#endif
system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER);
system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER);
/* GCLK 0 */
#if CONF_CLOCK_CONFIGURE_GCLK == true
/* Configure the main GCLK last as it might depend on other generators */
_CONF_CLOCK_GCLK_CONFIG(0, ~);
#endif
}

423
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/clock_config_check.h Normal file
View file

@ -0,0 +1,423 @@
/**
* \file
*
* \brief SAM D21/R21 Clock Driver
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef CLOCK_CONFIG_CHECK_H
# define CLOCK_CONFIG_CHECK_H
#if !defined(CONF_CLOCK_FLASH_WAIT_STATES)
# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_CPU_DIVIDER)
# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_APBA_DIVIDER)
# error CONF_CLOCK_APBA_DIVIDER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_APBB_DIVIDER)
# error CONF_CLOCK_APBB_DIVIDER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_OSC8M_PRESCALER)
# error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND)
# error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY)
# error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC_ENABLE)
# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL)
# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY)
# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME)
# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL)
# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC_ON_DEMAND)
# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY)
# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC32K_ENABLE)
# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL)
# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME)
# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL)
# error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT)
# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT)
# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND)
# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY)
# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_OSC32K_ENABLE)
# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME)
# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT)
# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT)
# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND)
# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY)
# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_ENABLE)
# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_LOOP_MODE)
# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_ON_DEMAND)
# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_COARSE_VALUE)
# error CONF_CLOCK_DFLL_COARSE_VALUE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_FINE_VALUE)
# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR)
# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR)
# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK)
# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK)
# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP)
# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE)
# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE)
# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE)
# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_ENABLE)
# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_ON_DEMAND)
# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY)
# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS)
# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST)
# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE)
# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_LOCK_TIME)
# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK)
# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_FILTER)
# error CONF_CLOCK_DPLL_FILTER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY)
# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_REFEREMCE_DIVIDER)
# error CONF_CLOCK_DPLL_REFEREMCE_DIVIDER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY)
# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_CONFIGURE_GCLK)
# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_0_ENABLE)
# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY)
# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE)
# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_0_PRESCALER)
# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE)
# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_1_ENABLE)
# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY)
# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE)
# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_1_PRESCALER)
# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE)
# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_2_ENABLE)
# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY)
# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE)
# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_2_PRESCALER)
# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE)
# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_3_ENABLE)
# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY)
# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE)
# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_3_PRESCALER)
# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE)
# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_4_ENABLE)
# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY)
# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE)
# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_4_PRESCALER)
# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE)
# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_5_ENABLE)
# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY)
# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE)
# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_5_PRESCALER)
# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE)
# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_6_ENABLE)
# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY)
# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE)
# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_6_PRESCALER)
# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE)
# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_7_ENABLE)
# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY)
# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE)
# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_7_PRESCALER)
# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clock.h
#endif
#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE)
# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clock.h
#endif
#endif /* CLOCK_CONFIG_CHECK_H */

496
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/clock/clock_samd21_r21/gclk.c Normal file
View file

@ -0,0 +1,496 @@
/**
* \file
*
* \brief SAM D21/R21 Generic Clock Driver
*
* Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <gclk.h>
#include <clock.h>
#include <system_interrupt.h>
/**
* \brief Initializes the GCLK driver.
*
* Initializes the Generic Clock module, disabling and resetting all active
* Generic Clock Generators and Channels to their power-on default values.
*/
void system_gclk_init(void)
{
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK);
/* Software reset the module to ensure it is re-initialized correctly */
GCLK->CTRL.reg = GCLK_CTRL_SWRST;
while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) {
/* Wait for reset to complete */
}
}
/**
* \brief Writes a Generic Clock Generator configuration to the hardware module.
*
* Writes out a given configuration of a Generic Clock Generator configuration
* to the hardware module.
*
* \note Changing the clock source on the fly (on a running
* generator) can take additional time if the clock source is configured
* to only run on-demand (ONDEMAND bit is set) and it is not currently
* running (no peripheral is requesting the clock source). In this case
* the GCLK will request the new clock while still keeping a request to
* the old clock source until the new clock source is ready.
*
* \note This function will not start a generator that is not already running;
* to start the generator, call \ref system_gclk_gen_enable()
* after configuring a generator.
*
* \param[in] generator Generic Clock Generator index to configure
* \param[in] config Configuration settings for the generator
*/
void system_gclk_gen_set_config(
const uint8_t generator,
struct system_gclk_gen_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Cache new register configurations to minimize sync requirements. */
uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos);
uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos);
/* Select the requested source clock for the generator */
new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos;
/* Configure the clock to be either high or low when disabled */
if (config->high_when_disabled) {
new_genctrl_config |= GCLK_GENCTRL_OOV;
}
/* Configure if the clock output to I/O pin should be enabled. */
if (config->output_enable) {
new_genctrl_config |= GCLK_GENCTRL_OE;
}
/* Set division factor */
if (config->division_factor > 1) {
/* Check if division is a power of two */
if (((config->division_factor & (config->division_factor - 1)) == 0)) {
/* Determine the index of the highest bit set to get the
* division factor that must be loaded into the division
* register */
uint32_t div2_count = 0;
uint32_t mask;
for (mask = (1UL << 1); mask < config->division_factor;
mask <<= 1) {
div2_count++;
}
/* Set binary divider power of 2 division factor */
new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos;
new_genctrl_config |= GCLK_GENCTRL_DIVSEL;
} else {
/* Set integer division factor */
new_gendiv_config |=
(config->division_factor) << GCLK_GENDIV_DIV_Pos;
/* Enable non-binary division with increased duty cycle accuracy */
new_genctrl_config |= GCLK_GENCTRL_IDC;
}
}
/* Enable or disable the clock in standby mode */
if (config->run_in_standby) {
new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY;
}
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
system_interrupt_enter_critical_section();
/* Select the correct generator */
*((uint8_t*)&GCLK->GENDIV.reg) = generator;
/* Write the new generator configuration */
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
GCLK->GENDIV.reg = new_gendiv_config;
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
system_interrupt_leave_critical_section();
}
/**
* \brief Enables a Generic Clock Generator that was previously configured.
*
* Starts the clock generation of a Generic Clock Generator that was previously
* configured via a call to \ref system_gclk_gen_set_config().
*
* \param[in] generator Generic Clock Generator index to enable
*/
void system_gclk_gen_enable(
const uint8_t generator)
{
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
system_interrupt_enter_critical_section();
/* Select the requested generator */
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
/* Enable generator */
GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN;
system_interrupt_leave_critical_section();
}
/**
* \brief Disables a Generic Clock Generator that was previously enabled.
*
* Stops the clock generation of a Generic Clock Generator that was previously
* started via a call to \ref system_gclk_gen_enable().
*
* \param[in] generator Generic Clock Generator index to disable
*/
void system_gclk_gen_disable(
const uint8_t generator)
{
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
system_interrupt_enter_critical_section();
/* Select the requested generator */
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
/* Disable generator */
GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN;
while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) {
/* Wait for clock to become disabled */
}
system_interrupt_leave_critical_section();
}
/**
* \brief Determins if the specified Generic Clock Generator is enabled
*
* \param[in] generator Generic Clock Generator index to check
*
* \return The enabled status.
* \retval true The Generic Clock Generator is enabled;
* \retval false The Generic Clock Generator is disabled.
*/
bool system_gclk_gen_is_enabled(
const uint8_t generator)
{
bool enabled;
system_interrupt_enter_critical_section();
/* Select the requested generator */
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
/* Obtain the enabled status */
enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN);
system_interrupt_leave_critical_section();
return enabled;
}
/**
* \brief Retrieves the clock frequency of a Generic Clock generator.
*
* Determines the clock frequency (in Hz) of a specified Generic Clock
* generator, used as a source to a Generic Clock Channel module.
*
* \param[in] generator Generic Clock Generator index
*
* \return The frequency of the generic clock generator, in Hz.
*/
uint32_t system_gclk_gen_get_hz(
const uint8_t generator)
{
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
system_interrupt_enter_critical_section();
/* Select the appropriate generator */
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
/* Get the frequency of the source connected to the GCLK generator */
uint32_t gen_input_hz = system_clock_source_get_hz(
(enum system_clock_source)GCLK->GENCTRL.bit.SRC);
*((uint8_t*)&GCLK->GENCTRL.reg) = generator;
uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL;
/* Select the appropriate generator division register */
*((uint8_t*)&GCLK->GENDIV.reg) = generator;
while (system_gclk_is_syncing()) {
/* Wait for synchronization */
};
uint32_t divider = GCLK->GENDIV.bit.DIV;
system_interrupt_leave_critical_section();
/* Check if the generator is using fractional or binary division */
if (!divsel && divider > 1) {
gen_input_hz /= divider;
} else if (divsel) {
gen_input_hz >>= (divider+1);
}
return gen_input_hz;
}
/**
* \brief Writes a Generic Clock configuration to the hardware module.
*
* Writes out a given configuration of a Generic Clock configuration to the
* hardware module. If the clock is currently running, it will be stopped.
*
* \note Once called the clock will not be running; to start the clock,
* call \ref system_gclk_chan_enable() after configuring a clock channel.
*
* \param[in] channel Generic Clock channel to configure
* \param[in] config Configuration settings for the clock
*
*/
void system_gclk_chan_set_config(
const uint8_t channel,
struct system_gclk_chan_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Cache the new config to reduce sync requirements */
uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos);
/* Select the desired generic clock generator */
new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos;
/* Disable generic clock channel */
system_gclk_chan_disable(channel);
/* Write the new configuration */
GCLK->CLKCTRL.reg = new_clkctrl_config;
}
/**
* \brief Enables a Generic Clock that was previously configured.
*
* Starts the clock generation of a Generic Clock that was previously
* configured via a call to \ref system_gclk_chan_set_config().
*
* \param[in] channel Generic Clock channel to enable
*/
void system_gclk_chan_enable(
const uint8_t channel)
{
system_interrupt_enter_critical_section();
/* Select the requested generator channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
/* Enable the generic clock */
GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
system_interrupt_leave_critical_section();
}
/**
* \brief Disables a Generic Clock that was previously enabled.
*
* Stops the clock generation of a Generic Clock that was previously started
* via a call to \ref system_gclk_chan_enable().
*
* \param[in] channel Generic Clock channel to disable
*/
void system_gclk_chan_disable(
const uint8_t channel)
{
system_interrupt_enter_critical_section();
/* Select the requested generator channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
/* Sanity check WRTLOCK */
Assert(!GCLK->CLKCTRL.bit.WRTLOCK);
/* Switch to known-working source so that the channel can be disabled */
uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN;
GCLK->CLKCTRL.bit.GEN = 0;
/* Disable the generic clock */
GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN;
while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) {
/* Wait for clock to become disabled */
}
/* Restore previous configured clock generator */
GCLK->CLKCTRL.bit.GEN = prev_gen_id;
system_interrupt_leave_critical_section();
}
/**
* \brief Determins if the specified Generic Clock channel is enabled
*
* \param[in] channel Generic Clock Channel index
*
* \return The enabled status.
* \retval true The Generic Clock channel is enabled;
* \retval false The Generic Clock channel is disabled.
*/
bool system_gclk_chan_is_enabled(
const uint8_t channel)
{
bool enabled;
system_interrupt_enter_critical_section();
/* Select the requested generic clock channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
enabled = GCLK->CLKCTRL.bit.CLKEN;
system_interrupt_leave_critical_section();
return enabled;
}
/**
* \brief Locks a Generic Clock channel from further configuration writes.
*
* Locks a generic clock channel from further configuration writes. It is only
* possible to unlock the channel configuration through a power on reset.
*
* \param[in] channel Generic Clock channel to enable
*/
void system_gclk_chan_lock(
const uint8_t channel)
{
system_interrupt_enter_critical_section();
/* Select the requested generator channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
/* Enable the generic clock */
GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN;
system_interrupt_leave_critical_section();
}
/**
* \brief Determins if the specified Generic Clock channel is locked
*
* \param[in] channel Generic Clock Channel index
*
* \return The lock status.
* \retval true The Generic Clock channel is locked;
* \retval false The Generic Clock channel is not locked.
*/
bool system_gclk_chan_is_locked(
const uint8_t channel)
{
bool locked;
system_interrupt_enter_critical_section();
/* Select the requested generic clock channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
locked = GCLK->CLKCTRL.bit.WRTLOCK;
system_interrupt_leave_critical_section();
return locked;
}
/**
* \brief Retrieves the clock frequency of a Generic Clock channel.
*
* Determines the clock frequency (in Hz) of a specified Generic Clock
* channel, used as a source to a device peripheral module.
*
* \param[in] channel Generic Clock Channel index
*
* \return The frequency of the generic clock channel, in Hz.
*/
uint32_t system_gclk_chan_get_hz(
const uint8_t channel)
{
uint8_t gen_id;
system_interrupt_enter_critical_section();
/* Select the requested generic clock channel */
*((uint8_t*)&GCLK->CLKCTRL.reg) = channel;
gen_id = GCLK->CLKCTRL.bit.GEN;
system_interrupt_leave_critical_section();
/* Return the clock speed of the associated GCLK generator */
return system_gclk_gen_get_hz(gen_id);
}

322
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/clock/gclk.h Normal file
View file

@ -0,0 +1,322 @@
/**
* \file
*
* \brief SAM Generic Clock Driver
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED
#define SYSTEM_CLOCK_GCLK_H_INCLUDED
/**
* \addtogroup asfdoc_sam0_system_clock_group
*
* @{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief List of available GCLK generators.
*
* List of Available GCLK generators. This enum is used in the peripheral
* device drivers to select the GCLK generator to be used for its operation.
*
* The number of GCLK generators available is device dependent.
*/
enum gclk_generator {
/** GCLK generator channel 0. */
GCLK_GENERATOR_0,
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0)
/** GCLK generator channel 1. */
GCLK_GENERATOR_1,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1)
/** GCLK generator channel 2. */
GCLK_GENERATOR_2,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2)
/** GCLK generator channel 3. */
GCLK_GENERATOR_3,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3)
/** GCLK generator channel 4. */
GCLK_GENERATOR_4,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4)
/** GCLK generator channel 5. */
GCLK_GENERATOR_5,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5)
/** GCLK generator channel 6. */
GCLK_GENERATOR_6,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6)
/** GCLK generator channel 7. */
GCLK_GENERATOR_7,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7)
/** GCLK generator channel 8. */
GCLK_GENERATOR_8,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8)
/** GCLK generator channel 9. */
GCLK_GENERATOR_9,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9)
/** GCLK generator channel 10. */
GCLK_GENERATOR_10,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10)
/** GCLK generator channel 11. */
GCLK_GENERATOR_11,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11)
/** GCLK generator channel 12. */
GCLK_GENERATOR_12,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12)
/** GCLK generator channel 13. */
GCLK_GENERATOR_13,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13)
/** GCLK generator channel 14. */
GCLK_GENERATOR_14,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14)
/** GCLK generator channel 15. */
GCLK_GENERATOR_15,
#endif
#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15)
/** GCLK generator channel 16. */
GCLK_GENERATOR_16,
#endif
};
/**
* \brief Generic Clock Generator configuration structure.
*
* Configuration structure for a Generic Clock Generator channel. This
* structure should be initialized by the
* \ref system_gclk_gen_get_config_defaults() function before being modified by
* the user application.
*/
struct system_gclk_gen_config {
/** Source clock input channel index, please see the \ref system_clock_source. */
uint8_t source_clock;
/** If \c true, the generator output level is high when disabled. */
bool high_when_disabled;
/** Integer division factor of the clock output compared to the input. */
uint32_t division_factor;
/** If \c true, the clock is kept enabled during device standby mode. */
bool run_in_standby;
/** If \c true, enables GCLK generator clock output to a GPIO pin. */
bool output_enable;
};
/**
* \brief Generic Clock configuration structure.
*
* Configuration structure for a Generic Clock channel. This structure
* should be initialized by the \ref system_gclk_chan_get_config_defaults()
* function before being modified by the user application.
*/
struct system_gclk_chan_config {
/** Generic Clock Generator source channel. */
enum gclk_generator source_generator;
};
/** \name Generic Clock management
* @{
*/
/**
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
*
* Checks to see if the underlying hardware peripheral module(s) are currently
* synchronizing across multiple clock domains to the hardware bus, This
* function can be used to delay further operations on a module until such time
* that it is ready, to prevent blocking delays for synchronization in the
* user application.
*
* \return Synchronization status of the underlying hardware module(s).
*
* \retval true if the module has completed synchronization
* \retval false if the module synchronization is ongoing
*/
static inline bool system_gclk_is_syncing(void)
{
if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {
return true;
}
return false;
}
void system_gclk_init(void);
/** @} */
/**
* \name Generic Clock management (Generators)
* @{
*/
/**
* \brief Initializes a Generic Clock Generator configuration structure to defaults.
*
* Initializes a given Generic Clock Generator configuration structure to
* a set of known default values. This function should be called on all
* new instances of these configuration structures before being modified
* by the user application.
*
* The default configuration is as follows:
* \li Clock is generated undivided from the source frequency
* \li Clock generator output is low when the generator is disabled
* \li The input clock is sourced from input clock channel 0
* \li Clock will be disabled during sleep
* \li The clock output will not be routed to a physical GPIO pin
*
* \param[out] config Configuration structure to initialize to default values
*/
static inline void system_gclk_gen_get_config_defaults(
struct system_gclk_gen_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->division_factor = 1;
config->high_when_disabled = false;
config->source_clock = GCLK_SOURCE_OSC8M;
config->run_in_standby = false;
config->output_enable = false;
}
void system_gclk_gen_set_config(
const uint8_t generator,
struct system_gclk_gen_config *const config);
void system_gclk_gen_enable(
const uint8_t generator);
void system_gclk_gen_disable(
const uint8_t generator);
bool system_gclk_gen_is_enabled(
const uint8_t generator);
/** @} */
/**
* \name Generic Clock management (Channels)
* @{
*/
/**
* \brief Initializes a Generic Clock configuration structure to defaults.
*
* Initializes a given Generic Clock configuration structure to a set of
* known default values. This function should be called on all new
* instances of these configuration structures before being modified by the
* user application.
*
* The default configuration is as follows:
* \li Clock is sourced from the Generic Clock Generator channel 0
* \li Clock configuration will not be write-locked when set
*
* \param[out] config Configuration structure to initialize to default values
*/
static inline void system_gclk_chan_get_config_defaults(
struct system_gclk_chan_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->source_generator = GCLK_GENERATOR_0;
}
void system_gclk_chan_set_config(
const uint8_t channel,
struct system_gclk_chan_config *const config);
void system_gclk_chan_enable(
const uint8_t channel);
void system_gclk_chan_disable(
const uint8_t channel);
bool system_gclk_chan_is_enabled(
const uint8_t channel);
void system_gclk_chan_lock(
const uint8_t channel);
bool system_gclk_chan_is_locked(
const uint8_t channel);
/** @} */
/**
* \name Generic Clock frequency retrieval
* @{
*/
uint32_t system_gclk_gen_get_hz(
const uint8_t generator);
uint32_t system_gclk_chan_get_hz(
const uint8_t channel);
/** @} */
#ifdef __cplusplus
}
#endif
/** @} */
#endif

129
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/clock/quick_start_clock/qs_clock_source.h Normal file
View file

@ -0,0 +1,129 @@
/**
* \file
*
* \brief SAM System Clock Driver Quick Start
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*/
/**
* \page asfdoc_sam0_system_clock_basic_use_case Quick Start Guide for SYSTEM CLOCK - Basic
*
* In this case we apply the following configuration:
* - RC8MHz (internal 8MHz RC oscillator)
* - Divide by 4, giving a frequency of 2MHz
* - DFLL (Digital frequency locked loop)
* - Open loop mode
* - 48MHz frequency
* - CPU clock
* - Use two wait states when reading from flash memory
* - Use the DFLL, configured to 48MHz
*
* \section asfdoc_sam0_system_clock_basic_use_case_setup Setup
*
* \subsection asfdoc_sam0_system_clock_basic_use_case_setup_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \subsection asfdoc_sam0_system_clock_basic_use_case_setup_code Code
* Copy-paste the following setup code to your application:
* \snippet qs_clock_source.c setup
*
* \subsection asfdoc_sam0_system_clock_basic_use_case_setup_flow Workflow
* -# Create a EXTOSC32K module configuration struct, which can be filled
* out to adjust the configuration of the external 32KHz oscillator channel.
* \snippet qs_clock_source.c config_extosc32k_config
*
* -# Initialize the oscillator configuration struct with the module's default
* values.
* \snippet qs_clock_source.c config_extosc32k_get_defaults
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Alter the EXTOSC32K module configuration struct to require a start-up time
* of 4096 clock cycles.
* \snippet qs_clock_source.c config_extosc32k_change_defaults
*
* -# Write the new configuration to the EXTOSC32K module.
* \snippet qs_clock_source.c config_extosc32k_set_config
*
* -# Create a DFLL module configuration struct, which can be filled
* out to adjust the configuration of the external 32KHz oscillator channel.
* \snippet qs_clock_source.c config_dfll_config
*
* -# Initialize the DFLL oscillator configuration struct with the module's
* default values.
* \snippet qs_clock_source.c config_dfll_get_defaults
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Write the new configuration to the DFLL module.
* \snippet qs_clock_source.c config_dfll_set_config
*
*
* \section asfdoc_sam0_system_clock_basic_use_case_use_main Use Case
*
* \subsection asfdoc_sam0_system_clock_basic_use_case_code Code
*
* Copy-paste the following code to your user application:
* \snippet qs_clock_source.c main
*
* \subsection asfdoc_sam0_system_clock_basic_use_case_flow Workflow
* -# Configure the external 32KHz oscillator source using the previously
* defined setup function.
* \snippet qs_clock_source.c config_extosc32k_main
*
* -# Enable the configured external 32KHz oscillator source.
* \snippet qs_clock_source.c enable_extosc32k_main
*
* -# Configure the DFLL oscillator source using the previously defined setup
* function.
* \snippet qs_clock_source.c config_dfll_main
*
* -# Enable the configured DFLL oscillator source.
* \snippet qs_clock_source.c enable_dfll_main
*
* -# Configure the flash wait states to have two wait states per read, as the
* high speed DFLL will be used as the system clock. If insufficient wait
* states are used, the device may crash randomly due to misread instructions.
* \snippet qs_clock_source.c set_sys_wait_states
*
* -# Switch the system clock source to the DFLL, by reconfiguring the main
* clock generator.
* \snippet qs_clock_source.c set_sys_clk_src
*/

126
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/clock/quick_start_gclk/qs_gclk_basic.h Normal file
View file

@ -0,0 +1,126 @@
/**
* \file
*
* \brief SAM Generic Clock Driver Quick Start
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_system_gclk_basic_use_case Quick Start Guide for SYSTEM CLOCK - GCLK Configuration
*
* In this use case, the GCLK module is configured for:
* \li One generator attached to the internal 8MHz RC oscillator clock source
* \li Generator output equal to input frequency divided by a factor of 128
* \li One channel (connected to the TC0 module) enabled with the enabled generator selected
*
* This use case configures a clock channel to output a clock for a peripheral
* within the device, by first setting up a clock generator from a master clock
* source, and then linking the generator to the desired channel. This clock
* can then be used to clock a module within the device.
*
* \section asfdoc_sam0_system_gclk_basic_use_case_setup Setup
*
* \subsection asfdoc_sam0_system_gclk_basic_use_case_setup_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \subsection asfdoc_sam0_system_gclk_basic_use_case_setup_code Code
* Copy-paste the following setup code to your user application:
* \snippet qs_gclk_basic.c setup
*
* Add to user application initialization (typically the start of \c main()):
* \snippet qs_gclk_basic.c setup_init
*
* \subsection asfdoc_sam0_system_gclk_basic_use_case_setup_flow Workflow
* -# Create a GCLK generator configuration struct, which can be filled out to
* adjust the configuration of a single clock generator.
* \snippet qs_gclk_basic.c setup_1
* -# Initialize the generator configuration struct with the module's default
* values.
* \snippet qs_gclk_basic.c setup_2
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Adjust the configuration struct to request that the master clock source
* channel 0 be used as the source of the generator, and set the generator
* output prescaler to divide the input clock by a factor of 128.
* \snippet qs_gclk_basic.c setup_3
* -# Configure the generator using the configuration structure.
* \snippet qs_gclk_basic.c setup_4
* \note The existing configuration struct may be re-used, as long as any
* values that have been altered from the default settings are taken
* into account by the user application.
*
* -# Enable the generator once it has been properly configured, to begin clock
* generation.
* \snippet qs_gclk_basic.c setup_5
*
* -# Create a GCLK channel configuration struct, which can be filled out to
* adjust the configuration of a single generic clock channel.
* \snippet qs_gclk_basic.c setup_6
* -# Initialize the channel configuration struct with the module's default
* values.
* \snippet qs_gclk_basic.c setup_7
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Adjust the configuration struct to request that the previously configured
* and enabled clock generator be used as the clock source for the channel.
* \snippet qs_gclk_basic.c setup_8
* -# Configure the channel using the configuration structure.
* \snippet qs_gclk_basic.c setup_9
* \note The existing configuration struct may be re-used, as long as any
* values that have been altered from the default settings are taken
* into account by the user application.
*
* -# Enable the channel once it has been properly configured, to output the
* clock to the channel's peripheral module consumers.
* \snippet qs_gclk_basic.c setup_10
*
* \section asfdoc_sam0_system_gclk_basic_use_case_main Use Case
*
* \subsection asfdoc_sam0_system_gclk_basic_use_case_code Code
* Copy-paste the following code to your user application:
* \snippet qs_gclk_basic.c main
*
* \subsection asfdoc_sam0_system_gclk_basic_use_case_flow Workflow
* -# As the clock is generated asynchronously to the system core, no special
* extra application code is required.
*/

102
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/interrupt/quick_start/qs_system_interrupt.h Normal file
View file

@ -0,0 +1,102 @@
/**
* \file
*
* \brief SAM System Interrupt Driver Quick Start
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_system_interrupt_critsec_use_case Quick Start Guide for SYSTEM INTERRUPT - Critical Section Use Case
*
* In this case we perform a critical piece of code, disabling all interrupts
* while a global shared flag is read. During the critical section, no interrupts
* may occur.
*
* \section asfdoc_sam0_system_interrupt_critsec_use_case_setup Setup
*
* \subsection asfdoc_sam0_system_interrupt_critsec_use_case_setup_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \section asfdoc_sam0_system_interrupt_critsec_use_case_use_main Use Case
*
* \subsection asfdoc_sam0_system_interrupt_critsec_use_case_code Code
* Copy-paste the following code to your user application:
* \snippet qs_system_interrupt.c main_1
*
* \subsection asfdoc_sam0_system_interrupt_critsec_use_case_flow Workflow
* -# Enter a critical section to disable global interrupts.
* \snippet qs_system_interrupt.c critical_section_start
* \note Critical sections <i>may</i> be nested if desired; if nested, global
* interrupts will only be re-enabled once the outer-most critical
* section has completed.
*
* -# Check a global shared flag and perform a response. This code may be any
* critical code that requires exclusive access to all resources without the
* possibility of interruption.
* \snippet qs_system_interrupt.c do_critical_code
*
* -# Exit the critical section to re-enable global interrupts.
* \snippet qs_system_interrupt.c critical_section_end
*/
/**
* \page asfdoc_sam0_system_interrupt_enablemodint_use_case Quick Start Guide for SYSTEM INTERRUPT - Enable Module Interrupt Use Case
*
* In this case we enable interrupt handling for a specific module, as well as
* enable interrupts globally for the device.
*
* \section asfdoc_sam0_system_interrupt_enablemodint_use_case_setup Setup
*
* \subsection asfdoc_sam0_system_interrupt_enablemodint_use_case_setup_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \section asfdoc_sam0_system_interrupt_enablemodint_use_case_use_main Use Case
*
* \subsection asfdoc_sam0_system_interrupt_enablemodint_use_case_code Code
* Copy-paste the following code to your user application:
* \snippet qs_system_interrupt.c main_2
*
* \subsection asfdoc_sam0_system_interrupt_enablemodint_use_case_flow Workflow
* -# Enable interrupt handling for the device's RTC peripheral.
* \snippet qs_system_interrupt.c module_int_enable
*
* -# Enable global interrupts, so that any enabled and active interrupt sources
* can trigger their respective handler functions.
* \snippet qs_system_interrupt.c global_int_enable
*/

214
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/interrupt/system_interrupt.c Normal file
View file

@ -0,0 +1,214 @@
/**
* \file
*
* \brief SAM System Interrupt Driver
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "system_interrupt.h"
/**
* \brief Check if a interrupt line is pending
*
* Checks if the requested interrupt vector is pending.
*
* \param[in] vector Interrupt vector number to check
*
* \returns A boolean identifying if the requested interrupt vector is pending.
*
* \retval true Specified interrupt vector is pending
* \retval false Specified interrupt vector is not pending
*
*/
bool system_interrupt_is_pending(
const enum system_interrupt_vector vector)
{
bool result;
if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
result = ((NVIC->ISPR[0] & (1 << vector)) != 0);
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0);
} else {
Assert(false);
result = false;
}
return result;
}
/**
* \brief Set a interrupt vector as pending
*
* Set the requested interrupt vector as pending (i.e issues a software
* interrupt request for the specified vector). The software handler will be
* handled (if enabled) in a priority order based on vector number and
* configured priority settings.
*
* \param[in] vector Interrupt vector number which is set as pending
*
* \returns Status code identifying if the vector was successfully set as
* pending.
*
* \retval STATUS_OK If no error was detected
* \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
*/
enum status_code system_interrupt_set_pending(
const enum system_interrupt_vector vector)
{
enum status_code status = STATUS_OK;
if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
NVIC->ISPR[0] = (1 << vector);
} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
/* Note: Because NMI has highest priority it will be executed
* immediately after it has been set pending */
SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk;
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
SCB->ICSR = SCB_ICSR_PENDSTSET_Msk;
} else {
/* The user want to set something unsupported as pending */
Assert(false);
status = STATUS_ERR_INVALID_ARG;
}
return status;
}
/**
* \brief Clear pending interrupt vector
*
* Clear a pending interrupt vector, so the software handler is not executed.
*
* \param[in] vector Interrupt vector number to clear
*
* \returns A status code identifying if the interrupt pending state was
* successfully cleared.
*
* \retval STATUS_OK If no error was detected
* \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
*/
enum status_code system_interrupt_clear_pending(
const enum system_interrupt_vector vector)
{
enum status_code status = STATUS_OK;
if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
NVIC->ICPR[0] = (1 << vector);
} else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) {
/* Note: Clearing of NMI pending interrupts does not make sense and is
* not supported by the device, as it has the highest priority and will
* always be executed at the moment it is set */
return STATUS_ERR_INVALID_ARG;
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk;
} else {
Assert(false);
status = STATUS_ERR_INVALID_ARG;
}
return status;
}
/**
* \brief Set interrupt vector priority level
*
* Set the priority level of an external interrupt or exception.
*
* \param[in] vector Interrupt vector to change
* \param[in] priority_level New vector priority level to set
*
* \returns Status code indicating if the priority level of the interrupt was
* successfully set.
*
* \retval STATUS_OK If no error was detected
* \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given
*/
enum status_code system_interrupt_set_priority(
const enum system_interrupt_vector vector,
const enum system_interrupt_priority_level priority_level)
{
enum status_code status = STATUS_OK;
if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) {
uint8_t register_num = vector / 4;
uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
NVIC->IP[register_num] =
(NVIC->IP[register_num] & ~(0x3 << priority_pos)) |
(priority_level << priority_pos);
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS);
} else {
Assert(false);
status = STATUS_ERR_INVALID_ARG;
}
return status;
}
/**
* \brief Get interrupt vector priority level
*
* Retrieves the priority level of the requested external interrupt or exception.
*
* \param[in] vector Interrupt vector of which the priority level will be read
*
* \return Currently configured interrupt priority level of the given interrupt
* vector.
*/
enum system_interrupt_priority_level system_interrupt_get_priority(
const enum system_interrupt_vector vector)
{
uint8_t register_num = vector / 4;
uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS);
enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0;
if (vector >= 0) {
priority = (enum system_interrupt_priority_level)
((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
} else if (vector == SYSTEM_INTERRUPT_SYSTICK) {
priority = (enum system_interrupt_priority_level)
((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK);
}
return priority;
}

431
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/interrupt/system_interrupt.h Normal file
View file

@ -0,0 +1,431 @@
/**
* \file
*
* \brief SAM System Interrupt Driver
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SYSTEM_INTERRUPT_H_INCLUDED
#define SYSTEM_INTERRUPT_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt Driver (SYSTEM INTERRUPT)
*
* This driver for SAM devices provides an interface for the configuration
* and management of internal software and hardware interrupts/exceptions.
*
* The following peripherals are used by this module:
* - NVIC (Nested Vector Interrupt Controller)
*
* The following devices can use this module:
* - SAM D20/D21
* - SAM R21
* - SAM D10/D11
*
* The outline of this documentation is as follows:
* - \ref asfdoc_sam0_system_interrupt_prerequisites
* - \ref asfdoc_sam0_system_interrupt_module_overview
* - \ref asfdoc_sam0_system_interrupt_special_considerations
* - \ref asfdoc_sam0_system_interrupt_extra_info
* - \ref asfdoc_sam0_system_interrupt_examples
* - \ref asfdoc_sam0_system_interrupt_api_overview
*
*
* \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites
*
* There are no prerequisites for this module.
*
*
* \section asfdoc_sam0_system_interrupt_module_overview Module Overview
*
* The ARM&reg; Cortex&reg; M0+ core contains an interrupt an exception vector table, which
* can be used to configure the device's interrupt handlers; individual
* interrupts and exceptions can be enabled and disabled, as well as configured
* with a variable priority.
*
* This driver provides a set of wrappers around the core interrupt functions,
* to expose a simple API for the management of global and individual interrupts
* within the device.
*
* \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections
* In some applications it is important to ensure that no interrupts may be
* executed by the system whilst a critical portion of code is being run; for
* example, a buffer may be copied from one context to another - during which
* interrupts must be disabled to avoid corruption of the source buffer contents
* until the copy has completed. This driver provides a basic API to enter and
* exit nested critical sections, so that global interrupts can be kept disabled
* for as long as necessary to complete a critical application code section.
*
* \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts
* For some applications, it may be desirable to raise a module or core
* interrupt via software. For this reason, a set of APIs to set an interrupt or
* exception as pending are provided to the user application.
*
* \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations
*
* Interrupts from peripherals in the SAM devices are on a per-module basis;
* an interrupt raised from any source within a module will cause a single,
* module-common handler to execute. It is the user application or driver's
* responsibility to de-multiplex the module-common interrupt to determine the
* exact interrupt cause.
*
* \section asfdoc_sam0_system_interrupt_extra_info Extra Information
*
* For extra information see \ref asfdoc_sam0_system_interrupt_extra. This includes:
* - \ref asfdoc_sam0_system_interrupt_extra_acronyms
* - \ref asfdoc_sam0_system_interrupt_extra_dependencies
* - \ref asfdoc_sam0_system_interrupt_extra_errata
* - \ref asfdoc_sam0_system_interrupt_extra_history
*
*
* \section asfdoc_sam0_system_interrupt_examples Examples
*
* For a list of examples related to this driver, see
* \ref asfdoc_sam0_system_interrupt_exqsg.
*
* \section asfdoc_sam0_system_interrupt_api_overview API Overview
* @{
*/
#include <compiler.h>
#include <core_cm0plus.h>
#include "system_interrupt_features.h"
/**
* \brief Table of possible system interrupt/exception vector priorities.
*
* Table of all possible interrupt and exception vector priorities within the
* device.
*/
enum system_interrupt_priority_level {
/** Priority level 0, the highest possible interrupt priority. */
SYSTEM_INTERRUPT_PRIORITY_LEVEL_0 = 0,
/** Priority level 1. */
SYSTEM_INTERRUPT_PRIORITY_LEVEL_1 = 1,
/** Priority level 2. */
SYSTEM_INTERRUPT_PRIORITY_LEVEL_2 = 2,
/** Priority level 3, the lowest possible interrupt priority. */
SYSTEM_INTERRUPT_PRIORITY_LEVEL_3 = 3,
};
/**
* \name Critical Section Management
* @{
*/
/**
* \brief Enters a critical section
*
* Disables global interrupts. To support nested critical sections, an internal
* count of the critical section nesting will be kept, so that global interrupts
* are only re-enabled upon leaving the outermost nested critical section.
*
*/
static inline void system_interrupt_enter_critical_section(void)
{
cpu_irq_enter_critical();
}
/**
* \brief Leaves a critical section
*
* Enables global interrupts. To support nested critical sections, an internal
* count of the critical section nesting will be kept, so that global interrupts
* are only re-enabled upon leaving the outermost nested critical section.
*
*/
static inline void system_interrupt_leave_critical_section(void)
{
cpu_irq_leave_critical();
}
/** @} */
/**
* \name Interrupt Enabling/Disabling
* @{
*/
/**
* \brief Check if global interrupts are enabled
*
* Checks if global interrupts are currently enabled.
*
* \returns A boolean that identifies if the global interrupts are enabled or not.
*
* \retval true Global interrupts are currently enabled
* \retval false Global interrupts are currently disabled
*
*/
static inline bool system_interrupt_is_global_enabled(void)
{
return cpu_irq_is_enabled();
}
/**
* \brief Enables global interrupts
*
* Enables global interrupts in the device to fire any enabled interrupt handlers.
*/
static inline void system_interrupt_enable_global(void)
{
cpu_irq_enable();
}
/**
* \brief Disables global interrupts
*
* Disabled global interrupts in the device, preventing any enabled interrupt
* handlers from executing.
*/
static inline void system_interrupt_disable_global(void)
{
cpu_irq_disable();
}
/**
* \brief Checks if an interrupt vector is enabled or not
*
* Checks if a specific interrupt vector is currently enabled.
*
* \param[in] vector Interrupt vector number to check
*
* \returns A variable identifying if the requested interrupt vector is enabled
*
* \retval true Specified interrupt vector is currently enabled
* \retval false Specified interrupt vector is currently disabled
*
*/
static inline bool system_interrupt_is_enabled(
const enum system_interrupt_vector vector)
{
return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001);
}
/**
* \brief Enable interrupt vector
*
* Enables execution of the software handler for the requested interrupt vector.
*
* \param[in] vector Interrupt vector to enable
*/
static inline void system_interrupt_enable(
const enum system_interrupt_vector vector)
{
NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
}
/**
* \brief Disable interrupt vector
*
* Disables execution of the software handler for the requested interrupt vector.
*
* \param[in] vector Interrupt vector to disable
*/
static inline void system_interrupt_disable(
const enum system_interrupt_vector vector)
{
NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f));
}
/** @} */
/**
* \name Interrupt State Management
* @{
*/
/**
* \brief Get active interrupt (if any)
*
* Return the vector number for the current executing software handler, if any.
*
* \return Interrupt number that is currently executing.
*/
static inline enum system_interrupt_vector system_interrupt_get_active(void)
{
uint32_t IPSR = __get_IPSR();
return (enum system_interrupt_vector)(IPSR & _SYSTEM_INTERRUPT_IPSR_MASK);
}
bool system_interrupt_is_pending(
const enum system_interrupt_vector vector);
enum status_code system_interrupt_set_pending(
const enum system_interrupt_vector vector);
enum status_code system_interrupt_clear_pending(
const enum system_interrupt_vector vector);
/** @} */
/**
* \name Interrupt Priority Management
* @{
*/
enum status_code system_interrupt_set_priority(
const enum system_interrupt_vector vector,
const enum system_interrupt_priority_level priority_level);
enum system_interrupt_priority_level system_interrupt_get_priority(
const enum system_interrupt_vector vector);
/** @} */
/** @} */
/**
* \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver
*
* \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms
* The table below presents the acronyms used in this module:
*
* <table>
* <tr>
* <th>Acronym</th>
* <th>Description</th>
* </tr>
* <tr>
* <td>ISR</td>
* <td>Interrupt Service Routine</td>
* </tr>
* <tr>
* <td>NMI</td>
* <td>Non-maskable interrupt</td>
* </tr>
* <tr>
* <td>SERCOM</td>
* <td>Serial Communication Interface</td>
* </tr>
* </table>
*
*
* \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies
* This driver has the following dependencies:
*
* - None
*
*
* \section asfdoc_sam0_system_interrupt_extra_errata Errata
* There are no errata related to this driver.
*
*
* \section asfdoc_sam0_system_interrupt_extra_history Module History
* An overview of the module history is presented in the table below, with
* details on the enhancements and fixes made to the module since its first
* release. The current version of this corresponds to the newest version in
* the table.
*
* <table>
* <tr>
* <th>Changelog</th>
* </tr>
* <tr>
* <td>Added support for SAMD10/D11</td>
* </tr>
* <tr>
* <td>Added support for SAMR21</td>
* </tr>
* <tr>
* <td>Added support for SAMD21</td>
* </tr>
* <tr>
* <td>Initial Release</td>
* </tr>
* </table>
*/
/**
* \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver
*
* This is a list of the available Quick Start guides (QSGs) and example
* applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with
* step-by-step instructions to configure and use this driver in a selection of
* use cases. Note that QSGs can be compiled as a standalone application or be
* added to the user application.
*
* - \subpage asfdoc_sam0_system_interrupt_critsec_use_case
* - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case
*
* \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>E</td>
* <td>04/2014</td>
* <td>Add support for SAMD10/D11.</td>
* </tr>
* <tr>
* <td>D</td>
* <td>02/2014</td>
* <td>Add support for SAMR21.</td>
* </tr>
* <tr>
* <td>C</td>
* <td>01/2014</td>
* <td>Add support for SAMD21.</td>
* </tr>
* <tr>
* <td>B</td>
* <td>06/2013</td>
* <td>Corrected documentation typos.</td>
* </tr>
* <tr>
* <td>A</td>
* <td>06/2013</td>
* <td>Initial release</td>
* </tr>
* </table>
*/
#ifdef __cplusplus
}
#endif
#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED

170
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h Normal file
View file

@ -0,0 +1,170 @@
/**
* \file
*
* \brief SAM D21 System Interrupt Driver
*
* Copyright (C) 2013-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED
#if !defined(__DOXYGEN__)
/* Generates a interrupt vector table enum list entry for a given module type
and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */
# define _MODULE_IRQn(n, module) \
SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn,
/* Generates interrupt vector table enum list entries for all instances of a
given module type on the selected device. */
# define _SYSTEM_INTERRUPT_MODULES(name) \
MREPEAT(name##_INST_NUM, _MODULE_IRQn, name)
# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f
# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000007
# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0
# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 29
#endif
/**
* \addtogroup asfdoc_sam0_system_interrupt_group
* @{
*/
/**
* \brief Table of possible system interrupt/exception vector numbers.
*
* Table of all possible interrupt and exception vector indexes within the
* SAMD21 device.
*/
#if defined(__DOXYGEN__)
/** \note The actual enumeration name is "system_interrupt_vector". */
enum system_interrupt_vector_samd21 {
#else
enum system_interrupt_vector {
#endif
/** Interrupt vector index for a NMI interrupt. */
SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn,
/** Interrupt vector index for a Hard Fault memory access exception. */
SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn,
/** Interrupt vector index for a Supervisor Call exception. */
SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn,
/** Interrupt vector index for a Pending Supervisor interrupt. */
SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn,
/** Interrupt vector index for a System Tick interrupt. */
SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn,
/** Interrupt vector index for a Power Manager peripheral interrupt. */
SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn,
/** Interrupt vector index for a System Control peripheral interrupt. */
SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn,
/** Interrupt vector index for a Watch Dog peripheral interrupt. */
SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn,
/** Interrupt vector index for a Real Time Clock peripheral interrupt. */
SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn,
/** Interrupt vector index for an External Interrupt peripheral interrupt. */
SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn,
/** Interrupt vector index for a Non Volatile Memory Controller interrupt. */
SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn,
/** Interrupt vector index for a Direct Memory Access interrupt. */
SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn,
/** Interrupt vector index for a Universal Serial Bus interrupt. */
SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn,
/** Interrupt vector index for an Event System interrupt. */
SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn,
#if defined(__DOXYGEN__)
/** Interrupt vector index for a SERCOM peripheral interrupt.
*
* Each specific device may contain several SERCOM peripherals; each module
* instance will have its own entry in the table, with the instance number
* substituted for "n" in the entry name (e.g.
* \c SYSTEM_INTERRUPT_MODULE_SERCOM0).
*/
SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn,
/** Interrupt vector index for a Timer/Counter Control peripheral interrupt.
*
* Each specific device may contain several TCC peripherals; each module
* instance will have its own entry in the table, with the instance number
* substituted for "n" in the entry name (e.g.
* \c SYSTEM_INTERRUPT_MODULE_TCC0).
*/
SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn,
/** Interrupt vector index for a Timer/Counter peripheral interrupt.
*
* Each specific device may contain several TC peripherals; each module
* instance will have its own entry in the table, with the instance number
* substituted for "n" in the entry name (e.g.
* \c SYSTEM_INTERRUPT_MODULE_TC3).
*/
SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn,
#else
_SYSTEM_INTERRUPT_MODULES(SERCOM)
_SYSTEM_INTERRUPT_MODULES(TCC)
SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn,
SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn,
SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn,
# if (SAMD21J)
//SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn,
//SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn,
# endif
#endif
/** Interrupt vector index for an Analog Comparator peripheral interrupt. */
SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn,
/** Interrupt vector index for an Analog-to-Digital peripheral interrupt. */
SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn,
/** Interrupt vector index for a Digital-to-Analog peripheral interrupt. */
SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn,
/** Interrupt vector index for a Peripheral Touch Controller peripheral
* interrupt. */
SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn,
/** Interrupt vector index for a Inter-IC Sound Interface peripheral
* interrupt. */
SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn,
};
/** @} */
#endif

215
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/pinmux/pinmux.c Normal file
View file

@ -0,0 +1,215 @@
/**
* \file
*
* \brief SAM Pin Multiplexer Driver
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <pinmux.h>
/**
* \internal
* Writes out a given configuration of a Port pin configuration to the
* hardware module.
*
* \note If the pin direction is set as an output, the pull-up/pull-down input
* configuration setting is ignored.
*
* \param[in] port Base of the PORT module to configure.
* \param[in] pin_mask Mask of the port pin to configure.
* \param[in] config Configuration settings for the pin.
*/
static void _system_pinmux_config(
PortGroup *const port,
const uint32_t pin_mask,
const struct system_pinmux_config *const config)
{
Assert(port);
Assert(config);
/* Track the configuration bits into a temporary variable before writing */
uint32_t pin_cfg = 0;
/* Enabled powersave mode, don't create configuration */
if (!config->powersave) {
/* Enable the pin peripheral mux flag if non-GPIO selected (pin mux will
* be written later) and store the new mux mask */
if (config->mux_position != SYSTEM_PINMUX_GPIO) {
pin_cfg |= PORT_WRCONFIG_PMUXEN;
pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos);
}
/* Check if the user has requested that the input buffer be enabled */
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) ||
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
/* Enable input buffer flag */
pin_cfg |= PORT_WRCONFIG_INEN;
/* Enable pull-up/pull-down control flag if requested */
if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) {
pin_cfg |= PORT_WRCONFIG_PULLEN;
}
/* Clear the port DIR bits to disable the output buffer */
port->DIRCLR.reg = pin_mask;
}
/* Check if the user has requested that the output buffer be enabled */
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
/* Cannot use a pullup if the output driver is enabled,
* if requested the input buffer can only sample the current
* output state */
pin_cfg &= ~PORT_WRCONFIG_PULLEN;
}
}
/* The Write Configuration register (WRCONFIG) requires the
* pins to to grouped into two 16-bit half-words - split them out here */
uint32_t lower_pin_mask = (pin_mask & 0xFFFF);
uint32_t upper_pin_mask = (pin_mask >> 16);
/* Configure the lower 16-bits of the port to the desired configuration,
* including the pin peripheral multiplexer just in case it is enabled */
port->WRCONFIG.reg
= (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG;
/* Configure the upper 16-bits of the port to the desired configuration,
* including the pin peripheral multiplexer just in case it is enabled */
port->WRCONFIG.reg
= (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) |
pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG |
PORT_WRCONFIG_HWSEL;
if(!config->powersave) {
/* Set the pull-up state once the port pins are configured if one was
* requested and it does not violate the valid set of port
* configurations */
if (pin_cfg & PORT_WRCONFIG_PULLEN) {
/* Set the OUT register bits to enable the pullup if requested,
* clear to enable pull-down */
if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) {
port->OUTSET.reg = pin_mask;
} else {
port->OUTCLR.reg = pin_mask;
}
}
/* Check if the user has requested that the output buffer be enabled */
if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) ||
(config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) {
/* Set the port DIR bits to enable the output buffer */
port->DIRSET.reg = pin_mask;
}
}
}
/**
* \brief Writes a Port pin configuration to the hardware module.
*
* Writes out a given configuration of a Port pin configuration to the hardware
* module.
*
* \note If the pin direction is set as an output, the pull-up/pull-down input
* configuration setting is ignored.
*
* \param[in] gpio_pin Index of the GPIO pin to configure.
* \param[in] config Configuration settings for the pin.
*/
void system_pinmux_pin_set_config(
const uint8_t gpio_pin,
const struct system_pinmux_config *const config)
{
PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_mask = (1UL << (gpio_pin % 32));
_system_pinmux_config(port, pin_mask, config);
}
/**
* \brief Writes a Port pin group configuration to the hardware module.
*
* Writes out a given configuration of a Port pin group configuration to the
* hardware module.
*
* \note If the pin direction is set as an output, the pull-up/pull-down input
* configuration setting is ignored.
*
* \param[in] port Base of the PORT module to configure.
* \param[in] mask Mask of the port pin(s) to configure.
* \param[in] config Configuration settings for the pin.
*/
void system_pinmux_group_set_config(
PortGroup *const port,
const uint32_t mask,
const struct system_pinmux_config *const config)
{
Assert(port);
for (int i = 0; i < 32; i++) {
if (mask & (1UL << i)) {
_system_pinmux_config(port, (1UL << i), config);
}
}
}
/**
* \brief Configures the input sampling mode for a group of pins.
*
* Configures the input sampling mode for a group of pins, to
* control when the physical I/O pin value is sampled and
* stored inside the microcontroller.
*
* \param[in] port Base of the PORT module to configure.
* \param[in] mask Mask of the port pin(s) to configure.
* \param[in] mode New pin sampling mode to configure.
*/
void system_pinmux_group_set_input_sample_mode(
PortGroup *const port,
const uint32_t mask,
const enum system_pinmux_pin_sample mode)
{
Assert(port);
if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
port->CTRL.reg |= mask;
} else {
port->CTRL.reg &= ~mask;
}
}

517
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/pinmux/pinmux.h Normal file
View file

@ -0,0 +1,517 @@
/**
* \file
*
* \brief SAM Pin Multiplexer Driver
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef PINMUX_H_INCLUDED
#define PINMUX_H_INCLUDED
/**
* \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer Driver (SYSTEM PINMUX)
*
* This driver for SAM devices provides an interface for the configuration
* and management of the device's physical I/O Pins, to alter the direction and
* input/drive characteristics as well as to configure the pin peripheral
* multiplexer selection.
*
* The following peripherals are used by this module:
* - PORT (Port I/O Management)
*
* The following devices can use this module:
* - SAM D20/D21
* - SAM R21
* - SAM D10/D11
*
* Physically, the modules are interconnected within the device as shown in the
* following diagram:
*
* The outline of this documentation is as follows:
* - \ref asfdoc_sam0_system_pinmux_prerequisites
* - \ref asfdoc_sam0_system_pinmux_module_overview
* - \ref asfdoc_sam0_system_pinmux_special_considerations
* - \ref asfdoc_sam0_system_pinmux_extra_info
* - \ref asfdoc_sam0_system_pinmux_examples
* - \ref asfdoc_sam0_system_pinmux_api_overview
*
*
* \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites
*
* There are no prerequisites for this module.
*
*
* \section asfdoc_sam0_system_pinmux_module_overview Module Overview
*
* The SAM devices contain a number of General Purpose I/O pins, used to
* interface the user application logic and internal hardware peripherals to
* an external system. The Pin Multiplexer (PINMUX) driver provides a method
* of configuring the individual pin peripheral multiplexers to select
* alternate pin functions.
*
* \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins
* SAM devices use two naming conventions for the I/O pins in the device; one
* physical, and one logical. Each physical pin on a device package is assigned
* both a physical port and pin identifier (e.g. "PORTA.0") as well as a
* monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the
* former is used to map physical pins to their physical internal device module
* counterparts, for simplicity the design of this driver uses the logical GPIO
* numbers instead.
*
* \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing
* SAM devices contain a peripheral MUX, which is individually controllable
* for each I/O pin of the device. The peripheral MUX allows you to select the
* function of a physical package pin - whether it will be controlled as a user
* controllable GPIO pin, or whether it will be connected internally to one of
* several peripheral modules (such as an I<SUP>2</SUP>C module). When a pin is
* configured in GPIO mode, other peripherals connected to the same pin will be
* disabled.
*
* \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics
* There are several special modes that can be selected on one or more I/O pins
* of the device, which alter the input and output characteristics of the pad:
*
* \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength
* The Drive Strength configures the strength of the output driver on the
* pad. Normally, there is a fixed current limit that each I/O pin can safely
* drive, however some I/O pads offer a higher drive mode which increases this
* limit for that I/O pin at the expense of an increased power consumption.
*
* \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate
* The Slew Rate configures the slew rate of the output driver, limiting the
* rate at which the pad output voltage can change with time.
*
* \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode
* The Input Sample Mode configures the input sampler buffer of the pad. By
* default, the input buffer is only sampled "on-demand", i.e. when the user
* application attempts to read from the input buffer. This mode is the most
* power efficient, but increases the latency of the input sample by two clock
* cycles of the port clock. To reduce latency, the input sampler can instead
* be configured to always sample the input buffer on each port clock cycle, at
* the expense of an increased power consumption.
*
* \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection
*
* \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows
* how this module is interconnected within the device:
*
* \anchor asfdoc_sam0_system_pinmux_intconnections
* \dot
* digraph overview {
* node [label="Port Pad" shape=square] pad;
*
* subgraph driver {
* node [label="Peripheral Mux" shape=trapezium] pinmux;
* node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio;
* node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals;
* }
*
* pinmux -> gpio;
* pad -> pinmux;
* pinmux -> peripherals;
* }
* \enddot
*
* \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations
*
* The SAM port pin input sampling mode is set in groups of four physical
* pins; setting the sampling mode of any pin in a sub-group of eight I/O pins
* will configure the sampling mode of the entire sub-group.
*
* High Drive Strength output driver mode is not available on all device pins -
* refer to your device specific datasheet.
*
*
* \section asfdoc_sam0_system_pinmux_extra_info Extra Information
*
* For extra information see \ref asfdoc_sam0_system_pinmux_extra. This includes:
* - \ref asfdoc_sam0_system_pinmux_extra_acronyms
* - \ref asfdoc_sam0_system_pinmux_extra_dependencies
* - \ref asfdoc_sam0_system_pinmux_extra_errata
* - \ref asfdoc_sam0_system_pinmux_extra_history
*
*
* \section asfdoc_sam0_system_pinmux_examples Examples
*
* For a list of examples related to this driver, see
* \ref asfdoc_sam0_system_pinmux_exqsg.
*
*
* \section asfdoc_sam0_system_pinmux_api_overview API Overview
* @{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Peripheral multiplexer index to select GPIO mode for a pin. */
#define SYSTEM_PINMUX_GPIO (1 << 7)
/**
* \brief Port pin direction configuration enum.
*
* Enum for the possible pin direction settings of the port pin configuration
* structure, to indicate the direction the pin should use.
*/
enum system_pinmux_pin_dir {
/** The pin's input buffer should be enabled, so that the pin state can
* be read. */
SYSTEM_PINMUX_PIN_DIR_INPUT,
/** The pin's output buffer should be enabled, so that the pin state can
* be set (but not read back). */
SYSTEM_PINMUX_PIN_DIR_OUTPUT,
/** The pin's output and input buffers should both be enabled, so that the
* pin state can be set and read back. */
SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK,
};
/**
* \brief Port pin input pull configuration enum.
*
* Enum for the possible pin pull settings of the port pin configuration
* structure, to indicate the type of logic level pull the pin should use.
*/
enum system_pinmux_pin_pull {
/** No logical pull should be applied to the pin. */
SYSTEM_PINMUX_PIN_PULL_NONE,
/** Pin should be pulled up when idle. */
SYSTEM_PINMUX_PIN_PULL_UP,
/** Pin should be pulled down when idle. */
SYSTEM_PINMUX_PIN_PULL_DOWN,
};
/**
* \brief Port pin digital input sampling mode enum.
*
* Enum for the possible input sampling modes for the port pin configuration
* structure, to indicate the type of sampling a port pin should use.
*/
enum system_pinmux_pin_sample {
/** Pin input buffer should continuously sample the pin state. */
SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS,
/** Pin input buffer should be enabled when the IN register is read. */
SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND,
};
/**
* \brief Port pin configuration structure.
*
* Configuration structure for a port pin instance. This structure should be
* structure should be initialized by the
* \ref system_pinmux_get_config_defaults() function before being modified by
* the user application.
*/
struct system_pinmux_config {
/** MUX index of the peripheral that should control the pin, if peripheral
* control is desired. For GPIO use, this should be set to
* \ref SYSTEM_PINMUX_GPIO. */
uint8_t mux_position;
/** Port buffer input/output direction. */
enum system_pinmux_pin_dir direction;
/** Logic level pull of the input buffer. */
enum system_pinmux_pin_pull input_pull;
/** Enable lowest possible powerstate on the pin
*
* \note All other configurations will be ignored, the pin will be disabled
*/
bool powersave;
};
/** \name Configuration and initialization
* @{
*/
/**
* \brief Initializes a Port pin configuration structure to defaults.
*
* Initializes a given Port pin configuration structure to a set of
* known default values. This function should be called on all new
* instances of these configuration structures before being modified by the
* user application.
*
* The default configuration is as follows:
* \li Non peripheral (i.e. GPIO) controlled
* \li Input mode with internal pull-up enabled
*
* \param[out] config Configuration structure to initialize to default values
*/
static inline void system_pinmux_get_config_defaults(
struct system_pinmux_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->mux_position = SYSTEM_PINMUX_GPIO;
config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
config->powersave = false;
}
void system_pinmux_pin_set_config(
const uint8_t gpio_pin,
const struct system_pinmux_config *const config);
void system_pinmux_group_set_config(
PortGroup *const port,
const uint32_t mask,
const struct system_pinmux_config *const config);
/** @} */
/** \name Special mode configuration (physical group orientated)
* @{
*/
/**
* \brief Retrieves the PORT module group instance from a given GPIO pin number.
*
* Retrieves the PORT module group instance associated with a given logical
* GPIO pin number.
*
* \param[in] gpio_pin Index of the GPIO pin to convert.
*
* \return Base address of the associated PORT module.
*/
static inline PortGroup* system_pinmux_get_group_from_gpio_pin(
const uint8_t gpio_pin)
{
uint8_t port_index = (gpio_pin / 128);
uint8_t group_index = (gpio_pin / 32);
/* Array of available ports. */
Port *const ports[PORT_INST_NUM] = PORT_INSTS;
if (port_index < PORT_INST_NUM) {
return &(ports[port_index]->Group[group_index]);
} else {
Assert(false);
return NULL;
}
}
void system_pinmux_group_set_input_sample_mode(
PortGroup *const port,
const uint32_t mask,
const enum system_pinmux_pin_sample mode);
/** @} */
/** \name Special mode configuration (logical pin orientated)
* @{
*/
/**
* \brief Retrieves the currently selected MUX position of a logical pin.
*
* Retrieves the selected MUX peripheral on a given logical GPIO pin.
*
* \param[in] gpio_pin Index of the GPIO pin to configure.
*
* \return Currently selected peripheral index on the specified pin.
*/
static inline uint8_t system_pinmux_pin_get_mux_position(
const uint8_t gpio_pin)
{
PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_index = (gpio_pin % 32);
if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) {
return SYSTEM_PINMUX_GPIO;
}
uint32_t pmux_reg = port->PMUX[pin_index / 2].reg;
if (pin_index & 1) {
return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos;
}
else {
return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos;
}
}
/**
* \brief Configures the input sampling mode for a GPIO pin.
*
* Configures the input sampling mode for a GPIO input, to
* control when the physical I/O pin value is sampled and
* stored inside the microcontroller.
*
* \param[in] gpio_pin Index of the GPIO pin to configure.
* \param[in] mode New pin sampling mode to configure.
*/
static inline void system_pinmux_pin_set_input_sample_mode(
const uint8_t gpio_pin,
const enum system_pinmux_pin_sample mode)
{
PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin);
uint32_t pin_index = (gpio_pin % 32);
if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) {
port->CTRL.reg |= (1 << pin_index);
} else {
port->CTRL.reg &= ~(1 << pin_index);
}
}
/** @} */
#ifdef __cplusplus
}
#endif
/** @} */
/**
* \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver
*
* \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms
* The table below presents the acronyms used in this module:
*
* <table>
* <tr>
* <th>Acronym</th>
* <th>Description</th>
* </tr>
* <tr>
* <td>GPIO</td>
* <td>General Purpose Input/Output</td>
* </tr>
* <tr>
* <td>MUX</td>
* <td>Multiplexer</td>
* </tr>
* </table>
*
*
* \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies
* This driver has the following dependencies:
*
* - None
*
*
* \section asfdoc_sam0_system_pinmux_extra_errata Errata
* There are no errata related to this driver.
*
*
* \section asfdoc_sam0_system_pinmux_extra_history Module History
* An overview of the module history is presented in the table below, with
* details on the enhancements and fixes made to the module since its first
* release. The current version of this corresponds to the newest version in
* the table.
*
* <table>
* <tr>
* <th>Changelog</th>
* </tr>
* <tr>
* <td>Removed code of open drain, slew limit and drive strength
* features.</td>
* </tr>
* <tr>
* <td>Fixed broken sampling mode function implementations, which wrote
* corrupt configuration values to the device registers.</td>
* </tr>
* <tr>
* <td>Added missing NULL pointer asserts to the PORT driver functions.</td>
* </tr>
* <tr>
* <td>Initial Release</td>
* </tr>
* </table>
*/
/**
* \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver
*
* This is a list of the available Quick Start guides (QSGs) and example
* applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple
* examples with step-by-step instructions to configure and use this driver in a
* selection of use cases. Note that QSGs can be compiled as a standalone
* application or be added to the user application.
*
* - \subpage asfdoc_sam0_system_pinmux_basic_use_case
*
* \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>F</td>
* <td>04/2014</td>
* <td>Add support for SAMD10/D11</td>
* </tr>
* <tr>
* <td>E</td>
* <td>02/2014</td>
* <td>Add support for SAMR21</td>
* </tr>
* <tr>
* <td>D</td>
* <td>01/2014</td>
* <td>Add support for SAMD21</td>
* </tr>
* <tr>
* <td>C</td>
* <td>09/2013</td>
* <td>Fixed incorrect documentation for the device pin sampling mode.</td>
* </tr>
* <tr>
* <td>B</td>
* <td>06/2013</td>
* <td>Corrected documentation typos.</td>
* </tr>
* <tr>
* <td>A</td>
* <td>06/2013</td>
* <td>Initial release</td>
* </tr>
* </table>
*/
#endif

93
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/pinmux/quick_start/qs_pinmux_basic.h Normal file
View file

@ -0,0 +1,93 @@
/**
* \file
*
* \brief SAM PINMUX Driver Quick Start
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/**
* \page asfdoc_sam0_system_pinmux_basic_use_case Quick Start Guide for SYSTEM PINMUX - Basic
*
* In this use case, the PINMUX module is configured for:
* \li One pin in input mode, with pull-up enabled, connected to the GPIO
* module
* \li Sampling mode of the pin changed to sample on demand
*
* This use case sets up the PINMUX to configure a physical I/O pin set as
* an input with pull-up. and changes the sampling mode of the pin to reduce
* power by only sampling the physical pin state when the user application
* attempts to read it.
*
* \section asfdoc_sam0_system_pinmux_basic_use_case_setup Setup
*
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_prereq Prerequisites
* There are no special setup requirements for this use-case.
*
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_code Code
* Copy-paste the following setup code to your application:
* \snippet qs_pinmux_basic.c setup
*
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_setup_flow Workflow
* -# Create a PINMUX module pin configuration struct, which can be filled out
* to adjust the configuration of a single port pin.
* \snippet qs_pinmux_basic.c pinmux_config
* -# Initialize the pin configuration struct with the module's default values.
* \snippet qs_pinmux_basic.c pinmux_config_defaults
* \note This should always be performed before using the configuration
* struct to ensure that all values are initialized to known default
* settings.
*
* -# Adjust the configuration struct to request an input pin with pullup
* connected to the GPIO peripheral.
* \snippet qs_pinmux_basic.c pinmux_update_config_values
* -# Configure GPIO10 with the initialized pin configuration struct, to enable
* the input sampler on the pin.
* \snippet qs_pinmux_basic.c pinmux_set_config
*
* \section asfdoc_sam0_system_pinmux_basic_use_case_use_main Use Case
*
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_code Code
* Copy-paste the following code to your user application:
* \snippet qs_pinmux_basic.c main
*
* \subsection asfdoc_sam0_system_pinmux_basic_use_case_flow Workflow
* -# Adjust the configuration of the pin to enable on-demand sampling mode.
* \snippet qs_pinmux_basic.c pinmux_change_input_sampling
*/

102
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/system.c Normal file
View file

@ -0,0 +1,102 @@
/**
* \file
*
* \brief SAM System related functionality
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <system.h>
/**
* \internal
* Dummy initialization function, used as a weak alias target for the various
* init functions called by \ref system_init().
*/
void _system_dummy_init(void);
void _system_dummy_init(void)
{
return;
}
#if !defined(__DOXYGEN__)
# if defined(__GNUC__)
void system_clock_init(void) WEAK __attribute__((alias("_system_dummy_init")));
void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init")));
void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init")));
void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init")));
# elif defined(__ICCARM__)
void system_clock_init(void);
void system_board_init(void);
void _system_events_init(void);
void _system_extint_init(void);
# pragma weak system_clock_init=_system_dummy_init
# pragma weak system_board_init=_system_dummy_init
# pragma weak _system_events_init=_system_dummy_init
# pragma weak _system_extint_init=_system_dummy_init
# endif
#endif
/**
* \brief Initialize system
*
* This function will call the various initialization functions within the
* system namespace. If a given optional system module is not available, the
* associated call will effectively be a NOP (No Operation).
*
* Currently the following initialization functions are supported:
* - System clock initialization (via the SYSTEM CLOCK sub-module)
* - Board hardware initialization (via the Board module)
* - Event system driver initialization (via the EVSYS module)
* - External Interrupt driver initialization (via the EXTINT module)
*/
void system_init(void)
{
/* Configure GCLK and clock sources according to conf_clocks.h */
system_clock_init();
/* Initialize board hardware */
system_board_init();
/* Initialize EVSYS hardware */
_system_events_init();
/* Initialize External hardware */
_system_extint_init();
}

577
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/system/system.h Normal file
View file

@ -0,0 +1,577 @@
/**
* \file
*
* \brief SAM System related functionality
*
* Copyright (C) 2012-2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SYSTEM_H_INCLUDED
#define SYSTEM_H_INCLUDED
#include <compiler.h>
#include <clock.h>
#include <gclk.h>
#include <pinmux.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup asfdoc_sam0_system_group SAM System Driver (SYSTEM)
*
* This driver for SAM devices provides an interface for the configuration
* and management of the device's system relation functionality, necessary for
* the basic device operation. This is not limited to a single peripheral, but
* extends across multiple hardware peripherals,
*
* The following peripherals are used by this module:
* - SYSCTRL (System Control)
* - PM (Power Manager)
*
* The following devices can use this module:
* - SAM D20/D21
* - SAM R21
* - SAM D10/D11
*
* The outline of this documentation is as follows:
* - \ref asfdoc_sam0_system_prerequisites
* - \ref asfdoc_sam0_system_module_overview
* - \ref asfdoc_sam0_system_special_considerations
* - \ref asfdoc_sam0_system_extra_info
* - \ref asfdoc_sam0_system_examples
* - \ref asfdoc_sam0_system_api_overview
*
*
* \section asfdoc_sam0_system_prerequisites Prerequisites
*
* There are no prerequisites for this module.
*
*
* \section asfdoc_sam0_system_module_overview Module Overview
*
* The System driver provides a collection of interfaces between the user
* application logic, and the core device functionality (such as clocks, reset
* cause determination, etc.) that is required for all applications. It contains
* a number of sub-modules that control one specific aspect of the device:
*
* - System Core (this module)
* - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module)
* - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module)
* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module)
*
*
* \subsection asfdoc_sam0_system_module_overview_vref Voltage References
* The various analog modules within the SAM devices (such as AC, ADC and
* DAC) require a voltage reference to be configured to act as a reference point
* for comparisons and conversions.
*
* The SAM devices contain multiple references, including an internal
* temperature sensor, and a fixed band-gap voltage source. When enabled, the
* associated voltage reference can be selected within the desired peripheral
* where applicable.
*
* \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause
* In some application there may be a need to execute a different program
* flow based on how the device was reset. For example, if the cause of reset
* was the Watchdog timer (WDT), this might indicate an error in the application
* and a form of error handling or error logging might be needed.
*
* For this reason, an API is provided to retrieve the cause of the last system
* reset, so that appropriate action can be taken.
*
* \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes
* The SAM devices have several sleep modes, where the sleep mode controls
* which clock systems on the device will remain enabled or disabled when the
* device enters a low power sleep mode.
* \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the
* clock settings of the different sleep modes.
*
* \anchor asfdoc_sam0_system_module_sleep_mode_table
* <table>
* <caption>SAM Device Sleep Modes</caption>
* <tr>
* <th>Sleep mode</th>
* <th>CPU clock</th>
* <th>AHB clock</th>
* <th>APB clocks</th>
* <th>Clock sources</th>
* <th>System clock</th>
* <th>32KHz</th>
* <th>Reg mode</th>
* <th>RAM mode</th>
* </tr>
* <tr>
* <td>IDLE 0</td>
* <td>Stop</td>
* <td>Run</td>
* <td>Run</td>
* <td>Run</td>
* <td>Run</td>
* <td>Run</td>
* <td>Normal</td>
* <td>Normal</td>
* </tr>
* <tr>
* <td>IDLE 1</td>
* <td>Stop</td>
* <td>Stop</td>
* <td>Run</td>
* <td>Run</td>
* <td>Run</td>
* <td>Run</td>
* <td>Normal</td>
* <td>Normal</td>
* </tr>
* <tr>
* <td>IDLE 2</td>
* <td>Stop</td>
* <td>Stop</td>
* <td>Stop</td>
* <td>Run</td>
* <td>Run</td>
* <td>Run</td>
* <td>Normal</td>
* <td>Normal</td>
* </tr>
* <tr>
* <td>STANDBY</td>
* <td>Stop</td>
* <td>Stop</td>
* <td>Stop</td>
* <td>Stop</td>
* <td>Stop</td>
* <td>Stop</td>
* <td>Low Power</td>
* <td>Source/Drain biasing</td>
* </tr>
* </table>
*
* To enter device sleep, one of the available sleep modes must be set, and the
* function to enter sleep called. The device will automatically wake up in
* response to an interrupt being generated or other device event.
*
* Some peripheral clocks will remain enabled during sleep, depending on their
* configuration; if desired, modules can remain clocked during sleep to allow
* them to continue to operate while other parts of the system are powered down
* to save power.
*
*
* \section asfdoc_sam0_system_special_considerations Special Considerations
*
* Most of the functions in this driver have device specific restrictions and
* caveats; refer to your device datasheet.
*
*
* \section asfdoc_sam0_system_extra_info Extra Information
*
* For extra information see \ref asfdoc_sam0_system_extra. This includes:
* - \ref asfdoc_sam0_system_extra_acronyms
* - \ref asfdoc_sam0_system_extra_dependencies
* - \ref asfdoc_sam0_system_extra_errata
* - \ref asfdoc_sam0_system_extra_history
*
*
* \section asfdoc_sam0_system_examples Examples
*
* For SYSTEM module related examples, please refer to the sub-modules listed in
* the \ref asfdoc_sam0_system_module_overview "system module overview".
*
*
* \section asfdoc_sam0_system_api_overview API Overview
* @{
*/
/**
* \brief Voltage references within the device.
*
* List of available voltage references (VREF) that may be used within the
* device.
*/
enum system_voltage_reference {
/** Temperature sensor voltage reference. */
SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE,
/** Bandgap voltage reference. */
SYSTEM_VOLTAGE_REFERENCE_BANDGAP,
};
/**
* \brief Device sleep modes.
*
* List of available sleep modes in the device. A table of clocks available in
* different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode.
*/
enum system_sleepmode {
/** IDLE 0 sleep mode. */
SYSTEM_SLEEPMODE_IDLE_0,
/** IDLE 1 sleep mode. */
SYSTEM_SLEEPMODE_IDLE_1,
/** IDLE 2 sleep mode. */
SYSTEM_SLEEPMODE_IDLE_2,
/** Standby sleep mode. */
SYSTEM_SLEEPMODE_STANDBY,
};
/**
* \brief Reset causes of the system.
*
* List of possible reset causes of the system.
*/
enum system_reset_cause {
/** The system was last reset by a software reset. */
SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST,
/** The system was last reset by the watchdog timer. */
SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT,
/** The system was last reset because the external reset line was pulled low. */
SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT,
/** The system was last reset by the BOD33. */
SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33,
/** The system was last reset by the BOD12. */
SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12,
/** The system was last reset by the POR (Power on reset). */
SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR,
};
/**
* \name System identification
* @{
*/
/**
* \brief Retrieve the device identification signature
*
* Retrieves the signature of the current device.
*
* \return Device ID signature as a 32-bit integer.
*/
static inline uint32_t system_get_device_id(void)
{
return DSU->DID.reg;
}
/**
* @}
*/
/**
* \name Voltage references
* @{
*/
/**
* \brief Enable the selected voltage reference
*
* Enables the selected voltage reference source, making the voltage reference
* available on a pin as well as an input source to the analog peripherals.
*
* \param[in] vref Voltage reference to enable
*/
static inline void system_voltage_reference_enable(
const enum system_voltage_reference vref)
{
switch (vref) {
case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN;
break;
case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN;
break;
default:
Assert(false);
return;
}
}
/**
* \brief Disable the selected voltage reference
*
* Disables the selected voltage reference source.
*
* \param[in] vref Voltage reference to disable
*/
static inline void system_voltage_reference_disable(
const enum system_voltage_reference vref)
{
switch (vref) {
case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE:
SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN;
break;
case SYSTEM_VOLTAGE_REFERENCE_BANDGAP:
SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN;
break;
default:
Assert(false);
return;
}
}
/**
* @}
*/
/**
* \name Device sleep
* @{
*/
/**
* \brief Set the sleep mode of the device
*
* Sets the sleep mode of the device; the configured sleep mode will be entered
* upon the next call of the \ref system_sleep() function.
*
* For an overview of which systems are disabled in sleep for the different
* sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode.
*
* \param[in] sleep_mode Sleep mode to configure for the next sleep operation
*
* \retval STATUS_OK Operation completed successfully
* \retval STATUS_ERR_INVALID_ARG The requested sleep mode was invalid or not
* available
*/
static inline enum status_code system_set_sleepmode(
const enum system_sleepmode sleep_mode)
{
switch (sleep_mode) {
case SYSTEM_SLEEPMODE_IDLE_0:
case SYSTEM_SLEEPMODE_IDLE_1:
case SYSTEM_SLEEPMODE_IDLE_2:
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PM->SLEEP.reg = sleep_mode;
break;
case SYSTEM_SLEEPMODE_STANDBY:
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
break;
default:
return STATUS_ERR_INVALID_ARG;
}
return STATUS_OK;
}
/**
* \brief Put the system to sleep waiting for interrupt
*
* Executes a device DSB (Data Synchronization Barrier) instruction to ensure
* all ongoing memory accesses have completed, then a WFI (Wait For Interrupt)
* instruction to place the device into the sleep mode specified by
* \ref system_set_sleepmode until woken by an interrupt.
*/
static inline void system_sleep(void)
{
__DSB();
__WFI();
}
/**
* @}
*/
/**
* \name Reset control
* @{
*/
/**
* \brief Check if bugger is present
*
* Check if debugger is connected to the onboard debug system (DAP)
*
* \return A bool identifying if a debugger is present
*
* \retval true Debugger is connected to the system
* \retval false Debugger is not connected to the system
*
*/
static inline bool system_is_debugger_present(void)
{
return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES;
}
/**
* \brief Reset the MCU
*
* Resets the MCU and all associated peripherals and registers, except RTC, all 32kHz sources,
* WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
*
*/
static inline void system_reset(void)
{
NVIC_SystemReset();
}
/**
* \brief Return the reset cause
*
* Retrieves the cause of the last system reset.
*
* \return An enum value indicating the cause of the last system reset.
*/
static inline enum system_reset_cause system_get_reset_cause(void)
{
return (enum system_reset_cause)PM->RCAUSE.reg;
}
/**
* @}
*/
/**
* \name System initialization
* @{
*/
void system_init(void);
/**
* @}
*/
/**
* @}
*/
/**
* \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver
*
* \section asfdoc_sam0_system_extra_acronyms Acronyms
* Below is a table listing the acronyms used in this module, along with their
* intended meanings.
*
* <table>
* <tr>
* <th>Acronym</th>
* <th>Definition</th>
* </tr>
* <tr>
* <td>PM</td>
* <td>Power Manager</td>
* </tr>
* <tr>
* <td>SYSCTRL</td>
* <td>System control interface</td>
* </tr>
* </table>
*
*
* \section asfdoc_sam0_system_extra_dependencies Dependencies
* This driver has the following dependencies:
*
* - None
*
*
* \section asfdoc_sam0_system_extra_errata Errata
* There are no errata related to this driver.
*
*
* \section asfdoc_sam0_system_extra_history Module History
* An overview of the module history is presented in the table below, with
* details on the enhancements and fixes made to the module since its first
* release. The current version of this corresponds to the newest version in
* the table.
*
* <table>
* <tr>
* <th>Changelog</th>
* </tr>
* <tr>
* <td>Added support for SAMD21</td>
* </tr>
* <tr>
* <td>Added new \c system_reset() to reset the complete MCU with some exceptions</td>
* </tr>
* <tr>
* <td>Added new \c system_get_device_id() function to retrieved the device
* ID.</td>
* </tr>
* <tr>
* <td>Initial Release</td>
* </tr>
* </table>
*
* \page asfdoc_sam0_system_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>E</td>
* <td>04/2014</td>
* <td>Added support for SAMD10/D11.</td>
* </tr>
* <tr>
* <td>D</td>
* <td>02/2014</td>
* <td>Added support for SAMR21.</td>
* </tr>
* <tr>
* <td>C</td>
* <td>01/2014</td>
* <td>Added support for SAMD21.</td>
* </tr>
* <tr>
* <td>B</td>
* <td>06/2013</td>
* <td>Corrected documentation typos.</td>
* </tr>
* <tr>
* <td>A</td>
* <td>06/2013</td>
* <td>Initial release</td>
* </tr>
* </table>
*/
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_H_INCLUDED */

1242
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/usb/stack_interface/usb_device_udd.c Normal file
View file

File diff suppressed because it is too large Load diff

175
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/usb/stack_interface/usb_dual.c Normal file
View file

@ -0,0 +1,175 @@
/**
* \file
*
* \brief SAM USB Dual Role driver file.
*
* Copyright (C) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include <compiler.h>
#include "usb_dual.h"
#ifndef UDD_ENABLE
# define udc_start()
# define udc_stop()
#else
#include <udc.h>
#endif
#ifndef UHD_ENABLE
# define uhc_start(void)
# define uhc_stop(b_id_stop)
#else
#include <uhc.h>
#endif
/* State of USB dual role initialization */
static bool _initialized = false;
#define _usb_is_id_device() port_pin_get_input_level(USB_ID_PIN)
#if USB_ID_EIC
static void usb_id_handler(void);
/**
* \name USB ID PAD management
*
* @{
*/
/**
* USB ID pin configuration
*/
static void usb_id_config(void)
{
struct extint_chan_conf eint_chan_conf;
extint_chan_get_config_defaults(&eint_chan_conf);
eint_chan_conf.gpio_pin = USB_ID_PIN;
eint_chan_conf.gpio_pin_mux = USB_ID_EIC_MUX;
eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH;
eint_chan_conf.filter_input_signal = true;
extint_chan_disable_callback(USB_ID_EIC_LINE,
EXTINT_CALLBACK_TYPE_DETECT);
extint_chan_set_config(USB_ID_EIC_LINE, &eint_chan_conf);
extint_register_callback(usb_id_handler,
USB_ID_EIC_LINE,
EXTINT_CALLBACK_TYPE_DETECT);
extint_chan_enable_callback(USB_ID_EIC_LINE,
EXTINT_CALLBACK_TYPE_DETECT);
}
/**
* USB ID pin change handler
*/
static void usb_id_handler(void)
{
extint_chan_disable_callback(USB_ID_EIC_LINE,
EXTINT_CALLBACK_TYPE_DETECT);
if (_usb_is_id_device()) {
uhc_stop(false);
UHC_MODE_CHANGE(false);
udc_start();
} else {
udc_stop();
UHC_MODE_CHANGE(true);
uhc_start();
}
extint_chan_enable_callback(USB_ID_EIC_LINE,
EXTINT_CALLBACK_TYPE_DETECT);
}
#endif
/** @} */
/**
* \brief Initialize the USB peripheral and set right role according to ID pin
*
* \return \c true if the ID pin management has been started, otherwise \c false.
*/
bool usb_dual_enable(void)
{
if (_initialized) {
return false; // Dual role already initialized
}
#if USB_ID_EIC
_initialized = true;
struct port_config pin_conf;
port_get_config_defaults(&pin_conf);
/* Set USB ID Pin as inputs */
pin_conf.direction = PORT_PIN_DIR_INPUT;
pin_conf.input_pull = PORT_PIN_PULL_UP;
port_pin_set_config(USB_ID_PIN, &pin_conf);
usb_id_config();
if (_usb_is_id_device()) {
UHC_MODE_CHANGE(false);
udc_start();
} else {
UHC_MODE_CHANGE(true);
uhc_start();
}
/**
* End of host or device startup,
* the current mode selected is already started now
*/
return true; // ID pin management has been enabled
#else
return false; // ID pin management has not been enabled
#endif
}
/**
* \brief Deinitialize the dual role driver
*/
void usb_dual_disable(void)
{
if (!_initialized) {
return; // Dual role not initialized
}
_initialized = false;
#if USB_ID_EIC
extint_chan_disable_callback(USB_ID_EIC_LINE,
EXTINT_CALLBACK_TYPE_DETECT);
#endif
}

110
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/usb/stack_interface/usb_dual.h Normal file
View file

@ -0,0 +1,110 @@
/**
* \file
*
* \brief SAM USB Dual Role driver header file.
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _USB_DUAL_H_
#define _USB_DUAL_H_
#include "compiler.h"
#include "preprocessor.h"
/* Get USB pads pins configuration in board configuration */
#include "conf_board.h"
#include "board.h"
//#include <extint.h>
#include "port.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup usb_group
* \defgroup usb_dual_group USB dual role driver
* USB low-level driver for dual role features
*
* @{
*/
bool usb_dual_enable(void);
void usb_dual_disable(void);
/**
* @name USB ID pin management
*
* The ID pin come from the USB connector (A and B receptable) and
* allows to select the USB mode between host or device.
* The ID pin can be managed through EIC pin.
* This feature is optional, and it is enabled if USB_ID_PIN
* is defined in board.h and CONF_BOARD_USB_ID_DETECT defined in
* conf_board.h.
*
* @{
*/
#ifdef BOOTLOADER_USES_HOST
#define USB_ID_DETECT (defined(CONF_BOARD_USB_ID_DETECT))
#define USB_ID_EIC (defined(USB_ID_PIN) && USB_ID_DETECT)
/** @} */
/**
* @name USB Vbus management
*
* The VBus line can be monitored through a EIC pin and
* a basic resistor voltage divider.
* This feature is optional, and it is enabled if USB_VBUS_PIN
* is defined in board.h and CONF_BOARD_USB_VBUS_DETECT defined in
* conf_board.h.
*
* @{
*/
#define USB_VBUS_DETECT (defined(CONF_BOARD_USB_VBUS_DETECT))
#define USB_VBUS_EIC (defined(USB_VBUS_PIN) && USB_VBUS_DETECT)
#endif //BOOTLOADER_USES_HOST
/** @} */
/** @} */
#ifdef __cplusplus
}
#endif
#endif // _USB_DUAL_H_

2066
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/usb/usb.c Normal file
View file

File diff suppressed because it is too large Load diff

820
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/drivers/usb/usb.h Normal file
View file

@ -0,0 +1,820 @@
/**
* \file
*
* \brief SAM USB Driver
*
* Copyright (C) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef USB_H_INCLUDED
#define USB_H_INCLUDED
#include <compiler.h>
#include <clock.h>
#include <gclk.h>
#include <pinmux.h>
#include <system_interrupt.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup asfdoc_sam0_usb_group SAM Universal Serial Bus (USB)
*
* The Universal Serial Bus (USB) module complies with the USB 2.1 specification.
*
* The following peripherals are used by this module:
* - USB (Universal Serial Bus)
*
* The following devices can use this module:
* - SAM D21
* - SAM R21
* - SAM D11
*
* The USB module covers following mode:
* \if USB_DEVICE_MODE
* - USB Device Mode
* \endif
* \if USB_HOST_MODE
* - USB Host Mode
* \endif
*
* The USB module covers following speed:
* \if USB_HS_MODE
* - USB High Speed (480Mbit/s)
* \endif
* - USB Full Speed (12Mbit/s)
* \if USB_LS_MODE
* - USB Low Speed (1.5Mbit/s)
* \endif
*
* \if USB_LPM_MODE
* The USB module supports Link Power Management (LPM-L1) protocol.
* \endif
*
* USB support needs whole set of enumeration process, to make the device
* recognizable and usable. The USB driver is designed to interface to the
* USB Stack in Atmel Software Framework (ASF).
*
* \if USB_DEVICE_MODE
* \section asfdoc_sam0_usb_device USB Device Mode
* The ASF USB Device Stack has defined the USB Device Driver (UDD) interface,
* to support USB device operations. The USB module device driver complies with
* this interface, so that the USB Device Stack can work based on the
* USB module.
*
* Refer to <a href="http://www.atmel.com/images/doc8360.pdf">
* "ASF - USB Device Stack"</a> for more details.
* \endif
*
* \if USB_HOST_MODE
* \section adfdoc_sam0_usb_host USB Host Mode
* The ASF USB Host Stack has defined the USB Host Driver (UHD) interface,
* to support USB host operations. The USB module host driver complies with
* this interface, so that the USB Host Stack can work based on the USB module.
*
* Refer to <a href="http://www.atmel.com/images/doc8486.pdf">
* "ASF - USB Host Stack"</a> for more details.
* \endif
*/
/** Enum for the speed status for the USB module */
enum usb_speed {
USB_SPEED_LOW,
USB_SPEED_FULL,
};
/** Enum for the possible callback types for the USB in host module */
enum usb_host_callback {
USB_HOST_CALLBACK_SOF,
USB_HOST_CALLBACK_RESET,
USB_HOST_CALLBACK_WAKEUP,
USB_HOST_CALLBACK_DNRSM,
USB_HOST_CALLBACK_UPRSM,
USB_HOST_CALLBACK_RAMACER,
USB_HOST_CALLBACK_CONNECT,
USB_HOST_CALLBACK_DISCONNECT,
USB_HOST_CALLBACK_N,
};
/** Enum for the possible callback types for the USB pipe in host module */
enum usb_host_pipe_callback {
USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE,
USB_HOST_PIPE_CALLBACK_ERROR,
USB_HOST_PIPE_CALLBACK_SETUP,
USB_HOST_PIPE_CALLBACK_STALL,
USB_HOST_PIPE_CALLBACK_N,
};
/**
* \brief Host pipe types.
*/
enum usb_host_pipe_type {
USB_HOST_PIPE_TYPE_DISABLE,
USB_HOST_PIPE_TYPE_CONTROL,
USB_HOST_PIPE_TYPE_ISO,
USB_HOST_PIPE_TYPE_BULK,
USB_HOST_PIPE_TYPE_INTERRUPT,
USB_HOST_PIPE_TYPE_EXTENDED,
};
/**
* \brief Host pipe token types.
*/
enum usb_host_pipe_token {
USB_HOST_PIPE_TOKEN_SETUP,
USB_HOST_PIPE_TOKEN_IN,
USB_HOST_PIPE_TOKEN_OUT,
};
/**
* \brief Enumeration for the possible callback types for the USB in device module
*/
enum usb_device_callback {
USB_DEVICE_CALLBACK_SOF,
USB_DEVICE_CALLBACK_RESET,
USB_DEVICE_CALLBACK_WAKEUP,
USB_DEVICE_CALLBACK_RAMACER,
USB_DEVICE_CALLBACK_SUSPEND,
USB_DEVICE_CALLBACK_LPMNYET,
USB_DEVICE_CALLBACK_LPMSUSP,
USB_DEVICE_CALLBACK_N,
};
/**
* \brief Enumeration for the possible callback types for the USB endpoint in device module
*/
enum usb_device_endpoint_callback {
USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,
USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,
USB_DEVICE_ENDPOINT_CALLBACK_RXSTP,
USB_DEVICE_ENDPOINT_CALLBACK_STALL,
USB_DEVICE_EP_CALLBACK_N,
};
/**
* \brief Device Endpoint types.
*/
enum usb_device_endpoint_type {
USB_DEVICE_ENDPOINT_TYPE_DISABLE,
USB_DEVICE_ENDPOINT_TYPE_CONTROL,
USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS,
USB_DEVICE_ENDPOINT_TYPE_BULK,
USB_DEVICE_ENDPOINT_TYPE_INTERRUPT,
};
/**
* \brief Endpoint Size
*/
enum usb_endpoint_size {
USB_ENDPOINT_8_BYTE,
USB_ENDPOINT_16_BYTE,
USB_ENDPOINT_32_BYTE,
USB_ENDPOINT_64_BYTE,
USB_ENDPOINT_128_BYTE,
USB_ENDPOINT_256_BYTE,
USB_ENDPOINT_512_BYTE,
USB_ENDPOINT_1023_BYTE,
};
/**
* \brief Link Power Management Handshake.
*/
enum usb_device_lpm_mode {
USB_DEVICE_LPM_NOT_SUPPORT,
USB_DEVICE_LPM_ACK,
USB_DEVICE_LPM_NYET,
};
/**
* \brief Module structure
*/
struct usb_module;
/**
* \name Host callback functions types
* @{
*/
typedef void (*usb_host_callback_t)(struct usb_module *module_inst);
typedef void (*usb_host_pipe_callback_t)(struct usb_module *module_inst, void *);
/** @} */
/**
* \name Device callback functions types
* @{
*/
typedef void (*usb_device_callback_t)(struct usb_module *module_inst, void* pointer);
typedef void (*usb_device_endpoint_callback_t)(struct usb_module *module_inst, void* pointer);
/** @} */
/** USB configurations */
struct usb_config {
/** \c true for host, \c false for device. */
bool select_host_mode;
/** When \c true the module is enabled during standby. */
bool run_in_standby;
/** Generic Clock Generator source channel. */
enum gclk_generator source_generator;
/** Speed mode */
enum usb_speed speed_mode;
};
/**
* \brief USB software module instance structure.
*
* USB software module instance structure, used to retain software state
* information of an associated hardware module instance.
*
*/
struct usb_module {
/** Hardware module pointer of the associated USB peripheral. */
Usb *hw;
/** Array to store host related callback functions */
usb_host_callback_t host_callback[USB_HOST_CALLBACK_N];
usb_host_pipe_callback_t host_pipe_callback[USB_PIPE_NUM][USB_HOST_PIPE_CALLBACK_N];
/** Bit mask for host callbacks registered */
uint8_t host_registered_callback_mask;
/** Bit mask for host callbacks enabled */
uint8_t host_enabled_callback_mask;
/** Bit mask for host pipe callbacks registered */
uint8_t host_pipe_registered_callback_mask[USB_PIPE_NUM];
/** Bit mask for host pipe callbacks enabled */
uint8_t host_pipe_enabled_callback_mask[USB_PIPE_NUM];
/** Array to store device related callback functions */
usb_device_callback_t device_callback[USB_DEVICE_CALLBACK_N];
usb_device_endpoint_callback_t device_endpoint_callback[USB_EPT_NUM][USB_DEVICE_EP_CALLBACK_N];
/** Bit mask for device callbacks registered */
uint16_t device_registered_callback_mask;
/** Bit mask for device callbacks enabled */
uint16_t device_enabled_callback_mask;
/** Bit mask for device endpoint callbacks registered */
uint8_t deivce_endpoint_registered_callback_mask[USB_EPT_NUM];
/** Bit mask for device endpoint callbacks enabled */
uint8_t device_endpoint_enabled_callback_mask[USB_EPT_NUM];
};
/** USB host pipe configurations */
struct usb_host_pipe_config {
/** device address */
uint8_t device_address;
/** endpoint address */
uint8_t endpoint_address;
/** Pipe type */
enum usb_host_pipe_type pipe_type;
/** interval */
uint8_t binterval;
/** pipe size */
uint16_t size;
};
/** USB device endpoint configurations */
struct usb_device_endpoint_config {
/** device address */
uint8_t ep_address;
/** endpoint size */
enum usb_endpoint_size ep_size;
/** automatic zero length packet mode, \c true to enable */
bool auto_zlp;
/** type of endpoint with Bank */
enum usb_device_endpoint_type ep_type;
};
/** USB host pipe callback status parameter structure */
struct usb_pipe_callback_parameter {
/** current pipe number */
uint8_t pipe_num;
/** pipe error status */
uint8_t pipe_error_status;
/** actual transferred data size */
uint16_t transfered_size;
/** required data size */
uint16_t required_size;
};
/** USB device endpoint callback status parameter structure */
struct usb_endpoint_callback_parameter {
uint16_t received_bytes;
uint16_t sent_bytes;
uint16_t out_buffer_size;
uint8_t endpoint_address;
};
void usb_enable(struct usb_module *module_inst);
void usb_disable(struct usb_module *module_inst);
/**
* \brief Get the status of USB module's state machine
*
* \param module_inst Pointer to USB module instance
*/
static inline uint8_t usb_get_state_machine_status(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
return module_inst->hw->HOST.FSMSTATUS.reg;
}
void usb_get_config_defaults(struct usb_config *module_config);
enum status_code usb_init(struct usb_module *module_inst, Usb *const hw,
struct usb_config *module_config);
/**
* \brief Enable the USB host by setting the VBUS OK
*
* \param module_inst Pointer to USB software instance struct
*/
static inline void usb_host_enable(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.CTRLB.bit.VBUSOK = 1;
}
/**
* \brief Send the USB reset
*
* \param module_inst Pointer to USB software instance struct
*/
static inline void usb_host_send_reset(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.CTRLB.bit.BUSRESET = 1;
}
/**
* \brief Enable the USB SOF generation
*
* \param module_inst Pointer to USB software instance struct
*/
static inline void usb_host_enable_sof(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.CTRLB.bit.SOFE = 1;
}
/**
* \brief Disable the USB SOF generation
*
* \param module_inst Pointer to USB software instance struct
*/
static inline void usb_host_disable_sof(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.CTRLB.bit.SOFE = 0;
}
/**
* \brief Check the USB SOF generation status
*
* \param module_inst Pointer to USB software instance struct
*
* \return USB SOF generation status, \c true if SOF generation is ON.
*/
static inline bool usb_host_is_sof_enabled(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
return module_inst->hw->HOST.CTRLB.bit.SOFE;
}
/**
* \brief Send the USB host resume
*
* \param module_inst Pointer to USB software instance struct
*/
static inline void usb_host_send_resume(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.CTRLB.bit.RESUME= 1;
}
/**
* \brief Send the USB host LPM resume
*
* \param module_inst Pointer to USB software instance struct
*/
static inline void usb_host_send_l1_resume(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.CTRLB.bit.L1RESUME = 1;
}
/**
* \brief Get the speed mode of USB host
*
* \param module_inst Pointer to USB module instance struct
*
* \return USB speed mode (\ref usb_speed)
*/
static inline enum usb_speed usb_host_get_speed(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
if (module_inst->hw->HOST.STATUS.bit.SPEED == 0) {
return USB_SPEED_FULL;
} else {
return USB_SPEED_LOW;
}
}
/**
* \brief Get the frame number
*
* \param module_inst Pointer to USB software instance struct
*
* \return frame number value
*/
static inline uint16_t usb_host_get_frame_number(struct usb_module *module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
return (uint16_t)(module_inst->hw->HOST.FNUM.bit.FNUM);
}
/**
* \brief Attach USB device to the bus
*
* \param module_inst Pointer to USB device module instance
*/
static inline void usb_device_attach(struct usb_module *module_inst)
{
module_inst->hw->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH;
}
/**
* \brief Detach USB device from the bus
*
* \param module_inst Pointer to USB device module instance
*/
static inline void usb_device_detach(struct usb_module *module_inst)
{
module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH;
}
/**
* \brief Get the speed mode of USB device
*
* \param module_inst Pointer to USB device module instance
* \return USB Speed mode (\ref usb_speed)
*/
static inline enum usb_speed usb_device_get_speed(struct usb_module *module_inst)
{
if (!(module_inst->hw->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk)) {
return USB_SPEED_FULL;
} else {
return USB_SPEED_LOW;
}
}
/**
* \brief Get the address of USB device
*
* \param module_inst Pointer to USB device module instance
* \return USB device address value
*/
static inline uint8_t usb_device_get_address(struct usb_module *module_inst)
{
return ((uint8_t)(module_inst->hw->DEVICE.DADD.bit.DADD));
}
/**
* \brief Set the speed mode of USB device
*
* \param module_inst Pointer to USB device module instance
* \param address USB device address value
*/
static inline void usb_device_set_address(struct usb_module *module_inst, uint8_t address)
{
module_inst->hw->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | address;
}
/**
* \brief Get the frame number of USB device
*
* \param module_inst Pointer to USB device module instance
* \return USB device frame number value
*/
static inline uint16_t usb_device_get_frame_number(struct usb_module *module_inst)
{
return ((uint16_t)(module_inst->hw->DEVICE.FNUM.bit.FNUM));
}
/**
* \brief Get the micro-frame number of USB device
*
* \param module_inst Pointer to USB device module instance
* \return USB device micro-frame number value
*/
static inline uint16_t usb_device_get_micro_frame_number(struct usb_module *module_inst)
{
return ((uint16_t)(module_inst->hw->DEVICE.FNUM.reg));
}
/**
* \brief USB device send the resume wakeup
*
* \param module_inst Pointer to USB device module instance
*/
static inline void usb_device_send_remote_wake_up(struct usb_module *module_inst)
{
module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM;
}
/**
* \brief USB device set the LPM mode
*
* \param module_inst Pointer to USB device module instance
* \param lpm_mode LPM mode
*/
static inline void usb_device_set_lpm_mode(struct usb_module *module_inst,
enum usb_device_lpm_mode lpm_mode)
{
module_inst->hw->DEVICE.CTRLB.bit.LPMHDSK = lpm_mode;
}
/**
* \name USB Host Callback management
* @{
*/
enum status_code usb_host_register_callback(struct usb_module *module_inst,
enum usb_host_callback callback_type,
usb_host_callback_t callback_func);
enum status_code usb_host_unregister_callback(struct usb_module *module_inst,
enum usb_host_callback callback_type);
enum status_code usb_host_enable_callback(struct usb_module *module_inst,
enum usb_host_callback callback_type);
enum status_code usb_host_disable_callback(struct usb_module *module_inst,
enum usb_host_callback callback_type);
/** @} */
/**
* \name USB Device Callback management
* @{
*/
enum status_code usb_device_register_callback(struct usb_module *module_inst,
enum usb_device_callback callback_type,
usb_device_callback_t callback_func);
enum status_code usb_device_unregister_callback(struct usb_module *module_inst,
enum usb_device_callback callback_type);
enum status_code usb_device_enable_callback(struct usb_module *module_inst,
enum usb_device_callback callback_type);
enum status_code usb_device_disable_callback(struct usb_module *module_inst,
enum usb_device_callback callback_type);
/** @} */
/**
* \name USB Host Pipe configuration
* @{
*/
void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config);
enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num,
struct usb_host_pipe_config *ep_config);
enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num,
struct usb_host_pipe_config *ep_config);
/** @} */
/**
* \name USB Device Endpoint Configuration
* @{
*/
void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config);
enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst,
struct usb_device_endpoint_config *ep_config);
bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep);
/** @} */
/**
* \name USB Host Pipe Callback management
* @{
*/
enum status_code usb_host_pipe_register_callback(
struct usb_module *module_inst, uint8_t pipe_num,
enum usb_host_pipe_callback callback_type,
usb_host_pipe_callback_t callback_func);
enum status_code usb_host_pipe_unregister_callback(
struct usb_module *module_inst, uint8_t pipe_num,
enum usb_host_pipe_callback callback_type);
enum status_code usb_host_pipe_enable_callback(
struct usb_module *module_inst, uint8_t pipe_num,
enum usb_host_pipe_callback callback_type);
enum status_code usb_host_pipe_disable_callback(
struct usb_module *module_inst, uint8_t pipe_num,
enum usb_host_pipe_callback callback_type);
/** @} */
/**
* \name USB Device Endpoint Callback management
* @{
*/
enum status_code usb_device_endpoint_register_callback(
struct usb_module *module_inst, uint8_t ep_num,
enum usb_device_endpoint_callback callback_type,
usb_device_endpoint_callback_t callback_func);
enum status_code usb_device_endpoint_unregister_callback(
struct usb_module *module_inst, uint8_t ep_num,
enum usb_device_endpoint_callback callback_type);
enum status_code usb_device_endpoint_enable_callback(
struct usb_module *module_inst, uint8_t ep,
enum usb_device_endpoint_callback callback_type);
enum status_code usb_device_endpoint_disable_callback(
struct usb_module *module_inst, uint8_t ep,
enum usb_device_endpoint_callback callback_type);
/** @} */
/**
* \name USB Host Pipe Job management
* @{
*/
enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst,
uint8_t pipe_num, uint8_t *buf);
enum status_code usb_host_pipe_read_job(struct usb_module *module_inst,
uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
enum status_code usb_host_pipe_write_job(struct usb_module *module_inst,
uint8_t pipe_num, uint8_t *buf, uint32_t buf_size);
enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num);
enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst,
uint8_t pipe_num, bool b_remotewakeup, uint8_t besl);
/** @} */
/**
* \name USB Device Endpoint Job management
* @{
*/
enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
uint8_t* pbuf, uint32_t buf_size);
enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num,
uint8_t* pbuf, uint32_t buf_size);
enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst,
uint8_t* pbuf);
void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep);
/** @} */
/**
* \name USB Host Pipe Operations
* @{
*/
/**
* \brief Freeze a pipe
*
* \param module_inst Pointer to USB module instance
* \param pipe_num Pipe number
*/
static inline void usb_host_pipe_freeze(struct usb_module *module_inst, uint8_t pipe_num)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE;
}
/**
* \brief Unfreeze a pipe
*
* \param module_inst Pointer to USB module instance
* \param pipe_num Pipe number
*/
static inline void usb_host_pipe_unfreeze(struct usb_module *module_inst, uint8_t pipe_num)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE;
}
/**
* \brief Check if the pipe is frozen
*
* \param module_inst Pointer to USB module instance
* \param pipe_num Pipe number
*/
static inline bool usb_host_pipe_is_frozen(struct usb_module *module_inst, uint8_t pipe_num)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
return (module_inst->hw->HOST.HostPipe[pipe_num].PSTATUS.bit.PFREEZE == 1);
}
/**
* \brief Set the data toggle bit of pipe
*
* \param module_inst Pointer to USB module instance
* \param pipe_num Pipe number
*/
static inline void usb_host_pipe_set_toggle(struct usb_module *module_inst, uint8_t pipe_num)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_DTGL;
}
/**
* \brief Clear the data toggle bit of pipe
*
* \param module_inst Pointer to USB module instance
* \param pipe_num Pipe number
*/
static inline void usb_host_pipe_clear_toggle(struct usb_module *module_inst, uint8_t pipe_num)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL;
}
/**
* \brief Set the auto zero length packet of pipe
*
* \param module_inst Pointer to USB module instance
* \param pipe_num Pipe number
* \param value \c true to enable auto ZLP and \c false to disable
*/
void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value);
/** @} */
/**
* \name USB Device Endpoint Operations
* @{
*/
bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep);
void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep);
void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* USB_H_INCLUDED */

559
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/ac.h Normal file
View file

@ -0,0 +1,559 @@
/**
* \file
*
* \brief Component description for AC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_AC_COMPONENT_
#define _SAMD21_AC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR AC */
/* ========================================================================== */
/** \addtogroup SAMD21_AC Analog Comparators */
/*@{*/
#define AC_U2205
#define REV_AC 0x111
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
#define AC_CTRLA_RESETVALUE 0x00 /**< \brief (AC_CTRLA reset_value) Control A */
#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
#define AC_CTRLA_SWRST (0x1u << AC_CTRLA_SWRST_Pos)
#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
#define AC_CTRLA_ENABLE (0x1u << AC_CTRLA_ENABLE_Pos)
#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */
#define AC_CTRLA_RUNSTDBY_Msk (0x1u << AC_CTRLA_RUNSTDBY_Pos)
#define AC_CTRLA_RUNSTDBY(value) ((AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)))
#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */
#define AC_CTRLA_LPMUX (0x1u << AC_CTRLA_LPMUX_Pos)
#define AC_CTRLA_MASK 0x87u /**< \brief (AC_CTRLA) MASK Register */
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
#define AC_CTRLB_RESETVALUE 0x00 /**< \brief (AC_CTRLB reset_value) Control B */
#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos)
#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos)
#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
#define AC_CTRLB_START_Msk (0x3u << AC_CTRLB_START_Pos)
#define AC_CTRLB_START(value) ((AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)))
#define AC_CTRLB_MASK 0x03u /**< \brief (AC_CTRLB) MASK Register */
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
#define AC_EVCTRL_RESETVALUE 0x0000 /**< \brief (AC_EVCTRL reset_value) Event Control */
#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos)
#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos)
#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
#define AC_EVCTRL_COMPEO_Msk (0x3u << AC_EVCTRL_COMPEO_Pos)
#define AC_EVCTRL_COMPEO(value) ((AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)))
#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos)
#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
#define AC_EVCTRL_WINEO_Msk (0x1u << AC_EVCTRL_WINEO_Pos)
#define AC_EVCTRL_WINEO(value) ((AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)))
#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */
#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos)
#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */
#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos)
#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */
#define AC_EVCTRL_COMPEI_Msk (0x3u << AC_EVCTRL_COMPEI_Pos)
#define AC_EVCTRL_COMPEI(value) ((AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)))
#define AC_EVCTRL_MASK 0x0313u /**< \brief (AC_EVCTRL) MASK Register */
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
#define AC_INTENCLR_RESETVALUE 0x00 /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos)
#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos)
#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
#define AC_INTENCLR_COMP_Msk (0x3u << AC_INTENCLR_COMP_Pos)
#define AC_INTENCLR_COMP(value) ((AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)))
#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos)
#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
#define AC_INTENCLR_WIN_Msk (0x1u << AC_INTENCLR_WIN_Pos)
#define AC_INTENCLR_WIN(value) ((AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)))
#define AC_INTENCLR_MASK 0x13u /**< \brief (AC_INTENCLR) MASK Register */
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
#define AC_INTENSET_RESETVALUE 0x00 /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos)
#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos)
#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
#define AC_INTENSET_COMP_Msk (0x3u << AC_INTENSET_COMP_Pos)
#define AC_INTENSET_COMP(value) ((AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)))
#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos)
#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
#define AC_INTENSET_WIN_Msk (0x1u << AC_INTENSET_WIN_Pos)
#define AC_INTENSET_WIN(value) ((AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)))
#define AC_INTENSET_MASK 0x13u /**< \brief (AC_INTENSET) MASK Register */
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
#define AC_INTFLAG_RESETVALUE 0x00 /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos)
#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos)
#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
#define AC_INTFLAG_COMP_Msk (0x3u << AC_INTFLAG_COMP_Pos)
#define AC_INTFLAG_COMP(value) ((AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)))
#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos)
#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
#define AC_INTFLAG_WIN_Msk (0x1u << AC_INTFLAG_WIN_Pos)
#define AC_INTFLAG_WIN(value) ((AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)))
#define AC_INTFLAG_MASK 0x13u /**< \brief (AC_INTFLAG) MASK Register */
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */
#define AC_STATUSA_RESETVALUE 0x00 /**< \brief (AC_STATUSA reset_value) Status A */
#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos)
#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos)
#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
#define AC_STATUSA_STATE_Msk (0x3u << AC_STATUSA_STATE_Pos)
#define AC_STATUSA_STATE(value) ((AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)))
#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
#define AC_STATUSA_WSTATE0_Msk (0x3u << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE0(value) ((AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)))
#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0u /**< \brief (AC_STATUSA) Signal is above window */
#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1u /**< \brief (AC_STATUSA) Signal is inside window */
#define AC_STATUSA_WSTATE0_BELOW_Val 0x2u /**< \brief (AC_STATUSA) Signal is below window */
#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_MASK 0x33u /**< \brief (AC_STATUSA) MASK Register */
/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
uint8_t :5; /*!< bit: 2.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */
#define AC_STATUSB_RESETVALUE 0x00 /**< \brief (AC_STATUSB reset_value) Status B */
#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos)
#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos)
#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
#define AC_STATUSB_READY_Msk (0x3u << AC_STATUSB_READY_Pos)
#define AC_STATUSB_READY(value) ((AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)))
#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */
#define AC_STATUSB_SYNCBUSY (0x1u << AC_STATUSB_SYNCBUSY_Pos)
#define AC_STATUSB_MASK 0x83u /**< \brief (AC_STATUSB) MASK Register */
/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */
#define AC_STATUSC_RESETVALUE 0x00 /**< \brief (AC_STATUSC reset_value) Status C */
#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */
#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos)
#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */
#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos)
#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */
#define AC_STATUSC_STATE_Msk (0x3u << AC_STATUSC_STATE_Pos)
#define AC_STATUSC_STATE(value) ((AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)))
#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */
#define AC_STATUSC_WSTATE0_Msk (0x3u << AC_STATUSC_WSTATE0_Pos)
#define AC_STATUSC_WSTATE0(value) ((AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)))
#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0u /**< \brief (AC_STATUSC) Signal is above window */
#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1u /**< \brief (AC_STATUSC) Signal is inside window */
#define AC_STATUSC_WSTATE0_BELOW_Val 0x2u /**< \brief (AC_STATUSC) Signal is below window */
#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos)
#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos)
#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos)
#define AC_STATUSC_MASK 0x33u /**< \brief (AC_STATUSC) MASK Register */
/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */
#define AC_WINCTRL_RESETVALUE 0x00 /**< \brief (AC_WINCTRL reset_value) Window Control */
#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
#define AC_WINCTRL_WEN0 (0x1u << AC_WINCTRL_WEN0_Pos)
#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
#define AC_WINCTRL_WINTSEL0_Msk (0x3u << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0(value) ((AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)))
#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0u /**< \brief (AC_WINCTRL) Interrupt on signal above window */
#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1u /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2u /**< \brief (AC_WINCTRL) Interrupt on signal below window */
#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3u /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_MASK 0x07u /**< \brief (AC_WINCTRL) MASK Register */
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /*!< bit: 0 Enable */
uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
uint32_t :1; /*!< bit: 4 Reserved */
uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
uint32_t :1; /*!< bit: 14 Reserved */
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
uint32_t OUT:2; /*!< bit: 16..17 Output */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
#define AC_COMPCTRL_RESETVALUE 0x00000000 /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */
#define AC_COMPCTRL_ENABLE (0x1u << AC_COMPCTRL_ENABLE_Pos)
#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
#define AC_COMPCTRL_SINGLE (0x1u << AC_COMPCTRL_SINGLE_Pos)
#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */
#define AC_COMPCTRL_SPEED_Msk (0x3u << AC_COMPCTRL_SPEED_Pos)
#define AC_COMPCTRL_SPEED(value) ((AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)))
#define AC_COMPCTRL_SPEED_LOW_Val 0x0u /**< \brief (AC_COMPCTRL) Low speed */
#define AC_COMPCTRL_SPEED_HIGH_Val 0x1u /**< \brief (AC_COMPCTRL) High speed */
#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */
#define AC_COMPCTRL_INTSEL_Msk (0x3u << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL(value) ((AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)))
#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0u /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
#define AC_COMPCTRL_INTSEL_RISING_Val 0x1u /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2u /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
#define AC_COMPCTRL_INTSEL_EOC_Val 0x3u /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
#define AC_COMPCTRL_MUXNEG_Msk (0x7u << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG(value) ((AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)))
#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0u /**< \brief (AC_COMPCTRL) I/O pin 0 */
#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1u /**< \brief (AC_COMPCTRL) I/O pin 1 */
#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2u /**< \brief (AC_COMPCTRL) I/O pin 2 */
#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3u /**< \brief (AC_COMPCTRL) I/O pin 3 */
#define AC_COMPCTRL_MUXNEG_GND_Val 0x4u /**< \brief (AC_COMPCTRL) Ground */
#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5u /**< \brief (AC_COMPCTRL) VDD scaler */
#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6u /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7u /**< \brief (AC_COMPCTRL) DAC output */
#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
#define AC_COMPCTRL_MUXPOS_Msk (0x3u << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS(value) ((AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)))
#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0u /**< \brief (AC_COMPCTRL) I/O pin 0 */
#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1u /**< \brief (AC_COMPCTRL) I/O pin 1 */
#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2u /**< \brief (AC_COMPCTRL) I/O pin 2 */
#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3u /**< \brief (AC_COMPCTRL) I/O pin 3 */
#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
#define AC_COMPCTRL_SWAP (0x1u << AC_COMPCTRL_SWAP_Pos)
#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */
#define AC_COMPCTRL_OUT_Msk (0x3u << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_OUT(value) ((AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)))
#define AC_COMPCTRL_OUT_OFF_Val 0x0u /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_ASYNC_Val 0x1u /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_SYNC_Val 0x2u /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
#define AC_COMPCTRL_HYST (0x1u << AC_COMPCTRL_HYST_Pos)
#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
#define AC_COMPCTRL_FLEN_Msk (0x7u << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_FLEN(value) ((AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)))
#define AC_COMPCTRL_FLEN_OFF_Val 0x0u /**< \brief (AC_COMPCTRL) No filtering */
#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1u /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2u /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_MASK 0x070BB76Fu /**< \brief (AC_COMPCTRL) MASK Register */
/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */
#define AC_SCALER_RESETVALUE 0x00 /**< \brief (AC_SCALER reset_value) Scaler n */
#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
#define AC_SCALER_VALUE_Msk (0x3Fu << AC_SCALER_VALUE_Pos)
#define AC_SCALER_VALUE(value) ((AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)))
#define AC_SCALER_MASK 0x3Fu /**< \brief (AC_SCALER) MASK Register */
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
__I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
RoReg8 Reserved2[0x1];
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
RoReg8 Reserved3[0x3];
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
RoReg8 Reserved4[0x8];
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_AC_COMPONENT_ */

699
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/adc.h Normal file
View file

@ -0,0 +1,699 @@
/**
* \file
*
* \brief Component description for ADC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_ADC_COMPONENT_
#define _SAMD21_ADC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR ADC */
/* ========================================================================== */
/** \addtogroup SAMD21_ADC Analog Digital Converter */
/*@{*/
#define ADC_U2204
#define REV_ADC 0x120
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
#define ADC_CTRLA_RESETVALUE 0x00 /**< \brief (ADC_CTRLA reset_value) Control A */
#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
#define ADC_CTRLA_SWRST (0x1u << ADC_CTRLA_SWRST_Pos)
#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
#define ADC_CTRLA_ENABLE (0x1u << ADC_CTRLA_ENABLE_Pos)
#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */
#define ADC_CTRLA_RUNSTDBY (0x1u << ADC_CTRLA_RUNSTDBY_Pos)
#define ADC_CTRLA_MASK 0x07u /**< \brief (ADC_CTRLA) MASK Register */
/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */
#define ADC_REFCTRL_RESETVALUE 0x00 /**< \brief (ADC_REFCTRL reset_value) Reference Control */
#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
#define ADC_REFCTRL_REFSEL_Msk (0xFu << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)))
#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0u /**< \brief (ADC_REFCTRL) 1.0V voltage reference */
#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1u /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */
#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2u /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */
#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3u /**< \brief (ADC_REFCTRL) External reference */
#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4u /**< \brief (ADC_REFCTRL) External reference */
#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
#define ADC_REFCTRL_REFCOMP (0x1u << ADC_REFCTRL_REFCOMP_Pos)
#define ADC_REFCTRL_MASK 0x8Fu /**< \brief (ADC_REFCTRL) MASK Register */
/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */
#define ADC_AVGCTRL_RESETVALUE 0x00 /**< \brief (ADC_AVGCTRL reset_value) Average Control */
#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFu << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)))
#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0u /**< \brief (ADC_AVGCTRL) 1 sample */
#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1u /**< \brief (ADC_AVGCTRL) 2 samples */
#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2u /**< \brief (ADC_AVGCTRL) 4 samples */
#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3u /**< \brief (ADC_AVGCTRL) 8 samples */
#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4u /**< \brief (ADC_AVGCTRL) 16 samples */
#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5u /**< \brief (ADC_AVGCTRL) 32 samples */
#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6u /**< \brief (ADC_AVGCTRL) 64 samples */
#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7u /**< \brief (ADC_AVGCTRL) 128 samples */
#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8u /**< \brief (ADC_AVGCTRL) 256 samples */
#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9u /**< \brief (ADC_AVGCTRL) 512 samples */
#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAu /**< \brief (ADC_AVGCTRL) 1024 samples */
#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
#define ADC_AVGCTRL_ADJRES_Msk (0x7u << ADC_AVGCTRL_ADJRES_Pos)
#define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)))
#define ADC_AVGCTRL_MASK 0x7Fu /**< \brief (ADC_AVGCTRL) MASK Register */
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */
#define ADC_SAMPCTRL_RESETVALUE 0x00 /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */
#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Fu << ADC_SAMPCTRL_SAMPLEN_Pos)
#define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)))
#define ADC_SAMPCTRL_MASK 0x3Fu /**< \brief (ADC_SAMPCTRL) MASK Register */
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */
#define ADC_CTRLB_RESETVALUE 0x0000 /**< \brief (ADC_CTRLB reset_value) Control B */
#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */
#define ADC_CTRLB_DIFFMODE (0x1u << ADC_CTRLB_DIFFMODE_Pos)
#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */
#define ADC_CTRLB_LEFTADJ (0x1u << ADC_CTRLB_LEFTADJ_Pos)
#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */
#define ADC_CTRLB_FREERUN (0x1u << ADC_CTRLB_FREERUN_Pos)
#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */
#define ADC_CTRLB_CORREN (0x1u << ADC_CTRLB_CORREN_Pos)
#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */
#define ADC_CTRLB_RESSEL_Msk (0x3u << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)))
#define ADC_CTRLB_RESSEL_12BIT_Val 0x0u /**< \brief (ADC_CTRLB) 12-bit result */
#define ADC_CTRLB_RESSEL_16BIT_Val 0x1u /**< \brief (ADC_CTRLB) For averaging mode output */
#define ADC_CTRLB_RESSEL_10BIT_Val 0x2u /**< \brief (ADC_CTRLB) 10-bit result */
#define ADC_CTRLB_RESSEL_8BIT_Val 0x3u /**< \brief (ADC_CTRLB) 8-bit result */
#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)
#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */
#define ADC_CTRLB_PRESCALER_Msk (0x7u << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)))
#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0u /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1u /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2u /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
#define ADC_CTRLB_PRESCALER_DIV32_Val 0x3u /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
#define ADC_CTRLB_PRESCALER_DIV64_Val 0x4u /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
#define ADC_CTRLB_PRESCALER_DIV128_Val 0x5u /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
#define ADC_CTRLB_PRESCALER_DIV256_Val 0x6u /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
#define ADC_CTRLB_PRESCALER_DIV512_Val 0x7u /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */
#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_MASK 0x073Fu /**< \brief (ADC_CTRLB) MASK Register */
/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */
#define ADC_WINCTRL_RESETVALUE 0x00 /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */
#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */
#define ADC_WINCTRL_WINMODE_Msk (0x7u << ADC_WINCTRL_WINMODE_Pos)
#define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)))
#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0u /**< \brief (ADC_WINCTRL) No window mode (default) */
#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1u /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */
#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2u /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */
#define ADC_WINCTRL_WINMODE_MODE3_Val 0x3u /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */
#define ADC_WINCTRL_WINMODE_MODE4_Val 0x4u /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */
#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos)
#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos)
#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos)
#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos)
#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos)
#define ADC_WINCTRL_MASK 0x07u /**< \brief (ADC_WINCTRL) MASK Register */
/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */
#define ADC_SWTRIG_RESETVALUE 0x00 /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */
#define ADC_SWTRIG_FLUSH (0x1u << ADC_SWTRIG_FLUSH_Pos)
#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */
#define ADC_SWTRIG_START (0x1u << ADC_SWTRIG_START_Pos)
#define ADC_SWTRIG_MASK 0x03u /**< \brief (ADC_SWTRIG) MASK Register */
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */
#define ADC_INPUTCTRL_RESETVALUE 0x00000000 /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Fu << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)))
#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0u /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1u /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2u /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3u /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4u /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5u /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6u /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7u /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8u /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9u /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAu /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBu /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCu /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDu /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEu /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFu /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10u /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11u /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12u /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */
#define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13u /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */
#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18u /**< \brief (ADC_INPUTCTRL) Temperature Reference */
#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19u /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Au /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bu /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cu /**< \brief (ADC_INPUTCTRL) DAC Output */
#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Fu << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)))
#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0u /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1u /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2u /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
#define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3u /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
#define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4u /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
#define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5u /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
#define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6u /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
#define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7u /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
#define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18u /**< \brief (ADC_INPUTCTRL) Internal Ground */
#define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19u /**< \brief (ADC_INPUTCTRL) I/O Ground */
#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */
#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFu << ADC_INPUTCTRL_INPUTSCAN_Pos)
#define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)))
#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */
#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFu << ADC_INPUTCTRL_INPUTOFFSET_Pos)
#define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)))
#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */
#define ADC_INPUTCTRL_GAIN_Msk (0xFu << ADC_INPUTCTRL_GAIN_Pos)
#define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)))
#define ADC_INPUTCTRL_GAIN_1X_Val 0x0u /**< \brief (ADC_INPUTCTRL) 1x */
#define ADC_INPUTCTRL_GAIN_2X_Val 0x1u /**< \brief (ADC_INPUTCTRL) 2x */
#define ADC_INPUTCTRL_GAIN_4X_Val 0x2u /**< \brief (ADC_INPUTCTRL) 4x */
#define ADC_INPUTCTRL_GAIN_8X_Val 0x3u /**< \brief (ADC_INPUTCTRL) 8x */
#define ADC_INPUTCTRL_GAIN_16X_Val 0x4u /**< \brief (ADC_INPUTCTRL) 16x */
#define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFu /**< \brief (ADC_INPUTCTRL) 1/2x */
#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos)
#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos)
#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos)
#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos)
#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos)
#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos)
#define ADC_INPUTCTRL_MASK 0x0FFF1F1Fu /**< \brief (ADC_INPUTCTRL) MASK Register */
/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */
#define ADC_EVCTRL_RESETVALUE 0x00 /**< \brief (ADC_EVCTRL reset_value) Event Control */
#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */
#define ADC_EVCTRL_STARTEI (0x1u << ADC_EVCTRL_STARTEI_Pos)
#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */
#define ADC_EVCTRL_SYNCEI (0x1u << ADC_EVCTRL_SYNCEI_Pos)
#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
#define ADC_EVCTRL_RESRDYEO (0x1u << ADC_EVCTRL_RESRDYEO_Pos)
#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
#define ADC_EVCTRL_WINMONEO (0x1u << ADC_EVCTRL_WINMONEO_Pos)
#define ADC_EVCTRL_MASK 0x33u /**< \brief (ADC_EVCTRL) MASK Register */
/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
#define ADC_INTENCLR_RESETVALUE 0x00 /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */
#define ADC_INTENCLR_RESRDY (0x1u << ADC_INTENCLR_RESRDY_Pos)
#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */
#define ADC_INTENCLR_OVERRUN (0x1u << ADC_INTENCLR_OVERRUN_Pos)
#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */
#define ADC_INTENCLR_WINMON (0x1u << ADC_INTENCLR_WINMON_Pos)
#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */
#define ADC_INTENCLR_SYNCRDY (0x1u << ADC_INTENCLR_SYNCRDY_Pos)
#define ADC_INTENCLR_MASK 0x0Fu /**< \brief (ADC_INTENCLR) MASK Register */
/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
#define ADC_INTENSET_RESETVALUE 0x00 /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
#define ADC_INTENSET_RESRDY (0x1u << ADC_INTENSET_RESRDY_Pos)
#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
#define ADC_INTENSET_OVERRUN (0x1u << ADC_INTENSET_OVERRUN_Pos)
#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
#define ADC_INTENSET_WINMON (0x1u << ADC_INTENSET_WINMON_Pos)
#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */
#define ADC_INTENSET_SYNCRDY (0x1u << ADC_INTENSET_SYNCRDY_Pos)
#define ADC_INTENSET_MASK 0x0Fu /**< \brief (ADC_INTENSET) MASK Register */
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
#define ADC_INTFLAG_RESETVALUE 0x00 /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */
#define ADC_INTFLAG_RESRDY (0x1u << ADC_INTFLAG_RESRDY_Pos)
#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */
#define ADC_INTFLAG_OVERRUN (0x1u << ADC_INTFLAG_OVERRUN_Pos)
#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */
#define ADC_INTFLAG_WINMON (0x1u << ADC_INTFLAG_WINMON_Pos)
#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */
#define ADC_INTFLAG_SYNCRDY (0x1u << ADC_INTFLAG_SYNCRDY_Pos)
#define ADC_INTFLAG_MASK 0x0Fu /**< \brief (ADC_INTFLAG) MASK Register */
/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */
#define ADC_STATUS_RESETVALUE 0x00 /**< \brief (ADC_STATUS reset_value) Status */
#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */
#define ADC_STATUS_SYNCBUSY (0x1u << ADC_STATUS_SYNCBUSY_Pos)
#define ADC_STATUS_MASK 0x80u /**< \brief (ADC_STATUS) MASK Register */
/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */
#define ADC_RESULT_RESETVALUE 0x0000 /**< \brief (ADC_RESULT reset_value) Result */
#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */
#define ADC_RESULT_RESULT_Msk (0xFFFFu << ADC_RESULT_RESULT_Pos)
#define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)))
#define ADC_RESULT_MASK 0xFFFFu /**< \brief (ADC_RESULT) MASK Register */
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
#define ADC_WINLT_RESETVALUE 0x0000 /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
#define ADC_WINLT_WINLT_Msk (0xFFFFu << ADC_WINLT_WINLT_Pos)
#define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)))
#define ADC_WINLT_MASK 0xFFFFu /**< \brief (ADC_WINLT) MASK Register */
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
#define ADC_WINUT_RESETVALUE 0x0000 /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
#define ADC_WINUT_WINUT_Msk (0xFFFFu << ADC_WINUT_WINUT_Pos)
#define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)))
#define ADC_WINUT_MASK 0xFFFFu /**< \brief (ADC_WINUT) MASK Register */
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */
#define ADC_GAINCORR_RESETVALUE 0x0000 /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
#define ADC_GAINCORR_GAINCORR_Msk (0xFFFu << ADC_GAINCORR_GAINCORR_Pos)
#define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)))
#define ADC_GAINCORR_MASK 0x0FFFu /**< \brief (ADC_GAINCORR) MASK Register */
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
#define ADC_OFFSETCORR_RESETVALUE 0x0000 /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFu << ADC_OFFSETCORR_OFFSETCORR_Pos)
#define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)))
#define ADC_OFFSETCORR_MASK 0x0FFFu /**< \brief (ADC_OFFSETCORR) MASK Register */
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */
#define ADC_CALIB_RESETVALUE 0x0000 /**< \brief (ADC_CALIB reset_value) Calibration */
#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */
#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFu << ADC_CALIB_LINEARITY_CAL_Pos)
#define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)))
#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */
#define ADC_CALIB_BIAS_CAL_Msk (0x7u << ADC_CALIB_BIAS_CAL_Pos)
#define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)))
#define ADC_CALIB_MASK 0x07FFu /**< \brief (ADC_CALIB) MASK Register */
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */
#define ADC_DBGCTRL_RESETVALUE 0x00 /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
#define ADC_DBGCTRL_DBGRUN (0x1u << ADC_DBGCTRL_DBGRUN_Pos)
#define ADC_DBGCTRL_MASK 0x01u /**< \brief (ADC_DBGCTRL) MASK Register */
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
RoReg8 Reserved1[0x2];
__IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
RoReg8 Reserved2[0x3];
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
RoReg8 Reserved3[0x3];
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
RoReg8 Reserved4[0x1];
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
RoReg8 Reserved5[0x2];
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
RoReg8 Reserved6[0x2];
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_ADC_COMPONENT_ */

286
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/dac.h Normal file
View file

@ -0,0 +1,286 @@
/**
* \file
*
* \brief Component description for DAC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_DAC_COMPONENT_
#define _SAMD21_DAC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR DAC */
/* ========================================================================== */
/** \addtogroup SAMD21_DAC Digital Analog Converter */
/*@{*/
#define DAC_U2214
#define REV_DAC 0x110
/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
#define DAC_CTRLA_RESETVALUE 0x00 /**< \brief (DAC_CTRLA reset_value) Control A */
#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
#define DAC_CTRLA_SWRST (0x1u << DAC_CTRLA_SWRST_Pos)
#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
#define DAC_CTRLA_ENABLE (0x1u << DAC_CTRLA_ENABLE_Pos)
#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
#define DAC_CTRLA_RUNSTDBY (0x1u << DAC_CTRLA_RUNSTDBY_Pos)
#define DAC_CTRLA_MASK 0x07u /**< \brief (DAC_CTRLA) MASK Register */
/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
uint8_t :1; /*!< bit: 5 Reserved */
uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
#define DAC_CTRLB_RESETVALUE 0x00 /**< \brief (DAC_CTRLB reset_value) Control B */
#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
#define DAC_CTRLB_EOEN (0x1u << DAC_CTRLB_EOEN_Pos)
#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
#define DAC_CTRLB_IOEN (0x1u << DAC_CTRLB_IOEN_Pos)
#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
#define DAC_CTRLB_LEFTADJ (0x1u << DAC_CTRLB_LEFTADJ_Pos)
#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
#define DAC_CTRLB_VPD (0x1u << DAC_CTRLB_VPD_Pos)
#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
#define DAC_CTRLB_BDWP (0x1u << DAC_CTRLB_BDWP_Pos)
#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
#define DAC_CTRLB_REFSEL_Msk (0x3u << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)))
#define DAC_CTRLB_REFSEL_INT1V_Val 0x0u /**< \brief (DAC_CTRLB) Internal 1.0V reference */
#define DAC_CTRLB_REFSEL_AVCC_Val 0x1u /**< \brief (DAC_CTRLB) AVCC */
#define DAC_CTRLB_REFSEL_VREFP_Val 0x2u /**< \brief (DAC_CTRLB) External reference */
#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_MASK 0xDFu /**< \brief (DAC_CTRLB) MASK Register */
/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
#define DAC_EVCTRL_RESETVALUE 0x00 /**< \brief (DAC_EVCTRL reset_value) Event Control */
#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
#define DAC_EVCTRL_STARTEI (0x1u << DAC_EVCTRL_STARTEI_Pos)
#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
#define DAC_EVCTRL_EMPTYEO (0x1u << DAC_EVCTRL_EMPTYEO_Pos)
#define DAC_EVCTRL_MASK 0x03u /**< \brief (DAC_EVCTRL) MASK Register */
/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
#define DAC_INTENCLR_RESETVALUE 0x00 /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
#define DAC_INTENCLR_UNDERRUN (0x1u << DAC_INTENCLR_UNDERRUN_Pos)
#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
#define DAC_INTENCLR_EMPTY (0x1u << DAC_INTENCLR_EMPTY_Pos)
#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
#define DAC_INTENCLR_SYNCRDY (0x1u << DAC_INTENCLR_SYNCRDY_Pos)
#define DAC_INTENCLR_MASK 0x07u /**< \brief (DAC_INTENCLR) MASK Register */
/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
#define DAC_INTENSET_RESETVALUE 0x00 /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
#define DAC_INTENSET_UNDERRUN (0x1u << DAC_INTENSET_UNDERRUN_Pos)
#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
#define DAC_INTENSET_EMPTY (0x1u << DAC_INTENSET_EMPTY_Pos)
#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
#define DAC_INTENSET_SYNCRDY (0x1u << DAC_INTENSET_SYNCRDY_Pos)
#define DAC_INTENSET_MASK 0x07u /**< \brief (DAC_INTENSET) MASK Register */
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
#define DAC_INTFLAG_RESETVALUE 0x00 /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
#define DAC_INTFLAG_UNDERRUN (0x1u << DAC_INTFLAG_UNDERRUN_Pos)
#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
#define DAC_INTFLAG_EMPTY (0x1u << DAC_INTFLAG_EMPTY_Pos)
#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
#define DAC_INTFLAG_SYNCRDY (0x1u << DAC_INTFLAG_SYNCRDY_Pos)
#define DAC_INTFLAG_MASK 0x07u /**< \brief (DAC_INTFLAG) MASK Register */
/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
#define DAC_STATUS_RESETVALUE 0x00 /**< \brief (DAC_STATUS reset_value) Status */
#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
#define DAC_STATUS_SYNCBUSY (0x1u << DAC_STATUS_SYNCBUSY_Pos)
#define DAC_STATUS_MASK 0x80u /**< \brief (DAC_STATUS) MASK Register */
/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
#define DAC_DATA_RESETVALUE 0x0000 /**< \brief (DAC_DATA reset_value) Data */
#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
#define DAC_DATA_DATA_Msk (0xFFFFu << DAC_DATA_DATA_Pos)
#define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)))
#define DAC_DATA_MASK 0xFFFFu /**< \brief (DAC_DATA) MASK Register */
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATABUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
#define DAC_DATABUF_RESETVALUE 0x0000 /**< \brief (DAC_DATABUF reset_value) Data Buffer */
#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
#define DAC_DATABUF_DATABUF_Msk (0xFFFFu << DAC_DATABUF_DATABUF_Pos)
#define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)))
#define DAC_DATABUF_MASK 0xFFFFu /**< \brief (DAC_DATABUF) MASK Register */
/** \brief DAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
RoReg8 Reserved1[0x1];
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
RoReg8 Reserved2[0x2];
__IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
} Dac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_DAC_COMPONENT_ */

1033
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/dmac.h Normal file
View file

File diff suppressed because it is too large Load diff

551
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/dsu.h Normal file
View file

@ -0,0 +1,551 @@
/**
* \file
*
* \brief Component description for DSU
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_DSU_COMPONENT_
#define _SAMD21_DSU_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR DSU */
/* ========================================================================== */
/** \addtogroup SAMD21_DSU Device Service Unit */
/*@{*/
#define DSU_U2209
#define REV_DSU 0x200
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
uint8_t CE:1; /*!< bit: 4 Chip Erase */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
#define DSU_CTRL_RESETVALUE 0x00 /**< \brief (DSU_CTRL reset_value) Control */
#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
#define DSU_CTRL_SWRST (0x1u << DSU_CTRL_SWRST_Pos)
#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */
#define DSU_CTRL_CRC (0x1u << DSU_CTRL_CRC_Pos)
#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */
#define DSU_CTRL_MBIST (0x1u << DSU_CTRL_MBIST_Pos)
#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */
#define DSU_CTRL_CE (0x1u << DSU_CTRL_CE_Pos)
#define DSU_CTRL_MASK 0x1Du /**< \brief (DSU_CTRL) MASK Register */
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1; /*!< bit: 0 Done */
uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
uint8_t BERR:1; /*!< bit: 2 Bus Error */
uint8_t FAIL:1; /*!< bit: 3 Failure */
uint8_t PERR:1; /*!< bit: 4 Protection Error */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
#define DSU_STATUSA_RESETVALUE 0x00 /**< \brief (DSU_STATUSA reset_value) Status A */
#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
#define DSU_STATUSA_DONE (0x1u << DSU_STATUSA_DONE_Pos)
#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
#define DSU_STATUSA_CRSTEXT (0x1u << DSU_STATUSA_CRSTEXT_Pos)
#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
#define DSU_STATUSA_BERR (0x1u << DSU_STATUSA_BERR_Pos)
#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
#define DSU_STATUSA_FAIL (0x1u << DSU_STATUSA_FAIL_Pos)
#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
#define DSU_STATUSA_PERR (0x1u << DSU_STATUSA_PERR_Pos)
#define DSU_STATUSA_MASK 0x1Fu /**< \brief (DSU_STATUSA) MASK Register */
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PROT:1; /*!< bit: 0 Protected */
uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
#define DSU_STATUSB_RESETVALUE 0x10 /**< \brief (DSU_STATUSB reset_value) Status B */
#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
#define DSU_STATUSB_PROT (0x1u << DSU_STATUSB_PROT_Pos)
#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
#define DSU_STATUSB_DBGPRES (0x1u << DSU_STATUSB_DBGPRES_Pos)
#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
#define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos)
#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
#define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos)
#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
#define DSU_STATUSB_DCCD_Msk (0x3u << DSU_STATUSB_DCCD_Pos)
#define DSU_STATUSB_DCCD(value) ((DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)))
#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
#define DSU_STATUSB_HPE (0x1u << DSU_STATUSB_HPE_Pos)
#define DSU_STATUSB_MASK 0x1Fu /**< \brief (DSU_STATUSB) MASK Register */
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t ADDR:30; /*!< bit: 2..31 Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
#define DSU_ADDR_RESETVALUE 0x00000000 /**< \brief (DSU_ADDR reset_value) Address */
#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
#define DSU_ADDR_ADDR_Msk (0x3FFFFFFFu << DSU_ADDR_ADDR_Pos)
#define DSU_ADDR_ADDR(value) ((DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)))
#define DSU_ADDR_MASK 0xFFFFFFFCu /**< \brief (DSU_ADDR) MASK Register */
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t LENGTH:30; /*!< bit: 2..31 Length */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
#define DSU_LENGTH_RESETVALUE 0x00000000 /**< \brief (DSU_LENGTH reset_value) Length */
#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
#define DSU_LENGTH_LENGTH_Msk (0x3FFFFFFFu << DSU_LENGTH_LENGTH_Pos)
#define DSU_LENGTH_LENGTH(value) ((DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)))
#define DSU_LENGTH_MASK 0xFFFFFFFCu /**< \brief (DSU_LENGTH) MASK Register */
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
#define DSU_DATA_RESETVALUE 0x00000000 /**< \brief (DSU_DATA reset_value) Data */
#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
#define DSU_DATA_DATA_Msk (0xFFFFFFFFu << DSU_DATA_DATA_Pos)
#define DSU_DATA_DATA(value) ((DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)))
#define DSU_DATA_MASK 0xFFFFFFFFu /**< \brief (DSU_DATA) MASK Register */
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
#define DSU_DCC_RESETVALUE 0x00000000 /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
#define DSU_DCC_DATA_Msk (0xFFFFFFFFu << DSU_DCC_DATA_Pos)
#define DSU_DCC_DATA(value) ((DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)))
#define DSU_DCC_MASK 0xFFFFFFFFu /**< \brief (DSU_DCC) MASK Register */
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
uint32_t REVISION:4; /*!< bit: 8..11 Revision */
uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
uint32_t :1; /*!< bit: 22 Reserved */
uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
#define DSU_DID_DEVSEL_Msk (0xFFu << DSU_DID_DEVSEL_Pos)
#define DSU_DID_DEVSEL(value) ((DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)))
#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */
#define DSU_DID_REVISION_Msk (0xFu << DSU_DID_REVISION_Pos)
#define DSU_DID_REVISION(value) ((DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)))
#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */
#define DSU_DID_DIE_Msk (0xFu << DSU_DID_DIE_Pos)
#define DSU_DID_DIE(value) ((DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)))
#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */
#define DSU_DID_SERIES_Msk (0x3Fu << DSU_DID_SERIES_Pos)
#define DSU_DID_SERIES(value) ((DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)))
#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */
#define DSU_DID_FAMILY_Msk (0x1Fu << DSU_DID_FAMILY_Pos)
#define DSU_DID_FAMILY(value) ((DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)))
#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
#define DSU_DID_PROCESSOR_Msk (0xFu << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR(value) ((DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)))
#define DSU_DID_MASK 0xFFBFFFFFu /**< \brief (DSU_DID) MASK Register */
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EPRES:1; /*!< bit: 0 Entry Present */
uint32_t FMT:1; /*!< bit: 1 Format */
uint32_t :10; /*!< bit: 2..11 Reserved */
uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */
#define DSU_ENTRY_RESETVALUE 0x00000002 /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */
#define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */
#define DSU_ENTRY_EPRES (0x1u << DSU_ENTRY_EPRES_Pos)
#define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */
#define DSU_ENTRY_FMT (0x1u << DSU_ENTRY_FMT_Pos)
#define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */
#define DSU_ENTRY_ADDOFF_Msk (0xFFFFFu << DSU_ENTRY_ADDOFF_Pos)
#define DSU_ENTRY_ADDOFF(value) ((DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)))
#define DSU_ENTRY_MASK 0xFFFFF003u /**< \brief (DSU_ENTRY) MASK Register */
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t END:32; /*!< bit: 0..31 End Marker */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */
#define DSU_END_RESETVALUE 0x00000000 /**< \brief (DSU_END reset_value) Coresight ROM Table End */
#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
#define DSU_END_END_Msk (0xFFFFFFFFu << DSU_END_END_Pos)
#define DSU_END_END(value) ((DSU_END_END_Msk & ((value) << DSU_END_END_Pos)))
#define DSU_END_MASK 0xFFFFFFFFu /**< \brief (DSU_END) MASK Register */
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */
#define DSU_MEMTYPE_RESETVALUE 0x00000000 /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */
#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
#define DSU_MEMTYPE_SMEMP (0x1u << DSU_MEMTYPE_SMEMP_Pos)
#define DSU_MEMTYPE_MASK 0x00000001u /**< \brief (DSU_MEMTYPE) MASK Register */
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
#define DSU_PID4_RESETVALUE 0x00000000 /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
#define DSU_PID4_JEPCC_Msk (0xFu << DSU_PID4_JEPCC_Pos)
#define DSU_PID4_JEPCC(value) ((DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)))
#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */
#define DSU_PID4_FKBC_Msk (0xFu << DSU_PID4_FKBC_Pos)
#define DSU_PID4_FKBC(value) ((DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)))
#define DSU_PID4_MASK 0x000000FFu /**< \brief (DSU_PID4) MASK Register */
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
#define DSU_PID0_RESETVALUE 0x000000D0 /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
#define DSU_PID0_PARTNBL_Msk (0xFFu << DSU_PID0_PARTNBL_Pos)
#define DSU_PID0_PARTNBL(value) ((DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)))
#define DSU_PID0_MASK 0x000000FFu /**< \brief (DSU_PID0) MASK Register */
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
#define DSU_PID1_RESETVALUE 0x000000FC /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
#define DSU_PID1_PARTNBH_Msk (0xFu << DSU_PID1_PARTNBH_Pos)
#define DSU_PID1_PARTNBH(value) ((DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)))
#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
#define DSU_PID1_JEPIDCL_Msk (0xFu << DSU_PID1_JEPIDCL_Pos)
#define DSU_PID1_JEPIDCL(value) ((DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)))
#define DSU_PID1_MASK 0x000000FFu /**< \brief (DSU_PID1) MASK Register */
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
#define DSU_PID2_RESETVALUE 0x00000009 /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
#define DSU_PID2_JEPIDCH_Msk (0x7u << DSU_PID2_JEPIDCH_Pos)
#define DSU_PID2_JEPIDCH(value) ((DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)))
#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
#define DSU_PID2_JEPU (0x1u << DSU_PID2_JEPU_Pos)
#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
#define DSU_PID2_REVISION_Msk (0xFu << DSU_PID2_REVISION_Pos)
#define DSU_PID2_REVISION(value) ((DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)))
#define DSU_PID2_MASK 0x000000FFu /**< \brief (DSU_PID2) MASK Register */
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
#define DSU_PID3_RESETVALUE 0x00000000 /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
#define DSU_PID3_CUSMOD_Msk (0xFu << DSU_PID3_CUSMOD_Pos)
#define DSU_PID3_CUSMOD(value) ((DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)))
#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
#define DSU_PID3_REVAND_Msk (0xFu << DSU_PID3_REVAND_Pos)
#define DSU_PID3_REVAND(value) ((DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)))
#define DSU_PID3_MASK 0x000000FFu /**< \brief (DSU_PID3) MASK Register */
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
#define DSU_CID0_RESETVALUE 0x0000000D /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
#define DSU_CID0_PREAMBLEB0_Msk (0xFFu << DSU_CID0_PREAMBLEB0_Pos)
#define DSU_CID0_PREAMBLEB0(value) ((DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)))
#define DSU_CID0_MASK 0x000000FFu /**< \brief (DSU_CID0) MASK Register */
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
#define DSU_CID1_RESETVALUE 0x00000010 /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
#define DSU_CID1_PREAMBLE_Msk (0xFu << DSU_CID1_PREAMBLE_Pos)
#define DSU_CID1_PREAMBLE(value) ((DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)))
#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
#define DSU_CID1_CCLASS_Msk (0xFu << DSU_CID1_CCLASS_Pos)
#define DSU_CID1_CCLASS(value) ((DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)))
#define DSU_CID1_MASK 0x000000FFu /**< \brief (DSU_CID1) MASK Register */
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
#define DSU_CID2_RESETVALUE 0x00000005 /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
#define DSU_CID2_PREAMBLEB2_Msk (0xFFu << DSU_CID2_PREAMBLEB2_Pos)
#define DSU_CID2_PREAMBLEB2(value) ((DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)))
#define DSU_CID2_MASK 0x000000FFu /**< \brief (DSU_CID2) MASK Register */
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
#define DSU_CID3_RESETVALUE 0x000000B1 /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
#define DSU_CID3_PREAMBLEB3_Msk (0xFFu << DSU_CID3_PREAMBLEB3_Pos)
#define DSU_CID3_PREAMBLEB3(value) ((DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)))
#define DSU_CID3_MASK 0x000000FFu /**< \brief (DSU_CID3) MASK Register */
/** \brief DSU hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
__IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
__I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
RoReg8 Reserved1[0x1];
__IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
__IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
RoReg8 Reserved2[0xFE4];
__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
RoReg8 Reserved4[0xC];
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
__I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
__I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
__I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
__I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
__I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_DSU_COMPONENT_ */

681
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/eic.h Normal file
View file

@ -0,0 +1,681 @@
/**
* \file
*
* \brief Component description for EIC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_EIC_COMPONENT_
#define _SAMD21_EIC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR EIC */
/* ========================================================================== */
/** \addtogroup SAMD21_EIC External Interrupt Controller */
/*@{*/
#define EIC_U2217
#define REV_EIC 0x101
/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */
#define EIC_CTRL_RESETVALUE 0x00 /**< \brief (EIC_CTRL reset_value) Control */
#define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */
#define EIC_CTRL_SWRST (0x1u << EIC_CTRL_SWRST_Pos)
#define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */
#define EIC_CTRL_ENABLE (0x1u << EIC_CTRL_ENABLE_Pos)
#define EIC_CTRL_MASK 0x03u /**< \brief (EIC_CTRL) MASK Register */
/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */
#define EIC_STATUS_RESETVALUE 0x00 /**< \brief (EIC_STATUS reset_value) Status */
#define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */
#define EIC_STATUS_SYNCBUSY (0x1u << EIC_STATUS_SYNCBUSY_Pos)
#define EIC_STATUS_MASK 0x80u /**< \brief (EIC_STATUS) MASK Register */
/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */
#define EIC_NMICTRL_RESETVALUE 0x00 /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */
#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */
#define EIC_NMICTRL_NMISENSE_Msk (0x7u << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE(value) ((EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)))
#define EIC_NMICTRL_NMISENSE_NONE_Val 0x0u /**< \brief (EIC_NMICTRL) No detection */
#define EIC_NMICTRL_NMISENSE_RISE_Val 0x1u /**< \brief (EIC_NMICTRL) Rising-edge detection */
#define EIC_NMICTRL_NMISENSE_FALL_Val 0x2u /**< \brief (EIC_NMICTRL) Falling-edge detection */
#define EIC_NMICTRL_NMISENSE_BOTH_Val 0x3u /**< \brief (EIC_NMICTRL) Both-edges detection */
#define EIC_NMICTRL_NMISENSE_HIGH_Val 0x4u /**< \brief (EIC_NMICTRL) High-level detection */
#define EIC_NMICTRL_NMISENSE_LOW_Val 0x5u /**< \brief (EIC_NMICTRL) Low-level detection */
#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */
#define EIC_NMICTRL_NMIFILTEN (0x1u << EIC_NMICTRL_NMIFILTEN_Pos)
#define EIC_NMICTRL_MASK 0x0Fu /**< \brief (EIC_NMICTRL) MASK Register */
/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */
#define EIC_NMIFLAG_RESETVALUE 0x00 /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */
#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */
#define EIC_NMIFLAG_NMI (0x1u << EIC_NMIFLAG_NMI_Pos)
#define EIC_NMIFLAG_MASK 0x01u /**< \brief (EIC_NMIFLAG) MASK Register */
/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */
#define EIC_EVCTRL_RESETVALUE 0x00000000 /**< \brief (EIC_EVCTRL reset_value) Event Control */
#define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos)
#define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos)
#define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos)
#define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos)
#define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos)
#define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos)
#define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos)
#define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos)
#define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos)
#define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos)
#define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos)
#define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos)
#define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos)
#define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos)
#define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos)
#define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */
#define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos)
#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */
#define EIC_EVCTRL_EXTINTEO_Msk (0xFFFFu << EIC_EVCTRL_EXTINTEO_Pos)
#define EIC_EVCTRL_EXTINTEO(value) ((EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)))
#define EIC_EVCTRL_MASK 0x0000FFFFu /**< \brief (EIC_EVCTRL) MASK Register */
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
#define EIC_INTENCLR_RESETVALUE 0x00000000 /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
#define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */
#define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos)
#define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */
#define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos)
#define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */
#define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos)
#define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */
#define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos)
#define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */
#define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos)
#define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */
#define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos)
#define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */
#define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos)
#define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */
#define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos)
#define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */
#define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos)
#define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */
#define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos)
#define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */
#define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos)
#define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */
#define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos)
#define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */
#define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos)
#define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */
#define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos)
#define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */
#define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos)
#define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */
#define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos)
#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */
#define EIC_INTENCLR_EXTINT_Msk (0xFFFFu << EIC_INTENCLR_EXTINT_Pos)
#define EIC_INTENCLR_EXTINT(value) ((EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)))
#define EIC_INTENCLR_MASK 0x0000FFFFu /**< \brief (EIC_INTENCLR) MASK Register */
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
#define EIC_INTENSET_RESETVALUE 0x00000000 /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
#define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */
#define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos)
#define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */
#define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos)
#define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */
#define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos)
#define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */
#define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos)
#define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */
#define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos)
#define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */
#define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos)
#define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */
#define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos)
#define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */
#define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos)
#define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */
#define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos)
#define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */
#define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos)
#define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */
#define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos)
#define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */
#define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos)
#define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */
#define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos)
#define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */
#define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos)
#define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */
#define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos)
#define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */
#define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos)
#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */
#define EIC_INTENSET_EXTINT_Msk (0xFFFFu << EIC_INTENSET_EXTINT_Pos)
#define EIC_INTENSET_EXTINT(value) ((EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)))
#define EIC_INTENSET_MASK 0x0000FFFFu /**< \brief (EIC_INTENSET) MASK Register */
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
#define EIC_INTFLAG_RESETVALUE 0x00000000 /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */
#define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos)
#define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */
#define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos)
#define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */
#define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos)
#define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */
#define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos)
#define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */
#define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos)
#define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */
#define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos)
#define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */
#define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos)
#define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */
#define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos)
#define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */
#define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos)
#define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */
#define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos)
#define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */
#define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos)
#define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */
#define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos)
#define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */
#define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos)
#define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */
#define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos)
#define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */
#define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos)
#define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */
#define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos)
#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */
#define EIC_INTFLAG_EXTINT_Msk (0xFFFFu << EIC_INTFLAG_EXTINT_Pos)
#define EIC_INTFLAG_EXTINT(value) ((EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)))
#define EIC_INTFLAG_MASK 0x0000FFFFu /**< \brief (EIC_INTFLAG) MASK Register */
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_WAKEUP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */
#define EIC_WAKEUP_RESETVALUE 0x00000000 /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */
#define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos)
#define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos)
#define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos)
#define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos)
#define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos)
#define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos)
#define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos)
#define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos)
#define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos)
#define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos)
#define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos)
#define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos)
#define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos)
#define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos)
#define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos)
#define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos)
#define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */
#define EIC_WAKEUP_WAKEUPEN_Msk (0xFFFFu << EIC_WAKEUP_WAKEUPEN_Pos)
#define EIC_WAKEUP_WAKEUPEN(value) ((EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)))
#define EIC_WAKEUP_MASK 0x0000FFFFu /**< \brief (EIC_WAKEUP) MASK Register */
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */
#define EIC_CONFIG_RESETVALUE 0x00000000 /**< \brief (EIC_CONFIG reset_value) Configuration n */
#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */
#define EIC_CONFIG_SENSE0_Msk (0x7u << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0(value) ((EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)))
#define EIC_CONFIG_SENSE0_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE0_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising-edge detection */
#define EIC_CONFIG_SENSE0_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling-edge detection */
#define EIC_CONFIG_SENSE0_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both-edges detection */
#define EIC_CONFIG_SENSE0_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High-level detection */
#define EIC_CONFIG_SENSE0_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low-level detection */
#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */
#define EIC_CONFIG_FILTEN0 (0x1u << EIC_CONFIG_FILTEN0_Pos)
#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */
#define EIC_CONFIG_SENSE1_Msk (0x7u << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1(value) ((EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)))
#define EIC_CONFIG_SENSE1_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE1_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE1_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE1_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE1_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE1_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */
#define EIC_CONFIG_FILTEN1 (0x1u << EIC_CONFIG_FILTEN1_Pos)
#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */
#define EIC_CONFIG_SENSE2_Msk (0x7u << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2(value) ((EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)))
#define EIC_CONFIG_SENSE2_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE2_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE2_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE2_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE2_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE2_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */
#define EIC_CONFIG_FILTEN2 (0x1u << EIC_CONFIG_FILTEN2_Pos)
#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */
#define EIC_CONFIG_SENSE3_Msk (0x7u << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3(value) ((EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)))
#define EIC_CONFIG_SENSE3_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE3_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE3_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE3_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE3_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE3_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */
#define EIC_CONFIG_FILTEN3 (0x1u << EIC_CONFIG_FILTEN3_Pos)
#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */
#define EIC_CONFIG_SENSE4_Msk (0x7u << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4(value) ((EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)))
#define EIC_CONFIG_SENSE4_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE4_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE4_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE4_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE4_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE4_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */
#define EIC_CONFIG_FILTEN4 (0x1u << EIC_CONFIG_FILTEN4_Pos)
#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */
#define EIC_CONFIG_SENSE5_Msk (0x7u << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5(value) ((EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)))
#define EIC_CONFIG_SENSE5_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE5_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE5_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE5_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE5_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE5_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */
#define EIC_CONFIG_FILTEN5 (0x1u << EIC_CONFIG_FILTEN5_Pos)
#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */
#define EIC_CONFIG_SENSE6_Msk (0x7u << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6(value) ((EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)))
#define EIC_CONFIG_SENSE6_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE6_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE6_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE6_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE6_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE6_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */
#define EIC_CONFIG_FILTEN6 (0x1u << EIC_CONFIG_FILTEN6_Pos)
#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */
#define EIC_CONFIG_SENSE7_Msk (0x7u << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7(value) ((EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)))
#define EIC_CONFIG_SENSE7_NONE_Val 0x0u /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE7_RISE_Val 0x1u /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE7_FALL_Val 0x2u /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE7_BOTH_Val 0x3u /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE7_HIGH_Val 0x4u /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE7_LOW_Val 0x5u /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */
#define EIC_CONFIG_FILTEN7 (0x1u << EIC_CONFIG_FILTEN7_Pos)
#define EIC_CONFIG_MASK 0xFFFFFFFFu /**< \brief (EIC_CONFIG) MASK Register */
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
__IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_EIC_COMPONENT_ */

604
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/evsys.h Normal file
View file

@ -0,0 +1,604 @@
/**
* \file
*
* \brief Component description for EVSYS
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_EVSYS_COMPONENT_
#define _SAMD21_EVSYS_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR EVSYS */
/* ========================================================================== */
/** \addtogroup SAMD21_EVSYS Event System Interface */
/*@{*/
#define EVSYS_U2208
#define REV_EVSYS 0x101
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :3; /*!< bit: 1.. 3 Reserved */
uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */
#define EVSYS_CTRL_RESETVALUE 0x00 /**< \brief (EVSYS_CTRL reset_value) Control */
#define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */
#define EVSYS_CTRL_SWRST (0x1u << EVSYS_CTRL_SWRST_Pos)
#define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */
#define EVSYS_CTRL_GCLKREQ (0x1u << EVSYS_CTRL_GCLKREQ_Pos)
#define EVSYS_CTRL_MASK 0x11u /**< \brief (EVSYS_CTRL) MASK Register */
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
uint32_t :7; /*!< bit: 9..15 Reserved */
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */
#define EVSYS_CHANNEL_RESETVALUE 0x00000000 /**< \brief (EVSYS_CHANNEL reset_value) Channel */
#define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */
#define EVSYS_CHANNEL_CHANNEL_Msk (0xFu << EVSYS_CHANNEL_CHANNEL_Pos)
#define EVSYS_CHANNEL_CHANNEL(value) ((EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)))
#define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */
#define EVSYS_CHANNEL_SWEVT (0x1u << EVSYS_CHANNEL_SWEVT_Pos)
#define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
#define EVSYS_CHANNEL_EVGEN_Msk (0x7Fu << EVSYS_CHANNEL_EVGEN_Pos)
#define EVSYS_CHANNEL_EVGEN(value) ((EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)))
#define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */
#define EVSYS_CHANNEL_PATH_Msk (0x3u << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH(value) ((EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)))
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val 0x0u /**< \brief (EVSYS_CHANNEL) Synchronous path */
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val 0x1u /**< \brief (EVSYS_CHANNEL) Resynchronized path */
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val 0x2u /**< \brief (EVSYS_CHANNEL) Asynchronous path */
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
#define EVSYS_CHANNEL_EDGSEL_Msk (0x3u << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL(value) ((EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)))
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val 0x0u /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val 0x1u /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val 0x2u /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val 0x3u /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_MASK 0x0F7F010Fu /**< \brief (EVSYS_CHANNEL) MASK Register */
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */
#define EVSYS_USER_RESETVALUE 0x0000 /**< \brief (EVSYS_USER reset_value) User Multiplexer */
#define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */
#define EVSYS_USER_USER_Msk (0x1Fu << EVSYS_USER_USER_Pos)
#define EVSYS_USER_USER(value) ((EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)))
#define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */
#define EVSYS_USER_CHANNEL_Msk (0x1Fu << EVSYS_USER_CHANNEL_Pos)
#define EVSYS_USER_CHANNEL(value) ((EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)))
#define EVSYS_USER_CHANNEL_0_Val 0x0u /**< \brief (EVSYS_USER) No Channel Output Selected */
#define EVSYS_USER_CHANNEL_0 (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos)
#define EVSYS_USER_MASK 0x1F1Fu /**< \brief (EVSYS_USER) MASK Register */
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
#define EVSYS_CHSTATUS_RESETVALUE 0x000F00FF /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
#define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos)
#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
#define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos)
#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
#define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos)
#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
#define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos)
#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
#define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos)
#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
#define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos)
#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
#define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos)
#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
#define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos)
#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
#define EVSYS_CHSTATUS_USRRDY_Msk (0xFFu << EVSYS_CHSTATUS_USRRDY_Pos)
#define EVSYS_CHSTATUS_USRRDY(value) ((EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)))
#define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
#define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos)
#define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
#define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos)
#define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
#define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos)
#define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
#define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos)
#define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
#define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos)
#define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
#define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos)
#define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
#define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos)
#define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
#define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos)
#define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
#define EVSYS_CHSTATUS_CHBUSY_Msk (0xFFu << EVSYS_CHSTATUS_CHBUSY_Pos)
#define EVSYS_CHSTATUS_CHBUSY(value) ((EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)))
#define EVSYS_CHSTATUS_USRRDY8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
#define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos)
#define EVSYS_CHSTATUS_USRRDY9_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
#define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos)
#define EVSYS_CHSTATUS_USRRDY10_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
#define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos)
#define EVSYS_CHSTATUS_USRRDY11_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
#define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos)
#define EVSYS_CHSTATUS_USRRDYp8_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x+8 User Ready */
#define EVSYS_CHSTATUS_USRRDYp8_Msk (0xFu << EVSYS_CHSTATUS_USRRDYp8_Pos)
#define EVSYS_CHSTATUS_USRRDYp8(value) ((EVSYS_CHSTATUS_USRRDYp8_Msk & ((value) << EVSYS_CHSTATUS_USRRDYp8_Pos)))
#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
#define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos)
#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
#define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos)
#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
#define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos)
#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
#define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos)
#define EVSYS_CHSTATUS_CHBUSYp8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel x+8 Busy */
#define EVSYS_CHSTATUS_CHBUSYp8_Msk (0xFu << EVSYS_CHSTATUS_CHBUSYp8_Pos)
#define EVSYS_CHSTATUS_CHBUSYp8(value) ((EVSYS_CHSTATUS_CHBUSYp8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSYp8_Pos)))
#define EVSYS_CHSTATUS_MASK 0x0F0FFFFFu /**< \brief (EVSYS_CHSTATUS) MASK Register */
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
#define EVSYS_INTENCLR_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos)
#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos)
#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos)
#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos)
#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos)
#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos)
#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos)
#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos)
#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR_Msk (0xFFu << EVSYS_INTENCLR_OVR_Pos)
#define EVSYS_INTENCLR_OVR(value) ((EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)))
#define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos)
#define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos)
#define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos)
#define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos)
#define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos)
#define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos)
#define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos)
#define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos)
#define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD_Msk (0xFFu << EVSYS_INTENCLR_EVD_Pos)
#define EVSYS_INTENCLR_EVD(value) ((EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)))
#define EVSYS_INTENCLR_OVR8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos)
#define EVSYS_INTENCLR_OVR9_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos)
#define EVSYS_INTENCLR_OVR10_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos)
#define EVSYS_INTENCLR_OVR11_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos)
#define EVSYS_INTENCLR_OVRp8_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x+8 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVRp8_Msk (0xFu << EVSYS_INTENCLR_OVRp8_Pos)
#define EVSYS_INTENCLR_OVRp8(value) ((EVSYS_INTENCLR_OVRp8_Msk & ((value) << EVSYS_INTENCLR_OVRp8_Pos)))
#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos)
#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos)
#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos)
#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos)
#define EVSYS_INTENCLR_EVDp8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel x+8 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVDp8_Msk (0xFu << EVSYS_INTENCLR_EVDp8_Pos)
#define EVSYS_INTENCLR_EVDp8(value) ((EVSYS_INTENCLR_EVDp8_Msk & ((value) << EVSYS_INTENCLR_EVDp8_Pos)))
#define EVSYS_INTENCLR_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTENCLR) MASK Register */
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
#define EVSYS_INTENSET_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos)
#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos)
#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos)
#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos)
#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos)
#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos)
#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos)
#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos)
#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR_Msk (0xFFu << EVSYS_INTENSET_OVR_Pos)
#define EVSYS_INTENSET_OVR(value) ((EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)))
#define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos)
#define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos)
#define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos)
#define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos)
#define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos)
#define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos)
#define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos)
#define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos)
#define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD_Msk (0xFFu << EVSYS_INTENSET_EVD_Pos)
#define EVSYS_INTENSET_EVD(value) ((EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)))
#define EVSYS_INTENSET_OVR8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos)
#define EVSYS_INTENSET_OVR9_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos)
#define EVSYS_INTENSET_OVR10_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos)
#define EVSYS_INTENSET_OVR11_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos)
#define EVSYS_INTENSET_OVRp8_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x+8 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVRp8_Msk (0xFu << EVSYS_INTENSET_OVRp8_Pos)
#define EVSYS_INTENSET_OVRp8(value) ((EVSYS_INTENSET_OVRp8_Msk & ((value) << EVSYS_INTENSET_OVRp8_Pos)))
#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos)
#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos)
#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos)
#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos)
#define EVSYS_INTENSET_EVDp8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel x+8 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVDp8_Msk (0xFu << EVSYS_INTENSET_EVDp8_Pos)
#define EVSYS_INTENSET_EVDp8(value) ((EVSYS_INTENSET_EVDp8_Msk & ((value) << EVSYS_INTENSET_EVDp8_Pos)))
#define EVSYS_INTENSET_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTENSET) MASK Register */
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
#define EVSYS_INTFLAG_RESETVALUE 0x00000000 /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
#define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos)
#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
#define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos)
#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
#define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos)
#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
#define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos)
#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
#define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos)
#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
#define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos)
#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
#define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos)
#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
#define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos)
#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
#define EVSYS_INTFLAG_OVR_Msk (0xFFu << EVSYS_INTFLAG_OVR_Pos)
#define EVSYS_INTFLAG_OVR(value) ((EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)))
#define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
#define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos)
#define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
#define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos)
#define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
#define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos)
#define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
#define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos)
#define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
#define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos)
#define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
#define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos)
#define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
#define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos)
#define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
#define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos)
#define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
#define EVSYS_INTFLAG_EVD_Msk (0xFFu << EVSYS_INTFLAG_EVD_Pos)
#define EVSYS_INTFLAG_EVD(value) ((EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)))
#define EVSYS_INTFLAG_OVR8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
#define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos)
#define EVSYS_INTFLAG_OVR9_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
#define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos)
#define EVSYS_INTFLAG_OVR10_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
#define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos)
#define EVSYS_INTFLAG_OVR11_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
#define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos)
#define EVSYS_INTFLAG_OVRp8_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x+8 Overrun */
#define EVSYS_INTFLAG_OVRp8_Msk (0xFu << EVSYS_INTFLAG_OVRp8_Pos)
#define EVSYS_INTFLAG_OVRp8(value) ((EVSYS_INTFLAG_OVRp8_Msk & ((value) << EVSYS_INTFLAG_OVRp8_Pos)))
#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
#define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos)
#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
#define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos)
#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
#define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos)
#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
#define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos)
#define EVSYS_INTFLAG_EVDp8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel x+8 Event Detection */
#define EVSYS_INTFLAG_EVDp8_Msk (0xFu << EVSYS_INTFLAG_EVDp8_Pos)
#define EVSYS_INTFLAG_EVDp8(value) ((EVSYS_INTFLAG_EVDp8_Msk & ((value) << EVSYS_INTFLAG_EVDp8_Pos)))
#define EVSYS_INTFLAG_MASK 0x0F0FFFFFu /**< \brief (EVSYS_INTFLAG) MASK Register */
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
RoReg8 Reserved1[0x3];
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
__IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
RoReg8 Reserved2[0x2];
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_EVSYS_COMPONENT_ */

234
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/gclk.h Normal file
View file

@ -0,0 +1,234 @@
/**
* \file
*
* \brief Component description for GCLK
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_GCLK_COMPONENT_
#define _SAMD21_GCLK_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR GCLK */
/* ========================================================================== */
/** \addtogroup SAMD21_GCLK Generic Clock Generator */
/*@{*/
#define GCLK_U2102
#define REV_GCLK 0x210
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
#define GCLK_CTRL_RESETVALUE 0x00 /**< \brief (GCLK_CTRL reset_value) Control */
#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
#define GCLK_CTRL_SWRST (0x1u << GCLK_CTRL_SWRST_Pos)
#define GCLK_CTRL_MASK 0x01u /**< \brief (GCLK_CTRL) MASK Register */
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
#define GCLK_STATUS_RESETVALUE 0x00 /**< \brief (GCLK_STATUS reset_value) Status */
#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
#define GCLK_STATUS_SYNCBUSY (0x1u << GCLK_STATUS_SYNCBUSY_Pos)
#define GCLK_STATUS_MASK 0x80u /**< \brief (GCLK_STATUS) MASK Register */
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
uint16_t :2; /*!< bit: 12..13 Reserved */
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} GCLK_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
#define GCLK_CLKCTRL_RESETVALUE 0x0000 /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
#define GCLK_CLKCTRL_ID_Msk (0x3Fu << GCLK_CLKCTRL_ID_Pos)
#define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos)))
#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
#define GCLK_CLKCTRL_GEN_Msk (0xFu << GCLK_CLKCTRL_GEN_Pos)
#define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos)))
#define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0u /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
#define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1u /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
#define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2u /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
#define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3u /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
#define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4u /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
#define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5u /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
#define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6u /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
#define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7u /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
#define GCLK_CLKCTRL_CLKEN (0x1u << GCLK_CLKCTRL_CLKEN_Pos)
#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
#define GCLK_CLKCTRL_WRTLOCK (0x1u << GCLK_CLKCTRL_WRTLOCK_Pos)
#define GCLK_CLKCTRL_MASK 0xCF3Fu /**< \brief (GCLK_CLKCTRL) MASK Register */
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
uint32_t OE:1; /*!< bit: 19 Output Enable */
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
#define GCLK_GENCTRL_RESETVALUE 0x00000000 /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
#define GCLK_GENCTRL_ID_Msk (0xFu << GCLK_GENCTRL_ID_Pos)
#define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos)))
#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
#define GCLK_GENCTRL_SRC_Msk (0x1Fu << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))
#define GCLK_GENCTRL_SRC_XOSC_Val 0x0u /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1u /**< \brief (GCLK_GENCTRL) Generator input pad */
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2u /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3u /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4u /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5u /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
#define GCLK_GENCTRL_SRC_OSC8M_Val 0x6u /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7u /**< \brief (GCLK_GENCTRL) DFLL48M output */
#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
#define GCLK_GENCTRL_GENEN (0x1u << GCLK_GENCTRL_GENEN_Pos)
#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
#define GCLK_GENCTRL_IDC (0x1u << GCLK_GENCTRL_IDC_Pos)
#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
#define GCLK_GENCTRL_OOV (0x1u << GCLK_GENCTRL_OOV_Pos)
#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
#define GCLK_GENCTRL_OE (0x1u << GCLK_GENCTRL_OE_Pos)
#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
#define GCLK_GENCTRL_DIVSEL (0x1u << GCLK_GENCTRL_DIVSEL_Pos)
#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
#define GCLK_GENCTRL_RUNSTDBY (0x1u << GCLK_GENCTRL_RUNSTDBY_Pos)
#define GCLK_GENCTRL_MASK 0x003F1F0Fu /**< \brief (GCLK_GENCTRL) MASK Register */
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
#define GCLK_GENDIV_RESETVALUE 0x00000000 /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
#define GCLK_GENDIV_ID_Msk (0xFu << GCLK_GENDIV_ID_Pos)
#define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos)))
#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
#define GCLK_GENDIV_DIV_Msk (0xFFFFu << GCLK_GENDIV_DIV_Pos)
#define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos)))
#define GCLK_GENDIV_MASK 0x00FFFF0Fu /**< \brief (GCLK_GENDIV) MASK Register */
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_GCLK_COMPONENT_ */

639
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/i2s.h Normal file
View file

@ -0,0 +1,639 @@
/**
* \file
*
* \brief Component description for I2S
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_I2S_COMPONENT_
#define _SAMD21_I2S_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR I2S */
/* ========================================================================== */
/** \addtogroup SAMD21_I2S Inter-IC Sound Interface */
/*@{*/
#define I2S_U2224
#define REV_I2S 0x101
/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} I2S_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */
#define I2S_CTRLA_RESETVALUE 0x00 /**< \brief (I2S_CTRLA reset_value) Control A */
#define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */
#define I2S_CTRLA_SWRST (0x1u << I2S_CTRLA_SWRST_Pos)
#define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */
#define I2S_CTRLA_ENABLE (0x1u << I2S_CTRLA_ENABLE_Pos)
#define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */
#define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos)
#define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */
#define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos)
#define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */
#define I2S_CTRLA_CKEN_Msk (0x3u << I2S_CTRLA_CKEN_Pos)
#define I2S_CTRLA_CKEN(value) ((I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)))
#define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */
#define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos)
#define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */
#define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos)
#define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */
#define I2S_CTRLA_SEREN_Msk (0x3u << I2S_CTRLA_SEREN_Pos)
#define I2S_CTRLA_SEREN(value) ((I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)))
#define I2S_CTRLA_MASK 0x3Fu /**< \brief (I2S_CTRLA) MASK Register */
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
uint32_t :2; /*!< bit: 9..10 Reserved */
uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
uint32_t :1; /*!< bit: 17 Reserved */
uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} I2S_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */
#define I2S_CLKCTRL_RESETVALUE 0x00000000 /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */
#define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */
#define I2S_CLKCTRL_SLOTSIZE_Msk (0x3u << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE(value) ((I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos)))
#define I2S_CLKCTRL_SLOTSIZE_8_Val 0x0u /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_16_Val 0x1u /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_24_Val 0x2u /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_32_Val 0x3u /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */
#define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos)
#define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */
#define I2S_CLKCTRL_NBSLOTS_Msk (0x7u << I2S_CLKCTRL_NBSLOTS_Pos)
#define I2S_CLKCTRL_NBSLOTS(value) ((I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos)))
#define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */
#define I2S_CLKCTRL_FSWIDTH_Msk (0x3u << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH(value) ((I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos)))
#define I2S_CLKCTRL_FSWIDTH_SLOT_Val 0x0u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */
#define I2S_CLKCTRL_FSWIDTH_HALF_Val 0x1u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */
#define I2S_CLKCTRL_FSWIDTH_BIT_Val 0x2u /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */
#define I2S_CLKCTRL_FSWIDTH_BURST_Val 0x3u /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */
#define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos)
#define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */
#define I2S_CLKCTRL_BITDELAY (0x1u << I2S_CLKCTRL_BITDELAY_Pos)
#define I2S_CLKCTRL_BITDELAY_LJ_Val 0x0u /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */
#define I2S_CLKCTRL_BITDELAY_I2S_Val 0x1u /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */
#define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos)
#define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos)
#define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */
#define I2S_CLKCTRL_FSSEL (0x1u << I2S_CLKCTRL_FSSEL_Pos)
#define I2S_CLKCTRL_FSSEL_SCKDIV_Val 0x0u /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */
#define I2S_CLKCTRL_FSSEL_FSPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */
#define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos)
#define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos)
#define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */
#define I2S_CLKCTRL_FSINV (0x1u << I2S_CLKCTRL_FSINV_Pos)
#define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */
#define I2S_CLKCTRL_SCKSEL (0x1u << I2S_CLKCTRL_SCKSEL_Pos)
#define I2S_CLKCTRL_SCKSEL_MCKDIV_Val 0x0u /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */
#define I2S_CLKCTRL_SCKSEL_SCKPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */
#define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos)
#define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos)
#define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */
#define I2S_CLKCTRL_MCKSEL (0x1u << I2S_CLKCTRL_MCKSEL_Pos)
#define I2S_CLKCTRL_MCKSEL_GCLK_Val 0x0u /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */
#define I2S_CLKCTRL_MCKSEL_MCKPIN_Val 0x1u /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */
#define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos)
#define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos)
#define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */
#define I2S_CLKCTRL_MCKEN (0x1u << I2S_CLKCTRL_MCKEN_Pos)
#define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */
#define I2S_CLKCTRL_MCKDIV_Msk (0x1Fu << I2S_CLKCTRL_MCKDIV_Pos)
#define I2S_CLKCTRL_MCKDIV(value) ((I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos)))
#define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */
#define I2S_CLKCTRL_MCKOUTDIV_Msk (0x1Fu << I2S_CLKCTRL_MCKOUTDIV_Pos)
#define I2S_CLKCTRL_MCKOUTDIV(value) ((I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos)))
#define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */
#define I2S_CLKCTRL_FSOUTINV (0x1u << I2S_CLKCTRL_FSOUTINV_Pos)
#define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */
#define I2S_CLKCTRL_SCKOUTINV (0x1u << I2S_CLKCTRL_SCKOUTINV_Pos)
#define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */
#define I2S_CLKCTRL_MCKOUTINV (0x1u << I2S_CLKCTRL_MCKOUTINV_Pos)
#define I2S_CLKCTRL_MASK 0xFFFD19FFu /**< \brief (I2S_CLKCTRL) MASK Register */
/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */
#define I2S_INTENCLR_RESETVALUE 0x0000 /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */
#define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */
#define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos)
#define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */
#define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos)
#define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */
#define I2S_INTENCLR_RXRDY_Msk (0x3u << I2S_INTENCLR_RXRDY_Pos)
#define I2S_INTENCLR_RXRDY(value) ((I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)))
#define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */
#define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos)
#define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */
#define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos)
#define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */
#define I2S_INTENCLR_RXOR_Msk (0x3u << I2S_INTENCLR_RXOR_Pos)
#define I2S_INTENCLR_RXOR(value) ((I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)))
#define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */
#define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos)
#define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */
#define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos)
#define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */
#define I2S_INTENCLR_TXRDY_Msk (0x3u << I2S_INTENCLR_TXRDY_Pos)
#define I2S_INTENCLR_TXRDY(value) ((I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)))
#define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */
#define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos)
#define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */
#define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos)
#define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */
#define I2S_INTENCLR_TXUR_Msk (0x3u << I2S_INTENCLR_TXUR_Pos)
#define I2S_INTENCLR_TXUR(value) ((I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)))
#define I2S_INTENCLR_MASK 0x3333u /**< \brief (I2S_INTENCLR) MASK Register */
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */
#define I2S_INTENSET_RESETVALUE 0x0000 /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */
#define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */
#define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos)
#define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */
#define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos)
#define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */
#define I2S_INTENSET_RXRDY_Msk (0x3u << I2S_INTENSET_RXRDY_Pos)
#define I2S_INTENSET_RXRDY(value) ((I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)))
#define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */
#define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos)
#define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */
#define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos)
#define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */
#define I2S_INTENSET_RXOR_Msk (0x3u << I2S_INTENSET_RXOR_Pos)
#define I2S_INTENSET_RXOR(value) ((I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)))
#define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */
#define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos)
#define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */
#define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos)
#define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */
#define I2S_INTENSET_TXRDY_Msk (0x3u << I2S_INTENSET_TXRDY_Pos)
#define I2S_INTENSET_TXRDY(value) ((I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)))
#define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */
#define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos)
#define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */
#define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos)
#define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */
#define I2S_INTENSET_TXUR_Msk (0x3u << I2S_INTENSET_TXUR_Pos)
#define I2S_INTENSET_TXUR(value) ((I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)))
#define I2S_INTENSET_MASK 0x3333u /**< \brief (I2S_INTENSET) MASK Register */
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */
#define I2S_INTFLAG_RESETVALUE 0x0000 /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */
#define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos)
#define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */
#define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos)
#define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */
#define I2S_INTFLAG_RXRDY_Msk (0x3u << I2S_INTFLAG_RXRDY_Pos)
#define I2S_INTFLAG_RXRDY(value) ((I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)))
#define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */
#define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos)
#define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */
#define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos)
#define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */
#define I2S_INTFLAG_RXOR_Msk (0x3u << I2S_INTFLAG_RXOR_Pos)
#define I2S_INTFLAG_RXOR(value) ((I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)))
#define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */
#define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos)
#define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */
#define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos)
#define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */
#define I2S_INTFLAG_TXRDY_Msk (0x3u << I2S_INTFLAG_TXRDY_Pos)
#define I2S_INTFLAG_TXRDY(value) ((I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)))
#define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */
#define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos)
#define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */
#define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos)
#define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */
#define I2S_INTFLAG_TXUR_Msk (0x3u << I2S_INTFLAG_TXUR_Pos)
#define I2S_INTFLAG_TXUR(value) ((I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)))
#define I2S_INTFLAG_MASK 0x3333u /**< \brief (I2S_INTFLAG) MASK Register */
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :2; /*!< bit: 0.. 1 Reserved */
uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */
#define I2S_SYNCBUSY_RESETVALUE 0x0000 /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */
#define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */
#define I2S_SYNCBUSY_SWRST (0x1u << I2S_SYNCBUSY_SWRST_Pos)
#define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */
#define I2S_SYNCBUSY_ENABLE (0x1u << I2S_SYNCBUSY_ENABLE_Pos)
#define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */
#define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos)
#define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */
#define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos)
#define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */
#define I2S_SYNCBUSY_CKEN_Msk (0x3u << I2S_SYNCBUSY_CKEN_Pos)
#define I2S_SYNCBUSY_CKEN(value) ((I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)))
#define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */
#define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos)
#define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */
#define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos)
#define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */
#define I2S_SYNCBUSY_SEREN_Msk (0x3u << I2S_SYNCBUSY_SEREN_Pos)
#define I2S_SYNCBUSY_SEREN(value) ((I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)))
#define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */
#define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos)
#define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */
#define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos)
#define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */
#define I2S_SYNCBUSY_DATA_Msk (0x3u << I2S_SYNCBUSY_DATA_Pos)
#define I2S_SYNCBUSY_DATA(value) ((I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)))
#define I2S_SYNCBUSY_MASK 0x033Fu /**< \brief (I2S_SYNCBUSY) MASK Register */
/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
uint32_t :1; /*!< bit: 6 Reserved */
uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
uint32_t MONO:1; /*!< bit: 24 Mono Mode */
uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
uint32_t :8; /*!< bit: 24..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} I2S_SERCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */
#define I2S_SERCTRL_RESETVALUE 0x00000000 /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */
#define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */
#define I2S_SERCTRL_SERMODE_Msk (0x3u << I2S_SERCTRL_SERMODE_Pos)
#define I2S_SERCTRL_SERMODE(value) ((I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos)))
#define I2S_SERCTRL_SERMODE_RX_Val 0x0u /**< \brief (I2S_SERCTRL) Receive */
#define I2S_SERCTRL_SERMODE_TX_Val 0x1u /**< \brief (I2S_SERCTRL) Transmit */
#define I2S_SERCTRL_SERMODE_PDM2_Val 0x2u /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */
#define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos)
#define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos)
#define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos)
#define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */
#define I2S_SERCTRL_TXDEFAULT_Msk (0x3u << I2S_SERCTRL_TXDEFAULT_Pos)
#define I2S_SERCTRL_TXDEFAULT(value) ((I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos)))
#define I2S_SERCTRL_TXDEFAULT_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Output Default Value is 0 */
#define I2S_SERCTRL_TXDEFAULT_ONE_Val 0x1u /**< \brief (I2S_SERCTRL) Output Default Value is 1 */
#define I2S_SERCTRL_TXDEFAULT_HIZ_Val 0x3u /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */
#define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos)
#define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos)
#define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos)
#define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */
#define I2S_SERCTRL_TXSAME (0x1u << I2S_SERCTRL_TXSAME_Pos)
#define I2S_SERCTRL_TXSAME_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */
#define I2S_SERCTRL_TXSAME_SAME_Val 0x1u /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */
#define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos)
#define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos)
#define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */
#define I2S_SERCTRL_CLKSEL (0x1u << I2S_SERCTRL_CLKSEL_Pos)
#define I2S_SERCTRL_CLKSEL_CLK0_Val 0x0u /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */
#define I2S_SERCTRL_CLKSEL_CLK1_Val 0x1u /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */
#define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos)
#define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos)
#define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */
#define I2S_SERCTRL_SLOTADJ (0x1u << I2S_SERCTRL_SLOTADJ_Pos)
#define I2S_SERCTRL_SLOTADJ_RIGHT_Val 0x0u /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */
#define I2S_SERCTRL_SLOTADJ_LEFT_Val 0x1u /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */
#define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos)
#define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos)
#define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */
#define I2S_SERCTRL_DATASIZE_Msk (0x7u << I2S_SERCTRL_DATASIZE_Pos)
#define I2S_SERCTRL_DATASIZE(value) ((I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos)))
#define I2S_SERCTRL_DATASIZE_32_Val 0x0u /**< \brief (I2S_SERCTRL) 32 bits */
#define I2S_SERCTRL_DATASIZE_24_Val 0x1u /**< \brief (I2S_SERCTRL) 24 bits */
#define I2S_SERCTRL_DATASIZE_20_Val 0x2u /**< \brief (I2S_SERCTRL) 20 bits */
#define I2S_SERCTRL_DATASIZE_18_Val 0x3u /**< \brief (I2S_SERCTRL) 18 bits */
#define I2S_SERCTRL_DATASIZE_16_Val 0x4u /**< \brief (I2S_SERCTRL) 16 bits */
#define I2S_SERCTRL_DATASIZE_16C_Val 0x5u /**< \brief (I2S_SERCTRL) 16 bits compact stereo */
#define I2S_SERCTRL_DATASIZE_8_Val 0x6u /**< \brief (I2S_SERCTRL) 8 bits */
#define I2S_SERCTRL_DATASIZE_8C_Val 0x7u /**< \brief (I2S_SERCTRL) 8 bits compact stereo */
#define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos)
#define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos)
#define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos)
#define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos)
#define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos)
#define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos)
#define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos)
#define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos)
#define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */
#define I2S_SERCTRL_WORDADJ (0x1u << I2S_SERCTRL_WORDADJ_Pos)
#define I2S_SERCTRL_WORDADJ_RIGHT_Val 0x0u /**< \brief (I2S_SERCTRL) Data is right adjusted in word */
#define I2S_SERCTRL_WORDADJ_LEFT_Val 0x1u /**< \brief (I2S_SERCTRL) Data is left adjusted in word */
#define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos)
#define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos)
#define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */
#define I2S_SERCTRL_EXTEND_Msk (0x3u << I2S_SERCTRL_EXTEND_Pos)
#define I2S_SERCTRL_EXTEND(value) ((I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos)))
#define I2S_SERCTRL_EXTEND_ZERO_Val 0x0u /**< \brief (I2S_SERCTRL) Extend with zeroes */
#define I2S_SERCTRL_EXTEND_ONE_Val 0x1u /**< \brief (I2S_SERCTRL) Extend with ones */
#define I2S_SERCTRL_EXTEND_MSBIT_Val 0x2u /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */
#define I2S_SERCTRL_EXTEND_LSBIT_Val 0x3u /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */
#define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos)
#define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos)
#define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
#define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos)
#define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */
#define I2S_SERCTRL_BITREV (0x1u << I2S_SERCTRL_BITREV_Pos)
#define I2S_SERCTRL_BITREV_MSBIT_Val 0x0u /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */
#define I2S_SERCTRL_BITREV_LSBIT_Val 0x1u /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */
#define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos)
#define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos)
#define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */
#define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos)
#define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */
#define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos)
#define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */
#define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos)
#define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */
#define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos)
#define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */
#define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos)
#define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */
#define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos)
#define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */
#define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos)
#define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */
#define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos)
#define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */
#define I2S_SERCTRL_SLOTDIS_Msk (0xFFu << I2S_SERCTRL_SLOTDIS_Pos)
#define I2S_SERCTRL_SLOTDIS(value) ((I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)))
#define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */
#define I2S_SERCTRL_MONO (0x1u << I2S_SERCTRL_MONO_Pos)
#define I2S_SERCTRL_MONO_STEREO_Val 0x0u /**< \brief (I2S_SERCTRL) Normal mode */
#define I2S_SERCTRL_MONO_MONO_Val 0x1u /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */
#define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos)
#define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos)
#define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */
#define I2S_SERCTRL_DMA (0x1u << I2S_SERCTRL_DMA_Pos)
#define I2S_SERCTRL_DMA_SINGLE_Val 0x0u /**< \brief (I2S_SERCTRL) Single DMA channel */
#define I2S_SERCTRL_DMA_MULTIPLE_Val 0x1u /**< \brief (I2S_SERCTRL) One DMA channel per data channel */
#define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos)
#define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos)
#define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */
#define I2S_SERCTRL_RXLOOP (0x1u << I2S_SERCTRL_RXLOOP_Pos)
#define I2S_SERCTRL_MASK 0x07FFF7BFu /**< \brief (I2S_SERCTRL) MASK Register */
/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} I2S_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */
#define I2S_DATA_RESETVALUE 0x00000000 /**< \brief (I2S_DATA reset_value) Data n */
#define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */
#define I2S_DATA_DATA_Msk (0xFFFFFFFFu << I2S_DATA_DATA_Pos)
#define I2S_DATA_DATA(value) ((I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos)))
#define I2S_DATA_MASK 0xFFFFFFFFu /**< \brief (I2S_DATA) MASK Register */
/** \brief I2S hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
RoReg8 Reserved1[0x3];
__IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
__IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
RoReg8 Reserved2[0x2];
__IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
RoReg8 Reserved3[0x2];
__IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x2];
__I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
RoReg8 Reserved5[0x6];
__IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
RoReg8 Reserved6[0x8];
__IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
} I2s;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_I2S_COMPONENT_ */

396
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/mtb.h Normal file
View file

@ -0,0 +1,396 @@
/**
* \file
*
* \brief Component description for MTB
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_MTB_COMPONENT_
#define _SAMD21_MTB_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR MTB */
/* ========================================================================== */
/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
/*@{*/
#define MTB_U2002
#define REV_MTB 0x100
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_POSITION_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
#define MTB_POSITION_WRAP (0x1u << MTB_POSITION_WRAP_Pos)
#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
#define MTB_POSITION_POINTER_Msk (0x1FFFFFFFu << MTB_POSITION_POINTER_Pos)
#define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)))
#define MTB_POSITION_MASK 0xFFFFFFFCu /**< \brief (MTB_POSITION) MASK Register */
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
uint32_t :21; /*!< bit: 10..30 Reserved */
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_MASTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
#define MTB_MASTER_RESETVALUE 0x00000000 /**< \brief (MTB_MASTER reset_value) MTB Master */
#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
#define MTB_MASTER_MASK_Msk (0x1Fu << MTB_MASTER_MASK_Pos)
#define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)))
#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
#define MTB_MASTER_TSTARTEN (0x1u << MTB_MASTER_TSTARTEN_Pos)
#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
#define MTB_MASTER_TSTOPEN (0x1u << MTB_MASTER_TSTOPEN_Pos)
#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
#define MTB_MASTER_SFRWPRIV (0x1u << MTB_MASTER_SFRWPRIV_Pos)
#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
#define MTB_MASTER_RAMPRIV (0x1u << MTB_MASTER_RAMPRIV_Pos)
#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
#define MTB_MASTER_HALTREQ (0x1u << MTB_MASTER_HALTREQ_Pos)
#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
#define MTB_MASTER_EN (0x1u << MTB_MASTER_EN_Pos)
#define MTB_MASTER_MASK_ 0x800003FFu /**< \brief (MTB_MASTER) MASK Register */
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
uint32_t :1; /*!< bit: 2 Reserved */
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_FLOW_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
#define MTB_FLOW_RESETVALUE 0x00000000 /**< \brief (MTB_FLOW reset_value) MTB Flow */
#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
#define MTB_FLOW_AUTOSTOP (0x1u << MTB_FLOW_AUTOSTOP_Pos)
#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
#define MTB_FLOW_AUTOHALT (0x1u << MTB_FLOW_AUTOHALT_Pos)
#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
#define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFu << MTB_FLOW_WATERMARK_Pos)
#define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)))
#define MTB_FLOW_MASK 0xFFFFFFFBu /**< \brief (MTB_FLOW) MASK Register */
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_BASE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
#define MTB_BASE_MASK 0xFFFFFFFFu /**< \brief (MTB_BASE) MASK Register */
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_ITCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
#define MTB_ITCTRL_MASK 0xFFFFFFFFu /**< \brief (MTB_ITCTRL) MASK Register */
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
#define MTB_CLAIMSET_MASK 0xFFFFFFFFu /**< \brief (MTB_CLAIMSET) MASK Register */
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
#define MTB_CLAIMCLR_MASK 0xFFFFFFFFu /**< \brief (MTB_CLAIMCLR) MASK Register */
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKACCESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
#define MTB_LOCKACCESS_MASK 0xFFFFFFFFu /**< \brief (MTB_LOCKACCESS) MASK Register */
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
#define MTB_LOCKSTATUS_MASK 0xFFFFFFFFu /**< \brief (MTB_LOCKSTATUS) MASK Register */
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_AUTHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
#define MTB_AUTHSTATUS_MASK 0xFFFFFFFFu /**< \brief (MTB_AUTHSTATUS) MASK Register */
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_DEVARCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
#define MTB_DEVARCH_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVARCH) MASK Register */
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_DEVID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
#define MTB_DEVID_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVID) MASK Register */
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_DEVTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
#define MTB_DEVTYPE_MASK 0xFFFFFFFFu /**< \brief (MTB_DEVTYPE) MASK Register */
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
#define MTB_PID4_MASK 0xFFFFFFFFu /**< \brief (MTB_PID4) MASK Register */
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
#define MTB_PID5_MASK 0xFFFFFFFFu /**< \brief (MTB_PID5) MASK Register */
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
#define MTB_PID6_MASK 0xFFFFFFFFu /**< \brief (MTB_PID6) MASK Register */
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
#define MTB_PID7_MASK 0xFFFFFFFFu /**< \brief (MTB_PID7) MASK Register */
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
#define MTB_PID0_MASK 0xFFFFFFFFu /**< \brief (MTB_PID0) MASK Register */
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
#define MTB_PID1_MASK 0xFFFFFFFFu /**< \brief (MTB_PID1) MASK Register */
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
#define MTB_PID2_MASK 0xFFFFFFFFu /**< \brief (MTB_PID2) MASK Register */
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
#define MTB_PID3_MASK 0xFFFFFFFFu /**< \brief (MTB_PID3) MASK Register */
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
#define MTB_CID0_MASK 0xFFFFFFFFu /**< \brief (MTB_CID0) MASK Register */
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
#define MTB_CID1_MASK 0xFFFFFFFFu /**< \brief (MTB_CID1) MASK Register */
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
#define MTB_CID2_MASK 0xFFFFFFFFu /**< \brief (MTB_CID2) MASK Register */
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
#define MTB_CID3_MASK 0xFFFFFFFFu /**< \brief (MTB_CID3) MASK Register */
/** \brief MTB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
RoReg8 Reserved1[0xEF0];
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
RoReg8 Reserved2[0x9C];
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
RoReg8 Reserved3[0x8];
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
RoReg8 Reserved4[0x8];
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
} Mtb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_MTB_COMPONENT_ */

530
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/nvmctrl.h Normal file
View file

@ -0,0 +1,530 @@
/**
* \file
*
* \brief Component description for NVMCTRL
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_NVMCTRL_COMPONENT_
#define _SAMD21_NVMCTRL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR NVMCTRL */
/* ========================================================================== */
/** \addtogroup SAMD21_NVMCTRL Non-Volatile Memory Controller */
/*@{*/
#define NVMCTRL_U2207
#define REV_NVMCTRL 0x106
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CMD:7; /*!< bit: 0.. 6 Command */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
#define NVMCTRL_CTRLA_RESETVALUE 0x0000 /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
#define NVMCTRL_CTRLA_CMD_Msk (0x7Fu << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD(value) ((NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)))
#define NVMCTRL_CTRLA_CMD_ER_Val 0x2u /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
#define NVMCTRL_CTRLA_CMD_WP_Val 0x4u /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
#define NVMCTRL_CTRLA_CMD_EAR_Val 0x5u /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
#define NVMCTRL_CTRLA_CMD_WAP_Val 0x6u /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
#define NVMCTRL_CTRLA_CMD_SF_Val 0xAu /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
#define NVMCTRL_CTRLA_CMD_WL_Val 0xFu /**< \brief (NVMCTRL_CTRLA) Write lockbits */
#define NVMCTRL_CTRLA_CMD_LR_Val 0x40u /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
#define NVMCTRL_CTRLA_CMD_UR_Val 0x41u /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
#define NVMCTRL_CTRLA_CMD_SPRM_Val 0x42u /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
#define NVMCTRL_CTRLA_CMD_CPRM_Val 0x43u /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
#define NVMCTRL_CTRLA_CMD_PBC_Val 0x44u /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
#define NVMCTRL_CTRLA_CMD_SSB_Val 0x45u /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
#define NVMCTRL_CTRLA_CMD_INVALL_Val 0x46u /**< \brief (NVMCTRL_CTRLA) Invalidates all cache lines. */
#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
#define NVMCTRL_CTRLA_CMDEX_Msk (0xFFu << NVMCTRL_CTRLA_CMDEX_Pos)
#define NVMCTRL_CTRLA_CMDEX(value) ((NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)))
#define NVMCTRL_CTRLA_CMDEX_KEY_Val 0xA5u /**< \brief (NVMCTRL_CTRLA) Execution Key */
#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
#define NVMCTRL_CTRLA_MASK 0xFF7Fu /**< \brief (NVMCTRL_CTRLA) MASK Register */
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t MANW:1; /*!< bit: 7 Manual Write */
uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
#define NVMCTRL_CTRLB_RESETVALUE 0x00000000 /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
#define NVMCTRL_CTRLB_RWS_Msk (0xFu << NVMCTRL_CTRLB_RWS_Pos)
#define NVMCTRL_CTRLB_RWS(value) ((NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)))
#define NVMCTRL_CTRLB_RWS_SINGLE_Val 0x0u /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
#define NVMCTRL_CTRLB_RWS_HALF_Val 0x1u /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
#define NVMCTRL_CTRLB_RWS_DUAL_Val 0x2u /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
#define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos)
#define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos)
#define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos)
#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */
#define NVMCTRL_CTRLB_MANW (0x1u << NVMCTRL_CTRLB_MANW_Pos)
#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
#define NVMCTRL_CTRLB_SLEEPPRM_Msk (0x3u << NVMCTRL_CTRLB_SLEEPPRM_Pos)
#define NVMCTRL_CTRLB_SLEEPPRM(value) ((NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)))
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val 0x0u /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val 0x1u /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val 0x3u /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
#define NVMCTRL_CTRLB_READMODE_Msk (0x3u << NVMCTRL_CTRLB_READMODE_Pos)
#define NVMCTRL_CTRLB_READMODE(value) ((NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)))
#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val 0x0u /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val 0x1u /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val 0x2u /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */
#define NVMCTRL_CTRLB_CACHEDIS (0x1u << NVMCTRL_CTRLB_CACHEDIS_Pos)
#define NVMCTRL_CTRLB_MASK 0x0007039Eu /**< \brief (NVMCTRL_CTRLB) MASK Register */
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
#define NVMCTRL_PARAM_RESETVALUE 0x00000000 /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
#define NVMCTRL_PARAM_NVMP_Msk (0xFFFFu << NVMCTRL_PARAM_NVMP_Pos)
#define NVMCTRL_PARAM_NVMP(value) ((NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)))
#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
#define NVMCTRL_PARAM_PSZ_Msk (0x7u << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ(value) ((NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)))
#define NVMCTRL_PARAM_PSZ_8_Val 0x0u /**< \brief (NVMCTRL_PARAM) 8 bytes */
#define NVMCTRL_PARAM_PSZ_16_Val 0x1u /**< \brief (NVMCTRL_PARAM) 16 bytes */
#define NVMCTRL_PARAM_PSZ_32_Val 0x2u /**< \brief (NVMCTRL_PARAM) 32 bytes */
#define NVMCTRL_PARAM_PSZ_64_Val 0x3u /**< \brief (NVMCTRL_PARAM) 64 bytes */
#define NVMCTRL_PARAM_PSZ_128_Val 0x4u /**< \brief (NVMCTRL_PARAM) 128 bytes */
#define NVMCTRL_PARAM_PSZ_256_Val 0x5u /**< \brief (NVMCTRL_PARAM) 256 bytes */
#define NVMCTRL_PARAM_PSZ_512_Val 0x6u /**< \brief (NVMCTRL_PARAM) 512 bytes */
#define NVMCTRL_PARAM_PSZ_1024_Val 0x7u /**< \brief (NVMCTRL_PARAM) 1024 bytes */
#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_MASK 0x0007FFFFu /**< \brief (NVMCTRL_PARAM) MASK Register */
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
#define NVMCTRL_INTENCLR_RESETVALUE 0x00 /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
#define NVMCTRL_INTENCLR_READY (0x1u << NVMCTRL_INTENCLR_READY_Pos)
#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
#define NVMCTRL_INTENCLR_ERROR (0x1u << NVMCTRL_INTENCLR_ERROR_Pos)
#define NVMCTRL_INTENCLR_MASK 0x03u /**< \brief (NVMCTRL_INTENCLR) MASK Register */
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
#define NVMCTRL_INTENSET_RESETVALUE 0x00 /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
#define NVMCTRL_INTENSET_READY (0x1u << NVMCTRL_INTENSET_READY_Pos)
#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
#define NVMCTRL_INTENSET_ERROR (0x1u << NVMCTRL_INTENSET_ERROR_Pos)
#define NVMCTRL_INTENSET_MASK 0x03u /**< \brief (NVMCTRL_INTENSET) MASK Register */
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready */
uint8_t ERROR:1; /*!< bit: 1 Error */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
#define NVMCTRL_INTFLAG_RESETVALUE 0x00 /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
#define NVMCTRL_INTFLAG_READY (0x1u << NVMCTRL_INTFLAG_READY_Pos)
#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */
#define NVMCTRL_INTFLAG_ERROR (0x1u << NVMCTRL_INTFLAG_ERROR_Pos)
#define NVMCTRL_INTFLAG_MASK 0x03u /**< \brief (NVMCTRL_INTFLAG) MASK Register */
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
uint16_t NVME:1; /*!< bit: 4 NVM Error */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t SB:1; /*!< bit: 8 Security Bit Status */
uint16_t :7; /*!< bit: 9..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */
#define NVMCTRL_STATUS_RESETVALUE 0x0000 /**< \brief (NVMCTRL_STATUS reset_value) Status */
#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
#define NVMCTRL_STATUS_PRM (0x1u << NVMCTRL_STATUS_PRM_Pos)
#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
#define NVMCTRL_STATUS_LOAD (0x1u << NVMCTRL_STATUS_LOAD_Pos)
#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */
#define NVMCTRL_STATUS_PROGE (0x1u << NVMCTRL_STATUS_PROGE_Pos)
#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */
#define NVMCTRL_STATUS_LOCKE (0x1u << NVMCTRL_STATUS_LOCKE_Pos)
#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */
#define NVMCTRL_STATUS_NVME (0x1u << NVMCTRL_STATUS_NVME_Pos)
#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */
#define NVMCTRL_STATUS_SB (0x1u << NVMCTRL_STATUS_SB_Pos)
#define NVMCTRL_STATUS_MASK 0x011Fu /**< \brief (NVMCTRL_STATUS) MASK Register */
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */
#define NVMCTRL_ADDR_RESETVALUE 0x00000000 /**< \brief (NVMCTRL_ADDR reset_value) Address */
#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
#define NVMCTRL_ADDR_ADDR_Msk (0x3FFFFFu << NVMCTRL_ADDR_ADDR_Pos)
#define NVMCTRL_ADDR_ADDR(value) ((NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)))
#define NVMCTRL_ADDR_MASK 0x003FFFFFu /**< \brief (NVMCTRL_ADDR) MASK Register */
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_LOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */
#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
#define NVMCTRL_LOCK_LOCK_Msk (0xFFFFu << NVMCTRL_LOCK_LOCK_Pos)
#define NVMCTRL_LOCK_LOCK(value) ((NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)))
#define NVMCTRL_LOCK_MASK 0xFFFFu /**< \brief (NVMCTRL_LOCK) MASK Register */
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
RoReg8 Reserved1[0x2];
__IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
__IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
__IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
RoReg8 Reserved2[0x3];
__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
RoReg8 Reserved3[0x3];
__IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x3];
__IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
RoReg8 Reserved5[0x2];
__IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
__IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_CAL
#define SECTION_NVMCTRL_LOCKBIT
#define SECTION_NVMCTRL_OTP1
#define SECTION_NVMCTRL_OTP2
#define SECTION_NVMCTRL_OTP4
#define SECTION_NVMCTRL_TEMP_LOG
#define SECTION_NVMCTRL_USER
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
/* ************************************************************************** */
/** \addtogroup fuses_api Peripheral Software API */
/*@{*/
#define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4)
#define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */
#define ADC_FUSES_BIASCAL_Msk (0x7u << ADC_FUSES_BIASCAL_Pos)
#define ADC_FUSES_BIASCAL(value) ((ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)))
#define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4
#define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */
#define ADC_FUSES_LINEARITY_0_Msk (0x1Fu << ADC_FUSES_LINEARITY_0_Pos)
#define ADC_FUSES_LINEARITY_0(value) ((ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)))
#define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4)
#define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */
#define ADC_FUSES_LINEARITY_1_Msk (0x7u << ADC_FUSES_LINEARITY_1_Pos)
#define ADC_FUSES_LINEARITY_1(value) ((ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)))
#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
#define NVMCTRL_FUSES_BOOTPROT_Msk (0x7u << NVMCTRL_FUSES_BOOTPROT_Pos)
#define NVMCTRL_FUSES_BOOTPROT(value) ((NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)))
#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (0x7u << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
#define NVMCTRL_FUSES_EEPROM_SIZE(value) ((NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)))
#define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
#define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */
#define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)
#define NVMCTRL_FUSES_HOT_ADC_VAL(value) ((NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)))
#define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
#define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */
#define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)
#define NVMCTRL_FUSES_HOT_INT1V_VAL(value) ((NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)))
#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */
#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)
#define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)))
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)
#define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)))
#define NVMCTRL_FUSES_NVMP_ADDR NVMCTRL_OTP1
#define NVMCTRL_FUSES_NVMP_Pos 16 /**< \brief (NVMCTRL_OTP1) Number of NVM Pages */
#define NVMCTRL_FUSES_NVMP_Msk (0xFFFFu << NVMCTRL_FUSES_NVMP_Pos)
#define NVMCTRL_FUSES_NVMP(value) ((NVMCTRL_FUSES_NVMP_Msk & ((value) << NVMCTRL_FUSES_NVMP_Pos)))
#define NVMCTRL_FUSES_NVM_LOCK_ADDR NVMCTRL_OTP1
#define NVMCTRL_FUSES_NVM_LOCK_Pos 0 /**< \brief (NVMCTRL_OTP1) NVM Lock */
#define NVMCTRL_FUSES_NVM_LOCK_Msk (0xFFu << NVMCTRL_FUSES_NVM_LOCK_Pos)
#define NVMCTRL_FUSES_NVM_LOCK(value) ((NVMCTRL_FUSES_NVM_LOCK_Msk & ((value) << NVMCTRL_FUSES_NVM_LOCK_Pos)))
#define NVMCTRL_FUSES_PSZ_ADDR NVMCTRL_OTP1
#define NVMCTRL_FUSES_PSZ_Pos 8 /**< \brief (NVMCTRL_OTP1) NVM Page Size */
#define NVMCTRL_FUSES_PSZ_Msk (0xFu << NVMCTRL_FUSES_PSZ_Pos)
#define NVMCTRL_FUSES_PSZ(value) ((NVMCTRL_FUSES_PSZ_Msk & ((value) << NVMCTRL_FUSES_PSZ_Pos)))
#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
#define NVMCTRL_FUSES_REGION_LOCKS_Msk (0xFFFFu << NVMCTRL_FUSES_REGION_LOCKS_Pos)
#define NVMCTRL_FUSES_REGION_LOCKS(value) ((NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)))
#define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4)
#define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */
#define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (0xFFFu << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)
#define NVMCTRL_FUSES_ROOM_ADC_VAL(value) ((NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)))
#define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG
#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */
#define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (0xFFu << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)
#define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) ((NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)))
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (0xFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)))
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (0xFFu << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)
#define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) ((NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)))
#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER
#define SYSCTRL_FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */
#define SYSCTRL_FUSES_BOD33USERLEVEL_Msk (0x3Fu << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)
#define SYSCTRL_FUSES_BOD33USERLEVEL(value) ((SYSCTRL_FUSES_BOD33USERLEVEL_Msk & ((value) << SYSCTRL_FUSES_BOD33USERLEVEL_Pos)))
#define SYSCTRL_FUSES_BOD33_ACTION_ADDR NVMCTRL_USER
#define SYSCTRL_FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */
#define SYSCTRL_FUSES_BOD33_ACTION_Msk (0x3u << SYSCTRL_FUSES_BOD33_ACTION_Pos)
#define SYSCTRL_FUSES_BOD33_ACTION(value) ((SYSCTRL_FUSES_BOD33_ACTION_Msk & ((value) << SYSCTRL_FUSES_BOD33_ACTION_Pos)))
#define SYSCTRL_FUSES_BOD33_EN_ADDR NVMCTRL_USER
#define SYSCTRL_FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */
#define SYSCTRL_FUSES_BOD33_EN_Msk (0x1u << SYSCTRL_FUSES_BOD33_EN_Pos)
#define SYSCTRL_FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4)
#define SYSCTRL_FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */
#define SYSCTRL_FUSES_BOD33_HYST_Msk (0x1u << SYSCTRL_FUSES_BOD33_HYST_Pos)
#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4)
#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */
#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk (0x3Fu << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)
#define SYSCTRL_FUSES_DFLL48M_COARSE_CAL(value) ((SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << SYSCTRL_FUSES_DFLL48M_COARSE_CAL_Pos)))
#define SYSCTRL_FUSES_OSC32K_CAL_ADDR (NVMCTRL_OTP4 + 4)
#define SYSCTRL_FUSES_OSC32K_CAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */
#define SYSCTRL_FUSES_OSC32K_CAL_Msk (0x7Fu << SYSCTRL_FUSES_OSC32K_CAL_Pos)
#define SYSCTRL_FUSES_OSC32K_CAL(value) ((SYSCTRL_FUSES_OSC32K_CAL_Msk & ((value) << SYSCTRL_FUSES_OSC32K_CAL_Pos)))
#define USB_FUSES_TRANSN_ADDR (NVMCTRL_OTP4 + 4)
#define USB_FUSES_TRANSN_Pos 13 /**< \brief (NVMCTRL_OTP4) USB pad Transn calibration */
#define USB_FUSES_TRANSN_Msk (0x1Fu << USB_FUSES_TRANSN_Pos)
#define USB_FUSES_TRANSN(value) ((USB_FUSES_TRANSN_Msk & ((value) << USB_FUSES_TRANSN_Pos)))
#define USB_FUSES_TRANSP_ADDR (NVMCTRL_OTP4 + 4)
#define USB_FUSES_TRANSP_Pos 18 /**< \brief (NVMCTRL_OTP4) USB pad Transp calibration */
#define USB_FUSES_TRANSP_Msk (0x1Fu << USB_FUSES_TRANSP_Pos)
#define USB_FUSES_TRANSP(value) ((USB_FUSES_TRANSP_Msk & ((value) << USB_FUSES_TRANSP_Pos)))
#define USB_FUSES_TRIM_ADDR (NVMCTRL_OTP4 + 4)
#define USB_FUSES_TRIM_Pos 23 /**< \brief (NVMCTRL_OTP4) USB pad Trim calibration */
#define USB_FUSES_TRIM_Msk (0x7u << USB_FUSES_TRIM_Pos)
#define USB_FUSES_TRIM(value) ((USB_FUSES_TRIM_Msk & ((value) << USB_FUSES_TRIM_Pos)))
#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
#define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */
#define WDT_FUSES_ALWAYSON_Msk (0x1u << WDT_FUSES_ALWAYSON_Pos)
#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER
#define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */
#define WDT_FUSES_ENABLE_Msk (0x1u << WDT_FUSES_ENABLE_Pos)
#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
#define WDT_FUSES_EWOFFSET_Msk (0xFu << WDT_FUSES_EWOFFSET_Pos)
#define WDT_FUSES_EWOFFSET(value) ((WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)))
#define WDT_FUSES_PER_ADDR NVMCTRL_USER
#define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */
#define WDT_FUSES_PER_Msk (0xFu << WDT_FUSES_PER_Pos)
#define WDT_FUSES_PER(value) ((WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)))
#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
#define WDT_FUSES_WEN_Msk (0x1u << WDT_FUSES_WEN_Pos)
#define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER
#define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */
#define WDT_FUSES_WINDOW_0_Msk (0x1u << WDT_FUSES_WINDOW_0_Pos)
#define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */
#define WDT_FUSES_WINDOW_1_Msk (0x7u << WDT_FUSES_WINDOW_1_Pos)
#define WDT_FUSES_WINDOW_1(value) ((WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)))
/*@}*/
#endif /* _SAMD21_NVMCTRL_COMPONENT_ */

104
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/pac.h Normal file
View file

@ -0,0 +1,104 @@
/**
* \file
*
* \brief Component description for PAC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_PAC_COMPONENT_
#define _SAMD21_PAC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PAC */
/* ========================================================================== */
/** \addtogroup SAMD21_PAC Peripheral Access Controller */
/*@{*/
#define PAC_U2211
#define REV_PAC 0x101
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WPCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */
#define PAC_WPCLR_RESETVALUE 0x00000000 /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */
#define PAC_WPCLR_WP_Msk (0x7FFFFFFFu << PAC_WPCLR_WP_Pos)
#define PAC_WPCLR_WP(value) ((PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)))
#define PAC_WPCLR_MASK 0xFFFFFFFEu /**< \brief (PAC_WPCLR) MASK Register */
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WPSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */
#define PAC_WPSET_RESETVALUE 0x00000000 /**< \brief (PAC_WPSET reset_value) Write Protection Set */
#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */
#define PAC_WPSET_WP_Msk (0x7FFFFFFFu << PAC_WPSET_WP_Pos)
#define PAC_WPSET_WP(value) ((PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)))
#define PAC_WPSET_MASK 0xFFFFFFFEu /**< \brief (PAC_WPSET) MASK Register */
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_PAC_COMPONENT_ */

530
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/pm.h Normal file
View file

@ -0,0 +1,530 @@
/**
* \file
*
* \brief Component description for PM
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_PM_COMPONENT_
#define _SAMD21_PM_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PM */
/* ========================================================================== */
/** \addtogroup SAMD21_PM Power Manager */
/*@{*/
#define PM_U2206
#define REV_PM 0x201
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint8_t reg; /*!< Type used for register access */
} PM_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_CTRL_OFFSET 0x00 /**< \brief (PM_CTRL offset) Control */
#define PM_CTRL_RESETVALUE 0x00 /**< \brief (PM_CTRL reset_value) Control */
#define PM_CTRL_MASK 0x00u /**< \brief (PM_CTRL) MASK Register */
/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_SLEEP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_SLEEP_OFFSET 0x01 /**< \brief (PM_SLEEP offset) Sleep Mode */
#define PM_SLEEP_RESETVALUE 0x00 /**< \brief (PM_SLEEP reset_value) Sleep Mode */
#define PM_SLEEP_IDLE_Pos 0 /**< \brief (PM_SLEEP) Idle Mode Configuration */
#define PM_SLEEP_IDLE_Msk (0x3u << PM_SLEEP_IDLE_Pos)
#define PM_SLEEP_IDLE(value) ((PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos)))
#define PM_SLEEP_IDLE_CPU_Val 0x0u /**< \brief (PM_SLEEP) The CPU clock domain is stopped */
#define PM_SLEEP_IDLE_AHB_Val 0x1u /**< \brief (PM_SLEEP) The CPU and AHB clock domains are stopped */
#define PM_SLEEP_IDLE_APB_Val 0x2u /**< \brief (PM_SLEEP) The CPU, AHB and APB clock domains are stopped */
#define PM_SLEEP_IDLE_CPU (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)
#define PM_SLEEP_IDLE_AHB (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)
#define PM_SLEEP_IDLE_APB (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)
#define PM_SLEEP_MASK 0x03u /**< \brief (PM_SLEEP) MASK Register */
/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_CPUSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_CPUSEL_OFFSET 0x08 /**< \brief (PM_CPUSEL offset) CPU Clock Select */
#define PM_CPUSEL_RESETVALUE 0x00 /**< \brief (PM_CPUSEL reset_value) CPU Clock Select */
#define PM_CPUSEL_CPUDIV_Pos 0 /**< \brief (PM_CPUSEL) CPU Prescaler Selection */
#define PM_CPUSEL_CPUDIV_Msk (0x7u << PM_CPUSEL_CPUDIV_Pos)
#define PM_CPUSEL_CPUDIV(value) ((PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos)))
#define PM_CPUSEL_CPUDIV_DIV1_Val 0x0u /**< \brief (PM_CPUSEL) Divide by 1 */
#define PM_CPUSEL_CPUDIV_DIV2_Val 0x1u /**< \brief (PM_CPUSEL) Divide by 2 */
#define PM_CPUSEL_CPUDIV_DIV4_Val 0x2u /**< \brief (PM_CPUSEL) Divide by 4 */
#define PM_CPUSEL_CPUDIV_DIV8_Val 0x3u /**< \brief (PM_CPUSEL) Divide by 8 */
#define PM_CPUSEL_CPUDIV_DIV16_Val 0x4u /**< \brief (PM_CPUSEL) Divide by 16 */
#define PM_CPUSEL_CPUDIV_DIV32_Val 0x5u /**< \brief (PM_CPUSEL) Divide by 32 */
#define PM_CPUSEL_CPUDIV_DIV64_Val 0x6u /**< \brief (PM_CPUSEL) Divide by 64 */
#define PM_CPUSEL_CPUDIV_DIV128_Val 0x7u /**< \brief (PM_CPUSEL) Divide by 128 */
#define PM_CPUSEL_CPUDIV_DIV1 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)
#define PM_CPUSEL_CPUDIV_DIV2 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)
#define PM_CPUSEL_CPUDIV_DIV4 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)
#define PM_CPUSEL_CPUDIV_DIV8 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)
#define PM_CPUSEL_CPUDIV_DIV16 (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos)
#define PM_CPUSEL_CPUDIV_DIV32 (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos)
#define PM_CPUSEL_CPUDIV_DIV64 (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos)
#define PM_CPUSEL_CPUDIV_DIV128 (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos)
#define PM_CPUSEL_MASK 0x07u /**< \brief (PM_CPUSEL) MASK Register */
/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBASEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_APBASEL_OFFSET 0x09 /**< \brief (PM_APBASEL offset) APBA Clock Select */
#define PM_APBASEL_RESETVALUE 0x00 /**< \brief (PM_APBASEL reset_value) APBA Clock Select */
#define PM_APBASEL_APBADIV_Pos 0 /**< \brief (PM_APBASEL) APBA Prescaler Selection */
#define PM_APBASEL_APBADIV_Msk (0x7u << PM_APBASEL_APBADIV_Pos)
#define PM_APBASEL_APBADIV(value) ((PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos)))
#define PM_APBASEL_APBADIV_DIV1_Val 0x0u /**< \brief (PM_APBASEL) Divide by 1 */
#define PM_APBASEL_APBADIV_DIV2_Val 0x1u /**< \brief (PM_APBASEL) Divide by 2 */
#define PM_APBASEL_APBADIV_DIV4_Val 0x2u /**< \brief (PM_APBASEL) Divide by 4 */
#define PM_APBASEL_APBADIV_DIV8_Val 0x3u /**< \brief (PM_APBASEL) Divide by 8 */
#define PM_APBASEL_APBADIV_DIV16_Val 0x4u /**< \brief (PM_APBASEL) Divide by 16 */
#define PM_APBASEL_APBADIV_DIV32_Val 0x5u /**< \brief (PM_APBASEL) Divide by 32 */
#define PM_APBASEL_APBADIV_DIV64_Val 0x6u /**< \brief (PM_APBASEL) Divide by 64 */
#define PM_APBASEL_APBADIV_DIV128_Val 0x7u /**< \brief (PM_APBASEL) Divide by 128 */
#define PM_APBASEL_APBADIV_DIV1 (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos)
#define PM_APBASEL_APBADIV_DIV2 (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos)
#define PM_APBASEL_APBADIV_DIV4 (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos)
#define PM_APBASEL_APBADIV_DIV8 (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos)
#define PM_APBASEL_APBADIV_DIV16 (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos)
#define PM_APBASEL_APBADIV_DIV32 (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos)
#define PM_APBASEL_APBADIV_DIV64 (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos)
#define PM_APBASEL_APBADIV_DIV128 (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos)
#define PM_APBASEL_MASK 0x07u /**< \brief (PM_APBASEL) MASK Register */
/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBBSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_APBBSEL_OFFSET 0x0A /**< \brief (PM_APBBSEL offset) APBB Clock Select */
#define PM_APBBSEL_RESETVALUE 0x00 /**< \brief (PM_APBBSEL reset_value) APBB Clock Select */
#define PM_APBBSEL_APBBDIV_Pos 0 /**< \brief (PM_APBBSEL) APBB Prescaler Selection */
#define PM_APBBSEL_APBBDIV_Msk (0x7u << PM_APBBSEL_APBBDIV_Pos)
#define PM_APBBSEL_APBBDIV(value) ((PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos)))
#define PM_APBBSEL_APBBDIV_DIV1_Val 0x0u /**< \brief (PM_APBBSEL) Divide by 1 */
#define PM_APBBSEL_APBBDIV_DIV2_Val 0x1u /**< \brief (PM_APBBSEL) Divide by 2 */
#define PM_APBBSEL_APBBDIV_DIV4_Val 0x2u /**< \brief (PM_APBBSEL) Divide by 4 */
#define PM_APBBSEL_APBBDIV_DIV8_Val 0x3u /**< \brief (PM_APBBSEL) Divide by 8 */
#define PM_APBBSEL_APBBDIV_DIV16_Val 0x4u /**< \brief (PM_APBBSEL) Divide by 16 */
#define PM_APBBSEL_APBBDIV_DIV32_Val 0x5u /**< \brief (PM_APBBSEL) Divide by 32 */
#define PM_APBBSEL_APBBDIV_DIV64_Val 0x6u /**< \brief (PM_APBBSEL) Divide by 64 */
#define PM_APBBSEL_APBBDIV_DIV128_Val 0x7u /**< \brief (PM_APBBSEL) Divide by 128 */
#define PM_APBBSEL_APBBDIV_DIV1 (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos)
#define PM_APBBSEL_APBBDIV_DIV2 (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos)
#define PM_APBBSEL_APBBDIV_DIV4 (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos)
#define PM_APBBSEL_APBBDIV_DIV8 (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos)
#define PM_APBBSEL_APBBDIV_DIV16 (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos)
#define PM_APBBSEL_APBBDIV_DIV32 (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos)
#define PM_APBBSEL_APBBDIV_DIV64 (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos)
#define PM_APBBSEL_APBBDIV_DIV128 (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos)
#define PM_APBBSEL_MASK 0x07u /**< \brief (PM_APBBSEL) MASK Register */
/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBCSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_APBCSEL_OFFSET 0x0B /**< \brief (PM_APBCSEL offset) APBC Clock Select */
#define PM_APBCSEL_RESETVALUE 0x00 /**< \brief (PM_APBCSEL reset_value) APBC Clock Select */
#define PM_APBCSEL_APBCDIV_Pos 0 /**< \brief (PM_APBCSEL) APBC Prescaler Selection */
#define PM_APBCSEL_APBCDIV_Msk (0x7u << PM_APBCSEL_APBCDIV_Pos)
#define PM_APBCSEL_APBCDIV(value) ((PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos)))
#define PM_APBCSEL_APBCDIV_DIV1_Val 0x0u /**< \brief (PM_APBCSEL) Divide by 1 */
#define PM_APBCSEL_APBCDIV_DIV2_Val 0x1u /**< \brief (PM_APBCSEL) Divide by 2 */
#define PM_APBCSEL_APBCDIV_DIV4_Val 0x2u /**< \brief (PM_APBCSEL) Divide by 4 */
#define PM_APBCSEL_APBCDIV_DIV8_Val 0x3u /**< \brief (PM_APBCSEL) Divide by 8 */
#define PM_APBCSEL_APBCDIV_DIV16_Val 0x4u /**< \brief (PM_APBCSEL) Divide by 16 */
#define PM_APBCSEL_APBCDIV_DIV32_Val 0x5u /**< \brief (PM_APBCSEL) Divide by 32 */
#define PM_APBCSEL_APBCDIV_DIV64_Val 0x6u /**< \brief (PM_APBCSEL) Divide by 64 */
#define PM_APBCSEL_APBCDIV_DIV128_Val 0x7u /**< \brief (PM_APBCSEL) Divide by 128 */
#define PM_APBCSEL_APBCDIV_DIV1 (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos)
#define PM_APBCSEL_APBCDIV_DIV2 (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos)
#define PM_APBCSEL_APBCDIV_DIV4 (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos)
#define PM_APBCSEL_APBCDIV_DIV8 (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos)
#define PM_APBCSEL_APBCDIV_DIV16 (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos)
#define PM_APBCSEL_APBCDIV_DIV32 (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos)
#define PM_APBCSEL_APBCDIV_DIV64 (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos)
#define PM_APBCSEL_APBCDIV_DIV128 (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos)
#define PM_APBCSEL_MASK 0x07u /**< \brief (PM_APBCSEL) MASK Register */
/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t HPB0:1; /*!< bit: 0 HPB0 AHB Clock Mask */
uint32_t HPB1:1; /*!< bit: 1 HPB1 AHB Clock Mask */
uint32_t HPB2:1; /*!< bit: 2 HPB2 AHB Clock Mask */
uint32_t DSU:1; /*!< bit: 3 DSU AHB Clock Mask */
uint32_t NVMCTRL:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
uint32_t DMAC:1; /*!< bit: 5 DMAC AHB Clock Mask */
uint32_t USB:1; /*!< bit: 6 USB AHB Clock Mask */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_AHBMASK_OFFSET 0x14 /**< \brief (PM_AHBMASK offset) AHB Mask */
#define PM_AHBMASK_RESETVALUE 0x0000007F /**< \brief (PM_AHBMASK reset_value) AHB Mask */
#define PM_AHBMASK_HPB0_Pos 0 /**< \brief (PM_AHBMASK) HPB0 AHB Clock Mask */
#define PM_AHBMASK_HPB0 (0x1u << PM_AHBMASK_HPB0_Pos)
#define PM_AHBMASK_HPB1_Pos 1 /**< \brief (PM_AHBMASK) HPB1 AHB Clock Mask */
#define PM_AHBMASK_HPB1 (0x1u << PM_AHBMASK_HPB1_Pos)
#define PM_AHBMASK_HPB2_Pos 2 /**< \brief (PM_AHBMASK) HPB2 AHB Clock Mask */
#define PM_AHBMASK_HPB2 (0x1u << PM_AHBMASK_HPB2_Pos)
#define PM_AHBMASK_DSU_Pos 3 /**< \brief (PM_AHBMASK) DSU AHB Clock Mask */
#define PM_AHBMASK_DSU (0x1u << PM_AHBMASK_DSU_Pos)
#define PM_AHBMASK_NVMCTRL_Pos 4 /**< \brief (PM_AHBMASK) NVMCTRL AHB Clock Mask */
#define PM_AHBMASK_NVMCTRL (0x1u << PM_AHBMASK_NVMCTRL_Pos)
#define PM_AHBMASK_DMAC_Pos 5 /**< \brief (PM_AHBMASK) DMAC AHB Clock Mask */
#define PM_AHBMASK_DMAC (0x1u << PM_AHBMASK_DMAC_Pos)
#define PM_AHBMASK_USB_Pos 6 /**< \brief (PM_AHBMASK) USB AHB Clock Mask */
#define PM_AHBMASK_USB (0x1u << PM_AHBMASK_USB_Pos)
#define PM_AHBMASK_MASK 0x0000007Fu /**< \brief (PM_AHBMASK) MASK Register */
/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC0:1; /*!< bit: 0 PAC0 APB Clock Enable */
uint32_t PM:1; /*!< bit: 1 PM APB Clock Enable */
uint32_t SYSCTRL:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
uint32_t GCLK:1; /*!< bit: 3 GCLK APB Clock Enable */
uint32_t WDT:1; /*!< bit: 4 WDT APB Clock Enable */
uint32_t RTC:1; /*!< bit: 5 RTC APB Clock Enable */
uint32_t EIC:1; /*!< bit: 6 EIC APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_APBAMASK_OFFSET 0x18 /**< \brief (PM_APBAMASK offset) APBA Mask */
#define PM_APBAMASK_RESETVALUE 0x0000007F /**< \brief (PM_APBAMASK reset_value) APBA Mask */
#define PM_APBAMASK_PAC0_Pos 0 /**< \brief (PM_APBAMASK) PAC0 APB Clock Enable */
#define PM_APBAMASK_PAC0 (0x1u << PM_APBAMASK_PAC0_Pos)
#define PM_APBAMASK_PM_Pos 1 /**< \brief (PM_APBAMASK) PM APB Clock Enable */
#define PM_APBAMASK_PM (0x1u << PM_APBAMASK_PM_Pos)
#define PM_APBAMASK_SYSCTRL_Pos 2 /**< \brief (PM_APBAMASK) SYSCTRL APB Clock Enable */
#define PM_APBAMASK_SYSCTRL (0x1u << PM_APBAMASK_SYSCTRL_Pos)
#define PM_APBAMASK_GCLK_Pos 3 /**< \brief (PM_APBAMASK) GCLK APB Clock Enable */
#define PM_APBAMASK_GCLK (0x1u << PM_APBAMASK_GCLK_Pos)
#define PM_APBAMASK_WDT_Pos 4 /**< \brief (PM_APBAMASK) WDT APB Clock Enable */
#define PM_APBAMASK_WDT (0x1u << PM_APBAMASK_WDT_Pos)
#define PM_APBAMASK_RTC_Pos 5 /**< \brief (PM_APBAMASK) RTC APB Clock Enable */
#define PM_APBAMASK_RTC (0x1u << PM_APBAMASK_RTC_Pos)
#define PM_APBAMASK_EIC_Pos 6 /**< \brief (PM_APBAMASK) EIC APB Clock Enable */
#define PM_APBAMASK_EIC (0x1u << PM_APBAMASK_EIC_Pos)
#define PM_APBAMASK_MASK 0x0000007Fu /**< \brief (PM_APBAMASK) MASK Register */
/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC1:1; /*!< bit: 0 PAC1 APB Clock Enable */
uint32_t DSU:1; /*!< bit: 1 DSU APB Clock Enable */
uint32_t NVMCTRL:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
uint32_t PORT:1; /*!< bit: 3 PORT APB Clock Enable */
uint32_t DMAC:1; /*!< bit: 4 DMAC APB Clock Enable */
uint32_t USB:1; /*!< bit: 5 USB APB Clock Enable */
uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_APBBMASK_OFFSET 0x1C /**< \brief (PM_APBBMASK offset) APBB Mask */
#define PM_APBBMASK_RESETVALUE 0x0000007F /**< \brief (PM_APBBMASK reset_value) APBB Mask */
#define PM_APBBMASK_PAC1_Pos 0 /**< \brief (PM_APBBMASK) PAC1 APB Clock Enable */
#define PM_APBBMASK_PAC1 (0x1u << PM_APBBMASK_PAC1_Pos)
#define PM_APBBMASK_DSU_Pos 1 /**< \brief (PM_APBBMASK) DSU APB Clock Enable */
#define PM_APBBMASK_DSU (0x1u << PM_APBBMASK_DSU_Pos)
#define PM_APBBMASK_NVMCTRL_Pos 2 /**< \brief (PM_APBBMASK) NVMCTRL APB Clock Enable */
#define PM_APBBMASK_NVMCTRL (0x1u << PM_APBBMASK_NVMCTRL_Pos)
#define PM_APBBMASK_PORT_Pos 3 /**< \brief (PM_APBBMASK) PORT APB Clock Enable */
#define PM_APBBMASK_PORT (0x1u << PM_APBBMASK_PORT_Pos)
#define PM_APBBMASK_DMAC_Pos 4 /**< \brief (PM_APBBMASK) DMAC APB Clock Enable */
#define PM_APBBMASK_DMAC (0x1u << PM_APBBMASK_DMAC_Pos)
#define PM_APBBMASK_USB_Pos 5 /**< \brief (PM_APBBMASK) USB APB Clock Enable */
#define PM_APBBMASK_USB (0x1u << PM_APBBMASK_USB_Pos)
#define PM_APBBMASK_MASK 0x0000003Fu /**< \brief (PM_APBBMASK) MASK Register */
/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC2:1; /*!< bit: 0 PAC2 APB Clock Enable */
uint32_t EVSYS:1; /*!< bit: 1 EVSYS APB Clock Enable */
uint32_t SERCOM0:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
uint32_t SERCOM1:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
uint32_t SERCOM2:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
uint32_t SERCOM3:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
uint32_t SERCOM4:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
uint32_t SERCOM5:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
uint32_t TCC0:1; /*!< bit: 8 TCC0 APB Clock Enable */
uint32_t TCC1:1; /*!< bit: 9 TCC1 APB Clock Enable */
uint32_t TCC2:1; /*!< bit: 10 TCC2 APB Clock Enable */
uint32_t TC3:1; /*!< bit: 11 TC3 APB Clock Enable */
uint32_t TC4:1; /*!< bit: 12 TC4 APB Clock Enable */
uint32_t TC5:1; /*!< bit: 13 TC5 APB Clock Enable */
uint32_t TC6:1; /*!< bit: 14 TC6 APB Clock Enable */
uint32_t TC7:1; /*!< bit: 15 TC7 APB Clock Enable */
uint32_t ADC:1; /*!< bit: 16 ADC APB Clock Enable */
uint32_t AC:1; /*!< bit: 17 AC APB Clock Enable */
uint32_t DAC:1; /*!< bit: 18 DAC APB Clock Enable */
uint32_t PTC:1; /*!< bit: 19 PTC APB Clock Enable */
uint32_t I2S:1; /*!< bit: 20 I2S APB Clock Enable */
uint32_t :11; /*!< bit: 21..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_APBCMASK_OFFSET 0x20 /**< \brief (PM_APBCMASK offset) APBC Mask */
#define PM_APBCMASK_RESETVALUE 0x00010000 /**< \brief (PM_APBCMASK reset_value) APBC Mask */
#define PM_APBCMASK_PAC2_Pos 0 /**< \brief (PM_APBCMASK) PAC2 APB Clock Enable */
#define PM_APBCMASK_PAC2 (0x1u << PM_APBCMASK_PAC2_Pos)
#define PM_APBCMASK_EVSYS_Pos 1 /**< \brief (PM_APBCMASK) EVSYS APB Clock Enable */
#define PM_APBCMASK_EVSYS (0x1u << PM_APBCMASK_EVSYS_Pos)
#define PM_APBCMASK_SERCOM0_Pos 2 /**< \brief (PM_APBCMASK) SERCOM0 APB Clock Enable */
#define PM_APBCMASK_SERCOM0 (0x1u << PM_APBCMASK_SERCOM0_Pos)
#define PM_APBCMASK_SERCOM1_Pos 3 /**< \brief (PM_APBCMASK) SERCOM1 APB Clock Enable */
#define PM_APBCMASK_SERCOM1 (0x1u << PM_APBCMASK_SERCOM1_Pos)
#define PM_APBCMASK_SERCOM2_Pos 4 /**< \brief (PM_APBCMASK) SERCOM2 APB Clock Enable */
#define PM_APBCMASK_SERCOM2 (0x1u << PM_APBCMASK_SERCOM2_Pos)
#define PM_APBCMASK_SERCOM3_Pos 5 /**< \brief (PM_APBCMASK) SERCOM3 APB Clock Enable */
#define PM_APBCMASK_SERCOM3 (0x1u << PM_APBCMASK_SERCOM3_Pos)
#define PM_APBCMASK_SERCOM4_Pos 6 /**< \brief (PM_APBCMASK) SERCOM4 APB Clock Enable */
#define PM_APBCMASK_SERCOM4 (0x1u << PM_APBCMASK_SERCOM4_Pos)
#define PM_APBCMASK_SERCOM5_Pos 7 /**< \brief (PM_APBCMASK) SERCOM5 APB Clock Enable */
#define PM_APBCMASK_SERCOM5 (0x1u << PM_APBCMASK_SERCOM5_Pos)
#define PM_APBCMASK_TCC0_Pos 8 /**< \brief (PM_APBCMASK) TCC0 APB Clock Enable */
#define PM_APBCMASK_TCC0 (0x1u << PM_APBCMASK_TCC0_Pos)
#define PM_APBCMASK_TCC1_Pos 9 /**< \brief (PM_APBCMASK) TCC1 APB Clock Enable */
#define PM_APBCMASK_TCC1 (0x1u << PM_APBCMASK_TCC1_Pos)
#define PM_APBCMASK_TCC2_Pos 10 /**< \brief (PM_APBCMASK) TCC2 APB Clock Enable */
#define PM_APBCMASK_TCC2 (0x1u << PM_APBCMASK_TCC2_Pos)
#define PM_APBCMASK_TC3_Pos 11 /**< \brief (PM_APBCMASK) TC3 APB Clock Enable */
#define PM_APBCMASK_TC3 (0x1u << PM_APBCMASK_TC3_Pos)
#define PM_APBCMASK_TC4_Pos 12 /**< \brief (PM_APBCMASK) TC4 APB Clock Enable */
#define PM_APBCMASK_TC4 (0x1u << PM_APBCMASK_TC4_Pos)
#define PM_APBCMASK_TC5_Pos 13 /**< \brief (PM_APBCMASK) TC5 APB Clock Enable */
#define PM_APBCMASK_TC5 (0x1u << PM_APBCMASK_TC5_Pos)
#define PM_APBCMASK_TC6_Pos 14 /**< \brief (PM_APBCMASK) TC6 APB Clock Enable */
#define PM_APBCMASK_TC6 (0x1u << PM_APBCMASK_TC6_Pos)
#define PM_APBCMASK_TC7_Pos 15 /**< \brief (PM_APBCMASK) TC7 APB Clock Enable */
#define PM_APBCMASK_TC7 (0x1u << PM_APBCMASK_TC7_Pos)
#define PM_APBCMASK_ADC_Pos 16 /**< \brief (PM_APBCMASK) ADC APB Clock Enable */
#define PM_APBCMASK_ADC (0x1u << PM_APBCMASK_ADC_Pos)
#define PM_APBCMASK_AC_Pos 17 /**< \brief (PM_APBCMASK) AC APB Clock Enable */
#define PM_APBCMASK_AC (0x1u << PM_APBCMASK_AC_Pos)
#define PM_APBCMASK_DAC_Pos 18 /**< \brief (PM_APBCMASK) DAC APB Clock Enable */
#define PM_APBCMASK_DAC (0x1u << PM_APBCMASK_DAC_Pos)
#define PM_APBCMASK_PTC_Pos 19 /**< \brief (PM_APBCMASK) PTC APB Clock Enable */
#define PM_APBCMASK_PTC (0x1u << PM_APBCMASK_PTC_Pos)
#define PM_APBCMASK_I2S_Pos 20 /**< \brief (PM_APBCMASK) I2S APB Clock Enable */
#define PM_APBCMASK_I2S (0x1u << PM_APBCMASK_I2S_Pos)
#define PM_APBCMASK_MASK 0x001FFFFFu /**< \brief (PM_APBCMASK) MASK Register */
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_INTENCLR_OFFSET 0x34 /**< \brief (PM_INTENCLR offset) Interrupt Enable Clear */
#define PM_INTENCLR_RESETVALUE 0x00 /**< \brief (PM_INTENCLR reset_value) Interrupt Enable Clear */
#define PM_INTENCLR_CKRDY_Pos 0 /**< \brief (PM_INTENCLR) Clock Ready Interrupt Enable */
#define PM_INTENCLR_CKRDY (0x1u << PM_INTENCLR_CKRDY_Pos)
#define PM_INTENCLR_MASK 0x01u /**< \brief (PM_INTENCLR) MASK Register */
/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_INTENSET_OFFSET 0x35 /**< \brief (PM_INTENSET offset) Interrupt Enable Set */
#define PM_INTENSET_RESETVALUE 0x00 /**< \brief (PM_INTENSET reset_value) Interrupt Enable Set */
#define PM_INTENSET_CKRDY_Pos 0 /**< \brief (PM_INTENSET) Clock Ready Interrupt Enable */
#define PM_INTENSET_CKRDY (0x1u << PM_INTENSET_CKRDY_Pos)
#define PM_INTENSET_MASK 0x01u /**< \brief (PM_INTENSET) MASK Register */
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_INTFLAG_OFFSET 0x36 /**< \brief (PM_INTFLAG offset) Interrupt Flag Status and Clear */
#define PM_INTFLAG_RESETVALUE 0x00 /**< \brief (PM_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define PM_INTFLAG_CKRDY_Pos 0 /**< \brief (PM_INTFLAG) Clock Ready */
#define PM_INTFLAG_CKRDY (0x1u << PM_INTFLAG_CKRDY_Pos)
#define PM_INTFLAG_MASK 0x01u /**< \brief (PM_INTFLAG) MASK Register */
/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t POR:1; /*!< bit: 0 Power On Reset */
uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t EXT:1; /*!< bit: 4 External Reset */
uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
uint8_t SYST:1; /*!< bit: 6 System Reset Request */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_RCAUSE_OFFSET 0x38 /**< \brief (PM_RCAUSE offset) Reset Cause */
#define PM_RCAUSE_RESETVALUE 0x01 /**< \brief (PM_RCAUSE reset_value) Reset Cause */
#define PM_RCAUSE_POR_Pos 0 /**< \brief (PM_RCAUSE) Power On Reset */
#define PM_RCAUSE_POR (0x1u << PM_RCAUSE_POR_Pos)
#define PM_RCAUSE_BOD12_Pos 1 /**< \brief (PM_RCAUSE) Brown Out 12 Detector Reset */
#define PM_RCAUSE_BOD12 (0x1u << PM_RCAUSE_BOD12_Pos)
#define PM_RCAUSE_BOD33_Pos 2 /**< \brief (PM_RCAUSE) Brown Out 33 Detector Reset */
#define PM_RCAUSE_BOD33 (0x1u << PM_RCAUSE_BOD33_Pos)
#define PM_RCAUSE_EXT_Pos 4 /**< \brief (PM_RCAUSE) External Reset */
#define PM_RCAUSE_EXT (0x1u << PM_RCAUSE_EXT_Pos)
#define PM_RCAUSE_WDT_Pos 5 /**< \brief (PM_RCAUSE) Watchdog Reset */
#define PM_RCAUSE_WDT (0x1u << PM_RCAUSE_WDT_Pos)
#define PM_RCAUSE_SYST_Pos 6 /**< \brief (PM_RCAUSE) System Reset Request */
#define PM_RCAUSE_SYST (0x1u << PM_RCAUSE_SYST_Pos)
#define PM_RCAUSE_MASK 0x77u /**< \brief (PM_RCAUSE) MASK Register */
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
RoReg8 Reserved1[0x6];
__IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
__IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
__IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
__IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
RoReg8 Reserved2[0x8];
__IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
__IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
__IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
__IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
RoReg8 Reserved3[0x10];
__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x1];
__I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_PM_COMPONENT_ */

395
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/port.h Normal file
View file

@ -0,0 +1,395 @@
/**
* \file
*
* \brief Component description for PORT
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_PORT_COMPONENT_
#define _SAMD21_PORT_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PORT */
/* ========================================================================== */
/** \addtogroup SAMD21_PORT Port Module */
/*@{*/
#define PORT_U2210
#define REV_PORT 0x100
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
#define PORT_DIR_RESETVALUE 0x00000000 /**< \brief (PORT_DIR reset_value) Data Direction */
#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
#define PORT_DIR_DIR_Msk (0xFFFFFFFFu << PORT_DIR_DIR_Pos)
#define PORT_DIR_DIR(value) ((PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos)))
#define PORT_DIR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIR) MASK Register */
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
#define PORT_DIRCLR_RESETVALUE 0x00000000 /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
#define PORT_DIRCLR_DIRCLR_Msk (0xFFFFFFFFu << PORT_DIRCLR_DIRCLR_Pos)
#define PORT_DIRCLR_DIRCLR(value) ((PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos)))
#define PORT_DIRCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRCLR) MASK Register */
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
#define PORT_DIRSET_RESETVALUE 0x00000000 /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
#define PORT_DIRSET_DIRSET_Msk (0xFFFFFFFFu << PORT_DIRSET_DIRSET_Pos)
#define PORT_DIRSET_DIRSET(value) ((PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos)))
#define PORT_DIRSET_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRSET) MASK Register */
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
#define PORT_DIRTGL_RESETVALUE 0x00000000 /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
#define PORT_DIRTGL_DIRTGL_Msk (0xFFFFFFFFu << PORT_DIRTGL_DIRTGL_Pos)
#define PORT_DIRTGL_DIRTGL(value) ((PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos)))
#define PORT_DIRTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_DIRTGL) MASK Register */
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
#define PORT_OUT_RESETVALUE 0x00000000 /**< \brief (PORT_OUT reset_value) Data Output Value */
#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
#define PORT_OUT_OUT_Msk (0xFFFFFFFFu << PORT_OUT_OUT_Pos)
#define PORT_OUT_OUT(value) ((PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos)))
#define PORT_OUT_MASK 0xFFFFFFFFu /**< \brief (PORT_OUT) MASK Register */
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
#define PORT_OUTCLR_RESETVALUE 0x00000000 /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
#define PORT_OUTCLR_OUTCLR_Msk (0xFFFFFFFFu << PORT_OUTCLR_OUTCLR_Pos)
#define PORT_OUTCLR_OUTCLR(value) ((PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos)))
#define PORT_OUTCLR_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTCLR) MASK Register */
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
#define PORT_OUTSET_RESETVALUE 0x00000000 /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
#define PORT_OUTSET_OUTSET_Msk (0xFFFFFFFFu << PORT_OUTSET_OUTSET_Pos)
#define PORT_OUTSET_OUTSET(value) ((PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos)))
#define PORT_OUTSET_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTSET) MASK Register */
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
#define PORT_OUTTGL_RESETVALUE 0x00000000 /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
#define PORT_OUTTGL_OUTTGL_Msk (0xFFFFFFFFu << PORT_OUTTGL_OUTTGL_Pos)
#define PORT_OUTTGL_OUTTGL(value) ((PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos)))
#define PORT_OUTTGL_MASK 0xFFFFFFFFu /**< \brief (PORT_OUTTGL) MASK Register */
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
#define PORT_IN_RESETVALUE 0x00000000 /**< \brief (PORT_IN reset_value) Data Input Value */
#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
#define PORT_IN_IN_Msk (0xFFFFFFFFu << PORT_IN_IN_Pos)
#define PORT_IN_IN(value) ((PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos)))
#define PORT_IN_MASK 0xFFFFFFFFu /**< \brief (PORT_IN) MASK Register */
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
#define PORT_CTRL_RESETVALUE 0x00000000 /**< \brief (PORT_CTRL reset_value) Control */
#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
#define PORT_CTRL_SAMPLING_Msk (0xFFFFFFFFu << PORT_CTRL_SAMPLING_Pos)
#define PORT_CTRL_SAMPLING(value) ((PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)))
#define PORT_CTRL_MASK 0xFFFFFFFFu /**< \brief (PORT_CTRL) MASK Register */
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
uint32_t INEN:1; /*!< bit: 17 Input Enable */
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
uint32_t :3; /*!< bit: 19..21 Reserved */
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
uint32_t :1; /*!< bit: 29 Reserved */
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
#define PORT_WRCONFIG_RESETVALUE 0x00000000 /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
#define PORT_WRCONFIG_PINMASK_Msk (0xFFFFu << PORT_WRCONFIG_PINMASK_Pos)
#define PORT_WRCONFIG_PINMASK(value) ((PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)))
#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
#define PORT_WRCONFIG_PMUXEN (0x1u << PORT_WRCONFIG_PMUXEN_Pos)
#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
#define PORT_WRCONFIG_INEN (0x1u << PORT_WRCONFIG_INEN_Pos)
#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
#define PORT_WRCONFIG_PULLEN (0x1u << PORT_WRCONFIG_PULLEN_Pos)
#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
#define PORT_WRCONFIG_DRVSTR (0x1u << PORT_WRCONFIG_DRVSTR_Pos)
#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
#define PORT_WRCONFIG_PMUX_Msk (0xFu << PORT_WRCONFIG_PMUX_Pos)
#define PORT_WRCONFIG_PMUX(value) ((PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)))
#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
#define PORT_WRCONFIG_WRPMUX (0x1u << PORT_WRCONFIG_WRPMUX_Pos)
#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
#define PORT_WRCONFIG_WRPINCFG (0x1u << PORT_WRCONFIG_WRPINCFG_Pos)
#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
#define PORT_WRCONFIG_HWSEL (0x1u << PORT_WRCONFIG_HWSEL_Pos)
#define PORT_WRCONFIG_MASK 0xDF47FFFFu /**< \brief (PORT_WRCONFIG) MASK Register */
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
#define PORT_PMUX_RESETVALUE 0x00 /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
#define PORT_PMUX_PMUXE_Msk (0xFu << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE(value) ((PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)))
#define PORT_PMUX_PMUXE_A_Val 0x0u /**< \brief (PORT_PMUX) Peripheral function A selected */
#define PORT_PMUX_PMUXE_B_Val 0x1u /**< \brief (PORT_PMUX) Peripheral function B selected */
#define PORT_PMUX_PMUXE_C_Val 0x2u /**< \brief (PORT_PMUX) Peripheral function C selected */
#define PORT_PMUX_PMUXE_D_Val 0x3u /**< \brief (PORT_PMUX) Peripheral function D selected */
#define PORT_PMUX_PMUXE_E_Val 0x4u /**< \brief (PORT_PMUX) Peripheral function E selected */
#define PORT_PMUX_PMUXE_F_Val 0x5u /**< \brief (PORT_PMUX) Peripheral function F selected */
#define PORT_PMUX_PMUXE_G_Val 0x6u /**< \brief (PORT_PMUX) Peripheral function G selected */
#define PORT_PMUX_PMUXE_H_Val 0x7u /**< \brief (PORT_PMUX) Peripheral function H selected */
#define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
#define PORT_PMUX_PMUXO_Msk (0xFu << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO(value) ((PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)))
#define PORT_PMUX_PMUXO_A_Val 0x0u /**< \brief (PORT_PMUX) Peripheral function A selected */
#define PORT_PMUX_PMUXO_B_Val 0x1u /**< \brief (PORT_PMUX) Peripheral function B selected */
#define PORT_PMUX_PMUXO_C_Val 0x2u /**< \brief (PORT_PMUX) Peripheral function C selected */
#define PORT_PMUX_PMUXO_D_Val 0x3u /**< \brief (PORT_PMUX) Peripheral function D selected */
#define PORT_PMUX_PMUXO_E_Val 0x4u /**< \brief (PORT_PMUX) Peripheral function E selected */
#define PORT_PMUX_PMUXO_F_Val 0x5u /**< \brief (PORT_PMUX) Peripheral function F selected */
#define PORT_PMUX_PMUXO_G_Val 0x6u /**< \brief (PORT_PMUX) Peripheral function G selected */
#define PORT_PMUX_PMUXO_H_Val 0x7u /**< \brief (PORT_PMUX) Peripheral function H selected */
#define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_MASK 0xFFu /**< \brief (PORT_PMUX) MASK Register */
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
uint8_t INEN:1; /*!< bit: 1 Input Enable */
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
#define PORT_PINCFG_RESETVALUE 0x00 /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
#define PORT_PINCFG_PMUXEN (0x1u << PORT_PINCFG_PMUXEN_Pos)
#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
#define PORT_PINCFG_INEN (0x1u << PORT_PINCFG_INEN_Pos)
#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
#define PORT_PINCFG_PULLEN (0x1u << PORT_PINCFG_PULLEN_Pos)
#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
#define PORT_PINCFG_DRVSTR (0x1u << PORT_PINCFG_DRVSTR_Pos)
#define PORT_PINCFG_MASK 0x47u /**< \brief (PORT_PINCFG) MASK Register */
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
RoReg8 Reserved1[0x4];
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
RoReg8 Reserved2[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_PORT_IOBUS
/*@}*/
#endif /* _SAMD21_PORT_COMPONENT_ */

1062
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/rtc.h Normal file
View file

File diff suppressed because it is too large Load diff

1508
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/sercom.h Normal file
View file

File diff suppressed because it is too large Load diff

948
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/sysctrl.h Normal file
View file

@ -0,0 +1,948 @@
/**
* \file
*
* \brief Component description for SYSCTRL
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_SYSCTRL_COMPONENT_
#define _SAMD21_SYSCTRL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR SYSCTRL */
/* ========================================================================== */
/** \addtogroup SAMD21_SYSCTRL System Control */
/*@{*/
#define SYSCTRL_U2100
#define REV_SYSCTRL 0x201
/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_INTENCLR_OFFSET 0x00 /**< \brief (SYSCTRL_INTENCLR offset) Interrupt Enable Clear */
#define SYSCTRL_INTENCLR_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTENCLR reset_value) Interrupt Enable Clear */
#define SYSCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENCLR) XOSC Ready Interrupt Enable */
#define SYSCTRL_INTENCLR_XOSCRDY (0x1u << SYSCTRL_INTENCLR_XOSCRDY_Pos)
#define SYSCTRL_INTENCLR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
#define SYSCTRL_INTENCLR_XOSC32KRDY (0x1u << SYSCTRL_INTENCLR_XOSC32KRDY_Pos)
#define SYSCTRL_INTENCLR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
#define SYSCTRL_INTENCLR_OSC32KRDY (0x1u << SYSCTRL_INTENCLR_OSC32KRDY_Pos)
#define SYSCTRL_INTENCLR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENCLR) OSC8M Ready Interrupt Enable */
#define SYSCTRL_INTENCLR_OSC8MRDY (0x1u << SYSCTRL_INTENCLR_OSC8MRDY_Pos)
#define SYSCTRL_INTENCLR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENCLR) DFLL Ready Interrupt Enable */
#define SYSCTRL_INTENCLR_DFLLRDY (0x1u << SYSCTRL_INTENCLR_DFLLRDY_Pos)
#define SYSCTRL_INTENCLR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */
#define SYSCTRL_INTENCLR_DFLLOOB (0x1u << SYSCTRL_INTENCLR_DFLLOOB_Pos)
#define SYSCTRL_INTENCLR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */
#define SYSCTRL_INTENCLR_DFLLLCKF (0x1u << SYSCTRL_INTENCLR_DFLLLCKF_Pos)
#define SYSCTRL_INTENCLR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */
#define SYSCTRL_INTENCLR_DFLLLCKC (0x1u << SYSCTRL_INTENCLR_DFLLLCKC_Pos)
#define SYSCTRL_INTENCLR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */
#define SYSCTRL_INTENCLR_DFLLRCS (0x1u << SYSCTRL_INTENCLR_DFLLRCS_Pos)
#define SYSCTRL_INTENCLR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENCLR) BOD33 Ready Interrupt Enable */
#define SYSCTRL_INTENCLR_BOD33RDY (0x1u << SYSCTRL_INTENCLR_BOD33RDY_Pos)
#define SYSCTRL_INTENCLR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENCLR) BOD33 Detection Interrupt Enable */
#define SYSCTRL_INTENCLR_BOD33DET (0x1u << SYSCTRL_INTENCLR_BOD33DET_Pos)
#define SYSCTRL_INTENCLR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENCLR) BOD33 Synchronization Ready Interrupt Enable */
#define SYSCTRL_INTENCLR_B33SRDY (0x1u << SYSCTRL_INTENCLR_B33SRDY_Pos)
#define SYSCTRL_INTENCLR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
#define SYSCTRL_INTENCLR_DPLLLCKR (0x1u << SYSCTRL_INTENCLR_DPLLLCKR_Pos)
#define SYSCTRL_INTENCLR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
#define SYSCTRL_INTENCLR_DPLLLCKF (0x1u << SYSCTRL_INTENCLR_DPLLLCKF_Pos)
#define SYSCTRL_INTENCLR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENCLR) DPLL Lock Timeout Interrupt Enable */
#define SYSCTRL_INTENCLR_DPLLLTO (0x1u << SYSCTRL_INTENCLR_DPLLLTO_Pos)
#define SYSCTRL_INTENCLR_MASK 0x00038FFFu /**< \brief (SYSCTRL_INTENCLR) MASK Register */
/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_INTENSET_OFFSET 0x04 /**< \brief (SYSCTRL_INTENSET offset) Interrupt Enable Set */
#define SYSCTRL_INTENSET_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTENSET reset_value) Interrupt Enable Set */
#define SYSCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTENSET) XOSC Ready Interrupt Enable */
#define SYSCTRL_INTENSET_XOSCRDY (0x1u << SYSCTRL_INTENSET_XOSCRDY_Pos)
#define SYSCTRL_INTENSET_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
#define SYSCTRL_INTENSET_XOSC32KRDY (0x1u << SYSCTRL_INTENSET_XOSC32KRDY_Pos)
#define SYSCTRL_INTENSET_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTENSET) OSC32K Ready Interrupt Enable */
#define SYSCTRL_INTENSET_OSC32KRDY (0x1u << SYSCTRL_INTENSET_OSC32KRDY_Pos)
#define SYSCTRL_INTENSET_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTENSET) OSC8M Ready Interrupt Enable */
#define SYSCTRL_INTENSET_OSC8MRDY (0x1u << SYSCTRL_INTENSET_OSC8MRDY_Pos)
#define SYSCTRL_INTENSET_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTENSET) DFLL Ready Interrupt Enable */
#define SYSCTRL_INTENSET_DFLLRDY (0x1u << SYSCTRL_INTENSET_DFLLRDY_Pos)
#define SYSCTRL_INTENSET_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */
#define SYSCTRL_INTENSET_DFLLOOB (0x1u << SYSCTRL_INTENSET_DFLLOOB_Pos)
#define SYSCTRL_INTENSET_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */
#define SYSCTRL_INTENSET_DFLLLCKF (0x1u << SYSCTRL_INTENSET_DFLLLCKF_Pos)
#define SYSCTRL_INTENSET_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */
#define SYSCTRL_INTENSET_DFLLLCKC (0x1u << SYSCTRL_INTENSET_DFLLLCKC_Pos)
#define SYSCTRL_INTENSET_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */
#define SYSCTRL_INTENSET_DFLLRCS (0x1u << SYSCTRL_INTENSET_DFLLRCS_Pos)
#define SYSCTRL_INTENSET_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTENSET) BOD33 Ready Interrupt Enable */
#define SYSCTRL_INTENSET_BOD33RDY (0x1u << SYSCTRL_INTENSET_BOD33RDY_Pos)
#define SYSCTRL_INTENSET_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTENSET) BOD33 Detection Interrupt Enable */
#define SYSCTRL_INTENSET_BOD33DET (0x1u << SYSCTRL_INTENSET_BOD33DET_Pos)
#define SYSCTRL_INTENSET_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTENSET) BOD33 Synchronization Ready Interrupt Enable */
#define SYSCTRL_INTENSET_B33SRDY (0x1u << SYSCTRL_INTENSET_B33SRDY_Pos)
#define SYSCTRL_INTENSET_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
#define SYSCTRL_INTENSET_DPLLLCKR (0x1u << SYSCTRL_INTENSET_DPLLLCKR_Pos)
#define SYSCTRL_INTENSET_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
#define SYSCTRL_INTENSET_DPLLLCKF (0x1u << SYSCTRL_INTENSET_DPLLLCKF_Pos)
#define SYSCTRL_INTENSET_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTENSET) DPLL Lock Timeout Interrupt Enable */
#define SYSCTRL_INTENSET_DPLLLTO (0x1u << SYSCTRL_INTENSET_DPLLLTO_Pos)
#define SYSCTRL_INTENSET_MASK 0x00038FFFu /**< \brief (SYSCTRL_INTENSET) MASK Register */
/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_INTFLAG_OFFSET 0x08 /**< \brief (SYSCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
#define SYSCTRL_INTFLAG_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define SYSCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_INTFLAG) XOSC Ready */
#define SYSCTRL_INTFLAG_XOSCRDY (0x1u << SYSCTRL_INTFLAG_XOSCRDY_Pos)
#define SYSCTRL_INTFLAG_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_INTFLAG) XOSC32K Ready */
#define SYSCTRL_INTFLAG_XOSC32KRDY (0x1u << SYSCTRL_INTFLAG_XOSC32KRDY_Pos)
#define SYSCTRL_INTFLAG_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_INTFLAG) OSC32K Ready */
#define SYSCTRL_INTFLAG_OSC32KRDY (0x1u << SYSCTRL_INTFLAG_OSC32KRDY_Pos)
#define SYSCTRL_INTFLAG_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_INTFLAG) OSC8M Ready */
#define SYSCTRL_INTFLAG_OSC8MRDY (0x1u << SYSCTRL_INTFLAG_OSC8MRDY_Pos)
#define SYSCTRL_INTFLAG_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_INTFLAG) DFLL Ready */
#define SYSCTRL_INTFLAG_DFLLRDY (0x1u << SYSCTRL_INTFLAG_DFLLRDY_Pos)
#define SYSCTRL_INTFLAG_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_INTFLAG) DFLL Out Of Bounds */
#define SYSCTRL_INTFLAG_DFLLOOB (0x1u << SYSCTRL_INTFLAG_DFLLOOB_Pos)
#define SYSCTRL_INTFLAG_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Fine */
#define SYSCTRL_INTFLAG_DFLLLCKF (0x1u << SYSCTRL_INTFLAG_DFLLLCKF_Pos)
#define SYSCTRL_INTFLAG_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_INTFLAG) DFLL Lock Coarse */
#define SYSCTRL_INTFLAG_DFLLLCKC (0x1u << SYSCTRL_INTFLAG_DFLLLCKC_Pos)
#define SYSCTRL_INTFLAG_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_INTFLAG) DFLL Reference Clock Stopped */
#define SYSCTRL_INTFLAG_DFLLRCS (0x1u << SYSCTRL_INTFLAG_DFLLRCS_Pos)
#define SYSCTRL_INTFLAG_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_INTFLAG) BOD33 Ready */
#define SYSCTRL_INTFLAG_BOD33RDY (0x1u << SYSCTRL_INTFLAG_BOD33RDY_Pos)
#define SYSCTRL_INTFLAG_BOD33DET_Pos 10 /**< \brief (SYSCTRL_INTFLAG) BOD33 Detection */
#define SYSCTRL_INTFLAG_BOD33DET (0x1u << SYSCTRL_INTFLAG_BOD33DET_Pos)
#define SYSCTRL_INTFLAG_B33SRDY_Pos 11 /**< \brief (SYSCTRL_INTFLAG) BOD33 Synchronization Ready */
#define SYSCTRL_INTFLAG_B33SRDY (0x1u << SYSCTRL_INTFLAG_B33SRDY_Pos)
#define SYSCTRL_INTFLAG_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Rise */
#define SYSCTRL_INTFLAG_DPLLLCKR (0x1u << SYSCTRL_INTFLAG_DPLLLCKR_Pos)
#define SYSCTRL_INTFLAG_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Fall */
#define SYSCTRL_INTFLAG_DPLLLCKF (0x1u << SYSCTRL_INTFLAG_DPLLLCKF_Pos)
#define SYSCTRL_INTFLAG_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_INTFLAG) DPLL Lock Timeout */
#define SYSCTRL_INTFLAG_DPLLLTO (0x1u << SYSCTRL_INTFLAG_DPLLLTO_Pos)
#define SYSCTRL_INTFLAG_MASK 0x00038FFFu /**< \brief (SYSCTRL_INTFLAG) MASK Register */
/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_PCLKSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_PCLKSR_OFFSET 0x0C /**< \brief (SYSCTRL_PCLKSR offset) Power and Clocks Status */
#define SYSCTRL_PCLKSR_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_PCLKSR reset_value) Power and Clocks Status */
#define SYSCTRL_PCLKSR_XOSCRDY_Pos 0 /**< \brief (SYSCTRL_PCLKSR) XOSC Ready */
#define SYSCTRL_PCLKSR_XOSCRDY (0x1u << SYSCTRL_PCLKSR_XOSCRDY_Pos)
#define SYSCTRL_PCLKSR_XOSC32KRDY_Pos 1 /**< \brief (SYSCTRL_PCLKSR) XOSC32K Ready */
#define SYSCTRL_PCLKSR_XOSC32KRDY (0x1u << SYSCTRL_PCLKSR_XOSC32KRDY_Pos)
#define SYSCTRL_PCLKSR_OSC32KRDY_Pos 2 /**< \brief (SYSCTRL_PCLKSR) OSC32K Ready */
#define SYSCTRL_PCLKSR_OSC32KRDY (0x1u << SYSCTRL_PCLKSR_OSC32KRDY_Pos)
#define SYSCTRL_PCLKSR_OSC8MRDY_Pos 3 /**< \brief (SYSCTRL_PCLKSR) OSC8M Ready */
#define SYSCTRL_PCLKSR_OSC8MRDY (0x1u << SYSCTRL_PCLKSR_OSC8MRDY_Pos)
#define SYSCTRL_PCLKSR_DFLLRDY_Pos 4 /**< \brief (SYSCTRL_PCLKSR) DFLL Ready */
#define SYSCTRL_PCLKSR_DFLLRDY (0x1u << SYSCTRL_PCLKSR_DFLLRDY_Pos)
#define SYSCTRL_PCLKSR_DFLLOOB_Pos 5 /**< \brief (SYSCTRL_PCLKSR) DFLL Out Of Bounds */
#define SYSCTRL_PCLKSR_DFLLOOB (0x1u << SYSCTRL_PCLKSR_DFLLOOB_Pos)
#define SYSCTRL_PCLKSR_DFLLLCKF_Pos 6 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Fine */
#define SYSCTRL_PCLKSR_DFLLLCKF (0x1u << SYSCTRL_PCLKSR_DFLLLCKF_Pos)
#define SYSCTRL_PCLKSR_DFLLLCKC_Pos 7 /**< \brief (SYSCTRL_PCLKSR) DFLL Lock Coarse */
#define SYSCTRL_PCLKSR_DFLLLCKC (0x1u << SYSCTRL_PCLKSR_DFLLLCKC_Pos)
#define SYSCTRL_PCLKSR_DFLLRCS_Pos 8 /**< \brief (SYSCTRL_PCLKSR) DFLL Reference Clock Stopped */
#define SYSCTRL_PCLKSR_DFLLRCS (0x1u << SYSCTRL_PCLKSR_DFLLRCS_Pos)
#define SYSCTRL_PCLKSR_BOD33RDY_Pos 9 /**< \brief (SYSCTRL_PCLKSR) BOD33 Ready */
#define SYSCTRL_PCLKSR_BOD33RDY (0x1u << SYSCTRL_PCLKSR_BOD33RDY_Pos)
#define SYSCTRL_PCLKSR_BOD33DET_Pos 10 /**< \brief (SYSCTRL_PCLKSR) BOD33 Detection */
#define SYSCTRL_PCLKSR_BOD33DET (0x1u << SYSCTRL_PCLKSR_BOD33DET_Pos)
#define SYSCTRL_PCLKSR_B33SRDY_Pos 11 /**< \brief (SYSCTRL_PCLKSR) BOD33 Synchronization Ready */
#define SYSCTRL_PCLKSR_B33SRDY (0x1u << SYSCTRL_PCLKSR_B33SRDY_Pos)
#define SYSCTRL_PCLKSR_DPLLLCKR_Pos 15 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Rise */
#define SYSCTRL_PCLKSR_DPLLLCKR (0x1u << SYSCTRL_PCLKSR_DPLLLCKR_Pos)
#define SYSCTRL_PCLKSR_DPLLLCKF_Pos 16 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Fall */
#define SYSCTRL_PCLKSR_DPLLLCKF (0x1u << SYSCTRL_PCLKSR_DPLLLCKF_Pos)
#define SYSCTRL_PCLKSR_DPLLLTO_Pos 17 /**< \brief (SYSCTRL_PCLKSR) DPLL Lock Timeout */
#define SYSCTRL_PCLKSR_DPLLLTO (0x1u << SYSCTRL_PCLKSR_DPLLLTO_Pos)
#define SYSCTRL_PCLKSR_MASK 0x00038FFFu /**< \brief (SYSCTRL_PCLKSR) MASK Register */
/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t :3; /*!< bit: 3.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_XOSC_OFFSET 0x10 /**< \brief (SYSCTRL_XOSC offset) External Multipurpose Crystal Oscillator (XOSC) Control */
#define SYSCTRL_XOSC_RESETVALUE 0x0080 /**< \brief (SYSCTRL_XOSC reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
#define SYSCTRL_XOSC_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC) Oscillator Enable */
#define SYSCTRL_XOSC_ENABLE (0x1u << SYSCTRL_XOSC_ENABLE_Pos)
#define SYSCTRL_XOSC_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC) Crystal Oscillator Enable */
#define SYSCTRL_XOSC_XTALEN (0x1u << SYSCTRL_XOSC_XTALEN_Pos)
#define SYSCTRL_XOSC_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC) Run in Standby */
#define SYSCTRL_XOSC_RUNSTDBY (0x1u << SYSCTRL_XOSC_RUNSTDBY_Pos)
#define SYSCTRL_XOSC_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC) On Demand Control */
#define SYSCTRL_XOSC_ONDEMAND (0x1u << SYSCTRL_XOSC_ONDEMAND_Pos)
#define SYSCTRL_XOSC_GAIN_Pos 8 /**< \brief (SYSCTRL_XOSC) Oscillator Gain */
#define SYSCTRL_XOSC_GAIN_Msk (0x7u << SYSCTRL_XOSC_GAIN_Pos)
#define SYSCTRL_XOSC_GAIN(value) ((SYSCTRL_XOSC_GAIN_Msk & ((value) << SYSCTRL_XOSC_GAIN_Pos)))
#define SYSCTRL_XOSC_GAIN_0_Val 0x0u /**< \brief (SYSCTRL_XOSC) 2MHz */
#define SYSCTRL_XOSC_GAIN_1_Val 0x1u /**< \brief (SYSCTRL_XOSC) 4MHz */
#define SYSCTRL_XOSC_GAIN_2_Val 0x2u /**< \brief (SYSCTRL_XOSC) 8MHz */
#define SYSCTRL_XOSC_GAIN_3_Val 0x3u /**< \brief (SYSCTRL_XOSC) 16MHz */
#define SYSCTRL_XOSC_GAIN_4_Val 0x4u /**< \brief (SYSCTRL_XOSC) 30MHz */
#define SYSCTRL_XOSC_GAIN_0 (SYSCTRL_XOSC_GAIN_0_Val << SYSCTRL_XOSC_GAIN_Pos)
#define SYSCTRL_XOSC_GAIN_1 (SYSCTRL_XOSC_GAIN_1_Val << SYSCTRL_XOSC_GAIN_Pos)
#define SYSCTRL_XOSC_GAIN_2 (SYSCTRL_XOSC_GAIN_2_Val << SYSCTRL_XOSC_GAIN_Pos)
#define SYSCTRL_XOSC_GAIN_3 (SYSCTRL_XOSC_GAIN_3_Val << SYSCTRL_XOSC_GAIN_Pos)
#define SYSCTRL_XOSC_GAIN_4 (SYSCTRL_XOSC_GAIN_4_Val << SYSCTRL_XOSC_GAIN_Pos)
#define SYSCTRL_XOSC_AMPGC_Pos 11 /**< \brief (SYSCTRL_XOSC) Automatic Amplitude Gain Control */
#define SYSCTRL_XOSC_AMPGC (0x1u << SYSCTRL_XOSC_AMPGC_Pos)
#define SYSCTRL_XOSC_STARTUP_Pos 12 /**< \brief (SYSCTRL_XOSC) Start-Up Time */
#define SYSCTRL_XOSC_STARTUP_Msk (0xFu << SYSCTRL_XOSC_STARTUP_Pos)
#define SYSCTRL_XOSC_STARTUP(value) ((SYSCTRL_XOSC_STARTUP_Msk & ((value) << SYSCTRL_XOSC_STARTUP_Pos)))
#define SYSCTRL_XOSC_MASK 0xFFC6u /**< \brief (SYSCTRL_XOSC) MASK Register */
/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint16_t :1; /*!< bit: 11 Reserved */
uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_XOSC32K_OFFSET 0x14 /**< \brief (SYSCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define SYSCTRL_XOSC32K_RESETVALUE 0x0080 /**< \brief (SYSCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define SYSCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_XOSC32K) Oscillator Enable */
#define SYSCTRL_XOSC32K_ENABLE (0x1u << SYSCTRL_XOSC32K_ENABLE_Pos)
#define SYSCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (SYSCTRL_XOSC32K) Crystal Oscillator Enable */
#define SYSCTRL_XOSC32K_XTALEN (0x1u << SYSCTRL_XOSC32K_XTALEN_Pos)
#define SYSCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (SYSCTRL_XOSC32K) 32kHz Output Enable */
#define SYSCTRL_XOSC32K_EN32K (0x1u << SYSCTRL_XOSC32K_EN32K_Pos)
#define SYSCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (SYSCTRL_XOSC32K) 1kHz Output Enable */
#define SYSCTRL_XOSC32K_EN1K (0x1u << SYSCTRL_XOSC32K_EN1K_Pos)
#define SYSCTRL_XOSC32K_AAMPEN_Pos 5 /**< \brief (SYSCTRL_XOSC32K) Automatic Amplitude Control Enable */
#define SYSCTRL_XOSC32K_AAMPEN (0x1u << SYSCTRL_XOSC32K_AAMPEN_Pos)
#define SYSCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_XOSC32K) Run in Standby */
#define SYSCTRL_XOSC32K_RUNSTDBY (0x1u << SYSCTRL_XOSC32K_RUNSTDBY_Pos)
#define SYSCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_XOSC32K) On Demand Control */
#define SYSCTRL_XOSC32K_ONDEMAND (0x1u << SYSCTRL_XOSC32K_ONDEMAND_Pos)
#define SYSCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_XOSC32K) Oscillator Start-Up Time */
#define SYSCTRL_XOSC32K_STARTUP_Msk (0x7u << SYSCTRL_XOSC32K_STARTUP_Pos)
#define SYSCTRL_XOSC32K_STARTUP(value) ((SYSCTRL_XOSC32K_STARTUP_Msk & ((value) << SYSCTRL_XOSC32K_STARTUP_Pos)))
#define SYSCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_XOSC32K) Write Lock */
#define SYSCTRL_XOSC32K_WRTLOCK (0x1u << SYSCTRL_XOSC32K_WRTLOCK_Pos)
#define SYSCTRL_XOSC32K_MASK 0x17FEu /**< \brief (SYSCTRL_XOSC32K) MASK Register */
/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_OSC32K_OFFSET 0x18 /**< \brief (SYSCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
#define SYSCTRL_OSC32K_RESETVALUE 0x003F0080 /**< \brief (SYSCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
#define SYSCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC32K) Oscillator Enable */
#define SYSCTRL_OSC32K_ENABLE (0x1u << SYSCTRL_OSC32K_ENABLE_Pos)
#define SYSCTRL_OSC32K_EN32K_Pos 2 /**< \brief (SYSCTRL_OSC32K) 32kHz Output Enable */
#define SYSCTRL_OSC32K_EN32K (0x1u << SYSCTRL_OSC32K_EN32K_Pos)
#define SYSCTRL_OSC32K_EN1K_Pos 3 /**< \brief (SYSCTRL_OSC32K) 1kHz Output Enable */
#define SYSCTRL_OSC32K_EN1K (0x1u << SYSCTRL_OSC32K_EN1K_Pos)
#define SYSCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC32K) Run in Standby */
#define SYSCTRL_OSC32K_RUNSTDBY (0x1u << SYSCTRL_OSC32K_RUNSTDBY_Pos)
#define SYSCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC32K) On Demand Control */
#define SYSCTRL_OSC32K_ONDEMAND (0x1u << SYSCTRL_OSC32K_ONDEMAND_Pos)
#define SYSCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (SYSCTRL_OSC32K) Oscillator Start-Up Time */
#define SYSCTRL_OSC32K_STARTUP_Msk (0x7u << SYSCTRL_OSC32K_STARTUP_Pos)
#define SYSCTRL_OSC32K_STARTUP(value) ((SYSCTRL_OSC32K_STARTUP_Msk & ((value) << SYSCTRL_OSC32K_STARTUP_Pos)))
#define SYSCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (SYSCTRL_OSC32K) Write Lock */
#define SYSCTRL_OSC32K_WRTLOCK (0x1u << SYSCTRL_OSC32K_WRTLOCK_Pos)
#define SYSCTRL_OSC32K_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC32K) Oscillator Calibration */
#define SYSCTRL_OSC32K_CALIB_Msk (0x7Fu << SYSCTRL_OSC32K_CALIB_Pos)
#define SYSCTRL_OSC32K_CALIB(value) ((SYSCTRL_OSC32K_CALIB_Msk & ((value) << SYSCTRL_OSC32K_CALIB_Pos)))
#define SYSCTRL_OSC32K_MASK 0x007F17CEu /**< \brief (SYSCTRL_OSC32K) MASK Register */
/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (SYSCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#define SYSCTRL_OSCULP32K_RESETVALUE 0x1F /**< \brief (SYSCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#define SYSCTRL_OSCULP32K_CALIB_Pos 0 /**< \brief (SYSCTRL_OSCULP32K) Oscillator Calibration */
#define SYSCTRL_OSCULP32K_CALIB_Msk (0x1Fu << SYSCTRL_OSCULP32K_CALIB_Pos)
#define SYSCTRL_OSCULP32K_CALIB(value) ((SYSCTRL_OSCULP32K_CALIB_Msk & ((value) << SYSCTRL_OSCULP32K_CALIB_Pos)))
#define SYSCTRL_OSCULP32K_WRTLOCK_Pos 7 /**< \brief (SYSCTRL_OSCULP32K) Write Lock */
#define SYSCTRL_OSCULP32K_WRTLOCK (0x1u << SYSCTRL_OSCULP32K_WRTLOCK_Pos)
#define SYSCTRL_OSCULP32K_MASK 0x9Fu /**< \brief (SYSCTRL_OSCULP32K) MASK Register */
/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t :4; /*!< bit: 2.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
uint32_t :2; /*!< bit: 28..29 Reserved */
uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC8M_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_OSC8M_OFFSET 0x20 /**< \brief (SYSCTRL_OSC8M offset) 8MHz Internal Oscillator (OSC8M) Control */
#define SYSCTRL_OSC8M_RESETVALUE 0x87070382 /**< \brief (SYSCTRL_OSC8M reset_value) 8MHz Internal Oscillator (OSC8M) Control */
#define SYSCTRL_OSC8M_ENABLE_Pos 1 /**< \brief (SYSCTRL_OSC8M) Oscillator Enable */
#define SYSCTRL_OSC8M_ENABLE (0x1u << SYSCTRL_OSC8M_ENABLE_Pos)
#define SYSCTRL_OSC8M_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_OSC8M) Run in Standby */
#define SYSCTRL_OSC8M_RUNSTDBY (0x1u << SYSCTRL_OSC8M_RUNSTDBY_Pos)
#define SYSCTRL_OSC8M_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_OSC8M) On Demand Control */
#define SYSCTRL_OSC8M_ONDEMAND (0x1u << SYSCTRL_OSC8M_ONDEMAND_Pos)
#define SYSCTRL_OSC8M_PRESC_Pos 8 /**< \brief (SYSCTRL_OSC8M) Oscillator Prescaler */
#define SYSCTRL_OSC8M_PRESC_Msk (0x3u << SYSCTRL_OSC8M_PRESC_Pos)
#define SYSCTRL_OSC8M_PRESC(value) ((SYSCTRL_OSC8M_PRESC_Msk & ((value) << SYSCTRL_OSC8M_PRESC_Pos)))
#define SYSCTRL_OSC8M_PRESC_0_Val 0x0u /**< \brief (SYSCTRL_OSC8M) 1 */
#define SYSCTRL_OSC8M_PRESC_1_Val 0x1u /**< \brief (SYSCTRL_OSC8M) 2 */
#define SYSCTRL_OSC8M_PRESC_2_Val 0x2u /**< \brief (SYSCTRL_OSC8M) 4 */
#define SYSCTRL_OSC8M_PRESC_3_Val 0x3u /**< \brief (SYSCTRL_OSC8M) 8 */
#define SYSCTRL_OSC8M_PRESC_0 (SYSCTRL_OSC8M_PRESC_0_Val << SYSCTRL_OSC8M_PRESC_Pos)
#define SYSCTRL_OSC8M_PRESC_1 (SYSCTRL_OSC8M_PRESC_1_Val << SYSCTRL_OSC8M_PRESC_Pos)
#define SYSCTRL_OSC8M_PRESC_2 (SYSCTRL_OSC8M_PRESC_2_Val << SYSCTRL_OSC8M_PRESC_Pos)
#define SYSCTRL_OSC8M_PRESC_3 (SYSCTRL_OSC8M_PRESC_3_Val << SYSCTRL_OSC8M_PRESC_Pos)
#define SYSCTRL_OSC8M_CALIB_Pos 16 /**< \brief (SYSCTRL_OSC8M) Oscillator Calibration */
#define SYSCTRL_OSC8M_CALIB_Msk (0xFFFu << SYSCTRL_OSC8M_CALIB_Pos)
#define SYSCTRL_OSC8M_CALIB(value) ((SYSCTRL_OSC8M_CALIB_Msk & ((value) << SYSCTRL_OSC8M_CALIB_Pos)))
#define SYSCTRL_OSC8M_FRANGE_Pos 30 /**< \brief (SYSCTRL_OSC8M) Oscillator Frequency Range */
#define SYSCTRL_OSC8M_FRANGE_Msk (0x3u << SYSCTRL_OSC8M_FRANGE_Pos)
#define SYSCTRL_OSC8M_FRANGE(value) ((SYSCTRL_OSC8M_FRANGE_Msk & ((value) << SYSCTRL_OSC8M_FRANGE_Pos)))
#define SYSCTRL_OSC8M_FRANGE_0_Val 0x0u /**< \brief (SYSCTRL_OSC8M) 4 to 6MHz */
#define SYSCTRL_OSC8M_FRANGE_1_Val 0x1u /**< \brief (SYSCTRL_OSC8M) 6 to 8MHz */
#define SYSCTRL_OSC8M_FRANGE_2_Val 0x2u /**< \brief (SYSCTRL_OSC8M) 8 to 11MHz */
#define SYSCTRL_OSC8M_FRANGE_3_Val 0x3u /**< \brief (SYSCTRL_OSC8M) 11 to 15MHz */
#define SYSCTRL_OSC8M_FRANGE_0 (SYSCTRL_OSC8M_FRANGE_0_Val << SYSCTRL_OSC8M_FRANGE_Pos)
#define SYSCTRL_OSC8M_FRANGE_1 (SYSCTRL_OSC8M_FRANGE_1_Val << SYSCTRL_OSC8M_FRANGE_Pos)
#define SYSCTRL_OSC8M_FRANGE_2 (SYSCTRL_OSC8M_FRANGE_2_Val << SYSCTRL_OSC8M_FRANGE_Pos)
#define SYSCTRL_OSC8M_FRANGE_3 (SYSCTRL_OSC8M_FRANGE_3_Val << SYSCTRL_OSC8M_FRANGE_Pos)
#define SYSCTRL_OSC8M_MASK 0xCFFF03C2u /**< \brief (SYSCTRL_OSC8M) MASK Register */
/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_DFLLCTRL_OFFSET 0x24 /**< \brief (SYSCTRL_DFLLCTRL offset) DFLL48M Control */
#define SYSCTRL_DFLLCTRL_RESETVALUE 0x0080 /**< \brief (SYSCTRL_DFLLCTRL reset_value) DFLL48M Control */
#define SYSCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (SYSCTRL_DFLLCTRL) DFLL Enable */
#define SYSCTRL_DFLLCTRL_ENABLE (0x1u << SYSCTRL_DFLLCTRL_ENABLE_Pos)
#define SYSCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (SYSCTRL_DFLLCTRL) Operating Mode Selection */
#define SYSCTRL_DFLLCTRL_MODE (0x1u << SYSCTRL_DFLLCTRL_MODE_Pos)
#define SYSCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (SYSCTRL_DFLLCTRL) Stable DFLL Frequency */
#define SYSCTRL_DFLLCTRL_STABLE (0x1u << SYSCTRL_DFLLCTRL_STABLE_Pos)
#define SYSCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (SYSCTRL_DFLLCTRL) Lose Lock After Wake */
#define SYSCTRL_DFLLCTRL_LLAW (0x1u << SYSCTRL_DFLLCTRL_LLAW_Pos)
#define SYSCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (SYSCTRL_DFLLCTRL) USB Clock Recovery Mode */
#define SYSCTRL_DFLLCTRL_USBCRM (0x1u << SYSCTRL_DFLLCTRL_USBCRM_Pos)
#define SYSCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DFLLCTRL) Run in Standby */
#define SYSCTRL_DFLLCTRL_RUNSTDBY (0x1u << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos)
#define SYSCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DFLLCTRL) On Demand Control */
#define SYSCTRL_DFLLCTRL_ONDEMAND (0x1u << SYSCTRL_DFLLCTRL_ONDEMAND_Pos)
#define SYSCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (SYSCTRL_DFLLCTRL) Chill Cycle Disable */
#define SYSCTRL_DFLLCTRL_CCDIS (0x1u << SYSCTRL_DFLLCTRL_CCDIS_Pos)
#define SYSCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (SYSCTRL_DFLLCTRL) Quick Lock Disable */
#define SYSCTRL_DFLLCTRL_QLDIS (0x1u << SYSCTRL_DFLLCTRL_QLDIS_Pos)
#define SYSCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (SYSCTRL_DFLLCTRL) Bypass Coarse Lock */
#define SYSCTRL_DFLLCTRL_BPLCKC (0x1u << SYSCTRL_DFLLCTRL_BPLCKC_Pos)
#define SYSCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (SYSCTRL_DFLLCTRL) Wait Lock */
#define SYSCTRL_DFLLCTRL_WAITLOCK (0x1u << SYSCTRL_DFLLCTRL_WAITLOCK_Pos)
#define SYSCTRL_DFLLCTRL_MASK 0x0FFEu /**< \brief (SYSCTRL_DFLLCTRL) MASK Register */
/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_DFLLVAL_OFFSET 0x28 /**< \brief (SYSCTRL_DFLLVAL offset) DFLL48M Value */
#define SYSCTRL_DFLLVAL_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DFLLVAL reset_value) DFLL48M Value */
#define SYSCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (SYSCTRL_DFLLVAL) Fine Value */
#define SYSCTRL_DFLLVAL_FINE_Msk (0x3FFu << SYSCTRL_DFLLVAL_FINE_Pos)
#define SYSCTRL_DFLLVAL_FINE(value) ((SYSCTRL_DFLLVAL_FINE_Msk & ((value) << SYSCTRL_DFLLVAL_FINE_Pos)))
#define SYSCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (SYSCTRL_DFLLVAL) Coarse Value */
#define SYSCTRL_DFLLVAL_COARSE_Msk (0x3Fu << SYSCTRL_DFLLVAL_COARSE_Pos)
#define SYSCTRL_DFLLVAL_COARSE(value) ((SYSCTRL_DFLLVAL_COARSE_Msk & ((value) << SYSCTRL_DFLLVAL_COARSE_Pos)))
#define SYSCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (SYSCTRL_DFLLVAL) Multiplication Ratio Difference */
#define SYSCTRL_DFLLVAL_DIFF_Msk (0xFFFFu << SYSCTRL_DFLLVAL_DIFF_Pos)
#define SYSCTRL_DFLLVAL_DIFF(value) ((SYSCTRL_DFLLVAL_DIFF_Msk & ((value) << SYSCTRL_DFLLVAL_DIFF_Pos)))
#define SYSCTRL_DFLLVAL_MASK 0xFFFFFFFFu /**< \brief (SYSCTRL_DFLLVAL) MASK Register */
/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLMUL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_DFLLMUL_OFFSET 0x2C /**< \brief (SYSCTRL_DFLLMUL offset) DFLL48M Multiplier */
#define SYSCTRL_DFLLMUL_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DFLLMUL reset_value) DFLL48M Multiplier */
#define SYSCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (SYSCTRL_DFLLMUL) DFLL Multiply Factor */
#define SYSCTRL_DFLLMUL_MUL_Msk (0xFFFFu << SYSCTRL_DFLLMUL_MUL_Pos)
#define SYSCTRL_DFLLMUL_MUL(value) ((SYSCTRL_DFLLMUL_MUL_Msk & ((value) << SYSCTRL_DFLLMUL_MUL_Pos)))
#define SYSCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (SYSCTRL_DFLLMUL) Fine Maximum Step */
#define SYSCTRL_DFLLMUL_FSTEP_Msk (0x3FFu << SYSCTRL_DFLLMUL_FSTEP_Pos)
#define SYSCTRL_DFLLMUL_FSTEP(value) ((SYSCTRL_DFLLMUL_FSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_FSTEP_Pos)))
#define SYSCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (SYSCTRL_DFLLMUL) Coarse Maximum Step */
#define SYSCTRL_DFLLMUL_CSTEP_Msk (0x3Fu << SYSCTRL_DFLLMUL_CSTEP_Pos)
#define SYSCTRL_DFLLMUL_CSTEP(value) ((SYSCTRL_DFLLMUL_CSTEP_Msk & ((value) << SYSCTRL_DFLLMUL_CSTEP_Pos)))
#define SYSCTRL_DFLLMUL_MASK 0xFFFFFFFFu /**< \brief (SYSCTRL_DFLLMUL) MASK Register */
/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t READREQ:1; /*!< bit: 7 Read Request */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLSYNC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_DFLLSYNC_OFFSET 0x30 /**< \brief (SYSCTRL_DFLLSYNC offset) DFLL48M Synchronization */
#define SYSCTRL_DFLLSYNC_RESETVALUE 0x00 /**< \brief (SYSCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */
#define SYSCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (SYSCTRL_DFLLSYNC) Read Request */
#define SYSCTRL_DFLLSYNC_READREQ (0x1u << SYSCTRL_DFLLSYNC_READREQ_Pos)
#define SYSCTRL_DFLLSYNC_MASK 0x80u /**< \brief (SYSCTRL_DFLLSYNC) MASK Register */
/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t HYST:1; /*!< bit: 2 Hysteresis */
uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
uint32_t :1; /*!< bit: 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MODE:1; /*!< bit: 8 Operation Mode */
uint32_t CEN:1; /*!< bit: 9 Clock Enable */
uint32_t :2; /*!< bit: 10..11 Reserved */
uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_BOD33_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_BOD33_OFFSET 0x34 /**< \brief (SYSCTRL_BOD33 offset) 3.3V Brown-Out Detector (BOD33) Control */
#define SYSCTRL_BOD33_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_BOD33 reset_value) 3.3V Brown-Out Detector (BOD33) Control */
#define SYSCTRL_BOD33_ENABLE_Pos 1 /**< \brief (SYSCTRL_BOD33) Enable */
#define SYSCTRL_BOD33_ENABLE (0x1u << SYSCTRL_BOD33_ENABLE_Pos)
#define SYSCTRL_BOD33_HYST_Pos 2 /**< \brief (SYSCTRL_BOD33) Hysteresis */
#define SYSCTRL_BOD33_HYST (0x1u << SYSCTRL_BOD33_HYST_Pos)
#define SYSCTRL_BOD33_ACTION_Pos 3 /**< \brief (SYSCTRL_BOD33) BOD33 Action */
#define SYSCTRL_BOD33_ACTION_Msk (0x3u << SYSCTRL_BOD33_ACTION_Pos)
#define SYSCTRL_BOD33_ACTION(value) ((SYSCTRL_BOD33_ACTION_Msk & ((value) << SYSCTRL_BOD33_ACTION_Pos)))
#define SYSCTRL_BOD33_ACTION_NONE_Val 0x0u /**< \brief (SYSCTRL_BOD33) No action */
#define SYSCTRL_BOD33_ACTION_RESET_Val 0x1u /**< \brief (SYSCTRL_BOD33) The BOD33 generates a reset */
#define SYSCTRL_BOD33_ACTION_INTERRUPT_Val 0x2u /**< \brief (SYSCTRL_BOD33) The BOD33 generates an interrupt */
#define SYSCTRL_BOD33_ACTION_NONE (SYSCTRL_BOD33_ACTION_NONE_Val << SYSCTRL_BOD33_ACTION_Pos)
#define SYSCTRL_BOD33_ACTION_RESET (SYSCTRL_BOD33_ACTION_RESET_Val << SYSCTRL_BOD33_ACTION_Pos)
#define SYSCTRL_BOD33_ACTION_INTERRUPT (SYSCTRL_BOD33_ACTION_INTERRUPT_Val << SYSCTRL_BOD33_ACTION_Pos)
#define SYSCTRL_BOD33_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_BOD33) Run in Standby */
#define SYSCTRL_BOD33_RUNSTDBY (0x1u << SYSCTRL_BOD33_RUNSTDBY_Pos)
#define SYSCTRL_BOD33_MODE_Pos 8 /**< \brief (SYSCTRL_BOD33) Operation Mode */
#define SYSCTRL_BOD33_MODE (0x1u << SYSCTRL_BOD33_MODE_Pos)
#define SYSCTRL_BOD33_CEN_Pos 9 /**< \brief (SYSCTRL_BOD33) Clock Enable */
#define SYSCTRL_BOD33_CEN (0x1u << SYSCTRL_BOD33_CEN_Pos)
#define SYSCTRL_BOD33_PSEL_Pos 12 /**< \brief (SYSCTRL_BOD33) Prescaler Select */
#define SYSCTRL_BOD33_PSEL_Msk (0xFu << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL(value) ((SYSCTRL_BOD33_PSEL_Msk & ((value) << SYSCTRL_BOD33_PSEL_Pos)))
#define SYSCTRL_BOD33_PSEL_DIV2_Val 0x0u /**< \brief (SYSCTRL_BOD33) Divide clock by 2 */
#define SYSCTRL_BOD33_PSEL_DIV4_Val 0x1u /**< \brief (SYSCTRL_BOD33) Divide clock by 4 */
#define SYSCTRL_BOD33_PSEL_DIV8_Val 0x2u /**< \brief (SYSCTRL_BOD33) Divide clock by 8 */
#define SYSCTRL_BOD33_PSEL_DIV16_Val 0x3u /**< \brief (SYSCTRL_BOD33) Divide clock by 16 */
#define SYSCTRL_BOD33_PSEL_DIV32_Val 0x4u /**< \brief (SYSCTRL_BOD33) Divide clock by 32 */
#define SYSCTRL_BOD33_PSEL_DIV64_Val 0x5u /**< \brief (SYSCTRL_BOD33) Divide clock by 64 */
#define SYSCTRL_BOD33_PSEL_DIV128_Val 0x6u /**< \brief (SYSCTRL_BOD33) Divide clock by 128 */
#define SYSCTRL_BOD33_PSEL_DIV256_Val 0x7u /**< \brief (SYSCTRL_BOD33) Divide clock by 256 */
#define SYSCTRL_BOD33_PSEL_DIV512_Val 0x8u /**< \brief (SYSCTRL_BOD33) Divide clock by 512 */
#define SYSCTRL_BOD33_PSEL_DIV1K_Val 0x9u /**< \brief (SYSCTRL_BOD33) Divide clock by 1024 */
#define SYSCTRL_BOD33_PSEL_DIV2K_Val 0xAu /**< \brief (SYSCTRL_BOD33) Divide clock by 2048 */
#define SYSCTRL_BOD33_PSEL_DIV4K_Val 0xBu /**< \brief (SYSCTRL_BOD33) Divide clock by 4096 */
#define SYSCTRL_BOD33_PSEL_DIV8K_Val 0xCu /**< \brief (SYSCTRL_BOD33) Divide clock by 8192 */
#define SYSCTRL_BOD33_PSEL_DIV16K_Val 0xDu /**< \brief (SYSCTRL_BOD33) Divide clock by 16384 */
#define SYSCTRL_BOD33_PSEL_DIV32K_Val 0xEu /**< \brief (SYSCTRL_BOD33) Divide clock by 32768 */
#define SYSCTRL_BOD33_PSEL_DIV64K_Val 0xFu /**< \brief (SYSCTRL_BOD33) Divide clock by 65536 */
#define SYSCTRL_BOD33_PSEL_DIV2 (SYSCTRL_BOD33_PSEL_DIV2_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV4 (SYSCTRL_BOD33_PSEL_DIV4_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV8 (SYSCTRL_BOD33_PSEL_DIV8_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV16 (SYSCTRL_BOD33_PSEL_DIV16_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV32 (SYSCTRL_BOD33_PSEL_DIV32_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV64 (SYSCTRL_BOD33_PSEL_DIV64_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV128 (SYSCTRL_BOD33_PSEL_DIV128_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV256 (SYSCTRL_BOD33_PSEL_DIV256_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV512 (SYSCTRL_BOD33_PSEL_DIV512_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV1K (SYSCTRL_BOD33_PSEL_DIV1K_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV2K (SYSCTRL_BOD33_PSEL_DIV2K_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV4K (SYSCTRL_BOD33_PSEL_DIV4K_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV8K (SYSCTRL_BOD33_PSEL_DIV8K_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV16K (SYSCTRL_BOD33_PSEL_DIV16K_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV32K (SYSCTRL_BOD33_PSEL_DIV32K_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_PSEL_DIV64K (SYSCTRL_BOD33_PSEL_DIV64K_Val << SYSCTRL_BOD33_PSEL_Pos)
#define SYSCTRL_BOD33_LEVEL_Pos 16 /**< \brief (SYSCTRL_BOD33) BOD33 Threshold Level */
#define SYSCTRL_BOD33_LEVEL_Msk (0x3Fu << SYSCTRL_BOD33_LEVEL_Pos)
#define SYSCTRL_BOD33_LEVEL(value) ((SYSCTRL_BOD33_LEVEL_Msk & ((value) << SYSCTRL_BOD33_LEVEL_Pos)))
#define SYSCTRL_BOD33_MASK 0x003FF35Eu /**< \brief (SYSCTRL_BOD33) MASK Register */
/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :6; /*!< bit: 0.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t :6; /*!< bit: 7..12 Reserved */
uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_VREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_VREG_OFFSET 0x3C /**< \brief (SYSCTRL_VREG offset) Voltage Regulator System (VREG) Control */
#define SYSCTRL_VREG_RESETVALUE 0x0000 /**< \brief (SYSCTRL_VREG reset_value) Voltage Regulator System (VREG) Control */
#define SYSCTRL_VREG_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_VREG) Run in Standby */
#define SYSCTRL_VREG_RUNSTDBY (0x1u << SYSCTRL_VREG_RUNSTDBY_Pos)
#define SYSCTRL_VREG_FORCELDO_Pos 13 /**< \brief (SYSCTRL_VREG) Force LDO Voltage Regulator */
#define SYSCTRL_VREG_FORCELDO (0x1u << SYSCTRL_VREG_FORCELDO_Pos)
#define SYSCTRL_VREG_MASK 0x2040u /**< \brief (SYSCTRL_VREG) MASK Register */
/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
uint32_t :13; /*!< bit: 3..15 Reserved */
uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_VREF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_VREF_OFFSET 0x40 /**< \brief (SYSCTRL_VREF offset) Voltage References System (VREF) Control */
#define SYSCTRL_VREF_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_VREF reset_value) Voltage References System (VREF) Control */
#define SYSCTRL_VREF_TSEN_Pos 1 /**< \brief (SYSCTRL_VREF) Temperature Sensor Enable */
#define SYSCTRL_VREF_TSEN (0x1u << SYSCTRL_VREF_TSEN_Pos)
#define SYSCTRL_VREF_BGOUTEN_Pos 2 /**< \brief (SYSCTRL_VREF) Bandgap Output Enable */
#define SYSCTRL_VREF_BGOUTEN (0x1u << SYSCTRL_VREF_BGOUTEN_Pos)
#define SYSCTRL_VREF_CALIB_Pos 16 /**< \brief (SYSCTRL_VREF) Bandgap Voltage Generator Calibration */
#define SYSCTRL_VREF_CALIB_Msk (0x7FFu << SYSCTRL_VREF_CALIB_Pos)
#define SYSCTRL_VREF_CALIB(value) ((SYSCTRL_VREF_CALIB_Msk & ((value) << SYSCTRL_VREF_CALIB_Pos)))
#define SYSCTRL_VREF_MASK 0x07FF0006u /**< \brief (SYSCTRL_VREF) MASK Register */
/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_DPLLCTRLA_OFFSET 0x44 /**< \brief (SYSCTRL_DPLLCTRLA offset) DPLL Control A */
#define SYSCTRL_DPLLCTRLA_RESETVALUE 0x80 /**< \brief (SYSCTRL_DPLLCTRLA reset_value) DPLL Control A */
#define SYSCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (SYSCTRL_DPLLCTRLA) DPLL Enable */
#define SYSCTRL_DPLLCTRLA_ENABLE (0x1u << SYSCTRL_DPLLCTRLA_ENABLE_Pos)
#define SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (SYSCTRL_DPLLCTRLA) Run in Standby */
#define SYSCTRL_DPLLCTRLA_RUNSTDBY (0x1u << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos)
#define SYSCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (SYSCTRL_DPLLCTRLA) On Demand Clock Activation */
#define SYSCTRL_DPLLCTRLA_ONDEMAND (0x1u << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos)
#define SYSCTRL_DPLLCTRLA_MASK 0xC2u /**< \brief (SYSCTRL_DPLLCTRLA) MASK Register */
/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLRATIO_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_DPLLRATIO_OFFSET 0x48 /**< \brief (SYSCTRL_DPLLRATIO offset) DPLL Ratio Control */
#define SYSCTRL_DPLLRATIO_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
#define SYSCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio */
#define SYSCTRL_DPLLRATIO_LDR_Msk (0xFFFu << SYSCTRL_DPLLRATIO_LDR_Pos)
#define SYSCTRL_DPLLRATIO_LDR(value) ((SYSCTRL_DPLLRATIO_LDR_Msk & ((value) << SYSCTRL_DPLLRATIO_LDR_Pos)))
#define SYSCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (SYSCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
#define SYSCTRL_DPLLRATIO_LDRFRAC_Msk (0xFu << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)
#define SYSCTRL_DPLLRATIO_LDRFRAC(value) ((SYSCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << SYSCTRL_DPLLRATIO_LDRFRAC_Pos)))
#define SYSCTRL_DPLLRATIO_MASK 0x000F0FFFu /**< \brief (SYSCTRL_DPLLRATIO) MASK Register */
/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_DPLLCTRLB_OFFSET 0x4C /**< \brief (SYSCTRL_DPLLCTRLB offset) DPLL Control B */
#define SYSCTRL_DPLLCTRLB_RESETVALUE 0x00000000 /**< \brief (SYSCTRL_DPLLCTRLB reset_value) DPLL Control B */
#define SYSCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (SYSCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
#define SYSCTRL_DPLLCTRLB_FILTER_Msk (0x3u << SYSCTRL_DPLLCTRLB_FILTER_Pos)
#define SYSCTRL_DPLLCTRLB_FILTER(value) ((SYSCTRL_DPLLCTRLB_FILTER_Msk & ((value) << SYSCTRL_DPLLCTRLB_FILTER_Pos)))
#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val 0x0u /**< \brief (SYSCTRL_DPLLCTRLB) Default filter mode */
#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val 0x1u /**< \brief (SYSCTRL_DPLLCTRLB) Low bandwidth filter */
#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val 0x2u /**< \brief (SYSCTRL_DPLLCTRLB) High bandwidth filter */
#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val 0x3u /**< \brief (SYSCTRL_DPLLCTRLB) High damping filter */
#define SYSCTRL_DPLLCTRLB_FILTER_DEFAULT (SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
#define SYSCTRL_DPLLCTRLB_FILTER_LBFILT (SYSCTRL_DPLLCTRLB_FILTER_LBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
#define SYSCTRL_DPLLCTRLB_FILTER_HBFILT (SYSCTRL_DPLLCTRLB_FILTER_HBFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
#define SYSCTRL_DPLLCTRLB_FILTER_HDFILT (SYSCTRL_DPLLCTRLB_FILTER_HDFILT_Val << SYSCTRL_DPLLCTRLB_FILTER_Pos)
#define SYSCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (SYSCTRL_DPLLCTRLB) Low-Power Enable */
#define SYSCTRL_DPLLCTRLB_LPEN (0x1u << SYSCTRL_DPLLCTRLB_LPEN_Pos)
#define SYSCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (SYSCTRL_DPLLCTRLB) Wake Up Fast */
#define SYSCTRL_DPLLCTRLB_WUF (0x1u << SYSCTRL_DPLLCTRLB_WUF_Pos)
#define SYSCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (SYSCTRL_DPLLCTRLB) Reference Clock Selection */
#define SYSCTRL_DPLLCTRLB_REFCLK_Msk (0x3u << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
#define SYSCTRL_DPLLCTRLB_REFCLK(value) ((SYSCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << SYSCTRL_DPLLCTRLB_REFCLK_Pos)))
#define SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val 0x0u /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF0 clock reference */
#define SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val 0x1u /**< \brief (SYSCTRL_DPLLCTRLB) CLK_DPLL_REF1 clock reference */
#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val 0x2u /**< \brief (SYSCTRL_DPLLCTRLB) GCLK_DPLL clock reference */
#define SYSCTRL_DPLLCTRLB_REFCLK_REF0 (SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
#define SYSCTRL_DPLLCTRLB_REFCLK_REF1 (SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
#define SYSCTRL_DPLLCTRLB_REFCLK_GCLK (SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val << SYSCTRL_DPLLCTRLB_REFCLK_Pos)
#define SYSCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Time */
#define SYSCTRL_DPLLCTRLB_LTIME_Msk (0x7u << SYSCTRL_DPLLCTRLB_LTIME_Pos)
#define SYSCTRL_DPLLCTRLB_LTIME(value) ((SYSCTRL_DPLLCTRLB_LTIME_Msk & ((value) << SYSCTRL_DPLLCTRLB_LTIME_Pos)))
#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val 0x0u /**< \brief (SYSCTRL_DPLLCTRLB) No time-out */
#define SYSCTRL_DPLLCTRLB_LTIME_8MS_Val 0x4u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 8 ms */
#define SYSCTRL_DPLLCTRLB_LTIME_9MS_Val 0x5u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 9 ms */
#define SYSCTRL_DPLLCTRLB_LTIME_10MS_Val 0x6u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 10 ms */
#define SYSCTRL_DPLLCTRLB_LTIME_11MS_Val 0x7u /**< \brief (SYSCTRL_DPLLCTRLB) Time-out if no lock within 11 ms */
#define SYSCTRL_DPLLCTRLB_LTIME_DEFAULT (SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
#define SYSCTRL_DPLLCTRLB_LTIME_8MS (SYSCTRL_DPLLCTRLB_LTIME_8MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
#define SYSCTRL_DPLLCTRLB_LTIME_9MS (SYSCTRL_DPLLCTRLB_LTIME_9MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
#define SYSCTRL_DPLLCTRLB_LTIME_10MS (SYSCTRL_DPLLCTRLB_LTIME_10MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
#define SYSCTRL_DPLLCTRLB_LTIME_11MS (SYSCTRL_DPLLCTRLB_LTIME_11MS_Val << SYSCTRL_DPLLCTRLB_LTIME_Pos)
#define SYSCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (SYSCTRL_DPLLCTRLB) Lock Bypass */
#define SYSCTRL_DPLLCTRLB_LBYPASS (0x1u << SYSCTRL_DPLLCTRLB_LBYPASS_Pos)
#define SYSCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (SYSCTRL_DPLLCTRLB) Clock Divider */
#define SYSCTRL_DPLLCTRLB_DIV_Msk (0x7FFu << SYSCTRL_DPLLCTRLB_DIV_Pos)
#define SYSCTRL_DPLLCTRLB_DIV(value) ((SYSCTRL_DPLLCTRLB_DIV_Msk & ((value) << SYSCTRL_DPLLCTRLB_DIV_Pos)))
#define SYSCTRL_DPLLCTRLB_MASK 0x07FF173Fu /**< \brief (SYSCTRL_DPLLCTRLB) MASK Register */
/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
uint8_t DIV:1; /*!< bit: 3 Divider Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SYSCTRL_DPLLSTATUS_OFFSET 0x50 /**< \brief (SYSCTRL_DPLLSTATUS offset) DPLL Status */
#define SYSCTRL_DPLLSTATUS_RESETVALUE 0x00 /**< \brief (SYSCTRL_DPLLSTATUS reset_value) DPLL Status */
#define SYSCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Lock Status */
#define SYSCTRL_DPLLSTATUS_LOCK (0x1u << SYSCTRL_DPLLSTATUS_LOCK_Pos)
#define SYSCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (SYSCTRL_DPLLSTATUS) Output Clock Ready */
#define SYSCTRL_DPLLSTATUS_CLKRDY (0x1u << SYSCTRL_DPLLSTATUS_CLKRDY_Pos)
#define SYSCTRL_DPLLSTATUS_ENABLE_Pos 2 /**< \brief (SYSCTRL_DPLLSTATUS) DPLL Enable */
#define SYSCTRL_DPLLSTATUS_ENABLE (0x1u << SYSCTRL_DPLLSTATUS_ENABLE_Pos)
#define SYSCTRL_DPLLSTATUS_DIV_Pos 3 /**< \brief (SYSCTRL_DPLLSTATUS) Divider Enable */
#define SYSCTRL_DPLLSTATUS_DIV (0x1u << SYSCTRL_DPLLSTATUS_DIV_Pos)
#define SYSCTRL_DPLLSTATUS_MASK 0x0Fu /**< \brief (SYSCTRL_DPLLSTATUS) MASK Register */
/** \brief SYSCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
RoReg8 Reserved1[0x2];
__IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
RoReg8 Reserved2[0x2];
__IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
__IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
RoReg8 Reserved3[0x3];
__IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
__IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
RoReg8 Reserved4[0x2];
__IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
__IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
__IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
RoReg8 Reserved5[0x3];
__IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
RoReg8 Reserved6[0x4];
__IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
RoReg8 Reserved7[0x2];
__IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
__IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
RoReg8 Reserved8[0x3];
__IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
__IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
__I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
} Sysctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_SYSCTRL_COMPONENT_ */

684
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/tc.h Normal file
View file

@ -0,0 +1,684 @@
/**
* \file
*
* \brief Component description for TC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_TC_COMPONENT_
#define _SAMD21_TC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR TC */
/* ========================================================================== */
/** \addtogroup SAMD21_TC Basic Timer Counter */
/*@{*/
#define TC_U2212
#define REV_TC 0x121
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
uint16_t :1; /*!< bit: 4 Reserved */
uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
#define TC_CTRLA_RESETVALUE 0x0000 /**< \brief (TC_CTRLA reset_value) Control A */
#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
#define TC_CTRLA_SWRST (0x1u << TC_CTRLA_SWRST_Pos)
#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
#define TC_CTRLA_ENABLE (0x1u << TC_CTRLA_ENABLE_Pos)
#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */
#define TC_CTRLA_MODE_Msk (0x3u << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE(value) ((TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)))
#define TC_CTRLA_MODE_COUNT16_Val 0x0u /**< \brief (TC_CTRLA) Counter in 16-bit mode */
#define TC_CTRLA_MODE_COUNT8_Val 0x1u /**< \brief (TC_CTRLA) Counter in 8-bit mode */
#define TC_CTRLA_MODE_COUNT32_Val 0x2u /**< \brief (TC_CTRLA) Counter in 32-bit mode */
#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */
#define TC_CTRLA_WAVEGEN_Msk (0x3u << TC_CTRLA_WAVEGEN_Pos)
#define TC_CTRLA_WAVEGEN(value) ((TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)))
#define TC_CTRLA_WAVEGEN_NFRQ_Val 0x0u /**< \brief (TC_CTRLA) */
#define TC_CTRLA_WAVEGEN_MFRQ_Val 0x1u /**< \brief (TC_CTRLA) */
#define TC_CTRLA_WAVEGEN_NPWM_Val 0x2u /**< \brief (TC_CTRLA) */
#define TC_CTRLA_WAVEGEN_MPWM_Val 0x3u /**< \brief (TC_CTRLA) */
#define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
#define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos)
#define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos)
#define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)
#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
#define TC_CTRLA_PRESCALER_Msk (0x7u << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER(value) ((TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)))
#define TC_CTRLA_PRESCALER_DIV1_Val 0x0u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
#define TC_CTRLA_PRESCALER_DIV2_Val 0x1u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
#define TC_CTRLA_PRESCALER_DIV4_Val 0x2u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
#define TC_CTRLA_PRESCALER_DIV8_Val 0x3u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
#define TC_CTRLA_PRESCALER_DIV16_Val 0x4u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
#define TC_CTRLA_PRESCALER_DIV64_Val 0x5u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
#define TC_CTRLA_PRESCALER_DIV256_Val 0x6u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
#define TC_CTRLA_PRESCALER_DIV1024_Val 0x7u /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */
#define TC_CTRLA_RUNSTDBY (0x1u << TC_CTRLA_RUNSTDBY_Pos)
#define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
#define TC_CTRLA_PRESCSYNC_Msk (0x3u << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC(value) ((TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)))
#define TC_CTRLA_PRESCSYNC_GCLK_Val 0x0u /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
#define TC_CTRLA_PRESCSYNC_PRESC_Val 0x1u /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
#define TC_CTRLA_PRESCSYNC_RESYNC_Val 0x2u /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter */
#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_MASK 0x3F6Fu /**< \brief (TC_CTRLA) MASK Register */
/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
uint16_t :9; /*!< bit: 5..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */
#define TC_READREQ_RESETVALUE 0x0000 /**< \brief (TC_READREQ reset_value) Read Request */
#define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */
#define TC_READREQ_ADDR_Msk (0x1Fu << TC_READREQ_ADDR_Pos)
#define TC_READREQ_ADDR(value) ((TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)))
#define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */
#define TC_READREQ_RCONT (0x1u << TC_READREQ_RCONT_Pos)
#define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */
#define TC_READREQ_RREQ (0x1u << TC_READREQ_RREQ_Pos)
#define TC_READREQ_MASK 0xC01Fu /**< \brief (TC_READREQ) MASK Register */
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
#define TC_CTRLBCLR_RESETVALUE 0x02 /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
#define TC_CTRLBCLR_DIR (0x1u << TC_CTRLBCLR_DIR_Pos)
#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */
#define TC_CTRLBCLR_ONESHOT (0x1u << TC_CTRLBCLR_ONESHOT_Pos)
#define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */
#define TC_CTRLBCLR_CMD_Msk (0x3u << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD(value) ((TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)))
#define TC_CTRLBCLR_CMD_NONE_Val 0x0u /**< \brief (TC_CTRLBCLR) No action */
#define TC_CTRLBCLR_CMD_RETRIGGER_Val 0x1u /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
#define TC_CTRLBCLR_CMD_STOP_Val 0x2u /**< \brief (TC_CTRLBCLR) Force a stop */
#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_MASK 0xC5u /**< \brief (TC_CTRLBCLR) MASK Register */
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
#define TC_CTRLBSET_RESETVALUE 0x00 /**< \brief (TC_CTRLBSET reset_value) Control B Set */
#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
#define TC_CTRLBSET_DIR (0x1u << TC_CTRLBSET_DIR_Pos)
#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot */
#define TC_CTRLBSET_ONESHOT (0x1u << TC_CTRLBSET_ONESHOT_Pos)
#define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */
#define TC_CTRLBSET_CMD_Msk (0x3u << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD(value) ((TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)))
#define TC_CTRLBSET_CMD_NONE_Val 0x0u /**< \brief (TC_CTRLBSET) No action */
#define TC_CTRLBSET_CMD_RETRIGGER_Val 0x1u /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
#define TC_CTRLBSET_CMD_STOP_Val 0x2u /**< \brief (TC_CTRLBSET) Force a stop */
#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_MASK 0xC5u /**< \brief (TC_CTRLBSET) MASK Register */
/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */
#define TC_CTRLC_RESETVALUE 0x00 /**< \brief (TC_CTRLC reset_value) Control C */
#define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */
#define TC_CTRLC_INVEN0 (1 << TC_CTRLC_INVEN0_Pos)
#define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */
#define TC_CTRLC_INVEN1 (1 << TC_CTRLC_INVEN1_Pos)
#define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */
#define TC_CTRLC_INVEN_Msk (0x3u << TC_CTRLC_INVEN_Pos)
#define TC_CTRLC_INVEN(value) ((TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)))
#define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */
#define TC_CTRLC_CPTEN0 (1 << TC_CTRLC_CPTEN0_Pos)
#define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */
#define TC_CTRLC_CPTEN1 (1 << TC_CTRLC_CPTEN1_Pos)
#define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */
#define TC_CTRLC_CPTEN_Msk (0x3u << TC_CTRLC_CPTEN_Pos)
#define TC_CTRLC_CPTEN(value) ((TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)))
#define TC_CTRLC_MASK 0x33u /**< \brief (TC_CTRLC) MASK Register */
/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */
#define TC_DBGCTRL_RESETVALUE 0x00 /**< \brief (TC_DBGCTRL reset_value) Debug Control */
#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */
#define TC_DBGCTRL_DBGRUN (0x1u << TC_DBGCTRL_DBGRUN_Pos)
#define TC_DBGCTRL_MASK 0x01u /**< \brief (TC_DBGCTRL) MASK Register */
/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
uint16_t :1; /*!< bit: 3 Reserved */
uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
uint16_t :3; /*!< bit: 9..11 Reserved */
uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :12; /*!< bit: 0..11 Reserved */
uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */
#define TC_EVCTRL_RESETVALUE 0x0000 /**< \brief (TC_EVCTRL reset_value) Event Control */
#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
#define TC_EVCTRL_EVACT_Msk (0x7u << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT(value) ((TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)))
#define TC_EVCTRL_EVACT_OFF_Val 0x0u /**< \brief (TC_EVCTRL) Event action disabled */
#define TC_EVCTRL_EVACT_RETRIGGER_Val 0x1u /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
#define TC_EVCTRL_EVACT_COUNT_Val 0x2u /**< \brief (TC_EVCTRL) Count on event */
#define TC_EVCTRL_EVACT_START_Val 0x3u /**< \brief (TC_EVCTRL) Start TC on event */
#define TC_EVCTRL_EVACT_PPW_Val 0x5u /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */
#define TC_EVCTRL_EVACT_PWP_Val 0x6u /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */
#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */
#define TC_EVCTRL_TCINV (0x1u << TC_EVCTRL_TCINV_Pos)
#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */
#define TC_EVCTRL_TCEI (0x1u << TC_EVCTRL_TCEI_Pos)
#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */
#define TC_EVCTRL_OVFEO (0x1u << TC_EVCTRL_OVFEO_Pos)
#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */
#define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos)
#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */
#define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos)
#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */
#define TC_EVCTRL_MCEO_Msk (0x3u << TC_EVCTRL_MCEO_Pos)
#define TC_EVCTRL_MCEO(value) ((TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)))
#define TC_EVCTRL_MASK 0x3137u /**< \brief (TC_EVCTRL) MASK Register */
/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
#define TC_INTENCLR_RESETVALUE 0x00 /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */
#define TC_INTENCLR_OVF (0x1u << TC_INTENCLR_OVF_Pos)
#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */
#define TC_INTENCLR_ERR (0x1u << TC_INTENCLR_ERR_Pos)
#define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */
#define TC_INTENCLR_SYNCRDY (0x1u << TC_INTENCLR_SYNCRDY_Pos)
#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */
#define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos)
#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */
#define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos)
#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */
#define TC_INTENCLR_MC_Msk (0x3u << TC_INTENCLR_MC_Pos)
#define TC_INTENCLR_MC(value) ((TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)))
#define TC_INTENCLR_MASK 0x3Bu /**< \brief (TC_INTENCLR) MASK Register */
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
#define TC_INTENSET_RESETVALUE 0x00 /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */
#define TC_INTENSET_OVF (0x1u << TC_INTENSET_OVF_Pos)
#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */
#define TC_INTENSET_ERR (0x1u << TC_INTENSET_ERR_Pos)
#define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */
#define TC_INTENSET_SYNCRDY (0x1u << TC_INTENSET_SYNCRDY_Pos)
#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */
#define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos)
#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */
#define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos)
#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */
#define TC_INTENSET_MC_Msk (0x3u << TC_INTENSET_MC_Pos)
#define TC_INTENSET_MC(value) ((TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)))
#define TC_INTENSET_MASK 0x3Bu /**< \brief (TC_INTENSET) MASK Register */
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow */
uint8_t ERR:1; /*!< bit: 1 Error */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
#define TC_INTFLAG_RESETVALUE 0x00 /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */
#define TC_INTFLAG_OVF (0x1u << TC_INTFLAG_OVF_Pos)
#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */
#define TC_INTFLAG_ERR (0x1u << TC_INTFLAG_ERR_Pos)
#define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */
#define TC_INTFLAG_SYNCRDY (0x1u << TC_INTFLAG_SYNCRDY_Pos)
#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */
#define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos)
#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */
#define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos)
#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */
#define TC_INTFLAG_MC_Msk (0x3u << TC_INTFLAG_MC_Pos)
#define TC_INTFLAG_MC(value) ((TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)))
#define TC_INTFLAG_MASK 0x3Bu /**< \brief (TC_INTFLAG) MASK Register */
/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :3; /*!< bit: 0.. 2 Reserved */
uint8_t STOP:1; /*!< bit: 3 Stop */
uint8_t SLAVE:1; /*!< bit: 4 Slave */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */
#define TC_STATUS_RESETVALUE 0x08 /**< \brief (TC_STATUS reset_value) Status */
#define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */
#define TC_STATUS_STOP (0x1u << TC_STATUS_STOP_Pos)
#define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */
#define TC_STATUS_SLAVE (0x1u << TC_STATUS_SLAVE_Pos)
#define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */
#define TC_STATUS_SYNCBUSY (0x1u << TC_STATUS_SYNCBUSY_Pos)
#define TC_STATUS_MASK 0x98u /**< \brief (TC_STATUS) MASK Register */
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */
#define TC_COUNT16_COUNT_RESETVALUE 0x0000 /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */
#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Count Value */
#define TC_COUNT16_COUNT_COUNT_Msk (0xFFFFu << TC_COUNT16_COUNT_COUNT_Pos)
#define TC_COUNT16_COUNT_COUNT(value) ((TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)))
#define TC_COUNT16_COUNT_MASK 0xFFFFu /**< \brief (TC_COUNT16_COUNT) MASK Register */
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */
#define TC_COUNT32_COUNT_RESETVALUE 0x00000000 /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */
#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Count Value */
#define TC_COUNT32_COUNT_COUNT_Msk (0xFFFFFFFFu << TC_COUNT32_COUNT_COUNT_Pos)
#define TC_COUNT32_COUNT_COUNT(value) ((TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)))
#define TC_COUNT32_COUNT_MASK 0xFFFFFFFFu /**< \brief (TC_COUNT32_COUNT) MASK Register */
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */
#define TC_COUNT8_COUNT_RESETVALUE 0x00 /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */
#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
#define TC_COUNT8_COUNT_COUNT_Msk (0xFFu << TC_COUNT8_COUNT_COUNT_Pos)
#define TC_COUNT8_COUNT_COUNT(value) ((TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)))
#define TC_COUNT8_COUNT_MASK 0xFFu /**< \brief (TC_COUNT8_COUNT) MASK Register */
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */
#define TC_COUNT8_PER_RESETVALUE 0xFF /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */
#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
#define TC_COUNT8_PER_PER_Msk (0xFFu << TC_COUNT8_PER_PER_Pos)
#define TC_COUNT8_PER_PER(value) ((TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)))
#define TC_COUNT8_PER_MASK 0xFFu /**< \brief (TC_COUNT8_PER) MASK Register */
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */
#define TC_COUNT16_CC_RESETVALUE 0x0000 /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */
#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */
#define TC_COUNT16_CC_CC_Msk (0xFFFFu << TC_COUNT16_CC_CC_Pos)
#define TC_COUNT16_CC_CC(value) ((TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)))
#define TC_COUNT16_CC_MASK 0xFFFFu /**< \brief (TC_COUNT16_CC) MASK Register */
/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */
#define TC_COUNT32_CC_RESETVALUE 0x00000000 /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */
#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */
#define TC_COUNT32_CC_CC_Msk (0xFFFFFFFFu << TC_COUNT32_CC_CC_Pos)
#define TC_COUNT32_CC_CC(value) ((TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)))
#define TC_COUNT32_CC_MASK 0xFFFFFFFFu /**< \brief (TC_COUNT32_CC) MASK Register */
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */
#define TC_COUNT8_CC_RESETVALUE 0x00 /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */
#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */
#define TC_COUNT8_CC_CC_Msk (0xFFu << TC_COUNT8_CC_CC_Pos)
#define TC_COUNT8_CC_CC(value) ((TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)))
#define TC_COUNT8_CC_MASK 0xFFu /**< \brief (TC_COUNT8_CC) MASK Register */
/** \brief TC_COUNT8 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
RoReg8 Reserved3[0x3];
__IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
RoReg8 Reserved4[0x3];
__IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT16 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
RoReg8 Reserved3[0x6];
__IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT32 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
RoReg8 Reserved3[0x4];
__IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_TC_COMPONENT_ */

1608
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/tcc.h Normal file
View file

File diff suppressed because it is too large Load diff

1767
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/usb.h Normal file
View file

File diff suppressed because it is too large Load diff

303
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/component/wdt.h Normal file
View file

@ -0,0 +1,303 @@
/**
* \file
*
* \brief Component description for WDT
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_WDT_COMPONENT_
#define _SAMD21_WDT_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR WDT */
/* ========================================================================== */
/** \addtogroup SAMD21_WDT Watchdog Timer */
/*@{*/
#define WDT_U2203
#define REV_WDT 0x200
/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */
#define WDT_CTRL_RESETVALUE 0x00 /**< \brief (WDT_CTRL reset_value) Control */
#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */
#define WDT_CTRL_ENABLE (0x1u << WDT_CTRL_ENABLE_Pos)
#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
#define WDT_CTRL_WEN (0x1u << WDT_CTRL_WEN_Pos)
#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */
#define WDT_CTRL_ALWAYSON (0x1u << WDT_CTRL_ALWAYSON_Pos)
#define WDT_CTRL_MASK 0x86u /**< \brief (WDT_CTRL) MASK Register */
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
#define WDT_CONFIG_RESETVALUE 0xBB /**< \brief (WDT_CONFIG reset_value) Configuration */
#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
#define WDT_CONFIG_PER_Msk (0xFu << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER(value) ((WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos)))
#define WDT_CONFIG_PER_0_Val 0x0u /**< \brief (WDT_CONFIG) 8 clock cycles */
#define WDT_CONFIG_PER_1_Val 0x1u /**< \brief (WDT_CONFIG) 16 clock cycles */
#define WDT_CONFIG_PER_2_Val 0x2u /**< \brief (WDT_CONFIG) 32 clock cycles */
#define WDT_CONFIG_PER_3_Val 0x3u /**< \brief (WDT_CONFIG) 64 clock cycles */
#define WDT_CONFIG_PER_4_Val 0x4u /**< \brief (WDT_CONFIG) 128 clock cycles */
#define WDT_CONFIG_PER_5_Val 0x5u /**< \brief (WDT_CONFIG) 256 clock cycles */
#define WDT_CONFIG_PER_6_Val 0x6u /**< \brief (WDT_CONFIG) 512 clock cycles */
#define WDT_CONFIG_PER_7_Val 0x7u /**< \brief (WDT_CONFIG) 1024 clock cycles */
#define WDT_CONFIG_PER_8_Val 0x8u /**< \brief (WDT_CONFIG) 2048 clock cycles */
#define WDT_CONFIG_PER_9_Val 0x9u /**< \brief (WDT_CONFIG) 4096 clock cycles */
#define WDT_CONFIG_PER_10_Val 0xAu /**< \brief (WDT_CONFIG) 8192 clock cycles */
#define WDT_CONFIG_PER_11_Val 0xBu /**< \brief (WDT_CONFIG) 16384 clock cycles */
#define WDT_CONFIG_PER_0 (WDT_CONFIG_PER_0_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_1 (WDT_CONFIG_PER_1_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_2 (WDT_CONFIG_PER_2_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_3 (WDT_CONFIG_PER_3_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_4 (WDT_CONFIG_PER_4_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_5 (WDT_CONFIG_PER_5_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_6 (WDT_CONFIG_PER_6_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_7 (WDT_CONFIG_PER_7_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_9 (WDT_CONFIG_PER_9_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_10 (WDT_CONFIG_PER_10_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_11 (WDT_CONFIG_PER_11_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
#define WDT_CONFIG_WINDOW_Msk (0xFu << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW(value) ((WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos)))
#define WDT_CONFIG_WINDOW_0_Val 0x0u /**< \brief (WDT_CONFIG) 8 clock cycles */
#define WDT_CONFIG_WINDOW_1_Val 0x1u /**< \brief (WDT_CONFIG) 16 clock cycles */
#define WDT_CONFIG_WINDOW_2_Val 0x2u /**< \brief (WDT_CONFIG) 32 clock cycles */
#define WDT_CONFIG_WINDOW_3_Val 0x3u /**< \brief (WDT_CONFIG) 64 clock cycles */
#define WDT_CONFIG_WINDOW_4_Val 0x4u /**< \brief (WDT_CONFIG) 128 clock cycles */
#define WDT_CONFIG_WINDOW_5_Val 0x5u /**< \brief (WDT_CONFIG) 256 clock cycles */
#define WDT_CONFIG_WINDOW_6_Val 0x6u /**< \brief (WDT_CONFIG) 512 clock cycles */
#define WDT_CONFIG_WINDOW_7_Val 0x7u /**< \brief (WDT_CONFIG) 1024 clock cycles */
#define WDT_CONFIG_WINDOW_8_Val 0x8u /**< \brief (WDT_CONFIG) 2048 clock cycles */
#define WDT_CONFIG_WINDOW_9_Val 0x9u /**< \brief (WDT_CONFIG) 4096 clock cycles */
#define WDT_CONFIG_WINDOW_10_Val 0xAu /**< \brief (WDT_CONFIG) 8192 clock cycles */
#define WDT_CONFIG_WINDOW_11_Val 0xBu /**< \brief (WDT_CONFIG) 16384 clock cycles */
#define WDT_CONFIG_WINDOW_0 (WDT_CONFIG_WINDOW_0_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_1 (WDT_CONFIG_WINDOW_1_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_2 (WDT_CONFIG_WINDOW_2_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_3 (WDT_CONFIG_WINDOW_3_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_4 (WDT_CONFIG_WINDOW_4_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_5 (WDT_CONFIG_WINDOW_5_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_6 (WDT_CONFIG_WINDOW_6_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_7 (WDT_CONFIG_WINDOW_7_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_9 (WDT_CONFIG_WINDOW_9_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_10 (WDT_CONFIG_WINDOW_10_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_11 (WDT_CONFIG_WINDOW_11_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_MASK 0xFFu /**< \brief (WDT_CONFIG) MASK Register */
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_EWCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
#define WDT_EWCTRL_RESETVALUE 0x0B /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
#define WDT_EWCTRL_EWOFFSET_Msk (0xFu << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET(value) ((WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos)))
#define WDT_EWCTRL_EWOFFSET_0_Val 0x0u /**< \brief (WDT_EWCTRL) 8 clock cycles */
#define WDT_EWCTRL_EWOFFSET_1_Val 0x1u /**< \brief (WDT_EWCTRL) 16 clock cycles */
#define WDT_EWCTRL_EWOFFSET_2_Val 0x2u /**< \brief (WDT_EWCTRL) 32 clock cycles */
#define WDT_EWCTRL_EWOFFSET_3_Val 0x3u /**< \brief (WDT_EWCTRL) 64 clock cycles */
#define WDT_EWCTRL_EWOFFSET_4_Val 0x4u /**< \brief (WDT_EWCTRL) 128 clock cycles */
#define WDT_EWCTRL_EWOFFSET_5_Val 0x5u /**< \brief (WDT_EWCTRL) 256 clock cycles */
#define WDT_EWCTRL_EWOFFSET_6_Val 0x6u /**< \brief (WDT_EWCTRL) 512 clock cycles */
#define WDT_EWCTRL_EWOFFSET_7_Val 0x7u /**< \brief (WDT_EWCTRL) 1024 clock cycles */
#define WDT_EWCTRL_EWOFFSET_8_Val 0x8u /**< \brief (WDT_EWCTRL) 2048 clock cycles */
#define WDT_EWCTRL_EWOFFSET_9_Val 0x9u /**< \brief (WDT_EWCTRL) 4096 clock cycles */
#define WDT_EWCTRL_EWOFFSET_10_Val 0xAu /**< \brief (WDT_EWCTRL) 8192 clock cycles */
#define WDT_EWCTRL_EWOFFSET_11_Val 0xBu /**< \brief (WDT_EWCTRL) 16384 clock cycles */
#define WDT_EWCTRL_EWOFFSET_0 (WDT_EWCTRL_EWOFFSET_0_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_1 (WDT_EWCTRL_EWOFFSET_1_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_2 (WDT_EWCTRL_EWOFFSET_2_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_3 (WDT_EWCTRL_EWOFFSET_3_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_4 (WDT_EWCTRL_EWOFFSET_4_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_5 (WDT_EWCTRL_EWOFFSET_5_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_6 (WDT_EWCTRL_EWOFFSET_6_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_7 (WDT_EWCTRL_EWOFFSET_7_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_9 (WDT_EWCTRL_EWOFFSET_9_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_10 (WDT_EWCTRL_EWOFFSET_10_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_11 (WDT_EWCTRL_EWOFFSET_11_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_MASK 0x0Fu /**< \brief (WDT_EWCTRL) MASK Register */
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
#define WDT_INTENCLR_RESETVALUE 0x00 /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
#define WDT_INTENCLR_EW (0x1u << WDT_INTENCLR_EW_Pos)
#define WDT_INTENCLR_MASK 0x01u /**< \brief (WDT_INTENCLR) MASK Register */
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
#define WDT_INTENSET_RESETVALUE 0x00 /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
#define WDT_INTENSET_EW (0x1u << WDT_INTENSET_EW_Pos)
#define WDT_INTENSET_MASK 0x01u /**< \brief (WDT_INTENSET) MASK Register */
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
#define WDT_INTFLAG_RESETVALUE 0x00 /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
#define WDT_INTFLAG_EW (0x1u << WDT_INTFLAG_EW_Pos)
#define WDT_INTFLAG_MASK 0x01u /**< \brief (WDT_INTFLAG) MASK Register */
/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */
#define WDT_STATUS_RESETVALUE 0x00 /**< \brief (WDT_STATUS reset_value) Status */
#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */
#define WDT_STATUS_SYNCBUSY (0x1u << WDT_STATUS_SYNCBUSY_Pos)
#define WDT_STATUS_MASK 0x80u /**< \brief (WDT_STATUS) MASK Register */
/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CLEAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */
#define WDT_CLEAR_RESETVALUE 0x00 /**< \brief (WDT_CLEAR reset_value) Clear */
#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
#define WDT_CLEAR_CLEAR_Msk (0xFFu << WDT_CLEAR_CLEAR_Pos)
#define WDT_CLEAR_CLEAR(value) ((WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos)))
#define WDT_CLEAR_CLEAR_KEY_Val 0xA5u /**< \brief (WDT_CLEAR) Clear Key */
#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
#define WDT_CLEAR_MASK 0xFFu /**< \brief (WDT_CLEAR) MASK Register */
/** \brief WDT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
__IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
RoReg8 Reserved1[0x1];
__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
} Wdt;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMD21_WDT_COMPONENT_ */

87
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/ac.h Normal file
View file

@ -0,0 +1,87 @@
/**
* \file
*
* \brief Instance description for AC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_AC_INSTANCE_
#define _SAMD21_AC_INSTANCE_
/* ========== Register definition for AC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AC_CTRLA (0x42004400U) /**< \brief (AC) Control A */
#define REG_AC_CTRLB (0x42004401U) /**< \brief (AC) Control B */
#define REG_AC_EVCTRL (0x42004402U) /**< \brief (AC) Event Control */
#define REG_AC_INTENCLR (0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
#define REG_AC_INTENSET (0x42004405U) /**< \brief (AC) Interrupt Enable Set */
#define REG_AC_INTFLAG (0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
#define REG_AC_STATUSA (0x42004408U) /**< \brief (AC) Status A */
#define REG_AC_STATUSB (0x42004409U) /**< \brief (AC) Status B */
#define REG_AC_STATUSC (0x4200440AU) /**< \brief (AC) Status C */
#define REG_AC_WINCTRL (0x4200440CU) /**< \brief (AC) Window Control */
#define REG_AC_COMPCTRL0 (0x42004410U) /**< \brief (AC) Comparator Control 0 */
#define REG_AC_COMPCTRL1 (0x42004414U) /**< \brief (AC) Comparator Control 1 */
#define REG_AC_SCALER0 (0x42004420U) /**< \brief (AC) Scaler 0 */
#define REG_AC_SCALER1 (0x42004421U) /**< \brief (AC) Scaler 1 */
#else
#define REG_AC_CTRLA (*(RwReg8 *)0x42004400U) /**< \brief (AC) Control A */
#define REG_AC_CTRLB (*(WoReg8 *)0x42004401U) /**< \brief (AC) Control B */
#define REG_AC_EVCTRL (*(RwReg16*)0x42004402U) /**< \brief (AC) Event Control */
#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404U) /**< \brief (AC) Interrupt Enable Clear */
#define REG_AC_INTENSET (*(RwReg8 *)0x42004405U) /**< \brief (AC) Interrupt Enable Set */
#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406U) /**< \brief (AC) Interrupt Flag Status and Clear */
#define REG_AC_STATUSA (*(RoReg8 *)0x42004408U) /**< \brief (AC) Status A */
#define REG_AC_STATUSB (*(RoReg8 *)0x42004409U) /**< \brief (AC) Status B */
#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AU) /**< \brief (AC) Status C */
#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CU) /**< \brief (AC) Window Control */
#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410U) /**< \brief (AC) Comparator Control 0 */
#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414U) /**< \brief (AC) Comparator Control 1 */
#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420U) /**< \brief (AC) Scaler 0 */
#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421U) /**< \brief (AC) Scaler 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for AC peripheral ========== */
#define AC_CMP_NUM 2
#define AC_GCLK_ID_ANA 32
#define AC_GCLK_ID_DIG 31
#define AC_NUM_CMP AC_CMP_NUM
#define AC_PAIRS 1
#endif /* _SAMD21_AC_INSTANCE_ */

99
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/adc.h Normal file
View file

@ -0,0 +1,99 @@
/**
* \file
*
* \brief Instance description for ADC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_ADC_INSTANCE_
#define _SAMD21_ADC_INSTANCE_
/* ========== Register definition for ADC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ADC_CTRLA (0x42004000U) /**< \brief (ADC) Control A */
#define REG_ADC_REFCTRL (0x42004001U) /**< \brief (ADC) Reference Control */
#define REG_ADC_AVGCTRL (0x42004002U) /**< \brief (ADC) Average Control */
#define REG_ADC_SAMPCTRL (0x42004003U) /**< \brief (ADC) Sampling Time Control */
#define REG_ADC_CTRLB (0x42004004U) /**< \brief (ADC) Control B */
#define REG_ADC_WINCTRL (0x42004008U) /**< \brief (ADC) Window Monitor Control */
#define REG_ADC_SWTRIG (0x4200400CU) /**< \brief (ADC) Software Trigger */
#define REG_ADC_INPUTCTRL (0x42004010U) /**< \brief (ADC) Input Control */
#define REG_ADC_EVCTRL (0x42004014U) /**< \brief (ADC) Event Control */
#define REG_ADC_INTENCLR (0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
#define REG_ADC_INTENSET (0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
#define REG_ADC_INTFLAG (0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
#define REG_ADC_STATUS (0x42004019U) /**< \brief (ADC) Status */
#define REG_ADC_RESULT (0x4200401AU) /**< \brief (ADC) Result */
#define REG_ADC_WINLT (0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
#define REG_ADC_WINUT (0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
#define REG_ADC_GAINCORR (0x42004024U) /**< \brief (ADC) Gain Correction */
#define REG_ADC_OFFSETCORR (0x42004026U) /**< \brief (ADC) Offset Correction */
#define REG_ADC_CALIB (0x42004028U) /**< \brief (ADC) Calibration */
#define REG_ADC_DBGCTRL (0x4200402AU) /**< \brief (ADC) Debug Control */
#else
#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000U) /**< \brief (ADC) Control A */
#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001U) /**< \brief (ADC) Reference Control */
#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002U) /**< \brief (ADC) Average Control */
#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003U) /**< \brief (ADC) Sampling Time Control */
#define REG_ADC_CTRLB (*(RwReg16*)0x42004004U) /**< \brief (ADC) Control B */
#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008U) /**< \brief (ADC) Window Monitor Control */
#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CU) /**< \brief (ADC) Software Trigger */
#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010U) /**< \brief (ADC) Input Control */
#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014U) /**< \brief (ADC) Event Control */
#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016U) /**< \brief (ADC) Interrupt Enable Clear */
#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017U) /**< \brief (ADC) Interrupt Enable Set */
#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018U) /**< \brief (ADC) Interrupt Flag Status and Clear */
#define REG_ADC_STATUS (*(RoReg8 *)0x42004019U) /**< \brief (ADC) Status */
#define REG_ADC_RESULT (*(RoReg16*)0x4200401AU) /**< \brief (ADC) Result */
#define REG_ADC_WINLT (*(RwReg16*)0x4200401CU) /**< \brief (ADC) Window Monitor Lower Threshold */
#define REG_ADC_WINUT (*(RwReg16*)0x42004020U) /**< \brief (ADC) Window Monitor Upper Threshold */
#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024U) /**< \brief (ADC) Gain Correction */
#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026U) /**< \brief (ADC) Offset Correction */
#define REG_ADC_CALIB (*(RwReg16*)0x42004028U) /**< \brief (ADC) Calibration */
#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AU) /**< \brief (ADC) Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for ADC peripheral ========== */
#define ADC_DMAC_ID_RESRDY 39
#define ADC_EXTCHANNEL_MSB 19
#define ADC_GCLK_ID 30
#define ADC_RESULT_BITS 16
#define ADC_RESULT_MSB (ADC_RESULT_BITS-1)
#endif /* _SAMD21_ADC_INSTANCE_ */

74
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/dac.h Normal file
View file

@ -0,0 +1,74 @@
/**
* \file
*
* \brief Instance description for DAC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_DAC_INSTANCE_
#define _SAMD21_DAC_INSTANCE_
/* ========== Register definition for DAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DAC_CTRLA (0x42004800U) /**< \brief (DAC) Control A */
#define REG_DAC_CTRLB (0x42004801U) /**< \brief (DAC) Control B */
#define REG_DAC_EVCTRL (0x42004802U) /**< \brief (DAC) Event Control */
#define REG_DAC_INTENCLR (0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
#define REG_DAC_INTENSET (0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
#define REG_DAC_INTFLAG (0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
#define REG_DAC_STATUS (0x42004807U) /**< \brief (DAC) Status */
#define REG_DAC_DATA (0x42004808U) /**< \brief (DAC) Data */
#define REG_DAC_DATABUF (0x4200480CU) /**< \brief (DAC) Data Buffer */
#else
#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800U) /**< \brief (DAC) Control A */
#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801U) /**< \brief (DAC) Control B */
#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802U) /**< \brief (DAC) Event Control */
#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804U) /**< \brief (DAC) Interrupt Enable Clear */
#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805U) /**< \brief (DAC) Interrupt Enable Set */
#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806U) /**< \brief (DAC) Interrupt Flag Status and Clear */
#define REG_DAC_STATUS (*(RoReg8 *)0x42004807U) /**< \brief (DAC) Status */
#define REG_DAC_DATA (*(RwReg16*)0x42004808U) /**< \brief (DAC) Data */
#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CU) /**< \brief (DAC) Data Buffer */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DAC peripheral ========== */
#define DAC_DMAC_ID_EMPTY 40
#define DAC_GCLK_ID 33
#endif /* _SAMD21_DAC_INSTANCE_ */

107
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/dmac.h Normal file
View file

@ -0,0 +1,107 @@
/**
* \file
*
* \brief Instance description for DMAC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_DMAC_INSTANCE_
#define _SAMD21_DMAC_INSTANCE_
/* ========== Register definition for DMAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */
#define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */
#define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */
#define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */
#define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */
#define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */
#define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */
#define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */
#define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */
#define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */
#define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */
#define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */
#define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
#define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
#define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
#define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */
#define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */
#define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */
#define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */
#else
#define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */
#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */
#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */
#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */
#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */
#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */
#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */
#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */
#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */
#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */
#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */
#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */
#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */
#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */
#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */
#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DMAC peripheral ========== */
#define DMAC_CH_BITS len(bin(DMAC_CH_NUM - 1))-2
#define DMAC_CH_NUM 12
#define DMAC_CLK_AHB_ID 5
#define DMAC_EVIN_NUM 4
#define DMAC_EVOUT_NUM 4
#define DMAC_LVL_BITS len(bin(DMAC_LVL_NUM - 1))-2
#define DMAC_LVL_NUM 4
#define DMAC_TRIG_BITS len(bin(DMAC_TRIG_NUM - 1))-2
#define DMAC_TRIG_NUM 45
#endif /* _SAMD21_DMAC_INSTANCE_ */

99
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/dsu.h Normal file
View file

@ -0,0 +1,99 @@
/**
* \file
*
* \brief Instance description for DSU
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_DSU_INSTANCE_
#define _SAMD21_DSU_INSTANCE_
/* ========== Register definition for DSU peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */
#define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */
#define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */
#define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */
#define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */
#define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */
#define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
#define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */
#define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
#define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
#define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
#define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
#define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
#define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
#define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
#define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
#define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
#define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
#define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
#define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
#else
#define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */
#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */
#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */
#define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */
#define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */
#define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */
#define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */
#define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */
#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */
#define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */
#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */
#define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */
#define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */
#define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */
#define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */
#define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */
#define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */
#define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */
#define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */
#define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DSU peripheral ========== */
#define DSU_CLK_HSB_ID 3
#endif /* _SAMD21_DSU_INSTANCE_ */

78
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/eic.h Normal file
View file

@ -0,0 +1,78 @@
/**
* \file
*
* \brief Instance description for EIC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_EIC_INSTANCE_
#define _SAMD21_EIC_INSTANCE_
/* ========== Register definition for EIC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EIC_CTRL (0x40001800U) /**< \brief (EIC) Control */
#define REG_EIC_STATUS (0x40001801U) /**< \brief (EIC) Status */
#define REG_EIC_NMICTRL (0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
#define REG_EIC_NMIFLAG (0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
#define REG_EIC_EVCTRL (0x40001804U) /**< \brief (EIC) Event Control */
#define REG_EIC_INTENCLR (0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
#define REG_EIC_INTENSET (0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
#define REG_EIC_INTFLAG (0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
#define REG_EIC_WAKEUP (0x40001814U) /**< \brief (EIC) Wake-Up Enable */
#define REG_EIC_CONFIG0 (0x40001818U) /**< \brief (EIC) Configuration 0 */
#define REG_EIC_CONFIG1 (0x4000181CU) /**< \brief (EIC) Configuration 1 */
#else
#define REG_EIC_CTRL (*(RwReg8 *)0x40001800U) /**< \brief (EIC) Control */
#define REG_EIC_STATUS (*(RoReg8 *)0x40001801U) /**< \brief (EIC) Status */
#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802U) /**< \brief (EIC) Non-Maskable Interrupt Control */
#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803U) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
#define REG_EIC_EVCTRL (*(RwReg *)0x40001804U) /**< \brief (EIC) Event Control */
#define REG_EIC_INTENCLR (*(RwReg *)0x40001808U) /**< \brief (EIC) Interrupt Enable Clear */
#define REG_EIC_INTENSET (*(RwReg *)0x4000180CU) /**< \brief (EIC) Interrupt Enable Set */
#define REG_EIC_INTFLAG (*(RwReg *)0x40001810U) /**< \brief (EIC) Interrupt Flag Status and Clear */
#define REG_EIC_WAKEUP (*(RwReg *)0x40001814U) /**< \brief (EIC) Wake-Up Enable */
#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818U) /**< \brief (EIC) Configuration 0 */
#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CU) /**< \brief (EIC) Configuration 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for EIC peripheral ========== */
#define EIC_CONFIG_NUM ((EIC_EXTINT_NUM+7)/8)
#define EIC_GCLK_ID 5
#endif /* _SAMD21_EIC_INSTANCE_ */

197
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/evsys.h Normal file
View file

@ -0,0 +1,197 @@
/**
* \file
*
* \brief Instance description for EVSYS
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_EVSYS_INSTANCE_
#define _SAMD21_EVSYS_INSTANCE_
/* ========== Register definition for EVSYS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EVSYS_CTRL (0x42000400U) /**< \brief (EVSYS) Control */
#define REG_EVSYS_CHANNEL (0x42000404U) /**< \brief (EVSYS) Channel */
#define REG_EVSYS_USER (0x42000408U) /**< \brief (EVSYS) User Multiplexer */
#define REG_EVSYS_CHSTATUS (0x4200040CU) /**< \brief (EVSYS) Channel Status */
#define REG_EVSYS_INTENCLR (0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
#define REG_EVSYS_INTENSET (0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
#define REG_EVSYS_INTFLAG (0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
#else
#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400U) /**< \brief (EVSYS) Control */
#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404U) /**< \brief (EVSYS) Channel */
#define REG_EVSYS_USER (*(RwReg16*)0x42000408U) /**< \brief (EVSYS) User Multiplexer */
#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CU) /**< \brief (EVSYS) Channel Status */
#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410U) /**< \brief (EVSYS) Interrupt Enable Clear */
#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414U) /**< \brief (EVSYS) Interrupt Enable Set */
#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418U) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for EVSYS peripheral ========== */
#define EVSYS_CHANNELS 12
#define EVSYS_CHANNELS_BITS (len(bin(EVSYS_CHANNELS-1))-2)
#define EVSYS_CHANNELS_MSB (EVSYS_CHANNELS-1)
#define EVSYS_EXTEVT_NUM 0
#define EVSYS_GCLK_ID_0 7
#define EVSYS_GCLK_ID_1 8
#define EVSYS_GCLK_ID_2 9
#define EVSYS_GCLK_ID_3 10
#define EVSYS_GCLK_ID_4 11
#define EVSYS_GCLK_ID_5 12
#define EVSYS_GCLK_ID_6 13
#define EVSYS_GCLK_ID_7 14
#define EVSYS_GCLK_ID_8 15
#define EVSYS_GCLK_ID_9 16
#define EVSYS_GCLK_ID_10 17
#define EVSYS_GCLK_ID_11 18
#define EVSYS_GCLK_ID_LSB 7
#define EVSYS_GCLK_ID_MSB 18
#define EVSYS_GCLK_ID_SIZE 12
#define EVSYS_GENERATORS 73
#define EVSYS_GENERATORS_BITS (len(bin(EVSYS_GENERATORS-1))-2)
#define EVSYS_USERS 29
#define EVSYS_USERS_BITS (len(bin(EVSYS_USERS-1))-2)
// GENERATORS
#define EVSYS_ID_GEN_RTC_CMP_0 1
#define EVSYS_ID_GEN_RTC_CMP_1 2
#define EVSYS_ID_GEN_RTC_OVF 3
#define EVSYS_ID_GEN_RTC_PER_0 4
#define EVSYS_ID_GEN_RTC_PER_1 5
#define EVSYS_ID_GEN_RTC_PER_2 6
#define EVSYS_ID_GEN_RTC_PER_3 7
#define EVSYS_ID_GEN_RTC_PER_4 8
#define EVSYS_ID_GEN_RTC_PER_5 9
#define EVSYS_ID_GEN_RTC_PER_6 10
#define EVSYS_ID_GEN_RTC_PER_7 11
#define EVSYS_ID_GEN_EIC_EXTINT_0 12
#define EVSYS_ID_GEN_EIC_EXTINT_1 13
#define EVSYS_ID_GEN_EIC_EXTINT_2 14
#define EVSYS_ID_GEN_EIC_EXTINT_3 15
#define EVSYS_ID_GEN_EIC_EXTINT_4 16
#define EVSYS_ID_GEN_EIC_EXTINT_5 17
#define EVSYS_ID_GEN_EIC_EXTINT_6 18
#define EVSYS_ID_GEN_EIC_EXTINT_7 19
#define EVSYS_ID_GEN_EIC_EXTINT_8 20
#define EVSYS_ID_GEN_EIC_EXTINT_9 21
#define EVSYS_ID_GEN_EIC_EXTINT_10 22
#define EVSYS_ID_GEN_EIC_EXTINT_11 23
#define EVSYS_ID_GEN_EIC_EXTINT_12 24
#define EVSYS_ID_GEN_EIC_EXTINT_13 25
#define EVSYS_ID_GEN_EIC_EXTINT_14 26
#define EVSYS_ID_GEN_EIC_EXTINT_15 27
#define EVSYS_ID_GEN_EIC_EXTINT_16 28
#define EVSYS_ID_GEN_EIC_EXTINT_17 29
#define EVSYS_ID_GEN_DMAC_CH_0 30
#define EVSYS_ID_GEN_DMAC_CH_1 31
#define EVSYS_ID_GEN_DMAC_CH_2 32
#define EVSYS_ID_GEN_DMAC_CH_3 33
#define EVSYS_ID_GEN_TCC0_OVF 34
#define EVSYS_ID_GEN_TCC0_TRG 35
#define EVSYS_ID_GEN_TCC0_CNT 36
#define EVSYS_ID_GEN_TCC0_MCX_0 37
#define EVSYS_ID_GEN_TCC0_MCX_1 38
#define EVSYS_ID_GEN_TCC0_MCX_2 39
#define EVSYS_ID_GEN_TCC0_MCX_3 40
#define EVSYS_ID_GEN_TCC1_OVF 41
#define EVSYS_ID_GEN_TCC1_TRG 42
#define EVSYS_ID_GEN_TCC1_CNT 43
#define EVSYS_ID_GEN_TCC1_MCX_0 44
#define EVSYS_ID_GEN_TCC1_MCX_1 45
#define EVSYS_ID_GEN_TCC2_OVF 46
#define EVSYS_ID_GEN_TCC2_TRG 47
#define EVSYS_ID_GEN_TCC2_CNT 48
#define EVSYS_ID_GEN_TCC2_MCX_0 49
#define EVSYS_ID_GEN_TCC2_MCX_1 50
#define EVSYS_ID_GEN_TC3_OVF 51
#define EVSYS_ID_GEN_TC3_MCX_0 52
#define EVSYS_ID_GEN_TC3_MCX_1 53
#define EVSYS_ID_GEN_TC4_OVF 54
#define EVSYS_ID_GEN_TC4_MCX_0 55
#define EVSYS_ID_GEN_TC4_MCX_1 56
#define EVSYS_ID_GEN_TC5_OVF 57
#define EVSYS_ID_GEN_TC5_MCX_0 58
#define EVSYS_ID_GEN_TC5_MCX_1 59
#define EVSYS_ID_GEN_TC6_OVF 60
#define EVSYS_ID_GEN_TC6_MCX_0 61
#define EVSYS_ID_GEN_TC6_MCX_1 62
#define EVSYS_ID_GEN_TC7_OVF 63
#define EVSYS_ID_GEN_TC7_MCX_0 64
#define EVSYS_ID_GEN_TC7_MCX_1 65
#define EVSYS_ID_GEN_ADC_RESRDY 66
#define EVSYS_ID_GEN_ADC_WINMON 67
#define EVSYS_ID_GEN_AC_COMP_0 68
#define EVSYS_ID_GEN_AC_COMP_1 69
#define EVSYS_ID_GEN_AC_WIN_0 70
#define EVSYS_ID_GEN_DAC_EMPTY 71
#define EVSYS_ID_GEN_PTC_EOC 72
#define EVSYS_ID_GEN_PTC_WCOMP 73
// USERS
#define EVSYS_ID_USER_DMAC_CH_0 0
#define EVSYS_ID_USER_DMAC_CH_1 1
#define EVSYS_ID_USER_DMAC_CH_2 2
#define EVSYS_ID_USER_DMAC_CH_3 3
#define EVSYS_ID_USER_TCC0_EV_0 4
#define EVSYS_ID_USER_TCC0_EV_1 5
#define EVSYS_ID_USER_TCC0_MC_0 6
#define EVSYS_ID_USER_TCC0_MC_1 7
#define EVSYS_ID_USER_TCC0_MC_2 8
#define EVSYS_ID_USER_TCC0_MC_3 9
#define EVSYS_ID_USER_TCC1_EV_0 10
#define EVSYS_ID_USER_TCC1_EV_1 11
#define EVSYS_ID_USER_TCC1_MC_0 12
#define EVSYS_ID_USER_TCC1_MC_1 13
#define EVSYS_ID_USER_TCC2_EV_0 14
#define EVSYS_ID_USER_TCC2_EV_1 15
#define EVSYS_ID_USER_TCC2_MC_0 16
#define EVSYS_ID_USER_TCC2_MC_1 17
#define EVSYS_ID_USER_TC3_EVU 18
#define EVSYS_ID_USER_TC4_EVU 19
#define EVSYS_ID_USER_TC5_EVU 20
#define EVSYS_ID_USER_TC6_EVU 21
#define EVSYS_ID_USER_TC7_EVU 22
#define EVSYS_ID_USER_ADC_START 23
#define EVSYS_ID_USER_ADC_SYNC 24
#define EVSYS_ID_USER_AC_SOC_0 25
#define EVSYS_ID_USER_AC_SOC_1 26
#define EVSYS_ID_USER_DAC_START 27
#define EVSYS_ID_USER_PTC_STCONV 28
#endif /* _SAMD21_EVSYS_INSTANCE_ */

79
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/gclk.h Normal file
View file

@ -0,0 +1,79 @@
/**
* \file
*
* \brief Instance description for GCLK
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_GCLK_INSTANCE_
#define _SAMD21_GCLK_INSTANCE_
/* ========== Register definition for GCLK peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_GCLK_CTRL (0x40000C00U) /**< \brief (GCLK) Control */
#define REG_GCLK_STATUS (0x40000C01U) /**< \brief (GCLK) Status */
#define REG_GCLK_CLKCTRL (0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
#define REG_GCLK_GENCTRL (0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
#define REG_GCLK_GENDIV (0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
#else
#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00U) /**< \brief (GCLK) Control */
#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01U) /**< \brief (GCLK) Status */
#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02U) /**< \brief (GCLK) Generic Clock Control */
#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04U) /**< \brief (GCLK) Generic Clock Generator Control */
#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08U) /**< \brief (GCLK) Generic Clock Generator Division */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_NUM 9
#define GCLK_GEN_NUM_MSB (GCLK_GEN_NUM-1)
#define GCLK_GEN_SOURCE_NUM_MSB (GCLK_SOURCE_NUM-1)
#define GCLK_NUM 37
#define GCLK_SOURCE_DFLL48M 7
#define GCLK_SOURCE_FDPLL 8
#define GCLK_SOURCE_GCLKGEN1 2
#define GCLK_SOURCE_GCLKIN 1
#define GCLK_SOURCE_NUM 9
#define GCLK_SOURCE_OSCULP32K 3
#define GCLK_SOURCE_OSC8M 6
#define GCLK_SOURCE_OSC32K 4
#define GCLK_SOURCE_XOSC 0
#define GCLK_SOURCE_XOSC32K 5
#endif /* _SAMD21_GCLK_INSTANCE_ */

94
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/i2s.h Normal file
View file

@ -0,0 +1,94 @@
/**
* \file
*
* \brief Instance description for I2S
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_I2S_INSTANCE_
#define _SAMD21_I2S_INSTANCE_
/* ========== Register definition for I2S peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_I2S_CTRLA (0x42005000U) /**< \brief (I2S) Control A */
#define REG_I2S_CLKCTRL0 (0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
#define REG_I2S_CLKCTRL1 (0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
#define REG_I2S_INTENCLR (0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
#define REG_I2S_INTENSET (0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
#define REG_I2S_INTFLAG (0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
#define REG_I2S_SYNCBUSY (0x42005018U) /**< \brief (I2S) Synchronization Status */
#define REG_I2S_SERCTRL0 (0x42005020U) /**< \brief (I2S) Serializer 0 Control */
#define REG_I2S_SERCTRL1 (0x42005024U) /**< \brief (I2S) Serializer 1 Control */
#define REG_I2S_DATA0 (0x42005030U) /**< \brief (I2S) Data 0 */
#define REG_I2S_DATA1 (0x42005034U) /**< \brief (I2S) Data 1 */
#else
#define REG_I2S_CTRLA (*(RwReg8 *)0x42005000U) /**< \brief (I2S) Control A */
#define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004U) /**< \brief (I2S) Clock Unit 0 Control */
#define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008U) /**< \brief (I2S) Clock Unit 1 Control */
#define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CU) /**< \brief (I2S) Interrupt Enable Clear */
#define REG_I2S_INTENSET (*(RwReg16*)0x42005010U) /**< \brief (I2S) Interrupt Enable Set */
#define REG_I2S_INTFLAG (*(RwReg16*)0x42005014U) /**< \brief (I2S) Interrupt Flag Status and Clear */
#define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018U) /**< \brief (I2S) Synchronization Status */
#define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020U) /**< \brief (I2S) Serializer 0 Control */
#define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024U) /**< \brief (I2S) Serializer 1 Control */
#define REG_I2S_DATA0 (*(RwReg *)0x42005030U) /**< \brief (I2S) Data 0 */
#define REG_I2S_DATA1 (*(RwReg *)0x42005034U) /**< \brief (I2S) Data 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for I2S peripheral ========== */
#define I2S_CLK_NUM 2
#define I2S_DMAC_ID_RX_0 41
#define I2S_DMAC_ID_RX_1 42
#define I2S_DMAC_ID_RX_LSB 41
#define I2S_DMAC_ID_RX_MSB 42
#define I2S_DMAC_ID_RX_SIZE 2
#define I2S_DMAC_ID_TX_0 43
#define I2S_DMAC_ID_TX_1 44
#define I2S_DMAC_ID_TX_LSB 43
#define I2S_DMAC_ID_TX_MSB 44
#define I2S_DMAC_ID_TX_SIZE 2
#define I2S_GCLK_ID_0 35
#define I2S_GCLK_ID_1 36
#define I2S_GCLK_ID_LSB 35
#define I2S_GCLK_ID_MSB 36
#define I2S_GCLK_ID_SIZE 2
#define I2S_MAX_SLOTS 8
#define I2S_SER_NUM 2
#endif /* _SAMD21_I2S_INSTANCE_ */

103
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/mtb.h Normal file
View file

@ -0,0 +1,103 @@
/**
* \file
*
* \brief Instance description for MTB
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_MTB_INSTANCE_
#define _SAMD21_MTB_INSTANCE_
/* ========== Register definition for MTB peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */
#define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */
#define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */
#define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */
#define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
#define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
#define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
#define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
#define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
#define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
#define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
#define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
#define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */
#define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) CoreSight */
#define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) CoreSight */
#define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) CoreSight */
#define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) CoreSight */
#define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) CoreSight */
#else
#define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */
#define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */
#define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */
#define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */
#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
#define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */
#define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) CoreSight */
#define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) CoreSight */
#define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) CoreSight */
#define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) CoreSight */
#define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) CoreSight */
#define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) CoreSight */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMD21_MTB_INSTANCE_ */

92
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/nvmctrl.h Normal file
View file

@ -0,0 +1,92 @@
/**
* \file
*
* \brief Instance description for NVMCTRL
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_NVMCTRL_INSTANCE_
#define _SAMD21_NVMCTRL_INSTANCE_
/* ========== Register definition for NVMCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_NVMCTRL_CTRLA (0x41004000U) /**< \brief (NVMCTRL) Control A */
#define REG_NVMCTRL_CTRLB (0x41004004U) /**< \brief (NVMCTRL) Control B */
#define REG_NVMCTRL_PARAM (0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
#define REG_NVMCTRL_INTENCLR (0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
#define REG_NVMCTRL_INTENSET (0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
#define REG_NVMCTRL_INTFLAG (0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
#define REG_NVMCTRL_STATUS (0x41004018U) /**< \brief (NVMCTRL) Status */
#define REG_NVMCTRL_ADDR (0x4100401CU) /**< \brief (NVMCTRL) Address */
#define REG_NVMCTRL_LOCK (0x41004020U) /**< \brief (NVMCTRL) Lock Section */
#else
#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000U) /**< \brief (NVMCTRL) Control A */
#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004U) /**< \brief (NVMCTRL) Control B */
#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008U) /**< \brief (NVMCTRL) NVM Parameter */
#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CU) /**< \brief (NVMCTRL) Interrupt Enable Clear */
#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010U) /**< \brief (NVMCTRL) Interrupt Enable Set */
#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014U) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018U) /**< \brief (NVMCTRL) Status */
#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CU) /**< \brief (NVMCTRL) Address */
#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020U) /**< \brief (NVMCTRL) Lock Section */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for NVMCTRL peripheral ========== */
#define NVMCTRL_AUX0_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00004000)
#define NVMCTRL_AUX1_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00006000)
#define NVMCTRL_AUX2_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00008000)
#define NVMCTRL_AUX3_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x0000A000)
#define NVMCTRL_CLK_AHB_ID 4
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
#define NVMCTRL_FLASH_SIZE (NVMCTRL_PAGES*NVMCTRL_PAGE_SIZE)
#define NVMCTRL_LOCKBIT_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00002000)
#define NVMCTRL_PAGES 4096
#define NVMCTRL_PAGE_HW (NVMCTRL_PAGE_SIZE/2)
#define NVMCTRL_PAGE_SIZE (1<<NVMCTRL_PSZ_BITS)
#define NVMCTRL_PAGE_W (NVMCTRL_PAGE_SIZE/4)
#define NVMCTRL_PMSB 3
#define NVMCTRL_PSZ_BITS 6
#define NVMCTRL_ROW_PAGES 4
#define NVMCTRL_ROW_SIZE (NVMCTRL_PAGE_SIZE*NVMCTRL_ROW_PAGES)
#define NVMCTRL_TEMP_LOG_ADDRESS (NVMCTRL_USER_PAGE_ADDRESS + 0x00006030)
#define NVMCTRL_USER_PAGE_ADDRESS (FLASH_ADDR + NVMCTRL_USER_PAGE_OFFSET)
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
#endif /* _SAMD21_NVMCTRL_INSTANCE_ */

59
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac0.h Normal file
View file

@ -0,0 +1,59 @@
/**
* \file
*
* \brief Instance description for PAC0
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_PAC0_INSTANCE_
#define _SAMD21_PAC0_INSTANCE_
/* ========== Register definition for PAC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PAC0_WPCLR (0x40000000U) /**< \brief (PAC0) Write Protection Clear */
#define REG_PAC0_WPSET (0x40000004U) /**< \brief (PAC0) Write Protection Set */
#else
#define REG_PAC0_WPCLR (*(RwReg *)0x40000000U) /**< \brief (PAC0) Write Protection Clear */
#define REG_PAC0_WPSET (*(RwReg *)0x40000004U) /**< \brief (PAC0) Write Protection Set */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PAC0 peripheral ========== */
#define PAC0_WPROT_DEFAULT_VAL 0x00000000
#endif /* _SAMD21_PAC0_INSTANCE_ */

59
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac1.h Normal file
View file

@ -0,0 +1,59 @@
/**
* \file
*
* \brief Instance description for PAC1
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_PAC1_INSTANCE_
#define _SAMD21_PAC1_INSTANCE_
/* ========== Register definition for PAC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PAC1_WPCLR (0x41000000U) /**< \brief (PAC1) Write Protection Clear */
#define REG_PAC1_WPSET (0x41000004U) /**< \brief (PAC1) Write Protection Set */
#else
#define REG_PAC1_WPCLR (*(RwReg *)0x41000000U) /**< \brief (PAC1) Write Protection Clear */
#define REG_PAC1_WPSET (*(RwReg *)0x41000004U) /**< \brief (PAC1) Write Protection Set */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PAC1 peripheral ========== */
#define PAC1_WPROT_DEFAULT_VAL 0x00000000
#endif /* _SAMD21_PAC1_INSTANCE_ */

59
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/pac2.h Normal file
View file

@ -0,0 +1,59 @@
/**
* \file
*
* \brief Instance description for PAC2
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_PAC2_INSTANCE_
#define _SAMD21_PAC2_INSTANCE_
/* ========== Register definition for PAC2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PAC2_WPCLR (0x42000000U) /**< \brief (PAC2) Write Protection Clear */
#define REG_PAC2_WPSET (0x42000004U) /**< \brief (PAC2) Write Protection Set */
#else
#define REG_PAC2_WPCLR (*(RwReg *)0x42000000U) /**< \brief (PAC2) Write Protection Clear */
#define REG_PAC2_WPSET (*(RwReg *)0x42000004U) /**< \brief (PAC2) Write Protection Set */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PAC2 peripheral ========== */
#define PAC2_WPROT_DEFAULT_VAL 0x00800000
#endif /* _SAMD21_PAC2_INSTANCE_ */

87
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/pm.h Normal file
View file

@ -0,0 +1,87 @@
/**
* \file
*
* \brief Instance description for PM
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_PM_INSTANCE_
#define _SAMD21_PM_INSTANCE_
/* ========== Register definition for PM peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PM_CTRL (0x40000400U) /**< \brief (PM) Control */
#define REG_PM_SLEEP (0x40000401U) /**< \brief (PM) Sleep Mode */
#define REG_PM_CPUSEL (0x40000408U) /**< \brief (PM) CPU Clock Select */
#define REG_PM_APBASEL (0x40000409U) /**< \brief (PM) APBA Clock Select */
#define REG_PM_APBBSEL (0x4000040AU) /**< \brief (PM) APBB Clock Select */
#define REG_PM_APBCSEL (0x4000040BU) /**< \brief (PM) APBC Clock Select */
#define REG_PM_AHBMASK (0x40000414U) /**< \brief (PM) AHB Mask */
#define REG_PM_APBAMASK (0x40000418U) /**< \brief (PM) APBA Mask */
#define REG_PM_APBBMASK (0x4000041CU) /**< \brief (PM) APBB Mask */
#define REG_PM_APBCMASK (0x40000420U) /**< \brief (PM) APBC Mask */
#define REG_PM_INTENCLR (0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
#define REG_PM_INTENSET (0x40000435U) /**< \brief (PM) Interrupt Enable Set */
#define REG_PM_INTFLAG (0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
#define REG_PM_RCAUSE (0x40000438U) /**< \brief (PM) Reset Cause */
#else
#define REG_PM_CTRL (*(RwReg8 *)0x40000400U) /**< \brief (PM) Control */
#define REG_PM_SLEEP (*(RwReg8 *)0x40000401U) /**< \brief (PM) Sleep Mode */
#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408U) /**< \brief (PM) CPU Clock Select */
#define REG_PM_APBASEL (*(RwReg8 *)0x40000409U) /**< \brief (PM) APBA Clock Select */
#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AU) /**< \brief (PM) APBB Clock Select */
#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BU) /**< \brief (PM) APBC Clock Select */
#define REG_PM_AHBMASK (*(RwReg *)0x40000414U) /**< \brief (PM) AHB Mask */
#define REG_PM_APBAMASK (*(RwReg *)0x40000418U) /**< \brief (PM) APBA Mask */
#define REG_PM_APBBMASK (*(RwReg *)0x4000041CU) /**< \brief (PM) APBB Mask */
#define REG_PM_APBCMASK (*(RwReg *)0x40000420U) /**< \brief (PM) APBC Mask */
#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434U) /**< \brief (PM) Interrupt Enable Clear */
#define REG_PM_INTENSET (*(RwReg8 *)0x40000435U) /**< \brief (PM) Interrupt Enable Set */
#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436U) /**< \brief (PM) Interrupt Flag Status and Clear */
#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438U) /**< \brief (PM) Reset Cause */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PM peripheral ========== */
#define PM_CTRL_MCSEL_DFLL48M 3
#define PM_CTRL_MCSEL_GCLK 0
#define PM_CTRL_MCSEL_OSC8M 1
#define PM_CTRL_MCSEL_XOSC 2
#define PM_PM_CLK_APB_NUM 2
#endif /* _SAMD21_PM_INSTANCE_ */

136
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/port.h Normal file
View file

@ -0,0 +1,136 @@
/**
* \file
*
* \brief Instance description for PORT
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_PORT_INSTANCE_
#define _SAMD21_PORT_INSTANCE_
/* ========== Register definition for PORT peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PORT_DIR0 (0x41004400U) /**< \brief (PORT) Data Direction 0 */
#define REG_PORT_DIRCLR0 (0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
#define REG_PORT_DIRSET0 (0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
#define REG_PORT_DIRTGL0 (0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
#define REG_PORT_OUT0 (0x41004410U) /**< \brief (PORT) Data Output Value 0 */
#define REG_PORT_OUTCLR0 (0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
#define REG_PORT_OUTSET0 (0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
#define REG_PORT_OUTTGL0 (0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
#define REG_PORT_IN0 (0x41004420U) /**< \brief (PORT) Data Input Value 0 */
#define REG_PORT_CTRL0 (0x41004424U) /**< \brief (PORT) Control 0 */
#define REG_PORT_WRCONFIG0 (0x41004428U) /**< \brief (PORT) Write Configuration 0 */
#define REG_PORT_PMUX0 (0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
#define REG_PORT_PINCFG0 (0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
#define REG_PORT_DIR1 (0x41004480U) /**< \brief (PORT) Data Direction 1 */
#define REG_PORT_DIRCLR1 (0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
#define REG_PORT_DIRSET1 (0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
#define REG_PORT_DIRTGL1 (0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
#define REG_PORT_OUT1 (0x41004490U) /**< \brief (PORT) Data Output Value 1 */
#define REG_PORT_OUTCLR1 (0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
#define REG_PORT_OUTSET1 (0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
#define REG_PORT_OUTTGL1 (0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
#define REG_PORT_IN1 (0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
#define REG_PORT_CTRL1 (0x410044A4U) /**< \brief (PORT) Control 1 */
#define REG_PORT_WRCONFIG1 (0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
#define REG_PORT_PMUX1 (0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
#define REG_PORT_PINCFG1 (0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
#else
#define REG_PORT_DIR0 (*(RwReg *)0x41004400U) /**< \brief (PORT) Data Direction 0 */
#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404U) /**< \brief (PORT) Data Direction Clear 0 */
#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408U) /**< \brief (PORT) Data Direction Set 0 */
#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CU) /**< \brief (PORT) Data Direction Toggle 0 */
#define REG_PORT_OUT0 (*(RwReg *)0x41004410U) /**< \brief (PORT) Data Output Value 0 */
#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414U) /**< \brief (PORT) Data Output Value Clear 0 */
#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418U) /**< \brief (PORT) Data Output Value Set 0 */
#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CU) /**< \brief (PORT) Data Output Value Toggle 0 */
#define REG_PORT_IN0 (*(RoReg *)0x41004420U) /**< \brief (PORT) Data Input Value 0 */
#define REG_PORT_CTRL0 (*(RwReg *)0x41004424U) /**< \brief (PORT) Control 0 */
#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428U) /**< \brief (PORT) Write Configuration 0 */
#define REG_PORT_PMUX0 (*(RwReg *)0x41004430U) /**< \brief (PORT) Peripheral Multiplexing 0 */
#define REG_PORT_PINCFG0 (*(RwReg *)0x41004440U) /**< \brief (PORT) Pin Configuration 0 */
#define REG_PORT_DIR1 (*(RwReg *)0x41004480U) /**< \brief (PORT) Data Direction 1 */
#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484U) /**< \brief (PORT) Data Direction Clear 1 */
#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488U) /**< \brief (PORT) Data Direction Set 1 */
#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CU) /**< \brief (PORT) Data Direction Toggle 1 */
#define REG_PORT_OUT1 (*(RwReg *)0x41004490U) /**< \brief (PORT) Data Output Value 1 */
#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494U) /**< \brief (PORT) Data Output Value Clear 1 */
#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498U) /**< \brief (PORT) Data Output Value Set 1 */
#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CU) /**< \brief (PORT) Data Output Value Toggle 1 */
#define REG_PORT_IN1 (*(RoReg *)0x410044A0U) /**< \brief (PORT) Data Input Value 1 */
#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4U) /**< \brief (PORT) Control 1 */
#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8U) /**< \brief (PORT) Write Configuration 1 */
#define REG_PORT_PMUX1 (*(RwReg *)0x410044B0U) /**< \brief (PORT) Peripheral Multiplexing 1 */
#define REG_PORT_PINCFG1 (*(RwReg *)0x410044C0U) /**< \brief (PORT) Pin Configuration 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PORT peripheral ========== */
#define PORT_BITS 84
#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF }
#define PORT_DRVSTR 1
#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF }
#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF }
#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF }
#define PORT_ODRAIN 0
#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF }
#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF }
#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 }
#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 }
#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 }
#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 }
#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 }
#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 }
#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE }
#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF }
#define PORT_SLEWLIM 0
#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 }
#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
#endif /* _SAMD21_PORT_INSTANCE_ */

117
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/rtc.h Normal file
View file

@ -0,0 +1,117 @@
/**
* \file
*
* \brief Instance description for RTC
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_RTC_INSTANCE_
#define _SAMD21_RTC_INSTANCE_
/* ========== Register definition for RTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RTC_READREQ (0x40001402U) /**< \brief (RTC) Read Request */
#define REG_RTC_STATUS (0x4000140AU) /**< \brief (RTC) Status */
#define REG_RTC_DBGCTRL (0x4000140BU) /**< \brief (RTC) Debug Control */
#define REG_RTC_FREQCORR (0x4000140CU) /**< \brief (RTC) Frequency Correction */
#define REG_RTC_MODE0_CTRL (0x40001400U) /**< \brief (RTC) MODE0 Control */
#define REG_RTC_MODE0_EVCTRL (0x40001404U) /**< \brief (RTC) MODE0 Event Control */
#define REG_RTC_MODE0_INTENCLR (0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
#define REG_RTC_MODE0_INTENSET (0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
#define REG_RTC_MODE0_INTFLAG (0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
#define REG_RTC_MODE0_COUNT (0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
#define REG_RTC_MODE0_COMP0 (0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
#define REG_RTC_MODE1_CTRL (0x40001400U) /**< \brief (RTC) MODE1 Control */
#define REG_RTC_MODE1_EVCTRL (0x40001404U) /**< \brief (RTC) MODE1 Event Control */
#define REG_RTC_MODE1_INTENCLR (0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
#define REG_RTC_MODE1_INTENSET (0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
#define REG_RTC_MODE1_INTFLAG (0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
#define REG_RTC_MODE1_COUNT (0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
#define REG_RTC_MODE1_PER (0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
#define REG_RTC_MODE1_COMP0 (0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
#define REG_RTC_MODE1_COMP1 (0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
#define REG_RTC_MODE2_CTRL (0x40001400U) /**< \brief (RTC) MODE2 Control */
#define REG_RTC_MODE2_EVCTRL (0x40001404U) /**< \brief (RTC) MODE2 Event Control */
#define REG_RTC_MODE2_INTENCLR (0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
#define REG_RTC_MODE2_INTENSET (0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
#define REG_RTC_MODE2_INTFLAG (0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
#define REG_RTC_MODE2_CLOCK (0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
#else
#define REG_RTC_READREQ (*(RwReg16*)0x40001402U) /**< \brief (RTC) Read Request */
#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AU) /**< \brief (RTC) Status */
#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BU) /**< \brief (RTC) Debug Control */
#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CU) /**< \brief (RTC) Frequency Correction */
#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE0 Control */
#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE0 Event Control */
#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE0 Interrupt Enable Set */
#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE0 Counter Value */
#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE0 Compare 0 Value */
#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE1 Control */
#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE1 Event Control */
#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE1 Interrupt Enable Set */
#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410U) /**< \brief (RTC) MODE1 Counter Value */
#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414U) /**< \brief (RTC) MODE1 Counter Period */
#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418U) /**< \brief (RTC) MODE1 Compare 0 Value */
#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AU) /**< \brief (RTC) MODE1 Compare 1 Value */
#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400U) /**< \brief (RTC) MODE2 Control */
#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404U) /**< \brief (RTC) MODE2 Event Control */
#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406U) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407U) /**< \brief (RTC) MODE2 Interrupt Enable Set */
#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408U) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410U) /**< \brief (RTC) MODE2 Clock Value */
#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418U) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg *)0x4000141CU) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RTC peripheral ========== */
#define RTC_ALARM_NUM 1
#define RTC_COMP16_NUM 2
#define RTC_COMP32_NUM RTC_ALARM_NUM
#define RTC_GCLK_ID 4
#define RTC_NUM_OF_ALARMS RTC_ALARM_NUM
#define RTC_NUM_OF_COMP16 RTC_COMP16_NUM
#define RTC_NUM_OF_COMP32 RTC_COMP32_NUM
#endif /* _SAMD21_RTC_INSTANCE_ */

143
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom0.h Normal file
View file

@ -0,0 +1,143 @@
/**
* \file
*
* \brief Instance description for SERCOM0
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_SERCOM0_INSTANCE_
#define _SAMD21_SERCOM0_INSTANCE_
/* ========== Register definition for SERCOM0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM0_I2CM_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
#define REG_SERCOM0_I2CM_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
#define REG_SERCOM0_I2CM_BAUD (0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
#define REG_SERCOM0_I2CM_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
#define REG_SERCOM0_I2CM_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
#define REG_SERCOM0_I2CM_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CM_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
#define REG_SERCOM0_I2CM_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CM Address */
#define REG_SERCOM0_I2CM_DATA (0x42000828U) /**< \brief (SERCOM0) I2CM Data */
#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
#define REG_SERCOM0_I2CS_CTRLA (0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
#define REG_SERCOM0_I2CS_CTRLB (0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
#define REG_SERCOM0_I2CS_INTENCLR (0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
#define REG_SERCOM0_I2CS_INTENSET (0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
#define REG_SERCOM0_I2CS_INTFLAG (0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CS_STATUS (0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
#define REG_SERCOM0_I2CS_ADDR (0x42000824U) /**< \brief (SERCOM0) I2CS Address */
#define REG_SERCOM0_I2CS_DATA (0x42000828U) /**< \brief (SERCOM0) I2CS Data */
#define REG_SERCOM0_SPI_CTRLA (0x42000800U) /**< \brief (SERCOM0) SPI Control A */
#define REG_SERCOM0_SPI_CTRLB (0x42000804U) /**< \brief (SERCOM0) SPI Control B */
#define REG_SERCOM0_SPI_BAUD (0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
#define REG_SERCOM0_SPI_INTENCLR (0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
#define REG_SERCOM0_SPI_INTENSET (0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
#define REG_SERCOM0_SPI_INTFLAG (0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM0_SPI_STATUS (0x4200081AU) /**< \brief (SERCOM0) SPI Status */
#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
#define REG_SERCOM0_SPI_ADDR (0x42000824U) /**< \brief (SERCOM0) SPI Address */
#define REG_SERCOM0_SPI_DATA (0x42000828U) /**< \brief (SERCOM0) SPI Data */
#define REG_SERCOM0_SPI_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
#define REG_SERCOM0_USART_CTRLA (0x42000800U) /**< \brief (SERCOM0) USART Control A */
#define REG_SERCOM0_USART_CTRLB (0x42000804U) /**< \brief (SERCOM0) USART Control B */
#define REG_SERCOM0_USART_BAUD (0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
#define REG_SERCOM0_USART_RXPL (0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
#define REG_SERCOM0_USART_INTENCLR (0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
#define REG_SERCOM0_USART_INTENSET (0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
#define REG_SERCOM0_USART_INTFLAG (0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
#define REG_SERCOM0_USART_STATUS (0x4200081AU) /**< \brief (SERCOM0) USART Status */
#define REG_SERCOM0_USART_SYNCBUSY (0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
#define REG_SERCOM0_USART_DATA (0x42000828U) /**< \brief (SERCOM0) USART Data */
#define REG_SERCOM0_USART_DBGCTRL (0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
#else
#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CM Control A */
#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CM Control B */
#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CU) /**< \brief (SERCOM0) I2CM Baud Rate */
#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CM Status */
#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CM Syncbusy */
#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CM Address */
#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CM Data */
#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) I2CM Debug Control */
#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) I2CS Control A */
#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) I2CS Control B */
#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) I2CS Status */
#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) I2CS Syncbusy */
#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) I2CS Address */
#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828U) /**< \brief (SERCOM0) I2CS Data */
#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) SPI Control A */
#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) SPI Control B */
#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CU) /**< \brief (SERCOM0) SPI Baud Rate */
#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) SPI Status */
#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) SPI Syncbusy */
#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824U) /**< \brief (SERCOM0) SPI Address */
#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828U) /**< \brief (SERCOM0) SPI Data */
#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) SPI Debug Control */
#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800U) /**< \brief (SERCOM0) USART Control A */
#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804U) /**< \brief (SERCOM0) USART Control B */
#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CU) /**< \brief (SERCOM0) USART Baud Rate */
#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EU) /**< \brief (SERCOM0) USART Receive Pulse Length */
#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814U) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816U) /**< \brief (SERCOM0) USART Interrupt Enable Set */
#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818U) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AU) /**< \brief (SERCOM0) USART Status */
#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CU) /**< \brief (SERCOM0) USART Syncbusy */
#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828U) /**< \brief (SERCOM0) USART Data */
#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830U) /**< \brief (SERCOM0) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM0 peripheral ========== */
#define SERCOM0_DMAC_ID_RX 1
#define SERCOM0_DMAC_ID_TX 2
#define SERCOM0_GCLK_ID_CORE 20
#define SERCOM0_GCLK_ID_SLOW 19
#define SERCOM0_INT_MSB 6
#endif /* _SAMD21_SERCOM0_INSTANCE_ */

143
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom1.h Normal file
View file

@ -0,0 +1,143 @@
/**
* \file
*
* \brief Instance description for SERCOM1
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_SERCOM1_INSTANCE_
#define _SAMD21_SERCOM1_INSTANCE_
/* ========== Register definition for SERCOM1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM1_I2CM_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
#define REG_SERCOM1_I2CM_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
#define REG_SERCOM1_I2CM_BAUD (0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
#define REG_SERCOM1_I2CM_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CM_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */
#define REG_SERCOM1_I2CM_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
#define REG_SERCOM1_I2CM_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
#define REG_SERCOM1_I2CS_CTRLA (0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
#define REG_SERCOM1_I2CS_CTRLB (0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
#define REG_SERCOM1_I2CS_INTENSET (0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CS_STATUS (0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */
#define REG_SERCOM1_I2CS_ADDR (0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
#define REG_SERCOM1_I2CS_DATA (0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
#define REG_SERCOM1_SPI_CTRLA (0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
#define REG_SERCOM1_SPI_CTRLB (0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
#define REG_SERCOM1_SPI_BAUD (0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
#define REG_SERCOM1_SPI_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
#define REG_SERCOM1_SPI_INTENSET (0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
#define REG_SERCOM1_SPI_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM1_SPI_STATUS (0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */
#define REG_SERCOM1_SPI_ADDR (0x42000C24U) /**< \brief (SERCOM1) SPI Address */
#define REG_SERCOM1_SPI_DATA (0x42000C28U) /**< \brief (SERCOM1) SPI Data */
#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
#define REG_SERCOM1_USART_CTRLA (0x42000C00U) /**< \brief (SERCOM1) USART Control A */
#define REG_SERCOM1_USART_CTRLB (0x42000C04U) /**< \brief (SERCOM1) USART Control B */
#define REG_SERCOM1_USART_BAUD (0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
#define REG_SERCOM1_USART_RXPL (0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
#define REG_SERCOM1_USART_INTENCLR (0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
#define REG_SERCOM1_USART_INTENSET (0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
#define REG_SERCOM1_USART_INTFLAG (0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
#define REG_SERCOM1_USART_STATUS (0x42000C1AU) /**< \brief (SERCOM1) USART Status */
#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */
#define REG_SERCOM1_USART_DATA (0x42000C28U) /**< \brief (SERCOM1) USART Data */
#define REG_SERCOM1_USART_DBGCTRL (0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
#else
#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CM Control A */
#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CM Control B */
#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CU) /**< \brief (SERCOM1) I2CM Baud Rate */
#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CM Status */
#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CM Syncbusy */
#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CM Address */
#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CM Data */
#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) I2CM Debug Control */
#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) I2CS Control A */
#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) I2CS Control B */
#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) I2CS Status */
#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) I2CS Syncbusy */
#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) I2CS Address */
#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28U) /**< \brief (SERCOM1) I2CS Data */
#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) SPI Control A */
#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) SPI Control B */
#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CU) /**< \brief (SERCOM1) SPI Baud Rate */
#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) SPI Status */
#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) SPI Syncbusy */
#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24U) /**< \brief (SERCOM1) SPI Address */
#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28U) /**< \brief (SERCOM1) SPI Data */
#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) SPI Debug Control */
#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00U) /**< \brief (SERCOM1) USART Control A */
#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04U) /**< \brief (SERCOM1) USART Control B */
#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CU) /**< \brief (SERCOM1) USART Baud Rate */
#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EU) /**< \brief (SERCOM1) USART Receive Pulse Length */
#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14U) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16U) /**< \brief (SERCOM1) USART Interrupt Enable Set */
#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18U) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AU) /**< \brief (SERCOM1) USART Status */
#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CU) /**< \brief (SERCOM1) USART Syncbusy */
#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28U) /**< \brief (SERCOM1) USART Data */
#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30U) /**< \brief (SERCOM1) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM1 peripheral ========== */
#define SERCOM1_DMAC_ID_RX 3
#define SERCOM1_DMAC_ID_TX 4
#define SERCOM1_GCLK_ID_CORE 21
#define SERCOM1_GCLK_ID_SLOW 19
#define SERCOM1_INT_MSB 6
#endif /* _SAMD21_SERCOM1_INSTANCE_ */

143
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom2.h Normal file
View file

@ -0,0 +1,143 @@
/**
* \file
*
* \brief Instance description for SERCOM2
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_SERCOM2_INSTANCE_
#define _SAMD21_SERCOM2_INSTANCE_
/* ========== Register definition for SERCOM2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM2_I2CM_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
#define REG_SERCOM2_I2CM_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
#define REG_SERCOM2_I2CM_BAUD (0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
#define REG_SERCOM2_I2CM_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
#define REG_SERCOM2_I2CM_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
#define REG_SERCOM2_I2CM_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CM_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
#define REG_SERCOM2_I2CM_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CM Address */
#define REG_SERCOM2_I2CM_DATA (0x42001028U) /**< \brief (SERCOM2) I2CM Data */
#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
#define REG_SERCOM2_I2CS_CTRLA (0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
#define REG_SERCOM2_I2CS_CTRLB (0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
#define REG_SERCOM2_I2CS_INTENCLR (0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
#define REG_SERCOM2_I2CS_INTENSET (0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
#define REG_SERCOM2_I2CS_INTFLAG (0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CS_STATUS (0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
#define REG_SERCOM2_I2CS_ADDR (0x42001024U) /**< \brief (SERCOM2) I2CS Address */
#define REG_SERCOM2_I2CS_DATA (0x42001028U) /**< \brief (SERCOM2) I2CS Data */
#define REG_SERCOM2_SPI_CTRLA (0x42001000U) /**< \brief (SERCOM2) SPI Control A */
#define REG_SERCOM2_SPI_CTRLB (0x42001004U) /**< \brief (SERCOM2) SPI Control B */
#define REG_SERCOM2_SPI_BAUD (0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
#define REG_SERCOM2_SPI_INTENCLR (0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
#define REG_SERCOM2_SPI_INTENSET (0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
#define REG_SERCOM2_SPI_INTFLAG (0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM2_SPI_STATUS (0x4200101AU) /**< \brief (SERCOM2) SPI Status */
#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
#define REG_SERCOM2_SPI_ADDR (0x42001024U) /**< \brief (SERCOM2) SPI Address */
#define REG_SERCOM2_SPI_DATA (0x42001028U) /**< \brief (SERCOM2) SPI Data */
#define REG_SERCOM2_SPI_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
#define REG_SERCOM2_USART_CTRLA (0x42001000U) /**< \brief (SERCOM2) USART Control A */
#define REG_SERCOM2_USART_CTRLB (0x42001004U) /**< \brief (SERCOM2) USART Control B */
#define REG_SERCOM2_USART_BAUD (0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
#define REG_SERCOM2_USART_RXPL (0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
#define REG_SERCOM2_USART_INTENCLR (0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
#define REG_SERCOM2_USART_INTENSET (0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
#define REG_SERCOM2_USART_INTFLAG (0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
#define REG_SERCOM2_USART_STATUS (0x4200101AU) /**< \brief (SERCOM2) USART Status */
#define REG_SERCOM2_USART_SYNCBUSY (0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
#define REG_SERCOM2_USART_DATA (0x42001028U) /**< \brief (SERCOM2) USART Data */
#define REG_SERCOM2_USART_DBGCTRL (0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
#else
#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CM Control A */
#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CM Control B */
#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CU) /**< \brief (SERCOM2) I2CM Baud Rate */
#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CM Status */
#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CM Syncbusy */
#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CM Address */
#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CM Data */
#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) I2CM Debug Control */
#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) I2CS Control A */
#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) I2CS Control B */
#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) I2CS Status */
#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) I2CS Syncbusy */
#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) I2CS Address */
#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028U) /**< \brief (SERCOM2) I2CS Data */
#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) SPI Control A */
#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) SPI Control B */
#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CU) /**< \brief (SERCOM2) SPI Baud Rate */
#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) SPI Status */
#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) SPI Syncbusy */
#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024U) /**< \brief (SERCOM2) SPI Address */
#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028U) /**< \brief (SERCOM2) SPI Data */
#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) SPI Debug Control */
#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000U) /**< \brief (SERCOM2) USART Control A */
#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004U) /**< \brief (SERCOM2) USART Control B */
#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CU) /**< \brief (SERCOM2) USART Baud Rate */
#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EU) /**< \brief (SERCOM2) USART Receive Pulse Length */
#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014U) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016U) /**< \brief (SERCOM2) USART Interrupt Enable Set */
#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018U) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AU) /**< \brief (SERCOM2) USART Status */
#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CU) /**< \brief (SERCOM2) USART Syncbusy */
#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028U) /**< \brief (SERCOM2) USART Data */
#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030U) /**< \brief (SERCOM2) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM2 peripheral ========== */
#define SERCOM2_DMAC_ID_RX 5
#define SERCOM2_DMAC_ID_TX 6
#define SERCOM2_GCLK_ID_CORE 22
#define SERCOM2_GCLK_ID_SLOW 19
#define SERCOM2_INT_MSB 6
#endif /* _SAMD21_SERCOM2_INSTANCE_ */

143
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom3.h Normal file
View file

@ -0,0 +1,143 @@
/**
* \file
*
* \brief Instance description for SERCOM3
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_SERCOM3_INSTANCE_
#define _SAMD21_SERCOM3_INSTANCE_
/* ========== Register definition for SERCOM3 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM3_I2CM_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
#define REG_SERCOM3_I2CM_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
#define REG_SERCOM3_I2CM_BAUD (0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
#define REG_SERCOM3_I2CM_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
#define REG_SERCOM3_I2CM_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
#define REG_SERCOM3_I2CM_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CM_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
#define REG_SERCOM3_I2CM_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CM Address */
#define REG_SERCOM3_I2CM_DATA (0x42001428U) /**< \brief (SERCOM3) I2CM Data */
#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
#define REG_SERCOM3_I2CS_CTRLA (0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
#define REG_SERCOM3_I2CS_CTRLB (0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
#define REG_SERCOM3_I2CS_INTENCLR (0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
#define REG_SERCOM3_I2CS_INTENSET (0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
#define REG_SERCOM3_I2CS_INTFLAG (0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CS_STATUS (0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
#define REG_SERCOM3_I2CS_ADDR (0x42001424U) /**< \brief (SERCOM3) I2CS Address */
#define REG_SERCOM3_I2CS_DATA (0x42001428U) /**< \brief (SERCOM3) I2CS Data */
#define REG_SERCOM3_SPI_CTRLA (0x42001400U) /**< \brief (SERCOM3) SPI Control A */
#define REG_SERCOM3_SPI_CTRLB (0x42001404U) /**< \brief (SERCOM3) SPI Control B */
#define REG_SERCOM3_SPI_BAUD (0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
#define REG_SERCOM3_SPI_INTENCLR (0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
#define REG_SERCOM3_SPI_INTENSET (0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
#define REG_SERCOM3_SPI_INTFLAG (0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM3_SPI_STATUS (0x4200141AU) /**< \brief (SERCOM3) SPI Status */
#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
#define REG_SERCOM3_SPI_ADDR (0x42001424U) /**< \brief (SERCOM3) SPI Address */
#define REG_SERCOM3_SPI_DATA (0x42001428U) /**< \brief (SERCOM3) SPI Data */
#define REG_SERCOM3_SPI_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
#define REG_SERCOM3_USART_CTRLA (0x42001400U) /**< \brief (SERCOM3) USART Control A */
#define REG_SERCOM3_USART_CTRLB (0x42001404U) /**< \brief (SERCOM3) USART Control B */
#define REG_SERCOM3_USART_BAUD (0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
#define REG_SERCOM3_USART_RXPL (0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
#define REG_SERCOM3_USART_INTENCLR (0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
#define REG_SERCOM3_USART_INTENSET (0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
#define REG_SERCOM3_USART_INTFLAG (0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
#define REG_SERCOM3_USART_STATUS (0x4200141AU) /**< \brief (SERCOM3) USART Status */
#define REG_SERCOM3_USART_SYNCBUSY (0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
#define REG_SERCOM3_USART_DATA (0x42001428U) /**< \brief (SERCOM3) USART Data */
#define REG_SERCOM3_USART_DBGCTRL (0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
#else
#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CM Control A */
#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CM Control B */
#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CU) /**< \brief (SERCOM3) I2CM Baud Rate */
#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CM Status */
#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CM Syncbusy */
#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CM Address */
#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CM Data */
#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) I2CM Debug Control */
#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) I2CS Control A */
#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) I2CS Control B */
#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) I2CS Status */
#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) I2CS Syncbusy */
#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) I2CS Address */
#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428U) /**< \brief (SERCOM3) I2CS Data */
#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) SPI Control A */
#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) SPI Control B */
#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CU) /**< \brief (SERCOM3) SPI Baud Rate */
#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) SPI Status */
#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) SPI Syncbusy */
#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424U) /**< \brief (SERCOM3) SPI Address */
#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428U) /**< \brief (SERCOM3) SPI Data */
#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) SPI Debug Control */
#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400U) /**< \brief (SERCOM3) USART Control A */
#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404U) /**< \brief (SERCOM3) USART Control B */
#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CU) /**< \brief (SERCOM3) USART Baud Rate */
#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EU) /**< \brief (SERCOM3) USART Receive Pulse Length */
#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414U) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416U) /**< \brief (SERCOM3) USART Interrupt Enable Set */
#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418U) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AU) /**< \brief (SERCOM3) USART Status */
#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CU) /**< \brief (SERCOM3) USART Syncbusy */
#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428U) /**< \brief (SERCOM3) USART Data */
#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430U) /**< \brief (SERCOM3) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM3 peripheral ========== */
#define SERCOM3_DMAC_ID_RX 7
#define SERCOM3_DMAC_ID_TX 8
#define SERCOM3_GCLK_ID_CORE 23
#define SERCOM3_GCLK_ID_SLOW 19
#define SERCOM3_INT_MSB 6
#endif /* _SAMD21_SERCOM3_INSTANCE_ */

143
bootloaders/mzero/Bootloader_D21/src/ASF/sam0/utils/cmsis/samd21/include/instance/sercom4.h Normal file
View file

@ -0,0 +1,143 @@
/**
* \file
*
* \brief Instance description for SERCOM4
*
* Copyright (c) 2014 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef _SAMD21_SERCOM4_INSTANCE_
#define _SAMD21_SERCOM4_INSTANCE_
/* ========== Register definition for SERCOM4 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM4_I2CM_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
#define REG_SERCOM4_I2CM_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
#define REG_SERCOM4_I2CM_BAUD (0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
#define REG_SERCOM4_I2CM_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
#define REG_SERCOM4_I2CM_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
#define REG_SERCOM4_I2CM_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CM_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
#define REG_SERCOM4_I2CM_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CM Address */
#define REG_SERCOM4_I2CM_DATA (0x42001828U) /**< \brief (SERCOM4) I2CM Data */
#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
#define REG_SERCOM4_I2CS_CTRLA (0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
#define REG_SERCOM4_I2CS_CTRLB (0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
#define REG_SERCOM4_I2CS_INTENCLR (0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
#define REG_SERCOM4_I2CS_INTENSET (0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
#define REG_SERCOM4_I2CS_INTFLAG (0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CS_STATUS (0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
#define REG_SERCOM4_I2CS_ADDR (0x42001824U) /**< \brief (SERCOM4) I2CS Address */
#define REG_SERCOM4_I2CS_DATA (0x42001828U) /**< \brief (SERCOM4) I2CS Data */
#define REG_SERCOM4_SPI_CTRLA (0x42001800U) /**< \brief (SERCOM4) SPI Control A */
#define REG_SERCOM4_SPI_CTRLB (0x42001804U) /**< \brief (SERCOM4) SPI Control B */
#define REG_SERCOM4_SPI_BAUD (0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
#define REG_SERCOM4_SPI_INTENCLR (0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
#define REG_SERCOM4_SPI_INTENSET (0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
#define REG_SERCOM4_SPI_INTFLAG (0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM4_SPI_STATUS (0x4200181AU) /**< \brief (SERCOM4) SPI Status */
#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
#define REG_SERCOM4_SPI_ADDR (0x42001824U) /**< \brief (SERCOM4) SPI Address */
#define REG_SERCOM4_SPI_DATA (0x42001828U) /**< \brief (SERCOM4) SPI Data */
#define REG_SERCOM4_SPI_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
#define REG_SERCOM4_USART_CTRLA (0x42001800U) /**< \brief (SERCOM4) USART Control A */
#define REG_SERCOM4_USART_CTRLB (0x42001804U) /**< \brief (SERCOM4) USART Control B */
#define REG_SERCOM4_USART_BAUD (0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
#define REG_SERCOM4_USART_RXPL (0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
#define REG_SERCOM4_USART_INTENCLR (0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
#define REG_SERCOM4_USART_INTENSET (0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
#define REG_SERCOM4_USART_INTFLAG (0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
#define REG_SERCOM4_USART_STATUS (0x4200181AU) /**< \brief (SERCOM4) USART Status */
#define REG_SERCOM4_USART_SYNCBUSY (0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
#define REG_SERCOM4_USART_DATA (0x42001828U) /**< \brief (SERCOM4) USART Data */
#define REG_SERCOM4_USART_DBGCTRL (0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
#else
#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CM Control A */
#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CM Control B */
#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CU) /**< \brief (SERCOM4) I2CM Baud Rate */
#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CM Status */
#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CM Syncbusy */
#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CM Address */
#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CM Data */
#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) I2CM Debug Control */
#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) I2CS Control A */
#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) I2CS Control B */
#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) I2CS Status */
#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) I2CS Syncbusy */
#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) I2CS Address */
#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828U) /**< \brief (SERCOM4) I2CS Data */
#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) SPI Control A */
#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) SPI Control B */
#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CU) /**< \brief (SERCOM4) SPI Baud Rate */
#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) SPI Status */
#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) SPI Syncbusy */
#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824U) /**< \brief (SERCOM4) SPI Address */
#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828U) /**< \brief (SERCOM4) SPI Data */
#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) SPI Debug Control */
#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800U) /**< \brief (SERCOM4) USART Control A */
#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804U) /**< \brief (SERCOM4) USART Control B */
#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CU) /**< \brief (SERCOM4) USART Baud Rate */
#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EU) /**< \brief (SERCOM4) USART Receive Pulse Length */
#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814U) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816U) /**< \brief (SERCOM4) USART Interrupt Enable Set */
#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818U) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AU) /**< \brief (SERCOM4) USART Status */
#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CU) /**< \brief (SERCOM4) USART Syncbusy */
#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828U) /**< \brief (SERCOM4) USART Data */
#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830U) /**< \brief (SERCOM4) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM4 peripheral ========== */
#define SERCOM4_DMAC_ID_RX 9
#define SERCOM4_DMAC_ID_TX 10
#define SERCOM4_GCLK_ID_CORE 24
#define SERCOM4_GCLK_ID_SLOW 19
#define SERCOM4_INT_MSB 6
#endif /* _SAMD21_SERCOM4_INSTANCE_ */

Some files were not shown because too many files have changed in this diff Show more