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DM: in progress SPI DMA

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This commit is contained in:
dean 2018-08-28 17:09:02 -04:00
parent a278034831
commit ae3d233b56
2 changed files with 37 additions and 0 deletions
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36
libraries/SPI/SPI.cpp
View file

@ -306,6 +306,42 @@ void SPIClass::transfer(void *rx, void *tx, size_t count)
}
}
//returns true if the transfer could be started, false otherwise
bool SPIClass::transferNonBlocking(void *rx, void *tx, size_t count)
{
if(count < 65536 && _dmaChannelRx > -1 && _dmaChannelTx > -1){
//previous transfer has not finished
if(_writeback[_dmaChannelTx].BTCTRL.bit.VALID || !_p_sercom->isDataRegisterEmptySPI() ||
!_p_sercom->isTransmitCompleteSPI()){
return false;
}
//use a synchronous DMA transfer
descrx->BTCTRL.bit.VALID = true;
descrx->DSTADDR.reg = (uint32_t)rx + count;
descrx->BTCNT.reg = count;
desctx->BTCTRL.bit.VALID = true;
desctx->SRCADDR.reg = (uint32_t)tx + count;
desctx->BTCNT.reg = count;
#ifdef __SAMD51__
DMAC->Channel[_dmaChannelTx].CHCTRLA.bit.ENABLE = 1;
if(rx != NULL)
DMAC->Channel[_dmaChannelRx].CHCTRLA.bit.ENABLE = 1;
#else
DMAC->CHID.bit.ID = _dmaChannelTx;
DMAC->CHCTRLA.bit.ENABLE = 1;
DMAC->CHID.bit.ID = _dmaChannelRx;
DMAC->CHCTRLA.bit.ENABLE = 1;
#endif
return true;
}
else{
return false;
}
}
void SPIClass::transfer(void *buf, size_t count){
transfer(buf, buf, count);
}

1
libraries/SPI/SPI.h
View file

@ -99,6 +99,7 @@ class SPIClass {
uint16_t transfer16(uint16_t data);
void transfer(void *buf, size_t count);
void transfer(void *rx, void *tx, size_t count);
bool transferNonBlocking(void *rx, void *tx, size_t count);
// Transaction Functions
void usingInterrupt(int interruptNumber);