DM: in progress i2s / dma support
This commit is contained in:
dean
parent
8a32178667
commit
dc5464d328
5 changed files with 402 additions and 10 deletions
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@ -20,10 +20,21 @@
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#include <wiring_private.h>
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#include "utility/DMA.h"
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#if defined(__SAMD51__)
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#include "utility/SAMD51_I2SDevice.h"
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static I2SDevice_SAMD51 i2sd(*I2S);
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#else
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#include "utility/SAMD21_I2SDevice.h"
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static I2SDevice_SAMD21G18x i2sd(*I2S);
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#endif
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#include "I2S.h"
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int I2SClass::_beginCount = 0;
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@ -98,7 +109,11 @@ int I2SClass::begin(int mode, long sampleRate, int bitsPerSample, bool driveCloc
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if (_beginCount == 0) {
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// enable the I2S interface
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#if defined(__SAMD51__)
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MCLK->APBDMASK.reg |= MCLK_APBDMASK_I2S;
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#else
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PM->APBCMASK.reg |= PM_APBCMASK_I2S;
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#endif
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// reset the device
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i2sd.reset();
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@ -176,7 +191,11 @@ void I2SClass::end()
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i2sd.disable();
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// disable the I2S interface
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#if defined(__SAMD51__)
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MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_I2S);
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#else
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PM->APBCMASK.reg &= ~PM_APBCMASK_I2S;
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#endif
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}
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}
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@ -39,9 +39,14 @@ DMAClass::~DMAClass()
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void DMAClass::begin()
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{
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if (_beginCount == 0) {
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#if defined(__SAMD51__)
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MCLK->AHBMASK.bit.DMAC_ = 1;
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#else
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// enable the DMA interface
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PM->AHBMASK.bit.DMAC_ = 1;
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PM->APBBMASK.bit.DMAC_ = 1;
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#endif
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// perform a reset
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DMAC->CTRL.bit.SWRST = 1;
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@ -57,9 +62,35 @@ void DMAClass::begin()
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DMAC->CTRL.bit.LVLEN3 = 1;
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DMAC->CTRL.bit.DMAENABLE = 1;
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// enable the interrupt at lowest priority
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#if defined(__SAMD51__)
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NVIC_DisableIRQ(DMAC_0_IRQn);
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NVIC_ClearPendingIRQ(DMAC_0_IRQn);
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NVIC_EnableIRQ(DMAC_0_IRQn);
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NVIC_SetPriority(DMAC_0_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
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NVIC_DisableIRQ(DMAC_1_IRQn);
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NVIC_ClearPendingIRQ(DMAC_1_IRQn);
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NVIC_EnableIRQ(DMAC_1_IRQn);
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NVIC_SetPriority(DMAC_1_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
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NVIC_DisableIRQ(DMAC_2_IRQn);
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NVIC_ClearPendingIRQ(DMAC_2_IRQn);
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NVIC_EnableIRQ(DMAC_2_IRQn);
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NVIC_SetPriority(DMAC_2_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
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NVIC_DisableIRQ(DMAC_3_IRQn);
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NVIC_ClearPendingIRQ(DMAC_3_IRQn);
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NVIC_EnableIRQ(DMAC_3_IRQn);
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NVIC_SetPriority(DMAC_3_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
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NVIC_DisableIRQ(DMAC_4_IRQn);
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NVIC_ClearPendingIRQ(DMAC_4_IRQn);
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NVIC_EnableIRQ(DMAC_4_IRQn);
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NVIC_SetPriority(DMAC_4_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
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#else
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NVIC_EnableIRQ(DMAC_IRQn);
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NVIC_SetPriority(DMAC_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
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#endif
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}
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_beginCount++;
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@ -71,14 +102,27 @@ void DMAClass::end()
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if (_beginCount == 0) {
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// disable the interrupt
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#if defined(__SAMD51__)
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NVIC_DisableIRQ(DMAC_0_IRQn);
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NVIC_DisableIRQ(DMAC_1_IRQn);
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NVIC_DisableIRQ(DMAC_2_IRQn);
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NVIC_DisableIRQ(DMAC_3_IRQn);
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NVIC_DisableIRQ(DMAC_4_IRQn);
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#else
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NVIC_DisableIRQ(DMAC_IRQn);
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#endif
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// disable
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DMAC->CTRL.bit.DMAENABLE = 0;
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// disable the DMA interface
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PM->APBBMASK.bit.DMAC_ = 0;
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#if defined(__SAMD51__)
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MCLK->AHBMASK.bit.DMAC_ = 0;
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#else
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// enable the DMA interface
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PM->AHBMASK.bit.DMAC_ = 0;
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PM->APBBMASK.bit.DMAC_ = 0;
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#endif
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}
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}
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@ -96,9 +140,14 @@ int DMAClass::allocateChannel()
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memset((void*)&_descriptors[i], 0x00, sizeof(_descriptors[i]));
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// select the channel and reset it
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#if defined(__SAMD51__)
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DMAC->Channel[i].CHCTRLA.bit.ENABLE = 0;
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DMAC->Channel[i].CHCTRLA.bit.SWRST = 1;
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#else
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DMAC->CHID.bit.ID = i;
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DMAC->CHCTRLA.bit.ENABLE = 0;
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DMAC->CHCTRLA.bit.SWRST = 1;
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#endif
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channel = i;
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break;
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@ -111,8 +160,12 @@ int DMAClass::allocateChannel()
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void DMAClass::freeChannel(int channel)
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{
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// select the channel and disable it
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DMAC->CHID.bit.ID = channel;
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DMAC->CHCTRLA.bit.ENABLE = 0;
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#if defined(__SAMD51__)
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DMAC->Channel[channel].CHCTRLA.bit.ENABLE = 0;
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#else
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DMAC->CHID.bit.ID = channel;
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DMAC->CHCTRLA.bit.ENABLE = 0;
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#endif
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_channelMask &= ~(1 << channel);
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}
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@ -120,12 +173,21 @@ void DMAClass::freeChannel(int channel)
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void DMAClass::setPriorityLevel(int channel, int level)
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{
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// select the channel and set priority level
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DMAC->CHID.bit.ID = channel;
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DMAC->CHCTRLB.bit.LVL = level;
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#if defined(__SAMD51__)
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DMAC->Channel[channel].CHPRILVL.reg = level;
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#else
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DMAC->CHID.bit.ID = channel;
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DMAC->CHCTRLB.bit.LVL = level;
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#endif
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}
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void DMAClass::setTriggerSource(int channel, int source)
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{
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#if defined(__SAMD51__)
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DMAC->Channel[channel].CHCTRLA.bit.TRIGSRC = source;
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DMAC->Channel[channel].CHCTRLA.bit.TRIGACT = DMAC_CHCTRLA_TRIGACT_BLOCK_Val;
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#else
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// select the channel and set a trigger source
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DMAC->CHID.bit.ID = channel;
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DMAC->CHCTRLB.bit.TRIGSRC = source;
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@ -136,6 +198,7 @@ void DMAClass::setTriggerSource(int channel, int source)
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} else {
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DMAC->CHCTRLB.bit.TRIGACT = DMAC_CHCTRLB_TRIGACT_BLOCK_Val;
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}
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#endif
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}
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void DMAClass::setTransferWidth(int channel, int transferWidth)
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@ -178,8 +241,11 @@ int DMAClass::transfer(int channel, void* src, void* dst, uint16_t size)
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return 1;
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}
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#if !defined(__SAMD51__)
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// select the channel
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DMAC->CHID.bit.ID = channel;
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#endif
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// disable event output generation and block actions
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_descriptors[channel].BTCTRL.bit.EVOSEL = DMAC_BTCTRL_EVOSEL_DISABLE_Val;
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@ -223,16 +289,26 @@ int DMAClass::transfer(int channel, void* src, void* dst, uint16_t size)
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// validate the descriptor
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_descriptors[channel].BTCTRL.bit.VALID = 1;
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#if defined(__SAMD51__)
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DMAC->Channel[channel].CHINTENSET.bit.TERR = 1;
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DMAC->Channel[channel].CHINTENSET.bit.TCMPL = 1;
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DMAC->Channel[channel].CHCTRLA.bit.ENABLE = 1;
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if (DMAC->Channel[channel].CHCTRLA.bit.TRIGSRC == 0) {
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// uses software trigger, so trigger it
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DMAC->SWTRIGCTRL.reg |= (1 << channel);
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}
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#else
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// enable channel and transfer error + complete interrupts
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DMAC->CHINTENSET.bit.TERR = 1;
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DMAC->CHINTENSET.bit.TCMPL = 1;
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DMAC->CHCTRLA.bit.ENABLE = 1;
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if (DMAC->CHCTRLB.bit.TRIGSRC == 0) {
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// uses software trigger, so trigger it
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DMAC->SWTRIGCTRL.reg |= (1 << channel);
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}
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#endif
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return 0;
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}
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@ -251,11 +327,32 @@ void DMAClass::onService()
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{
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// get the channel and select it
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int channel = DMAC->INTPEND.bit.ID;
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#if !defined(__SAMD51__)
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DMAC->CHID.bit.ID = channel;
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#endif
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// invalidate the channel
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_descriptors[channel].BTCTRL.bit.VALID = 0;
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#if defined(__SAMD51__)
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if (DMAC->Channel[channel].CHINTFLAG.bit.TERR) {
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// clear the error interrupt and call the error callback if there is one
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DMAC->Channel[channel].CHINTFLAG.bit.TERR = 1;
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if (_transferErrorCallbacks[channel]) {
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_transferErrorCallbacks[channel](channel);
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}
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}
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if (DMAC->Channel[channel].CHINTFLAG.bit.TCMPL) {
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// clear the complete interrupt and call the callback if there is one
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DMAC->Channel[channel].CHINTFLAG.bit.TCMPL = 1;
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if (_transferCompleteCallbacks[channel]) {
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_transferCompleteCallbacks[channel](channel);
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}
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}
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#else
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if (DMAC->CHINTFLAG.bit.TERR) {
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// clear the error interrupt and call the error callback if there is one
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DMAC->CHINTFLAG.bit.TERR = 1;
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@ -273,12 +370,55 @@ void DMAClass::onService()
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_transferCompleteCallbacks[channel](channel);
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}
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}
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#endif
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}
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extern "C" {
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#if defined(__SAMD51__)
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static void _dmac_handler(void)
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{
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DMA.onService();
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}
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/**
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* \brief DMAC interrupt handler
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*/
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void DMAC_0_Handler(void)
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{
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_dmac_handler();
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}
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/**
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* \brief DMAC interrupt handler
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*/
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void DMAC_1_Handler(void)
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{
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_dmac_handler();
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}
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/**
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* \brief DMAC interrupt handler
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*/
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void DMAC_2_Handler(void)
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{
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_dmac_handler();
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}
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/**
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* \brief DMAC interrupt handler
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*/
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void DMAC_3_Handler(void)
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{
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_dmac_handler();
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}
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/**
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* \brief DMAC interrupt handler
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*/
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void DMAC_4_Handler(void)
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{
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_dmac_handler();
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}
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#else
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void DMAC_Handler() {
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DMA.onService();
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}
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#endif
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}
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DMAClass DMA;
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@ -17,7 +17,11 @@
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*/
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#pragma once
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#if defined(__SAMD51__)
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#define NUM_DMA_CHANNELS 4
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#else
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#define NUM_DMA_CHANNELS 1
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#endif
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/*
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WARNING: The API for this class may change and it's not intended for public use!
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229
libraries/I2S/src/utility/SAMD51_I2SDevice.h
Normal file
229
libraries/I2S/src/utility/SAMD51_I2SDevice.h
Normal file
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@ -0,0 +1,229 @@
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/*
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Copyright (c) 2016 Arduino LLC. 2017 Adafruit All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#pragma once
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#include <Arduino.h>
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class I2SDevice_SAMD51 {
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public:
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I2SDevice_SAMD51(I2s& _i2s) :
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i2s(_i2s)
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{
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// Empty
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}
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inline void reset() {
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while(i2s.SYNCBUSY.bit.SWRST);
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i2s.CTRLA.bit.SWRST = 1;
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}
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inline void disable() {
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while(i2s.SYNCBUSY.bit.ENABLE);
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i2s.CTRLA.bit.ENABLE = 0;
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}
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inline void enable() {
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while(i2s.SYNCBUSY.bit.ENABLE);
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i2s.CTRLA.bit.ENABLE = 1;
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}
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inline int glckId(int index) {
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return (index == 0) ? I2S_GCLK_ID_0 : I2S_GCLK_ID_1;
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}
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inline void setSerialClockSelectMasterClockDiv(int index) {
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i2s.CLKCTRL[index].bit.SCKSEL = I2S_CLKCTRL_SCKSEL_MCKDIV_Val;
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}
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inline void setSerialClockSelectPin(int index) {
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i2s.CLKCTRL[index].bit.SCKSEL = I2S_CLKCTRL_SCKSEL_SCKPIN_Val;
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}
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inline void setFrameSyncSelectSerialClockDiv(int index) {
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i2s.CLKCTRL[index].bit.FSSEL = I2S_CLKCTRL_FSSEL_SCKDIV_Val;
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}
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inline void setFrameSyncSelectPin(int index) {
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i2s.CLKCTRL[index].bit.FSSEL = I2S_CLKCTRL_FSSEL_FSPIN_Val;
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}
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inline void set0BitDelay(int index) {
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i2s.CLKCTRL[index].bit.BITDELAY = I2S_CLKCTRL_BITDELAY_LJ_Val;
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}
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inline void set1BitDelay(int index) {
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i2s.CLKCTRL[index].bit.BITDELAY = I2S_CLKCTRL_BITDELAY_I2S_Val;
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}
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inline void setNumberOfSlots(int index, int nbslots) {
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i2s.CLKCTRL[index].bit.NBSLOTS = nbslots;
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}
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inline void setSlotSize(int index, int size) {
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switch (size) {
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case 32:
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i2s.CLKCTRL[index].bit.SLOTSIZE = I2S_CLKCTRL_SLOTSIZE_32_Val;
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break;
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case 24:
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i2s.CLKCTRL[index].bit.SLOTSIZE = I2S_CLKCTRL_SLOTSIZE_24_Val;
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break;
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case 16:
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i2s.CLKCTRL[index].bit.SLOTSIZE = I2S_CLKCTRL_SLOTSIZE_16_Val;
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break;
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case 8:
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i2s.CLKCTRL[index].bit.SLOTSIZE = I2S_CLKCTRL_SLOTSIZE_8_Val;
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break;
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}
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}
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inline void setDataSize(int index, int size) {
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switch (size) {
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case 32:
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i2s.RXCTRL.bit.DATASIZE = I2S_RXCTRL_DATASIZE_32_Val;
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i2s.TXCTRL.bit.DATASIZE = I2S_TXCTRL_DATASIZE_32_Val;
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break;
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case 24:
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i2s.RXCTRL.bit.DATASIZE = I2S_RXCTRL_DATASIZE_24_Val;
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i2s.TXCTRL.bit.DATASIZE = I2S_TXCTRL_DATASIZE_24_Val;
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break;
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case 16:
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i2s.RXCTRL.bit.DATASIZE = I2S_RXCTRL_DATASIZE_16_Val;
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i2s.TXCTRL.bit.DATASIZE = I2S_TXCTRL_DATASIZE_16_Val;
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break;
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case 8:
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i2s.RXCTRL.bit.DATASIZE = I2S_RXCTRL_DATASIZE_8_Val;
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i2s.TXCTRL.bit.DATASIZE = I2S_TXCTRL_DATASIZE_8_Val;
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break;
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}
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}
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inline void setSlotAdjustedRight(int index) {
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i2s.RXCTRL.bit.SLOTADJ = I2S_RXCTRL_SLOTADJ_RIGHT_Val;
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i2s.TXCTRL.bit.SLOTADJ = I2S_TXCTRL_SLOTADJ_RIGHT_Val;
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}
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inline void setSlotAdjustedLeft(int index) {
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i2s.RXCTRL.bit.SLOTADJ = I2S_RXCTRL_SLOTADJ_LEFT_Val;
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i2s.TXCTRL.bit.SLOTADJ = I2S_TXCTRL_SLOTADJ_LEFT_Val;
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}
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inline void setClockUnit(int index) {
|
||||
i2s.RXCTRL.bit.CLKSEL = (index == 0) ? I2S_RXCTRL_CLKSEL_CLK0_Val : I2S_RXCTRL_CLKSEL_CLK1_Val;
|
||||
}
|
||||
|
||||
inline void setTxMode(int index) {
|
||||
i2s.RXCTRL.bit.SERMODE = 0x01;
|
||||
i2s.TXCTRL.reg &= ~(0x03); //TODO: why is this not in CMSIS...
|
||||
i2s.TXCTRL.reg |= 0x01;
|
||||
}
|
||||
|
||||
inline void setRxMode(int index) {
|
||||
i2s.RXCTRL.bit.SERMODE = 0x00;
|
||||
i2s.TXCTRL.reg &= ~(0x03); //TODO: why is this not in CMSIS...
|
||||
i2s.TXCTRL.reg |= 0x00;
|
||||
}
|
||||
|
||||
inline void enableClockUnit(int index) {
|
||||
if (index == 0) {
|
||||
while(i2s.SYNCBUSY.bit.CKEN0);
|
||||
i2s.CTRLA.bit.CKEN0 = 1;
|
||||
} else {
|
||||
while(i2s.SYNCBUSY.bit.CKEN1);
|
||||
i2s.CTRLA.bit.CKEN1 = 1;
|
||||
}
|
||||
}
|
||||
|
||||
inline void disableClockUnit(int index) {
|
||||
if (index == 0) {
|
||||
while(i2s.SYNCBUSY.bit.CKEN0);
|
||||
i2s.CTRLA.bit.CKEN0 = 0;
|
||||
} else {
|
||||
while(i2s.SYNCBUSY.bit.CKEN1);
|
||||
i2s.CTRLA.bit.CKEN1 = 0;
|
||||
}
|
||||
}
|
||||
|
||||
inline void enableSerializer(int index) {
|
||||
i2s.CTRLA.bit.RXEN = 1;
|
||||
i2s.CTRLA.bit.TXEN = 1;
|
||||
}
|
||||
|
||||
inline void disableSerializer(int index) {
|
||||
i2s.CTRLA.bit.RXEN = 0;
|
||||
i2s.CTRLA.bit.TXEN = 0;
|
||||
}
|
||||
|
||||
inline int dmaTriggerSource(int index) {
|
||||
/*
|
||||
if (i2s.SERCTRL[index].bit.SERMODE == I2S_SERCTRL_SERMODE_TX_Val) {
|
||||
return (index == 0) ? I2S_DMAC_ID_TX_0 : I2S_DMAC_ID_TX_1;
|
||||
} else {
|
||||
return (index == 0) ? I2S_DMAC_ID_RX_0 : I2S_DMAC_ID_RX_1;
|
||||
}
|
||||
*/
|
||||
}
|
||||
|
||||
inline int txReady(int index) {
|
||||
return (index == 0) ? i2s.INTFLAG.bit.TXRDY0 :i2s.INTFLAG.bit.TXRDY1;
|
||||
}
|
||||
|
||||
inline void writeData(int index, int32_t value) {
|
||||
while (i2s.SYNCBUSY.bit.TXDATA);
|
||||
|
||||
i2s.TXDATA.bit.DATA = value;
|
||||
}
|
||||
|
||||
inline void clearTxReady(int index) {
|
||||
if (index == 0) {
|
||||
i2s.INTFLAG.bit.TXRDY0 = 1;
|
||||
} else {
|
||||
i2s.INTFLAG.bit.TXRDY1 = 1;
|
||||
}
|
||||
}
|
||||
|
||||
inline int rxReady(int index) {
|
||||
return (index == 0) ? i2s.INTFLAG.bit.RXRDY0 :i2s.INTFLAG.bit.RXRDY1;
|
||||
}
|
||||
|
||||
inline int32_t readData(int index) {
|
||||
while(i2s.SYNCBUSY.bit.RXDATA)
|
||||
return i2s.RXDATA.bit.DATA;
|
||||
}
|
||||
|
||||
inline void clearRxReady(int index) {
|
||||
if (index == 0) {
|
||||
i2s.INTFLAG.bit.RXRDY0 = 1;
|
||||
} else {
|
||||
i2s.INTFLAG.bit.RXRDY1 = 1;
|
||||
}
|
||||
}
|
||||
|
||||
inline void* data(int index) {
|
||||
return (void*)&i2s.RXDATA.reg;
|
||||
}
|
||||
|
||||
private:
|
||||
volatile I2s &i2s;
|
||||
};
|
||||
|
|
@ -191,9 +191,9 @@ static const uint8_t SCL = PIN_WIRE_SCL;
|
|||
#define I2S_CLOCK_GENERATOR 3
|
||||
|
||||
//TODO: these
|
||||
#define PIN_I2S_SD (9u)
|
||||
#define PIN_I2S_SCK (1u)
|
||||
#define PIN_I2S_FS (0u)
|
||||
#define PIN_I2S_SD (13u)
|
||||
#define PIN_I2S_SCK (3u)
|
||||
#define PIN_I2S_FS (12u)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue