dean
45013af3a3
DM: updates for m4 mega
2018-11-19 13:38:51 -05:00
dean
87eae6f55c
DM: add copyrights
2018-08-30 15:12:51 -04:00
dean
4c1bca832e
DM: update sercom IRQs for M4
2018-08-30 14:56:11 -04:00
dean
850c490a53
DM: fixed dpll1 freq
2018-08-30 14:56:11 -04:00
dean
33e58f40c4
DM: fixed SERCOM baud rates
2018-08-30 14:55:41 -04:00
dean
c1827b289d
DM: added support for samd51J20A
2018-08-30 14:46:42 -04:00
dean
b5c2b6483b
DM: clocked to 120MHZ, peripherals to 100, USB to 48
2018-08-30 14:44:35 -04:00
ladyada
03eae9b5c5
Add Gemma m0 - tested just about everything
2018-08-30 14:34:13 -04:00
dean
358b11addd
DM: added samd51 support
2018-08-30 14:32:21 -04:00
Sandeep Mistry
a62ef2633b
UART frame error handling
2018-08-17 16:37:47 -04:00
Sandeep Mistry
b753095e56
Correct I2C frequency calculation formula
...
Allow variant to override the default rise time in nanoseconds via
define
2018-01-25 11:31:04 -05:00
Sandeep Mistry
a7c33fea4b
UART: manually handle IRQ if DRE + interrupts disabled or in higher priority ISR
...
When write is called and TX buffer is full.
2018-01-25 11:27:16 -05:00
Mitchell Pontague
ee913a0828
samd21e sercom compatibility ( #280 )
...
Make sercom4 and sercom5 optional to allow compilation of samd21e variants.
2018-01-25 11:25:58 -05:00
agdl
8f5e2eb58c
Changed boradcast variable to enableGeneralCall
2017-12-15 09:06:48 -05:00
agdl
6a1295459b
Allow General Calls on I2C bus (aka brodcast)
2017-12-15 09:06:48 -05:00
Kees Bakker
fd15a1c603
Avoid read-modify-write when enabling SERCOM DRE interrupt
2017-12-11 08:55:04 -05:00
Sandeep Mistry
af14b97ee2
Use port manipulation instead of SERCOM h/w for UART RTS
2017-11-29 13:49:13 +01:00
Sandeep Mistry
7fc402f3b5
Leverage SERCOM h/w functionality for RTS and CTS
2017-11-29 13:49:13 +01:00
Sandeep Mistry
12b3774c3f
Use reg instead of bit to enable/disable the DRE interrupt
...
The RXC interrupt was being disabled when using bit to disable the DRE
interrupt.
2017-07-11 12:58:15 +02:00
Sandeep Mistry
158df98d0c
Correct disableDataRegisterEmptyInterruptUART to use INTENCLR instead of INTENSET
2017-07-11 12:58:15 +02:00
Sandeep Mistry
57c432e688
Add enable and disable data register interrupt APIs for UART
2017-07-11 12:51:58 +02:00
Sandeep Mistry
a15d190ada
Add support for updating sketches from an SD card
...
Via 2nd stage boot code that checks SD card for UPDATE.bin
2017-02-15 15:31:18 -05:00
Sandeep Mistry
e77ae8fe8e
Optimize SPI transfers
2016-11-17 17:17:05 -05:00
Sandeep Mistry
e5166fb922
Use TX buffer for slave writes, empty on master read mode + DRDY IRQ
2016-06-17 09:55:49 -04:00
Sandeep Mistry
1634b5e0cb
Code styling for #144
2016-05-30 11:55:47 -04:00
rocketscream
bfd2a0bb28
Fix Serial.flush() blocking if called immediately after Serial.begin().
2016-05-30 11:54:18 -04:00
Sandeep Mistry
2a37de989a
Correct use of I2C slave address mask, it should be set to 0 for exact match
2016-01-19 11:38:55 -05:00
Tom Keddie
7fad702687
Change flush semantics to match AVR, fixes https://github.com/arduino/ArduinoCore-samd/issues/82
2016-01-18 11:46:45 +01:00
Cristian Maglie
f763660671
Merge branch 'wire-master-repeated-starts' of https://github.com/sandeepmistry/ArduinoCore-samd
2016-01-13 11:31:38 +01:00
Sandeep Mistry
20104a6c77
Use asynchronous fractional mode to configure UART
2016-01-05 10:57:32 -05:00
Cristian Maglie
04bda59c48
Merge branch 'Wire-slave' of https://github.com/sandeepmistry/ArduinoCore-samd
2015-11-18 19:01:26 +01:00
Sandeep Mistry
a2949d505f
Wait for idle or bus owner state in startTransmissionWIRE instead of storing repeated start state.
2015-11-18 09:19:04 -05:00
William
b993249630
Add I2C Repeated Start Capability
...
Adjust requestFrom, endTransmission, and startTransmissionWire to handle
repeated starts
2015-11-17 16:00:54 -05:00
Sandeep Mistry
2ceac4411c
Add getDataOrderSPI API to Sercom
2015-11-04 15:05:18 -05:00
Sandeep Mistry
4efe39eb49
Changes to get Wire slave receiver working
2015-09-08 17:47:30 -04:00
Erin Tomson
0bfeec7f4b
Fix two bugs that can cause deadlock conditions when i2c bus errors occur.
...
The first occurs when starting a read transaction from a slave that doesn't respond. The code would wait until the SB (slave on bus) bit is set in the INTFLAGS register, but when a nack occurs that never happens so we're stuck in an infinite loop. The fix is to also look for the MB flag to be set. If it is, issue a stop condition and return.
The second happens when a bus error (ie, an illegal stop condition) occurs while sending data as a master. In that case we are waiting for the MB (master on bus) flag to be set. When a bus error occurs that never happens, so again we end up in an infinite loop. The fix here is to also look for the BUSERR flag to be set. If it is, return an error condition.
2015-07-24 23:08:36 -07:00
Cristian Maglie
49fe43806d
Uart: fix acknowledge of UART errors
...
This fix lock-ups on UART errors (for example when disconnecting
and reconnecting RX/TX wires or if the method Serial.begin is
called while another device is already transmitting).
2015-07-05 13:36:52 +02:00
Thibaut VIARD
8e2a8cbc99
Adding a test on serial port init
...
Signed-off-by: Thibaut VIARD <thibaut.viard@atmel.com>
2014-10-14 16:16:27 +02:00
Cristian Maglie
5f849abcc8
Fixed some warnings
2014-10-08 11:08:30 +02:00
Thibaut VIARD
ae42fd1167
Adding license in files, update platform.txt
2014-07-25 17:11:29 +02:00
Jonathan BAUDIN
280bc4e001
Fix SPI
2014-06-05 12:15:20 +02:00
Jonathan BAUDIN
6c67c97fad
Fix Wire bug. First bytes not read.
2014-06-02 16:23:26 +02:00
Jonathan BAUDIN
ff46a3c100
Fixing Wire
2014-05-20 17:34:26 +02:00
Jonathan BAUDIN
ead58260a3
Fix SERCOM Wire, add functions Wire class
2014-05-19 13:24:35 +02:00
Jonathan BAUDIN
8b1d9bfd27
SPI implement tested
2014-05-15 18:10:01 +02:00
Jonathan BAUDIN
e4ab3ba3ef
Few UART corrections, modifiy Variant files
2014-05-15 11:54:59 +02:00
Thibaut VIARD
770d1f85bb
Fixing UART compilation
2014-05-13 00:30:04 +02:00
Jonathan BAUDIN
07e782b2b1
Fix UART EDBG and baudrate
2014-05-12 20:37:59 +02:00
Jonathan BAUDIN
86b6f1060e
UART class usable
2014-05-09 19:51:30 +02:00
Jonathan BAUDIN
3c6f9b55f7
Initialize clock
2014-05-09 14:07:29 +02:00
