146 lines
4.2 KiB
C
146 lines
4.2 KiB
C
/*
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Copyright (c) 2014 Arduino. All right reserved.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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See the GNU Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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//#include "Arduino.h"
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#include "variant.h"
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//#include "wiring_constants.h"
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#include "wiring_digital.h"
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#include "wiring.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* System Core Clock is at 1MHz at Reset.
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* It is switched to 48MHz in the Reset Handler (startup.c)
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*/
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uint32_t SystemCoreClock=1000000ul ;
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/*
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void calibrateADC()
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{
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volatile uint32_t valeur = 0;
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for(int i = 0; i < 5; ++i)
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{
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ADC->SWTRIG.bit.START = 1;
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while( ADC->INTFLAG.bit.RESRDY == 0 || ADC->STATUS.bit.SYNCBUSY == 1 )
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{
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// Waiting for a complete conversion and complete synchronization
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}
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valeur += ADC->RESULT.bit.RESULT;
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}
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valeur = valeur/5;
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}*/
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/*
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* Arduino Zero board initialization
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*
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* Good to know:
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* - At reset, ResetHandler did the system clock configuration. Core is running at 48MHz.
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* - Watchdog is disabled by default, unless someone plays with NVM User page
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* - During reset, all PORT lines are configured as inputs with input buffers, output buffers and pull disabled.
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*/
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void init( void )
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{
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uint32_t ul ;
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// Set Systick to 1ms interval, common to all Cortex-M variants
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if ( SysTick_Config( SystemCoreClock / 1000 ) )
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{
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// Capture error
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while ( 1 ) ;
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}
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// Clock PORT for Digital I/O
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// PM->APBBMASK.reg |= PM_APBBMASK_PORT ;
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//
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// // Clock EIC for I/O interrupts
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// PM->APBAMASK.reg |= PM_APBAMASK_EIC ;
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// Clock SERCOM for Serial
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PM->APBCMASK.reg |= PM_APBCMASK_SERCOM0 | PM_APBCMASK_SERCOM1 | PM_APBCMASK_SERCOM2 | PM_APBCMASK_SERCOM3 | PM_APBCMASK_SERCOM4 | PM_APBCMASK_SERCOM5 ;
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// Clock TC/TCC for Pulse and Analog
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PM->APBCMASK.reg |= PM_APBCMASK_TCC0 | PM_APBCMASK_TCC1 | PM_APBCMASK_TCC2 | PM_APBCMASK_TC3 | PM_APBCMASK_TC4 | PM_APBCMASK_TC5 | PM_APBCMASK_TC6 | PM_APBCMASK_TC7 ;
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// Clock ADC/DAC for Analog
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PM->APBCMASK.reg |= PM_APBCMASK_ADC | PM_APBCMASK_DAC ;
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// Setup all pins (digital and analog) in INPUT mode (default is nothing)
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for ( ul = 0 ; ul < NUM_DIGITAL_PINS ; ul++ )
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{
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pinMode( ul, INPUT ) ;
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}
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// Initialize Serial port U(S)ART pins
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// Todo
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// Initialize USB pins
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// Todo
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// Initialize Analog Controller
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// Setting clock
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_ADC ) | // Generic Clock ADC
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GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
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GCLK_CLKCTRL_CLKEN ;
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ADC->CTRLB.reg = ADC_CTRLB_PRESCALER_DIV128 | // Divide Clock by 512.
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ADC_CTRLB_RESSEL_10BIT; // Result on 10 bits
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ADC->INPUTCTRL.reg = ADC_INPUTCTRL_MUXNEG_GND; // No Negative input (Internal Ground)
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// Averaging (see table 31-2 p.816 datasheet)
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ADC->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM_2 | // 2 samples
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ADC_AVGCTRL_ADJRES(0x01ul); // Adjusting result by 1
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ADC->REFCTRL.reg = ADC_REFCTRL_REFSEL_AREFA; // RReference AREFA (pin AREF) [default]
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ADC->CTRLA.bit.ENABLE = 1; // Enable ADC
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while( ADC->STATUS.bit.SYNCBUSY == 1 )
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{
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// Waiting for synchroinization
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}
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// Initialize DAC
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// Setting clock
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID( GCM_DAC ) | // Generic Clock ADC
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GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is source
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GCLK_CLKCTRL_CLKEN ;
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DAC->CTRLB.reg = DAC_CTRLB_REFSEL_AVCC | // Using the 3.3V reference
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DAC_CTRLB_EOEN; // External Output Enable (Vout)
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DAC->DATA.reg = 0x3FFul;
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// Enable DAC
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DAC->CTRLA.bit.ENABLE = 1;
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while(DAC->STATUS.bit.SYNCBUSY != 0)
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{
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// Waiting for synchronization
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}
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}
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#ifdef __cplusplus
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}
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#endif
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