From ef0ba3be8af17862792f5ec204390801da27c0f7 Mon Sep 17 00:00:00 2001 From: jean-marcharvengt Date: Sun, 24 Nov 2019 15:48:57 +0100 Subject: [PATCH] add gameboy, sms and genesis emus --- MCUME_teensy/teensycastaway/diskapi.h | 9 + MCUME_teensy/teensycastaway/emuapi.cpp | 270 +- MCUME_teensy/teensycastaway/emuapi.h | 23 +- MCUME_teensy/teensycastaway/fdc.cpp | 17 +- MCUME_teensy/teensycastaway/iopins.h | 24 +- MCUME_teensy/teensycastaway/psram_t.cpp | 301 + MCUME_teensy/teensycastaway/psram_t.h | 45 + MCUME_teensy/teensycastaway/sound.cpp | 100 +- MCUME_teensy/teensycastaway/sound.h | 2 +- MCUME_teensy/teensycastaway/test.cpp | 119 +- MCUME_teensy/teensycastaway/tft_t_dma.cpp | 3 +- .../teensygen}/.DS_Store | Bin MCUME_teensy/teensygen/AudioPlaySystem.cpp | 196 + MCUME_teensy/teensygen/AudioPlaySystem.h | 28 + MCUME_teensy/teensygen/arduinoproto.h | 7 + MCUME_teensy/teensygen/cpuintrf.h | 30 + MCUME_teensy/teensygen/emu.cpp | 173 + MCUME_teensy/teensygen/emu.h | 5 + MCUME_teensy/teensygen/emuapi.cpp | 1196 + MCUME_teensy/teensygen/emuapi.h | 152 + MCUME_teensy/teensygen/fm.c | 1495 + MCUME_teensy/teensygen/fm.h | 181 + MCUME_teensy/teensygen/font8x8.h | 135 + MCUME_teensy/teensygen/genesis.c | 160 + MCUME_teensy/teensygen/genesis.h | 28 + MCUME_teensy/teensygen/genlut.h | 20483 +++++ MCUME_teensy/teensygen/hcnt.h | 69 + MCUME_teensy/teensygen/hvc.h | 193 + MCUME_teensy/teensygen/io.c | 186 + MCUME_teensy/teensygen/io.h | 36 + MCUME_teensy/teensygen/iopins.h | 98 + MCUME_teensy/teensygen/keyboard_osd.h | 20 + MCUME_teensy/teensygen/logo.h | 241 + MCUME_teensy/teensygen/m68k.h | 339 + MCUME_teensy/teensygen/m68kconf.h | 183 + MCUME_teensy/teensygen/m68kcpu.c | 895 + MCUME_teensy/teensygen/m68kcpu.h | 1839 + MCUME_teensy/teensygen/m68kopac.c | 11948 +++ MCUME_teensy/teensygen/m68kopdm.c | 13286 +++ MCUME_teensy/teensygen/m68kopnz.c | 8746 ++ MCUME_teensy/teensygen/m68kops.c | 4101 + MCUME_teensy/teensygen/m68kops.h | 1984 + MCUME_teensy/teensygen/m68kops_pre.c | 65546 +++++++++++++++ MCUME_teensy/teensygen/macros.h | 24 + MCUME_teensy/teensygen/mem68k.c | 715 + MCUME_teensy/teensygen/mem68k.h | 15 + MCUME_teensy/teensygen/membnk.c | 327 + MCUME_teensy/teensygen/membnk.h | 17 + MCUME_teensy/teensygen/memory.c | 47 + MCUME_teensy/teensygen/memory.h | 35 + MCUME_teensy/teensygen/memvdp.c | 54 + MCUME_teensy/teensygen/memvdp.h | 8 + MCUME_teensy/teensygen/memz80.c | 250 + MCUME_teensy/teensygen/memz80.h | 17 + MCUME_teensy/teensygen/musashi34/m68k.h | 358 + MCUME_teensy/teensygen/musashi34/m68kconf.h | 189 + MCUME_teensy/teensygen/musashi34/m68kcpu.c | 882 + MCUME_teensy/teensygen/musashi34/m68kcpu.h | 1986 + MCUME_teensy/teensygen/musashi34/m68kdasm.c | 3477 + MCUME_teensy/teensygen/musashi34/m68kopac.c | 12062 +++ MCUME_teensy/teensygen/musashi34/m68kopdm.c | 13223 +++ MCUME_teensy/teensygen/musashi34/m68kopnz.c | 8817 ++ MCUME_teensy/teensygen/musashi34/m68kops.h | 1988 + .../teensygen/musashi34/m68kops_pre.c | 69644 ++++++++++++++++ MCUME_teensy/teensygen/osd_cpu.h | 70 + MCUME_teensy/teensygen/psram_t.cpp | 356 + MCUME_teensy/teensygen/psram_t.h | 46 + MCUME_teensy/teensygen/render.c | 1047 + MCUME_teensy/teensygen/render.h | 40 + MCUME_teensy/teensygen/shared.h | 53 + MCUME_teensy/teensygen/sn76496.c | 273 + MCUME_teensy/teensygen/sn76496.h | 21 + MCUME_teensy/teensygen/sound.c | 170 + MCUME_teensy/teensygen/sound.h | 30 + MCUME_teensy/teensygen/system.c | 256 + MCUME_teensy/teensygen/system.h | 85 + MCUME_teensy/teensygen/teensygen.ino | 279 + MCUME_teensy/teensygen/tft_t_dma.cpp | 1182 + MCUME_teensy/teensygen/tft_t_dma.h | 233 + MCUME_teensy/teensygen/tft_t_dma_config.h | 10 + MCUME_teensy/teensygen/vcnt.h | 28 + MCUME_teensy/teensygen/vdp.c | 557 + MCUME_teensy/teensygen/vdp.h | 53 + MCUME_teensy/teensygen/z80.c | 4514 + MCUME_teensy/teensygen/z80.h | 62 + MCUME_teensy/teensygen/z80daa.h | 2053 + MCUME_teensy/teensygnuboy/AudioPlaySystem.cpp | 196 + MCUME_teensy/teensygnuboy/AudioPlaySystem.h | 28 + MCUME_teensy/teensygnuboy/arduinoproto.h | 7 + MCUME_teensy/teensygnuboy/cpu.c | 877 + MCUME_teensy/teensygnuboy/cpu.h | 37 + MCUME_teensy/teensygnuboy/cpucore.h | 291 + MCUME_teensy/teensygnuboy/cpuregs.h | 56 + MCUME_teensy/teensygnuboy/defs.h | 47 + MCUME_teensy/teensygnuboy/emu.cpp | 157 + MCUME_teensy/teensygnuboy/emu.h | 5 + MCUME_teensy/teensygnuboy/emuapi.cpp | 1196 + MCUME_teensy/teensygnuboy/emuapi.h | 152 + MCUME_teensy/teensygnuboy/font8x8.h | 135 + MCUME_teensy/teensygnuboy/hw.c | 181 + MCUME_teensy/teensygnuboy/hw.h | 41 + MCUME_teensy/teensygnuboy/iopins.h | 98 + MCUME_teensy/teensygnuboy/keyboard_osd.h | 20 + MCUME_teensy/teensygnuboy/lcd.c | 683 + MCUME_teensy/teensygnuboy/lcd.h | 57 + MCUME_teensy/teensygnuboy/lcdc.c | 172 + MCUME_teensy/teensygnuboy/loader.c | 125 + MCUME_teensy/teensygnuboy/loader.h | 9 + MCUME_teensy/teensygnuboy/logo.h | 241 + MCUME_teensy/teensygnuboy/mem.c | 578 + MCUME_teensy/teensygnuboy/mem.h | 121 + MCUME_teensy/teensygnuboy/memory.c | 39 + MCUME_teensy/teensygnuboy/memory.h | 16 + MCUME_teensy/teensygnuboy/noise.h | 533 + MCUME_teensy/teensygnuboy/psram_t.cpp | 356 + MCUME_teensy/teensygnuboy/psram_t.h | 46 + MCUME_teensy/teensygnuboy/rc.h | 63 + MCUME_teensy/teensygnuboy/regs.h | 181 + MCUME_teensy/teensygnuboy/rtc.c | 101 + MCUME_teensy/teensygnuboy/rtc.h | 26 + MCUME_teensy/teensygnuboy/shared.h | 9 + MCUME_teensy/teensygnuboy/sound.c | 582 + MCUME_teensy/teensygnuboy/sound.h | 38 + MCUME_teensy/teensygnuboy/teensygnuboy.ino | 279 + MCUME_teensy/teensygnuboy/tft_t_dma.cpp | 1182 + MCUME_teensy/teensygnuboy/tft_t_dma.h | 233 + MCUME_teensy/teensygnuboy/tft_t_dma_config.h | 10 + MCUME_teensy/teensylogo/tft_t_dma.cpp | 2 +- MCUME_teensy/teensypce/emuapi.cpp | 3 +- MCUME_teensy/teensypce/psram_t.cpp | 93 +- MCUME_teensy/teensypce/psram_t.h | 3 +- MCUME_teensy/teensypce/tft_t_dma.cpp | 45 +- MCUME_teensy/teensypce/tft_t_dma.h | 1 + MCUME_teensy/{ => teensysms}/.DS_Store | Bin 6148 -> 6148 bytes MCUME_teensy/teensysms/AudioPlaySystem.cpp | 196 + MCUME_teensy/teensysms/AudioPlaySystem.h | 28 + MCUME_teensy/teensysms/arduinoproto.h | 7 + MCUME_teensy/teensysms/cpuintrf.h | 383 + MCUME_teensy/teensysms/emu.cpp | 159 + MCUME_teensy/teensysms/emu.h | 5 + MCUME_teensy/teensysms/emuapi.cpp | 1196 + MCUME_teensy/teensysms/emuapi.h | 152 + MCUME_teensy/teensysms/fmopl.c | 1319 + MCUME_teensy/teensysms/fmopl.h | 142 + MCUME_teensy/teensysms/font8x8.h | 135 + MCUME_teensy/teensysms/iopins.h | 98 + MCUME_teensy/teensysms/keyboard_osd.h | 20 + MCUME_teensy/teensysms/logo.h | 241 + MCUME_teensy/teensysms/memory.c | 25 + MCUME_teensy/teensysms/memory.h | 22 + MCUME_teensy/teensysms/psram_t.cpp | 356 + MCUME_teensy/teensysms/psram_t.h | 46 + MCUME_teensy/teensysms/render.c | 512 + MCUME_teensy/teensysms/render.h | 23 + MCUME_teensy/teensysms/shared.h | 60 + MCUME_teensy/teensysms/sms.c | 316 + MCUME_teensy/teensysms/sms.h | 36 + MCUME_teensy/teensysms/smslut.h | 4099 + MCUME_teensy/teensysms/sn76496.c | 245 + MCUME_teensy/teensysms/sn76496.h | 30 + MCUME_teensy/teensysms/system.c | 231 + MCUME_teensy/teensysms/system.h | 92 + MCUME_teensy/teensysms/teensysms.ino | 279 + MCUME_teensy/teensysms/tft_t_dma.cpp | 1182 + MCUME_teensy/teensysms/tft_t_dma.h | 233 + MCUME_teensy/teensysms/tft_t_dma_config.h | 10 + MCUME_teensy/teensysms/vdp.c | 297 + MCUME_teensy/teensysms/vdp.h | 45 + MCUME_teensy/teensysms/ym2413.c | 397 + MCUME_teensy/teensysms/ym2413.h | 33 + MCUME_teensy/teensysms/z80.c | 4390 + MCUME_teensy/teensysms/z80.h | 76 + MCUME_teensy/teensysms/z80daa.h | 2052 + .../atmegai2ckeyboard/atmegai2ckeyboard.ino | 253 +- images/teensy4SD.png | Bin 4611909 -> 456073 bytes 175 files changed, 288962 insertions(+), 255 deletions(-) create mode 100644 MCUME_teensy/teensycastaway/diskapi.h create mode 100644 MCUME_teensy/teensycastaway/psram_t.cpp create mode 100644 MCUME_teensy/teensycastaway/psram_t.h rename {i2ckeyboard => MCUME_teensy/teensygen}/.DS_Store (100%) create mode 100644 MCUME_teensy/teensygen/AudioPlaySystem.cpp create mode 100644 MCUME_teensy/teensygen/AudioPlaySystem.h create mode 100644 MCUME_teensy/teensygen/arduinoproto.h create mode 100644 MCUME_teensy/teensygen/cpuintrf.h create mode 100644 MCUME_teensy/teensygen/emu.cpp create mode 100644 MCUME_teensy/teensygen/emu.h create mode 100644 MCUME_teensy/teensygen/emuapi.cpp create mode 100644 MCUME_teensy/teensygen/emuapi.h create mode 100644 MCUME_teensy/teensygen/fm.c create mode 100644 MCUME_teensy/teensygen/fm.h create mode 100644 MCUME_teensy/teensygen/font8x8.h create mode 100644 MCUME_teensy/teensygen/genesis.c create mode 100644 MCUME_teensy/teensygen/genesis.h create mode 100644 MCUME_teensy/teensygen/genlut.h create mode 100644 MCUME_teensy/teensygen/hcnt.h create mode 100644 MCUME_teensy/teensygen/hvc.h create mode 100644 MCUME_teensy/teensygen/io.c create mode 100644 MCUME_teensy/teensygen/io.h create mode 100644 MCUME_teensy/teensygen/iopins.h create mode 100644 MCUME_teensy/teensygen/keyboard_osd.h create mode 100644 MCUME_teensy/teensygen/logo.h create mode 100644 MCUME_teensy/teensygen/m68k.h create mode 100644 MCUME_teensy/teensygen/m68kconf.h create mode 100644 MCUME_teensy/teensygen/m68kcpu.c create mode 100644 MCUME_teensy/teensygen/m68kcpu.h create mode 100644 MCUME_teensy/teensygen/m68kopac.c create mode 100644 MCUME_teensy/teensygen/m68kopdm.c create mode 100644 MCUME_teensy/teensygen/m68kopnz.c create mode 100644 MCUME_teensy/teensygen/m68kops.c create mode 100644 MCUME_teensy/teensygen/m68kops.h create mode 100644 MCUME_teensy/teensygen/m68kops_pre.c create mode 100644 MCUME_teensy/teensygen/macros.h create mode 100644 MCUME_teensy/teensygen/mem68k.c create mode 100644 MCUME_teensy/teensygen/mem68k.h create mode 100644 MCUME_teensy/teensygen/membnk.c create mode 100644 MCUME_teensy/teensygen/membnk.h create mode 100644 MCUME_teensy/teensygen/memory.c create mode 100644 MCUME_teensy/teensygen/memory.h create mode 100644 MCUME_teensy/teensygen/memvdp.c create mode 100644 MCUME_teensy/teensygen/memvdp.h create mode 100644 MCUME_teensy/teensygen/memz80.c create mode 100644 MCUME_teensy/teensygen/memz80.h create mode 100644 MCUME_teensy/teensygen/musashi34/m68k.h create mode 100644 MCUME_teensy/teensygen/musashi34/m68kconf.h create mode 100644 MCUME_teensy/teensygen/musashi34/m68kcpu.c create mode 100644 MCUME_teensy/teensygen/musashi34/m68kcpu.h create mode 100644 MCUME_teensy/teensygen/musashi34/m68kdasm.c create mode 100644 MCUME_teensy/teensygen/musashi34/m68kopac.c create mode 100644 MCUME_teensy/teensygen/musashi34/m68kopdm.c create mode 100644 MCUME_teensy/teensygen/musashi34/m68kopnz.c create mode 100644 MCUME_teensy/teensygen/musashi34/m68kops.h create mode 100644 MCUME_teensy/teensygen/musashi34/m68kops_pre.c create mode 100644 MCUME_teensy/teensygen/osd_cpu.h create mode 100644 MCUME_teensy/teensygen/psram_t.cpp create mode 100644 MCUME_teensy/teensygen/psram_t.h create mode 100644 MCUME_teensy/teensygen/render.c create mode 100644 MCUME_teensy/teensygen/render.h create mode 100644 MCUME_teensy/teensygen/shared.h create mode 100644 MCUME_teensy/teensygen/sn76496.c create mode 100644 MCUME_teensy/teensygen/sn76496.h create mode 100644 MCUME_teensy/teensygen/sound.c create mode 100644 MCUME_teensy/teensygen/sound.h create mode 100644 MCUME_teensy/teensygen/system.c create mode 100644 MCUME_teensy/teensygen/system.h create mode 100644 MCUME_teensy/teensygen/teensygen.ino create mode 100644 MCUME_teensy/teensygen/tft_t_dma.cpp create mode 100644 MCUME_teensy/teensygen/tft_t_dma.h create mode 100644 MCUME_teensy/teensygen/tft_t_dma_config.h create mode 100644 MCUME_teensy/teensygen/vcnt.h create mode 100644 MCUME_teensy/teensygen/vdp.c create mode 100644 MCUME_teensy/teensygen/vdp.h create mode 100644 MCUME_teensy/teensygen/z80.c create mode 100644 MCUME_teensy/teensygen/z80.h create mode 100644 MCUME_teensy/teensygen/z80daa.h create mode 100644 MCUME_teensy/teensygnuboy/AudioPlaySystem.cpp create mode 100644 MCUME_teensy/teensygnuboy/AudioPlaySystem.h create mode 100644 MCUME_teensy/teensygnuboy/arduinoproto.h create mode 100644 MCUME_teensy/teensygnuboy/cpu.c create mode 100644 MCUME_teensy/teensygnuboy/cpu.h create mode 100644 MCUME_teensy/teensygnuboy/cpucore.h create mode 100644 MCUME_teensy/teensygnuboy/cpuregs.h create mode 100644 MCUME_teensy/teensygnuboy/defs.h create mode 100644 MCUME_teensy/teensygnuboy/emu.cpp create mode 100644 MCUME_teensy/teensygnuboy/emu.h create mode 100644 MCUME_teensy/teensygnuboy/emuapi.cpp create mode 100644 MCUME_teensy/teensygnuboy/emuapi.h create mode 100644 MCUME_teensy/teensygnuboy/font8x8.h create mode 100644 MCUME_teensy/teensygnuboy/hw.c create mode 100644 MCUME_teensy/teensygnuboy/hw.h create mode 100644 MCUME_teensy/teensygnuboy/iopins.h create mode 100644 MCUME_teensy/teensygnuboy/keyboard_osd.h create mode 100644 MCUME_teensy/teensygnuboy/lcd.c create mode 100644 MCUME_teensy/teensygnuboy/lcd.h create mode 100644 MCUME_teensy/teensygnuboy/lcdc.c create mode 100644 MCUME_teensy/teensygnuboy/loader.c create mode 100644 MCUME_teensy/teensygnuboy/loader.h create mode 100644 MCUME_teensy/teensygnuboy/logo.h create mode 100644 MCUME_teensy/teensygnuboy/mem.c create mode 100644 MCUME_teensy/teensygnuboy/mem.h create mode 100644 MCUME_teensy/teensygnuboy/memory.c create mode 100644 MCUME_teensy/teensygnuboy/memory.h create mode 100644 MCUME_teensy/teensygnuboy/noise.h create mode 100644 MCUME_teensy/teensygnuboy/psram_t.cpp create mode 100644 MCUME_teensy/teensygnuboy/psram_t.h create mode 100644 MCUME_teensy/teensygnuboy/rc.h create mode 100644 MCUME_teensy/teensygnuboy/regs.h create mode 100644 MCUME_teensy/teensygnuboy/rtc.c create mode 100644 MCUME_teensy/teensygnuboy/rtc.h create mode 100644 MCUME_teensy/teensygnuboy/shared.h create mode 100644 MCUME_teensy/teensygnuboy/sound.c create mode 100644 MCUME_teensy/teensygnuboy/sound.h create mode 100644 MCUME_teensy/teensygnuboy/teensygnuboy.ino create mode 100644 MCUME_teensy/teensygnuboy/tft_t_dma.cpp create mode 100644 MCUME_teensy/teensygnuboy/tft_t_dma.h create mode 100644 MCUME_teensy/teensygnuboy/tft_t_dma_config.h rename MCUME_teensy/{ => teensysms}/.DS_Store (82%) create mode 100644 MCUME_teensy/teensysms/AudioPlaySystem.cpp create mode 100644 MCUME_teensy/teensysms/AudioPlaySystem.h create mode 100644 MCUME_teensy/teensysms/arduinoproto.h create mode 100644 MCUME_teensy/teensysms/cpuintrf.h create mode 100644 MCUME_teensy/teensysms/emu.cpp create mode 100644 MCUME_teensy/teensysms/emu.h create mode 100644 MCUME_teensy/teensysms/emuapi.cpp create mode 100644 MCUME_teensy/teensysms/emuapi.h create mode 100644 MCUME_teensy/teensysms/fmopl.c create mode 100644 MCUME_teensy/teensysms/fmopl.h create mode 100644 MCUME_teensy/teensysms/font8x8.h create mode 100644 MCUME_teensy/teensysms/iopins.h create mode 100644 MCUME_teensy/teensysms/keyboard_osd.h create mode 100644 MCUME_teensy/teensysms/logo.h create mode 100644 MCUME_teensy/teensysms/memory.c create mode 100644 MCUME_teensy/teensysms/memory.h create mode 100644 MCUME_teensy/teensysms/psram_t.cpp create mode 100644 MCUME_teensy/teensysms/psram_t.h create mode 100644 MCUME_teensy/teensysms/render.c create mode 100644 MCUME_teensy/teensysms/render.h create mode 100644 MCUME_teensy/teensysms/shared.h create mode 100644 MCUME_teensy/teensysms/sms.c create mode 100644 MCUME_teensy/teensysms/sms.h create mode 100644 MCUME_teensy/teensysms/smslut.h create mode 100644 MCUME_teensy/teensysms/sn76496.c create mode 100644 MCUME_teensy/teensysms/sn76496.h create mode 100644 MCUME_teensy/teensysms/system.c create mode 100644 MCUME_teensy/teensysms/system.h create mode 100644 MCUME_teensy/teensysms/teensysms.ino create mode 100644 MCUME_teensy/teensysms/tft_t_dma.cpp create mode 100644 MCUME_teensy/teensysms/tft_t_dma.h create mode 100644 MCUME_teensy/teensysms/tft_t_dma_config.h create mode 100644 MCUME_teensy/teensysms/vdp.c create mode 100644 MCUME_teensy/teensysms/vdp.h create mode 100644 MCUME_teensy/teensysms/ym2413.c create mode 100644 MCUME_teensy/teensysms/ym2413.h create mode 100644 MCUME_teensy/teensysms/z80.c create mode 100644 MCUME_teensy/teensysms/z80.h create mode 100644 MCUME_teensy/teensysms/z80daa.h diff --git a/MCUME_teensy/teensycastaway/diskapi.h b/MCUME_teensy/teensycastaway/diskapi.h new file mode 100644 index 0000000..17f333e --- /dev/null +++ b/MCUME_teensy/teensycastaway/diskapi.h @@ -0,0 +1,9 @@ +#ifndef DISKAPI_H +#define DISKAPI_H + +int disk_Size(char * filename); +int disk_Open(char * filename); +int disk_Read(char * buf, int size); +int disk_Seek(int seek); + +#endif \ No newline at end of file diff --git a/MCUME_teensy/teensycastaway/emuapi.cpp b/MCUME_teensy/teensycastaway/emuapi.cpp index f8e270c..e35369c 100644 --- a/MCUME_teensy/teensycastaway/emuapi.cpp +++ b/MCUME_teensy/teensycastaway/emuapi.cpp @@ -7,28 +7,31 @@ #include "tft_t_dma.h" //#include "logo.h" -#//include "bmpjoy.h" -#//include "bmpvbar.h" +//#include "bmpjoy.h" +//#include "bmpvbar.h" //#include "bmpvga.h" //#include "bmptft.h" #ifndef SD_CS -#define USE_SDFAT 1 +#define USE_SDFS 1 #endif #ifdef HAS_I2CKBD #include #endif -#ifdef USE_SDFAT -#include -static SdFatSdio SD; +#ifdef USE_SDFS +#define SDFSDEV "2:" + +#include "uSDFS.h" +static FATFS fatfs; +static FIL file; #else #include +static File file; #endif extern TFT_T_DMA tft; -static File file; static char romspath[64]; static int16_t calMinX=-1,calMinY=-1,calMaxX=-1,calMaxY=-1; static bool i2cKeyboardPresent = false; @@ -36,10 +39,15 @@ const uint16_t deflogo[] = { 0x0000,0x0000 }; static const uint16_t * logo = deflogo; +static unsigned short * keys; +static int keyMap; +#ifdef USE_SDFS +#define CALIBRATION_FILE SDFSDEV "/cal.cfg" +#else #define CALIBRATION_FILE "/cal.cfg" - -#define MAX_FILES 32 +#endif +#define MAX_FILES 128 #define MAX_FILENAME_SIZE 28 #define MAX_MENULINES (MKEY_L9) #define TEXT_HEIGHT 16 @@ -105,11 +113,36 @@ static int topFile=0; static char selection[MAX_FILENAME_SIZE+1]=""; static uint8_t prev_zt=0; - static char files[MAX_FILES][MAX_FILENAME_SIZE]; static int readNbFiles(void) { int totalFiles = 0; + +#ifdef USE_SDFS + DIR dir; + FILINFO entry; + f_opendir(&dir, romspath); + while ( (true) && (totalFiles= 256) { - int retval = file.read(buffer, 256); + int byteread = 0; + int retval=0; + while (remaining>0) { +#ifdef USE_SDFS + if( !(f_read (&file, buffer, 256, &retval)) ) + //f_read (&file, buffer, 256, &retval); +#else + retval = file.read(buffer, 256); +#endif if (retval>0) { + //emu_printi(retval); memcpy(buf,buffer,retval); buf += retval; byteread += retval; remaining -= retval; } - } - if (remaining) { - int retval = file.read(buffer, remaining); - if (retval>0) { - memcpy(buf,buffer,retval); - byteread += retval; + else { + break; } - } + } + return byteread; } unsigned char emu_FileGetc(void) { unsigned char c; +#ifdef USE_SDFS + int retval=0; + if( !(f_read (&file, &c, 1, &retval)) ) +#else int retval = file.read(&c, 1); +#endif if (retval != 1) { emu_printf("emu_FileGetc failed"); } @@ -640,7 +742,11 @@ unsigned char emu_FileGetc(void) { void emu_FileClose(void) { +#ifdef USE_SDFS + f_close(&file); +#else file.close(); +#endif } int emu_FileSize(char * filename) @@ -652,7 +758,11 @@ int emu_FileSize(char * filename) strcat(filepath, filename); emu_printf("FileSize..."); emu_printf(filepath); - +#ifdef USE_SDFS + FILINFO entry; + f_stat(filepath, &entry); + filesize = entry.fsize; +#else if ((file = SD.open(filepath, O_READ))) { emu_printf("filesize is..."); @@ -660,16 +770,31 @@ int emu_FileSize(char * filename) emu_printf(filesize); file.close(); } +#endif return(filesize); } int emu_FileSeek(int seek) { +#ifdef USE_SDFS + f_lseek(&file, seek); +#else file.seek(seek); +#endif return (seek); } +int emu_FileTell(void) +{ +#ifdef USE_SDFS + return (f_tell(&file)); +#else + return (50); +#endif +} + + int emu_LoadFile(char * filename, char * buf, int size) { int filesize = 0; @@ -680,7 +805,20 @@ int emu_LoadFile(char * filename, char * buf, int size) strcat(filepath, filename); emu_printf("LoadFile..."); emu_printf(filepath); - +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { + filesize = f_size(&file); + emu_printf(filesize); + if (size >= filesize) + { + int retval=0; + if( (f_read (&file, buf, filesize, &retval)) ) { + emu_printf("File read failed"); + } + } + f_close(&file); + } +#else if ((file = SD.open(filepath, O_READ))) { filesize = file.size(); @@ -695,6 +833,7 @@ int emu_LoadFile(char * filename, char * buf, int size) } file.close(); } +#endif return(filesize); } @@ -709,7 +848,22 @@ int emu_LoadFileSeek(char * filename, char * buf, int size, int seek) strcat(filepath, filename); emu_printf("LoadFileSeek..."); emu_printf(filepath); - +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { + f_lseek(&file, seek); + emu_printf(size); + if (size >= filesize) + { + int retval=0; + if( (!f_read (&file, buf, size, &retval)) ) + if (retval != size) + { + emu_printf("File read failed"); + } + } + f_close(&file); + } +#else if ((file = SD.open(filepath, O_READ))) { file.seek(seek); @@ -719,6 +873,7 @@ int emu_LoadFileSeek(char * filename, char * buf, int size, int seek) } file.close(); } +#endif return(filesize); } @@ -837,7 +992,7 @@ int emu_ReadKeys(void) if ( digitalRead(PIN_KEY_USER4) == LOW ) retval |= MASK_KEY_USER4; #endif - //Serial.println(retval,HEX); + //Serial.println(j1,HEX); return (retval); } @@ -879,7 +1034,7 @@ int emu_ReadI2CKeyboard(void) { //Serial.println(match,HEX); for (i=0; i #define TITLE " AtariST Emulator " #define ROMSDIR "/st" @@ -55,14 +57,23 @@ const unsigned short keysw[]= //TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, TAREA_END}; -const unsigned short keys[]={ - -59, 60, 61, 62, 63, 64, 65, 66, 67, 68, -109,110,111,112,106,107,108,17,18,19, -20,21,22,23,24,25,26,27,28,29, -30,31,32,33,34,35,36,37,38,57 }; +const unsigned short key_map1[]={ +109, 110, 111, 106, 107, 108, 103, 104, 105, 112, // keypad +16,17,18,19,20,21,22,23,24,25, +30,31,32,33,34,35,36,37,38,28, +44,45,46,47,48,49,50,51,52,57 }; +const unsigned short key_map2[]={ +59, 60, 61, 62, 63, 64, 65, 66, 67, 68, // Function keys +16,17,18,19,20,21,22,23,24,25, +30,31,32,33,34,35,36,37,38,28, +44,45,46,47,48,49,50,51,52,57 }; +const unsigned short key_map3[]={ +2, 3, 4, 5, 6, 7, 8, 9, 10, 11, // digits +16,17,18,19,20,21,22,23,24,25, +30,31,32,33,34,35,36,37,38,28, +44,45,46,47,48,49,50,51,52,57 }; #ifdef HAS_I2CKBD diff --git a/MCUME_teensy/teensycastaway/fdc.cpp b/MCUME_teensy/teensycastaway/fdc.cpp index 71a5b5a..5e9e1f2 100644 --- a/MCUME_teensy/teensycastaway/fdc.cpp +++ b/MCUME_teensy/teensycastaway/fdc.cpp @@ -22,6 +22,7 @@ static char sccsid[] = "$Id: fdc.c,v 1.2 2002/06/08 23:31:58 jhoenig Exp $"; #include "m68k_intrf.h" #include "emuapi.h" +#include "diskapi.h" //#define MEMDISC 1 @@ -110,12 +111,14 @@ PROGMEM int discread(unsigned long address,int a,int len,int discn) #endif #else + LOG("disc read: ",len); uint8 buf[256]; int totlen = len; while (totlen>=256) { //fread(buf,1,256,disk[discn].file); - emu_FileRead(buf,256); + disk_Read(buf,256); + LOG("b read: ",buf[0]); totlen -= 256; for (i=0; i<256; i++) { @@ -125,7 +128,7 @@ PROGMEM int discread(unsigned long address,int a,int len,int discn) } if (totlen) { //fread(buf,1,totlen,disk[discn].file); - emu_FileRead(buf,totlen); + disk_Read(buf,totlen); LOG("b: ",buf[0]); for (i=0; i +#include + +#define SPI SPI2 + +//#define SPICLOCK 104000000 +#define SPICLOCK 60000000 +//#define SPICLOCK 144e6 //Just a number..max speed +#define SPI_MODE SPI_MODE0 + +#define RAM_READ 0xB +//#define RAM_READ 0x3 +#define RAM_WRITE 0x2 + + +uint8_t PSRAM_T::_cs, PSRAM_T::_miso, PSRAM_T::_mosi, PSRAM_T::_sclk; +Page PSRAM_T::pages[MAX_PAGES]; +uint8_t PSRAM_T::nbPages=0; +int8_t PSRAM_T::top=0; +int8_t PSRAM_T::last=0; + + +PSRAM_T::PSRAM_T(uint8_t cs, uint8_t mosi, uint8_t sclk, uint8_t miso) +{ + _cs = cs; + _mosi = mosi; + _sclk = sclk; + _miso = miso; + pinMode(_cs, OUTPUT); + digitalWrite(_cs, 1); +} + + +void PSRAM_T::begin(void) +{ + SPI.setMOSI(_mosi); + SPI.setMISO(_miso); + SPI.setSCK(_sclk); + SPI.begin(); + //SPI.setClockDivider(SPI_CLOCK_DIV2); + delay(1); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + SPI.transfer(0x66); + digitalWrite(_cs, 1); + SPI.endTransaction(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + SPI.transfer(0x99); + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + + + +uint8_t PSRAM_T::psram_read(uint32_t addr) +{ + uint8_t val=0; + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + SPI.transfer(RAM_READ); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); +#if RAM_READ == 0xB + SPI.transfer(0xFF); +#endif + val = SPI.transfer(0xFF); + digitalWrite(_cs, 1); + SPI.endTransaction(); + return val; +} + + +void PSRAM_T::psram_read_n(uint32_t addr, uint8_t * val, int n) +{ + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + SPI.transfer(RAM_READ); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); +#if RAM_READ == 0xB + SPI.transfer(0xFF); +#endif + /* + while (n > 0) { + *val++ = SPI.transfer(0xFF); + n--; + } + */ + SPI.transfer(val,n); + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + + +void PSRAM_T::psram_write(uint32_t addr, uint8_t val) +{ + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + SPI.transfer(val); + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + +static uint8_t resp[PAGE_SIZE]; + + +void PSRAM_T::psram_write_n(uint32_t addr, uint8_t * val, int n) +{ + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + /* + while (n > 0) { + SPI.transfer(*val++); + n--; + } + */ + SPI.transfer(val,&resp[0],n); + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + + +#ifdef DMATRY +#include + +DMAMEM static uint8_t src[PAGE_SIZE+4]; +DMAMEM static uint8_t dst[PAGE_SIZE+4]; +static DMASetting dmasettings[8]; +static DMAChannel dmatx; +static volatile uint8_t rstop = 0; + +#define DMASPI_PRINT(x) do {Serial.printf(x) ; Serial.flush();} while (0); + +static void dmaInterrupt() +{ + dmatx.clearInterrupt(); + rstop = 1; + //DMASPI_PRINT("irq"); +} + +void PSRAM_T::psram_write_n_dma(uint32_t addr, uint8_t * val, int n) { + uint8_t * dstPt = &dst[0]; + //*dstPt++ = RAM_WRITE; + //*dstPt++ = (addr>>16)&0xff; + //*dstPt++ = (addr>>8)&0xff; + //*dstPt++ = addr&0xff; + int cnt = n; + while (cnt > 0) { + *dstPt++ = *val++; + cnt--; + } + arm_dcache_flush(&dst[0], n); + rstop = 0; + dmatx.disable(); + dmatx.attachInterrupt(dmaInterrupt); + + dmasettings[0].sourceBuffer(&dst[0], n); + //dmasettings[0].destination((uint8_t &) LPSPI4_TDR); + dmasettings[0].destination((uint8_t &) IMXRT_LPSPI1_S.TDR); + dmasettings[0].TCD->ATTR_DST = 1; + dmasettings[0].interruptAtCompletion(); + +Serial.printf("A") ; Serial.flush(); + + digitalWrite(_cs, HIGH); + // SPI.begin(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + + digitalWrite(_cs, 0); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + //SPI.transfer(0); + //SPI.transfer(1); +Serial.printf("B") ; Serial.flush(); + +#ifdef XXX + LPSPI4_CR &= ~LPSPI_CR_MEN;//disable LPSPI: + LPSPI4_CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + //LPSPI4_TCR = 15; // Framesize 16 Bits + IMXRT_LPSPI4_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + LPSPI4_DER = LPSPI_DER_TDDE; //TX DMA Request Enable + // IMXRT_LPSPI4_S.DER = LPSPI_DER_TDDE; // | LPSPI_DER_RDDE; //enable DMA on both TX and RX + LPSPI4_CR |= LPSPI_CR_MEN; //enable LPSPI: + //IMXRT_LPSPI4_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + // IMXRT_LPSPI4_S.FCR = 0; + // Lets try to output the first byte to make sure that we are in 8 bit mode... + // IMXRT_LPSPI4_S.SR = 0x3f00; // clear out all of the other status... + + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI4_TX ); +#endif + IMXRT_LPSPI1_S.CR &= ~LPSPI_CR_MEN;//disable LPSPI: + IMXRT_LPSPI1_S.CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + IMXRT_LPSPI1_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + IMXRT_LPSPI1_S.DER = LPSPI_DER_TDDE; //TX DMA Request Enable + IMXRT_LPSPI1_S.CR |= LPSPI_CR_MEN; //enable LPSPI: + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI1_TX ); +Serial.printf("C") ; Serial.flush(); +// SPI.initDMAChannels(); + dmatx = dmasettings[0]; + + dmatx.enable(); +Serial.printf("D") ; Serial.flush(); + while (rstop == 0) {}; + + Serial.printf("E") ; Serial.flush(); + digitalWrite(_cs, 1); +} +#endif + + + + +void PSRAM_T::pswrite(uint32_t addr, uint8_t val) +{ + psram_write(addr, val); + //return; + uint32_t curPage=addr&(~(PAGE_SIZE-1)); + for (int i=0; i + +#define PAGE_SIZE 16 //16 //32 //2048 //1024 +#define MAX_PAGES 8 + +struct Page { + uint8_t page[PAGE_SIZE]; + uint32_t pageid; + int8_t next; + int8_t prev; +}; + +class PSRAM_T +{ + public: + PSRAM_T(uint8_t _CS, uint8_t _MOSI=11, uint8_t _SCLK=13, uint8_t _MISO=12); + void begin(void); + void pswrite(uint32_t addr, uint8_t val); + uint8_t psread(uint32_t addr); + + private: + static uint8_t psram_read(uint32_t addr); + static void psram_read_n(uint32_t addr, uint8_t * val, int n); + static void psram_write(uint32_t addr, uint8_t val); + static void psram_write_n(uint32_t addr, uint8_t * val, int n); + + protected: + static uint8_t _cs, _miso, _mosi, _sclk; + static Page pages[MAX_PAGES]; + static uint8_t nbPages; + static int8_t top; + static int8_t last; +}; +#endif + +#endif + diff --git a/MCUME_teensy/teensycastaway/sound.cpp b/MCUME_teensy/teensycastaway/sound.cpp index 6c74a3b..9045c63 100644 --- a/MCUME_teensy/teensycastaway/sound.cpp +++ b/MCUME_teensy/teensycastaway/sound.cpp @@ -79,7 +79,7 @@ typedef struct /* Square wave look up table */ -PROGMEM static const int SquareWave[16] = { 127,127,127,127,127,127,127,127, -128,-128,-128,-128,-128,-128,-128,-128 }; +static const int SquareWave[16] = { 127,127,127,127,127,127,127,127, -128,-128,-128,-128,-128,-128,-128,-128 }; static long RandomNum; @@ -177,7 +177,7 @@ void Sound_ClearMixBuffer(void) Find how many samples to generate and store in 'nSamplesToGenerate' Also update 'SoundCycles' to store how many we actually did so generates set amount each frame */ -PROGMEM static void Sound_SetSamplesPassed(void) +static void Sound_SetSamplesPassed(void) { int nSampleCycles; int nSamplesPerFrame; @@ -369,7 +369,7 @@ static void Sound_GenerateChannel(int *pBuffer, unsigned char ToneFine, unsigned *pChannelFreq = ToneFreq; } - +#ifdef XXX /*-----------------------------------------------------------------------*/ /* Generate samples for all channels during this time-frame @@ -423,20 +423,6 @@ void Sound_Update(void) } - -/*-----------------------------------------------------------------------*/ -/* - On each VBL (50fps) complete samples. -*/ -void Sound_Update_VBL(void) -{ - //Sound_Update(); - - /* Clear write to register '13', used for YM file saving */ - bEnvelopeFreqFlag = FALSE; -} - - /*-----------------------------------------------------------------------*/ /* This is called from the audio callback function to create enough samples @@ -452,10 +438,65 @@ void Sound_UpdateFromAudioCallBack(void) nSamplesToGenerate = SOUND_BUFFER_SIZE - nGeneratedSamples; Sound_GenerateSamples(); +Serial.println("vvv"); } + +#endif + +void Sound_Update(void) +{ + int Dec=1; + + /* Check how many cycles have passed, as we use this to help find out if we are playing sample data */ + + /* First, add decay to channel amplitude variables */ + if (SoundCycles>(CYCLES_PER_FRAME/4)) + Dec = 16; /* Been long time between sound writes, must be normal tone sound */ + + if (!bWriteChannelAAmp) /* Not written to amplitude, decay value */ + { + ChannelAmpDecayTime[0]-=Dec; + if (ChannelAmpDecayTime[0]<0) ChannelAmpDecayTime[0] = 0; + } + if (!bWriteChannelBAmp) + { + ChannelAmpDecayTime[1]-=Dec; + if (ChannelAmpDecayTime[1]<0) ChannelAmpDecayTime[1] = 0; + } + if (!bWriteChannelCAmp) + { + ChannelAmpDecayTime[2]-=Dec; + if (ChannelAmpDecayTime[2]<0) ChannelAmpDecayTime[2] = 0; + } + + //Sound_Update(); + + /* Clear write to register '13', used for YM file saving */ + //bEnvelopeFreqFlag = FALSE; + + /* Reset the write to register '13' flag */ + bWriteEnvelopeFreq = FALSE; + /* And amplitude write flags */ + bWriteChannelAAmp = bWriteChannelBAmp = bWriteChannelCAmp = FALSE; + +} + +/*-----------------------------------------------------------------------*/ +/* + On each VBL (50fps) complete samples. +*/ +void Sound_Update_VBL(void) +{ + } + + + + void Sound_UpdateFromCallBack16(short *pBuffer, int len) { + len = len >> 1; + int *pChannelA=Channel_A_Buffer, *pChannelB=Channel_B_Buffer, *pChannelC=Channel_C_Buffer; int i; nSamplesToGenerate = len; @@ -471,18 +512,25 @@ void Sound_UpdateFromCallBack16(short *pBuffer, int len) /* Mix channels together, using table to clip and also convert to 'unsigned char' */ for(i=0; i +#define SAMPLERATE AUDIO_SAMPLE_RATE_EXACT +#define CLOCKFREQ 985248 + +#ifndef CUSTOM_SND +PROGMEM static const short square[]={ +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +}; + +PROGMEM const short noise[] { +-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,-32767,-32767, +32767,-32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,-32767, +32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767, +32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767, +}; + +#define NOISEBSIZE 0x100 + +typedef struct +{ + unsigned int spos; + unsigned int sinc; + unsigned int vol; +} Channel; + +static Channel chan[6] = { + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} }; + +#endif + +volatile bool playing = false; + + + + +PROGMEM static void snd_Reset(void) +{ +#ifndef CUSTOM_SND + chan[0].vol = 0; + chan[1].vol = 0; + chan[2].vol = 0; + chan[3].vol = 0; + chan[4].vol = 0; + chan[5].vol = 0; + chan[0].sinc = 0; + chan[1].sinc = 0; + chan[2].sinc = 0; + chan[3].sinc = 0; + chan[4].sinc = 0; + chan[5].sinc = 0; +#endif +} + + +#ifdef CUSTOM_SND +void SND_Process(void *sndbuffer, int sndn); +#endif + +PROGMEM static void snd_Mixer(short * stream, int len ) +{ + if (playing) + { +#ifdef CUSTOM_SND + SND_Process((void*)stream, len); +#else + int i; + long s; + len = len >> 1; + + short v0=chan[0].vol; + short v1=chan[1].vol; + short v2=chan[2].vol; + short v3=chan[3].vol; + short v4=chan[4].vol; + short v5=chan[5].vol; + for (i=0;i>8)&0x3f])>>11); + s+=((v1*square[(chan[1].spos>>8)&0x3f])>>11); + s+=((v2*square[(chan[2].spos>>8)&0x3f])>>11); + s+=((v3*noise[(chan[3].spos>>8)&(NOISEBSIZE-1)])>>11); + s+=((v4*noise[(chan[4].spos>>8)&(NOISEBSIZE-1)])>>11); + s+=((v5*noise[(chan[5].spos>>8)&(NOISEBSIZE-1)])>>11); + *stream++ = (short)(s); + *stream++ = (short)(s); + chan[0].spos += chan[0].sinc; + chan[1].spos += chan[1].sinc; + chan[2].spos += chan[2].sinc; + chan[3].spos += chan[3].sinc; + chan[4].spos += chan[4].sinc; + chan[5].spos += chan[5].sinc; + } +#endif + } +} + +PROGMEM void AudioPlaySystem::begin(void) +{ + //emu_printf("AudioPlaySystem constructor"); + this->reset(); + setSampleParameters(CLOCKFREQ, SAMPLERATE); +} + +PROGMEM void AudioPlaySystem::start(void) +{ + //emu_printf("allocating sound buf"); + playing = true; +} + +PROGMEM void AudioPlaySystem::setSampleParameters(float clockfreq, float samplerate) { +} + +PROGMEM void AudioPlaySystem::reset(void) +{ + snd_Reset(); +} + +PROGMEM void AudioPlaySystem::stop(void) +{ + //__disable_irq(); + playing = false; + //__enable_irq(); +} + +PROGMEM bool AudioPlaySystem::isPlaying(void) +{ + return playing; +} + +PROGMEM void AudioPlaySystem::update(void) { + audio_block_t *block; + + // only update if we're playing + if (!playing) return; + + // allocate the audio blocks to transmit + block = allocate(); + if (block == NULL) return; + + snd_Mixer((short*)block->data,AUDIO_BLOCK_SAMPLES); + //memset( (void*)block->data, 0, AUDIO_BLOCK_SAMPLES*2); + + transmit(block); + release(block); +} + +PROGMEM void AudioPlaySystem::sound(int C, int F, int V) { +#ifndef CUSTOM_SND + if (C < 6) { + chan[C].vol = V; + chan[C].sinc = F>>1; + } +#endif +} + +PROGMEM void AudioPlaySystem::step(void) { +} +#endif + diff --git a/MCUME_teensy/teensygen/AudioPlaySystem.h b/MCUME_teensy/teensygen/AudioPlaySystem.h new file mode 100644 index 0000000..0333adb --- /dev/null +++ b/MCUME_teensy/teensygen/AudioPlaySystem.h @@ -0,0 +1,28 @@ +#ifndef audioplaysystem_h_ +#define audioplaysystem_h_ + +#ifdef HAS_SND + +#include + +class AudioPlaySystem : public AudioStream +{ +public: + AudioPlaySystem(void) : AudioStream(0, NULL) { begin(); } + void begin(void); + void setSampleParameters(float clockfreq, float samplerate); + void reset(void); + void start(void); + void stop(void); + bool isPlaying(void); + void sound(int C, int F, int V); + void buzz(int size, int val); + void step(void); + +private: + virtual void update(void); +}; +#endif + +#endif + diff --git a/MCUME_teensy/teensygen/arduinoproto.h b/MCUME_teensy/teensygen/arduinoproto.h new file mode 100644 index 0000000..289030c --- /dev/null +++ b/MCUME_teensy/teensygen/arduinoproto.h @@ -0,0 +1,7 @@ +#ifndef _ARDUINOPROTO_H_ +#define _ARDUINOPROTO_H_ + +#include +//#define PROGMEM + +#endif diff --git a/MCUME_teensy/teensygen/cpuintrf.h b/MCUME_teensy/teensygen/cpuintrf.h new file mode 100644 index 0000000..d78b29d --- /dev/null +++ b/MCUME_teensy/teensygen/cpuintrf.h @@ -0,0 +1,30 @@ + +#ifndef CPUINTRF_H +#define CPUINTRF_H + +#include "osd_cpu.h" + +#define CPU_16BIT_PORT 0x4000 +#define CPU_FLAGS_MASK 0xff00 +#define CLEAR_LINE 0 +#define ASSERT_LINE 1 +#define REG_PREVIOUSPC -1 +#define REG_SP_CONTENTS -2 + +/* daisy-chain link */ +typedef struct { + void (*reset)(int); /* reset callback */ + int (*interrupt_entry)(int); /* entry callback */ + void (*interrupt_reti)(int); /* reti callback */ + int irq_param; /* callback paramater */ +} Z80_DaisyChain; + +#define Z80_MAXDAISY 4 /* maximum of daisy chan device */ + +#define Z80_INT_REQ 0x01 /* interrupt request mask */ +#define Z80_INT_IEO 0x02 /* interrupt disable mask(IEO) */ + +#define Z80_VECTOR(device,state) (((device)<<8)|(state)) + + +#endif /* CPUINTRF_H */ diff --git a/MCUME_teensy/teensygen/emu.cpp b/MCUME_teensy/teensygen/emu.cpp new file mode 100644 index 0000000..00b19d9 --- /dev/null +++ b/MCUME_teensy/teensygen/emu.cpp @@ -0,0 +1,173 @@ +#include + +#include "emuapi.h" +#include "tft_t_dma.h" +#include "psram_t.h" +#include "iopins.h" + +extern "C" { +#include "shared.h" +#include "system.h" +} + +PSRAM_T psram = PSRAM_T(PSRAM_CS, PSRAM_MOSI, PSRAM_SCLK, PSRAM_MISO); + +extern "C" uint8 read_rom(int address) { + return (psram.psread(address)); +} + +extern "C" uint8 readb_swap_rom(int address) { + return(psram.psread(address^1)); +} + +extern "C" uint16 readw_swap_rom(int address) { + return psram.psread_w(address); +} +extern "C" void write_rom(int address, uint8 val) { + psram.pswrite(address,val); +} + +static uint8 romversion; +extern "C" uint8 rom_version(void) { + return romversion; +} + +static deinterleave_block(int offset, int srcoffset) +{ + int i; + int srcaddr = offset + srcoffset; + uint8 * block = work_ram; // 0x4000 bytes tmp buffer + for(i = 0; i < 0x4000; i += 1) { + block[i] = read_rom(srcaddr++); + } + for(i = 0; i < 0x2000; i += 1) + { + write_rom(srcoffset + i*2+1, block[0x2000 + (i)]); + write_rom(srcoffset + i*2+0, block[0x0000 + (i)]); + } +} + + +void gen_Init(void) +{ + emu_printf("Allocating MEM"); + psram.begin(); + mem_init(); + emu_printf("Allocating MEM done"); +} + + +static int hk = 0; +static int k = 0; + + +void gen_Input(int click) { + hk = emu_ReadI2CKeyboard(); + k = emu_ReadKeys(); +} + + +void gen_Start(char * filename) +{ + emu_printf("load and init"); + + + int size; + int offset = 0; + + size = emu_FileSize(filename); + int pos = 0; + int n; + int i; + char * buf = (char*)bg_pattern_cache; + size = 0; + if (emu_FileOpen(filename)) { + while ( (n = emu_FileRead(buf,0x40000) ) ) { + size += n; + for (int i=0; i +#endif + +#ifdef USE_SDFS +#define SDFSDEV "2:" + +#include "uSDFS.h" +static FATFS fatfs; +static FIL file; +#else +#include +static File file; +#endif + +extern TFT_T_DMA tft; +static char romspath[64]; +static int16_t calMinX=-1,calMinY=-1,calMaxX=-1,calMaxY=-1; +static bool i2cKeyboardPresent = false; +const uint16_t deflogo[] = { + 0x0000,0x0000 +}; +static const uint16_t * logo = deflogo; + +#ifdef USE_SDFS +#define CALIBRATION_FILE SDFSDEV "/cal.cfg" +#else +#define CALIBRATION_FILE "/cal.cfg" +#endif +#define MAX_FILES 128 +#define MAX_FILENAME_SIZE 28 +#define MAX_MENULINES (MKEY_L9) +#define TEXT_HEIGHT 16 +#define TEXT_WIDTH 8 +#define MENU_FILE_XOFFSET (6*TEXT_WIDTH) +#define MENU_FILE_YOFFSET (2*TEXT_HEIGHT) +#define MENU_FILE_W (MAX_FILENAME_SIZE*TEXT_WIDTH) +#define MENU_FILE_H (MAX_MENULINES*TEXT_HEIGHT) +#define MENU_FILE_BGCOLOR RGBVAL16(0x00,0x00,0x20) +#define MENU_JOYS_YOFFSET (12*TEXT_HEIGHT) +#define MENU_VBAR_XOFFSET (0*TEXT_WIDTH) +#define MENU_VBAR_YOFFSET (MENU_FILE_YOFFSET) + +#define MENU_TFT_XOFFSET (MENU_FILE_XOFFSET+MENU_FILE_W+8) +#define MENU_TFT_YOFFSET (MENU_VBAR_YOFFSET+32) +//#define MENU_VGA_XOFFSET (MENU_FILE_XOFFSET+MENU_FILE_W+8) +//#define MENU_VGA_YOFFSET (MENU_VBAR_YOFFSET+MENU_FILE_H-32-37) + + +#define MKEY_L1 1 +#define MKEY_L2 2 +#define MKEY_L3 3 +#define MKEY_L4 4 +#define MKEY_L5 5 +#define MKEY_L6 6 +#define MKEY_L7 7 +#define MKEY_L8 8 +#define MKEY_L9 9 +#define MKEY_UP 20 +#define MKEY_DOWN 21 +#define MKEY_JOY 22 +#define MKEY_TFT 23 +#define MKEY_VGA 24 + +const unsigned short menutouchareas[] = { + TAREA_XY,MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, + TAREA_WH,MENU_FILE_W, TEXT_HEIGHT, + TAREA_NEW_COL,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT, + + TAREA_XY,MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET, + TAREA_WH,32,48, + TAREA_NEW_COL, 72,72,8,40, + + TAREA_XY,MENU_TFT_XOFFSET,MENU_TFT_YOFFSET, + TAREA_WH,32,37, + TAREA_NEW_COL, 38,38, + + TAREA_END}; + +const unsigned short menutouchactions[] = { + MKEY_L1,MKEY_L2,MKEY_L3,MKEY_L4,MKEY_L5,MKEY_L6,MKEY_L7,MKEY_L8,MKEY_L9, + MKEY_UP,MKEY_DOWN,ACTION_NONE,MKEY_JOY, + MKEY_TFT,MKEY_VGA}; + + +static bool menuOn=true; +static bool callibrationOn=false; +static int callibrationStep=0; +static bool menuRedraw=true; +static int nbFiles=0; +static int curFile=0; +static int topFile=0; +static char selection[MAX_FILENAME_SIZE+1]=""; +static uint8_t prev_zt=0; + +static char files[MAX_FILES][MAX_FILENAME_SIZE]; + +static int readNbFiles(void) { + int totalFiles = 0; + +#ifdef USE_SDFS + DIR dir; + FILINFO entry; + f_opendir(&dir, romspath); + while ( (true) && (totalFiles= y1) && (yt < y2) && (xt >= x1) && (xt < x2) ) { + *rx = x1; + *ry = y1; + *rw = x2-x1; + *rh = y2-y1; + return (actions[k]); + } + k++; + } + } + } + prev_zt =1; + } else { + prev_zt=0; + } + + return ACTION_NONE; +} + +void toggleMenu(bool on) { + if (on) { + callibrationOn=false; + menuOn=true; + menuRedraw=true; + tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00)); + tft.drawTextNoDma(0,0, TITLE, RGBVAL16(0x00,0xff,0xff), RGBVAL16(0x00,0x00,0xff), true); + //tft.drawSpriteNoDma(MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET,(uint16_t*)bmpvbar); + //tft.drawSpriteNoDma(MENU_TFT_XOFFSET,MENU_TFT_YOFFSET,(uint16_t*)bmptft); + //tft.drawSpriteNoDma(MENU_VGA_XOFFSET,MENU_VGA_YOFFSET,(uint16_t*)bmpvga); + } else { + menuOn = false; + } +} + + +static void callibrationInit(void) +{ + callibrationOn=true; + menuOn=false; + callibrationStep = 0; + calMinX=0,calMinY=0,calMaxX=0,calMaxY=0; + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration process:", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " Hit the red cross at each corner", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + prev_zt = 1; +} + + +static void readCallibration(void) +{ + char fileBuffer[64]; + +#ifdef USE_SDFS + FIL file; + int retval; + if( !(f_open(&file, CALIBRATION_FILE, FA_READ)) ) { + if( !(f_read (&file, fileBuffer, 64, &retval)) ) { + if (retval == 64) { + sscanf(fileBuffer,"%d %d %d %d", &calMinX,&calMinY,&calMaxX,&calMaxY); + } + } + f_close(&file); + } +#else + File file = SD.open(CALIBRATION_FILE, O_READ); + if (file) { + if ( file.read(fileBuffer, 64) ) { + sscanf(fileBuffer,"%d %d %d %d", &calMinX,&calMinY,&calMaxX,&calMaxY); + } + file.close(); + Serial.println("Current callibration params:"); + Serial.println(calMinX); + Serial.println(calMinY); + Serial.println(calMaxX); + Serial.println(calMaxY); + } + else { + Serial.println("Callibration read error"); + } +#endif + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); +} + +static void writeCallibration(void) +{ + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); +#ifdef USE_SDFS + FIL file; + int retval; + if( !(f_open(&file, CALIBRATION_FILE, FA_WRITE)) ) { + //if( !(f_read (&file, fileBuffer, 64, &retval)) ) { + // if (retval == 64) { + // sscanf(fileBuffer,"%d %d %d %d", &calMinX,&calMinY,&calMaxX,&calMaxY); + // } + //} + f_close(&file); + } + +#else + File file = SD.open(CALIBRATION_FILE, O_WRITE | O_CREAT | O_TRUNC); + if (file) { + file.print(calMinX); + file.print(" "); + file.print(calMinY); + file.print(" "); + file.print(calMaxX); + file.print(" "); + file.println(calMaxY); + file.close(); + } + else { + Serial.println("Callibration write error"); + } +#endif +} + + +bool callibrationActive(void) +{ + return (callibrationOn); +} + + + +int handleCallibration(uint16_t bClick) { + uint16_t xt=0; + uint16_t yt=0; + uint16_t zt=0; + if (tft.isTouching()) { + if (prev_zt == 0) { + prev_zt = 1; + tft.readRaw(&xt,&yt,&zt); + if (zt < 1000) { + return 0; + } + switch (callibrationStep) + { + case 0: + callibrationStep++; + tft.drawTextNoDma(0,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(TFT_REALWIDTH-8,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMinX += xt; + calMinY += yt; + break; + case 1: + callibrationStep++; + tft.drawTextNoDma(TFT_REALWIDTH-8,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(TFT_REALWIDTH-8,TFT_REALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMinY += yt; + break; + case 2: + callibrationStep++; + tft.drawTextNoDma(TFT_REALWIDTH-8,TFT_REALHEIGHT-16, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,TFT_REALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMaxY += yt; + break; + case 3: + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration done!", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " (Click center to exit)", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + callibrationStep++; + calMinX += xt; + calMaxY += yt; + break; + case 4: + //Serial.println(xt); + //Serial.println(yt); + if ( (xt > (TFT_REALWIDTH/4)) && (xt < (TFT_REALWIDTH*3)/4) + && (yt > (TFT_REALHEIGHT/4)) && (yt < (TFT_REALHEIGHT*3)/4) ) { + calMinX /= 2; + calMinY /= 2; + calMaxX /= 2; + calMaxY /= 2; + writeCallibration(); + toggleMenu(true); + } + else { + callibrationInit(); + } + break; + + } + delay(100); + } + } + else { + prev_zt = 0; + } +} + + + +bool menuActive(void) +{ + return (menuOn); +} + +int handleMenu(uint16_t bClick) +{ + int action = ACTION_NONE; + + char newpath[80]; + strcpy(newpath, romspath); + strcat(newpath, "/"); + strcat(newpath, selection); + + int rx=0,ry=0,rw=0,rh=0; + char c = captureTouchZone(menutouchareas, menutouchactions, &rx,&ry,&rw,&rh); + + if ( (bClick & MASK_JOY2_BTN) || (c == MKEY_TFT) ) { + emu_printf(newpath); +#ifdef USE_SDFS + FILINFO entry; + f_stat(newpath, &entry); + if ( (entry.fattrib & AM_DIR) ) { +#else + File file = SD.open(newpath); + if (file.isDirectory()) { +#endif + strcpy(romspath,newpath); + curFile = 0; + nbFiles = readNbFiles(); + } + else { + action = ACTION_RUNTFT; + } + menuRedraw=true; + } + else if ( (bClick & MASK_KEY_USER1) || (c == MKEY_VGA) ) { + menuRedraw=true; + action = ACTION_RUNVGA; + } + else if ( (c >= MKEY_L1) && (c <= MKEY_L9) ) { + if ( (topFile+(int)c-1) <= (nbFiles-1) ) + { + curFile = topFile + (int)c -1; + menuRedraw=true; + //tft.drawRectNoDma( rx,ry,rw,rh, KEYBOARD_HIT_COLOR ); + } + } + else if (bClick & MASK_JOY2_UP) { + if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if ( (bClick & MASK_JOY2_RIGHT) || (bClick & MASK_JOY1_RIGHT) || (c == MKEY_UP) ) { + if ((curFile-9)>=0) { + menuRedraw=true; + curFile -= 9; + } else if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if (bClick & MASK_JOY2_DOWN) { + if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_JOY2_LEFT) || (bClick & MASK_JOY1_LEFT) || (c == MKEY_DOWN) ) { + if ((curFile<(nbFiles-9)) && (nbFiles)) { + curFile += 9; + menuRedraw=true; + } + else if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_KEY_USER2) || (c == MKEY_JOY) ) { + emu_SwapJoysticks(0); + menuRedraw=true; + } + + if (menuRedraw && nbFiles) { + int fileIndex = 0; + tft.drawRectNoDma(MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, MENU_FILE_W, MENU_FILE_H, MENU_FILE_BGCOLOR); +// if (curFile <= (MAX_MENULINES/2-1)) topFile=0; +// else topFile=curFile-(MAX_MENULINES/2); + if (curFile <= (MAX_MENULINES-1)) topFile=0; + else topFile=curFile-(MAX_MENULINES/2); + + //Serial.print("curfile: "); + //Serial.println(curFile); + //Serial.print("topFile: "); + //Serial.println(topFile); + + int i=0; + while (i=nbFiles) { + // no more files + break; + } + char * filename = &files[fileIndex][0]; + if (fileIndex >= topFile) { + if ((i+topFile) < nbFiles ) { + if ((i+topFile)==curFile) { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, filename, RGBVAL16(0xff,0xff,0x00), RGBVAL16(0xff,0x00,0x00), true); + strcpy(selection,filename); + } + else { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, filename, 0xFFFF, 0x0000, true); + } + } + i++; + } + fileIndex++; + } + + //tft.drawSpriteNoDma(0,MENU_JOYS_YOFFSET,(uint16_t*)bmpjoy); + tft.drawTextNoDma(48,MENU_JOYS_YOFFSET+8, (emu_SwapJoysticks(1)?(char*)"SWAP=1":(char*)"SWAP=0"), RGBVAL16(0x00,0xff,0xff), RGBVAL16(0xff,0x00,0x00), false); + menuRedraw=false; + } + + return (action); +} + +char * menuSelection(void) +{ + return (selection); +} + + + + +void emu_init(void) +{ + Serial.begin(115200); + //while (!Serial) {} +#ifdef USE_SDFS + strcpy(romspath,SDFSDEV); + strcat(romspath,ROMSDIR); + FRESULT rc; + if((rc = f_mount (&fatfs, romspath, 1))) { + emu_printf("Fail mounting SDFS"); + } + else { + rc = f_chdrive(ROMSDIR); + } +#else + while (!SD.begin(SD_CS)) { + emu_printf("SdFat.begin() failed"); + delay(1000); + } + strcpy(romspath,ROMSDIR); +#endif + nbFiles = readNbFiles(); + + Serial.print("SD initialized, files found: "); + Serial.println(nbFiles); + + emu_InitJoysticks(); + readCallibration(); + + if ((tft.isTouching()) || (emu_ReadKeys() & MASK_JOY2_BTN) ) { + callibrationInit(); + } + else + { + toggleMenu(true); + } + +#ifdef HAS_I2CKBD + byte msg[7]={0,0,0,0,0,0,0}; + Wire.begin(); // join i2c bus SDA2/SCL2 + Wire.requestFrom(8, 7); // request 7 bytes from slave device #8 + int i = 0; + while (Wire.available() && (i<7) ) { // slave may send less than requested + byte b = Wire.read(); // receive a byte + msg[i++] = b; + } + /* + Serial.println(msg[0], BIN); + Serial.println(msg[1], BIN); + Serial.println(msg[2], BIN); + Serial.println(msg[3], BIN); + Serial.println(msg[4], BIN); + Serial.println(msg[5], BIN); + Serial.println(msg[6], BIN); + */ + if ( (msg[0] == 0xff) && (msg[1] == 0xff) && + (msg[2] == 0xff) && (msg[3] == 0xff) && + (msg[4] == 0xff) && (msg[5] == 0xff) && (msg[6] == 0xff)) { + i2cKeyboardPresent = true; + Serial.println("i2C keyboard found"); + } +#endif +} + + +void emu_printf(char * text) +{ + Serial.println(text); +} + +void emu_printf(int val) +{ + Serial.println(val); +} + +void emu_printi(int val) +{ + Serial.println(val); +} + +void emu_printh(int val) +{ + Serial.println(val,HEX); +} + +static int malbufpt = 0; +static char malbuf[EXTRA_HEAP]; + +void * emu_Malloc(int size) +{ + void * retval = malloc(size); + if (!retval) { + emu_printf("failled to allocate"); + emu_printf(size); + emu_printf("fallback"); + if ( (malbufpt+size) < sizeof(malbuf) ) { + retval = (void *)&malbuf[malbufpt]; + malbufpt += size; + } + else { + emu_printf("failure to allocate"); + } + } + else { + emu_printf("could allocate "); + emu_printf(size); + } + + return retval; +} + +void emu_Free(void * pt) +{ + free(pt); +} + + + +int emu_FileOpen(char * filename) +{ + int retval = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("FileOpen..."); + emu_printf(filepath); +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { +#else + if ((file = SD.open(filepath, O_READ))) { +#endif + retval = 1; + } + else { + emu_printf("FileOpen failed"); + } + return (retval); +} + +int emu_FileRead(char * buf, int size) +{ + unsigned char buffer[256]; + + int remaining = size; + int byteread = 0; + int retval=0; + while (remaining>0) { +#ifdef USE_SDFS + if( !(f_read (&file, buffer, 256, &retval)) ) + //f_read (&file, buffer, 256, &retval); +#else + retval = file.read(buffer, 256); +#endif + if (retval>0) { + //emu_printi(retval); + memcpy(buf,buffer,retval); + buf += retval; + byteread += retval; + remaining -= retval; + } + else { + break; + } + } + + return byteread; +} + +unsigned char emu_FileGetc(void) { + unsigned char c; +#ifdef USE_SDFS + int retval=0; + if( !(f_read (&file, &c, 1, &retval)) ) +#else + int retval = file.read(&c, 1); +#endif + if (retval != 1) { + emu_printf("emu_FileGetc failed"); + } + return c; +} + + +void emu_FileClose(void) +{ +#ifdef USE_SDFS + f_close(&file); +#else + file.close(); +#endif +} + +int emu_FileSize(char * filename) +{ + int filesize=0; + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("FileSize..."); + emu_printf(filepath); +#ifdef USE_SDFS + FILINFO entry; + f_stat(filepath, &entry); + filesize = entry.fsize; +#else + if ((file = SD.open(filepath, O_READ))) + { + emu_printf("filesize is..."); + filesize = file.size(); + emu_printf(filesize); + file.close(); + } +#endif + + return(filesize); +} + +int emu_FileSeek(int seek) +{ +#ifdef USE_SDFS + f_lseek(&file, seek); +#else + file.seek(seek); +#endif + return (seek); +} + +int emu_FileTell(void) +{ +#ifdef USE_SDFS + return (f_tell(&file)); +#else + return (50); +#endif +} + + +int emu_LoadFile(char * filename, char * buf, int size) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("LoadFile..."); + emu_printf(filepath); +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { + filesize = f_size(&file); + emu_printf(filesize); + if (size >= filesize) + { + int retval=0; + if( (f_read (&file, buf, filesize, &retval)) ) { + emu_printf("File read failed"); + } + } + f_close(&file); + } +#else + if ((file = SD.open(filepath, O_READ))) + { + filesize = file.size(); + emu_printf(filesize); + + if (size >= filesize) + { + if (emu_FileRead(buf, filesize) != filesize) + { + emu_printf("File read failed"); + } + } + file.close(); + } +#endif + + return(filesize); +} + +int emu_LoadFileSeek(char * filename, char * buf, int size, int seek) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("LoadFileSeek..."); + emu_printf(filepath); +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { + f_lseek(&file, seek); + emu_printf(size); + if (size >= filesize) + { + int retval=0; + if( (!f_read (&file, buf, size, &retval)) ) + if (retval != size) + { + emu_printf("File read failed"); + } + } + f_close(&file); + } +#else + if ((file = SD.open(filepath, O_READ))) + { + file.seek(seek); + emu_printf(size); + if (file.read(buf, size) != size) { + emu_printf("File read failed"); + } + file.close(); + } +#endif + + return(filesize); +} + +static int keypadval=0; +static boolean joySwapped = false; +static uint16_t bLastState; +static int xRef; +static int yRef; + + +int emu_ReadAnalogJoyX(int min, int max) +{ + int val = analogRead(PIN_JOY2_A1X); +#if INVX + val = 4095 - val; +#endif + val = val-xRef; + val = ((val*140)/100); + if ( (val > -512) && (val < 512) ) val = 0; + val = val+2048; + return (val*(max-min))/4096; +} + +int emu_ReadAnalogJoyY(int min, int max) +{ + int val = analogRead(PIN_JOY2_A2Y); +#if INVY + val = 4095 - val; +#endif + val = val-yRef; + val = ((val*120)/100); + if ( (val > -512) && (val < 512) ) val = 0; + //val = (val*(max-min))/4096; + val = val+2048; + //return val+(max-min)/2; + return (val*(max-min))/4096; +} + + +static uint16_t readAnalogJoystick(void) +{ + uint16_t joysval = 0; + + int xReading = emu_ReadAnalogJoyX(0,256); + if (xReading > 128) joysval |= MASK_JOY2_LEFT; + else if (xReading < 128) joysval |= MASK_JOY2_RIGHT; + + int yReading = emu_ReadAnalogJoyY(0,256); + if (yReading < 128) joysval |= MASK_JOY2_UP; + else if (yReading > 128) joysval |= MASK_JOY2_DOWN; + +#ifdef PIN_JOY2_BTN + joysval |= (digitalRead(PIN_JOY2_BTN) == HIGH ? 0 : MASK_JOY2_BTN); +#endif + return (joysval); +} + + +int emu_SwapJoysticks(int statusOnly) { + if (!statusOnly) { + if (joySwapped) { + joySwapped = false; + } + else { + joySwapped = true; + } + } + return(joySwapped?1:0); +} + +int emu_GetPad(void) +{ + return(keypadval|((joySwapped?1:0)<<7)); +} + +int emu_ReadKeys(void) +{ + uint16_t retval; + uint16_t j1 = readAnalogJoystick(); + uint16_t j2 = 0; + + // Second joystick +#ifdef PIN_JOY1_1 + if ( digitalRead(PIN_JOY1_1) == LOW ) j2 |= MASK_JOY2_UP; +#endif +#ifdef PIN_JOY1_2 + if ( digitalRead(PIN_JOY1_2) == LOW ) j2 |= MASK_JOY2_DOWN; +#endif +#ifdef PIN_JOY1_3 + if ( digitalRead(PIN_JOY1_3) == LOW ) j2 |= MASK_JOY2_RIGHT; +#endif +#ifdef PIN_JOY1_4 + if ( digitalRead(PIN_JOY1_4) == LOW ) j2 |= MASK_JOY2_LEFT; +#endif +#ifdef PIN_JOY1_BTN + if ( digitalRead(PIN_JOY1_BTN) == LOW ) j2 |= MASK_JOY2_BTN; +#endif + if (joySwapped) { + retval = ((j1 << 8) | j2); + } + else { + retval = ((j2 << 8) | j1); + } + +#ifdef PIN_KEY_USER1 + if ( digitalRead(PIN_KEY_USER1) == LOW ) retval |= MASK_KEY_USER1; +#endif +#ifdef PIN_KEY_USER2 + if ( digitalRead(PIN_KEY_USER2) == LOW ) retval |= MASK_KEY_USER2; +#endif +#ifdef PIN_KEY_USER3 + if ( digitalRead(PIN_KEY_USER3) == LOW ) retval |= MASK_KEY_USER3; +#endif +#ifdef PIN_KEY_USER4 + if ( digitalRead(PIN_KEY_USER4) == LOW ) retval |= MASK_KEY_USER4; +#endif + + //Serial.println(j1,HEX); + + return (retval); +} + +unsigned short emu_DebounceLocalKeys(void) +{ + uint16_t bCurState = emu_ReadKeys(); + uint16_t bClick = bCurState & ~bLastState; + bLastState = bCurState; + + return (bClick); +} + +int emu_ReadI2CKeyboard(void) { + int retval=0; +#ifdef HAS_I2CKBD + if (i2cKeyboardPresent) { + byte msg[7]={0,0,0,0,0,0,0}; + Wire.requestFrom(8, 7); // request 7 bytes from slave device #8 + int i = 0; + int hitindex=-1; + while (Wire.available() && (i<7) ) { // slave may send less than requested + byte b = Wire.read(); // receive a byte + if (b != 0xff) hitindex=i; + msg[i++] = b; + } + + if (hitindex >=0 ) { + /* + Serial.println(msg[0], BIN); + Serial.println(msg[1], BIN); + Serial.println(msg[2], BIN); + Serial.println(msg[3], BIN); + Serial.println(msg[4], BIN); + Serial.println(msg[5], BIN); + Serial.println(msg[6], BIN); + */ + unsigned short match = (~msg[hitindex])&0x00FF | (hitindex<<8); + //Serial.println(match,HEX); + for (i=0; i=1) && (c <= ACTION_MAXKBDVAL) ) { + + keypadval = c; + keyPressCount = 10; + delay(50); + vkeyRefresh = true; + exitVkbd = true; + } + else if (c == ACTION_EXITKBD) { + vkeyRefresh = true; + exitVkbd = true; + } + } + } + + if (vkeyRefresh) { + vkeyRefresh = false; + tft.drawSpriteNoDma(0,0,(uint16_t*)logo, rx, ry, rw, rh); + } + + if ( (exitVkbd) && (vkbActive) ) { + if (!vkbKeepOn) { + toggleVirtualkeyboard(false); + } + else { + toggleVirtualkeyboard(true); + } + } +} + +int emu_setKeymap(int index) { + if (index) { + } + else { + } +} + + + diff --git a/MCUME_teensy/teensygen/emuapi.h b/MCUME_teensy/teensygen/emuapi.h new file mode 100644 index 0000000..31d06b9 --- /dev/null +++ b/MCUME_teensy/teensygen/emuapi.h @@ -0,0 +1,152 @@ +#ifndef EMUAPI_H +#define EMUAPI_H + +//#define INVX 1 +//#define INVY 1 +#define HAS_SND 1 +#define CUSTOM_SND 1 +//#define HAS_I2CKBD 1 +//#define TIMER_REND 1 + +#define EXTRA_HEAP 0x10 //0x9000 + +// Title: < > +#define TITLE " Genesis Emulator " +#define ROMSDIR "/gen" + +#define emu_Init(ROM) {gen_Init(); gen_Start(ROM);} +#define emu_Step(x) {gen_Step();} +#define emu_Input(x) {gen_Input(x);} + +#define PALETTE_SIZE 2 +#define VID_FRAME_SKIP 0x0 +#define TFT_VBUFFER_YCROP 0 +#define SINGLELINE_RENDERING 1 + +#define R32(rgb) ((rgb>>16)&0xff) +#define G32(rgb) ((rgb>>8)&0xff) +#define B32(rgb) (rgb & 0xff) + +#define ACTION_NONE 0 +#define ACTION_MAXKBDVAL 16 +#define ACTION_EXITKBD 128 +#define ACTION_RUNTFT 129 +#define ACTION_RUNVGA 130 + +#ifdef KEYMAP_PRESENT + +#define TAREA_W_DEF 32 +#define TAREA_H_DEF 32 +#define TAREA_END 255 +#define TAREA_NEW_ROW 254 +#define TAREA_NEW_COL 253 +#define TAREA_XY 252 +#define TAREA_WH 251 + +#define KEYBOARD_X 16 +#define KEYBOARD_Y 32 +#define KEYBOARD_KEY_H 30 +#define KEYBOARD_KEY_W 28 +#define KEYBOARD_HIT_COLOR RGBVAL16(0xff,0x00,0x00) + +const unsigned short keysw[]= +{ TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + //TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_END}; + +const unsigned short keys[]={ + +59, 60, 61, 62, 63, 64, 65, 66, 67, 68, +109,110,111,112,106,107,108,17,18,19, +20,21,22,23,24,25,26,27,28,29, +30,31,32,33,34,35,36,37,38,57 }; + + + + +#ifdef HAS_I2CKBD +const unsigned short i2ckeys[] = { + 0X0080,0X0008,0X0180,0X0108,0X0280,0X0208,0X0380,0X0308,0X0480,0X0408, + 0X0040,0X0004,0X0140,0X0104,0X0240,0X0204,0X0340,0X0304,0X0440,0X0404, + 0X0020,0X0002,0X0120,0X0102,0X0220,0X0202,0X0320,0X0302,0X0420,0X0402, + 0X0010,0X0001,0X0110,0X0101,0X0210,0X0201,0X0310,0X0301,0X0410,0X0401 }; + //0X0580,0X0540,0X0520,0X0510,0X0508,0X0504,0X0502,0X0501,0X0680,0X0640 }; +#endif + +#endif + + + +#define MASK_JOY2_RIGHT 0x0001 +#define MASK_JOY2_LEFT 0x0002 +#define MASK_JOY2_UP 0x0004 +#define MASK_JOY2_DOWN 0x0008 +#define MASK_JOY2_BTN 0x0010 +#define MASK_KEY_USER1 0x0020 +#define MASK_KEY_USER2 0x0040 +#define MASK_KEY_USER3 0x0080 +#define MASK_JOY1_RIGHT 0x0100 +#define MASK_JOY1_LEFT 0x0200 +#define MASK_JOY1_UP 0x0400 +#define MASK_JOY1_DOWN 0x0800 +#define MASK_JOY1_BTN 0x1000 +#define MASK_KEY_USER4 0x2000 + + + +#ifdef __cplusplus +extern "C" { +#endif +extern void emu_init(void); +extern void emu_printf(char * text); +extern void emu_printi(int val); +extern void emu_printh(int val); +extern void * emu_Malloc(int size); +extern void emu_Free(void * pt); + + +extern int emu_FileOpen(char * filename); +extern int emu_FileRead(char * buf, int size); +extern unsigned char emu_FileGetc(void); +extern int emu_FileTell(void); +extern int emu_FileSeek(int seek); +extern void emu_FileClose(void); +extern int emu_FileSize(char * filename); +extern int emu_LoadFile(char * filename, char * buf, int size); +extern int emu_LoadFileSeek(char * filename, char * buf, int size, int seek); +extern void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index); +extern void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride); +extern void emu_DrawLine(unsigned char * VBuf, int width, int height, int line); +extern void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line); +extern void emu_DrawVsync(void); +extern int emu_FrameSkip(void); +extern void * emu_LineBuffer(int line); + +extern void emu_InitJoysticks(void); +extern int emu_SwapJoysticks(int statusOnly); +extern unsigned short emu_DebounceLocalKeys(void); +extern int emu_ReadKeys(void); +extern int emu_GetPad(void); +extern int emu_ReadAnalogJoyX(int min, int max); +extern int emu_ReadAnalogJoyY(int min, int max); +extern int emu_ReadI2CKeyboard(void); +extern void emu_sndPlaySound(int chan, int volume, int freq); +extern void emu_sndPlayBuzz(int size, int val); +extern void emu_sndInit(); +extern void emu_resetus(void); +extern int emu_us(void); + +extern int emu_setKeymap(int index); + +#ifdef __cplusplus +} +#endif + +#endif + + + + diff --git a/MCUME_teensy/teensygen/fm.c b/MCUME_teensy/teensygen/fm.c new file mode 100644 index 0000000..279b079 --- /dev/null +++ b/MCUME_teensy/teensygen/fm.c @@ -0,0 +1,1495 @@ + +#include "shared.h" +#include + +#ifndef PI +#define PI 3.14159265358979323846 +#endif + +#define BUILD_OPN (BUILD_YM2612) +#define BUILD_STEREO (BUILD_YM2612) +#define BUILD_LFO (BUILD_YM2612) + +#define SIN_ENT 2048 +#define ENV_BITS 16 +#define EG_ENT 4096 +#define EG_STEP (96.0/EG_ENT) /* OPL == 0.1875 dB */ + +#if FM_LFO_SUPPORT +/* LFO table entries */ +#define LFO_ENT 512 +#define LFO_SHIFT (32-9) +#define LFO_RATE 0x10000 +#endif + +/* -------------------- preliminary define section --------------------- */ +/* attack/decay rate time rate */ +#define OPM_ARRATE 399128 +#define OPM_DRRATE 5514396 +/* It is not checked , because I haven't YM2203 rate */ +#define OPN_ARRATE OPM_ARRATE +#define OPN_DRRATE OPM_DRRATE + +/* PG output cut off level : 78dB(14bit)? */ +#define PG_CUT_OFF ((int)(78.0/EG_STEP)) +/* EG output cut off level : 68dB? */ +#define EG_CUT_OFF ((int)(68.0/EG_STEP)) + +#define FREQ_BITS 24 /* frequency turn */ + +/* PG counter is 21bits @oct.7 */ +#define FREQ_RATE (1<<(FREQ_BITS-21)) +#define TL_BITS (FREQ_BITS+2) +/* OPbit = 14(13+sign) : TL_BITS+1(sign) / output = 16bit */ +#define TL_SHIFT (TL_BITS+1-(14-16)) + +/* output final shift */ +#define FM_OUTSB (TL_SHIFT-FM_OUTPUT_BIT) +#define FM_MAXOUT ((1<<(TL_SHIFT-1))-1) +#define FM_MINOUT (-(1<<(TL_SHIFT-1))) + +/* -------------------- local defines , macros --------------------- */ + +/* envelope counter position */ +#define EG_AST 0 /* start of Attack phase */ +#define EG_AED (EG_ENT<>2)&3) +#define OPM_CHAN(N) (N&7) +#define OPM_SLOT(N) ((N>>3)&3) +/* slot number */ +#define SLOT1 0 +#define SLOT2 2 +#define SLOT3 1 +#define SLOT4 3 + +/* bit0 = Right enable , bit1 = Left enable */ +#define OUTD_RIGHT 1 +#define OUTD_LEFT 2 +#define OUTD_CENTER 3 + +/* FM timer model */ +#define FM_TIMER_SINGLE (0) +#define FM_TIMER_INTERVAL (1) + +/* ---------- OPN / OPM one channel ---------- */ +typedef struct fm_slot { + INT32 *DT; /* detune :DT_TABLE[DT] */ + int DT2; /* multiple,Detune2:(DT2<<4)|ML for OPM*/ + int TL; /* total level :TL << 8 */ + UINT8 KSR; /* key scale rate :3-KSR */ + const INT32 *AR; /* attack rate :&AR_TABLE[AR<<1] */ + const INT32 *DR; /* decay rate :&DR_TABLE[DR<<1] */ + const INT32 *SR; /* sustin rate :&DR_TABLE[SR<<1] */ + int SL; /* sustin level :SL_TABLE[SL] */ + const INT32 *RR; /* release rate :&DR_TABLE[RR<<2+2] */ + UINT8 SEG; /* SSG EG type :SSGEG */ + UINT8 ksr; /* key scale rate :kcode>>(3-KSR) */ + UINT32 mul; /* multiple :ML_TABLE[ML] */ + /* Phase Generator */ + UINT32 Cnt; /* frequency count : */ + UINT32 Incr; /* frequency step : */ + /* Envelope Generator */ + void (*eg_next)(struct fm_slot *SLOT); /* pointer of phase handler */ + INT32 evc; /* envelope counter */ + INT32 eve; /* envelope counter end point */ + INT32 evs; /* envelope counter step */ + INT32 evsa; /* envelope step for Attack */ + INT32 evsd; /* envelope step for Decay */ + INT32 evss; /* envelope step for Sustain */ + INT32 evsr; /* envelope step for Release */ + INT32 TLL; /* adjusted TotalLevel */ + /* LFO */ + UINT8 amon; /* AMS enable flag */ + UINT32 ams; /* AMS depth level of this SLOT */ +}FM_SLOT; + +typedef struct fm_chan { + FM_SLOT SLOT[4]; + UINT8 PAN; /* PAN :NONE,LEFT,RIGHT or CENTER */ + UINT8 ALGO; /* Algorythm */ + UINT8 FB; /* shift count of self feed back */ + INT32 op1_out[2]; /* op1 output for beedback */ + /* Algorythm (connection) */ + INT32 *connect1; /* pointer of SLOT1 output */ + INT32 *connect2; /* pointer of SLOT2 output */ + INT32 *connect3; /* pointer of SLOT3 output */ + INT32 *connect4; /* pointer of SLOT4 output */ + /* LFO */ + INT32 pms; /* PMS depth level of channel */ + UINT32 ams; /* AMS depth level of channel */ + /* Phase Generator */ + UINT32 fc; /* fnum,blk :adjusted to sampling rate */ + UINT8 fn_h; /* freq latch : */ + UINT8 kcode; /* key code : */ +} FM_CH; + +/* OPN/OPM common state */ +typedef struct fm_state { + UINT8 index; /* chip index (number of chip) */ + int clock; /* master clock (Hz) */ + int rate; /* sampling rate (Hz) */ + double freqbase; /* frequency base */ + double TimerBase; /* Timer base time */ + UINT8 address; /* address register */ + UINT8 irq; /* interrupt level */ + UINT8 irqmask; /* irq mask */ + UINT8 status; /* status flag */ + UINT32 mode; /* mode CSM / 3SLOT */ + int TA; /* timer a */ + int TAC; /* timer a counter */ + UINT8 TB; /* timer b */ + int TBC; /* timer b counter */ + /* speedup customize */ + /* local time tables */ + INT32 DT_TABLE[8][32]; /* DeTune tables */ + INT32 AR_TABLE[94]; /* Atttack rate tables */ + INT32 DR_TABLE[94]; /* Decay rate tables */ + /* Extention Timer and IRQ handler */ + FM_TIMERHANDLER Timer_Handler; + FM_IRQHANDLER IRQ_Handler; + /* timer model single / interval */ + UINT8 timermodel; +}FM_ST; + +/* -------------------- tables --------------------- */ + +/* sustain lebel table (3db per step) */ +/* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/ +#define SC(db) (int)((db*((3/EG_STEP)*(1< max ) val = max; \ + else if ( val < min ) val = min; \ +} + +/* ----- buffering one of data(STEREO chip) ----- */ +#if FM_STEREO_MIX +/* stereo mixing */ +#define FM_BUFFERING_STEREO \ +{ \ + /* get left & right output with clipping */ \ + out_ch[OUTD_LEFT] += out_ch[OUTD_CENTER]; \ + Limit( out_ch[OUTD_LEFT] , FM_MAXOUT, FM_MINOUT ); \ + out_ch[OUTD_RIGHT] += out_ch[OUTD_CENTER]; \ + Limit( out_ch[OUTD_RIGHT], FM_MAXOUT, FM_MINOUT ); \ + /* buffering */ \ + *bufL++ = out_ch[OUTD_LEFT] >>FM_OUTSB; \ + *bufL++ = out_ch[OUTD_RIGHT]>>FM_OUTSB; \ +} +#else +/* stereo separate */ +#define FM_BUFFERING_STEREO \ +{ \ + /* get left & right output with clipping */ \ + out_ch[OUTD_LEFT] += out_ch[OUTD_CENTER]; \ + Limit( out_ch[OUTD_LEFT] , FM_MAXOUT, FM_MINOUT ); \ + out_ch[OUTD_RIGHT] += out_ch[OUTD_CENTER]; \ + Limit( out_ch[OUTD_RIGHT], FM_MAXOUT, FM_MINOUT ); \ + /* buffering */ \ + bufL[i] = out_ch[OUTD_LEFT] >>FM_OUTSB; \ + bufR[i] = out_ch[OUTD_RIGHT]>>FM_OUTSB; \ +} +#endif + +#if FM_INTERNAL_TIMER +/* ----- internal timer mode , update timer */ +/* ---------- calcrate timer A ---------- */ +#define INTERNAL_TIMER_A(ST,CSM_CH) \ +{ \ + if( ST->TAC && (ST->Timer_Handler==0) ) \ + if( (ST->TAC -= (int)(ST->freqbase*4096)) <= 0 ) \ + { \ + TimerAOver( ST ); \ + /* CSM mode total level latch and auto key on */ \ + if( ST->mode & 0x80 ) \ + CSMKeyControll( CSM_CH ); \ + } \ +} +/* ---------- calcrate timer B ---------- */ +#define INTERNAL_TIMER_B(ST,step) \ +{ \ + if( ST->TBC && (ST->Timer_Handler==0) ) \ + if( (ST->TBC -= (int)(ST->freqbase*4096*step)) <= 0 ) \ + TimerBOver( ST ); \ +} +#else /* FM_INTERNAL_TIMER */ +/* external timer mode */ +#define INTERNAL_TIMER_A(ST,CSM_CH) +#define INTERNAL_TIMER_B(ST,step) +#endif /* FM_INTERNAL_TIMER */ + +/* --------------------- subroutines --------------------- */ +/* status set and IRQ handling */ +static __inline__ void FM_STATUS_SET(FM_ST *ST,int flag) +{ + /* set status flag */ + ST->status |= flag; + if ( !(ST->irq) && (ST->status & ST->irqmask) ) + { + ST->irq = 1; + /* callback user interrupt handler (IRQ is OFF to ON) */ + if(ST->IRQ_Handler) (ST->IRQ_Handler)(ST->index,1); + } +} + +/* status reset and IRQ handling */ +static __inline__ void FM_STATUS_RESET(FM_ST *ST,int flag) +{ + /* reset status flag */ + ST->status &=~flag; + if ( (ST->irq) && !(ST->status & ST->irqmask) ) + { + ST->irq = 0; + /* callback user interrupt handler (IRQ is ON to OFF) */ + if(ST->IRQ_Handler) (ST->IRQ_Handler)(ST->index,0); + } +} + +/* IRQ mask set */ +static __inline__ void FM_IRQMASK_SET(FM_ST *ST,int flag) +{ + ST->irqmask = flag; + /* IRQ handling check */ + FM_STATUS_SET(ST,0); + FM_STATUS_RESET(ST,0); +} + +/* ---------- event hander of Phase Generator ---------- */ + +/* Release end -> stop counter */ +static void FM_EG_Release( FM_SLOT *SLOT ) +{ + SLOT->evc = EG_OFF; + SLOT->eve = EG_OFF+1; + SLOT->evs = 0; +} + +/* SUSTAIN end -> stop counter */ +static void FM_EG_SR( FM_SLOT *SLOT ) +{ + SLOT->evs = 0; + SLOT->evc = EG_OFF; + SLOT->eve = EG_OFF+1; +} + +/* Decay end -> Sustain */ +static void FM_EG_DR( FM_SLOT *SLOT ) +{ + SLOT->eg_next = FM_EG_SR; + SLOT->evc = SLOT->SL; + SLOT->eve = EG_DED; + SLOT->evs = SLOT->evss; +} + +/* Attack end -> Decay */ +static void FM_EG_AR( FM_SLOT *SLOT ) +{ + /* next DR */ + SLOT->eg_next = FM_EG_DR; + SLOT->evc = EG_DST; + SLOT->eve = SLOT->SL; + SLOT->evs = SLOT->evsd; +} + +#if FM_SEG_SUPPORT +static void FM_EG_SSG_SR( FM_SLOT *SLOT ); + +/* SEG down side end */ +static void FM_EG_SSG_DR( FM_SLOT *SLOT ) +{ + if( SLOT->SEG&2){ + /* reverce */ + SLOT->eg_next = FM_EG_SSG_SR; + SLOT->evc = SLOT->SL + (EG_UST - EG_DST); + SLOT->eve = EG_UED; + SLOT->evs = SLOT->evss; + }else{ + /* again */ + SLOT->evc = EG_DST; + } + /* hold */ + if( SLOT->SEG&1) SLOT->evs = 0; +} + +/* SEG upside side end */ +static void FM_EG_SSG_SR( FM_SLOT *SLOT ) +{ + if( SLOT->SEG&2){ + /* reverce */ + SLOT->eg_next = FM_EG_SSG_DR; + SLOT->evc = EG_DST; + SLOT->eve = EG_DED; + SLOT->evs = SLOT->evsd; + }else{ + /* again */ + SLOT->evc = SLOT->SL + (EG_UST - EG_DST); + } + /* hold check */ + if( SLOT->SEG&1) SLOT->evs = 0; +} + +/* SEG Attack end */ +static void FM_EG_SSG_AR( FM_SLOT *SLOT ) +{ + if( SLOT->SEG&4){ /* start direction */ + /* next SSG-SR (upside start ) */ + SLOT->eg_next = FM_EG_SSG_SR; + SLOT->evc = SLOT->SL + (EG_UST - EG_DST); + SLOT->eve = EG_UED; + SLOT->evs = SLOT->evss; + }else{ + /* next SSG-DR (downside start ) */ + SLOT->eg_next = FM_EG_SSG_DR; + SLOT->evc = EG_DST; + SLOT->eve = EG_DED; + SLOT->evs = SLOT->evsd; + } +} +#endif /* FM_SEG_SUPPORT */ + +/* ----- key on of SLOT ----- */ +#define FM_KEY_IS(SLOT) ((SLOT)->eg_next!=FM_EG_Release) + +static __inline__ void FM_KEYON(FM_CH *CH , int s ) +{ + FM_SLOT *SLOT = &CH->SLOT[s]; + if( !FM_KEY_IS(SLOT) ) + { + /* restart Phage Generator */ + SLOT->Cnt = 0; + /* phase -> Attack */ +#if FM_SEG_SUPPORT + if( SLOT->SEG&8 ) SLOT->eg_next = FM_EG_SSG_AR; + else +#endif + SLOT->eg_next = FM_EG_AR; + SLOT->evs = SLOT->evsa; +#if 0 + /* convert decay count to attack count */ + /* --- This caused the problem by credit sound of paper boy. --- */ + SLOT->evc = EG_AST + DRAR_TABLE[ENV_CURVE[SLOT->evc>>ENV_BITS]];/* + SLOT->evs;*/ +#else + /* reset attack counter */ + SLOT->evc = EG_AST; +#endif + SLOT->eve = EG_AED; + } +} +/* ----- key off of SLOT ----- */ +static __inline__ void FM_KEYOFF(FM_CH *CH , int s ) +{ + FM_SLOT *SLOT = &CH->SLOT[s]; + if( FM_KEY_IS(SLOT) ) + { + /* if Attack phase then adjust envelope counter */ + if( SLOT->evc < EG_DST ) + SLOT->evc = (ENV_CURVE[SLOT->evc>>ENV_BITS]< Release */ + SLOT->eg_next = FM_EG_Release; + SLOT->eve = EG_DED; + SLOT->evs = SLOT->evsr; + } +} + +/* setup Algorythm and PAN connection */ +static void setup_connection( FM_CH *CH ) +{ + INT32 *carrier = &out_ch[CH->PAN]; /* NONE,LEFT,RIGHT or CENTER */ + + switch( CH->ALGO ){ + case 0: + /* PG---S1---S2---S3---S4---OUT */ + CH->connect1 = &pg_in2; + CH->connect2 = &pg_in3; + CH->connect3 = &pg_in4; + break; + case 1: + /* PG---S1-+-S3---S4---OUT */ + /* PG---S2-+ */ + CH->connect1 = &pg_in3; + CH->connect2 = &pg_in3; + CH->connect3 = &pg_in4; + break; + case 2: + /* PG---S1------+-S4---OUT */ + /* PG---S2---S3-+ */ + CH->connect1 = &pg_in4; + CH->connect2 = &pg_in3; + CH->connect3 = &pg_in4; + break; + case 3: + /* PG---S1---S2-+-S4---OUT */ + /* PG---S3------+ */ + CH->connect1 = &pg_in2; + CH->connect2 = &pg_in4; + CH->connect3 = &pg_in4; + break; + case 4: + /* PG---S1---S2-+--OUT */ + /* PG---S3---S4-+ */ + CH->connect1 = &pg_in2; + CH->connect2 = carrier; + CH->connect3 = &pg_in4; + break; + case 5: + /* +-S2-+ */ + /* PG---S1-+-S3-+-OUT */ + /* +-S4-+ */ + CH->connect1 = 0; /* special case */ + CH->connect2 = carrier; + CH->connect3 = carrier; + break; + case 6: + /* PG---S1---S2-+ */ + /* PG--------S3-+-OUT */ + /* PG--------S4-+ */ + CH->connect1 = &pg_in2; + CH->connect2 = carrier; + CH->connect3 = carrier; + break; + case 7: + /* PG---S1-+ */ + /* PG---S2-+-OUT */ + /* PG---S3-+ */ + /* PG---S4-+ */ + CH->connect1 = carrier; + CH->connect2 = carrier; + CH->connect3 = carrier; + } + CH->connect4 = carrier; +} + +/* set detune & multiple */ +static __inline__ void set_det_mul(FM_ST *ST,FM_CH *CH,FM_SLOT *SLOT,int v) +{ + SLOT->mul = MUL_TABLE[v&0x0f]; + SLOT->DT = ST->DT_TABLE[(v>>4)&7]; + CH->SLOT[SLOT1].Incr=-1; +} + +/* set total level */ +static __inline__ void set_tl(FM_CH *CH,FM_SLOT *SLOT , int v,int csmflag) +{ + v &= 0x7f; + v = (v<<7)|v; /* 7bit -> 14bit */ + SLOT->TL = (v*EG_ENT)>>14; + /* if it is not a CSM channel , latch the total level */ + if( !csmflag ) + SLOT->TLL = SLOT->TL; +} + +/* set attack rate & key scale */ +static __inline__ void set_ar_ksr(FM_CH *CH,FM_SLOT *SLOT,int v,INT32 *ar_table) +{ + SLOT->KSR = 3-(v>>6); + SLOT->AR = (v&=0x1f) ? &ar_table[v<<1] : RATE_0; + SLOT->evsa = SLOT->AR[SLOT->ksr]; + if( SLOT->eg_next == FM_EG_AR ) SLOT->evs = SLOT->evsa; + CH->SLOT[SLOT1].Incr=-1; +} +/* set decay rate */ +static __inline__ void set_dr(FM_SLOT *SLOT,int v,INT32 *dr_table) +{ + SLOT->DR = (v&=0x1f) ? &dr_table[v<<1] : RATE_0; + SLOT->evsd = SLOT->DR[SLOT->ksr]; + if( SLOT->eg_next == FM_EG_DR ) SLOT->evs = SLOT->evsd; +} +/* set sustain rate */ +static __inline__ void set_sr(FM_SLOT *SLOT,int v,INT32 *dr_table) +{ + SLOT->SR = (v&=0x1f) ? &dr_table[v<<1] : RATE_0; + SLOT->evss = SLOT->SR[SLOT->ksr]; + if( SLOT->eg_next == FM_EG_SR ) SLOT->evs = SLOT->evss; +} +/* set release rate */ +static __inline__ void set_sl_rr(FM_SLOT *SLOT,int v,INT32 *dr_table) +{ + SLOT->SL = SL_TABLE[(v>>4)]; + SLOT->RR = &dr_table[((v&0x0f)<<2)|2]; + SLOT->evsr = SLOT->RR[SLOT->ksr]; + if( SLOT->eg_next == FM_EG_Release ) SLOT->evs = SLOT->evsr; +} + +/* operator output calcrator */ +#define OP_OUT(PG,EG) SIN_TABLE[(PG/(0x1000000/SIN_ENT))&(SIN_ENT-1)][EG] +#define OP_OUTN(PG,EG) NOISE_TABLE[(PG/(0x1000000/SIN_ENT))&(SIN_ENT-1)][EG] + +/* eg calcration */ +#if FM_LFO_SUPPORT +#define FM_CALC_EG(OUT,SLOT) \ +{ \ + if( (SLOT.evc += SLOT.evs) >= SLOT.eve) \ + SLOT.eg_next(&(SLOT)); \ + OUT = SLOT.TLL+ENV_CURVE[SLOT.evc>>ENV_BITS]; \ + if(SLOT.ams) \ + OUT += (SLOT.ams*lfo_amd/LFO_RATE); \ +} +#else +#define FM_CALC_EG(OUT,SLOT) \ +{ \ + if( (SLOT.evc += SLOT.evs) >= SLOT.eve) \ + SLOT.eg_next(&(SLOT)); \ + OUT = SLOT.TLL+ENV_CURVE[SLOT.evc>>ENV_BITS]; \ +} +#endif + +/* ---------- calcrate one of channel ---------- */ +static __inline__ void FM_CALC_CH( FM_CH *CH ) +{ + UINT32 eg_out1,eg_out2,eg_out3,eg_out4; //envelope output + + /* Phase Generator */ +#if FM_LFO_SUPPORT + INT32 pms = lfo_pmd * CH->pms / LFO_RATE; + if(pms) + { + pg_in1 = (CH->SLOT[SLOT1].Cnt += CH->SLOT[SLOT1].Incr + (INT32)(pms * CH->SLOT[SLOT1].Incr) / PMS_RATE); + pg_in2 = (CH->SLOT[SLOT2].Cnt += CH->SLOT[SLOT2].Incr + (INT32)(pms * CH->SLOT[SLOT2].Incr) / PMS_RATE); + pg_in3 = (CH->SLOT[SLOT3].Cnt += CH->SLOT[SLOT3].Incr + (INT32)(pms * CH->SLOT[SLOT3].Incr) / PMS_RATE); + pg_in4 = (CH->SLOT[SLOT4].Cnt += CH->SLOT[SLOT4].Incr + (INT32)(pms * CH->SLOT[SLOT4].Incr) / PMS_RATE); + } + else +#endif + { + pg_in1 = (CH->SLOT[SLOT1].Cnt += CH->SLOT[SLOT1].Incr); + pg_in2 = (CH->SLOT[SLOT2].Cnt += CH->SLOT[SLOT2].Incr); + pg_in3 = (CH->SLOT[SLOT3].Cnt += CH->SLOT[SLOT3].Incr); + pg_in4 = (CH->SLOT[SLOT4].Cnt += CH->SLOT[SLOT4].Incr); + } + + /* Envelope Generator */ + FM_CALC_EG(eg_out1,CH->SLOT[SLOT1]); + FM_CALC_EG(eg_out2,CH->SLOT[SLOT2]); + FM_CALC_EG(eg_out3,CH->SLOT[SLOT3]); + FM_CALC_EG(eg_out4,CH->SLOT[SLOT4]); + + /* Connection */ + if( eg_out1 < EG_CUT_OFF ) /* SLOT 1 */ + { + if( CH->FB ){ + /* with self feed back */ + pg_in1 += (CH->op1_out[0]+CH->op1_out[1])>>CH->FB; + CH->op1_out[1] = CH->op1_out[0]; + } + CH->op1_out[0] = OP_OUT(pg_in1,eg_out1); + /* output slot1 */ + if( !CH->connect1 ) + { + /* algorythm 5 */ + pg_in2 += CH->op1_out[0]; + pg_in3 += CH->op1_out[0]; + pg_in4 += CH->op1_out[0]; + }else{ + /* other algorythm */ + *CH->connect1 += CH->op1_out[0]; + } + } + if( eg_out2 < EG_CUT_OFF ) /* SLOT 2 */ + *CH->connect2 += OP_OUT(pg_in2,eg_out2); + if( eg_out3 < EG_CUT_OFF ) /* SLOT 3 */ + *CH->connect3 += OP_OUT(pg_in3,eg_out3); + if( eg_out4 < EG_CUT_OFF ) /* SLOT 4 */ + *CH->connect4 += OP_OUT(pg_in4,eg_out4); +} +/* ---------- frequency counter for operater update ---------- */ +static __inline__ void CALC_FCSLOT(FM_SLOT *SLOT , int fc , int kc ) +{ + int ksr; + + /* frequency step counter */ + SLOT->Incr= (fc+SLOT->DT[kc])*SLOT->mul; /* verified on real chip */ + /* SLOT->Incr= fc*SLOT->mul + SLOT->DT[kc]; */ + ksr = kc >> SLOT->KSR; + if( SLOT->ksr != ksr ) + { + SLOT->ksr = ksr; + /* attack , decay rate recalcration */ + SLOT->evsa = SLOT->AR[ksr]; + SLOT->evsd = SLOT->DR[ksr]; + SLOT->evss = SLOT->SR[ksr]; + SLOT->evsr = SLOT->RR[ksr]; + } +} + +/* ---------- frequency counter ---------- */ +static __inline__ void OPN_CALC_FCOUNT(FM_CH *CH ) +{ + if( CH->SLOT[SLOT1].Incr==-1){ + int fc = CH->fc; + int kc = CH->kcode; + CALC_FCSLOT(&CH->SLOT[SLOT1] , fc , kc ); + CALC_FCSLOT(&CH->SLOT[SLOT2] , fc , kc ); + CALC_FCSLOT(&CH->SLOT[SLOT3] , fc , kc ); + CALC_FCSLOT(&CH->SLOT[SLOT4] , fc , kc ); + } +} + +/* ----------- initialize time tabls ----------- */ +static void init_timetables( FM_ST *ST , UINT8 *DTTABLE , int ARRATE , int DRRATE ) +{ + int i,d; + double rate; + + /* DeTune table */ + for (d = 0;d <= 3;d++){ + for (i = 0;i <= 31;i++){ + rate = (double)DTTABLE[d*32 + i] * ST->freqbase * FREQ_RATE; + ST->DT_TABLE[d][i] = (INT32) rate; + ST->DT_TABLE[d+4][i] = (INT32)-rate; + } + } + /* make Attack & Decay tables */ + for (i = 0;i < 4;i++) ST->AR_TABLE[i] = ST->DR_TABLE[i] = 0; + for (i = 4;i < 64;i++){ + rate = ST->freqbase; /* frequency rate */ + if( i < 60 ) rate *= 1.0+(i&3)*0.25; /* b0-1 : x1 , x1.25 , x1.5 , x1.75 */ + rate *= 1<<((i>>2)-1); /* b2-5 : shift bit */ + rate *= (double)(EG_ENT<AR_TABLE[i] = (INT32)(rate / ARRATE); + ST->DR_TABLE[i] = (INT32)(rate / DRRATE); + } + ST->AR_TABLE[62] = EG_AED; + ST->AR_TABLE[63] = EG_AED; + for (i = 64;i < 94 ;i++){ /* make for overflow area */ + ST->AR_TABLE[i] = ST->AR_TABLE[63]; + ST->DR_TABLE[i] = ST->DR_TABLE[63]; + } + +} + +/* ---------- reset one of channel ---------- */ +static void reset_channel( FM_ST *ST , FM_CH *CH , int chan ) +{ + int c,s; + + ST->mode = 0; /* normal mode */ + FM_STATUS_RESET(ST,0xff); + ST->TA = 0; + ST->TAC = 0; + ST->TB = 0; + ST->TBC = 0; + + for( c = 0 ; c < chan ; c++ ) + { + CH[c].fc = 0; + CH[c].PAN = OUTD_CENTER; + for(s = 0 ; s < 4 ; s++ ) + { + CH[c].SLOT[s].SEG = 0; + CH[c].SLOT[s].eg_next= FM_EG_Release; + CH[c].SLOT[s].evc = EG_OFF; + CH[c].SLOT[s].eve = EG_OFF+1; + CH[c].SLOT[s].evs = 0; + } + } +} + + +/* ---------- generic table initialize ---------- */ +static int FMInitTable( void ) +{ + int s,t; + double rate; + int i,j; + double pom; + + /* allocate total level table plus+minus section */ + TL_TABLE = (INT32 *)emu_Malloc(2*TL_MAX*sizeof(int)); + if( TL_TABLE == 0 ) return 0; + /* make total level table */ + for (t = 0;t < TL_MAX ;t++){ + if(t >= PG_CUT_OFF) + rate = 0; /* under cut off area */ + else + rate = ((1< voltage */ + TL_TABLE[ t] = (int)rate; + TL_TABLE[TL_MAX+t] = -TL_TABLE[t]; + } + + /* make sinwave table (pointer of total level) */ + for (s = 1;s <= SIN_ENT/4;s++){ + pom = sin(2.0*PI*s/SIN_ENT); /* sin */ + pom = 20*log10(1/pom); /* -> decibel */ + j = (int)(pom / EG_STEP); /* TL_TABLE steps */ + /* cut off check */ + if(j > PG_CUT_OFF) + j = PG_CUT_OFF; + /* degree 0 - 90 , degree 180 - 90 : plus section */ + SIN_TABLE[ s] = SIN_TABLE[SIN_ENT/2-s] = &TL_TABLE[j]; + /* degree 180 - 270 , degree 360 - 270 : minus section */ + SIN_TABLE[SIN_ENT/2+s] = SIN_TABLE[SIN_ENT -s] = &TL_TABLE[TL_MAX+j]; + + } + /* degree 0 = degree 180 = off */ + SIN_TABLE[0] = SIN_TABLE[SIN_ENT/2] = &TL_TABLE[PG_CUT_OFF]; + + /* envelope counter -> envelope output table */ + for (i=0; i= EG_ENT ) pom = EG_ENT-1; */ + ENV_CURVE[i] = (int)pom; + /* DECAY ,RELEASE curve */ + ENV_CURVE[(EG_DST>>ENV_BITS)+i]= i; +#if FM_SEG_SUPPORT + /* DECAY UPSIDE (SSG ENV) */ + ENV_CURVE[(EG_UST>>ENV_BITS)+i]= EG_ENT-1-i; +#endif + } + /* off */ + ENV_CURVE[EG_OFF>>ENV_BITS]= EG_ENT-1; + + /* decay to reattack envelope converttable */ + j = EG_ENT-1; + for (i=0; imode = v; + + /* reset Timer b flag */ + if( v & 0x20 ) + FM_STATUS_RESET(ST,0x02); + /* reset Timer a flag */ + if( v & 0x10 ) + FM_STATUS_RESET(ST,0x01); + /* load b */ + if( v & 0x02 ) + { + if( ST->TBC == 0 ) + { + ST->TBC = ( 256-ST->TB)<<4; + /* External timer handler */ + if (ST->Timer_Handler) (ST->Timer_Handler)(n,1,ST->TBC,ST->TimerBase); + } + }else if (ST->timermodel == FM_TIMER_INTERVAL) + { /* stop interbval timer */ + if( ST->TBC != 0 ) + { + ST->TBC = 0; + if (ST->Timer_Handler) (ST->Timer_Handler)(n,1,0,ST->TimerBase); + } + } + /* load a */ + if( v & 0x01 ) + { + if( ST->TAC == 0 ) + { + ST->TAC = (1024-ST->TA); + /* External timer handler */ + if (ST->Timer_Handler) (ST->Timer_Handler)(n,0,ST->TAC,ST->TimerBase); + } + }else if (ST->timermodel == FM_TIMER_INTERVAL) + { /* stop interbval timer */ + if( ST->TAC != 0 ) + { + ST->TAC = 0; + if (ST->Timer_Handler) (ST->Timer_Handler)(n,0,0,ST->TimerBase); + } + } +} + +/* Timer A Overflow */ +static __inline__ void TimerAOver(FM_ST *ST) +{ + /* status set if enabled */ + if(ST->mode & 0x04) FM_STATUS_SET(ST,0x01); + /* clear or reload the counter */ + if (ST->timermodel == FM_TIMER_INTERVAL) + { + ST->TAC = (1024-ST->TA); + if (ST->Timer_Handler) (ST->Timer_Handler)(ST->index,0,ST->TAC,ST->TimerBase); + } + else ST->TAC = 0; +} +/* Timer B Overflow */ +static __inline__ void TimerBOver(FM_ST *ST) +{ + /* status set if enabled */ + if(ST->mode & 0x08) FM_STATUS_SET(ST,0x02); + /* clear or reload the counter */ + if (ST->timermodel == FM_TIMER_INTERVAL) + { + ST->TBC = ( 256-ST->TB)<<4; + if (ST->Timer_Handler) (ST->Timer_Handler)(ST->index,1,ST->TBC,ST->TimerBase); + } + else ST->TBC = 0; +} +/* CSM Key Controll */ +static __inline__ void CSMKeyControll(FM_CH *CH) +{ + /* all key off */ + /* FM_KEYOFF(CH,SLOT1); */ + /* FM_KEYOFF(CH,SLOT2); */ + /* FM_KEYOFF(CH,SLOT3); */ + /* FM_KEYOFF(CH,SLOT4); */ + /* total level latch */ + CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL; + CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL; + CH->SLOT[SLOT3].TLL = CH->SLOT[SLOT3].TL; + CH->SLOT[SLOT4].TLL = CH->SLOT[SLOT4].TL; + /* all key on */ + FM_KEYON(CH,SLOT1); + FM_KEYON(CH,SLOT2); + FM_KEYON(CH,SLOT3); + FM_KEYON(CH,SLOT4); +} + +#if BUILD_OPN +/***********************************************************/ +/* OPN unit */ +/***********************************************************/ + +/* OPN 3slot struct */ +typedef struct opn_3slot { + UINT32 fc[3]; /* fnum3,blk3 :calcrated */ + UINT8 fn_h[3]; /* freq3 latch */ + UINT8 kcode[3]; /* key code : */ +}FM_3SLOT; + +/* OPN/A/B common state */ +typedef struct opn_f { + UINT8 type; /* chip type */ + FM_ST ST; /* general state */ + FM_3SLOT SL3; /* 3 slot mode state */ + FM_CH *P_CH; /* pointer of CH */ + UINT32 FN_TABLE[2048]; /* fnumber -> increment counter */ +#if FM_LFO_SUPPORT + /* LFO */ + UINT32 LFOCnt; + UINT32 LFOIncr; + UINT32 LFO_FREQ[8];/* LFO FREQ table */ +#endif +} FM_OPN; + +/* OPN key frequency number -> key code follow table */ +/* fnum higher 4bit -> keycode lower 2bit */ +static const UINT8 OPN_FKTABLE[16]={0,0,0,0,0,0,0,1,2,3,3,3,3,3,3,3}; + +#if FM_LFO_SUPPORT +/* OPN LFO waveform table */ +static INT32 OPN_LFO_wave[LFO_ENT]; +#endif + +static int OPNInitTable(void) +{ + int i; + +#if FM_LFO_SUPPORT + /* LFO wave table */ + for(i=0;iST.freqbase = (OPN->ST.rate) ? ((double)OPN->ST.clock / OPN->ST.rate) / pris : 0; + /* Timer base time */ + OPN->ST.TimerBase = 1.0/((double)OPN->ST.clock / (double)TimerPris); +// /* SSG part priscaler set */ +// if( SSGpris ) SSGClk( OPN->ST.index, OPN->ST.clock * 2 / SSGpris ); + /* make time tables */ + init_timetables( &OPN->ST , OPN_DTTABLE , OPN_ARRATE , OPN_DRRATE ); + /* make fnumber -> increment counter table */ + for( i=0 ; i < 2048 ; i++ ) + { + /* it is freq table for octave 7 */ + /* opn freq counter = 20bit */ + OPN->FN_TABLE[i] = (UINT32)( (double)i * OPN->ST.freqbase * FREQ_RATE * (1<<7) / 2 ); + } +#if FM_LFO_SUPPORT + /* LFO freq. table */ + { + /* 3.98Hz,5.56Hz,6.02Hz,6.37Hz,6.88Hz,9.63Hz,48.1Hz,72.2Hz @ 8MHz */ +#define FM_LF(Hz) ((double)LFO_ENT*(1<LFO_FREQ[i] = (UINT32)(freq_table[i] * OPN->ST.freqbase); + } + } +#endif + +} + +/* ---------- write a OPN mode register 0x20-0x2f ---------- */ +static void OPNWriteMode(FM_OPN *OPN, int r, int v) +{ + UINT8 c; + FM_CH *CH; + + switch(r){ + case 0x21: /* Test */ + break; +#if FM_LFO_SUPPORT + case 0x22: /* LFO FREQ (YM2608/YM2612) */ + if( OPN->type & TYPE_LFOPAN ) + { + OPN->LFOIncr = (v&0x08) ? OPN->LFO_FREQ[v&7] : 0; + cur_chip = NULL; + } + break; +#endif + case 0x24: /* timer A High 8*/ + OPN->ST.TA = (OPN->ST.TA & 0x03)|(((int)v)<<2); + break; + case 0x25: /* timer A Low 2*/ + OPN->ST.TA = (OPN->ST.TA & 0x3fc)|(v&3); + break; + case 0x26: /* timer B */ + OPN->ST.TB = v; + break; + case 0x27: /* mode , timer controll */ + FMSetMode( &(OPN->ST),OPN->ST.index,v ); + break; + case 0x28: /* key on / off */ + c = v&0x03; + if( c == 3 ) break; + if( (v&0x04) && (OPN->type & TYPE_6CH) ) c+=3; + CH = OPN->P_CH; + CH = &CH[c]; + /* csm mode */ + /* if( c == 2 && (OPN->ST.mode & 0x80) ) break; */ + if(v&0x10) FM_KEYON(CH,SLOT1); else FM_KEYOFF(CH,SLOT1); + if(v&0x20) FM_KEYON(CH,SLOT2); else FM_KEYOFF(CH,SLOT2); + if(v&0x40) FM_KEYON(CH,SLOT3); else FM_KEYOFF(CH,SLOT3); + if(v&0x80) FM_KEYON(CH,SLOT4); else FM_KEYOFF(CH,SLOT4); + + break; + } +} + +/* ---------- write a OPN register (0x30-0xff) ---------- */ +static void OPNWriteReg(FM_OPN *OPN, int r, int v) +{ + UINT8 c; + FM_CH *CH; + FM_SLOT *SLOT; + + /* 0x30 - 0xff */ + if( (c = OPN_CHAN(r)) == 3 ) return; /* 0xX3,0xX7,0xXB,0xXF */ + if( (r >= 0x100) /* && (OPN->type & TYPE_6CH) */ ) c+=3; + CH = OPN->P_CH; + CH = &CH[c]; + + SLOT = &(CH->SLOT[OPN_SLOT(r)]); + switch( r & 0xf0 ) { + case 0x30: /* DET , MUL */ + set_det_mul(&OPN->ST,CH,SLOT,v); + break; + case 0x40: /* TL */ + set_tl(CH,SLOT,v,(c == 2) && (OPN->ST.mode & 0x80) ); + break; + case 0x50: /* KS, AR */ + set_ar_ksr(CH,SLOT,v,OPN->ST.AR_TABLE); + break; + case 0x60: /* DR */ + /* bit7 = AMS_ON ENABLE(YM2612) */ + set_dr(SLOT,v,OPN->ST.DR_TABLE); +#if FM_LFO_SUPPORT + if( OPN->type & TYPE_LFOPAN) + { + SLOT->amon = v>>7; + SLOT->ams = CH->ams * SLOT->amon; + } +#endif + break; + case 0x70: /* SR */ + set_sr(SLOT,v,OPN->ST.DR_TABLE); + break; + case 0x80: /* SL, RR */ + set_sl_rr(SLOT,v,OPN->ST.DR_TABLE); + break; + case 0x90: /* SSG-EG */ + SLOT->SEG = v&0x0f; + break; + case 0xa0: + switch( OPN_SLOT(r) ){ + case 0: /* 0xa0-0xa2 : FNUM1 */ + { + UINT32 fn = (((UINT32)( (CH->fn_h)&7))<<8) + v; + UINT8 blk = CH->fn_h>>3; + /* make keyscale code */ + CH->kcode = (blk<<2)|OPN_FKTABLE[(fn>>7)]; + /* make basic increment counter 32bit = 1 cycle */ + CH->fc = OPN->FN_TABLE[fn]>>(7-blk); + CH->SLOT[SLOT1].Incr=-1; + } + break; + case 1: /* 0xa4-0xa6 : FNUM2,BLK */ + CH->fn_h = v&0x3f; + break; + case 2: /* 0xa8-0xaa : 3CH FNUM1 */ + if( r < 0x100) + { + UINT32 fn = (((UINT32)(OPN->SL3.fn_h[c]&7))<<8) + v; + UINT8 blk = OPN->SL3.fn_h[c]>>3; + /* make keyscale code */ + OPN->SL3.kcode[c]= (blk<<2)|OPN_FKTABLE[(fn>>7)]; + /* make basic increment counter 32bit = 1 cycle */ + OPN->SL3.fc[c] = OPN->FN_TABLE[fn]>>(7-blk); + (OPN->P_CH)[2].SLOT[SLOT1].Incr=-1; + } + break; + case 3: /* 0xac-0xae : 3CH FNUM2,BLK */ + if( r < 0x100) + OPN->SL3.fn_h[c] = v&0x3f; + break; + } + break; + case 0xb0: + switch( OPN_SLOT(r) ){ + case 0: /* 0xb0-0xb2 : FB,ALGO */ + { + int feedback = (v>>3)&7; + CH->ALGO = v&7; + CH->FB = feedback ? 8+1 - feedback : 0; + setup_connection( CH ); + } + break; + case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (YM2612/YM2608) */ + if( OPN->type & TYPE_LFOPAN) + { +#if FM_LFO_SUPPORT + /* b0-2 PMS */ + /* 0,3.4,6.7,10,14,20,40,80(cent) */ + static const double pmd_table[8]={0,3.4,6.7,10,14,20,40,80}; + static const int amd_table[4]={(int)(0/EG_STEP),(int)(1.4/EG_STEP),(int)(5.9/EG_STEP),(int)(11.8/EG_STEP) }; + CH->pms = (INT32)( (1.5/1200.0)*pmd_table[v & 7] * PMS_RATE); + /* b4-5 AMS */ + /* 0 , 1.4 , 5.9 , 11.8(dB) */ + CH->ams = amd_table[(v>>4) & 0x03]; + CH->SLOT[SLOT1].ams = CH->ams * CH->SLOT[SLOT1].amon; + CH->SLOT[SLOT2].ams = CH->ams * CH->SLOT[SLOT2].amon; + CH->SLOT[SLOT3].ams = CH->ams * CH->SLOT[SLOT3].amon; + CH->SLOT[SLOT4].ams = CH->ams * CH->SLOT[SLOT4].amon; +#endif + /* PAN */ + CH->PAN = (v>>6)&0x03; /* PAN : b6 = R , b7 = L */ + setup_connection( CH ); + + } + break; + } + break; + } +} +#endif /* BUILD_OPN */ + +#if BUILD_YM2612 +/*******************************************************************************/ +/* YM2612 local section */ +/*******************************************************************************/ +/* here's the virtual YM2612 */ +typedef struct ym2612_f { + FM_OPN OPN; /* OPN state */ + FM_CH CH[6]; /* channel state */ + int address1; /* address register1 */ + /* dac output (YM2612) */ + int dacen; + int dacout; +} YM2612; + +static int YM2612NumChips; /* total chip */ +static YM2612 *FM2612=NULL; /* array of YM2612's */ + +static int dacen; + +/* ---------- update one of chip ----------- */ +void YM2612UpdateOne(int num, INT16 **buffer, int length) +{ + YM2612 *F2612 = &(FM2612[num]); + FM_OPN *OPN = &(FM2612[num].OPN); + int i; + FM_CH *ch,*ech; + FMSAMPLE *bufL,*bufR; + int dacout = F2612->dacout; + + /* set bufer */ + bufL = buffer[0]; + bufR = buffer[1]; + + if( (void *)F2612 != cur_chip ){ + cur_chip = (void *)F2612; + + State = &OPN->ST; + cch[0] = &F2612->CH[0]; + cch[1] = &F2612->CH[1]; + cch[2] = &F2612->CH[2]; + cch[3] = &F2612->CH[3]; + cch[4] = &F2612->CH[4]; + cch[5] = &F2612->CH[5]; + /* DAC mode */ + dacen = F2612->dacen; +#if FM_LFO_SUPPORT + LFOCnt = OPN->LFOCnt; + LFOIncr = OPN->LFOIncr; + if( !LFOIncr ) lfo_amd = lfo_pmd = 0; +#endif + } + /* update frequency counter */ + OPN_CALC_FCOUNT( cch[0] ); + OPN_CALC_FCOUNT( cch[1] ); + if( (State->mode & 0xc0) ){ + /* 3SLOT MODE */ + if( cch[2]->SLOT[SLOT1].Incr==-1){ + /* 3 slot mode */ + CALC_FCSLOT(&cch[2]->SLOT[SLOT1] , OPN->SL3.fc[1] , OPN->SL3.kcode[1] ); + CALC_FCSLOT(&cch[2]->SLOT[SLOT2] , OPN->SL3.fc[2] , OPN->SL3.kcode[2] ); + CALC_FCSLOT(&cch[2]->SLOT[SLOT3] , OPN->SL3.fc[0] , OPN->SL3.kcode[0] ); + CALC_FCSLOT(&cch[2]->SLOT[SLOT4] , cch[2]->fc , cch[2]->kcode ); + } + }else OPN_CALC_FCOUNT( cch[2] ); + OPN_CALC_FCOUNT( cch[3] ); + OPN_CALC_FCOUNT( cch[4] ); + OPN_CALC_FCOUNT( cch[5] ); + + ech = dacen ? cch[4] : cch[5]; + /* buffering */ + for( i=0; i < length ; i++ ) + { +#if FM_LFO_SUPPORT + /* LFO */ + if( LFOIncr ) + { + lfo_amd = OPN_LFO_wave[(LFOCnt+=LFOIncr)>>LFO_SHIFT]; + lfo_pmd = lfo_amd-(LFO_RATE/2); + } +#endif + /* clear output acc. */ + out_ch[OUTD_LEFT] = out_ch[OUTD_RIGHT]= out_ch[OUTD_CENTER] = 0; + /* calcrate channel output */ + for(ch = cch[0] ; ch <= ech ; ch++) + FM_CALC_CH( ch ); + if( dacen ) *cch[5]->connect4 += dacout; + /* buffering */ + FM_BUFFERING_STEREO; + /* timer A controll */ + INTERNAL_TIMER_A( State , cch[2] ) + } + INTERNAL_TIMER_B(State,length) +#if FM_LFO_SUPPORT + OPN->LFOCnt = LFOCnt; +#endif +} + +/* -------------------------- YM2612 ---------------------------------- */ +int YM2612Init(int num, int clock, int rate, + FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler) +{ + int i; + + if (FM2612) return (-1); /* duplicate init. */ + cur_chip = NULL; /* hiro-shi!! */ + + YM2612NumChips = num; + + /* allocate extend state space */ + if( (FM2612 = (YM2612 *)emu_Malloc(sizeof(YM2612) * YM2612NumChips))==NULL) + return (-1); + /* clear */ + memset(FM2612,0,sizeof(YM2612) * YM2612NumChips); + /* allocate total level table (128kb space) */ + if( !OPNInitTable() ) + { + emu_Free( FM2612 ); + return (-1); + } + + for ( i = 0 ; i < YM2612NumChips; i++ ) { + FM2612[i].OPN.ST.index = i; + FM2612[i].OPN.type = TYPE_YM2612; + FM2612[i].OPN.P_CH = FM2612[i].CH; + FM2612[i].OPN.ST.clock = clock; + FM2612[i].OPN.ST.rate = rate; + /* FM2612[i].OPN.ST.irq = 0; */ + /* FM2612[i].OPN.ST.status = 0; */ + FM2612[i].OPN.ST.timermodel = FM_TIMER_INTERVAL; + /* Extend handler */ + FM2612[i].OPN.ST.Timer_Handler = TimerHandler; + FM2612[i].OPN.ST.IRQ_Handler = IRQHandler; + YM2612ResetChip(i); + } + return 0; +} + +/* ---------- shut down emurator ----------- */ +void YM2612Shutdown() +{ + if (!FM2612) return; + + FMCloseTable(); + emu_Free(FM2612); + FM2612 = NULL; +} + +/* ---------- reset one of chip ---------- */ +void YM2612ResetChip(int num) +{ + int i; + YM2612 *F2612 = &(FM2612[num]); + FM_OPN *OPN = &(FM2612[num].OPN); + + OPNSetPris( OPN , 12*12, 12*12, 0); + /* status clear */ + FM_IRQMASK_SET(&OPN->ST,0x03); + OPNWriteMode(OPN,0x27,0x30); /* mode 0 , timer reset */ + + reset_channel( &OPN->ST , &F2612->CH[0] , 6 ); + + for(i = 0xb6 ; i >= 0xb4 ; i-- ) + { + OPNWriteReg(OPN,i ,0xc0); + OPNWriteReg(OPN,i|0x100,0xc0); + } + for(i = 0xb2 ; i >= 0x30 ; i-- ) + { + OPNWriteReg(OPN,i ,0); + OPNWriteReg(OPN,i|0x100,0); + } + for(i = 0x26 ; i >= 0x20 ; i-- ) OPNWriteReg(OPN,i,0); + /* DAC mode clear */ + F2612->dacen = 0; +} + +/* YM2612 write */ +/* n = number */ +/* a = address */ +/* v = value */ +int YM2612Write(int n, int a,UINT8 v) +{ + YM2612 *F2612 = &(FM2612[n]); + int addr; + + switch( a&3){ + case 0: /* address port 0 */ + F2612->OPN.ST.address = v & 0xff; + break; + case 1: /* data port 0 */ + addr = F2612->OPN.ST.address; + switch( addr & 0xf0 ) + { + case 0x20: /* 0x20-0x2f Mode */ + switch( addr ) + { + case 0x2a: /* DAC data (YM2612) */ + F2612->dacout = ((int)v - 0x80)<<(TL_BITS-7); + F2612->dacout = ((int)(v/2)-0x80)<<(TL_BITS-7); + break; + case 0x2b: /* DAC Sel (YM2612) */ + /* b7 = dac enable */ + F2612->dacen = v & 0x80; + cur_chip = NULL; + break; + default: /* OPN section */ + /* write register */ + OPNWriteMode(&(F2612->OPN),addr,v); + } + break; + default: /* 0x30-0xff OPN section */ + /* write register */ + OPNWriteReg(&(F2612->OPN),addr,v); + } + break; + case 2: /* address port 1 */ + F2612->address1 = v & 0xff; + break; + case 3: /* data port 1 */ + addr = F2612->address1; + OPNWriteReg(&(F2612->OPN),addr|0x100,v); + break; + } + return F2612->OPN.ST.irq; +} +UINT8 YM2612Read(int n,int a) +{ + YM2612 *F2612 = &(FM2612[n]); + + switch( a&3){ + case 0: /* status 0 */ + return F2612->OPN.ST.status; + case 1: + case 2: + case 3: + return F2612->OPN.ST.status; + } + return 0; +} + +int YM2612TimerOver(int n,int c) +{ + YM2612 *F2612 = &(FM2612[n]); + + if( c ) + { /* Timer B */ + TimerBOver( &(F2612->OPN.ST) ); + } + else + { /* Timer A */ + /* timer update */ + TimerAOver( &(F2612->OPN.ST) ); + /* CSM mode key,TL controll */ + if( F2612->OPN.ST.mode & 0x80 ) + { /* CSM mode total level latch and auto key on */ + CSMKeyControll( &(F2612->CH[2]) ); + } + } + return F2612->OPN.ST.irq; +} + +#endif /* BUILD_YM2612 */ diff --git a/MCUME_teensy/teensygen/fm.h b/MCUME_teensy/teensygen/fm.h new file mode 100644 index 0000000..8e47af0 --- /dev/null +++ b/MCUME_teensy/teensygen/fm.h @@ -0,0 +1,181 @@ + +#ifndef _H_FM_FM_ +#define _H_FM_FM_ + +#define HAS_YM2612 1 + +#define BUILD_YM2612 (HAS_YM2612 || HAS_YM3438) + +#define FM_STEREO_MIX 0 +#define FM_OUTPUT_BIT 16 +#define FM_INTERNAL_TIMER 0 + +#define FM_LFO_SUPPORT 1 +#define FM_SEG_SUPPORT 0 + +#if BUILD_YM2612 + /* in 2612intf.c */ + #define YM2612UpdateReq(chip) YM2612UpdateRequest(chip); +#endif + +/* compiler dependence */ +#ifndef OSD_CPU_H +#define OSD_CPU_H +typedef unsigned char UINT8; /* unsigned 8bit */ +typedef unsigned short UINT16; /* unsigned 16bit */ +typedef unsigned int UINT32; /* unsigned 32bit */ +typedef signed char INT8; /* signed 8bit */ +typedef signed short INT16; /* signed 16bit */ +typedef signed int INT32; /* signed 32bit */ +#endif + +#define YM2203_NUMBUF 1 +#if FM_STEREO_MIX + #define YM2151_NUMBUF 1 + #define YM2608_NUMBUF 1 + #define YM2612_NUMBUF 1 + #define YM2610_NUMBUF 1 +#else + #define YM2151_NUMBUF 2 /* FM L+R */ + #define YM2608_NUMBUF 2 /* FM L+R+ADPCM+RYTHM */ + #define YM2610_NUMBUF 2 /* FM L+R+ADPCMA+ADPCMB */ + #define YM2612_NUMBUF 2 /* FM L+R */ +#endif + +#if (FM_OUTPUT_BIT==16) +typedef INT16 FMSAMPLE; +typedef unsigned long FMSAMPLE_MIX; +#endif +#if (FM_OUTPUT_BIT==8) +typedef unsigned char FMSAMPLE; +typedef unsigned short FMSAMPLE_MIX; +#endif + +typedef void (*FM_TIMERHANDLER)(int n,int c,int cnt,double stepTime); +typedef void (*FM_IRQHANDLER)(int n,int irq); +/* FM_TIMERHANDLER : Stop or Start timer */ +/* int n = chip number */ +/* int c = Channel 0=TimerA,1=TimerB */ +/* int count = timer count (0=stop) */ +/* doube stepTime = step time of one count (sec.)*/ + +/* FM_IRQHHANDLER : IRQ level changing sense */ +/* int n = chip number */ +/* int irq = IRQ level 0=OFF,1=ON */ + +#if BUILD_YM2203 +/* -------------------- YM2203(OPN) Interface -------------------- */ + +/* +** Initialize YM2203 emulator(s). +** +** 'num' is the number of virtual YM2203's to allocate +** 'baseclock' +** 'rate' is sampling rate +** 'TimerHandler' timer callback handler when timer start and clear +** 'IRQHandler' IRQ callback handler when changed IRQ level +** return 0 = success +*/ +int YM2203Init(int num, int baseclock, int rate, + FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler); + +/* +** shutdown the YM2203 emulators .. make sure that no sound system stuff +** is touching our audio buffers ... +*/ +void YM2203Shutdown(void); + +/* +** reset all chip registers for YM2203 number 'num' +*/ +void YM2203ResetChip(int num); +/* +** update one of chip +*/ + +void YM2203UpdateOne(int num, INT16 *buffer, int length); + +/* +** Write +** return : InterruptLevel +*/ +int YM2203Write(int n,int a,unsigned char v); +/* +** Read +** return : InterruptLevel +*/ +unsigned char YM2203Read(int n,int a); + +/* +** Timer OverFlow +*/ +int YM2203TimerOver(int n, int c); + +#endif /* BUILD_YM2203 */ + +#if BUILD_YM2608 +/* -------------------- YM2608(OPNA) Interface -------------------- */ +int YM2608Init(int num, int baseclock, int rate, + void **pcmroma,int *pcmsizea,short *rhythmrom,int *rhythmpos, + FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler); +void YM2608Shutdown(void); +void YM2608ResetChip(int num); +void YM2608UpdateOne(int num, INT16 **buffer, int length); + +int YM2608Write(int n, int a,unsigned char v); +unsigned char YM2608Read(int n,int a); +int YM2608TimerOver(int n, int c ); +#endif /* BUILD_YM2608 */ + +#if (BUILD_YM2610||BUILD_YM2610B) +/* -------------------- YM2610(OPNB) Interface -------------------- */ +int YM2610Init(int num, int baseclock, int rate, + void **pcmroma,int *pcmasize,void **pcmromb,int *pcmbsize, + FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler); +void YM2610Shutdown(void); +void YM2610ResetChip(int num); +void YM2610UpdateOne(int num, INT16 **buffer, int length); +#if BUILD_YM2610B +void YM2610BUpdateOne(int num, INT16 **buffer, int length); +#endif + +int YM2610Write(int n, int a,unsigned char v); +unsigned char YM2610Read(int n,int a); +int YM2610TimerOver(int n, int c ); + +#endif /* BUILD_YM2610 */ + +#if BUILD_YM2612 +int YM2612Init(int num, int baseclock, int rate, + FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler); +void YM2612Shutdown(void); +void YM2612ResetChip(int num); +void YM2612UpdateOne(int num, INT16 **buffer, int length); +int YM2612Write(int n, int a,unsigned char v); +unsigned char YM2612Read(int n,int a); +int YM2612TimerOver(int n, int c ); + +#endif /* BUILD_YM2612 */ + +#if BUILD_YM2151 +/* -------------------- YM2151(OPM) Interface -------------------- */ +int OPMInit(int num, int baseclock, int rate, + FM_TIMERHANDLER TimerHandler,FM_IRQHANDLER IRQHandler); +void OPMShutdown(void); +void OPMResetChip(int num); + +void OPMUpdateOne(int num, INT16 **buffer, int length ); +/* ---- set callback hander when port CT0/1 write ----- */ +/* CT.bit0 = CT0 , CT.bit1 = CT1 */ +/* +typedef void (*mem_write_handler)(int offset,int data); +*/ +void OPMSetPortHander(int n,mem_write_handler PortWrite); +/* JB 981119 - so it will match MAME's memory write functions scheme*/ + +int YM2151Write(int n,int a,unsigned char v); +unsigned char YM2151Read(int n,int a); +int YM2151TimerOver(int n,int c); +#endif /* BUILD_YM2151 */ + +#endif /* _H_FM_FM_ */ diff --git a/MCUME_teensy/teensygen/font8x8.h b/MCUME_teensy/teensygen/font8x8.h new file mode 100644 index 0000000..2b2ab25 --- /dev/null +++ b/MCUME_teensy/teensygen/font8x8.h @@ -0,0 +1,135 @@ + +// Font: c64_lower.64c + +PROGMEM const unsigned char font8x8[128][8] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0000 (nul) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0001 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0002 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0003 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0004 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0005 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0006 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0007 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0008 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0009 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0010 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0011 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0012 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0013 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0014 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0015 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0016 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0017 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0018 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0019 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0020 (space) + { 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00}, // U+0021 (!) + { 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0022 (") + { 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00}, // U+0023 (#) + { 0x0C, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x0C, 0x00}, // U+0024 ($) + { 0x00, 0x63, 0x33, 0x18, 0x0C, 0x66, 0x63, 0x00}, // U+0025 (%) + { 0x1C, 0x36, 0x1C, 0x6E, 0x3B, 0x33, 0x6E, 0x00}, // U+0026 (&) + { 0x06, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0027 (') + { 0x18, 0x0C, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x00}, // U+0028 (() + { 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06, 0x00}, // U+0029 ()) + { 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00}, // U+002A (*) + { 0x00, 0x0C, 0x0C, 0x3F, 0x0C, 0x0C, 0x00, 0x00}, // U+002B (+) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+002C (,) + { 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00}, // U+002D (-) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+002E (.) + { 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x00}, // U+002F (/) + { 0x3E, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x3E, 0x00}, // U+0030 (0) + { 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x3F, 0x00}, // U+0031 (1) + { 0x1E, 0x33, 0x30, 0x1C, 0x06, 0x33, 0x3F, 0x00}, // U+0032 (2) + { 0x1E, 0x33, 0x30, 0x1C, 0x30, 0x33, 0x1E, 0x00}, // U+0033 (3) + { 0x38, 0x3C, 0x36, 0x33, 0x7F, 0x30, 0x78, 0x00}, // U+0034 (4) + { 0x3F, 0x03, 0x1F, 0x30, 0x30, 0x33, 0x1E, 0x00}, // U+0035 (5) + { 0x1C, 0x06, 0x03, 0x1F, 0x33, 0x33, 0x1E, 0x00}, // U+0036 (6) + { 0x3F, 0x33, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00}, // U+0037 (7) + { 0x1E, 0x33, 0x33, 0x1E, 0x33, 0x33, 0x1E, 0x00}, // U+0038 (8) + { 0x1E, 0x33, 0x33, 0x3E, 0x30, 0x18, 0x0E, 0x00}, // U+0039 (9) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+003A (:) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+003B (//) + { 0x18, 0x0C, 0x06, 0x03, 0x06, 0x0C, 0x18, 0x00}, // U+003C (<) + { 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00}, // U+003D (=) + { 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06, 0x00}, // U+003E (>) + { 0x1E, 0x33, 0x30, 0x18, 0x0C, 0x00, 0x0C, 0x00}, // U+003F (?) + { 0x3E, 0x63, 0x7B, 0x7B, 0x7B, 0x03, 0x1E, 0x00}, // U+0040 (@) + { 0x0C, 0x1E, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x00}, // U+0041 (A) + { 0x3F, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3F, 0x00}, // U+0042 (B) + { 0x3C, 0x66, 0x03, 0x03, 0x03, 0x66, 0x3C, 0x00}, // U+0043 (C) + { 0x1F, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1F, 0x00}, // U+0044 (D) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x46, 0x7F, 0x00}, // U+0045 (E) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x06, 0x0F, 0x00}, // U+0046 (F) + { 0x3C, 0x66, 0x03, 0x03, 0x73, 0x66, 0x7C, 0x00}, // U+0047 (G) + { 0x33, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x33, 0x00}, // U+0048 (H) + { 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0049 (I) + { 0x78, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, 0x00}, // U+004A (J) + { 0x67, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x67, 0x00}, // U+004B (K) + { 0x0F, 0x06, 0x06, 0x06, 0x46, 0x66, 0x7F, 0x00}, // U+004C (L) + { 0x63, 0x77, 0x7F, 0x7F, 0x6B, 0x63, 0x63, 0x00}, // U+004D (M) + { 0x63, 0x67, 0x6F, 0x7B, 0x73, 0x63, 0x63, 0x00}, // U+004E (N) + { 0x1C, 0x36, 0x63, 0x63, 0x63, 0x36, 0x1C, 0x00}, // U+004F (O) + { 0x3F, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x0F, 0x00}, // U+0050 (P) + { 0x1E, 0x33, 0x33, 0x33, 0x3B, 0x1E, 0x38, 0x00}, // U+0051 (Q) + { 0x3F, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x67, 0x00}, // U+0052 (R) + { 0x1E, 0x33, 0x07, 0x0E, 0x38, 0x33, 0x1E, 0x00}, // U+0053 (S) + { 0x3F, 0x2D, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0054 (T) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F, 0x00}, // U+0055 (U) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0056 (V) + { 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00}, // U+0057 (W) + { 0x63, 0x63, 0x36, 0x1C, 0x1C, 0x36, 0x63, 0x00}, // U+0058 (X) + { 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x0C, 0x1E, 0x00}, // U+0059 (Y) + { 0x7F, 0x63, 0x31, 0x18, 0x4C, 0x66, 0x7F, 0x00}, // U+005A (Z) + { 0x1E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1E, 0x00}, // U+005B ([) + { 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00}, // U+005C (\) + { 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00}, // U+005D (]) + { 0x08, 0x1C, 0x36, 0x63, 0x00, 0x00, 0x00, 0x00}, // U+005E (^) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF}, // U+005F (_) + { 0x0C, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0060 (`) + { 0x00, 0x00, 0x1E, 0x30, 0x3E, 0x33, 0x6E, 0x00}, // U+0061 (a) + { 0x07, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3B, 0x00}, // U+0062 (b) + { 0x00, 0x00, 0x1E, 0x33, 0x03, 0x33, 0x1E, 0x00}, // U+0063 (c) + { 0x38, 0x30, 0x30, 0x3e, 0x33, 0x33, 0x6E, 0x00}, // U+0064 (d) + { 0x00, 0x00, 0x1E, 0x33, 0x3f, 0x03, 0x1E, 0x00}, // U+0065 (e) + { 0x1C, 0x36, 0x06, 0x0f, 0x06, 0x06, 0x0F, 0x00}, // U+0066 (f) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0067 (g) + { 0x07, 0x06, 0x36, 0x6E, 0x66, 0x66, 0x67, 0x00}, // U+0068 (h) + { 0x0C, 0x00, 0x0E, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0069 (i) + { 0x30, 0x00, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E}, // U+006A (j) + { 0x07, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x67, 0x00}, // U+006B (k) + { 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+006C (l) + { 0x00, 0x00, 0x33, 0x7F, 0x7F, 0x6B, 0x63, 0x00}, // U+006D (m) + { 0x00, 0x00, 0x1F, 0x33, 0x33, 0x33, 0x33, 0x00}, // U+006E (n) + { 0x00, 0x00, 0x1E, 0x33, 0x33, 0x33, 0x1E, 0x00}, // U+006F (o) + { 0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x0F}, // U+0070 (p) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x78}, // U+0071 (q) + { 0x00, 0x00, 0x3B, 0x6E, 0x66, 0x06, 0x0F, 0x00}, // U+0072 (r) + { 0x00, 0x00, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x00}, // U+0073 (s) + { 0x08, 0x0C, 0x3E, 0x0C, 0x0C, 0x2C, 0x18, 0x00}, // U+0074 (t) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x6E, 0x00}, // U+0075 (u) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0076 (v) + { 0x00, 0x00, 0x63, 0x6B, 0x7F, 0x7F, 0x36, 0x00}, // U+0077 (w) + { 0x00, 0x00, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x00}, // U+0078 (x) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0079 (y) + { 0x00, 0x00, 0x3F, 0x19, 0x0C, 0x26, 0x3F, 0x00}, // U+007A (z) + { 0x38, 0x0C, 0x0C, 0x07, 0x0C, 0x0C, 0x38, 0x00}, // U+007B ({) + { 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00}, // U+007C (|) + { 0x07, 0x0C, 0x0C, 0x38, 0x0C, 0x0C, 0x07, 0x00}, // U+007D (}) + { 0x6E, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+007E (~) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} // U+007F +}; + diff --git a/MCUME_teensy/teensygen/genesis.c b/MCUME_teensy/teensygen/genesis.c new file mode 100644 index 0000000..f1c07dd --- /dev/null +++ b/MCUME_teensy/teensygen/genesis.c @@ -0,0 +1,160 @@ +/* + Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + + +#include "shared.h" + +//uint8 work_ram[0x10000]; /* 68K work RAM */ +//uint8 zram[0x2000]; /* Z80 work RAM */ +uint8 zbusreq; /* /BUSREQ from Z80 */ +uint8 zreset; /* /RESET to Z80 */ +uint8 zbusack; /* /BUSACK to Z80 */ +uint8 zirq; /* /IRQ to Z80 */ +uint32 zbank; /* Address of Z80 bank window */ +uint8 gen_running; + +/*--------------------------------------------------------------------------*/ +/* Init, reset, shutdown functions */ +/*--------------------------------------------------------------------------*/ + +void gen_init(void) +{ + sound_init(); + memset(&snd, 0, sizeof(snd)); + + m68k_set_cpu_type(M68K_CPU_TYPE_68000); + m68k_pulse_reset(); + error("PC:%08X\tSP:%08X\n", m68k_get_reg(NULL,M68K_REG_PC), m68k_get_reg(NULL,M68K_REG_SP)); + gen_running = 1; +} + +void gen_reset(void) +{ + /* Clear RAM */ + memset(work_ram, 0, WORK_RAM_SIZE); + memset(zram, 0, Z_RAM_SIZE); + + gen_running = 1; + zreset = 0; /* Z80 is reset */ + zbusreq = 0; /* Z80 has control of the Z bus */ + zbusack = 1; /* Z80 is busy using the Z bus */ + zbank = 0; /* Assume default bank is 000000-007FFF */ + zirq = 0; /* No interrupts occuring */ + + io_reset(); + + /* Reset the 68000 emulator */ + m68k_pulse_reset(); + error("PC:%08X\tSP:%08X\n", m68k_get_reg(NULL,M68K_REG_PC), m68k_get_reg(NULL,M68K_REG_SP)); + z80_reset(0); + z80_set_irq_callback(z80_irq_callback); +} + +void gen_shutdown(void) +{ + int i; + + /* Print 68K and Z80 state */ + error("\n"); + error("\nPC:%08X\tSP:%08X\tSR:%04X\n", m68k_get_reg(NULL,M68K_REG_PC), m68k_get_reg(NULL,M68K_REG_SP), m68k_get_reg(NULL, M68K_REG_SR)); + for(i=0;i<8;i++) + { + error("D%d:%08X\tA%d:%08X\n", + i, m68k_get_reg(NULL, M68K_REG_D0+i), + i, m68k_get_reg(NULL, M68K_REG_A0+i)); + } + + error("\n"); + error("PC:%04X\tSP:%04X\n", z80_get_reg(Z80_PC), z80_get_reg(Z80_SP)); + error("AF:%04X\tAF:%04X\n", z80_get_reg(Z80_AF), z80_get_reg(Z80_AF2)); + error("BC:%04X\tBC:%04X\n", z80_get_reg(Z80_BC), z80_get_reg(Z80_BC2)); + error("DE:%04X\tDE:%04X\n", z80_get_reg(Z80_DE), z80_get_reg(Z80_DE2)); + error("HL:%04X\tHL:%04X\n", z80_get_reg(Z80_HL), z80_get_reg(Z80_HL2)); + error("IX:%04X\tIY:%04X\n", z80_get_reg(Z80_IX), z80_get_reg(Z80_IY)); + error("\n"); +} + +/*--------------------------------------------------------------------------*/ +/* Bus controller chip functions */ +/*--------------------------------------------------------------------------*/ + +int gen_busack_r(void) +{ + return (zbusack & 1); +} + +void gen_busreq_w(int state) +{ + zbusreq = (state & 1); + zbusack = 1 ^ (zbusreq & zreset); + + if(zbusreq == 0 && zreset == 1) + { + z80_execute(32); + } +} + +void gen_reset_w(int state) +{ + zreset = (state & 1); + zbusack = 1 ^ (zbusreq & zreset); + + if(zreset == 0) + { + if(snd.enabled) + { + YM2612ResetChip(0); + } + + z80_reset(0); + z80_set_irq_callback(z80_irq_callback); + } +} + + +void gen_bank_w(int state) +{ + zbank = ((zbank >> 1) | ((state & 1) << 23)) & 0xFF8000; +} + + + +int z80_irq_callback(int param) +{ + zirq = 0; + z80_set_irq_line(0, CLEAR_LINE); + return 0xFF; +} + +int vdp_int_ack_callback(int int_level) +{ + switch(int_level) + { + case 4: + hint_pending = 0; + break; + + case 6: + status &= ~0x0080; + vint_pending = 0; + break; + } + + return M68K_INT_ACK_AUTOVECTOR; +} + diff --git a/MCUME_teensy/teensygen/genesis.h b/MCUME_teensy/teensygen/genesis.h new file mode 100644 index 0000000..5eca126 --- /dev/null +++ b/MCUME_teensy/teensygen/genesis.h @@ -0,0 +1,28 @@ + +#ifndef _GENESIS_H_ +#define _GENESIS_H_ + +/* Global variables */ +//extern uint8 work_ram[0x10000]; +//extern uint8 zram[0x2000]; +extern uint8 zbusreq; +extern uint8 zbusack; +extern uint8 zreset; +extern uint8 zirq; +extern uint32 zbank; +extern uint8 gen_running; + +/* Function prototypes */ +void gen_init(void); +void gen_reset(void); +void gen_shutdown(void); +int gen_busack_r(void); +void gen_busreq_w(int state); +void gen_reset_w(int state); +void gen_bank_w(int state); +//void bswap(uint8 *mem, int length); +int z80_irq_callback(int param); +void m68k_irq_ack_callback(int int_level); + +#endif /* _GEN_H_ */ + diff --git a/MCUME_teensy/teensygen/genlut.h b/MCUME_teensy/teensygen/genlut.h new file mode 100644 index 0000000..65e5065 --- /dev/null +++ b/MCUME_teensy/teensygen/genlut.h @@ -0,0 +1,20483 @@ +#include "arduinoproto.h" +PROGMEM const uint8 lut_base[327680] = { +0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F, +0x00,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1A,0x1B,0x1C,0x1D,0x1E,0x1F, +0x00,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2A,0x2B,0x2C,0x2D,0x2E,0x2F, +0x00,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F, 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+0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F, +0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F, +0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F, +0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F, +0x7F,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F, +0x7F,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x7F,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F, +0x7F,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0xBF,0x3F, +0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F, +0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F, +0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F, +0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F,0x7F, +0x7F,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,0x4A,0x4B,0x4C,0x4D,0x4E,0x4F, +0x7F,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x7F,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6A,0x6B,0x6C,0x6D,0x6E,0x6F, +0x7F,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,0x7A,0x7B,0x7C,0x7D,0xBF,0x3F, +}; diff --git a/MCUME_teensy/teensygen/hcnt.h b/MCUME_teensy/teensygen/hcnt.h new file mode 100644 index 0000000..ee9f061 --- /dev/null +++ b/MCUME_teensy/teensygen/hcnt.h @@ -0,0 +1,69 @@ +#include "arduinoproto.h" +PROGMEM const uint8 cycle2hc32[488] = +{ + 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x04, 0x04, 0x04, 0x05, + 0x05, 0x05, 0x06, 0x06, 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x09, 0x09, 0x09, 0x0A, 0x0A, 0x0A, + 0x0B, 0x0B, 0x0B, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0E, 0x0E, 0x0E, 0x0F, 0x0F, 0x0F, 0x10, 0x10, + 0x10, 0x11, 0x11, 0x11, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x14, 0x14, 0x15, 0x15, 0x15, 0x16, + 0x16, 0x16, 0x17, 0x17, 0x17, 0x18, 0x18, 0x18, 0x19, 0x19, 0x19, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, + 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, + 0x21, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x24, 0x24, 0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x26, + 0x27, 0x27, 0x27, 0x28, 0x28, 0x29, 0x29, 0x29, 0x2A, 0x2A, 0x2A, 0x2B, 0x2B, 0x2B, 0x2C, 0x2C, + 0x2C, 0x2D, 0x2D, 0x2D, 0x2E, 0x2E, 0x2F, 0x2F, 0x2F, 0x30, 0x30, 0x30, 0x31, 0x31, 0x31, 0x32, + 0x32, 0x32, 0x33, 0x33, 0x33, 0x34, 0x34, 0x34, 0x35, 0x35, 0x36, 0x36, 0x36, 0x37, 0x37, 0x37, + 0x38, 0x38, 0x38, 0x39, 0x39, 0x39, 0x3A, 0x3A, 0x3A, 0x3B, 0x3B, 0x3B, 0x3C, 0x3C, 0x3D, 0x3D, + 0x3D, 0x3E, 0x3E, 0x3E, 0x3F, 0x3F, 0x3F, 0x40, 0x40, 0x40, 0x41, 0x41, 0x41, 0x42, 0x42, 0x42, + 0x43, 0x43, 0x44, 0x44, 0x44, 0x45, 0x45, 0x45, 0x46, 0x46, 0x46, 0x47, 0x47, 0x47, 0x48, 0x48, + 0x48, 0x49, 0x49, 0x4A, 0x4A, 0x4A, 0x4B, 0x4B, 0x4B, 0x4C, 0x4C, 0x4C, 0x4D, 0x4D, 0x4D, 0x4E, + 0x4E, 0x4E, 0x4F, 0x4F, 0x4F, 0x50, 0x50, 0x51, 0x51, 0x51, 0x52, 0x52, 0x52, 0x53, 0x53, 0x53, + 0x54, 0x54, 0x54, 0x55, 0x55, 0x55, 0x56, 0x56, 0x56, 0x57, 0x57, 0x58, 0x58, 0x58, 0x59, 0x59, + 0x59, 0x5A, 0x5A, 0x5A, 0x5B, 0x5B, 0x5B, 0x5C, 0x5C, 0x5C, 0x5D, 0x5D, 0x5E, 0x5E, 0x5E, 0x5F, + 0x5F, 0x5F, 0x60, 0x60, 0x60, 0x61, 0x61, 0x61, 0x62, 0x62, 0x62, 0x63, 0x63, 0x63, 0x64, 0x64, + 0x65, 0x65, 0x65, 0x66, 0x66, 0x66, 0x67, 0x67, 0x67, 0x68, 0x68, 0x68, 0x69, 0x69, 0x69, 0x6A, + 0x6A, 0x6A, 0x6B, 0x6B, 0x6C, 0x6C, 0x6C, 0x6D, 0x6D, 0x6D, 0x6E, 0x6E, 0x6E, 0x6F, 0x6F, 0x6F, + 0x70, 0x70, 0x70, 0x71, 0x71, 0x72, 0x72, 0x72, 0x73, 0x73, 0x73, 0x74, 0x74, 0x74, 0x75, 0x75, + 0x75, 0x76, 0x76, 0x76, 0x77, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x79, 0x7A, 0x7A, 0x7A, 0x7B, + 0x7B, 0x7B, 0x7C, 0x7C, 0x7C, 0x7D, 0x7D, 0x7D, 0x7E, 0x7E, 0x7E, 0x7F, 0x7F, 0x80, 0x80, 0x80, + 0x81, 0x81, 0x81, 0x82, 0x82, 0x82, 0x83, 0x83, 0x83, 0x84, 0x84, 0x84, 0x85, 0x85, 0x85, 0x86, + 0x86, 0x87, 0x87, 0x87, 0x88, 0x88, 0x88, 0x89, 0x89, 0x89, 0x8A, 0x8A, 0x8A, 0x8B, 0x8B, 0x8B, + 0x8C, 0x8C, 0x8D, 0x8D, 0x8D, 0x8E, 0x8E, 0x8E, 0x8F, 0x8F, 0x8F, 0x90, 0x90, 0x90, 0x91, 0x91, + 0x91, 0x92, 0x92, 0x92, 0x93, 0x93, 0xE9, 0xE9, 0xE9, 0xEA, 0xEA, 0xEA, 0xEB, 0xEB, 0xEB, 0xEC, + 0xEC, 0xEC, 0xED, 0xED, 0xED, 0xEE, 0xEE, 0xEE, 0xEF, 0xEF, 0xF0, 0xF0, 0xF0, 0xF1, 0xF1, 0xF1, + 0xF2, 0xF2, 0xF2, 0xF3, 0xF3, 0xF3, 0xF4, 0xF4, 0xF4, 0xF5, 0xF5, 0xF6, 0xF6, 0xF6, 0xF7, 0xF7, + 0xF7, 0xF8, 0xF8, 0xF8, 0xF9, 0xF9, 0xF9, 0xFA, 0xFA, 0xFA, 0xFB, 0xFB, 0xFB, 0xFC, 0xFC, 0xFD, + 0xFD, 0xFD, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, +}; +PROGMEM const uint8 cycle2hc40[488] = +{ + 0x00, 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, 0x06, + 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x09, 0x0A, 0x0A, 0x0B, 0x0B, 0x0C, 0x0C, 0x0C, 0x0D, + 0x0D, 0x0E, 0x0E, 0x0F, 0x0F, 0x10, 0x10, 0x10, 0x11, 0x11, 0x12, 0x12, 0x13, 0x13, 0x13, 0x14, + 0x14, 0x15, 0x15, 0x16, 0x16, 0x16, 0x17, 0x17, 0x18, 0x18, 0x19, 0x19, 0x19, 0x1A, 0x1A, 0x1B, + 0x1B, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1E, 0x1E, 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, 0x21, 0x22, + 0x22, 0x23, 0x23, 0x23, 0x24, 0x24, 0x25, 0x25, 0x26, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, + 0x29, 0x29, 0x2A, 0x2A, 0x2B, 0x2B, 0x2C, 0x2C, 0x2D, 0x2D, 0x2D, 0x2E, 0x2E, 0x2F, 0x2F, 0x30, + 0x30, 0x30, 0x31, 0x31, 0x32, 0x32, 0x33, 0x33, 0x33, 0x34, 0x34, 0x35, 0x35, 0x36, 0x36, 0x36, + 0x37, 0x37, 0x38, 0x38, 0x39, 0x39, 0x39, 0x3A, 0x3A, 0x3B, 0x3B, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D, + 0x3E, 0x3E, 0x3F, 0x3F, 0x40, 0x40, 0x40, 0x41, 0x41, 0x42, 0x42, 0x43, 0x43, 0x43, 0x44, 0x44, + 0x45, 0x45, 0x46, 0x46, 0x46, 0x47, 0x47, 0x48, 0x48, 0x49, 0x49, 0x4A, 0x4A, 0x4A, 0x4B, 0x4B, + 0x4C, 0x4C, 0x4D, 0x4D, 0x4D, 0x4E, 0x4E, 0x4F, 0x4F, 0x50, 0x50, 0x50, 0x51, 0x51, 0x52, 0x52, + 0x53, 0x53, 0x53, 0x54, 0x54, 0x55, 0x55, 0x56, 0x56, 0x56, 0x57, 0x57, 0x58, 0x58, 0x59, 0x59, + 0x5A, 0x5A, 0x5A, 0x5B, 0x5B, 0x5C, 0x5C, 0x5D, 0x5D, 0x5D, 0x5E, 0x5E, 0x5F, 0x5F, 0x60, 0x60, + 0x60, 0x61, 0x61, 0x62, 0x62, 0x63, 0x63, 0x63, 0x64, 0x64, 0x65, 0x65, 0x66, 0x66, 0x67, 0x67, + 0x67, 0x68, 0x68, 0x69, 0x69, 0x6A, 0x6A, 0x6A, 0x6B, 0x6B, 0x6C, 0x6C, 0x6D, 0x6D, 0x6D, 0x6E, + 0x6E, 0x6F, 0x6F, 0x70, 0x70, 0x70, 0x71, 0x71, 0x72, 0x72, 0x73, 0x73, 0x73, 0x74, 0x74, 0x75, + 0x75, 0x76, 0x76, 0x77, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7A, 0x7A, 0x7A, 0x7B, 0x7B, 0x7C, + 0x7C, 0x7D, 0x7D, 0x7D, 0x7E, 0x7E, 0x7F, 0x7F, 0x80, 0x80, 0x80, 0x81, 0x81, 0x82, 0x82, 0x83, + 0x83, 0x84, 0x84, 0x84, 0x85, 0x85, 0x86, 0x86, 0x87, 0x87, 0x87, 0x88, 0x88, 0x89, 0x89, 0x8A, + 0x8A, 0x8A, 0x8B, 0x8B, 0x8C, 0x8C, 0x8D, 0x8D, 0x8D, 0x8E, 0x8E, 0x8F, 0x8F, 0x90, 0x90, 0x90, + 0x91, 0x91, 0x92, 0x92, 0x93, 0x93, 0x94, 0x94, 0x94, 0x95, 0x95, 0x96, 0x96, 0x97, 0x97, 0x97, + 0x98, 0x98, 0x99, 0x99, 0x9A, 0x9A, 0x9A, 0x9B, 0x9B, 0x9C, 0x9C, 0x9D, 0x9D, 0x9D, 0x9E, 0x9E, + 0x9F, 0x9F, 0xA0, 0xA0, 0xA1, 0xA1, 0xA1, 0xA2, 0xA2, 0xA3, 0xA3, 0xA4, 0xA4, 0xA4, 0xA5, 0xA5, + 0xA6, 0xA6, 0xA7, 0xA7, 0xA7, 0xA8, 0xA8, 0xA9, 0xA9, 0xAA, 0xAA, 0xAA, 0xAB, 0xAB, 0xAC, 0xAC, + 0xAD, 0xAD, 0xAD, 0xAE, 0xAE, 0xAF, 0xAF, 0xB0, 0xB0, 0xB1, 0xB1, 0xB1, 0xB2, 0xB2, 0xB3, 0xB3, + 0xB4, 0xB4, 0xB4, 0xB5, 0xB5, 0xB6, 0xB6, 0xE4, 0xE4, 0xE4, 0xE5, 0xE5, 0xE6, 0xE6, 0xE7, 0xE7, + 0xE7, 0xE8, 0xE8, 0xE9, 0xE9, 0xEA, 0xEA, 0xEB, 0xEB, 0xEB, 0xEC, 0xEC, 0xED, 0xED, 0xEE, 0xEE, + 0xEE, 0xEF, 0xEF, 0xF0, 0xF0, 0xF1, 0xF1, 0xF1, 0xF2, 0xF2, 0xF3, 0xF3, 0xF4, 0xF4, 0xF4, 0xF5, + 0xF5, 0xF6, 0xF6, 0xF7, 0xF7, 0xF7, 0xF8, 0xF8, 0xF9, 0xF9, 0xFA, 0xFA, 0xFB, 0xFB, 0xFB, 0xFC, + 0xFC, 0xFD, 0xFD, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, +}; diff --git a/MCUME_teensy/teensygen/hvc.h b/MCUME_teensy/teensygen/hvc.h new file mode 100644 index 0000000..6cb3d12 --- /dev/null +++ b/MCUME_teensy/teensygen/hvc.h @@ -0,0 +1,193 @@ + +#ifndef _HVC_H_ +#define _HVC_H_ + +#include "arduinoproto.h" + +/* V counter values for NTSC 192-line display */ +PROGMEM const uint8 vc_ntsc_192[262] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, + 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF +}; + +/* V counter values for NTSC 224-line display */ +PROGMEM const uint8 vc_ntsc_224[262] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, + 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF +}; + +/* V counter values for NTSC 240-line display */ +PROGMEM const uint8 vc_ntsc_240[262] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 +}; + +/* V counter values for PAL 192-line display */ +PROGMEM const uint8 vc_pal_192[313] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, + 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF +}; + +/* V counter values for PAL 224-line display */ +PROGMEM const uint8 vc_pal_224[313] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, + 0x00, 0x01, 0x02, + 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF +}; + +/* V counter values for PAL 240-line display */ +PROGMEM const uint8 vc_pal_240[313] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, + 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, +}; + +/* H counter values for a 256-pixel wide display (342 pixel max.) */ +PROGMEM const uint8 hc_256[171] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, + 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF +}; + +/* H counter values for a 320-pixel wide display (442 pixels max.) */ +PROGMEM const uint8 hc_320[211] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, + 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF +}; + +uint8 *vc_table[6] = { + vc_ntsc_192, + vc_ntsc_224, + vc_ntsc_240, + vc_pal_192, + vc_pal_224, + vc_pal_240 +}; + +uint8 *hc_table[2] = { + hc_256, + hc_320, +}; + +#endif /* _HVC_H_ */ + diff --git a/MCUME_teensy/teensygen/io.c b/MCUME_teensy/teensygen/io.c new file mode 100644 index 0000000..f619dd9 --- /dev/null +++ b/MCUME_teensy/teensygen/io.c @@ -0,0 +1,186 @@ +/* + io.c + I/O controller chip emulation +*/ + +#include "shared.h" + +port_t port[3]; +uint8 io_reg[0x10]; + + +void io_reset(void) +{ + /* I/O register default settings */ + uint8 io_def[0x10] = + { + 0xA0, + 0x7F, 0x7F, 0x7F, + 0x00, 0x00, 0x00, + 0xFF, 0x00, 0x00, + 0xFF, 0x00, 0x00, + 0xFB, 0x00, 0x00, + }; + + /* Initialize I/O registers */ + memcpy(io_reg, io_def, 0x10); + + /* + Port A : 3B pad + Port B : Unused + Port C : Unused + */ + port[0].data_w = device_3b_w; + port[0].data_r = device_3b_r; + port[1].data_w = NULL; + port[1].data_r = NULL; + port[2].data_w = NULL; + port[2].data_r = NULL; +} + +/*--------------------------------------------------------------------------*/ +/* I/O chip functions */ +/*--------------------------------------------------------------------------*/ + +void gen_io_w(int offset, int value) +{ + switch(offset) + { + case 0x01: /* Port A Data */ + value = ((value & 0x80) | (value & io_reg[offset+3])); + io_reg[offset] = value; + if(port[0].data_w) port[0].data_w(value); + return; + + case 0x02: /* Port B Data */ + value = ((value & 0x80) | (value & io_reg[offset+3])); + io_reg[offset] = value; + if(port[1].data_w) port[1].data_w(value); + return; + + case 0x03: /* Port C Data */ + value = ((value & 0x80) | (value & io_reg[offset+3])); + io_reg[offset] = value; + if(port[2].data_w) port[2].data_w(value); + return; + + case 0x04: /* Port A Ctrl */ + case 0x05: /* Port B Ctrl */ + case 0x06: /* Port C Ctrl */ + io_reg[offset] = value & 0xFF; + break; + + case 0x07: /* Port A TxData */ + case 0x0A: /* Port B TxData */ + case 0x0D: /* Port C TxData */ + io_reg[offset] = value; + break; + + case 0x09: /* Port A S-Ctrl */ + case 0x0C: /* Port B S-Ctrl */ + case 0x0F: /* Port C S-Ctrl */ + io_reg[offset] = (value & 0xF8); + break; + } +} + +int gen_io_r(int offset) +{ + uint8 temp; + uint8 has_scd = 0x20; /* No Sega CD unit attached */ + uint8 gen_ver = 0x00; /* Version 0 hardware */ + + switch(offset) + { + case 0x00: /* Version */ + switch(rom_version()) + { + case 'J': + temp = 0x00; + break; + case 'U': + temp = 0x80; + break; + case 'E': + temp = 0xC0; + break; + case 'A': + temp = 0xC0; + break; + case 'B': + temp = 0xC0; + break; + case '4': + temp = 0x80; + break; + default: + temp = 0x80; + break; + } + return (temp | has_scd | gen_ver); + break; + + case 0x01: /* Port A Data */ + if(port[0].data_r) return ((io_reg[offset] & 0x80) | port[0].data_r()); + return (io_reg[offset] | ((~io_reg[offset+3]) & 0x7F)); + + case 0x02: /* Port B Data */ + if(port[1].data_r) return ((io_reg[offset] & 0x80) | port[1].data_r()); + return (io_reg[offset] | ((~io_reg[offset+3]) & 0x7F)); + + case 0x03: /* Port C Data */ + if(port[2].data_r) return ((io_reg[offset] & 0x80) | port[2].data_r()); + return (io_reg[offset] | ((~io_reg[offset+3]) & 0x7F)); + } + + return (io_reg[offset]); +} + +/*--------------------------------------------------------------------------*/ +/* Input callbacks */ +/*--------------------------------------------------------------------------*/ + +uint8 pad_2b_r(void) +{ + uint8 temp = 0x3F; + if(input.pad[0] & INPUT_UP) temp &= ~0x01; + if(input.pad[0] & INPUT_DOWN) temp &= ~0x02; + if(input.pad[0] & INPUT_LEFT) temp &= ~0x04; + if(input.pad[0] & INPUT_RIGHT) temp &= ~0x08; + if(input.pad[0] & INPUT_B) temp &= ~0x10; + if(input.pad[0] & INPUT_C) temp &= ~0x20; + return (temp); +} + +static int th = 0; + +uint8 device_3b_r(void) +{ + uint8 temp = 0x3F; + + if(th) + { + temp = 0x3f; + if(input.pad[0] & INPUT_UP) temp &= ~0x01; + if(input.pad[0] & INPUT_DOWN) temp &= ~0x02; + if(input.pad[0] & INPUT_LEFT) temp &= ~0x04; + if(input.pad[0] & INPUT_RIGHT) temp &= ~0x08; + if(input.pad[0] & INPUT_B) temp &= ~0x10; + if(input.pad[0] & INPUT_C) temp &= ~0x20; + return (temp | 0x40); + } + else + { + temp = 0x33; + if(input.pad[0] & INPUT_UP) temp &= ~0x01; + if(input.pad[0] & INPUT_DOWN) temp &= ~0x02; + if(input.pad[0] & INPUT_A) temp &= ~0x10; + if(input.pad[0] & INPUT_START) temp &= ~0x20; + return (temp); + } +} + +void device_3b_w(uint8 data) +{ + th = (data & 0x40); +} diff --git a/MCUME_teensy/teensygen/io.h b/MCUME_teensy/teensygen/io.h new file mode 100644 index 0000000..bde7901 --- /dev/null +++ b/MCUME_teensy/teensygen/io.h @@ -0,0 +1,36 @@ +#ifndef _IO_H_ +#define _IO_H_ + +/* + +void io_reset(void); +void io_set_version(int export, int pal, int fdd, int n); + + +*/ + +typedef struct +{ + void (*data_w)(uint8 data); + uint8 (*data_r)(void); +} port_t; + +typedef struct +{ + uint8 state; +} t_input_3b; + +/* Global variables */ +extern port_t port[3]; +extern uint8 io_reg[0x10]; + +/* Function prototypes */ +extern void io_reset(void); +extern void gen_io_w(int offset, int value); +extern int gen_io_r(int offset); +extern uint8 pad_2b_r(void); +extern uint8 device_3b_r(void); +extern void device_3b_w(uint8 data); + +#endif /* _IO_H_ */ + diff --git a/MCUME_teensy/teensygen/iopins.h b/MCUME_teensy/teensygen/iopins.h new file mode 100644 index 0000000..f57086c --- /dev/null +++ b/MCUME_teensy/teensygen/iopins.h @@ -0,0 +1,98 @@ +#ifndef IOPINS_H +#define IOPINS_H + +//#define OLD_LAYOUT 1 + +#include "tft_t_dma_config.h" + +#ifndef OLD_LAYOUT + +#ifdef ST7789 +// ST7789 +#define TFT_SCLK 13 +#define TFT_MOSI 11 +#define TFT_MISO 12 +#define TFT_TOUCH_CS 255 +#define TFT_TOUCH_INT 255 +#define TFT_DC 9 +#define TFT_CS 255 +#define TFT_RST 23 +#else +// ILI9341 +#define TFT_SCLK 13 +#define TFT_MOSI 11 +#define TFT_MISO 12 +#define TFT_TOUCH_CS 255 //38 +#define TFT_TOUCH_INT 255 //37 +#define TFT_DC 9 +#define TFT_CS 23 +#define TFT_RST 255 +#endif + +// PSRAM +#define PSRAM_CS 36 +#define PSRAM_MOSI 35 +#define PSRAM_MISO 34 +#define PSRAM_SCLK 37 + +// SD +#define SD_SCLK 13 +#define SD_MOSI 11 +#define SD_MISO 12 +//#define SD_CS BUILTIN_SDCARD +#define SD_CS 5 + +// I2C keyboard +#define I2C_SCL_IO 19 +#define I2C_SDA_IO 18 + +// Analog joystick (primary) for JOY2 and 5 extra buttons +#define PIN_JOY2_A1X A1 +#define PIN_JOY2_A2Y A2 +#define PIN_JOY2_BTN 17 +#define PIN_KEY_USER1 3 //34 +#define PIN_KEY_USER2 4 //35 +//#define PIN_KEY_USER3 255 +//#define PIN_KEY_USER4 255 + + +#else // OLD LAYOUT!!!! + +#define HAS_VGA 1 + +// ILI9341 +#define TFT_SCLK 13 +#define TFT_MOSI 11 +#define TFT_MISO 12 +#define TFT_TOUCH_CS 38 +#define TFT_TOUCH_INT 37 +#define TFT_DC 9 +#define TFT_CS 10 +#define TFT_RST 255 //connected to 3.3V + +// I2C keyboard +#define I2C_SCL_IO 3 +#define I2C_SDA_IO 4 + +// Analog joystick (primary) for JOY2 and 5 extra buttons +#define PIN_JOY2_A1X A12 +#define PIN_JOY2_A2Y A13 +#define PIN_JOY2_BTN 36 +#define PIN_KEY_USER1 35 +#define PIN_KEY_USER2 34 +#define PIN_KEY_USER3 33 +#define PIN_KEY_USER4 39 + +// Second joystick +#define PIN_JOY1_BTN 30 +#define PIN_JOY1_1 16 +#define PIN_JOY1_2 17 +#define PIN_JOY1_3 18 +#define PIN_JOY1_4 19 +#endif + +#endif + + + + diff --git a/MCUME_teensy/teensygen/keyboard_osd.h b/MCUME_teensy/teensygen/keyboard_osd.h new file mode 100644 index 0000000..062eb4e --- /dev/null +++ b/MCUME_teensy/teensygen/keyboard_osd.h @@ -0,0 +1,20 @@ + +#ifndef keyboard_osd_h_ +#define keyboard_osd_h_ + +extern bool virtualkeyboardIsActive(void); +extern void drawVirtualkeyboard(void); +extern void toggleVirtualkeyboard(bool keepOn); +extern void handleVirtualkeyboard(void); + +extern bool callibrationActive(void); +extern int handleCallibration(uint16_t bClick); + +extern bool menuActive(void); +extern char * menuSelection(void); +extern void toggleMenu(bool on); +extern int handleMenu(uint16_t bClick); + + +#endif + diff --git a/MCUME_teensy/teensygen/logo.h b/MCUME_teensy/teensygen/logo.h new file mode 100644 index 0000000..692a06c --- /dev/null +++ b/MCUME_teensy/teensygen/logo.h @@ -0,0 +1,241 @@ +PROGMEM const uint16_t logo[] = { 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diff --git a/MCUME_teensy/teensygen/m68k.h b/MCUME_teensy/teensygen/m68k.h new file mode 100644 index 0000000..1c93c2d --- /dev/null +++ b/MCUME_teensy/teensygen/m68k.h @@ -0,0 +1,339 @@ +#ifndef M68K__HEADER +#define M68K__HEADER + +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.3 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * + * This code may be freely used for non-commercial purposes as long as this + * copyright notice remains unaltered in the source code and any binary files + * containing this code in compiled form. + * + * All other lisencing terms must be negotiated with the author + * (Karl Stenerud). + * + * The latest version of this code can be obtained at: + * http://kstenerud.cjb.net + */ + + + +/* ======================================================================== */ +/* ============================ GENERAL DEFINES =========================== */ + +/* ======================================================================== */ + +/* There are 7 levels of interrupt to the 68K. + * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). + */ +#define M68K_IRQ_NONE 0 +#define M68K_IRQ_1 1 +#define M68K_IRQ_2 2 +#define M68K_IRQ_3 3 +#define M68K_IRQ_4 4 +#define M68K_IRQ_5 5 +#define M68K_IRQ_6 6 +#define M68K_IRQ_7 7 + + +/* Special interrupt acknowledge values. + * Use these as special returns from the interrupt acknowledge callback + * (specified later in this header). + */ + +/* Causes an interrupt autovector (0x18 + interrupt level) to be taken. + * This happens in a real 68K if VPA or AVEC is asserted during an interrupt + * acknowledge cycle instead of DTACK. + */ +#define M68K_INT_ACK_AUTOVECTOR 0xffffffff + +/* Causes the spurious interrupt vector (0x18) to be taken + * This happens in a real 68K if BERR is asserted during the interrupt + * acknowledge cycle (i.e. no devices responded to the acknowledge). + */ +#define M68K_INT_ACK_SPURIOUS 0xfffffffe + + +/* CPU types for use in m68k_set_cpu_type() */ +enum +{ + M68K_CPU_TYPE_INVALID, + M68K_CPU_TYPE_68000, + M68K_CPU_TYPE_68010, + M68K_CPU_TYPE_68EC020, + M68K_CPU_TYPE_68020, + M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */ + M68K_CPU_TYPE_68040 /* Supported by disassembler ONLY */ +}; + +/* Registers used by m68k_get_reg() and m68k_set_reg() */ +typedef enum +{ + /* Real registers */ + M68K_REG_D0, /* Data registers */ + M68K_REG_D1, + M68K_REG_D2, + M68K_REG_D3, + M68K_REG_D4, + M68K_REG_D5, + M68K_REG_D6, + M68K_REG_D7, + M68K_REG_A0, /* Address registers */ + M68K_REG_A1, + M68K_REG_A2, + M68K_REG_A3, + M68K_REG_A4, + M68K_REG_A5, + M68K_REG_A6, + M68K_REG_A7, + M68K_REG_PC, /* Program Counter */ + M68K_REG_SR, /* Status Register */ + M68K_REG_SP, /* The current Stack Pointer (located in A7) */ + M68K_REG_USP, /* User Stack Pointer */ + M68K_REG_ISP, /* Interrupt Stack Pointer */ + M68K_REG_MSP, /* Master Stack Pointer */ + M68K_REG_SFC, /* Source Function Code */ + M68K_REG_DFC, /* Destination Function Code */ + M68K_REG_VBR, /* Vector Base Register */ + M68K_REG_CACR, /* Cache Control Register */ + M68K_REG_CAAR, /* Cache Address Register */ + + /* Assumed registers */ + /* These are cheat registers which emulate the 1-longword prefetch + * present in the 68000 and 68010. + */ + M68K_REG_PREF_ADDR, /* Last prefetch address */ + M68K_REG_PREF_DATA, /* Last prefetch data */ + + /* Convenience registers */ + M68K_REG_PPC, /* Previous value in the program counter */ + M68K_REG_IR, /* Instruction register */ + M68K_REG_CPU_TYPE /* Type of CPU being run */ +} m68k_register_t; + +/* ======================================================================== */ +/* ====================== FUNCTIONS CALLED BY THE CPU ===================== */ +/* ======================================================================== */ + +/* You will have to implement these functions */ + +/* read/write functions called by the CPU to access memory. + * while values used are 32 bits, only the appropriate number + * of bits are relevant (i.e. in write_memory_8, only the lower 8 bits + * of value should be written to memory). + * + * NOTE: I have separated the immediate and PC-relative memory fetches + * from the other memory fetches because some systems require + * differentiation between PROGRAM and DATA fetches (usually + * for security setups such as encryption). + * This separation can either be achieved by setting + * M68K_SEPARATE_READS in m68kconf.h and defining + * the read functions, or by setting M68K_EMULATE_FC and + * making a function code callback function. + * Using the callback offers better emulation coverage + * because you can also monitor whether the CPU is in SYSTEM or + * USER mode, but it is also slower. + */ + +/* Read from anywhere */ +unsigned int m68k_read_memory_8(unsigned int address); +unsigned int m68k_read_memory_16(unsigned int address); +unsigned int m68k_read_memory_32(unsigned int address); + +/* Read data immediately following the PC */ +unsigned int m68k_read_immediate_16(unsigned int address); +unsigned int m68k_read_immediate_32(unsigned int address); + +/* Read data relative to the PC */ +unsigned int m68k_read_pcrelative_8(unsigned int address); +unsigned int m68k_read_pcrelative_16(unsigned int address); +unsigned int m68k_read_pcrelative_32(unsigned int address); + +/* Memory access for the disassembler */ +unsigned int m68k_read_disassembler_8 (unsigned int address); +unsigned int m68k_read_disassembler_16 (unsigned int address); +unsigned int m68k_read_disassembler_32 (unsigned int address); + +/* Write to anywhere */ +void m68k_write_memory_8(unsigned int address, unsigned int value); +void m68k_write_memory_16(unsigned int address, unsigned int value); +void m68k_write_memory_32(unsigned int address, unsigned int value); + + + +/* ======================================================================== */ +/* ============================== CALLBACKS =============================== */ +/* ======================================================================== */ + +/* These functions allow you to set callbacks to the host when specific events + * occur. Note that you must enable the corresponding value in m68kconf.h + * in order for these to do anything useful. + * Note: I have defined default callbacks which are used if you have enabled + * the corresponding #define in m68kconf.h but either haven't assigned a + * callback or have assigned a callback of NULL. + */ + +/* Set the callback for an interrupt acknowledge. + * You must enable M68K_EMULATE_INT_ACK in m68kconf.h. + * The CPU will call the callback with the interrupt level being acknowledged. + * The host program must return either a vector from 0x02-0xff, or one of the + * special interrupt acknowledge values specified earlier in this header. + * If this is not implemented, the CPU will always assume an autovectored + * interrupt, and will automatically clear the interrupt request when it + * services the interrupt. + * Default behavior: return M68K_INT_ACK_AUTOVECTOR. + */ +void m68k_set_int_ack_callback(int (*callback)(int int_level)); + + +/* Set the callback for a breakpoint acknowledge (68010+). + * You must enable M68K_EMULATE_BKPT_ACK in m68kconf.h. + * The CPU will call the callback with whatever was in the data field of the + * BKPT instruction for 68020+, or 0 for 68010. + * Default behavior: do nothing. + */ +void m68k_set_bkpt_ack_callback(void (*callback)(unsigned int data)); + + +/* Set the callback for the RESET instruction. + * You must enable M68K_EMULATE_RESET in m68kconf.h. + * The CPU calls this callback every time it encounters a RESET instruction. + * Default behavior: do nothing. + */ +void m68k_set_reset_instr_callback(void (*callback)(void)); + + +/* Set the callback for informing of a large PC change. + * You must enable M68K_MONITOR_PC in m68kconf.h. + * The CPU calls this callback with the new PC value every time the PC changes + * by a large value (currently set for changes by longwords). + * Default behavior: do nothing. + */ +void m68k_set_pc_changed_callback(void (*callback)(unsigned int new_pc)); + + +/* Set the callback for CPU function code changes. + * You must enable M68K_EMULATE_FC in m68kconf.h. + * The CPU calls this callback with the function code before every memory + * access to set the CPU's function code according to what kind of memory + * access it is (supervisor/user, program/data and such). + * Default behavior: do nothing. + */ +void m68k_set_fc_callback(void (*callback)(unsigned int new_fc)); + + +/* Set a callback for the instruction cycle of the CPU. + * You must enable M68K_INSTRUCTION_HOOK in m68kconf.h. + * The CPU calls this callback just before fetching the opcode in the + * instruction cycle. + * Default behavior: do nothing. + */ +void m68k_set_instr_hook_callback(void (*callback)(void)); + + + +/* ======================================================================== */ +/* ====================== FUNCTIONS TO ACCESS THE CPU ===================== */ +/* ======================================================================== */ + +/* Use this function to set the CPU type you want to emulate. + * Currently supported types are: M68K_CPU_TYPE_68000, M68K_CPU_TYPE_68010, + * M68K_CPU_TYPE_EC020, and M68K_CPU_TYPE_68020. + */ +void m68k_set_cpu_type(unsigned int cpu_type); + +/* Pulse the RESET pin on the CPU. + * You *MUST* reset the CPU at least once to initialize the emulation + * Note: If you didn't call m68k_set_cpu_type() before resetting + * the CPU for the first time, the CPU will be set to + * M68K_CPU_TYPE_68000. + */ +void m68k_pulse_reset(void); + +/* execute num_cycles worth of instructions. returns number of cycles used */ +int m68k_execute(int num_cycles); + +/* These functions let you read/write/modify the number of cycles left to run + * while m68k_execute() is running. + * These are useful if the 68k accesses a memory-mapped port on another device + * that requires immediate processing by another CPU. + */ +int m68k_cycles_run(void); /* Number of cycles run so far */ +int m68k_cycles_remaining(void); /* Number of cycles left */ +void m68k_modify_timeslice(int cycles); /* Modify cycles left */ +void m68k_end_timeslice(void); /* End timeslice now */ + +/* Set the IPL0-IPL2 pins on the CPU (IRQ). + * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). + * Setting IRQ to 0 will clear an interrupt request. + */ +void m68k_set_irq(unsigned int int_level); + + +/* Halt the CPU as if you pulsed the HALT pin. */ +void m68k_pulse_halt(void); + + +/* Context switching to allow multiple CPUs */ + +/* Get the size of the cpu context in bytes */ +unsigned int m68k_context_size(void); + +/* Get a cpu context */ +unsigned int m68k_get_context(void* dst); + +/* set the current cpu context */ +void m68k_set_context(void* dst); + +/* Save the current cpu context to disk. + * You must provide a function pointer of the form: + * void save_value(char* identifier, unsigned int value) + */ +void m68k_save_context( void (*save_value)(char* identifier, unsigned int value)); + +/* Load a cpu context from disk. + * You must provide a function pointer of the form: + * unsigned int load_value(char* identifier) + */ +void m68k_load_context(unsigned int (*load_value)(char* identifier)); + + + +/* Peek at the internals of a CPU context. This can either be a context + * retrieved using m68k_get_context() or the currently running context. + * If context is NULL, the currently running CPU context will be used. + */ +unsigned int m68k_get_reg(void* context, m68k_register_t reg); + +/* Poke values into the internals of the currently running CPU context */ +void m68k_set_reg(m68k_register_t reg, unsigned int value); + +/* Check if an instruction is valid for the specified CPU type */ +unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type); + +/* Disassemble 1 instruction using the epecified CPU type at pc. Stores + * disassembly in str_buff and returns the size of the instruction in bytes. + */ +unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type); + + +/* ======================================================================== */ +/* ============================= CONFIGURATION ============================ */ +/* ======================================================================== */ + +/* Import the configuration for this build */ +#include "m68kconf.h" + + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68K__HEADER */ diff --git a/MCUME_teensy/teensygen/m68kconf.h b/MCUME_teensy/teensygen/m68kconf.h new file mode 100644 index 0000000..18301e0 --- /dev/null +++ b/MCUME_teensy/teensygen/m68kconf.h @@ -0,0 +1,183 @@ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.3 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * + * This code may be freely used for non-commercial purposes as long as this + * copyright notice remains unaltered in the source code and any binary files + * containing this code in compiled form. + * + * All other lisencing terms must be negotiated with the author + * (Karl Stenerud). + * + * The latest version of this code can be obtained at: + * http://kstenerud.cjb.net + */ + + + +#ifndef M68KCONF__HEADER +#define M68KCONF__HEADER + + +/* Configuration switches. + * Use OPT_SPECIFY_HANDLER for configuration options that allow callbacks. + * OPT_SPECIFY_HANDLER causes the core to link directly to the function + * or macro you specify, rather than using callback functions whose pointer + * must be passed in using m68k_set_xxx_callback(). + */ +#define OPT_OFF 0 +#define OPT_ON 1 +#define OPT_SPECIFY_HANDLER 2 + + +/* ======================================================================== */ +/* ============================== MAME STUFF ============================== */ +/* ======================================================================== */ + +/* If you're compiling this for MAME, only change M68K_COMPILE_FOR_MAME + * to OPT_ON and use m68kmame.h to configure the 68k core. + */ +#ifndef M68K_COMPILE_FOR_MAME +#define M68K_COMPILE_FOR_MAME OPT_OFF +#endif /* M68K_COMPILE_FOR_MAME */ + +#if M68K_COMPILE_FOR_MAME == OPT_ON +#include "m68kmame.h" +#else + + + +/* ======================================================================== */ +/* ============================= CONFIGURATION ============================ */ +/* ======================================================================== */ + +/* Turn on if you want to use the following M68K variants */ +#define M68K_EMULATE_010 OPT_ON +#define M68K_EMULATE_EC020 OPT_ON +#define M68K_EMULATE_020 OPT_ON + + +/* If on, the CPU will call m68k_read_immediate_xx() for immediate addressing + * and m68k_read_pcrelative_xx() for PC-relative addressing. + * If off, all read requests from the CPU will be redirected to m68k_read_xx() + */ +#define M68K_SEPARATE_READS OPT_OFF + + +/* If on, CPU will call the interrupt acknowledge callback when it services an + * interrupt. + * If off, all interrupts will be autovectored and all interrupt requests will + * auto-clear when the interrupt is serviced. + */ +#define M68K_EMULATE_INT_ACK OPT_SPECIFY_HANDLER +#define M68K_INT_ACK_CALLBACK(A) vdp_int_ack_callback(A) + + +/* If on, CPU will call the breakpoint acknowledge callback when it encounters + * a breakpoint instruction and it is running a 68010+. + */ +#define M68K_EMULATE_BKPT_ACK OPT_OFF +#define M68K_BKPT_ACK_CALLBACK() your_bkpt_ack_handler_function() + + +/* If on, the CPU will monitor the trace flags and take trace exceptions + */ +#define M68K_EMULATE_TRACE OPT_OFF + + +/* If on, CPU will call the output reset callback when it encounters a reset + * instruction. + */ +#define M68K_EMULATE_RESET OPT_OFF +#define M68K_RESET_CALLBACK() your_reset_handler_function() + + +/* If on, CPU will call the set fc callback on every memory access to + * differentiate between user/supervisor, program/data access like a real + * 68000 would. This should be enabled and the callback should be set if you + * want to properly emulate the m68010 or higher. (moves uses function codes + * to read/write data from different address spaces) + */ +#define M68K_EMULATE_FC OPT_OFF +#define M68K_SET_FC_CALLBACK(A) your_set_fc_handler_function(A) + + +/* If on, CPU will call the pc changed callback when it changes the PC by a + * large value. This allows host programs to be nicer when it comes to + * fetching immediate data and instructions on a banked memory system. + */ +#define M68K_MONITOR_PC OPT_OFF +#define M68K_SET_PC_CALLBACK(A) your_pc_changed_handler_function(A) + + +/* If on, CPU will call the instruction hook callback before every + * instruction. + */ +#define M68K_INSTRUCTION_HOOK OPT_OFF +#define M68K_INSTRUCTION_CALLBACK() your_instruction_hook_function() + + +/* If on, the CPU will emulate the 4-byte prefetch queue of a real 68000 */ +#define M68K_EMULATE_PREFETCH OPT_OFF + + +/* If on, the CPU will generate address error exceptions if it tries to + * access a word or longword at an odd address. + * NOTE: Do not enable this! It is not working! + */ +#define M68K_EMULATE_ADDRESS_ERROR OPT_OFF + + +/* Turn on to enable logging of illegal instruction calls. + * M68K_LOG_FILEHANDLE must be #defined to a stdio file stream. + * Turn on M68K_LOG_1010_1111 to log all 1010 and 1111 calls. + */ +#define M68K_LOG_ENABLE OPT_OFF +#define M68K_LOG_1010_1111 OPT_OFF +#define M68K_LOG_FILEHANDLE some_file_handle + + +/* ----------------------------- COMPATIBILITY ---------------------------- */ + +/* The following options set optimizations that violate the current ANSI + * standard, but will be compliant under the forthcoming C9X standard. + */ + + +/* If on, the enulation core will use 64-bit integers to speed up some + * operations. +*/ +#define M68K_USE_64_BIT OPT_OFF + + +/* Set to your compiler's static inline keyword to enable it, or + * set it to blank to disable it. + * If you define INLINE in the makefile, it will override this value. + * NOTE: not enabling inline functions will SEVERELY slow down emulation. + */ +#ifndef INLINE +#define INLINE static __inline__ +#endif /* INLINE */ + + +/* If your environment requires special prefixes for system callback functions + * such as the argument to qsort(), then set them here or in the makefile. + */ +#ifndef DECL_SPEC +#define DECL_SPEC +#endif + +#endif /* M68K_COMPILE_FOR_MAME */ + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68KCONF__HEADER */ diff --git a/MCUME_teensy/teensygen/m68kcpu.c b/MCUME_teensy/teensygen/m68kcpu.c new file mode 100644 index 0000000..f82ca3f --- /dev/null +++ b/MCUME_teensy/teensygen/m68kcpu.c @@ -0,0 +1,895 @@ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ + +#if 0 +static const char* copyright_notice = +"MUSASHI\n" +"Version 3.3 (2001-01-29)\n" +"A portable Motorola M680x0 processor emulation engine.\n" +"Copyright 1998-2001 Karl Stenerud. All rights reserved.\n" +"\n" +"This code may be freely used for non-commercial purpooses as long as this\n" +"copyright notice remains unaltered in the source code and any binary files\n" +"containing this code in compiled form.\n" +"\n" +"All other lisencing terms must be negotiated with the author\n" +"(Karl Stenerud).\n" +"\n" +"The latest version of this code can be obtained at:\n" +"http://kstenerud.cjb.net\n" +; +#endif + + +/* ======================================================================== */ +/* ================================= NOTES ================================ */ +/* ======================================================================== */ + + + +/* ======================================================================== */ +/* ================================ INCLUDES ============================== */ +/* ======================================================================== */ + +#include "m68kops.h" +#include "m68kcpu.h" + +/* ======================================================================== */ +/* ================================= DATA ================================= */ +/* ======================================================================== */ + +int m68ki_initial_cycles; +int m68ki_remaining_cycles = 0; /* Number of clocks remaining */ +uint m68ki_tracing = 0; +uint m68ki_address_space; + +#ifdef M68K_LOG_ENABLE +char* m68ki_cpu_names[9] = +{ + "Invalid CPU", + "M68000", + "M68010", + "Invalid CPU", + "M68EC020" + "Invalid CPU", + "Invalid CPU", + "Invalid CPU", + "M68020" +}; +#endif /* M68K_LOG_ENABLE */ + +/* The CPU core */ +m68ki_cpu_core m68ki_cpu = {0}; + +#if M68K_EMULATE_ADDRESS_ERROR +jmp_buf m68ki_address_error_trap; +#endif /* M68K_EMULATE_ADDRESS_ERROR */ + +#include "arduinoproto.h" +/* Used by shift & rotate instructions */ +PROGMEM const uint8 m68ki_shift_8_table[65] = +{ + 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff +}; +PROGMEM const uint16 m68ki_shift_16_table[65] = +{ + 0x0000, 0x8000, 0xc000, 0xe000, 0xf000, 0xf800, 0xfc00, 0xfe00, 0xff00, + 0xff80, 0xffc0, 0xffe0, 0xfff0, 0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff +}; +PROGMEM const uint m68ki_shift_32_table[65] = +{ + 0x00000000, 0x80000000, 0xc0000000, 0xe0000000, 0xf0000000, 0xf8000000, + 0xfc000000, 0xfe000000, 0xff000000, 0xff800000, 0xffc00000, 0xffe00000, + 0xfff00000, 0xfff80000, 0xfffc0000, 0xfffe0000, 0xffff0000, 0xffff8000, + 0xffffc000, 0xffffe000, 0xfffff000, 0xfffff800, 0xfffffc00, 0xfffffe00, + 0xffffff00, 0xffffff80, 0xffffffc0, 0xffffffe0, 0xfffffff0, 0xfffffff8, + 0xfffffffc, 0xfffffffe, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff +}; + + +/* Number of clock cycles to use for exception processing. + * I used 4 for any vectors that are undocumented for processing times. + */ +PROGMEM const uint8 m68ki_exception_cycle_table[3][256] = +{ + { /* 000 */ + 4, /* 0: Reset - Initial Stack Pointer */ + 4, /* 1: Reset - Initial Program Counter */ + 50, /* 2: Bus Error (unemulated) */ + 50, /* 3: Address Error (unemulated) */ + 34, /* 4: Illegal Instruction */ + 38, /* 5: Divide by Zero -- ASG: changed from 42 */ + 40, /* 6: CHK -- ASG: chanaged from 44 */ + 34, /* 7: TRAPV */ + 34, /* 8: Privilege Violation */ + 34, /* 9: Trace */ + 4, /* 10: 1010 */ + 4, /* 11: 1111 */ + 4, /* 12: RESERVED */ + 4, /* 13: Coprocessor Protocol Violation (unemulated) */ + 4, /* 14: Format Error */ + 44, /* 15: Uninitialized Interrupt */ + 4, /* 16: RESERVED */ + 4, /* 17: RESERVED */ + 4, /* 18: RESERVED */ + 4, /* 19: RESERVED */ + 4, /* 20: RESERVED */ + 4, /* 21: RESERVED */ + 4, /* 22: RESERVED */ + 4, /* 23: RESERVED */ + 44, /* 24: Spurious Interrupt */ + 44, /* 25: Level 1 Interrupt Autovector */ + 44, /* 26: Level 2 Interrupt Autovector */ + 44, /* 27: Level 3 Interrupt Autovector */ + 44, /* 28: Level 4 Interrupt Autovector */ + 44, /* 29: Level 5 Interrupt Autovector */ + 44, /* 30: Level 6 Interrupt Autovector */ + 44, /* 31: Level 7 Interrupt Autovector */ + 34, /* 32: TRAP #0 -- ASG: chanaged from 38 */ + 34, /* 33: TRAP #1 */ + 34, /* 34: TRAP #2 */ + 34, /* 35: TRAP #3 */ + 34, /* 36: TRAP #4 */ + 34, /* 37: TRAP #5 */ + 34, /* 38: TRAP #6 */ + 34, /* 39: TRAP #7 */ + 34, /* 40: TRAP #8 */ + 34, /* 41: TRAP #9 */ + 34, /* 42: TRAP #10 */ + 34, /* 43: TRAP #11 */ + 34, /* 44: TRAP #12 */ + 34, /* 45: TRAP #13 */ + 34, /* 46: TRAP #14 */ + 34, /* 47: TRAP #15 */ + 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */ + 4, /* 49: FP Inexact Result (unemulated) */ + 4, /* 50: FP Divide by Zero (unemulated) */ + 4, /* 51: FP Underflow (unemulated) */ + 4, /* 52: FP Operand Error (unemulated) */ + 4, /* 53: FP Overflow (unemulated) */ + 4, /* 54: FP Signaling NAN (unemulated) */ + 4, /* 55: FP Unimplemented Data Type (unemulated) */ + 4, /* 56: MMU Configuration Error (unemulated) */ + 4, /* 57: MMU Illegal Operation Error (unemulated) */ + 4, /* 58: MMU Access Level Violation Error (unemulated) */ + 4, /* 59: RESERVED */ + 4, /* 60: RESERVED */ + 4, /* 61: RESERVED */ + 4, /* 62: RESERVED */ + 4, /* 63: RESERVED */ + /* 64-255: User Defined */ + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 + }, + { /* 010 */ + 4, /* 0: Reset - Initial Stack Pointer */ + 4, /* 1: Reset - Initial Program Counter */ + 126, /* 2: Bus Error (unemulated) */ + 126, /* 3: Address Error (unemulated) */ + 38, /* 4: Illegal Instruction */ + 44, /* 5: Divide by Zero */ + 44, /* 6: CHK */ + 34, /* 7: TRAPV */ + 38, /* 8: Privilege Violation */ + 38, /* 9: Trace */ + 4, /* 10: 1010 */ + 4, /* 11: 1111 */ + 4, /* 12: RESERVED */ + 4, /* 13: Coprocessor Protocol Violation (unemulated) */ + 4, /* 14: Format Error */ + 44, /* 15: Uninitialized Interrupt */ + 4, /* 16: RESERVED */ + 4, /* 17: RESERVED */ + 4, /* 18: RESERVED */ + 4, /* 19: RESERVED */ + 4, /* 20: RESERVED */ + 4, /* 21: RESERVED */ + 4, /* 22: RESERVED */ + 4, /* 23: RESERVED */ + 46, /* 24: Spurious Interrupt */ + 46, /* 25: Level 1 Interrupt Autovector */ + 46, /* 26: Level 2 Interrupt Autovector */ + 46, /* 27: Level 3 Interrupt Autovector */ + 46, /* 28: Level 4 Interrupt Autovector */ + 46, /* 29: Level 5 Interrupt Autovector */ + 46, /* 30: Level 6 Interrupt Autovector */ + 46, /* 31: Level 7 Interrupt Autovector */ + 38, /* 32: TRAP #0 */ + 38, /* 33: TRAP #1 */ + 38, /* 34: TRAP #2 */ + 38, /* 35: TRAP #3 */ + 38, /* 36: TRAP #4 */ + 38, /* 37: TRAP #5 */ + 38, /* 38: TRAP #6 */ + 38, /* 39: TRAP #7 */ + 38, /* 40: TRAP #8 */ + 38, /* 41: TRAP #9 */ + 38, /* 42: TRAP #10 */ + 38, /* 43: TRAP #11 */ + 38, /* 44: TRAP #12 */ + 38, /* 45: TRAP #13 */ + 38, /* 46: TRAP #14 */ + 38, /* 47: TRAP #15 */ + 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */ + 4, /* 49: FP Inexact Result (unemulated) */ + 4, /* 50: FP Divide by Zero (unemulated) */ + 4, /* 51: FP Underflow (unemulated) */ + 4, /* 52: FP Operand Error (unemulated) */ + 4, /* 53: FP Overflow (unemulated) */ + 4, /* 54: FP Signaling NAN (unemulated) */ + 4, /* 55: FP Unimplemented Data Type (unemulated) */ + 4, /* 56: MMU Configuration Error (unemulated) */ + 4, /* 57: MMU Illegal Operation Error (unemulated) */ + 4, /* 58: MMU Access Level Violation Error (unemulated) */ + 4, /* 59: RESERVED */ + 4, /* 60: RESERVED */ + 4, /* 61: RESERVED */ + 4, /* 62: RESERVED */ + 4, /* 63: RESERVED */ + /* 64-255: User Defined */ + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 + }, + { /* 020 */ + 4, /* 0: Reset - Initial Stack Pointer */ + 4, /* 1: Reset - Initial Program Counter */ + 50, /* 2: Bus Error (unemulated) */ + 50, /* 3: Address Error (unemulated) */ + 20, /* 4: Illegal Instruction */ + 38, /* 5: Divide by Zero */ + 40, /* 6: CHK */ + 20, /* 7: TRAPV */ + 34, /* 8: Privilege Violation */ + 25, /* 9: Trace */ + 20, /* 10: 1010 */ + 20, /* 11: 1111 */ + 4, /* 12: RESERVED */ + 4, /* 13: Coprocessor Protocol Violation (unemulated) */ + 4, /* 14: Format Error */ + 30, /* 15: Uninitialized Interrupt */ + 4, /* 16: RESERVED */ + 4, /* 17: RESERVED */ + 4, /* 18: RESERVED */ + 4, /* 19: RESERVED */ + 4, /* 20: RESERVED */ + 4, /* 21: RESERVED */ + 4, /* 22: RESERVED */ + 4, /* 23: RESERVED */ + 30, /* 24: Spurious Interrupt */ + 30, /* 25: Level 1 Interrupt Autovector */ + 30, /* 26: Level 2 Interrupt Autovector */ + 30, /* 27: Level 3 Interrupt Autovector */ + 30, /* 28: Level 4 Interrupt Autovector */ + 30, /* 29: Level 5 Interrupt Autovector */ + 30, /* 30: Level 6 Interrupt Autovector */ + 30, /* 31: Level 7 Interrupt Autovector */ + 20, /* 32: TRAP #0 */ + 20, /* 33: TRAP #1 */ + 20, /* 34: TRAP #2 */ + 20, /* 35: TRAP #3 */ + 20, /* 36: TRAP #4 */ + 20, /* 37: TRAP #5 */ + 20, /* 38: TRAP #6 */ + 20, /* 39: TRAP #7 */ + 20, /* 40: TRAP #8 */ + 20, /* 41: TRAP #9 */ + 20, /* 42: TRAP #10 */ + 20, /* 43: TRAP #11 */ + 20, /* 44: TRAP #12 */ + 20, /* 45: TRAP #13 */ + 20, /* 46: TRAP #14 */ + 20, /* 47: TRAP #15 */ + 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */ + 4, /* 49: FP Inexact Result (unemulated) */ + 4, /* 50: FP Divide by Zero (unemulated) */ + 4, /* 51: FP Underflow (unemulated) */ + 4, /* 52: FP Operand Error (unemulated) */ + 4, /* 53: FP Overflow (unemulated) */ + 4, /* 54: FP Signaling NAN (unemulated) */ + 4, /* 55: FP Unimplemented Data Type (unemulated) */ + 4, /* 56: MMU Configuration Error (unemulated) */ + 4, /* 57: MMU Illegal Operation Error (unemulated) */ + 4, /* 58: MMU Access Level Violation Error (unemulated) */ + 4, /* 59: RESERVED */ + 4, /* 60: RESERVED */ + 4, /* 61: RESERVED */ + 4, /* 62: RESERVED */ + 4, /* 63: RESERVED */ + /* 64-255: User Defined */ + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 + } +}; + +PROGMEM const uint8 m68ki_ea_idx_cycle_table[64] = +{ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, /* ..01.000 no memory indirect, base NULL */ + 5, /* ..01..01 memory indirect, base NULL, outer NULL */ + 7, /* ..01..10 memory indirect, base NULL, outer 16 */ + 7, /* ..01..11 memory indirect, base NULL, outer 32 */ + 0, 5, 7, 7, 0, 5, 7, 7, 0, 5, 7, 7, + 2, /* ..10.000 no memory indirect, base 16 */ + 7, /* ..10..01 memory indirect, base 16, outer NULL */ + 9, /* ..10..10 memory indirect, base 16, outer 16 */ + 9, /* ..10..11 memory indirect, base 16, outer 32 */ + 0, 7, 9, 9, 0, 7, 9, 9, 0, 7, 9, 9, + 6, /* ..11.000 no memory indirect, base 32 */ + 11, /* ..11..01 memory indirect, base 32, outer NULL */ + 13, /* ..11..10 memory indirect, base 32, outer 16 */ + 13, /* ..11..11 memory indirect, base 32, outer 32 */ + 0, 11, 13, 13, 0, 11, 13, 13, 0, 11, 13, 13 +}; + + + +/* ======================================================================== */ +/* =============================== CALLBACKS ============================== */ +/* ======================================================================== */ + +/* Default callbacks used if the callback hasn't been set yet, or if the + * callback is set to NULL + */ + +/* Interrupt acknowledge */ +static int default_int_ack_callback_data; +static int default_int_ack_callback(int int_level) +{ + default_int_ack_callback_data = int_level; + CPU_INT_LEVEL = 0; + return M68K_INT_ACK_AUTOVECTOR; +} + +/* Breakpoint acknowledge */ +static unsigned int default_bkpt_ack_callback_data; +static void default_bkpt_ack_callback(unsigned int data) +{ + default_bkpt_ack_callback_data = data; +} + +/* Called when a reset instruction is executed */ +static void default_reset_instr_callback(void) +{ +} + +/* Called when the program counter changed by a large value */ +static unsigned int default_pc_changed_callback_data; +static void default_pc_changed_callback(unsigned int new_pc) +{ + default_pc_changed_callback_data = new_pc; +} + +/* Called every time there's bus activity (read/write to/from memory */ +static unsigned int default_set_fc_callback_data; +static void default_set_fc_callback(unsigned int new_fc) +{ + default_set_fc_callback_data = new_fc; +} + +/* Called every instruction cycle prior to execution */ +static void default_instr_hook_callback(void) +{ +} + + + +/* ======================================================================== */ +/* ================================= API ================================== */ +/* ======================================================================== */ + +/* Access the internals of the CPU */ +unsigned int m68k_get_reg(void* context, m68k_register_t regnum) +{ + m68ki_cpu_core* cpu = context != NULL ?(m68ki_cpu_core*)context : &m68ki_cpu; + + switch(regnum) + { + case M68K_REG_D0: return cpu->dar[0]; + case M68K_REG_D1: return cpu->dar[1]; + case M68K_REG_D2: return cpu->dar[2]; + case M68K_REG_D3: return cpu->dar[3]; + case M68K_REG_D4: return cpu->dar[4]; + case M68K_REG_D5: return cpu->dar[5]; + case M68K_REG_D6: return cpu->dar[6]; + case M68K_REG_D7: return cpu->dar[7]; + case M68K_REG_A0: return cpu->dar[8]; + case M68K_REG_A1: return cpu->dar[9]; + case M68K_REG_A2: return cpu->dar[10]; + case M68K_REG_A3: return cpu->dar[11]; + case M68K_REG_A4: return cpu->dar[12]; + case M68K_REG_A5: return cpu->dar[13]; + case M68K_REG_A6: return cpu->dar[14]; + case M68K_REG_A7: return cpu->dar[15]; + case M68K_REG_PC: return MASK_OUT_ABOVE_32(cpu->pc); + case M68K_REG_SR: return cpu->t1_flag | + cpu->t0_flag | + (cpu->s_flag << 11) | + (cpu->m_flag << 11) | + cpu->int_mask | + ((cpu->x_flag & XFLAG_SET) >> 4) | + ((cpu->n_flag & NFLAG_SET) >> 4) | + ((!cpu->not_z_flag) << 2) | + ((cpu->v_flag & VFLAG_SET) >> 6) | + ((cpu->c_flag & CFLAG_SET) >> 8); + case M68K_REG_SP: return cpu->dar[15]; + case M68K_REG_USP: return cpu->s_flag ? cpu->sp[0] : cpu->dar[15]; + case M68K_REG_ISP: return cpu->s_flag && !cpu->m_flag ? cpu->dar[15] : cpu->sp[4]; + case M68K_REG_MSP: return cpu->s_flag && cpu->m_flag ? cpu->dar[15] : cpu->sp[6]; + case M68K_REG_SFC: return cpu->sfc; + case M68K_REG_DFC: return cpu->dfc; + case M68K_REG_VBR: return cpu->vbr; + case M68K_REG_CACR: return cpu->cacr; + case M68K_REG_CAAR: return cpu->caar; + case M68K_REG_PREF_ADDR: return cpu->pref_addr; + case M68K_REG_PREF_DATA: return cpu->pref_data; + case M68K_REG_PPC: return MASK_OUT_ABOVE_32(cpu->ppc); + case M68K_REG_IR: return cpu->ir; + case M68K_REG_CPU_TYPE: + switch(cpu->cpu_type) + { + case CPU_TYPE_000: return (unsigned int)M68K_CPU_TYPE_68000; + case CPU_TYPE_010: return (unsigned int)M68K_CPU_TYPE_68010; + case CPU_TYPE_EC020: return (unsigned int)M68K_CPU_TYPE_68EC020; + case CPU_TYPE_020: return (unsigned int)M68K_CPU_TYPE_68020; + } + return M68K_CPU_TYPE_INVALID; + default: return 0; + } + return 0; +} + +void m68k_set_reg(m68k_register_t regnum, unsigned int value) +{ + switch(regnum) + { + case M68K_REG_D0: REG_D[0] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D1: REG_D[1] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D2: REG_D[2] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D3: REG_D[3] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D4: REG_D[4] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D5: REG_D[5] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D6: REG_D[6] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D7: REG_D[7] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A0: REG_A[0] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A1: REG_A[1] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A2: REG_A[2] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A3: REG_A[3] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A4: REG_A[4] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A5: REG_A[5] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A6: REG_A[6] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A7: REG_A[7] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_PC: m68ki_jump(MASK_OUT_ABOVE_32(value)); return; + case M68K_REG_SR: m68ki_set_sr(value); return; + case M68K_REG_SP: REG_SP = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_USP: if(FLAG_S) + REG_USP = MASK_OUT_ABOVE_32(value); + else + REG_SP = MASK_OUT_ABOVE_32(value); + return; + case M68K_REG_ISP: if(FLAG_S && !FLAG_M) + REG_SP = MASK_OUT_ABOVE_32(value); + else + REG_ISP = MASK_OUT_ABOVE_32(value); + return; + case M68K_REG_MSP: if(FLAG_S && FLAG_M) + REG_SP = MASK_OUT_ABOVE_32(value); + else + REG_MSP = MASK_OUT_ABOVE_32(value); + return; + case M68K_REG_VBR: REG_VBR = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_SFC: REG_SFC = value & 7; return; + case M68K_REG_DFC: REG_DFC = value & 7; return; + case M68K_REG_CACR: REG_CACR = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_CAAR: REG_CAAR = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_PPC: REG_PPC = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_IR: REG_IR = MASK_OUT_ABOVE_16(value); return; + case M68K_REG_CPU_TYPE: m68k_set_cpu_type(value); return; + default: return; + } +} + +/* Set the callbacks */ +void m68k_set_int_ack_callback(int (*callback)(int int_level)) +{ + CALLBACK_INT_ACK = callback ? callback : default_int_ack_callback; +} + +void m68k_set_bkpt_ack_callback(void (*callback)(unsigned int data)) +{ + CALLBACK_BKPT_ACK = callback ? callback : default_bkpt_ack_callback; +} + +void m68k_set_reset_instr_callback(void (*callback)(void)) +{ + CALLBACK_RESET_INSTR = callback ? callback : default_reset_instr_callback; +} + +void m68k_set_pc_changed_callback(void (*callback)(unsigned int new_pc)) +{ + CALLBACK_PC_CHANGED = callback ? callback : default_pc_changed_callback; +} + +void m68k_set_fc_callback(void (*callback)(unsigned int new_fc)) +{ + CALLBACK_SET_FC = callback ? callback : default_set_fc_callback; +} + +void m68k_set_instr_hook_callback(void (*callback)(void)) +{ + CALLBACK_INSTR_HOOK = callback ? callback : default_instr_hook_callback; +} + +#include +/* Set the CPU type. */ +void m68k_set_cpu_type(unsigned int cpu_type) +{ + switch(cpu_type) + { + case M68K_CPU_TYPE_68000: + CPU_TYPE = CPU_TYPE_000; + CPU_ADDRESS_MASK = 0x00ffffff; + CPU_SR_MASK = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */ + CYC_INSTRUCTION = m68ki_cycles[0]; + CYC_EXCEPTION = m68ki_exception_cycle_table[0]; + CYC_BCC_NOTAKE_B = -2; + CYC_BCC_NOTAKE_W = 2; + CYC_DBCC_F_NOEXP = -2; + CYC_DBCC_F_EXP = 2; + CYC_SCC_R_FALSE = 2; + CYC_MOVEM_W = 2; + CYC_MOVEM_L = 3; + CYC_SHIFT = 1; + CYC_RESET = 132; + return; + case M68K_CPU_TYPE_68010: + CPU_TYPE = CPU_TYPE_010; + CPU_ADDRESS_MASK = 0x00ffffff; + CPU_SR_MASK = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */ + CYC_INSTRUCTION = m68ki_cycles[1]; + CYC_EXCEPTION = m68ki_exception_cycle_table[1]; + CYC_BCC_NOTAKE_B = -4; + CYC_BCC_NOTAKE_W = 0; + CYC_DBCC_F_NOEXP = 0; + CYC_DBCC_F_EXP = 6; + CYC_SCC_R_FALSE = 0; + CYC_MOVEM_W = 2; + CYC_MOVEM_L = 3; + CYC_SHIFT = 1; + CYC_RESET = 130; + return; + case M68K_CPU_TYPE_68EC020: + CPU_TYPE = CPU_TYPE_EC020; + CPU_ADDRESS_MASK = 0x00ffffff; + CPU_SR_MASK = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */ + CYC_INSTRUCTION = m68ki_cycles[2]; + CYC_EXCEPTION = m68ki_exception_cycle_table[2]; + CYC_BCC_NOTAKE_B = -2; + CYC_BCC_NOTAKE_W = 0; + CYC_DBCC_F_NOEXP = 0; + CYC_DBCC_F_EXP = 4; + CYC_SCC_R_FALSE = 0; + CYC_MOVEM_W = 2; + CYC_MOVEM_L = 2; + CYC_SHIFT = 0; + CYC_RESET = 518; + return; + case M68K_CPU_TYPE_68020: + CPU_TYPE = CPU_TYPE_020; + CPU_ADDRESS_MASK = 0xffffffff; + CPU_SR_MASK = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */ + CYC_INSTRUCTION = m68ki_cycles[2]; + CYC_EXCEPTION = m68ki_exception_cycle_table[2]; + CYC_BCC_NOTAKE_B = -2; + CYC_BCC_NOTAKE_W = 0; + CYC_DBCC_F_NOEXP = 0; + CYC_DBCC_F_EXP = 4; + CYC_SCC_R_FALSE = 0; + CYC_MOVEM_W = 2; + CYC_MOVEM_L = 2; + CYC_SHIFT = 0; + CYC_RESET = 518; + return; + } +} + +/* Execute some instructions until we use up num_cycles clock cycles */ +/* ASG: removed per-instruction interrupt checks */ +int m68k_execute(int num_cycles) +{ + /* Make sure we're not stopped */ + if(!CPU_STOPPED) + { + /* Set our pool of clock cycles available */ + SET_CYCLES(num_cycles); + m68ki_initial_cycles = num_cycles; + + /* ASG: update cycles */ + USE_CYCLES(CPU_INT_CYCLES); + CPU_INT_CYCLES = 0; + + /* Return point if we had an address error */ + m68ki_set_address_error_trap(); /* auto-disable (see m68kcpu.h) */ + + /* Main loop. Keep going until we run out of clock cycles */ + do + { + /* Set tracing accodring to T1. (T0 is done inside instruction) */ + m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */ + + /* Set the address space for reads */ + m68ki_use_data_space(); /* auto-disable (see m68kcpu.h) */ + + /* Call external hook to peek at CPU */ + m68ki_instr_hook(); /* auto-disable (see m68kcpu.h) */ + + /* Record previous program counter */ + REG_PPC = REG_PC; + + /* Read an instruction and call its handler */ + REG_IR = m68ki_read_imm_16(); + m68ki_instruction_jump_table[REG_IR](); + USE_CYCLES(CYC_INSTRUCTION[REG_IR]); + + /* Trace m68k_exception, if necessary */ + m68ki_exception_if_trace(); /* auto-disable (see m68kcpu.h) */ + } while(GET_CYCLES() > 0); + + /* set previous PC to current PC for the next entry into the loop */ + REG_PPC = REG_PC; + + /* ASG: update cycles */ + USE_CYCLES(CPU_INT_CYCLES); + CPU_INT_CYCLES = 0; + + /* return how many clocks we used */ + return m68ki_initial_cycles - GET_CYCLES(); + } + + /* We get here if the CPU is stopped or halted */ + SET_CYCLES(0); + CPU_INT_CYCLES = 0; + + return num_cycles; +} + + +int m68k_cycles_run(void) +{ + return m68ki_initial_cycles - GET_CYCLES(); +} + +int m68k_cycles_remaining(void) +{ + return GET_CYCLES(); +} + +/* Change the timeslice */ +void m68k_modify_timeslice(int cycles) +{ + m68ki_initial_cycles += cycles; + ADD_CYCLES(cycles); +} + + +void m68k_end_timeslice(void) +{ + m68ki_initial_cycles = GET_CYCLES(); + SET_CYCLES(0); +} + + +/* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */ +/* KS: Modified so that IPL* bits match with mask positions in the SR + * and cleaned out remenants of the interrupt controller. + */ +void m68k_set_irq(unsigned int int_level) +{ + uint old_level = CPU_INT_LEVEL; + CPU_INT_LEVEL = int_level << 8; + + /* A transition from < 7 to 7 always interrupts (NMI) */ + /* Note: Level 7 can also level trigger like a normal IRQ */ + if(old_level != 0x0700 && CPU_INT_LEVEL == 0x0700) + m68ki_exception_interrupt(7); /* Edge triggered level 7 (NMI) */ + else + m68ki_check_interrupts(); /* Level triggered (IRQ) */ +} + + +/* Pulse the RESET line on the CPU */ +void m68k_pulse_reset(void) +{ + static uint emulation_initialized = 0; + + /* The first call to this function initializes the opcode handler jump table */ + if(!emulation_initialized) + { + m68ki_build_opcode_table(); + m68k_set_int_ack_callback(NULL); + m68k_set_bkpt_ack_callback(NULL); + m68k_set_reset_instr_callback(NULL); + m68k_set_pc_changed_callback(NULL); + m68k_set_fc_callback(NULL); + m68k_set_instr_hook_callback(NULL); + + emulation_initialized = 1; + } + + + if(CPU_TYPE == 0) /* KW 990319 */ + m68k_set_cpu_type(M68K_CPU_TYPE_68000); + + /* Clear all stop levels and eat up all remaining cycles */ + CPU_STOPPED = 0; + SET_CYCLES(0); + + /* Turn off tracing */ + FLAG_T1 = FLAG_T0 = 0; + m68ki_clear_trace(); + /* Interrupt mask to level 7 */ + FLAG_INT_MASK = 0x0700; + /* Reset VBR */ + REG_VBR = 0; + /* Go to supervisor mode */ + m68ki_set_sm_flag(SFLAG_SET | MFLAG_CLEAR); + + /* Invalidate the prefetch queue */ +#if M68K_EMULATE_PREFETCH + /* Set to arbitrary number since our first fetch is from 0 */ + CPU_PREF_ADDR = 0x1000; +#endif /* M68K_EMULATE_PREFETCH */ + + /* Read the initial stack pointer and program counter */ + m68ki_jump(0); + REG_SP = m68ki_read_imm_32(); + REG_PC = m68ki_read_imm_32(); + m68ki_jump(REG_PC); +} + +/* Pulse the HALT line on the CPU */ +void m68k_pulse_halt(void) +{ + CPU_STOPPED |= STOP_LEVEL_HALT; +} + + +/* Get and set the current CPU context */ +/* This is to allow for multiple CPUs */ +unsigned int m68k_context_size() +{ + return sizeof(m68ki_cpu_core); +} + +unsigned int m68k_get_context(void* dst) +{ + if(dst) *(m68ki_cpu_core*)dst = m68ki_cpu; + return sizeof(m68ki_cpu_core); +} + +void m68k_set_context(void* src) +{ + if(src) m68ki_cpu = *(m68ki_cpu_core*)src; +} + +void m68k_save_context( void (*save_value)(char*, unsigned int)) +{ + if(!save_value) + return; + + save_value("CPU_TYPE" , m68k_get_reg(NULL, M68K_REG_CPU_TYPE)); + save_value("D0" , REG_D[0]); + save_value("D1" , REG_D[1]); + save_value("D2" , REG_D[2]); + save_value("D3" , REG_D[3]); + save_value("D4" , REG_D[4]); + save_value("D5" , REG_D[5]); + save_value("D6" , REG_D[6]); + save_value("D7" , REG_D[7]); + save_value("A0" , REG_A[0]); + save_value("A1" , REG_A[1]); + save_value("A2" , REG_A[2]); + save_value("A3" , REG_A[3]); + save_value("A4" , REG_A[4]); + save_value("A5" , REG_A[5]); + save_value("A6" , REG_A[6]); + save_value("A7" , REG_A[7]); + save_value("PPC" , REG_PPC); + save_value("PC" , REG_PC); + save_value("USP" , REG_USP); + save_value("ISP" , REG_ISP); + save_value("MSP" , REG_MSP); + save_value("VBR" , REG_VBR); + save_value("SFC" , REG_SFC); + save_value("DFC" , REG_DFC); + save_value("CACR" , REG_CACR); + save_value("CAAR" , REG_CAAR); + save_value("SR" , m68ki_get_sr()); + save_value("INT_LEVEL" , CPU_INT_LEVEL); + save_value("INT_CYCLES", CPU_INT_CYCLES); + save_value("STOPPED" , (CPU_STOPPED & STOP_LEVEL_STOP) != 0); + save_value("HALTED" , (CPU_STOPPED & STOP_LEVEL_HALT) != 0); + save_value("PREF_ADDR" , CPU_PREF_ADDR); + save_value("PREF_DATA" , CPU_PREF_DATA); +} + +void m68k_load_context(unsigned int (*load_value)(char*)) +{ + unsigned int temp; + + m68k_set_cpu_type(load_value("CPU_TYPE")); + REG_PPC = load_value("PPC"); + REG_PC = load_value("PC"); + m68ki_jump(REG_PC); + CPU_INT_LEVEL = 0; + m68ki_set_sr_noint(load_value("SR")); + REG_D[0] = load_value("D0"); + REG_D[1] = load_value("D1"); + REG_D[2] = load_value("D2"); + REG_D[3] = load_value("D3"); + REG_D[4] = load_value("D4"); + REG_D[5] = load_value("D5"); + REG_D[6] = load_value("D6"); + REG_D[7] = load_value("D7"); + REG_A[0] = load_value("A0"); + REG_A[1] = load_value("A1"); + REG_A[2] = load_value("A2"); + REG_A[3] = load_value("A3"); + REG_A[4] = load_value("A4"); + REG_A[5] = load_value("A5"); + REG_A[6] = load_value("A6"); + REG_A[7] = load_value("A7"); + REG_USP = load_value("USP"); + REG_ISP = load_value("ISP"); + REG_MSP = load_value("MSP"); + REG_VBR = load_value("VBR"); + REG_SFC = load_value("SFC"); + REG_DFC = load_value("DFC"); + REG_CACR = load_value("CACR"); + REG_CAAR = load_value("CAAR"); + CPU_INT_LEVEL = load_value("INT_LEVEL"); + CPU_INT_CYCLES = load_value("INT_CYCLES"); + + CPU_STOPPED = 0; + temp = load_value("STOPPED"); + if(temp) CPU_STOPPED |= STOP_LEVEL_STOP; + temp = load_value("HALTED"); + if(temp) CPU_STOPPED |= STOP_LEVEL_HALT; + + CPU_PREF_ADDR = load_value("PREF_ADDR"); + CPU_PREF_DATA = load_value("PREF_DATA"); +} + + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ diff --git a/MCUME_teensy/teensygen/m68kcpu.h b/MCUME_teensy/teensygen/m68kcpu.h new file mode 100644 index 0000000..31fc87d --- /dev/null +++ b/MCUME_teensy/teensygen/m68kcpu.h @@ -0,0 +1,1839 @@ +#include "shared.h" +#include +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.3 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * + * This code may be freely used for non-commercial purposes as long as this + * copyright notice remains unaltered in the source code and any binary files + * containing this code in compiled form. + * + * All other lisencing terms must be negotiated with the author + * (Karl Stenerud). + * + * The latest version of this code can be obtained at: + * http://kstenerud.cjb.net + */ + + + + +#ifndef M68KCPU__HEADER +#define M68KCPU__HEADER + +#include "m68k.h" +#include + +#if M68K_EMULATE_ADDRESS_ERROR +#include +#endif /* M68K_EMULATE_ADDRESS_ERROR */ + +/* ======================================================================== */ +/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */ +/* ======================================================================== */ + +/* Check for > 32bit sizes */ +#if UINT_MAX > 0xffffffff + #define M68K_INT_GT_32_BIT 1 +#endif + +/* Data types used in this emulation core */ +#undef sint8 +#undef sint16 +#undef sint32 +#undef sint64 +#undef uint8 +#undef uint16 +#undef uint32 +#undef uint64 +#undef sint +#undef uint + +#define sint8 signed char /* ASG: changed from char to signed char */ +#define sint16 signed short +#define sint32 signed long +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned long + +/* signed and unsigned int must be at least 32 bits wide */ +#define sint signed int +#define uint unsigned int + + +#if M68K_USE_64_BIT +#define sint64 signed long long +#define uint64 unsigned long long +#else +#define sint64 sint32 +#define uint64 uint32 +#endif /* M68K_USE_64_BIT */ + + + +/* Allow for architectures that don't have 8-bit sizes */ +#if UCHAR_MAX == 0xff + #define MAKE_INT_8(A) (sint8)(A) +#else + #undef sint8 + #define sint8 signed int + #undef uint8 + #define uint8 unsigned int + INLINE sint MAKE_INT_8(uint value) + { + return (value & 0x80) ? value | ~0xff : value & 0xff; + } +#endif /* UCHAR_MAX == 0xff */ + + +/* Allow for architectures that don't have 16-bit sizes */ +#if USHRT_MAX == 0xffff + #define MAKE_INT_16(A) (sint16)(A) +#else + #undef sint16 + #define sint16 signed int + #undef uint16 + #define uint16 unsigned int + INLINE sint MAKE_INT_16(uint value) + { + return (value & 0x8000) ? value | ~0xffff : value & 0xffff; + } +#endif /* USHRT_MAX == 0xffff */ + + +/* Allow for architectures that don't have 32-bit sizes */ +#if ULONG_MAX == 0xffffffff + #define MAKE_INT_32(A) (sint32)(A) +#else + #undef sint32 + #define sint32 signed int + #undef uint32 + #define uint32 unsigned int + INLINE sint MAKE_INT_32(uint value) + { + return (value & 0x80000000) ? value | ~0xffffffff : value & 0xffffffff; + } +#endif /* ULONG_MAX == 0xffffffff */ + + + + +/* ======================================================================== */ +/* ============================ GENERAL DEFINES =========================== */ +/* ======================================================================== */ + +/* Exception Vectors handled by emulation */ +#define EXCEPTION_BUS_ERROR 2 /* This one is not emulated! */ +#define EXCEPTION_ADDRESS_ERROR 3 /* This one is partially emulated (doesn't stack a proper frame yet) */ +#define EXCEPTION_ILLEGAL_INSTRUCTION 4 +#define EXCEPTION_ZERO_DIVIDE 5 +#define EXCEPTION_CHK 6 +#define EXCEPTION_TRAPV 7 +#define EXCEPTION_PRIVILEGE_VIOLATION 8 +#define EXCEPTION_TRACE 9 +#define EXCEPTION_1010 10 +#define EXCEPTION_1111 11 +#define EXCEPTION_FORMAT_ERROR 14 +#define EXCEPTION_UNINITIALIZED_INTERRUPT 15 +#define EXCEPTION_SPURIOUS_INTERRUPT 24 +#define EXCEPTION_INTERRUPT_AUTOVECTOR 24 +#define EXCEPTION_TRAP_BASE 32 + +/* Function codes set by CPU during data/address bus activity */ +#define FUNCTION_CODE_USER_DATA 1 +#define FUNCTION_CODE_USER_PROGRAM 2 +#define FUNCTION_CODE_SUPERVISOR_DATA 5 +#define FUNCTION_CODE_SUPERVISOR_PROGRAM 6 +#define FUNCTION_CODE_CPU_SPACE 7 + +/* CPU types for deciding what to emulate */ +#define CPU_TYPE_000 1 +#define CPU_TYPE_010 2 +#define CPU_TYPE_EC020 4 +#define CPU_TYPE_020 8 + +/* Different ways to stop the CPU */ +#define STOP_LEVEL_STOP 1 +#define STOP_LEVEL_HALT 2 + +#ifndef NULL +#define NULL ((void*)0) +#endif + +/* ======================================================================== */ +/* ================================ MACROS ================================ */ +/* ======================================================================== */ + + +/* ---------------------------- General Macros ---------------------------- */ + +/* Bit Isolation Macros */ +#define BIT_0(A) ((A) & 0x00000001) +#define BIT_1(A) ((A) & 0x00000002) +#define BIT_2(A) ((A) & 0x00000004) +#define BIT_3(A) ((A) & 0x00000008) +#define BIT_4(A) ((A) & 0x00000010) +#define BIT_5(A) ((A) & 0x00000020) +#define BIT_6(A) ((A) & 0x00000040) +#define BIT_7(A) ((A) & 0x00000080) +#define BIT_8(A) ((A) & 0x00000100) +#define BIT_9(A) ((A) & 0x00000200) +#define BIT_A(A) ((A) & 0x00000400) +#define BIT_B(A) ((A) & 0x00000800) +#define BIT_C(A) ((A) & 0x00001000) +#define BIT_D(A) ((A) & 0x00002000) +#define BIT_E(A) ((A) & 0x00004000) +#define BIT_F(A) ((A) & 0x00008000) +#define BIT_10(A) ((A) & 0x00010000) +#define BIT_11(A) ((A) & 0x00020000) +#define BIT_12(A) ((A) & 0x00040000) +#define BIT_13(A) ((A) & 0x00080000) +#define BIT_14(A) ((A) & 0x00100000) +#define BIT_15(A) ((A) & 0x00200000) +#define BIT_16(A) ((A) & 0x00400000) +#define BIT_17(A) ((A) & 0x00800000) +#define BIT_18(A) ((A) & 0x01000000) +#define BIT_19(A) ((A) & 0x02000000) +#define BIT_1A(A) ((A) & 0x04000000) +#define BIT_1B(A) ((A) & 0x08000000) +#define BIT_1C(A) ((A) & 0x10000000) +#define BIT_1D(A) ((A) & 0x20000000) +#define BIT_1E(A) ((A) & 0x40000000) +#define BIT_1F(A) ((A) & 0x80000000) + +/* Get the most significant bit for specific sizes */ +#define GET_MSB_8(A) ((A) & 0x80) +#define GET_MSB_9(A) ((A) & 0x100) +#define GET_MSB_16(A) ((A) & 0x8000) +#define GET_MSB_17(A) ((A) & 0x10000) +#define GET_MSB_32(A) ((A) & 0x80000000) +#if M68K_USE_64_BIT +#define GET_MSB_33(A) ((A) & 0x100000000) +#endif /* M68K_USE_64_BIT */ + +/* Isolate nibbles */ +#define LOW_NIBBLE(A) ((A) & 0x0f) +#define HIGH_NIBBLE(A) ((A) & 0xf0) + +/* These are used to isolate 8, 16, and 32 bit sizes */ +#define MASK_OUT_ABOVE_2(A) ((A) & 3) +#define MASK_OUT_ABOVE_8(A) ((A) & 0xff) +#define MASK_OUT_ABOVE_16(A) ((A) & 0xffff) +#define MASK_OUT_BELOW_2(A) ((A) & ~3) +#define MASK_OUT_BELOW_8(A) ((A) & ~0xff) +#define MASK_OUT_BELOW_16(A) ((A) & ~0xffff) + +/* No need to mask if we are 32 bit */ +#if M68K_INT_GT_32BIT || M68K_USE_64_BIT + #define MASK_OUT_ABOVE_32(A) ((A) & 0xffffffff) + #define MASK_OUT_BELOW_32(A) ((A) & ~0xffffffff) +#else + #define MASK_OUT_ABOVE_32(A) (A) + #define MASK_OUT_BELOW_32(A) 0 +#endif /* M68K_INT_GT_32BIT || M68K_USE_64_BIT */ + +/* Simulate address lines of 68k family */ +#define ADDRESS_68K(A) ((A)&CPU_ADDRESS_MASK) + + +/* Shift & Rotate Macros. */ +#define LSL(A, C) ((A) << (C)) +#define LSR(A, C) ((A) >> (C)) + +/* Some > 32-bit optimizations */ +#if M68K_INT_GT_32BIT + /* Shift left and right */ + #define LSR_32(A, C) ((A) >> (C)) + #define LSL_32(A, C) ((A) << (C)) +#else + /* We have to do this because the morons at ANSI decided that shifts + * by >= data size are undefined. + */ + #define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0) + #define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0) +#endif /* M68K_INT_GT_32BIT */ + +#if M68K_USE_64_BIT + #define LSL_32_64(A, C) ((A) << (C)) + #define LSR_32_64(A, C) ((A) >> (C)) + #define ROL_33_64(A, C) (LSL_32_64(A, C) | LSR_32_64(A, 33-(C))) + #define ROR_33_64(A, C) (LSR_32_64(A, C) | LSL_32_64(A, 33-(C))) +#endif /* M68K_USE_64_BIT */ + +#define ROL_8(A, C) MASK_OUT_ABOVE_8(LSL(A, C) | LSR(A, 8-(C))) +#define ROL_9(A, C) (LSL(A, C) | LSR(A, 9-(C))) +#define ROL_16(A, C) MASK_OUT_ABOVE_16(LSL(A, C) | LSR(A, 16-(C))) +#define ROL_17(A, C) (LSL(A, C) | LSR(A, 17-(C))) +#define ROL_32(A, C) MASK_OUT_ABOVE_32(LSL_32(A, C) | LSR_32(A, 32-(C))) +#define ROL_33(A, C) (LSL_32(A, C) | LSR_32(A, 33-(C))) + +#define ROR_8(A, C) MASK_OUT_ABOVE_8(LSR(A, C) | LSL(A, 8-(C))) +#define ROR_9(A, C) (LSR(A, C) | LSL(A, 9-(C))) +#define ROR_16(A, C) MASK_OUT_ABOVE_16(LSR(A, C) | LSL(A, 16-(C))) +#define ROR_17(A, C) (LSR(A, C) | LSL(A, 17-(C))) +#define ROR_32(A, C) MASK_OUT_ABOVE_32(LSR_32(A, C) | LSL_32(A, 32-(C))) +#define ROR_33(A, C) (LSR_32(A, C) | LSL_32(A, 33-(C))) + + + +/* ------------------------------ CPU Access ------------------------------ */ + +/* Access the CPU registers */ +#define CPU_TYPE m68ki_cpu.cpu_type + +#define REG_DA m68ki_cpu.dar /* easy access to data and address regs */ +#define REG_D m68ki_cpu.dar +#define REG_A (m68ki_cpu.dar+8) +#define REG_PPC m68ki_cpu.ppc +#define REG_PC m68ki_cpu.pc +#define REG_SP_BASE m68ki_cpu.sp +#define REG_USP m68ki_cpu.sp[0] +#define REG_ISP m68ki_cpu.sp[4] +#define REG_MSP m68ki_cpu.sp[6] +#define REG_SP m68ki_cpu.dar[15] +#define REG_VBR m68ki_cpu.vbr +#define REG_SFC m68ki_cpu.sfc +#define REG_DFC m68ki_cpu.dfc +#define REG_CACR m68ki_cpu.cacr +#define REG_CAAR m68ki_cpu.caar +#define REG_IR m68ki_cpu.ir + +#define FLAG_T1 m68ki_cpu.t1_flag +#define FLAG_T0 m68ki_cpu.t0_flag +#define FLAG_S m68ki_cpu.s_flag +#define FLAG_M m68ki_cpu.m_flag +#define FLAG_X m68ki_cpu.x_flag +#define FLAG_N m68ki_cpu.n_flag +#define FLAG_Z m68ki_cpu.not_z_flag +#define FLAG_V m68ki_cpu.v_flag +#define FLAG_C m68ki_cpu.c_flag +#define FLAG_INT_MASK m68ki_cpu.int_mask + +#define CPU_INT_LEVEL m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */ +#define CPU_INT_CYCLES m68ki_cpu.int_cycles /* ASG */ +#define CPU_STOPPED m68ki_cpu.stopped +#define CPU_PREF_ADDR m68ki_cpu.pref_addr +#define CPU_PREF_DATA m68ki_cpu.pref_data +#define CPU_ADDRESS_MASK m68ki_cpu.address_mask +#define CPU_SR_MASK m68ki_cpu.sr_mask + +#define CYC_INSTRUCTION m68ki_cpu.cyc_instruction +#define CYC_EXCEPTION m68ki_cpu.cyc_exception +#define CYC_BCC_NOTAKE_B m68ki_cpu.cyc_bcc_notake_b +#define CYC_BCC_NOTAKE_W m68ki_cpu.cyc_bcc_notake_w +#define CYC_DBCC_F_NOEXP m68ki_cpu.cyc_dbcc_f_noexp +#define CYC_DBCC_F_EXP m68ki_cpu.cyc_dbcc_f_exp +#define CYC_SCC_R_FALSE m68ki_cpu.cyc_scc_r_false +#define CYC_MOVEM_W m68ki_cpu.cyc_movem_w +#define CYC_MOVEM_L m68ki_cpu.cyc_movem_l +#define CYC_SHIFT m68ki_cpu.cyc_shift +#define CYC_RESET m68ki_cpu.cyc_reset + + +#define CALLBACK_INT_ACK m68ki_cpu.int_ack_callback +#define CALLBACK_BKPT_ACK m68ki_cpu.bkpt_ack_callback +#define CALLBACK_RESET_INSTR m68ki_cpu.reset_instr_callback +#define CALLBACK_PC_CHANGED m68ki_cpu.pc_changed_callback +#define CALLBACK_SET_FC m68ki_cpu.set_fc_callback +#define CALLBACK_INSTR_HOOK m68ki_cpu.instr_hook_callback + + + +/* ----------------------------- Configuration ---------------------------- */ + +/* These defines are dependant on the configuration defines in m68kconf.h */ + +/* Disable certain comparisons if we're not using all CPU types */ +#if M68K_EMULATE_020 + #define CPU_TYPE_IS_020_PLUS(A) ((A) & CPU_TYPE_020) + #define CPU_TYPE_IS_020_LESS(A) 1 +#else + #define CPU_TYPE_IS_020_PLUS(A) 0 + #define CPU_TYPE_IS_020_LESS(A) 1 +#endif + +#if M68K_EMULATE_EC020 + #define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020)) + #define CPU_TYPE_IS_EC020_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_010 | CPU_TYPE_EC020)) +#else + #define CPU_TYPE_IS_EC020_PLUS(A) CPU_TYPE_IS_020_PLUS(A) + #define CPU_TYPE_IS_EC020_LESS(A) CPU_TYPE_IS_020_LESS(A) +#endif + +#if M68K_EMULATE_010 + #define CPU_TYPE_IS_010(A) ((A) == CPU_TYPE_010) + #define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020)) + #define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_010)) +#else + #define CPU_TYPE_IS_010(A) 0 + #define CPU_TYPE_IS_010_PLUS(A) CPU_TYPE_IS_EC020_PLUS(A) + #define CPU_TYPE_IS_010_LESS(A) CPU_TYPE_IS_EC020_LESS(A) +#endif + +#if M68K_EMULATE_020 || M68K_EMULATE_EC020 + #define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020)) +#else + #define CPU_TYPE_IS_020_VARIANT(A) 0 +#endif + +#if M68K_EMULATE_020 || M68K_EMULATE_EC020 || M68K_EMULATE_010 + #define CPU_TYPE_IS_000(A) ((A) == CPU_TYPE_000) +#else + #define CPU_TYPE_IS_000(A) 1 +#endif + + +#if !M68K_SEPARATE_READS +#define m68k_read_immediate_16(A) m68ki_read_program_16(A) +#define m68k_read_immediate_32(A) m68ki_read_program_32(A) + +#define m68k_read_pcrelative_8(A) m68ki_read_program_8(A) +#define m68k_read_pcrelative_16(A) m68ki_read_program_16(A) +#define m68k_read_pcrelative_32(A) m68ki_read_program_32(A) +#endif /* M68K_SEPARATE_READS */ + + +/* Enable or disable callback functions */ +#if M68K_EMULATE_INT_ACK + #if M68K_EMULATE_INT_ACK == OPT_SPECIFY_HANDLER + #define m68ki_int_ack(A) M68K_INT_ACK_CALLBACK(A) + #else + #define m68ki_int_ack(A) CALLBACK_INT_ACK(A) + #endif +#else + /* Default action is to used autovector mode, which is most common */ + #define m68ki_int_ack(A) M68K_INT_ACK_AUTOVECTOR +#endif /* M68K_EMULATE_INT_ACK */ + +#if M68K_EMULATE_BKPT_ACK + #if M68K_EMULATE_BKPT_ACK == OPT_SPECIFY_HANDLER + #define m68ki_bkpt_ack(A) M68K_BKPT_ACK_CALLBACK(A) + #else + #define m68ki_bkpt_ack(A) CALLBACK_BKPT_ACK(A) + #endif +#else + #define m68ki_bkpt_ack(A) +#endif /* M68K_EMULATE_BKPT_ACK */ + +#if M68K_EMULATE_RESET + #if M68K_EMULATE_RESET == OPT_SPECIFY_HANDLER + #define m68ki_output_reset() M68K_RESET_CALLBACK() + #else + #define m68ki_output_reset() CALLBACK_RESET_INSTR() + #endif +#else + #define m68ki_output_reset() +#endif /* M68K_EMULATE_RESET */ + +#if M68K_INSTRUCTION_HOOK + #if M68K_INSTRUCTION_HOOK == OPT_SPECIFY_HANDLER + #define m68ki_instr_hook() M68K_INSTRUCTION_CALLBACK() + #else + #define m68ki_instr_hook() CALLBACK_INSTR_HOOK() + #endif +#else + #define m68ki_instr_hook() +#endif /* M68K_INSTRUCTION_HOOK */ + +#if M68K_MONITOR_PC + #if M68K_MONITOR_PC == OPT_SPECIFY_HANDLER + #define m68ki_pc_changed(A) M68K_SET_PC_CALLBACK(ADDRESS_68K(A)) + #else + #define m68ki_pc_changed(A) CALLBACK_PC_CHANGED(ADDRESS_68K(A)) + #endif +#else + #define m68ki_pc_changed(A) +#endif /* M68K_MONITOR_PC */ + + +/* Enable or disable function code emulation */ +#if M68K_EMULATE_FC + #if M68K_EMULATE_FC == OPT_SPECIFY_HANDLER + #define m68ki_set_fc(A) M68K_SET_FC_CALLBACK(A) + #else + #define m68ki_set_fc(A) CALLBACK_SET_FC(A) + #endif + #define m68ki_use_data_space() m68ki_address_space = FUNCTION_CODE_USER_DATA + #define m68ki_use_program_space() m68ki_address_space = FUNCTION_CODE_USER_PROGRAM + #define m68ki_get_address_space() m68ki_address_space +#else + #define m68ki_set_fc(A) + #define m68ki_use_data_space() + #define m68ki_use_program_space() + #define m68ki_get_address_space() FUNCTION_CODE_USER_DATA +#endif /* M68K_EMULATE_FC */ + + +/* Enable or disable trace emulation */ +#if M68K_EMULATE_TRACE + /* Initiates trace checking before each instruction (t1) */ + #define m68ki_trace_t1() m68ki_tracing = FLAG_T1 + /* adds t0 to trace checking if we encounter change of flow */ + #define m68ki_trace_t0() m68ki_tracing |= FLAG_T0 + /* Clear all tracing */ + #define m68ki_clear_trace() m68ki_tracing = 0 + /* Cause a trace exception if we are tracing */ + #define m68ki_exception_if_trace() if(m68ki_tracing) m68ki_exception_trace() +#else + #define m68ki_trace_t1() + #define m68ki_trace_t0() + #define m68ki_clear_trace() + #define m68ki_exception_if_trace() +#endif /* M68K_EMULATE_TRACE */ + + + +/* Address error */ +#if M68K_EMULATE_ADDRESS_ERROR + extern jmp_buf m68ki_address_error_trap; + #define m68ki_set_address_error_trap() if(setjmp(m68ki_address_error_trap)) m68ki_exception_address_error(); + #define m68ki_check_address_error(A) if((A)&1) longjmp(m68ki_address_error_jump, 1); +#else + #define m68ki_set_address_error_trap() + #define m68ki_check_address_error(A) +#endif /* M68K_ADDRESS_ERROR */ + +/* Logging */ +#if M68K_LOG_ENABLE + #include + extern FILE* M68K_LOG_FILEHANDLE + extern char* m68ki_cpu_names[]; + + #define M68K_DO_LOG(A) if(M68K_LOG_FILEHANDLE) fprintf A + #if M68K_LOG_1010_1111 + #define M68K_DO_LOG_EMU(A) if(M68K_LOG_FILEHANDLE) fprintf A + #else + #define M68K_DO_LOG_EMU(A) + #endif +#else + #define M68K_DO_LOG(A) + #define M68K_DO_LOG_EMU(A) +#endif + + + +/* -------------------------- EA / Operand Access ------------------------- */ + +/* + * The general instruction format follows this pattern: + * .... XXX. .... .YYY + * where XXX is register X and YYY is register Y + */ +/* Data Register Isolation */ +#define DX (REG_D[(REG_IR >> 9) & 7]) +#define DY (REG_D[REG_IR & 7]) +/* Address Register Isolation */ +#define AX (REG_A[(REG_IR >> 9) & 7]) +#define AY (REG_A[REG_IR & 7]) + + +/* Effective Address Calculations */ +#define EA_AY_AI_8() AY /* address register indirect */ +#define EA_AY_AI_16() EA_AY_AI_8() +#define EA_AY_AI_32() EA_AY_AI_8() +#define EA_AY_PI_8() (AY++) /* postincrement (size = byte) */ +#define EA_AY_PI_16() ((AY+=2)-2) /* postincrement (size = word) */ +#define EA_AY_PI_32() ((AY+=4)-4) /* postincrement (size = long) */ +#define EA_AY_PD_8() (--AY) /* predecrement (size = byte) */ +#define EA_AY_PD_16() (AY-=2) /* predecrement (size = word) */ +#define EA_AY_PD_32() (AY-=4) /* predecrement (size = long) */ +#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */ +#define EA_AY_DI_16() EA_AY_DI_8() +#define EA_AY_DI_32() EA_AY_DI_8() +#define EA_AY_IX_8() m68ki_get_ea_ix(AY) /* indirect + index */ +#define EA_AY_IX_16() EA_AY_IX_8() +#define EA_AY_IX_32() EA_AY_IX_8() + +#define EA_AX_AI_8() AX +#define EA_AX_AI_16() EA_AX_AI_8() +#define EA_AX_AI_32() EA_AX_AI_8() +#define EA_AX_PI_8() (AX++) +#define EA_AX_PI_16() ((AX+=2)-2) +#define EA_AX_PI_32() ((AX+=4)-4) +#define EA_AX_PD_8() (--AX) +#define EA_AX_PD_16() (AX-=2) +#define EA_AX_PD_32() (AX-=4) +#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16())) +#define EA_AX_DI_16() EA_AX_DI_8() +#define EA_AX_DI_32() EA_AX_DI_8() +#define EA_AX_IX_8() m68ki_get_ea_ix(AX) +#define EA_AX_IX_16() EA_AX_IX_8() +#define EA_AX_IX_32() EA_AX_IX_8() + +#define EA_A7_PI_8() ((REG_A[7]+=2)-2) +#define EA_A7_PD_8() (REG_A[7]-=2) + +#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16()) /* absolute word */ +#define EA_AW_16() EA_AW_8() +#define EA_AW_32() EA_AW_8() +#define EA_AL_8() m68ki_read_imm_32() /* absolute long */ +#define EA_AL_16() EA_AL_8() +#define EA_AL_32() EA_AL_8() +#define EA_PCDI_8() m68ki_get_ea_pcdi() /* pc indirect + displacement */ +#define EA_PCDI_16() EA_PCDI_8() +#define EA_PCDI_32() EA_PCDI_8() +#define EA_PCIX_8() m68ki_get_ea_pcix() /* pc indirect + index */ +#define EA_PCIX_16() EA_PCIX_8() +#define EA_PCIX_32() EA_PCIX_8() + + +#define OPER_I_8() m68ki_read_imm_8() +#define OPER_I_16() m68ki_read_imm_16() +#define OPER_I_32() m68ki_read_imm_32() + + + +/* --------------------------- Status Register ---------------------------- */ + +/* Flag Calculation Macros */ +#define CFLAG_8(A) (A) +#define CFLAG_16(A) ((A)>>8) + +#if M68K_INT_GT_32_BIT + #define CFLAG_ADD_32(S, D, R) ((R)>>24) + #define CFLAG_SUB_32(S, D, R) ((R)>>24) +#else + #define CFLAG_ADD_32(S, D, R) (((S & D) | (~R & (S | D)))>>23) + #define CFLAG_SUB_32(S, D, R) (((S & R) | (~D & (S | R)))>>23) +#endif /* M68K_INT_GT_32_BIT */ + +#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R)) +#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8) +#define VFLAG_ADD_32(S, D, R) (((S^R) & (D^R))>>24) + +#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D)) +#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8) +#define VFLAG_SUB_32(S, D, R) (((S^D) & (R^D))>>24) + +#define NFLAG_8(A) (A) +#define NFLAG_16(A) ((A)>>8) +#define NFLAG_32(A) ((A)>>24) +#define NFLAG_64(A) ((A)>>56) + +#define ZFLAG_8(A) MASK_OUT_ABOVE_8(A) +#define ZFLAG_16(A) MASK_OUT_ABOVE_16(A) +#define ZFLAG_32(A) MASK_OUT_ABOVE_32(A) + + +/* Flag values */ +#define NFLAG_SET 0x80 +#define NFLAG_CLEAR 0 +#define CFLAG_SET 0x100 +#define CFLAG_CLEAR 0 +#define XFLAG_SET 0x100 +#define XFLAG_CLEAR 0 +#define VFLAG_SET 0x80 +#define VFLAG_CLEAR 0 +#define ZFLAG_SET 0 +#define ZFLAG_CLEAR 0xffffffff + +#define SFLAG_SET 4 +#define SFLAG_CLEAR 0 +#define MFLAG_SET 2 +#define MFLAG_CLEAR 0 + +/* Turn flag values into 1 or 0 */ +#define XFLAG_AS_1() ((FLAG_X>>8)&1) +#define NFLAG_AS_1() ((FLAG_N>>7)&1) +#define VFLAG_AS_1() ((FLAG_V>>7)&1) +#define ZFLAG_AS_1() (!FLAG_Z) +#define CFLAG_AS_1() ((FLAG_C>>8)&1) + + +/* Conditions */ +#define COND_CS() (FLAG_C&0x100) +#define COND_CC() (!COND_CS()) +#define COND_VS() (FLAG_V&0x80) +#define COND_VC() (!COND_VS()) +#define COND_NE() FLAG_Z +#define COND_EQ() (!COND_NE()) +#define COND_MI() (FLAG_N&0x80) +#define COND_PL() (!COND_MI()) +#define COND_LT() ((FLAG_N^FLAG_V)&0x80) +#define COND_GE() (!COND_LT()) +#define COND_HI() (COND_CC() && COND_NE()) +#define COND_LS() (COND_CS() || COND_EQ()) +#define COND_GT() (COND_GE() && COND_NE()) +#define COND_LE() (COND_LT() || COND_EQ()) + +/* Reversed conditions */ +#define COND_NOT_CS() COND_CC() +#define COND_NOT_CC() COND_CS() +#define COND_NOT_VS() COND_VC() +#define COND_NOT_VC() COND_VS() +#define COND_NOT_NE() COND_EQ() +#define COND_NOT_EQ() COND_NE() +#define COND_NOT_MI() COND_PL() +#define COND_NOT_PL() COND_MI() +#define COND_NOT_LT() COND_GE() +#define COND_NOT_GE() COND_LT() +#define COND_NOT_HI() COND_LS() +#define COND_NOT_LS() COND_HI() +#define COND_NOT_GT() COND_LE() +#define COND_NOT_LE() COND_GT() + +/* Not real conditions, but here for convenience */ +#define COND_XS() (FLAG_X&0x100) +#define COND_XC() (!COND_XS) + + +/* Get the condition code register */ +#define m68ki_get_ccr() ((COND_XS() >> 4) | \ + (COND_MI() >> 4) | \ + (COND_EQ() << 2) | \ + (COND_VS() >> 6) | \ + (COND_CS() >> 8)) + +/* Get the status register */ +#define m68ki_get_sr() ( FLAG_T1 | \ + FLAG_T0 | \ + (FLAG_S << 11) | \ + (FLAG_M << 11) | \ + FLAG_INT_MASK | \ + m68ki_get_ccr()) + + + +/* ---------------------------- Cycle Counting ---------------------------- */ + +#define ADD_CYCLES(A) m68ki_remaining_cycles += (A) +#define USE_CYCLES(A) m68ki_remaining_cycles -= (A) +#define SET_CYCLES(A) m68ki_remaining_cycles = A +#define GET_CYCLES() m68ki_remaining_cycles +#define USE_ALL_CYCLES() m68ki_remaining_cycles = 0 + + + +/* ----------------------------- Read / Write ----------------------------- */ + +/* Read from the current address space */ +#define m68ki_read_8(A) m68ki_read_8_fc (A, FLAG_S | m68ki_get_address_space()) +#define m68ki_read_16(A) m68ki_read_16_fc(A, FLAG_S | m68ki_get_address_space()) +#define m68ki_read_32(A) m68ki_read_32_fc(A, FLAG_S | m68ki_get_address_space()) + +/* Write to the current data space */ +#define m68ki_write_8(A, V) m68ki_write_8_fc (A, FLAG_S | FUNCTION_CODE_USER_DATA, V) +#define m68ki_write_16(A, V) m68ki_write_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) +#define m68ki_write_32(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) + +/* map read immediate 8 to read immediate 16 */ +#define m68ki_read_imm_8() MASK_OUT_ABOVE_8(m68ki_read_imm_16()) + +/* Map PC-relative reads */ +#define m68ki_read_pcrel_8(A) m68k_read_pcrelative_8(A) +#define m68ki_read_pcrel_16(A) m68k_read_pcrelative_16(A) +#define m68ki_read_pcrel_32(A) m68k_read_pcrelative_32(A) + +/* Read from the program space */ +#define m68ki_read_program_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM) +#define m68ki_read_program_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM) +#define m68ki_read_program_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM) + +/* Read from the data space */ +#define m68ki_read_data_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA) +#define m68ki_read_data_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA) +#define m68ki_read_data_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA) + + + +/* ======================================================================== */ +/* =============================== PROTOTYPES ============================= */ +/* ======================================================================== */ + +typedef struct +{ + uint cpu_type; /* CPU Type: 68000, 68010, 68EC020, or 68020 */ + uint dar[16]; /* Data and Address Registers */ + uint ppc; /* Previous program counter */ + uint pc; /* Program Counter */ + uint sp[7]; /* User, Interrupt, and Master Stack Pointers */ + uint vbr; /* Vector Base Register (m68010+) */ + uint sfc; /* Source Function Code Register (m68010+) */ + uint dfc; /* Destination Function Code Register (m68010+) */ + uint cacr; /* Cache Control Register (m68020, unemulated) */ + uint caar; /* Cache Address Register (m68020, unemulated) */ + uint ir; /* Instruction Register */ + uint t1_flag; /* Trace 1 */ + uint t0_flag; /* Trace 0 */ + uint s_flag; /* Supervisor */ + uint m_flag; /* Master/Interrupt state */ + uint x_flag; /* Extend */ + uint n_flag; /* Negative */ + uint not_z_flag; /* Zero, inverted for speedups */ + uint v_flag; /* Overflow */ + uint c_flag; /* Carry */ + uint int_mask; /* I0-I2 */ + uint int_level; /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */ + uint int_cycles; /* ASG: extra cycles from generated interrupts */ + uint stopped; /* Stopped state */ + uint pref_addr; /* Last prefetch address */ + uint pref_data; /* Data in the prefetch queue */ + uint address_mask; /* Available address pins */ + uint sr_mask; /* Implemented status register bits */ + + /* Clocks required for instructions / exceptions */ + uint cyc_bcc_notake_b; + uint cyc_bcc_notake_w; + uint cyc_dbcc_f_noexp; + uint cyc_dbcc_f_exp; + uint cyc_scc_r_false; + uint cyc_movem_w; + uint cyc_movem_l; + uint cyc_shift; + uint cyc_reset; + uint8* cyc_instruction; + uint8* cyc_exception; + + /* Callbacks to host */ + int (*int_ack_callback)(int int_line); /* Interrupt Acknowledge */ + void (*bkpt_ack_callback)(unsigned int data); /* Breakpoint Acknowledge */ + void (*reset_instr_callback)(void); /* Called when a RESET instruction is encountered */ + void (*pc_changed_callback)(unsigned int new_pc); /* Called when the PC changes by a large amount */ + void (*set_fc_callback)(unsigned int new_fc); /* Called when the CPU function code changes */ + void (*instr_hook_callback)(void); /* Called every instruction cycle prior to execution */ + +} m68ki_cpu_core; + + +extern m68ki_cpu_core m68ki_cpu; +extern sint m68ki_remaining_cycles; +extern uint m68ki_tracing; +extern const uint8 m68ki_shift_8_table[]; +extern const uint16 m68ki_shift_16_table[]; +extern const uint m68ki_shift_32_table[]; +extern const uint8 m68ki_exception_cycle_table[][256]; +extern uint m68ki_address_space; +extern const uint8 m68ki_ea_idx_cycle_table[]; + + +/* Read data immediately after the program counter */ +INLINE uint m68ki_read_imm_16(void); +INLINE uint m68ki_read_imm_32(void); + +/* Read data with specific function code */ +INLINE uint m68ki_read_8_fc (uint address, uint fc); +INLINE uint m68ki_read_16_fc (uint address, uint fc); +INLINE uint m68ki_read_32_fc (uint address, uint fc); + +/* Write data with specific function code */ +INLINE void m68ki_write_8_fc (uint address, uint fc, uint value); +INLINE void m68ki_write_16_fc(uint address, uint fc, uint value); +INLINE void m68ki_write_32_fc(uint address, uint fc, uint value); + +/* Indexed and PC-relative ea fetching */ +INLINE uint m68ki_get_ea_pcdi(void); +INLINE uint m68ki_get_ea_pcix(void); +INLINE uint m68ki_get_ea_ix(uint An); + +/* Operand fetching */ +INLINE uint OPER_AY_AI_8(void); +INLINE uint OPER_AY_AI_16(void); +INLINE uint OPER_AY_AI_32(void); +INLINE uint OPER_AY_PI_8(void); +INLINE uint OPER_AY_PI_16(void); +INLINE uint OPER_AY_PI_32(void); +INLINE uint OPER_AY_PD_8(void); +INLINE uint OPER_AY_PD_16(void); +INLINE uint OPER_AY_PD_32(void); +INLINE uint OPER_AY_DI_8(void); +INLINE uint OPER_AY_DI_16(void); +INLINE uint OPER_AY_DI_32(void); +INLINE uint OPER_AY_IX_8(void); +INLINE uint OPER_AY_IX_16(void); +INLINE uint OPER_AY_IX_32(void); + +INLINE uint OPER_AX_AI_8(void); +INLINE uint OPER_AX_AI_16(void); +INLINE uint OPER_AX_AI_32(void); +INLINE uint OPER_AX_PI_8(void); +INLINE uint OPER_AX_PI_16(void); +INLINE uint OPER_AX_PI_32(void); +INLINE uint OPER_AX_PD_8(void); +INLINE uint OPER_AX_PD_16(void); +INLINE uint OPER_AX_PD_32(void); +INLINE uint OPER_AX_DI_8(void); +INLINE uint OPER_AX_DI_16(void); +INLINE uint OPER_AX_DI_32(void); +INLINE uint OPER_AX_IX_8(void); +INLINE uint OPER_AX_IX_16(void); +INLINE uint OPER_AX_IX_32(void); + +INLINE uint OPER_A7_PI_8(void); +INLINE uint OPER_A7_PD_8(void); + +INLINE uint OPER_AW_8(void); +INLINE uint OPER_AW_16(void); +INLINE uint OPER_AW_32(void); +INLINE uint OPER_AL_8(void); +INLINE uint OPER_AL_16(void); +INLINE uint OPER_AL_32(void); +INLINE uint OPER_PCDI_8(void); +INLINE uint OPER_PCDI_16(void); +INLINE uint OPER_PCDI_32(void); +INLINE uint OPER_PCIX_8(void); +INLINE uint OPER_PCIX_16(void); +INLINE uint OPER_PCIX_32(void); + +/* Stack operations */ +INLINE void m68ki_push_16(uint value); +INLINE void m68ki_push_32(uint value); +INLINE uint m68ki_pull_16(void); +INLINE uint m68ki_pull_32(void); + +/* Program flow operations */ +INLINE void m68ki_jump(uint new_pc); +INLINE void m68ki_jump_vector(uint vector); +INLINE void m68ki_branch_8(uint offset); +INLINE void m68ki_branch_16(uint offset); +INLINE void m68ki_branch_32(uint offset); + +/* Status register operations. */ +INLINE void m68ki_set_s_flag(uint value); /* Only bit 2 of value should be set (i.e. 4 or 0) */ +INLINE void m68ki_set_sm_flag(uint value); /* only bits 1 and 2 of value should be set */ +INLINE void m68ki_set_ccr(uint value); /* set the condition code register */ +INLINE void m68ki_set_sr(uint value); /* set the status register */ +INLINE void m68ki_set_sr_noint(uint value); /* set the status register */ + +/* Exception processing */ +INLINE uint m68ki_init_exception(void); /* Initial exception processing */ + +INLINE void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */ +INLINE void m68ki_stack_frame_buserr(uint pc, uint sr, uint address, uint write, uint instruction, uint fc); + +INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector); +INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector); +INLINE void m68ki_stack_frame_0010(uint sr, uint vector); +INLINE void m68ki_stack_frame_1000(uint pc, uint sr, uint vector); +INLINE void m68ki_stack_frame_1010(uint sr, uint vector, uint pc); +INLINE void m68ki_stack_frame_1011(uint sr, uint vector, uint pc); + +INLINE void m68ki_exception_trap(uint vector); +INLINE void m68ki_exception_trapN(uint vector); +INLINE void m68ki_exception_trace(void); +INLINE void m68ki_exception_privilege_violation(void); +INLINE void m68ki_exception_1010(void); +INLINE void m68ki_exception_1111(void); +INLINE void m68ki_exception_illegal(void); +INLINE void m68ki_exception_format_error(void); +INLINE void m68ki_exception_address_error(void); +INLINE void m68ki_exception_interrupt(uint int_level); +INLINE void m68ki_check_interrupts(void); /* ASG: check for interrupts */ + +/* quick disassembly (used for logging) */ +char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type); + + +/* ======================================================================== */ +/* =========================== UTILITY FUNCTIONS ========================== */ +/* ======================================================================== */ + + +/* ---------------------------- Read Immediate ---------------------------- */ + +/* Handles all immediate reads, does address error check, function code setting, + * and prefetching if they are enabled in m68kconf.h + */ +INLINE uint m68ki_read_imm_16(void) +{ + m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(REG_PC); /* auto-disable (see m68kcpu.h) */ +#if M68K_EMULATE_PREFETCH + if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR) + { + CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC); + CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR)); + } + REG_PC += 2; + return MASK_OUT_ABOVE_16(CPU_PREF_DATA >> ((2-((REG_PC-2)&2))<<3)); +#else + REG_PC += 2; + return m68k_read_immediate_16(ADDRESS_68K(REG_PC-2)); +#endif /* M68K_EMULATE_PREFETCH */ +} +INLINE uint m68ki_read_imm_32(void) +{ +#if M68K_EMULATE_PREFETCH + uint temp_val; + + m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(REG_PC); /* auto-disable (see m68kcpu.h) */ + if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR) + { + CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC); + CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR)); + } + temp_val = CPU_PREF_DATA; + REG_PC += 2; + if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR) + { + CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC); + CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR)); + temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | (CPU_PREF_DATA >> 16)); + } + REG_PC += 2; + + return temp_val; +#else + m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(REG_PC); /* auto-disable (see m68kcpu.h) */ + REG_PC += 4; + return m68k_read_immediate_32(ADDRESS_68K(REG_PC-4)); +#endif /* M68K_EMULATE_PREFETCH */ +} + + + +/* ------------------------- Top level read/write ------------------------- */ + +/* Handles all memory accesses (except for immediate reads if they are + * configured to use separate functions in m68kconf.h). + * All memory accesses must go through these top level functions. + * These functions will also check for address error and set the function + * code if they are enabled in m68kconf.h. + */ +INLINE uint m68ki_read_8_fc(uint address, uint fc) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + return m68k_read_memory_8(ADDRESS_68K(address)); +} +INLINE uint m68ki_read_16_fc(uint address, uint fc) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(address); /* auto-disable (see m68kcpu.h) */ + return m68k_read_memory_16(ADDRESS_68K(address)); +} +INLINE uint m68ki_read_32_fc(uint address, uint fc) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(address); /* auto-disable (see m68kcpu.h) */ + return m68k_read_memory_32(ADDRESS_68K(address)); +} + +INLINE void m68ki_write_8_fc(uint address, uint fc, uint value) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68k_write_memory_8(ADDRESS_68K(address), value); +} +INLINE void m68ki_write_16_fc(uint address, uint fc, uint value) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(address); /* auto-disable (see m68kcpu.h) */ + m68k_write_memory_16(ADDRESS_68K(address), value); +} +INLINE void m68ki_write_32_fc(uint address, uint fc, uint value) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(address); /* auto-disable (see m68kcpu.h) */ + m68k_write_memory_32(ADDRESS_68K(address), value); +} + + + +/* --------------------- Effective Address Calculation -------------------- */ + +/* The program counter relative addressing modes cause operands to be + * retrieved from program space, not data space. + */ +INLINE uint m68ki_get_ea_pcdi(void) +{ + uint old_pc = REG_PC; + m68ki_use_program_space(); /* auto-disable */ + return old_pc + MAKE_INT_16(m68ki_read_imm_16()); +} + + +INLINE uint m68ki_get_ea_pcix(void) +{ + m68ki_use_program_space(); /* auto-disable */ + return m68ki_get_ea_ix(REG_PC); +} + +/* Indexed addressing modes are encoded as follows: + * + * Base instruction format: + * F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 + * x x x x x x x x x x | 1 1 0 | BASE REGISTER (An) + * + * Base instruction format for destination EA in move instructions: + * F E D C | B A 9 | 8 7 6 | 5 4 3 2 1 0 + * x x x x | BASE REG | 1 1 0 | X X X X X X (An) + * + * Brief extension format: + * F | E D C | B | A 9 | 8 | 7 6 5 4 3 2 1 0 + * D/A | REGISTER | W/L | SCALE | 0 | DISPLACEMENT + * + * Full extension format: + * F E D C B A 9 8 7 6 5 4 3 2 1 0 + * D/A | REGISTER | W/L | SCALE | 1 | BS | IS | BD SIZE | 0 | I/IS + * BASE DISPLACEMENT (0, 16, 32 bit) (bd) + * OUTER DISPLACEMENT (0, 16, 32 bit) (od) + * + * D/A: 0 = Dn, 1 = An (Xn) + * W/L: 0 = W (sign extend), 1 = L (.SIZE) + * SCALE: 00=1, 01=2, 10=4, 11=8 (*SCALE) + * BS: 0=add base reg, 1=suppress base reg (An suppressed) + * IS: 0=add index, 1=suppress index (Xn suppressed) + * BD SIZE: 00=reserved, 01=NULL, 10=Word, 11=Long (size of bd) + * + * IS I/IS Operation + * 0 000 No Memory Indirect + * 0 001 indir prex with null outer + * 0 010 indir prex with word outer + * 0 011 indir prex with long outer + * 0 100 reserved + * 0 101 indir postx with null outer + * 0 110 indir postx with word outer + * 0 111 indir postx with long outer + * 1 000 no memory indirect + * 1 001 mem indir with null outer + * 1 010 mem indir with word outer + * 1 011 mem indir with long outer + * 1 100-111 reserved + */ +INLINE uint m68ki_get_ea_ix(uint An) +{ + /* An = base register */ + uint extension = m68ki_read_imm_16(); + uint Xn = 0; /* Index register */ + uint bd = 0; /* Base Displacement */ + uint od = 0; /* Outer Displacement */ + + if(CPU_TYPE_IS_010_LESS(CPU_TYPE)) + { + /* Calculate index */ + Xn = REG_DA[extension>>12]; /* Xn */ + if(!BIT_B(extension)) /* W/L */ + Xn = MAKE_INT_16(Xn); + + /* Add base register and displacement and return */ + return An + Xn + MAKE_INT_8(extension); + } + + /* Brief extension format */ + if(!BIT_8(extension)) + { + /* Calculate index */ + Xn = REG_DA[extension>>12]; /* Xn */ + if(!BIT_B(extension)) /* W/L */ + Xn = MAKE_INT_16(Xn); + /* Add scale if proper CPU type */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + Xn <<= (extension>>9) & 3; /* SCALE */ + + /* Add base register and displacement and return */ + return An + Xn + MAKE_INT_8(extension); + } + + /* Full extension format */ + + USE_CYCLES(m68ki_ea_idx_cycle_table[extension&0x3f]); + + /* Check if base register is present */ + if(BIT_7(extension)) /* BS */ + An = 0; /* An */ + + /* Check if index is present */ + if(!BIT_6(extension)) /* IS */ + { + Xn = REG_DA[extension>>12]; /* Xn */ + if(!BIT_B(extension)) /* W/L */ + Xn = MAKE_INT_16(Xn); + Xn <<= (extension>>9) & 3; /* SCALE */ + } + + /* Check if base displacement is present */ + if(BIT_5(extension)) /* BD SIZE */ + bd = BIT_4(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16()); + + /* If no indirect action, we are done */ + if(!(extension&7)) /* No Memory Indirect */ + return An + bd + Xn; + + /* Check if outer displacement is present */ + if(BIT_1(extension)) /* I/IS: od */ + od = BIT_0(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16()); + + /* Postindex */ + if(BIT_2(extension)) /* I/IS: 0 = preindex, 1 = postindex */ + return m68ki_read_32(An + bd) + Xn + od; + + /* Preindex */ + return m68ki_read_32(An + bd + Xn) + od; +} + + +/* Fetch operands */ +INLINE uint OPER_AY_AI_8(void) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AY_PI_8(void) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AY_PD_8(void) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AY_DI_8(void) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AY_IX_8(void) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);} + +INLINE uint OPER_AX_AI_8(void) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AX_PI_8(void) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AX_PD_8(void) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AX_DI_8(void) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AX_IX_8(void) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);} + +INLINE uint OPER_A7_PI_8(void) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_A7_PD_8(void) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); } + +INLINE uint OPER_AW_8(void) {uint ea = EA_AW_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AW_16(void) {uint ea = EA_AW_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AW_32(void) {uint ea = EA_AW_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AL_8(void) {uint ea = EA_AL_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AL_16(void) {uint ea = EA_AL_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AL_32(void) {uint ea = EA_AL_32(); return m68ki_read_32(ea);} +INLINE uint OPER_PCDI_8(void) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); } +INLINE uint OPER_PCDI_16(void) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);} +INLINE uint OPER_PCDI_32(void) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);} +INLINE uint OPER_PCIX_8(void) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); } +INLINE uint OPER_PCIX_16(void) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);} +INLINE uint OPER_PCIX_32(void) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);} + + + +/* ---------------------------- Stack Functions --------------------------- */ + +/* Push/pull data from the stack */ +INLINE void m68ki_push_16(uint value) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); + m68ki_write_16(REG_SP, value); +} + +INLINE void m68ki_push_32(uint value) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); + m68ki_write_32(REG_SP, value); +} + +INLINE uint m68ki_pull_16(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); + return m68ki_read_16(REG_SP-2); +} + +INLINE uint m68ki_pull_32(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); + return m68ki_read_32(REG_SP-4); +} + + +/* Increment/decrement the stack as if doing a push/pull but + * don't do any memory access. + */ +INLINE void m68ki_fake_push_16(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); +} + +INLINE void m68ki_fake_push_32(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); +} + +INLINE void m68ki_fake_pull_16(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); +} + +INLINE void m68ki_fake_pull_32(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); +} + + +/* ----------------------------- Program Flow ----------------------------- */ + +/* Jump to a new program location or vector. + * These functions will also call the pc_changed callback if it was enabled + * in m68kconf.h. + */ +INLINE void m68ki_jump(uint new_pc) +{ + REG_PC = new_pc; + m68ki_pc_changed(REG_PC); +} + +INLINE void m68ki_jump_vector(uint vector) +{ + REG_PC = (vector<<2) + REG_VBR; + REG_PC = m68ki_read_data_32(REG_PC); + m68ki_pc_changed(REG_PC); +} + + +/* Branch to a new memory location. + * The 32-bit branch will call pc_changed if it was enabled in m68kconf.h. + * So far I've found no problems with not calling pc_changed for 8 or 16 + * bit branches. + */ +INLINE void m68ki_branch_8(uint offset) +{ + REG_PC += MAKE_INT_8(offset); +} + +INLINE void m68ki_branch_16(uint offset) +{ + REG_PC += MAKE_INT_16(offset); +} + +INLINE void m68ki_branch_32(uint offset) +{ + REG_PC += offset; + m68ki_pc_changed(REG_PC); +} + + + +/* ---------------------------- Status Register --------------------------- */ + +/* Set the S flag and change the active stack pointer. + * Note that value MUST be 4 or 0. + */ +INLINE void m68ki_set_s_flag(uint value) +{ + /* Backup the old stack pointer */ + REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP; + /* Set the S flag */ + FLAG_S = value; + /* Set the new stack pointer */ + REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)]; +} + +/* Set the S and M flags and change the active stack pointer. + * Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M). + */ +INLINE void m68ki_set_sm_flag(uint value) +{ + /* Backup the old stack pointer */ + REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP; + /* Set the S and M flags */ + FLAG_S = value & SFLAG_SET; + FLAG_M = value & MFLAG_SET; + /* Set the new stack pointer */ + REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)]; +} + + +/* Set the condition code register */ +INLINE void m68ki_set_ccr(uint value) +{ + FLAG_X = BIT_4(value) << 4; + FLAG_N = BIT_3(value) << 4; + FLAG_Z = !BIT_2(value); + FLAG_V = BIT_1(value) << 6; + FLAG_C = BIT_0(value) << 8; +} + +/* Set the status register but don't check for interrupts */ +INLINE void m68ki_set_sr_noint(uint value) +{ + /* Mask out the "unimplemented" bits */ + value &= CPU_SR_MASK; + + /* Now set the status register */ + FLAG_T1 = BIT_F(value); + FLAG_T0 = BIT_E(value); + FLAG_INT_MASK = value & 0x0700; + m68ki_set_ccr(value); + m68ki_set_sm_flag((value >> 11) & 6); +} + +/* Set the status register and check for interrupts */ +INLINE void m68ki_set_sr(uint value) +{ + m68ki_set_sr_noint(value); + m68ki_check_interrupts(); +} + + +/* ------------------------- Exception Processing ------------------------- */ + +/* Initiate exception processing */ +INLINE uint m68ki_init_exception(void) +{ + /* Save the old status register */ + uint sr = m68ki_get_sr(); + + /* Turn off trace flag, clear pending traces */ + FLAG_T1 = FLAG_T0 = 0; + m68ki_clear_trace(); + /* Enter supervisor mode */ + m68ki_set_s_flag(SFLAG_SET); + + return sr; +} + +/* 3 word stack frame (68000 only) */ +INLINE void m68ki_stack_frame_3word(uint pc, uint sr) +{ + m68ki_push_32(pc); + m68ki_push_16(sr); +} + +/* Format 0 stack frame. + * This is the standard stack frame for 68010+. + */ +INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector) +{ + /* Stack a 3-word frame if we are 68000 */ + if(CPU_TYPE == CPU_TYPE_000) + { + m68ki_stack_frame_3word(pc, sr); + return; + } + m68ki_push_16(vector<<2); + m68ki_push_32(pc); + m68ki_push_16(sr); +} + +/* Format 1 stack frame (68020). + * For 68020, this is the 4 word throwaway frame. + */ +INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector) +{ + m68ki_push_16(0x1000 | (vector<<2)); + m68ki_push_32(pc); + m68ki_push_16(sr); +} + +/* Format 2 stack frame. + * This is used only by 68020 for trap exceptions. + */ +INLINE void m68ki_stack_frame_0010(uint sr, uint vector) +{ + m68ki_push_32(REG_PPC); + m68ki_push_16(0x2000 | (vector<<2)); + m68ki_push_32(REG_PC); + m68ki_push_16(sr); +} + + +/* Bus error stack frame (68000 only). + */ +INLINE void m68ki_stack_frame_buserr(uint pc, uint sr, uint address, uint write, uint instruction, uint fc) +{ + m68ki_push_32(pc); + m68ki_push_16(sr); + m68ki_push_16(REG_IR); + m68ki_push_32(address); /* access address */ + /* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC + * R/W 0 = write, 1 = read + * I/N 0 = instruction, 1 = not + * FC 3-bit function code + */ + m68ki_push_16(((!write)<<4) | ((!instruction)<<3) | fc); +} + +/* Format 8 stack frame (68010). + * 68010 only. This is the 29 word bus/address error frame. + */ +void m68ki_stack_frame_1000(uint pc, uint sr, uint vector) +{ + /* VERSION + * NUMBER + * INTERNAL INFORMATION, 16 WORDS + */ + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + + /* INSTRUCTION INPUT BUFFER */ + m68ki_push_16(0); + + /* UNUSED, RESERVED (not written) */ + m68ki_fake_push_16(); + + /* DATA INPUT BUFFER */ + m68ki_push_16(0); + + /* UNUSED, RESERVED (not written) */ + m68ki_fake_push_16(); + + /* DATA OUTPUT BUFFER */ + m68ki_push_16(0); + + /* UNUSED, RESERVED (not written) */ + m68ki_fake_push_16(); + + /* FAULT ADDRESS */ + m68ki_push_32(0); + + /* SPECIAL STATUS WORD */ + m68ki_push_16(0); + + /* 1000, VECTOR OFFSET */ + m68ki_push_16(0x8000 | (vector<<2)); + + /* PROGRAM COUNTER */ + m68ki_push_32(pc); + + /* STATUS REGISTER */ + m68ki_push_16(sr); +} + +/* Format A stack frame (short bus fault). + * This is used only by 68020 for bus fault and address error + * if the error happens at an instruction boundary. + * PC stacked is address of next instruction. + */ +void m68ki_stack_frame_1010(uint sr, uint vector, uint pc) +{ + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* DATA OUTPUT BUFFER (2 words) */ + m68ki_push_32(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* DATA CYCLE FAULT ADDRESS (2 words) */ + m68ki_push_32(0); + + /* INSTRUCTION PIPE STAGE B */ + m68ki_push_16(0); + + /* INSTRUCTION PIPE STAGE C */ + m68ki_push_16(0); + + /* SPECIAL STATUS REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* 1010, VECTOR OFFSET */ + m68ki_push_16(0xa000 | (vector<<2)); + + /* PROGRAM COUNTER */ + m68ki_push_32(pc); + + /* STATUS REGISTER */ + m68ki_push_16(sr); +} + +/* Format B stack frame (long bus fault). + * This is used only by 68020 for bus fault and address error + * if the error happens during instruction execution. + * PC stacked is address of instruction in progress. + */ +void m68ki_stack_frame_1011(uint sr, uint vector, uint pc) +{ + /* INTERNAL REGISTERS (18 words) */ + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + + /* VERSION# (4 bits), INTERNAL INFORMATION */ + m68ki_push_16(0); + + /* INTERNAL REGISTERS (3 words) */ + m68ki_push_32(0); + m68ki_push_16(0); + + /* DATA INTPUT BUFFER (2 words) */ + m68ki_push_32(0); + + /* INTERNAL REGISTERS (2 words) */ + m68ki_push_32(0); + + /* STAGE B ADDRESS (2 words) */ + m68ki_push_32(0); + + /* INTERNAL REGISTER (4 words) */ + m68ki_push_32(0); + m68ki_push_32(0); + + /* DATA OUTPUT BUFFER (2 words) */ + m68ki_push_32(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* DATA CYCLE FAULT ADDRESS (2 words) */ + m68ki_push_32(0); + + /* INSTRUCTION PIPE STAGE B */ + m68ki_push_16(0); + + /* INSTRUCTION PIPE STAGE C */ + m68ki_push_16(0); + + /* SPECIAL STATUS REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* 1011, VECTOR OFFSET */ + m68ki_push_16(0xb000 | (vector<<2)); + + /* PROGRAM COUNTER */ + m68ki_push_32(pc); + + /* STATUS REGISTER */ + m68ki_push_16(sr); +} + + +/* Used for Group 2 exceptions. + * These stack a type 2 frame on the 020. + */ +INLINE void m68ki_exception_trap(uint vector) +{ + uint sr = m68ki_init_exception(); + + if(CPU_TYPE_IS_010_LESS(CPU_TYPE)) + m68ki_stack_frame_0000(REG_PC, sr, vector); + else + m68ki_stack_frame_0010(sr, vector); + + m68ki_jump_vector(vector); + + /* Use up some clock cycles */ + USE_CYCLES(CYC_EXCEPTION[vector]); +} + +/* Trap#n stacks a 0 frame but behaves like group2 otherwise */ +INLINE void m68ki_exception_trapN(uint vector) +{ + uint sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PC, sr, vector); + m68ki_jump_vector(vector); + + /* Use up some clock cycles */ + USE_CYCLES(CYC_EXCEPTION[vector]); +} + +/* Exception for trace mode */ +INLINE void m68ki_exception_trace(void) +{ + uint sr = m68ki_init_exception(); + + if(CPU_TYPE_IS_010_LESS(CPU_TYPE)) + m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_TRACE); + else + m68ki_stack_frame_0010(sr, EXCEPTION_TRACE); + + m68ki_jump_vector(EXCEPTION_TRACE); + + /* Trace nullifies a STOP instruction */ + CPU_STOPPED &= ~STOP_LEVEL_STOP; + + /* Use up some clock cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_TRACE]); +} + +/* Exception for privilege violation */ +INLINE void m68ki_exception_privilege_violation(void) +{ + uint sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_PRIVILEGE_VIOLATION); + m68ki_jump_vector(EXCEPTION_PRIVILEGE_VIOLATION); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_PRIVILEGE_VIOLATION] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for A-Line instructions */ +INLINE void m68ki_exception_1010(void) +{ + uint sr; +#if M68K_LOG_1010_1111 == OPT_ON + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1010 instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, + m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); +#endif + + sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PC-2, sr, EXCEPTION_1010); + m68ki_jump_vector(EXCEPTION_1010); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1010] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for F-Line instructions */ +INLINE void m68ki_exception_1111(void) +{ + uint sr; + +#if M68K_LOG_1010_1111 == OPT_ON + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1111 instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, + m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); +#endif + + sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PC-2, sr, EXCEPTION_1111); + m68ki_jump_vector(EXCEPTION_1111); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1111] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for illegal instructions */ +INLINE void m68ki_exception_illegal(void) +{ + uint sr; + + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: illegal instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, + m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); + + sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_ILLEGAL_INSTRUCTION); + m68ki_jump_vector(EXCEPTION_ILLEGAL_INSTRUCTION); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for format errror in RTE */ +INLINE void m68ki_exception_format_error(void) +{ + uint sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_FORMAT_ERROR); + m68ki_jump_vector(EXCEPTION_FORMAT_ERROR); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_FORMAT_ERROR] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for address error */ +INLINE void m68ki_exception_address_error(void) +{ + /* Not emulated yet */ +} + + +/* Service an interrupt request and start exception processing */ +void m68ki_exception_interrupt(uint int_level) +{ + uint vector; + uint sr; + uint new_pc; + + /* Turn off the stopped state */ + CPU_STOPPED &= ~STOP_LEVEL_STOP; + + /* If we are halted, don't do anything */ + if(CPU_STOPPED) + return; + + /* Acknowledge the interrupt */ + vector = m68ki_int_ack(int_level); + + /* Get the interrupt vector */ + if(vector == M68K_INT_ACK_AUTOVECTOR) + /* Use the autovectors. This is the most commonly used implementation */ + vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level; + else if(vector == M68K_INT_ACK_SPURIOUS) + /* Called if no devices respond to the interrupt acknowledge */ + vector = EXCEPTION_SPURIOUS_INTERRUPT; + else if(vector > 255) + { + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector)); + return; + } + + /* Start exception processing */ + sr = m68ki_init_exception(); + + /* Set the interrupt mask to the level of the one being serviced */ + FLAG_INT_MASK = int_level<<8; + + /* Get the new PC */ + new_pc = m68ki_read_data_32((vector<<2) + REG_VBR); + + /* If vector is uninitialized, call the uninitialized interrupt vector */ + if(new_pc == 0) + new_pc = m68ki_read_data_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + REG_VBR); + + /* Generate a stack frame */ + m68ki_stack_frame_0000(REG_PC, sr, vector); + if(FLAG_M && CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Create throwaway frame */ + m68ki_set_sm_flag(FLAG_S); /* clear M */ + sr |= 0x2000; /* Same as SR in master stack frame except S is forced high */ + m68ki_stack_frame_0001(REG_PC, sr, vector); + } + + m68ki_jump(new_pc); + + /* Defer cycle counting until later */ + CPU_INT_CYCLES += CYC_EXCEPTION[vector]; + +//#if !M68K_EMULATE_INT_ACK + /* Automatically clear IRQ if we are not using an acknowledge scheme */ + CPU_INT_LEVEL = 0; +//#endif /* M68K_EMULATE_INT_ACK */ +} + + +/* ASG: Check for interrupts */ +INLINE void m68ki_check_interrupts(void) +{ + if(CPU_INT_LEVEL > FLAG_INT_MASK) + m68ki_exception_interrupt(CPU_INT_LEVEL>>8); +} + + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68KCPU__HEADER */ diff --git a/MCUME_teensy/teensygen/m68kopac.c b/MCUME_teensy/teensygen/m68kopac.c new file mode 100644 index 0000000..553497f --- /dev/null +++ b/MCUME_teensy/teensygen/m68kopac.c @@ -0,0 +1,11948 @@ +#include "m68kcpu.h" + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ + + +void m68k_op_1010(void) +{ + m68ki_exception_1010(); +} + + +void m68k_op_1111(void) +{ + m68ki_exception_1111(); +} + + +void m68k_op_abcd_8_rr(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_N = NFLAG_8(res); /* officially undefined */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_abcd_8_mm_ax7(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_N = NFLAG_8(res); /* officially undefined */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_abcd_8_mm_ay7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_N = NFLAG_8(res); /* officially undefined */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_abcd_8_mm_axy7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_N = NFLAG_8(res); /* officially undefined */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_abcd_8_mm(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_N = NFLAG_8(res); /* officially undefined */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_add_8_er_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pi7(void) +{ + uint* r_dst = &DX; + uint src = OPER_A7_PI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pd7(void) +{ + uint* r_dst = &DX; + uint src = OPER_A7_PD_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_a(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(AY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_32_er_d(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_a(void) +{ + uint* r_dst = &DX; + uint src = AY; + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_8_re_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_aw(void) +{ + uint ea = EA_AW_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_al(void) +{ + uint ea = EA_AL_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_aw(void) +{ + uint ea = EA_AW_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_al(void) +{ + uint ea = EA_AL_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_di(void) +{ + uint ea = EA_AY_DI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_aw(void) +{ + uint ea = EA_AW_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_al(void) +{ + uint ea = EA_AL_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_adda_16_d(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY)); +} + + +void m68k_op_adda_16_a(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY)); +} + + +void m68k_op_adda_16_ai(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_AI_16())); +} + + +void m68k_op_adda_16_pi(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_PI_16())); +} + + +void m68k_op_adda_16_pd(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_PD_16())); +} + + +void m68k_op_adda_16_di(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_DI_16())); +} + + +void m68k_op_adda_16_ix(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AY_IX_16())); +} + + +void m68k_op_adda_16_aw(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AW_16())); +} + + +void m68k_op_adda_16_al(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_AL_16())); +} + + +void m68k_op_adda_16_pcdi(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_PCDI_16())); +} + + +void m68k_op_adda_16_pcix(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_PCIX_16())); +} + + +void m68k_op_adda_16_i(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(OPER_I_16())); +} + + +void m68k_op_adda_32_d(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY); +} + + +void m68k_op_adda_32_a(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY); +} + + +void m68k_op_adda_32_ai(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_AI_32()); +} + + +void m68k_op_adda_32_pi(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_PI_32()); +} + + +void m68k_op_adda_32_pd(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_PD_32()); +} + + +void m68k_op_adda_32_di(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_DI_32()); +} + + +void m68k_op_adda_32_ix(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AY_IX_32()); +} + + +void m68k_op_adda_32_aw(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AW_32()); +} + + +void m68k_op_adda_32_al(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_AL_32()); +} + + +void m68k_op_adda_32_pcdi(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_PCDI_32()); +} + + +void m68k_op_adda_32_pcix(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_PCIX_32()); +} + + +void m68k_op_adda_32_i(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + OPER_I_32()); +} + + +void m68k_op_addi_8_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_addi_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_16_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_addi_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_32_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_addi_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_8_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_addq_8_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_pi7(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_pd7(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_16_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_addq_16_a(void) +{ + uint* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); +} + + +void m68k_op_addq_16_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_32_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_addq_32_a(void) +{ + uint* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); +} + + +void m68k_op_addq_32_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addx_8_rr(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_addx_16_rr(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +void m68k_op_addx_32_rr(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + *r_dst = res; +} + + +void m68k_op_addx_8_mm_ax7(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_addx_8_mm_ay7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_addx_8_mm_axy7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_addx_8_mm(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_addx_16_mm(void) +{ + uint src = OPER_AY_PD_16(); + uint ea = EA_AX_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_addx_32_mm(void) +{ + uint src = OPER_AY_PD_32(); + uint ea = EA_AX_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_8_er_d(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_ai(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_AI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pi(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pi7(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pd(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PD_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pd7(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PD_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_di(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_DI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_ix(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_IX_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_aw(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AW_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_al(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AL_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pcdi(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCDI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pcix(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCIX_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_i(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_I_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_d(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_ai(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_AI_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_pi(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PI_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_pd(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PD_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_di(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_DI_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_ix(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_IX_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_aw(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AW_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_al(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AL_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_pcdi(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCDI_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_pcix(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCIX_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_i(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_I_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_d(void) +{ + FLAG_Z = DX &= DY; + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_ai(void) +{ + FLAG_Z = DX &= OPER_AY_AI_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_pi(void) +{ + FLAG_Z = DX &= OPER_AY_PI_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_pd(void) +{ + FLAG_Z = DX &= OPER_AY_PD_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_di(void) +{ + FLAG_Z = DX &= OPER_AY_DI_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_ix(void) +{ + FLAG_Z = DX &= OPER_AY_IX_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_aw(void) +{ + FLAG_Z = DX &= OPER_AW_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_al(void) +{ + FLAG_Z = DX &= OPER_AL_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_pcdi(void) +{ + FLAG_Z = DX &= OPER_PCDI_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_pcix(void) +{ + FLAG_Z = DX &= OPER_PCIX_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_i(void) +{ + FLAG_Z = DX &= OPER_I_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_re_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_di(void) +{ + uint ea = EA_AY_DI_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_aw(void) +{ + uint ea = EA_AW_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_al(void) +{ + uint ea = EA_AL_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_di(void) +{ + uint ea = EA_AY_DI_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_aw(void) +{ + uint ea = EA_AW_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_al(void) +{ + uint ea = EA_AL_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_32_re_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_di(void) +{ + uint ea = EA_AY_DI_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_aw(void) +{ + uint ea = EA_AW_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_al(void) +{ + uint ea = EA_AL_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_8_d(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_andi_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_16_d(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_andi_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_32_d(void) +{ + FLAG_Z = DY &= (OPER_I_32()); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_andi_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_16_toc(void) +{ + m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16()); +} + + +void m68k_op_andi_16_tos(void) +{ + if(FLAG_S) + { + uint src = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68ki_get_sr() & src); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_asr_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = src >> shift; + + if(GET_MSB_8(src)) + res |= m68ki_shift_8_table[shift]; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_X = FLAG_C = src << (9-shift); +} + + +void m68k_op_asr_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = src >> shift; + + if(GET_MSB_16(src)) + res |= m68ki_shift_16_table[shift]; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_X = FLAG_C = src << (9-shift); +} + + +void m68k_op_asr_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = src >> shift; + + if(GET_MSB_32(src)) + res |= m68ki_shift_32_table[shift]; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_X = FLAG_C = src << (9-shift); +} + + +void m68k_op_asr_8_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = src >> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> (shift - 1))<<8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + if(GET_MSB_16(src)) + { + *r_dst |= 0xffff; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_asr_32_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = *r_dst; + uint res = src >> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> (shift - 1))<<8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + if(GET_MSB_32(src)) + { + *r_dst = 0xffffffff; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_asr_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asl_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = MASK_OUT_ABOVE_8(src << shift); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_X = FLAG_C = src << shift; + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + src &= m68ki_shift_8_table[shift + 1]; + FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7; +} + + +void m68k_op_asl_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = MASK_OUT_ABOVE_16(src << shift); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> (8-shift); + src &= m68ki_shift_16_table[shift + 1]; + FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; +} + + +void m68k_op_asl_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32(src << shift); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> (24-shift); + src &= m68ki_shift_32_table[shift + 1]; + FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; +} + + +void m68k_op_asl_8_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + { + USE_CYCLES(shift<> 8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + src &= m68ki_shift_16_table[shift + 1]; + FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; + return; + } + + *r_dst &= 0xffff0000; + FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = (!(src == 0))<<7; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_asl_32_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + { + USE_CYCLES(shift<> (32 - shift)) << 8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + src &= m68ki_shift_32_table[shift + 1]; + FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; + return; + } + + *r_dst = 0; + FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = (!(src == 0))<<7; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_asl_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_bhi_8(void) +{ + if(COND_HI()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bls_8(void) +{ + if(COND_LS()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bcc_8(void) +{ + if(COND_CC()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bcs_8(void) +{ + if(COND_CS()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bne_8(void) +{ + if(COND_NE()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_beq_8(void) +{ + if(COND_EQ()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bvc_8(void) +{ + if(COND_VC()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bvs_8(void) +{ + if(COND_VS()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bpl_8(void) +{ + if(COND_PL()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bmi_8(void) +{ + if(COND_MI()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bge_8(void) +{ + if(COND_GE()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_blt_8(void) +{ + if(COND_LT()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bgt_8(void) +{ + if(COND_GT()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_ble_8(void) +{ + if(COND_LE()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bhi_16(void) +{ + if(COND_HI()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bls_16(void) +{ + if(COND_LS()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bcc_16(void) +{ + if(COND_CC()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bcs_16(void) +{ + if(COND_CS()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bne_16(void) +{ + if(COND_NE()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_beq_16(void) +{ + if(COND_EQ()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bvc_16(void) +{ + if(COND_VC()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bvs_16(void) +{ + if(COND_VS()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bpl_16(void) +{ + if(COND_PL()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bmi_16(void) +{ + if(COND_MI()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bge_16(void) +{ + if(COND_GE()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_blt_16(void) +{ + if(COND_LT()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bgt_16(void) +{ + if(COND_GT()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_ble_16(void) +{ + if(COND_LE()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bhi_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_HI()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bls_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LS()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CC()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bcs_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CS()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bne_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_NE()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_beq_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_EQ()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bvc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VC()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bvs_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VS()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bpl_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_PL()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bmi_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_MI()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bge_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GE()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_blt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LT()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bgt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GT()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_ble_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LE()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bchg_32_r_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (DX & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst ^= mask; +} + + +void m68k_op_bchg_8_r_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_32_s_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (OPER_I_8() & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst ^= mask; +} + + +void m68k_op_bchg_8_s_ai(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_pi(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_pi7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_pd(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_pd7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_di(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_ix(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_aw(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_al(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bclr_32_r_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (DX & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst &= ~mask; +} + + +void m68k_op_bclr_8_r_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_32_s_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (OPER_I_8() & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst &= ~mask; +} + + +void m68k_op_bclr_8_s_ai(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_pi(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_pi7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_pd(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_pd7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_di(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_ix(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_aw(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_al(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bfchg_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + FLAG_N = NFLAG_32(*data<>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfchg_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfchg_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfchg_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfchg_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + FLAG_N = NFLAG_32(*data<>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint64 data = DY; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2>>12)&7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_PCDI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_PCIX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint64 data = DY; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + FLAG_N = NFLAG_32(data); + data >>= 32 - width; + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2>>12)&7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_PCDI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_PCIX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint64 data = DY; + uint bit; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + FLAG_N = NFLAG_32(data); + data >>= 32 - width; + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_PCDI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_PCIX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + uint64 insert = REG_D[(word2>>12)&7]; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + insert = MASK_OUT_ABOVE_32(insert << (32 - width)); + FLAG_N = NFLAG_32(insert); + FLAG_Z = insert; + insert = ROR_32(insert, offset); + + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + *data &= ~mask; + *data |= insert; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + FLAG_N = NFLAG_32(*data<>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + FLAG_N = NFLAG_32(*data<>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_PCDI_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_PCIX_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bkpt(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */ + } + m68ki_exception_illegal(); +} + + +void m68k_op_bra_8(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_bra_16(void) +{ + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_bra_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bset_32_r_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (DX & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst |= mask; +} + + +void m68k_op_bset_8_r_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_32_s_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (OPER_I_8() & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst |= mask; +} + + +void m68k_op_bset_8_s_ai(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_pi(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_pi7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_pd(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_pd7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_di(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_ix(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_aw(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_al(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bsr_8(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); +} + + +void m68k_op_bsr_16(void) +{ + uint offset = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + REG_PC -= 2; + m68ki_branch_16(offset); +} + + +void m68k_op_bsr_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint offset = OPER_I_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + REG_PC -= 4; + m68ki_branch_32(offset); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_btst_32_r_d(void) +{ + FLAG_Z = DY & (1 << (DX & 0x1f)); +} + + +void m68k_op_btst_8_r_ai(void) +{ + FLAG_Z = OPER_AY_AI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pi(void) +{ + FLAG_Z = OPER_AY_PI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pi7(void) +{ + FLAG_Z = OPER_A7_PI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pd(void) +{ + FLAG_Z = OPER_AY_PD_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pd7(void) +{ + FLAG_Z = OPER_A7_PD_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_di(void) +{ + FLAG_Z = OPER_AY_DI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_ix(void) +{ + FLAG_Z = OPER_AY_IX_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_aw(void) +{ + FLAG_Z = OPER_AW_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_al(void) +{ + FLAG_Z = OPER_AL_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pcdi(void) +{ + FLAG_Z = OPER_PCDI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pcix(void) +{ + FLAG_Z = OPER_PCIX_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_i(void) +{ + FLAG_Z = OPER_I_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_32_s_d(void) +{ + FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f)); +} + + +void m68k_op_btst_8_s_ai(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_AI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pi(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_PI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pi7(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_A7_PI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pd(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_PD_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pd7(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_A7_PD_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_di(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_DI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_ix(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_IX_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_aw(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AW_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_al(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AL_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pcdi(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_PCDI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pcix(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_PCIX_8() & (1 << bit); +} + + +void m68k_op_callm_32_ai(void) +{ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AY_AI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_di(void) +{ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AY_DI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_ix(void) +{ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AY_IX_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_aw(void) +{ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AW_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_al(void) +{ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AL_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_pcdi(void) +{ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_PCDI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_pcix(void) +{ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_PCIX_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_pi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_pi7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_A7_PI_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_pd(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_pd7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_A7_PD_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_pi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_pd(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_pi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_pd(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas2_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_32(); + uint* compare1 = ®_D[(word2 >> 16) & 7]; + uint ea1 = REG_DA[(word2 >> 28) & 15]; + uint dest1 = m68ki_read_16(ea1); + uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1); + uint* compare2 = ®_D[word2 & 7]; + uint ea2 = REG_DA[(word2 >> 12) & 15]; + uint dest2 = m68ki_read_16(ea2); + uint res2; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res1); + FLAG_Z = MASK_OUT_ABOVE_16(res1); + FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1); + FLAG_C = CFLAG_16(res1); + + if(COND_EQ()) + { + res2 = dest2 - MASK_OUT_ABOVE_16(*compare2); + + FLAG_N = NFLAG_16(res2); + FLAG_Z = MASK_OUT_ABOVE_16(res2); + FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2); + FLAG_C = CFLAG_16(res2); + + if(COND_EQ()) + { + USE_CYCLES(3); + m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]); + m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]); + return; + } + } + *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1; + *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas2_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_32(); + uint* compare1 = ®_D[(word2 >> 16) & 7]; + uint ea1 = REG_DA[(word2 >> 28) & 15]; + uint dest1 = m68ki_read_32(ea1); + uint res1 = dest1 - *compare1; + uint* compare2 = ®_D[word2 & 7]; + uint ea2 = REG_DA[(word2 >> 12) & 15]; + uint dest2 = m68ki_read_32(ea2); + uint res2; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res1); + FLAG_Z = MASK_OUT_ABOVE_32(res1); + FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1); + FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1); + + if(COND_EQ()) + { + res2 = dest2 - *compare2; + + FLAG_N = NFLAG_32(res2); + FLAG_Z = MASK_OUT_ABOVE_32(res2); + FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2); + FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2); + + if(COND_EQ()) + { + USE_CYCLES(3); + m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]); + m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]); + return; + } + } + *compare1 = dest1; + *compare2 = dest2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_16_d(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(DY); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_ai(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_AI_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_pi(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_PI_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_pd(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_PD_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_di(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_DI_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_ix(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_IX_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_aw(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AW_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_al(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AL_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_pcdi(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_PCDI_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_pcix(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_PCIX_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_i(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_I_16()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(DY); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_AI_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_pi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_PI_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_pd(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_PD_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_DI_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_IX_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AW_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AL_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_PCDI_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_PCIX_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_i(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_I_32()); + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_AI_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_8(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_DI_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_8(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_IX_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_8(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AW_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_8(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AL_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_8(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_PCDI_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_8(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_PCIX_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_8(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_AI_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_16(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_DI_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_16(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_IX_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_16(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AW_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_16(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AL_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_16(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_PCDI_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_16(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_PCIX_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 1); + + if(!BIT_F(word2)) + compare = MAKE_INT_16(compare); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_AI_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 1); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_DI_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 1); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_IX_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 1); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AW_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 1); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AL_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 1); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_PCDI_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 1); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_PCIX_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 1); + + FLAG_C = compare - lower_bound; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C); + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_clr_8_d(void) +{ + DY &= 0xffffff00; + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_al(void) +{ + m68ki_write_8(EA_AL_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_d(void) +{ + DY &= 0xffff0000; + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_ai(void) +{ + m68ki_write_16(EA_AY_AI_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_pi(void) +{ + m68ki_write_16(EA_AY_PI_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_pd(void) +{ + m68ki_write_16(EA_AY_PD_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_di(void) +{ + m68ki_write_16(EA_AY_DI_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_ix(void) +{ + m68ki_write_16(EA_AY_IX_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_aw(void) +{ + m68ki_write_16(EA_AW_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_al(void) +{ + m68ki_write_16(EA_AL_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_d(void) +{ + DY = 0; + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_ai(void) +{ + m68ki_write_32(EA_AY_AI_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_pi(void) +{ + m68ki_write_32(EA_AY_PI_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_pd(void) +{ + m68ki_write_32(EA_AY_PD_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_di(void) +{ + m68ki_write_32(EA_AY_DI_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_ix(void) +{ + m68ki_write_32(EA_AY_IX_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_aw(void) +{ + m68ki_write_32(EA_AW_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_al(void) +{ + m68ki_write_32(EA_AL_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_cmp_8_d(void) +{ + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_ai(void) +{ + uint src = OPER_AY_AI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pi(void) +{ + uint src = OPER_AY_PI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pi7(void) +{ + uint src = OPER_A7_PI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pd(void) +{ + uint src = OPER_AY_PD_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pd7(void) +{ + uint src = OPER_A7_PD_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_di(void) +{ + uint src = OPER_AY_DI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_ix(void) +{ + uint src = OPER_AY_IX_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_aw(void) +{ + uint src = OPER_AW_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_al(void) +{ + uint src = OPER_AL_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pcdi(void) +{ + uint src = OPER_PCDI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pcix(void) +{ + uint src = OPER_PCIX_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_i(void) +{ + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_16_d(void) +{ + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_a(void) +{ + uint src = MASK_OUT_ABOVE_16(AY); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_ai(void) +{ + uint src = OPER_AY_AI_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_pi(void) +{ + uint src = OPER_AY_PI_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_pd(void) +{ + uint src = OPER_AY_PD_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_di(void) +{ + uint src = OPER_AY_DI_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_ix(void) +{ + uint src = OPER_AY_IX_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_aw(void) +{ + uint src = OPER_AW_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_al(void) +{ + uint src = OPER_AL_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_pcdi(void) +{ + uint src = OPER_PCDI_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_pcix(void) +{ + uint src = OPER_PCIX_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_i(void) +{ + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_32_d(void) +{ + uint src = DY; + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_a(void) +{ + uint src = AY; + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_ai(void) +{ + uint src = OPER_AY_AI_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_pi(void) +{ + uint src = OPER_AY_PI_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_pd(void) +{ + uint src = OPER_AY_PD_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_di(void) +{ + uint src = OPER_AY_DI_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_ix(void) +{ + uint src = OPER_AY_IX_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_aw(void) +{ + uint src = OPER_AW_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_al(void) +{ + uint src = OPER_AL_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_pcdi(void) +{ + uint src = OPER_PCDI_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_pcix(void) +{ + uint src = OPER_PCIX_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_i(void) +{ + uint src = OPER_I_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_d(void) +{ + uint src = MAKE_INT_16(DY); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_a(void) +{ + uint src = MAKE_INT_16(AY); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_ai(void) +{ + uint src = MAKE_INT_16(OPER_AY_AI_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_pi(void) +{ + uint src = MAKE_INT_16(OPER_AY_PI_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_pd(void) +{ + uint src = MAKE_INT_16(OPER_AY_PD_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_di(void) +{ + uint src = MAKE_INT_16(OPER_AY_DI_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_ix(void) +{ + uint src = MAKE_INT_16(OPER_AY_IX_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_aw(void) +{ + uint src = MAKE_INT_16(OPER_AW_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_al(void) +{ + uint src = MAKE_INT_16(OPER_AL_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_pcdi(void) +{ + uint src = MAKE_INT_16(OPER_PCDI_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_pcix(void) +{ + uint src = MAKE_INT_16(OPER_PCIX_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_i(void) +{ + uint src = MAKE_INT_16(OPER_I_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_d(void) +{ + uint src = DY; + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_a(void) +{ + uint src = AY; + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_ai(void) +{ + uint src = OPER_AY_AI_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_pi(void) +{ + uint src = OPER_AY_PI_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_pd(void) +{ + uint src = OPER_AY_PD_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_di(void) +{ + uint src = OPER_AY_DI_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_ix(void) +{ + uint src = OPER_AY_IX_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_aw(void) +{ + uint src = OPER_AW_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_al(void) +{ + uint src = OPER_AL_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_pcdi(void) +{ + uint src = OPER_PCDI_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_pcix(void) +{ + uint src = OPER_PCIX_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_i(void) +{ + uint src = OPER_I_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_8_d(void) +{ + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(DY); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_ai(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_AI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pi(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pi7(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_A7_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pd(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_PD_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pd7(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_A7_PD_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_di(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_DI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_ix(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_IX_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_aw(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AW_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_al(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AL_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_8(); + uint dst = OPER_PCDI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_8_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_8(); + uint dst = OPER_PCIX_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_16_d(void) +{ + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(DY); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_ai(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_AI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_pi(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_PI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_pd(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_PD_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_di(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_DI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_ix(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_IX_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_aw(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AW_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_al(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AL_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_16(); + uint dst = OPER_PCDI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_16_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_16(); + uint dst = OPER_PCIX_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_32_d(void) +{ + uint src = OPER_I_32(); + uint dst = DY; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_ai(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_AI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_pi(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_PI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_pd(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_PD_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_di(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_DI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_ix(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_IX_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_aw(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AW_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_al(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AL_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_32(); + uint dst = OPER_PCDI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_32(); + uint dst = OPER_PCIX_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpm_8_ax7(void) +{ + uint src = OPER_AY_PI_8(); + uint dst = OPER_A7_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpm_8_ay7(void) +{ + uint src = OPER_A7_PI_8(); + uint dst = OPER_AX_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpm_8_axy7(void) +{ + uint src = OPER_A7_PI_8(); + uint dst = OPER_A7_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpm_8(void) +{ + uint src = OPER_AY_PI_8(); + uint dst = OPER_AX_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpm_16(void) +{ + uint src = OPER_AY_PI_16(); + uint dst = OPER_AX_PI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpm_32(void) +{ + uint src = OPER_AY_PI_32(); + uint dst = OPER_AX_PI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cpbcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +void m68k_op_cpdbcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +void m68k_op_cpgen_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +void m68k_op_cpscc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +void m68k_op_cptrapcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + diff --git a/MCUME_teensy/teensygen/m68kopdm.c b/MCUME_teensy/teensygen/m68kopdm.c new file mode 100644 index 0000000..e60992a --- /dev/null +++ b/MCUME_teensy/teensygen/m68kopdm.c @@ -0,0 +1,13286 @@ +#include "m68kcpu.h" + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ + + +void m68k_op_dbt_16(void) +{ + REG_PC += 2; +} + + +void m68k_op_dbf_16(void) +{ + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbhi_16(void) +{ + if(COND_NOT_HI()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbls_16(void) +{ + if(COND_NOT_LS()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbcc_16(void) +{ + if(COND_NOT_CC()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbcs_16(void) +{ + if(COND_NOT_CS()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbne_16(void) +{ + if(COND_NOT_NE()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbeq_16(void) +{ + if(COND_NOT_EQ()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbvc_16(void) +{ + if(COND_NOT_VC()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbvs_16(void) +{ + if(COND_NOT_VS()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbpl_16(void) +{ + if(COND_NOT_PL()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbmi_16(void) +{ + if(COND_NOT_MI()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbge_16(void) +{ + if(COND_NOT_GE()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dblt_16(void) +{ + if(COND_NOT_LT()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbgt_16(void) +{ + if(COND_NOT_GT()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dble_16(void) +{ + if(COND_NOT_LE()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_divs_16_d(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(DY); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_ai(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_AI_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_pi(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_PI_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_pd(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_PD_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_di(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_DI_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_ix(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_IX_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_aw(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AW_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_al(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AL_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_pcdi(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_PCDI_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_pcix(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_PCIX_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_i(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_I_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divl_32_d(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = DY; + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = DY; + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_ai(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_AI_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_AI_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_pi(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_PI_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_PI_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_pd(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_PD_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_PD_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_di(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_DI_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_DI_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_ix(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_IX_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_IX_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_aw(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AW_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AW_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_al(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AL_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AL_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_pcdi(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_PCDI_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_PCDI_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_pcix(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_PCIX_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_PCIX_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_i(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_I_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_I_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_eor_8_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX)); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_aw(void) +{ + uint ea = EA_AW_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_al(void) +{ + uint ea = EA_AL_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX)); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_aw(void) +{ + uint ea = EA_AW_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_al(void) +{ + uint ea = EA_AL_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_d(void) +{ + uint res = DY ^= DX; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_di(void) +{ + uint ea = EA_AY_DI_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_aw(void) +{ + uint ea = EA_AW_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_al(void) +{ + uint ea = EA_AL_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8()); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16()); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_d(void) +{ + uint res = DY ^= OPER_I_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_toc(void) +{ + m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16()); +} + + +void m68k_op_eori_16_tos(void) +{ + if(FLAG_S) + { + uint src = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68ki_get_sr() ^ src); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_exg_32_dd(void) +{ + uint* reg_a = &DX; + uint* reg_b = &DY; + uint tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +void m68k_op_exg_32_aa(void) +{ + uint* reg_a = &AX; + uint* reg_b = &AY; + uint tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +void m68k_op_exg_32_da(void) +{ + uint* reg_a = &DX; + uint* reg_b = &AY; + uint tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +void m68k_op_ext_16(void) +{ + uint* r_dst = &DY; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0); + + FLAG_N = NFLAG_16(*r_dst); + FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_ext_32(void) +{ + uint* r_dst = &DY; + + *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0); + + FLAG_N = NFLAG_32(*r_dst); + FLAG_Z = *r_dst; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_extb_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint* r_dst = &DY; + + *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0); + + FLAG_N = NFLAG_32(*r_dst); + FLAG_Z = *r_dst; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_illegal(void) +{ + m68ki_exception_illegal(); +} + + +void m68k_op_jmp_32_ai(void) +{ + m68ki_jump(EA_AY_AI_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_di(void) +{ + m68ki_jump(EA_AY_DI_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_ix(void) +{ + m68ki_jump(EA_AY_IX_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_aw(void) +{ + m68ki_jump(EA_AW_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_al(void) +{ + m68ki_jump(EA_AL_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_pcdi(void) +{ + m68ki_jump(EA_PCDI_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_pcix(void) +{ + m68ki_jump(EA_PCIX_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jsr_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_di(void) +{ + uint ea = EA_AY_DI_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_aw(void) +{ + uint ea = EA_AW_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_al(void) +{ + uint ea = EA_AL_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_pcdi(void) +{ + uint ea = EA_PCDI_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_pcix(void) +{ + uint ea = EA_PCIX_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_lea_32_ai(void) +{ + AX = EA_AY_AI_32(); +} + + +void m68k_op_lea_32_di(void) +{ + AX = EA_AY_DI_32(); +} + + +void m68k_op_lea_32_ix(void) +{ + AX = EA_AY_IX_32(); +} + + +void m68k_op_lea_32_aw(void) +{ + AX = EA_AW_32(); +} + + +void m68k_op_lea_32_al(void) +{ + AX = EA_AL_32(); +} + + +void m68k_op_lea_32_pcdi(void) +{ + AX = EA_PCDI_32(); +} + + +void m68k_op_lea_32_pcix(void) +{ + AX = EA_PCIX_32(); +} + + +void m68k_op_link_16_a7(void) +{ + REG_A[7] -= 4; + m68ki_write_32(REG_A[7], REG_A[7]); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); +} + + +void m68k_op_link_16(void) +{ + uint* r_dst = &AY; + + m68ki_push_32(*r_dst); + *r_dst = REG_A[7]; + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); +} + + +void m68k_op_link_32_a7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_A[7] -= 4; + m68ki_write_32(REG_A[7], REG_A[7]); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_link_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint* r_dst = &AY; + + m68ki_push_32(*r_dst); + *r_dst = REG_A[7]; + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_lsr_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = src >> shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_X = FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = src >> shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_X = FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = src >> shift; + + *r_dst = res; + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_X = FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_8_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = src >> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> (shift - 1))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + FLAG_X = XFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_32_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = *r_dst; + uint res = src >> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> (shift - 1))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0); + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = MASK_OUT_ABOVE_8(src << shift); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src << shift; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = MASK_OUT_ABOVE_16(src << shift); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> (8-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32(src << shift); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> (24-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_8_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + { + USE_CYCLES(shift<> 8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + FLAG_X = XFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_32_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + { + USE_CYCLES(shift<> (32 - shift)) << 8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_move_8_d_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_di(void) +{ + uint res = OPER_AY_DI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_aw(void) +{ + uint res = OPER_AW_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_al(void) +{ + uint res = OPER_AL_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_i(void) +{ + uint res = OPER_I_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_di(void) +{ + uint res = OPER_AY_DI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_aw(void) +{ + uint res = OPER_AW_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_al(void) +{ + uint res = OPER_AL_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_i(void) +{ + uint res = OPER_I_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_d(void) +{ + uint res = DY; + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_a(void) +{ + uint res = AY; + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_di(void) +{ + uint res = OPER_AY_DI_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_aw(void) +{ + uint res = OPER_AW_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_al(void) +{ + uint res = OPER_AL_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_i(void) +{ + uint res = OPER_I_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_d(void) +{ + uint res = DY; + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_a(void) +{ + uint res = AY; + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_d(void) +{ + uint res = DY; + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_a(void) +{ + uint res = AY; + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_d(void) +{ + uint res = DY; + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_a(void) +{ + uint res = AY; + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_PD_32(); + +#if GENESIS_HACKS + m68ki_write_16(ea+2, res & 0xFFFF ); + m68ki_write_16(ea, (res >> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, res); +#endif + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_d(void) +{ + uint res = DY; + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_a(void) +{ + uint res = AY; + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_d(void) +{ + uint res = DY; + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_a(void) +{ + uint res = AY; + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_d(void) +{ + uint res = DY; + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_a(void) +{ + uint res = AY; + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_d(void) +{ + uint res = DY; + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_a(void) +{ + uint res = AY; + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_movea_16_d(void) +{ + AX = MAKE_INT_16(DY); +} + + +void m68k_op_movea_16_a(void) +{ + AX = MAKE_INT_16(AY); +} + + +void m68k_op_movea_16_ai(void) +{ + AX = MAKE_INT_16(OPER_AY_AI_16()); +} + + +void m68k_op_movea_16_pi(void) +{ + AX = MAKE_INT_16(OPER_AY_PI_16()); +} + + +void m68k_op_movea_16_pd(void) +{ + AX = MAKE_INT_16(OPER_AY_PD_16()); +} + + +void m68k_op_movea_16_di(void) +{ + AX = MAKE_INT_16(OPER_AY_DI_16()); +} + + +void m68k_op_movea_16_ix(void) +{ + AX = MAKE_INT_16(OPER_AY_IX_16()); +} + + +void m68k_op_movea_16_aw(void) +{ + AX = MAKE_INT_16(OPER_AW_16()); +} + + +void m68k_op_movea_16_al(void) +{ + AX = MAKE_INT_16(OPER_AL_16()); +} + + +void m68k_op_movea_16_pcdi(void) +{ + AX = MAKE_INT_16(OPER_PCDI_16()); +} + + +void m68k_op_movea_16_pcix(void) +{ + AX = MAKE_INT_16(OPER_PCIX_16()); +} + + +void m68k_op_movea_16_i(void) +{ + AX = MAKE_INT_16(OPER_I_16()); +} + + +void m68k_op_movea_32_d(void) +{ + AX = DY; +} + + +void m68k_op_movea_32_a(void) +{ + AX = AY; +} + + +void m68k_op_movea_32_ai(void) +{ + AX = OPER_AY_AI_32(); +} + + +void m68k_op_movea_32_pi(void) +{ + AX = OPER_AY_PI_32(); +} + + +void m68k_op_movea_32_pd(void) +{ + AX = OPER_AY_PD_32(); +} + + +void m68k_op_movea_32_di(void) +{ + AX = OPER_AY_DI_32(); +} + + +void m68k_op_movea_32_ix(void) +{ + AX = OPER_AY_IX_32(); +} + + +void m68k_op_movea_32_aw(void) +{ + AX = OPER_AW_32(); +} + + +void m68k_op_movea_32_al(void) +{ + AX = OPER_AL_32(); +} + + +void m68k_op_movea_32_pcdi(void) +{ + AX = OPER_PCDI_32(); +} + + +void m68k_op_movea_32_pcix(void) +{ + AX = OPER_PCIX_32(); +} + + +void m68k_op_movea_32_i(void) +{ + AX = OPER_I_32(); +} + + +void m68k_op_move_16_frc_d(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_ai(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_AI_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_pi(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_PI_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_pd(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_PD_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_di(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_DI_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_ix(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_IX_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_aw(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AW_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_al(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AL_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_toc_d(void) +{ + m68ki_set_ccr(DY); +} + + +void m68k_op_move_16_toc_ai(void) +{ + m68ki_set_ccr(OPER_AY_AI_16()); +} + + +void m68k_op_move_16_toc_pi(void) +{ + m68ki_set_ccr(OPER_AY_PI_16()); +} + + +void m68k_op_move_16_toc_pd(void) +{ + m68ki_set_ccr(OPER_AY_PD_16()); +} + + +void m68k_op_move_16_toc_di(void) +{ + m68ki_set_ccr(OPER_AY_DI_16()); +} + + +void m68k_op_move_16_toc_ix(void) +{ + m68ki_set_ccr(OPER_AY_IX_16()); +} + + +void m68k_op_move_16_toc_aw(void) +{ + m68ki_set_ccr(OPER_AW_16()); +} + + +void m68k_op_move_16_toc_al(void) +{ + m68ki_set_ccr(OPER_AL_16()); +} + + +void m68k_op_move_16_toc_pcdi(void) +{ + m68ki_set_ccr(OPER_PCDI_16()); +} + + +void m68k_op_move_16_toc_pcix(void) +{ + m68ki_set_ccr(OPER_PCIX_16()); +} + + +void m68k_op_move_16_toc_i(void) +{ + m68ki_set_ccr(OPER_I_16()); +} + + +void m68k_op_move_16_frs_d(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr(); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_ai(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_AI_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_pi(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_PI_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_pd(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_PD_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_di(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_DI_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_ix(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_IX_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_aw(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AW_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_al(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AL_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_d(void) +{ + if(FLAG_S) + { + m68ki_set_sr(DY); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_ai(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_AI_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_pi(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_PI_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_pd(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_PD_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_di(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_DI_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_ix(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_IX_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_aw(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AW_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_al(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AL_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_pcdi(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_PCDI_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_pcix(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_PCIX_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_i(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_32_fru(void) +{ + if(FLAG_S) + { + AY = REG_USP; + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_32_tou(void) +{ + if(FLAG_S) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_USP = AY; + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_movec_32_cr(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + switch (word2 & 0xfff) + { + case 0x000: /* SFC */ + REG_DA[(word2 >> 12) & 15] = REG_SFC; + return; + case 0x001: /* DFC */ + REG_DA[(word2 >> 12) & 15] = REG_DFC; + return; + case 0x002: /* CACR */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_DA[(word2 >> 12) & 15] = REG_CACR; + return; + } + return; + case 0x800: /* USP */ + REG_DA[(word2 >> 12) & 15] = REG_USP; + return; + case 0x801: /* VBR */ + REG_DA[(word2 >> 12) & 15] = REG_VBR; + return; + case 0x802: /* CAAR */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_DA[(word2 >> 12) & 15] = REG_CAAR; + return; + } + m68ki_exception_illegal(); + break; + case 0x803: /* MSP */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP; + return; + } + m68ki_exception_illegal(); + return; + case 0x804: /* ISP */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP; + return; + } + m68ki_exception_illegal(); + return; + default: + m68ki_exception_illegal(); + return; + } + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_movec_32_rc(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + switch (word2 & 0xfff) + { + case 0x000: /* SFC */ + REG_SFC = REG_DA[(word2 >> 12) & 15] & 7; + return; + case 0x001: /* DFC */ + REG_DFC = REG_DA[(word2 >> 12) & 15] & 7; + return; + case 0x002: /* CACR */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_CACR = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(); + return; + case 0x800: /* USP */ + REG_USP = REG_DA[(word2 >> 12) & 15]; + return; + case 0x801: /* VBR */ + REG_VBR = REG_DA[(word2 >> 12) & 15]; + return; + case 0x802: /* CAAR */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_CAAR = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(); + return; + case 0x803: /* MSP */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* we are in supervisor mode so just check for M flag */ + if(!FLAG_M) + { + REG_MSP = REG_DA[(word2 >> 12) & 15]; + return; + } + REG_SP = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(); + return; + case 0x804: /* ISP */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(!FLAG_M) + { + REG_SP = REG_DA[(word2 >> 12) & 15]; + return; + } + REG_ISP = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(); + return; + default: + m68ki_exception_illegal(); + return; + } + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_movem_16_re_pd(void) +{ + uint i = 0; + uint register_list = OPER_I_16(); + uint ea = AY; + uint count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + ea -= 2; + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i])); + count++; + } + AY = ea; + + USE_CYCLES(count<> 16) & 0xFFFF ); +#else + m68ki_write_32(ea, REG_DA[15-i]); +#endif + count++; + } + AY = ea; + + USE_CYCLES(count<> 8)); + m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src)); +} + + +void m68k_op_movep_32_re(void) +{ + uint ea = EA_AY_DI_32(); + uint src = DX; + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24)); + m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16)); + m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8)); + m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src)); +} + + +void m68k_op_movep_16_er(void) +{ + uint ea = EA_AY_DI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2)); +} + + +void m68k_op_movep_32_er(void) +{ + uint ea = EA_AY_DI_32(); + + DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16) + + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6); +} + + +void m68k_op_moves_8_ai(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_pi(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_pi7(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_A7_PI_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_pd(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_pd7(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_A7_PD_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_di(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_ix(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_aw(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_al(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_ai(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_pi(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_pd(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_di(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_ix(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_aw(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_al(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_ai(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_pi(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_pd(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_di(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_ix(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_aw(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_al(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moveq_32(void) +{ + uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR)); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_d(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_ai(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_AI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_pi(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_pd(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PD_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_di(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_DI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_ix(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_IX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_aw(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AW_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_al(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AL_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_pcdi(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCDI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_pcix(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCIX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_i(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_I_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_d(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_ai(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_AI_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_pi(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_PI_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_pd(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_PD_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_di(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_DI_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_ix(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_IX_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_aw(void) +{ + uint* r_dst = &DX; + uint res = OPER_AW_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_al(void) +{ + uint* r_dst = &DX; + uint res = OPER_AL_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_pcdi(void) +{ + uint* r_dst = &DX; + uint res = OPER_PCDI_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_pcix(void) +{ + uint* r_dst = &DX; + uint res = OPER_PCIX_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_i(void) +{ + uint* r_dst = &DX; + uint res = OPER_I_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mull_32_d(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = DY; + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = DY; + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_ai(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_AI_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_AI_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_pi(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_PI_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_PI_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_pd(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_PD_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_PD_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_di(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_DI_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_DI_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_ix(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_IX_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_IX_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_aw(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AW_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AW_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_al(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AL_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AL_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_pcdi(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_PCDI_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_PCDI_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_pcix(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_PCIX_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_PCIX_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_i(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_I_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_I_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + diff --git a/MCUME_teensy/teensygen/m68kopnz.c b/MCUME_teensy/teensygen/m68kopnz.c new file mode 100644 index 0000000..b5be77d --- /dev/null +++ b/MCUME_teensy/teensygen/m68kopnz.c @@ -0,0 +1,8746 @@ +#include "m68kcpu.h" + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ + + +void m68k_op_nbcd_8_d(void) +{ + uint* r_dst = &DY; + uint dst = *r_dst; + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_nbcd_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_nbcd_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_nbcd_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_nbcd_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_nbcd_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_nbcd_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_nbcd_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_nbcd_8_aw(void) +{ + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_nbcd_8_al(void) +{ + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* officially undefined */ +} + + +void m68k_op_neg_8_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_8(*r_dst); + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = *r_dst & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_neg_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_16_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_16(*r_dst); + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (*r_dst & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_neg_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_32_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - *r_dst; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res); + FLAG_V = (*r_dst & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_neg_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_di(void) +{ + uint ea = EA_AY_DI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_aw(void) +{ + uint ea = EA_AW_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_al(void) +{ + uint ea = EA_AL_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_negx_8_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = *r_dst & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_negx_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_16_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (*r_dst & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +void m68k_op_negx_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_32_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res); + FLAG_V = (*r_dst & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + *r_dst = res; +} + + +void m68k_op_negx_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_di(void) +{ + uint ea = EA_AY_DI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_aw(void) +{ + uint ea = EA_AW_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_al(void) +{ + uint ea = EA_AL_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_nop(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ +} + + +void m68k_op_not_8_d(void) +{ + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_8(~*r_dst); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_aw(void) +{ + uint ea = EA_AW_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_al(void) +{ + uint ea = EA_AL_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_d(void) +{ + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(~*r_dst); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_aw(void) +{ + uint ea = EA_AW_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_al(void) +{ + uint ea = EA_AL_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_d(void) +{ + uint* r_dst = &DY; + uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_di(void) +{ + uint ea = EA_AY_DI_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_aw(void) +{ + uint ea = EA_AW_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_al(void) +{ + uint ea = EA_AL_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_d(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY))); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_ai(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_AI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pi(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pi7(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pd(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PD_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pd7(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PD_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_di(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_DI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_ix(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_IX_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_aw(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AW_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_al(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AL_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pcdi(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCDI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pcix(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCIX_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_i(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_I_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_d(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY))); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_ai(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_AI_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_pi(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PI_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_pd(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PD_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_di(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_DI_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_ix(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_IX_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_aw(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AW_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_al(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AL_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_pcdi(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCDI_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_pcix(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCIX_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_i(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_I_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_d(void) +{ + uint res = DX |= DY; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_ai(void) +{ + uint res = DX |= OPER_AY_AI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_pi(void) +{ + uint res = DX |= OPER_AY_PI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_pd(void) +{ + uint res = DX |= OPER_AY_PD_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_di(void) +{ + uint res = DX |= OPER_AY_DI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_ix(void) +{ + uint res = DX |= OPER_AY_IX_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_aw(void) +{ + uint res = DX |= OPER_AW_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_al(void) +{ + uint res = DX |= OPER_AL_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_pcdi(void) +{ + uint res = DX |= OPER_PCDI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_pcix(void) +{ + uint res = DX |= OPER_PCIX_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_i(void) +{ + uint res = DX |= OPER_I_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_di(void) +{ + uint ea = EA_AY_DI_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_aw(void) +{ + uint ea = EA_AW_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_al(void) +{ + uint ea = EA_AL_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_di(void) +{ + uint ea = EA_AY_DI_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_aw(void) +{ + uint ea = EA_AW_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_al(void) +{ + uint ea = EA_AL_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_di(void) +{ + uint ea = EA_AY_DI_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_aw(void) +{ + uint ea = EA_AW_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_al(void) +{ + uint ea = EA_AL_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_d(void) +{ + uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16()); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_d(void) +{ + uint res = DY |= OPER_I_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_toc(void) +{ + m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16()); +} + + +void m68k_op_ori_16_tos(void) +{ + if(FLAG_S) + { + uint src = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68ki_get_sr() | src); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_pack_16_rr(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: DX and DY are reversed in Motorola's docs */ + uint src = DY + OPER_I_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pack_16_mm_ax7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint ea_src = EA_AY_PD_8(); + uint src = m68ki_read_8(ea_src); + ea_src = EA_AY_PD_8(); + src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); + + m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pack_16_mm_ay7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint ea_src = EA_A7_PD_8(); + uint src = m68ki_read_8(ea_src); + ea_src = EA_A7_PD_8(); + src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); + + m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pack_16_mm_axy7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint ea_src = EA_A7_PD_8(); + uint src = m68ki_read_8(ea_src); + ea_src = EA_A7_PD_8(); + src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); + + m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pack_16_mm(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint ea_src = EA_AY_PD_8(); + uint src = m68ki_read_8(ea_src); + ea_src = EA_AY_PD_8(); + src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); + + m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pea_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_di(void) +{ + uint ea = EA_AY_DI_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_aw(void) +{ + uint ea = EA_AW_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_al(void) +{ + uint ea = EA_AL_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_pcdi(void) +{ + uint ea = EA_PCDI_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_pcix(void) +{ + uint ea = EA_PCIX_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_reset(void) +{ + if(FLAG_S) + { + m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */ + USE_CYCLES(CYC_RESET); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_ror_8_s(void) +{ + uint* r_dst = &DY; + uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint shift = orig_shift & 7; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROR_8(src, shift); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = src << (9-orig_shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = ROR_16(src, shift); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint64 src = *r_dst; + uint res = ROR_32(src, shift); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_8_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift & 7; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROR_8(src, shift); + + if(orig_shift != 0) + { + USE_CYCLES(orig_shift<> ((shift - 1) & 15)) << 8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_32_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift & 31; + uint64 src = *r_dst; + uint res = ROR_32(src, shift); + + if(orig_shift != 0) + { + USE_CYCLES(orig_shift<> ((shift - 1) & 31)) << 8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_8_s(void) +{ + uint* r_dst = &DY; + uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint shift = orig_shift & 7; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROL_8(src, shift); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = src << orig_shift; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = ROL_16(src, shift); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> (8-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint64 src = *r_dst; + uint res = ROL_32(src, shift); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = src >> (24-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_8_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift & 7; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROL_8(src, shift); + + if(orig_shift != 0) + { + USE_CYCLES(orig_shift<> 8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + FLAG_C = (src & 1)<<8; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_32_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift & 31; + uint64 src = *r_dst; + uint res = ROL_32(src, shift); + + if(orig_shift != 0) + { + USE_CYCLES(orig_shift<> (32 - shift)) << 8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift); + + FLAG_C = FLAG_X = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_32_s(void) +{ +#if M68K_USE_64_BIT + + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint64 src = *r_dst; + uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); + + res = ROR_33_64(res, shift); + + FLAG_C = FLAG_X = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + +#else + + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift))); + uint new_x_flag = src & (1 << (shift - 1)); + + *r_dst = res; + + FLAG_C = FLAG_X = (new_x_flag != 0)<<8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + +#endif +} + + +void m68k_op_roxr_8_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + uint shift = orig_shift % 9; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift); + + USE_CYCLES(orig_shift<> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = FLAG_X; + FLAG_N = NFLAG_16(*r_dst); + FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_32_r(void) +{ +#if M68K_USE_64_BIT + + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + uint shift = orig_shift % 33; + uint64 src = *r_dst; + uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); + + res = ROR_33_64(res, shift); + + USE_CYCLES(orig_shift<> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = FLAG_X; + FLAG_N = NFLAG_32(*r_dst); + FLAG_Z = *r_dst; + FLAG_V = VFLAG_CLEAR; + +#else + + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift % 33; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift))); + uint new_x_flag = src & (1 << (shift - 1)); + + if(orig_shift != 0) + USE_CYCLES(orig_shift<> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift); + + FLAG_C = FLAG_X = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_32_s(void) +{ +#if M68K_USE_64_BIT + + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint64 src = *r_dst; + uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); + + res = ROL_33_64(res, shift); + + FLAG_C = FLAG_X = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + +#else + + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1))); + uint new_x_flag = src & (1 << (32 - shift)); + + *r_dst = res; + + FLAG_C = FLAG_X = (new_x_flag != 0)<<8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + +#endif +} + + +void m68k_op_roxl_8_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + + + if(orig_shift != 0) + { + uint shift = orig_shift % 9; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift); + + USE_CYCLES(orig_shift<> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = FLAG_X; + FLAG_N = NFLAG_16(*r_dst); + FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_32_r(void) +{ +#if M68K_USE_64_BIT + + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + uint shift = orig_shift % 33; + uint64 src = *r_dst; + uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); + + res = ROL_33_64(res, shift); + + USE_CYCLES(orig_shift<> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = FLAG_X; + FLAG_N = NFLAG_32(*r_dst); + FLAG_Z = *r_dst; + FLAG_V = VFLAG_CLEAR; + +#else + + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift % 33; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1))); + uint new_x_flag = src & (1 << (32 - shift)); + + if(orig_shift != 0) + USE_CYCLES(orig_shift<> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rtd_32(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + uint new_pc = m68ki_pull_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); + m68ki_jump(new_pc); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_rte_32(void) +{ + if(FLAG_S) + { + uint new_sr; + uint new_pc; + uint format_word; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + + if(CPU_TYPE_IS_000(CPU_TYPE)) + { + new_sr = m68ki_pull_16(); + new_pc = m68ki_pull_32(); + m68ki_jump(new_pc); + m68ki_set_sr(new_sr); + return; + } + + if(CPU_TYPE_IS_010(CPU_TYPE)) + { + format_word = m68ki_read_16(REG_A[7]+6) >> 12; + if(format_word == 0) + { + new_sr = m68ki_pull_16(); + new_pc = m68ki_pull_32(); + m68ki_fake_pull_16(); /* format word */ + m68ki_jump(new_pc); + m68ki_set_sr(new_sr); + return; + } + /* Not handling bus fault (9) */ + m68ki_exception_format_error(); + return; + } + + /* Otherwise it's 020 */ +rte_loop: + format_word = m68ki_read_16(REG_A[7]+6) >> 12; + switch(format_word) + { + case 0: /* Normal */ + new_sr = m68ki_pull_16(); + new_pc = m68ki_pull_32(); + m68ki_fake_pull_16(); /* format word */ + m68ki_jump(new_pc); + m68ki_set_sr(new_sr); + return; + case 1: /* Throwaway */ + new_sr = m68ki_pull_16(); + m68ki_fake_pull_32(); /* program counter */ + m68ki_fake_pull_16(); /* format word */ + m68ki_set_sr_noint(new_sr); + goto rte_loop; + case 2: /* Trap */ + new_sr = m68ki_pull_16(); + new_pc = m68ki_pull_32(); + m68ki_fake_pull_16(); /* format word */ + m68ki_fake_pull_32(); /* address */ + m68ki_jump(new_pc); + m68ki_set_sr(new_sr); + return; + } + /* Not handling long or short bus fault */ + m68ki_exception_format_error(); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_rtm_32(void) +{ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_rtr_32(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_ccr(m68ki_pull_16()); + m68ki_jump(m68ki_pull_32()); +} + + +void m68k_op_rts_32(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_jump(m68ki_pull_32()); +} + + +void m68k_op_sbcd_8_rr(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_N = NFLAG_8(res); /* officially undefined */ + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_sbcd_8_mm_ax7(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_N = NFLAG_8(res); /* officially undefined */ + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_sbcd_8_mm_ay7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_N = NFLAG_8(res); /* officially undefined */ + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_sbcd_8_mm_axy7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_N = NFLAG_8(res); /* officially undefined */ + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_sbcd_8_mm(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_N = NFLAG_8(res); /* officially undefined */ + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_st_8_d(void) +{ + DY |= 0xff; +} + + +void m68k_op_st_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), 0xff); +} + + +void m68k_op_st_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), 0xff); +} + + +void m68k_op_st_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), 0xff); +} + + +void m68k_op_st_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), 0xff); +} + + +void m68k_op_st_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), 0xff); +} + + +void m68k_op_st_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), 0xff); +} + + +void m68k_op_st_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), 0xff); +} + + +void m68k_op_st_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), 0xff); +} + + +void m68k_op_st_8_al(void) +{ + m68ki_write_8(EA_AL_8(), 0xff); +} + + +void m68k_op_sf_8_d(void) +{ + DY &= 0xffffff00; +} + + +void m68k_op_sf_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), 0); +} + + +void m68k_op_sf_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), 0); +} + + +void m68k_op_sf_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), 0); +} + + +void m68k_op_sf_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), 0); +} + + +void m68k_op_sf_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), 0); +} + + +void m68k_op_sf_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), 0); +} + + +void m68k_op_sf_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), 0); +} + + +void m68k_op_sf_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), 0); +} + + +void m68k_op_sf_8_al(void) +{ + m68ki_write_8(EA_AL_8(), 0); +} + + +void m68k_op_shi_8_d(void) +{ + if(COND_HI()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sls_8_d(void) +{ + if(COND_LS()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_scc_8_d(void) +{ + if(COND_CC()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_scs_8_d(void) +{ + if(COND_CS()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sne_8_d(void) +{ + if(COND_NE()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_seq_8_d(void) +{ + if(COND_EQ()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_svc_8_d(void) +{ + if(COND_VC()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_svs_8_d(void) +{ + if(COND_VS()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_spl_8_d(void) +{ + if(COND_PL()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_smi_8_d(void) +{ + if(COND_MI()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sge_8_d(void) +{ + if(COND_GE()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_slt_8_d(void) +{ + if(COND_LT()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sgt_8_d(void) +{ + if(COND_GT()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sle_8_d(void) +{ + if(COND_LE()) + { + DY |= 0xff; + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_shi_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_sls_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_scc_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scs_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_sne_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_seq_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_svc_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svs_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_spl_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_smi_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_sge_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_slt_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sle_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_stop(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + CPU_STOPPED |= STOP_LEVEL_STOP; + m68ki_set_sr(new_sr); + m68ki_remaining_cycles = 0; + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_sub_8_er_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pi7(void) +{ + uint* r_dst = &DX; + uint src = OPER_A7_PI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pd7(void) +{ + uint* r_dst = &DX; + uint src = OPER_A7_PD_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_a(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(AY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_32_er_d(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_a(void) +{ + uint* r_dst = &DX; + uint src = AY; + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_8_re_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_aw(void) +{ + uint ea = EA_AW_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_al(void) +{ + uint ea = EA_AL_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_aw(void) +{ + uint ea = EA_AW_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_al(void) +{ + uint ea = EA_AL_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_di(void) +{ + uint ea = EA_AY_DI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_aw(void) +{ + uint ea = EA_AW_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_al(void) +{ + uint ea = EA_AL_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_suba_16_d(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY)); +} + + +void m68k_op_suba_16_a(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY)); +} + + +void m68k_op_suba_16_ai(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_AI_16())); +} + + +void m68k_op_suba_16_pi(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_PI_16())); +} + + +void m68k_op_suba_16_pd(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_PD_16())); +} + + +void m68k_op_suba_16_di(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_DI_16())); +} + + +void m68k_op_suba_16_ix(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AY_IX_16())); +} + + +void m68k_op_suba_16_aw(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AW_16())); +} + + +void m68k_op_suba_16_al(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_AL_16())); +} + + +void m68k_op_suba_16_pcdi(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_PCDI_16())); +} + + +void m68k_op_suba_16_pcix(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_PCIX_16())); +} + + +void m68k_op_suba_16_i(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(OPER_I_16())); +} + + +void m68k_op_suba_32_d(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY); +} + + +void m68k_op_suba_32_a(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY); +} + + +void m68k_op_suba_32_ai(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_AI_32()); +} + + +void m68k_op_suba_32_pi(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_PI_32()); +} + + +void m68k_op_suba_32_pd(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_PD_32()); +} + + +void m68k_op_suba_32_di(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_DI_32()); +} + + +void m68k_op_suba_32_ix(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AY_IX_32()); +} + + +void m68k_op_suba_32_aw(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AW_32()); +} + + +void m68k_op_suba_32_al(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_AL_32()); +} + + +void m68k_op_suba_32_pcdi(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_PCDI_32()); +} + + +void m68k_op_suba_32_pcix(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_PCIX_32()); +} + + +void m68k_op_suba_32_i(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - OPER_I_32()); +} + + +void m68k_op_subi_8_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_subi_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_16_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_subi_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_32_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_subi_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_8_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_subq_8_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_pi7(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_pd7(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_16_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_subq_16_a(void) +{ + uint* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1)); +} + + +void m68k_op_subq_16_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_32_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_subq_32_a(void) +{ + uint* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1)); +} + + +void m68k_op_subq_32_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subx_8_rr(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_subx_16_rr(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +void m68k_op_subx_32_rr(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + *r_dst = res; +} + + +void m68k_op_subx_8_mm_ax7(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_subx_8_mm_ay7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_subx_8_mm_axy7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_subx_8_mm(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_subx_16_mm(void) +{ + uint src = OPER_AY_PD_16(); + uint ea = EA_AX_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_subx_32_mm(void) +{ + uint src = OPER_AY_PD_32(); + uint ea = EA_AX_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_swap_32(void) +{ + uint* r_dst = &DY; + + FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16); + *r_dst = (*r_dst>>16) | FLAG_Z; + + FLAG_Z = *r_dst; + FLAG_N = NFLAG_32(*r_dst); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_tas_8_d(void) +{ + uint* r_dst = &DY; + + FLAG_Z = MASK_OUT_ABOVE_8(*r_dst); + FLAG_N = NFLAG_8(*r_dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst |= 0x80; +} + + +void m68k_op_tas_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +#if GENESIS_HACKS + /* Write-back prevented in this system */ +#else + m68ki_write_8(ea, dst | 0x80); +#endif +} + + +void m68k_op_tas_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +#if GENESIS_HACKS + /* Write-back prevented in this system */ +#else + m68ki_write_8(ea, dst | 0x80); +#endif +} + + +void m68k_op_tas_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +#if GENESIS_HACKS + /* Write-back prevented in this system */ +#else + m68ki_write_8(ea, dst | 0x80); +#endif +} + + +void m68k_op_tas_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +#if GENESIS_HACKS + /* Write-back prevented in this system */ +#else + m68ki_write_8(ea, dst | 0x80); +#endif +} + + +void m68k_op_tas_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +#if GENESIS_HACKS + /* Write-back prevented in this system */ +#else + m68ki_write_8(ea, dst | 0x80); +#endif +} + + +void m68k_op_tas_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +#if GENESIS_HACKS + /* Write-back prevented in this system */ +#else + m68ki_write_8(ea, dst | 0x80); +#endif +} + + +void m68k_op_tas_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +#if GENESIS_HACKS + /* Write-back prevented in this system */ +#else + m68ki_write_8(ea, dst | 0x80); +#endif +} + + +void m68k_op_tas_8_aw(void) +{ + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +#if GENESIS_HACKS + /* Write-back prevented in this system */ +#else + m68ki_write_8(ea, dst | 0x80); +#endif +} + + +void m68k_op_tas_8_al(void) +{ + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +#if GENESIS_HACKS + /* Write-back prevented in this system */ +#else + m68ki_write_8(ea, dst | 0x80); +#endif +} + + +void m68k_op_trap(void) +{ + /* Trap#n stacks exception frame type 0 */ + m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */ +} + + +void m68k_op_trapt(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapt_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapf(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapf_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapf_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traphi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_HI()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapls(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LS()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcc(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CC()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcs(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CS()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapne(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_NE()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapeq(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_EQ()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvc(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VC()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvs(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VS()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trappl(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_PL()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapmi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_MI()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapge(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GE()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traplt(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LT()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapgt(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GT()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traple(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LE()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traphi_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_HI()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapls_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcc_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CC()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcs_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapne_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_NE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapeq_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_EQ()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvc_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VC()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvs_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trappl_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_PL()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapmi_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_MI()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapge_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traplt_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LT()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapgt_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GT()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traple_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traphi_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_HI()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapls_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CC()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcs_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapne_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_NE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapeq_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_EQ()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VC()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvs_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trappl_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_PL()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapmi_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_MI()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapge_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traplt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LT()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapgt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GT()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traple_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapv(void) +{ + if(COND_VC()) + { + return; + } + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ +} + + +void m68k_op_tst_8_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint res = m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint res = m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint res = m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint res = m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint res = m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint res = m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint res = m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_aw(void) +{ + uint ea = EA_AW_8(); + uint res = m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_al(void) +{ + uint ea = EA_AL_8(); + uint res = m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCDI_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_8_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCIX_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_8_i(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_I_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_16_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_a(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = MAKE_INT_16(AY); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_16_ai(void) +{ + uint res = OPER_AY_AI_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_pi(void) +{ + uint res = OPER_AY_PI_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_pd(void) +{ + uint res = OPER_AY_PD_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_di(void) +{ + uint res = OPER_AY_DI_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_ix(void) +{ + uint res = OPER_AY_IX_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_aw(void) +{ + uint res = OPER_AW_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_al(void) +{ + uint res = OPER_AL_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCDI_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_16_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCIX_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_16_i(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_I_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_32_d(void) +{ + uint res = DY; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_a(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = AY; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_32_ai(void) +{ + uint res = OPER_AY_AI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_pi(void) +{ + uint res = OPER_AY_PI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_pd(void) +{ + uint res = OPER_AY_PD_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_di(void) +{ + uint res = OPER_AY_DI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_ix(void) +{ + uint res = OPER_AY_IX_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_aw(void) +{ + uint res = OPER_AW_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_al(void) +{ + uint res = OPER_AL_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCDI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCIX_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_32_i(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_I_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unlk_32_a7(void) +{ + REG_A[7] = m68ki_read_32(REG_A[7]); +} + + +void m68k_op_unlk_32(void) +{ + uint* r_dst = &AY; + + REG_A[7] = *r_dst; + *r_dst = m68ki_pull_32(); +} + + +void m68k_op_unpk_16_rr(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: DX and DY are reversed in Motorola's docs */ + uint src = DY; + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unpk_16_mm_ax7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint src = OPER_AY_PD_8(); + uint ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + ea_dst = EA_A7_PD_8(); + m68ki_write_8(ea_dst, (src >> 8) & 0xff); + ea_dst = EA_A7_PD_8(); + m68ki_write_8(ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unpk_16_mm_ay7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint src = OPER_A7_PD_8(); + uint ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + ea_dst = EA_AX_PD_8(); + m68ki_write_8(ea_dst, (src >> 8) & 0xff); + ea_dst = EA_AX_PD_8(); + m68ki_write_8(ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unpk_16_mm_axy7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_A7_PD_8(); + uint ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + ea_dst = EA_A7_PD_8(); + m68ki_write_8(ea_dst, (src >> 8) & 0xff); + ea_dst = EA_A7_PD_8(); + m68ki_write_8(ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unpk_16_mm(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint src = OPER_AY_PD_8(); + uint ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + ea_dst = EA_AX_PD_8(); + m68ki_write_8(ea_dst, (src >> 8) & 0xff); + ea_dst = EA_AX_PD_8(); + m68ki_write_8(ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(); +} + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + diff --git a/MCUME_teensy/teensygen/m68kops.c b/MCUME_teensy/teensygen/m68kops.c new file mode 100644 index 0000000..a16629e --- /dev/null +++ b/MCUME_teensy/teensygen/m68kops.c @@ -0,0 +1,4101 @@ +#include "arduinoproto.h" + +PROGMEM const unsigned char m68ki_cycles[1][0x10000]={ + { + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0, + 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, + 30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, + 34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 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a/MCUME_teensy/teensygen/m68kops.h b/MCUME_teensy/teensygen/m68kops.h new file mode 100644 index 0000000..4ce5cda --- /dev/null +++ b/MCUME_teensy/teensygen/m68kops.h @@ -0,0 +1,1984 @@ +#ifndef M68KOPS__HEADER +#define M68KOPS__HEADER + +/* ======================================================================== */ +/* ============================ OPCODE HANDLERS =========================== */ +/* ======================================================================== */ + + +void m68k_op_1010(void); +void m68k_op_1111(void); +void m68k_op_abcd_8_rr(void); +void m68k_op_abcd_8_mm_ax7(void); +void m68k_op_abcd_8_mm_ay7(void); +void m68k_op_abcd_8_mm_axy7(void); +void m68k_op_abcd_8_mm(void); +void m68k_op_add_8_er_d(void); +void m68k_op_add_8_er_ai(void); +void m68k_op_add_8_er_pi(void); +void m68k_op_add_8_er_pi7(void); +void m68k_op_add_8_er_pd(void); +void m68k_op_add_8_er_pd7(void); +void m68k_op_add_8_er_di(void); +void m68k_op_add_8_er_ix(void); +void m68k_op_add_8_er_aw(void); +void m68k_op_add_8_er_al(void); +void m68k_op_add_8_er_pcdi(void); +void m68k_op_add_8_er_pcix(void); +void m68k_op_add_8_er_i(void); +void m68k_op_add_16_er_d(void); +void m68k_op_add_16_er_a(void); +void m68k_op_add_16_er_ai(void); +void m68k_op_add_16_er_pi(void); +void m68k_op_add_16_er_pd(void); +void m68k_op_add_16_er_di(void); +void m68k_op_add_16_er_ix(void); +void m68k_op_add_16_er_aw(void); +void m68k_op_add_16_er_al(void); +void m68k_op_add_16_er_pcdi(void); +void m68k_op_add_16_er_pcix(void); +void m68k_op_add_16_er_i(void); +void m68k_op_add_32_er_d(void); +void m68k_op_add_32_er_a(void); +void m68k_op_add_32_er_ai(void); +void m68k_op_add_32_er_pi(void); +void m68k_op_add_32_er_pd(void); +void m68k_op_add_32_er_di(void); +void m68k_op_add_32_er_ix(void); +void m68k_op_add_32_er_aw(void); +void m68k_op_add_32_er_al(void); +void m68k_op_add_32_er_pcdi(void); +void m68k_op_add_32_er_pcix(void); +void m68k_op_add_32_er_i(void); +void m68k_op_add_8_re_ai(void); +void m68k_op_add_8_re_pi(void); +void m68k_op_add_8_re_pi7(void); +void m68k_op_add_8_re_pd(void); +void m68k_op_add_8_re_pd7(void); +void m68k_op_add_8_re_di(void); +void m68k_op_add_8_re_ix(void); +void m68k_op_add_8_re_aw(void); +void m68k_op_add_8_re_al(void); +void m68k_op_add_16_re_ai(void); +void m68k_op_add_16_re_pi(void); +void m68k_op_add_16_re_pd(void); +void m68k_op_add_16_re_di(void); +void m68k_op_add_16_re_ix(void); +void m68k_op_add_16_re_aw(void); +void m68k_op_add_16_re_al(void); +void m68k_op_add_32_re_ai(void); +void m68k_op_add_32_re_pi(void); +void m68k_op_add_32_re_pd(void); +void m68k_op_add_32_re_di(void); +void m68k_op_add_32_re_ix(void); +void m68k_op_add_32_re_aw(void); +void m68k_op_add_32_re_al(void); +void m68k_op_adda_16_d(void); +void m68k_op_adda_16_a(void); +void m68k_op_adda_16_ai(void); +void m68k_op_adda_16_pi(void); +void m68k_op_adda_16_pd(void); +void m68k_op_adda_16_di(void); +void m68k_op_adda_16_ix(void); +void m68k_op_adda_16_aw(void); +void m68k_op_adda_16_al(void); +void m68k_op_adda_16_pcdi(void); +void m68k_op_adda_16_pcix(void); +void m68k_op_adda_16_i(void); +void m68k_op_adda_32_d(void); +void m68k_op_adda_32_a(void); +void m68k_op_adda_32_ai(void); +void m68k_op_adda_32_pi(void); +void m68k_op_adda_32_pd(void); +void m68k_op_adda_32_di(void); +void m68k_op_adda_32_ix(void); +void m68k_op_adda_32_aw(void); +void m68k_op_adda_32_al(void); +void m68k_op_adda_32_pcdi(void); +void m68k_op_adda_32_pcix(void); +void m68k_op_adda_32_i(void); +void m68k_op_addi_8_d(void); +void m68k_op_addi_8_ai(void); +void m68k_op_addi_8_pi(void); +void m68k_op_addi_8_pi7(void); +void m68k_op_addi_8_pd(void); +void m68k_op_addi_8_pd7(void); +void m68k_op_addi_8_di(void); +void m68k_op_addi_8_ix(void); +void m68k_op_addi_8_aw(void); +void m68k_op_addi_8_al(void); +void m68k_op_addi_16_d(void); +void m68k_op_addi_16_ai(void); +void m68k_op_addi_16_pi(void); +void m68k_op_addi_16_pd(void); +void m68k_op_addi_16_di(void); +void m68k_op_addi_16_ix(void); +void m68k_op_addi_16_aw(void); +void m68k_op_addi_16_al(void); +void m68k_op_addi_32_d(void); +void m68k_op_addi_32_ai(void); +void m68k_op_addi_32_pi(void); +void m68k_op_addi_32_pd(void); +void m68k_op_addi_32_di(void); +void m68k_op_addi_32_ix(void); +void m68k_op_addi_32_aw(void); +void m68k_op_addi_32_al(void); +void m68k_op_addq_8_d(void); +void m68k_op_addq_8_ai(void); +void m68k_op_addq_8_pi(void); +void m68k_op_addq_8_pi7(void); +void m68k_op_addq_8_pd(void); +void m68k_op_addq_8_pd7(void); +void m68k_op_addq_8_di(void); +void m68k_op_addq_8_ix(void); +void m68k_op_addq_8_aw(void); +void m68k_op_addq_8_al(void); +void m68k_op_addq_16_d(void); +void m68k_op_addq_16_a(void); +void m68k_op_addq_16_ai(void); +void m68k_op_addq_16_pi(void); +void m68k_op_addq_16_pd(void); +void m68k_op_addq_16_di(void); +void m68k_op_addq_16_ix(void); +void m68k_op_addq_16_aw(void); +void m68k_op_addq_16_al(void); +void m68k_op_addq_32_d(void); +void m68k_op_addq_32_a(void); +void m68k_op_addq_32_ai(void); +void m68k_op_addq_32_pi(void); +void m68k_op_addq_32_pd(void); +void m68k_op_addq_32_di(void); +void m68k_op_addq_32_ix(void); +void m68k_op_addq_32_aw(void); +void m68k_op_addq_32_al(void); +void m68k_op_addx_8_rr(void); +void m68k_op_addx_16_rr(void); +void m68k_op_addx_32_rr(void); +void m68k_op_addx_8_mm_ax7(void); +void m68k_op_addx_8_mm_ay7(void); +void m68k_op_addx_8_mm_axy7(void); +void m68k_op_addx_8_mm(void); +void m68k_op_addx_16_mm(void); +void m68k_op_addx_32_mm(void); +void m68k_op_and_8_er_d(void); +void m68k_op_and_8_er_ai(void); +void m68k_op_and_8_er_pi(void); +void m68k_op_and_8_er_pi7(void); +void m68k_op_and_8_er_pd(void); +void m68k_op_and_8_er_pd7(void); +void m68k_op_and_8_er_di(void); +void m68k_op_and_8_er_ix(void); +void m68k_op_and_8_er_aw(void); +void m68k_op_and_8_er_al(void); +void m68k_op_and_8_er_pcdi(void); +void m68k_op_and_8_er_pcix(void); +void m68k_op_and_8_er_i(void); +void m68k_op_and_16_er_d(void); +void m68k_op_and_16_er_ai(void); +void m68k_op_and_16_er_pi(void); +void m68k_op_and_16_er_pd(void); +void m68k_op_and_16_er_di(void); +void m68k_op_and_16_er_ix(void); +void m68k_op_and_16_er_aw(void); +void m68k_op_and_16_er_al(void); +void m68k_op_and_16_er_pcdi(void); +void m68k_op_and_16_er_pcix(void); +void m68k_op_and_16_er_i(void); +void m68k_op_and_32_er_d(void); +void m68k_op_and_32_er_ai(void); +void m68k_op_and_32_er_pi(void); +void m68k_op_and_32_er_pd(void); +void m68k_op_and_32_er_di(void); +void m68k_op_and_32_er_ix(void); +void m68k_op_and_32_er_aw(void); +void m68k_op_and_32_er_al(void); +void m68k_op_and_32_er_pcdi(void); +void m68k_op_and_32_er_pcix(void); +void m68k_op_and_32_er_i(void); +void m68k_op_and_8_re_ai(void); +void m68k_op_and_8_re_pi(void); +void m68k_op_and_8_re_pi7(void); +void m68k_op_and_8_re_pd(void); +void m68k_op_and_8_re_pd7(void); +void m68k_op_and_8_re_di(void); +void m68k_op_and_8_re_ix(void); +void m68k_op_and_8_re_aw(void); +void m68k_op_and_8_re_al(void); +void m68k_op_and_16_re_ai(void); +void m68k_op_and_16_re_pi(void); +void m68k_op_and_16_re_pd(void); +void m68k_op_and_16_re_di(void); +void m68k_op_and_16_re_ix(void); +void m68k_op_and_16_re_aw(void); +void m68k_op_and_16_re_al(void); +void m68k_op_and_32_re_ai(void); +void m68k_op_and_32_re_pi(void); +void m68k_op_and_32_re_pd(void); +void m68k_op_and_32_re_di(void); +void m68k_op_and_32_re_ix(void); +void m68k_op_and_32_re_aw(void); +void m68k_op_and_32_re_al(void); +void m68k_op_andi_8_d(void); +void m68k_op_andi_8_ai(void); +void m68k_op_andi_8_pi(void); +void m68k_op_andi_8_pi7(void); +void m68k_op_andi_8_pd(void); +void m68k_op_andi_8_pd7(void); +void m68k_op_andi_8_di(void); +void m68k_op_andi_8_ix(void); +void m68k_op_andi_8_aw(void); +void m68k_op_andi_8_al(void); +void m68k_op_andi_16_d(void); +void m68k_op_andi_16_ai(void); +void m68k_op_andi_16_pi(void); +void m68k_op_andi_16_pd(void); +void m68k_op_andi_16_di(void); +void m68k_op_andi_16_ix(void); +void m68k_op_andi_16_aw(void); +void m68k_op_andi_16_al(void); +void m68k_op_andi_32_d(void); +void m68k_op_andi_32_ai(void); +void m68k_op_andi_32_pi(void); +void m68k_op_andi_32_pd(void); +void m68k_op_andi_32_di(void); +void m68k_op_andi_32_ix(void); +void m68k_op_andi_32_aw(void); +void m68k_op_andi_32_al(void); +void m68k_op_andi_16_toc(void); +void m68k_op_andi_16_tos(void); +void m68k_op_asr_8_s(void); +void m68k_op_asr_16_s(void); +void m68k_op_asr_32_s(void); +void m68k_op_asr_8_r(void); +void m68k_op_asr_16_r(void); +void m68k_op_asr_32_r(void); +void m68k_op_asr_16_ai(void); +void m68k_op_asr_16_pi(void); +void m68k_op_asr_16_pd(void); +void m68k_op_asr_16_di(void); +void m68k_op_asr_16_ix(void); +void m68k_op_asr_16_aw(void); +void m68k_op_asr_16_al(void); +void m68k_op_asl_8_s(void); +void m68k_op_asl_16_s(void); +void m68k_op_asl_32_s(void); +void m68k_op_asl_8_r(void); +void m68k_op_asl_16_r(void); +void m68k_op_asl_32_r(void); +void m68k_op_asl_16_ai(void); +void m68k_op_asl_16_pi(void); +void m68k_op_asl_16_pd(void); +void m68k_op_asl_16_di(void); +void m68k_op_asl_16_ix(void); +void m68k_op_asl_16_aw(void); +void m68k_op_asl_16_al(void); +void m68k_op_bhi_8(void); +void m68k_op_bls_8(void); +void m68k_op_bcc_8(void); +void m68k_op_bcs_8(void); +void m68k_op_bne_8(void); +void m68k_op_beq_8(void); +void m68k_op_bvc_8(void); +void m68k_op_bvs_8(void); +void m68k_op_bpl_8(void); +void m68k_op_bmi_8(void); +void m68k_op_bge_8(void); +void m68k_op_blt_8(void); +void m68k_op_bgt_8(void); +void m68k_op_ble_8(void); +void m68k_op_bhi_16(void); +void m68k_op_bls_16(void); +void m68k_op_bcc_16(void); +void m68k_op_bcs_16(void); +void m68k_op_bne_16(void); +void m68k_op_beq_16(void); +void m68k_op_bvc_16(void); +void m68k_op_bvs_16(void); +void m68k_op_bpl_16(void); +void m68k_op_bmi_16(void); +void m68k_op_bge_16(void); +void m68k_op_blt_16(void); +void m68k_op_bgt_16(void); +void m68k_op_ble_16(void); +void m68k_op_bhi_32(void); +void m68k_op_bls_32(void); +void m68k_op_bcc_32(void); +void m68k_op_bcs_32(void); +void m68k_op_bne_32(void); +void m68k_op_beq_32(void); +void m68k_op_bvc_32(void); +void m68k_op_bvs_32(void); +void m68k_op_bpl_32(void); +void m68k_op_bmi_32(void); +void m68k_op_bge_32(void); +void m68k_op_blt_32(void); +void m68k_op_bgt_32(void); +void m68k_op_ble_32(void); +void m68k_op_bchg_32_r_d(void); +void m68k_op_bchg_8_r_ai(void); +void m68k_op_bchg_8_r_pi(void); +void m68k_op_bchg_8_r_pi7(void); +void m68k_op_bchg_8_r_pd(void); +void m68k_op_bchg_8_r_pd7(void); +void m68k_op_bchg_8_r_di(void); +void m68k_op_bchg_8_r_ix(void); +void m68k_op_bchg_8_r_aw(void); +void m68k_op_bchg_8_r_al(void); +void m68k_op_bchg_32_s_d(void); +void m68k_op_bchg_8_s_ai(void); +void m68k_op_bchg_8_s_pi(void); +void m68k_op_bchg_8_s_pi7(void); +void m68k_op_bchg_8_s_pd(void); +void m68k_op_bchg_8_s_pd7(void); +void m68k_op_bchg_8_s_di(void); +void m68k_op_bchg_8_s_ix(void); +void m68k_op_bchg_8_s_aw(void); +void m68k_op_bchg_8_s_al(void); +void m68k_op_bclr_32_r_d(void); +void m68k_op_bclr_8_r_ai(void); +void m68k_op_bclr_8_r_pi(void); +void m68k_op_bclr_8_r_pi7(void); +void m68k_op_bclr_8_r_pd(void); +void m68k_op_bclr_8_r_pd7(void); +void m68k_op_bclr_8_r_di(void); +void m68k_op_bclr_8_r_ix(void); +void m68k_op_bclr_8_r_aw(void); +void m68k_op_bclr_8_r_al(void); +void m68k_op_bclr_32_s_d(void); +void m68k_op_bclr_8_s_ai(void); +void m68k_op_bclr_8_s_pi(void); +void m68k_op_bclr_8_s_pi7(void); +void m68k_op_bclr_8_s_pd(void); +void m68k_op_bclr_8_s_pd7(void); +void m68k_op_bclr_8_s_di(void); +void m68k_op_bclr_8_s_ix(void); +void m68k_op_bclr_8_s_aw(void); +void m68k_op_bclr_8_s_al(void); +void m68k_op_bfchg_32_d(void); +void m68k_op_bfchg_32_ai(void); +void m68k_op_bfchg_32_di(void); +void m68k_op_bfchg_32_ix(void); +void m68k_op_bfchg_32_aw(void); +void m68k_op_bfchg_32_al(void); +void m68k_op_bfclr_32_d(void); +void m68k_op_bfclr_32_ai(void); +void m68k_op_bfclr_32_di(void); +void m68k_op_bfclr_32_ix(void); +void m68k_op_bfclr_32_aw(void); +void m68k_op_bfclr_32_al(void); +void m68k_op_bfexts_32_d(void); +void m68k_op_bfexts_32_ai(void); +void m68k_op_bfexts_32_di(void); +void m68k_op_bfexts_32_ix(void); +void m68k_op_bfexts_32_aw(void); +void m68k_op_bfexts_32_al(void); +void m68k_op_bfexts_32_pcdi(void); +void m68k_op_bfexts_32_pcix(void); +void m68k_op_bfextu_32_d(void); +void m68k_op_bfextu_32_ai(void); +void m68k_op_bfextu_32_di(void); +void m68k_op_bfextu_32_ix(void); +void m68k_op_bfextu_32_aw(void); +void m68k_op_bfextu_32_al(void); +void m68k_op_bfextu_32_pcdi(void); +void m68k_op_bfextu_32_pcix(void); +void m68k_op_bfffo_32_d(void); +void m68k_op_bfffo_32_ai(void); +void m68k_op_bfffo_32_di(void); +void m68k_op_bfffo_32_ix(void); +void m68k_op_bfffo_32_aw(void); +void m68k_op_bfffo_32_al(void); +void m68k_op_bfffo_32_pcdi(void); +void m68k_op_bfffo_32_pcix(void); +void m68k_op_bfins_32_d(void); +void m68k_op_bfins_32_ai(void); +void m68k_op_bfins_32_di(void); +void m68k_op_bfins_32_ix(void); +void m68k_op_bfins_32_aw(void); +void m68k_op_bfins_32_al(void); +void m68k_op_bfset_32_d(void); +void m68k_op_bfset_32_ai(void); +void m68k_op_bfset_32_di(void); +void m68k_op_bfset_32_ix(void); +void m68k_op_bfset_32_aw(void); +void m68k_op_bfset_32_al(void); +void m68k_op_bftst_32_d(void); +void m68k_op_bftst_32_ai(void); +void m68k_op_bftst_32_di(void); +void m68k_op_bftst_32_ix(void); +void m68k_op_bftst_32_aw(void); +void m68k_op_bftst_32_al(void); +void m68k_op_bftst_32_pcdi(void); +void m68k_op_bftst_32_pcix(void); +void m68k_op_bkpt(void); +void m68k_op_bra_8(void); +void m68k_op_bra_16(void); +void m68k_op_bra_32(void); +void m68k_op_bset_32_r_d(void); +void m68k_op_bset_8_r_ai(void); +void m68k_op_bset_8_r_pi(void); +void m68k_op_bset_8_r_pi7(void); +void m68k_op_bset_8_r_pd(void); +void m68k_op_bset_8_r_pd7(void); +void m68k_op_bset_8_r_di(void); +void m68k_op_bset_8_r_ix(void); +void m68k_op_bset_8_r_aw(void); +void m68k_op_bset_8_r_al(void); +void m68k_op_bset_32_s_d(void); +void m68k_op_bset_8_s_ai(void); +void m68k_op_bset_8_s_pi(void); +void m68k_op_bset_8_s_pi7(void); +void m68k_op_bset_8_s_pd(void); +void m68k_op_bset_8_s_pd7(void); +void m68k_op_bset_8_s_di(void); +void m68k_op_bset_8_s_ix(void); +void m68k_op_bset_8_s_aw(void); +void m68k_op_bset_8_s_al(void); +void m68k_op_bsr_8(void); +void m68k_op_bsr_16(void); +void m68k_op_bsr_32(void); +void m68k_op_btst_32_r_d(void); +void m68k_op_btst_8_r_ai(void); +void m68k_op_btst_8_r_pi(void); +void m68k_op_btst_8_r_pi7(void); +void m68k_op_btst_8_r_pd(void); +void m68k_op_btst_8_r_pd7(void); +void m68k_op_btst_8_r_di(void); +void m68k_op_btst_8_r_ix(void); +void m68k_op_btst_8_r_aw(void); +void m68k_op_btst_8_r_al(void); +void m68k_op_btst_8_r_pcdi(void); +void m68k_op_btst_8_r_pcix(void); +void m68k_op_btst_8_r_i(void); +void m68k_op_btst_32_s_d(void); +void m68k_op_btst_8_s_ai(void); +void m68k_op_btst_8_s_pi(void); +void m68k_op_btst_8_s_pi7(void); +void m68k_op_btst_8_s_pd(void); +void m68k_op_btst_8_s_pd7(void); +void m68k_op_btst_8_s_di(void); +void m68k_op_btst_8_s_ix(void); +void m68k_op_btst_8_s_aw(void); +void m68k_op_btst_8_s_al(void); +void m68k_op_btst_8_s_pcdi(void); +void m68k_op_btst_8_s_pcix(void); +void m68k_op_callm_32_ai(void); +void m68k_op_callm_32_di(void); +void m68k_op_callm_32_ix(void); +void m68k_op_callm_32_aw(void); +void m68k_op_callm_32_al(void); +void m68k_op_callm_32_pcdi(void); +void m68k_op_callm_32_pcix(void); +void m68k_op_cas_8_ai(void); +void m68k_op_cas_8_pi(void); +void m68k_op_cas_8_pi7(void); +void m68k_op_cas_8_pd(void); +void m68k_op_cas_8_pd7(void); +void m68k_op_cas_8_di(void); +void m68k_op_cas_8_ix(void); +void m68k_op_cas_8_aw(void); +void m68k_op_cas_8_al(void); +void m68k_op_cas_16_ai(void); +void m68k_op_cas_16_pi(void); +void m68k_op_cas_16_pd(void); +void m68k_op_cas_16_di(void); +void m68k_op_cas_16_ix(void); +void m68k_op_cas_16_aw(void); +void m68k_op_cas_16_al(void); +void m68k_op_cas_32_ai(void); +void m68k_op_cas_32_pi(void); +void m68k_op_cas_32_pd(void); +void m68k_op_cas_32_di(void); +void m68k_op_cas_32_ix(void); +void m68k_op_cas_32_aw(void); +void m68k_op_cas_32_al(void); +void m68k_op_cas2_16(void); +void m68k_op_cas2_32(void); +void m68k_op_chk_16_d(void); +void m68k_op_chk_16_ai(void); +void m68k_op_chk_16_pi(void); +void m68k_op_chk_16_pd(void); +void m68k_op_chk_16_di(void); +void m68k_op_chk_16_ix(void); +void m68k_op_chk_16_aw(void); +void m68k_op_chk_16_al(void); +void m68k_op_chk_16_pcdi(void); +void m68k_op_chk_16_pcix(void); +void m68k_op_chk_16_i(void); +void m68k_op_chk_32_d(void); +void m68k_op_chk_32_ai(void); +void m68k_op_chk_32_pi(void); +void m68k_op_chk_32_pd(void); +void m68k_op_chk_32_di(void); +void m68k_op_chk_32_ix(void); +void m68k_op_chk_32_aw(void); +void m68k_op_chk_32_al(void); +void m68k_op_chk_32_pcdi(void); +void m68k_op_chk_32_pcix(void); +void m68k_op_chk_32_i(void); +void m68k_op_chk2cmp2_8_ai(void); +void m68k_op_chk2cmp2_8_di(void); +void m68k_op_chk2cmp2_8_ix(void); +void m68k_op_chk2cmp2_8_aw(void); +void m68k_op_chk2cmp2_8_al(void); +void m68k_op_chk2cmp2_8_pcdi(void); +void m68k_op_chk2cmp2_8_pcix(void); +void m68k_op_chk2cmp2_16_ai(void); +void m68k_op_chk2cmp2_16_di(void); +void m68k_op_chk2cmp2_16_ix(void); +void m68k_op_chk2cmp2_16_aw(void); +void m68k_op_chk2cmp2_16_al(void); +void m68k_op_chk2cmp2_16_pcdi(void); +void m68k_op_chk2cmp2_16_pcix(void); +void m68k_op_chk2cmp2_32_ai(void); +void m68k_op_chk2cmp2_32_di(void); +void m68k_op_chk2cmp2_32_ix(void); +void m68k_op_chk2cmp2_32_aw(void); +void m68k_op_chk2cmp2_32_al(void); +void m68k_op_chk2cmp2_32_pcdi(void); +void m68k_op_chk2cmp2_32_pcix(void); +void m68k_op_clr_8_d(void); +void m68k_op_clr_8_ai(void); +void m68k_op_clr_8_pi(void); +void m68k_op_clr_8_pi7(void); +void m68k_op_clr_8_pd(void); +void m68k_op_clr_8_pd7(void); +void m68k_op_clr_8_di(void); +void m68k_op_clr_8_ix(void); +void m68k_op_clr_8_aw(void); +void m68k_op_clr_8_al(void); +void m68k_op_clr_16_d(void); +void m68k_op_clr_16_ai(void); +void m68k_op_clr_16_pi(void); +void m68k_op_clr_16_pd(void); +void m68k_op_clr_16_di(void); +void m68k_op_clr_16_ix(void); +void m68k_op_clr_16_aw(void); +void m68k_op_clr_16_al(void); +void m68k_op_clr_32_d(void); +void m68k_op_clr_32_ai(void); +void m68k_op_clr_32_pi(void); +void m68k_op_clr_32_pd(void); +void m68k_op_clr_32_di(void); +void m68k_op_clr_32_ix(void); +void m68k_op_clr_32_aw(void); +void m68k_op_clr_32_al(void); +void m68k_op_cmp_8_d(void); +void m68k_op_cmp_8_ai(void); +void m68k_op_cmp_8_pi(void); +void m68k_op_cmp_8_pi7(void); +void m68k_op_cmp_8_pd(void); +void m68k_op_cmp_8_pd7(void); +void m68k_op_cmp_8_di(void); +void m68k_op_cmp_8_ix(void); +void m68k_op_cmp_8_aw(void); +void m68k_op_cmp_8_al(void); +void m68k_op_cmp_8_pcdi(void); +void m68k_op_cmp_8_pcix(void); +void m68k_op_cmp_8_i(void); +void m68k_op_cmp_16_d(void); +void m68k_op_cmp_16_a(void); +void m68k_op_cmp_16_ai(void); +void m68k_op_cmp_16_pi(void); +void m68k_op_cmp_16_pd(void); +void m68k_op_cmp_16_di(void); +void m68k_op_cmp_16_ix(void); +void m68k_op_cmp_16_aw(void); +void m68k_op_cmp_16_al(void); +void m68k_op_cmp_16_pcdi(void); +void m68k_op_cmp_16_pcix(void); +void m68k_op_cmp_16_i(void); +void m68k_op_cmp_32_d(void); +void m68k_op_cmp_32_a(void); +void m68k_op_cmp_32_ai(void); +void m68k_op_cmp_32_pi(void); +void m68k_op_cmp_32_pd(void); +void m68k_op_cmp_32_di(void); +void m68k_op_cmp_32_ix(void); +void m68k_op_cmp_32_aw(void); +void m68k_op_cmp_32_al(void); +void m68k_op_cmp_32_pcdi(void); +void m68k_op_cmp_32_pcix(void); +void m68k_op_cmp_32_i(void); +void m68k_op_cmpa_16_d(void); +void m68k_op_cmpa_16_a(void); +void m68k_op_cmpa_16_ai(void); +void m68k_op_cmpa_16_pi(void); +void m68k_op_cmpa_16_pd(void); +void m68k_op_cmpa_16_di(void); +void m68k_op_cmpa_16_ix(void); +void m68k_op_cmpa_16_aw(void); +void m68k_op_cmpa_16_al(void); +void m68k_op_cmpa_16_pcdi(void); +void m68k_op_cmpa_16_pcix(void); +void m68k_op_cmpa_16_i(void); +void m68k_op_cmpa_32_d(void); +void m68k_op_cmpa_32_a(void); +void m68k_op_cmpa_32_ai(void); +void m68k_op_cmpa_32_pi(void); +void m68k_op_cmpa_32_pd(void); +void m68k_op_cmpa_32_di(void); +void m68k_op_cmpa_32_ix(void); +void m68k_op_cmpa_32_aw(void); +void m68k_op_cmpa_32_al(void); +void m68k_op_cmpa_32_pcdi(void); +void m68k_op_cmpa_32_pcix(void); +void m68k_op_cmpa_32_i(void); +void m68k_op_cmpi_8_d(void); +void m68k_op_cmpi_8_ai(void); +void m68k_op_cmpi_8_pi(void); +void m68k_op_cmpi_8_pi7(void); +void m68k_op_cmpi_8_pd(void); +void m68k_op_cmpi_8_pd7(void); +void m68k_op_cmpi_8_di(void); +void m68k_op_cmpi_8_ix(void); +void m68k_op_cmpi_8_aw(void); +void m68k_op_cmpi_8_al(void); +void m68k_op_cmpi_8_pcdi(void); +void m68k_op_cmpi_8_pcix(void); +void m68k_op_cmpi_16_d(void); +void m68k_op_cmpi_16_ai(void); +void m68k_op_cmpi_16_pi(void); +void m68k_op_cmpi_16_pd(void); +void m68k_op_cmpi_16_di(void); +void m68k_op_cmpi_16_ix(void); +void m68k_op_cmpi_16_aw(void); +void m68k_op_cmpi_16_al(void); +void m68k_op_cmpi_16_pcdi(void); +void m68k_op_cmpi_16_pcix(void); +void m68k_op_cmpi_32_d(void); +void m68k_op_cmpi_32_ai(void); +void m68k_op_cmpi_32_pi(void); +void m68k_op_cmpi_32_pd(void); +void m68k_op_cmpi_32_di(void); +void m68k_op_cmpi_32_ix(void); +void m68k_op_cmpi_32_aw(void); +void m68k_op_cmpi_32_al(void); +void m68k_op_cmpi_32_pcdi(void); +void m68k_op_cmpi_32_pcix(void); +void m68k_op_cmpm_8_ax7(void); +void m68k_op_cmpm_8_ay7(void); +void m68k_op_cmpm_8_axy7(void); +void m68k_op_cmpm_8(void); +void m68k_op_cmpm_16(void); +void m68k_op_cmpm_32(void); +void m68k_op_cpbcc_32(void); +void m68k_op_cpdbcc_32(void); +void m68k_op_cpgen_32(void); +void m68k_op_cpscc_32(void); +void m68k_op_cptrapcc_32(void); +void m68k_op_dbt_16(void); +void m68k_op_dbf_16(void); +void m68k_op_dbhi_16(void); +void m68k_op_dbls_16(void); +void m68k_op_dbcc_16(void); +void m68k_op_dbcs_16(void); +void m68k_op_dbne_16(void); +void m68k_op_dbeq_16(void); +void m68k_op_dbvc_16(void); +void m68k_op_dbvs_16(void); +void m68k_op_dbpl_16(void); +void m68k_op_dbmi_16(void); +void m68k_op_dbge_16(void); +void m68k_op_dblt_16(void); +void m68k_op_dbgt_16(void); +void m68k_op_dble_16(void); +void m68k_op_divs_16_d(void); +void m68k_op_divs_16_ai(void); +void m68k_op_divs_16_pi(void); +void m68k_op_divs_16_pd(void); +void m68k_op_divs_16_di(void); +void m68k_op_divs_16_ix(void); +void m68k_op_divs_16_aw(void); +void m68k_op_divs_16_al(void); +void m68k_op_divs_16_pcdi(void); +void m68k_op_divs_16_pcix(void); +void m68k_op_divs_16_i(void); +void m68k_op_divu_16_d(void); +void m68k_op_divu_16_ai(void); +void m68k_op_divu_16_pi(void); +void m68k_op_divu_16_pd(void); +void m68k_op_divu_16_di(void); +void m68k_op_divu_16_ix(void); +void m68k_op_divu_16_aw(void); +void m68k_op_divu_16_al(void); +void m68k_op_divu_16_pcdi(void); +void m68k_op_divu_16_pcix(void); +void m68k_op_divu_16_i(void); +void m68k_op_divl_32_d(void); +void m68k_op_divl_32_ai(void); +void m68k_op_divl_32_pi(void); +void m68k_op_divl_32_pd(void); +void m68k_op_divl_32_di(void); +void m68k_op_divl_32_ix(void); +void m68k_op_divl_32_aw(void); +void m68k_op_divl_32_al(void); +void m68k_op_divl_32_pcdi(void); +void m68k_op_divl_32_pcix(void); +void m68k_op_divl_32_i(void); +void m68k_op_eor_8_d(void); +void m68k_op_eor_8_ai(void); +void m68k_op_eor_8_pi(void); +void m68k_op_eor_8_pi7(void); +void m68k_op_eor_8_pd(void); +void m68k_op_eor_8_pd7(void); +void m68k_op_eor_8_di(void); +void m68k_op_eor_8_ix(void); +void m68k_op_eor_8_aw(void); +void m68k_op_eor_8_al(void); +void m68k_op_eor_16_d(void); +void m68k_op_eor_16_ai(void); +void m68k_op_eor_16_pi(void); +void m68k_op_eor_16_pd(void); +void m68k_op_eor_16_di(void); +void m68k_op_eor_16_ix(void); +void m68k_op_eor_16_aw(void); +void m68k_op_eor_16_al(void); +void m68k_op_eor_32_d(void); +void m68k_op_eor_32_ai(void); +void m68k_op_eor_32_pi(void); +void m68k_op_eor_32_pd(void); +void m68k_op_eor_32_di(void); +void m68k_op_eor_32_ix(void); +void m68k_op_eor_32_aw(void); +void m68k_op_eor_32_al(void); +void m68k_op_eori_8_d(void); +void m68k_op_eori_8_ai(void); +void m68k_op_eori_8_pi(void); +void m68k_op_eori_8_pi7(void); +void m68k_op_eori_8_pd(void); +void m68k_op_eori_8_pd7(void); +void m68k_op_eori_8_di(void); +void m68k_op_eori_8_ix(void); +void m68k_op_eori_8_aw(void); +void m68k_op_eori_8_al(void); +void m68k_op_eori_16_d(void); +void m68k_op_eori_16_ai(void); +void m68k_op_eori_16_pi(void); +void m68k_op_eori_16_pd(void); +void m68k_op_eori_16_di(void); +void m68k_op_eori_16_ix(void); +void m68k_op_eori_16_aw(void); +void m68k_op_eori_16_al(void); +void m68k_op_eori_32_d(void); +void m68k_op_eori_32_ai(void); +void m68k_op_eori_32_pi(void); +void m68k_op_eori_32_pd(void); +void m68k_op_eori_32_di(void); +void m68k_op_eori_32_ix(void); +void m68k_op_eori_32_aw(void); +void m68k_op_eori_32_al(void); +void m68k_op_eori_16_toc(void); +void m68k_op_eori_16_tos(void); +void m68k_op_exg_32_dd(void); +void m68k_op_exg_32_aa(void); +void m68k_op_exg_32_da(void); +void m68k_op_ext_16(void); +void m68k_op_ext_32(void); +void m68k_op_extb_32(void); +void m68k_op_illegal(void); +void m68k_op_jmp_32_ai(void); +void m68k_op_jmp_32_di(void); +void m68k_op_jmp_32_ix(void); +void m68k_op_jmp_32_aw(void); +void m68k_op_jmp_32_al(void); +void m68k_op_jmp_32_pcdi(void); +void m68k_op_jmp_32_pcix(void); +void m68k_op_jsr_32_ai(void); +void m68k_op_jsr_32_di(void); +void m68k_op_jsr_32_ix(void); +void m68k_op_jsr_32_aw(void); +void m68k_op_jsr_32_al(void); +void m68k_op_jsr_32_pcdi(void); +void m68k_op_jsr_32_pcix(void); +void m68k_op_lea_32_ai(void); +void m68k_op_lea_32_di(void); +void m68k_op_lea_32_ix(void); +void m68k_op_lea_32_aw(void); +void m68k_op_lea_32_al(void); +void m68k_op_lea_32_pcdi(void); +void m68k_op_lea_32_pcix(void); +void m68k_op_link_16_a7(void); +void m68k_op_link_16(void); +void m68k_op_link_32_a7(void); +void m68k_op_link_32(void); +void m68k_op_lsr_8_s(void); +void m68k_op_lsr_16_s(void); +void m68k_op_lsr_32_s(void); +void m68k_op_lsr_8_r(void); +void m68k_op_lsr_16_r(void); +void m68k_op_lsr_32_r(void); +void m68k_op_lsr_16_ai(void); +void m68k_op_lsr_16_pi(void); +void m68k_op_lsr_16_pd(void); +void m68k_op_lsr_16_di(void); +void m68k_op_lsr_16_ix(void); +void m68k_op_lsr_16_aw(void); +void m68k_op_lsr_16_al(void); +void m68k_op_lsl_8_s(void); +void m68k_op_lsl_16_s(void); +void m68k_op_lsl_32_s(void); +void m68k_op_lsl_8_r(void); +void m68k_op_lsl_16_r(void); +void m68k_op_lsl_32_r(void); +void m68k_op_lsl_16_ai(void); +void m68k_op_lsl_16_pi(void); +void m68k_op_lsl_16_pd(void); +void m68k_op_lsl_16_di(void); +void m68k_op_lsl_16_ix(void); +void m68k_op_lsl_16_aw(void); +void m68k_op_lsl_16_al(void); +void m68k_op_move_8_d_d(void); +void m68k_op_move_8_d_ai(void); +void m68k_op_move_8_d_pi(void); +void m68k_op_move_8_d_pi7(void); +void m68k_op_move_8_d_pd(void); +void m68k_op_move_8_d_pd7(void); +void m68k_op_move_8_d_di(void); +void m68k_op_move_8_d_ix(void); +void m68k_op_move_8_d_aw(void); +void m68k_op_move_8_d_al(void); +void m68k_op_move_8_d_pcdi(void); +void m68k_op_move_8_d_pcix(void); +void m68k_op_move_8_d_i(void); +void m68k_op_move_8_ai_d(void); +void m68k_op_move_8_ai_ai(void); +void m68k_op_move_8_ai_pi(void); +void m68k_op_move_8_ai_pi7(void); +void m68k_op_move_8_ai_pd(void); +void m68k_op_move_8_ai_pd7(void); +void m68k_op_move_8_ai_di(void); +void m68k_op_move_8_ai_ix(void); +void m68k_op_move_8_ai_aw(void); +void m68k_op_move_8_ai_al(void); +void m68k_op_move_8_ai_pcdi(void); +void m68k_op_move_8_ai_pcix(void); +void m68k_op_move_8_ai_i(void); +void m68k_op_move_8_pi7_d(void); +void m68k_op_move_8_pi_d(void); +void m68k_op_move_8_pi7_ai(void); +void m68k_op_move_8_pi7_pi(void); +void m68k_op_move_8_pi7_pi7(void); +void m68k_op_move_8_pi7_pd(void); +void m68k_op_move_8_pi7_pd7(void); +void m68k_op_move_8_pi7_di(void); +void m68k_op_move_8_pi7_ix(void); +void m68k_op_move_8_pi7_aw(void); +void m68k_op_move_8_pi7_al(void); +void m68k_op_move_8_pi7_pcdi(void); +void m68k_op_move_8_pi7_pcix(void); +void m68k_op_move_8_pi7_i(void); +void m68k_op_move_8_pi_ai(void); +void m68k_op_move_8_pi_pi(void); +void m68k_op_move_8_pi_pi7(void); +void m68k_op_move_8_pi_pd(void); +void m68k_op_move_8_pi_pd7(void); +void m68k_op_move_8_pi_di(void); +void m68k_op_move_8_pi_ix(void); +void m68k_op_move_8_pi_aw(void); +void m68k_op_move_8_pi_al(void); +void m68k_op_move_8_pi_pcdi(void); +void m68k_op_move_8_pi_pcix(void); +void m68k_op_move_8_pi_i(void); +void m68k_op_move_8_pd7_d(void); +void m68k_op_move_8_pd_d(void); +void m68k_op_move_8_pd7_ai(void); +void m68k_op_move_8_pd7_pi(void); +void m68k_op_move_8_pd7_pi7(void); +void m68k_op_move_8_pd7_pd(void); +void m68k_op_move_8_pd7_pd7(void); +void m68k_op_move_8_pd7_di(void); +void m68k_op_move_8_pd7_ix(void); +void m68k_op_move_8_pd7_aw(void); +void m68k_op_move_8_pd7_al(void); +void m68k_op_move_8_pd7_pcdi(void); +void m68k_op_move_8_pd7_pcix(void); +void m68k_op_move_8_pd7_i(void); +void m68k_op_move_8_pd_ai(void); +void m68k_op_move_8_pd_pi(void); +void m68k_op_move_8_pd_pi7(void); +void m68k_op_move_8_pd_pd(void); +void m68k_op_move_8_pd_pd7(void); +void m68k_op_move_8_pd_di(void); +void m68k_op_move_8_pd_ix(void); +void m68k_op_move_8_pd_aw(void); +void m68k_op_move_8_pd_al(void); +void m68k_op_move_8_pd_pcdi(void); +void m68k_op_move_8_pd_pcix(void); +void m68k_op_move_8_pd_i(void); +void m68k_op_move_8_di_d(void); +void m68k_op_move_8_di_ai(void); +void m68k_op_move_8_di_pi(void); +void m68k_op_move_8_di_pi7(void); +void m68k_op_move_8_di_pd(void); +void m68k_op_move_8_di_pd7(void); +void m68k_op_move_8_di_di(void); +void m68k_op_move_8_di_ix(void); +void m68k_op_move_8_di_aw(void); +void m68k_op_move_8_di_al(void); +void m68k_op_move_8_di_pcdi(void); +void m68k_op_move_8_di_pcix(void); +void m68k_op_move_8_di_i(void); +void m68k_op_move_8_ix_d(void); +void m68k_op_move_8_ix_ai(void); +void m68k_op_move_8_ix_pi(void); +void m68k_op_move_8_ix_pi7(void); +void m68k_op_move_8_ix_pd(void); +void m68k_op_move_8_ix_pd7(void); +void m68k_op_move_8_ix_di(void); +void m68k_op_move_8_ix_ix(void); +void m68k_op_move_8_ix_aw(void); +void m68k_op_move_8_ix_al(void); +void m68k_op_move_8_ix_pcdi(void); +void m68k_op_move_8_ix_pcix(void); +void m68k_op_move_8_ix_i(void); +void m68k_op_move_8_aw_d(void); +void m68k_op_move_8_aw_ai(void); +void m68k_op_move_8_aw_pi(void); +void m68k_op_move_8_aw_pi7(void); +void m68k_op_move_8_aw_pd(void); +void m68k_op_move_8_aw_pd7(void); +void m68k_op_move_8_aw_di(void); +void m68k_op_move_8_aw_ix(void); +void m68k_op_move_8_aw_aw(void); +void m68k_op_move_8_aw_al(void); +void m68k_op_move_8_aw_pcdi(void); +void m68k_op_move_8_aw_pcix(void); +void m68k_op_move_8_aw_i(void); +void m68k_op_move_8_al_d(void); +void m68k_op_move_8_al_ai(void); +void m68k_op_move_8_al_pi(void); +void m68k_op_move_8_al_pi7(void); +void m68k_op_move_8_al_pd(void); +void m68k_op_move_8_al_pd7(void); +void m68k_op_move_8_al_di(void); +void m68k_op_move_8_al_ix(void); +void m68k_op_move_8_al_aw(void); +void m68k_op_move_8_al_al(void); +void m68k_op_move_8_al_pcdi(void); +void m68k_op_move_8_al_pcix(void); +void m68k_op_move_8_al_i(void); +void m68k_op_move_16_d_d(void); +void m68k_op_move_16_d_a(void); +void m68k_op_move_16_d_ai(void); +void m68k_op_move_16_d_pi(void); +void m68k_op_move_16_d_pd(void); +void m68k_op_move_16_d_di(void); +void m68k_op_move_16_d_ix(void); +void m68k_op_move_16_d_aw(void); +void m68k_op_move_16_d_al(void); +void m68k_op_move_16_d_pcdi(void); +void m68k_op_move_16_d_pcix(void); +void m68k_op_move_16_d_i(void); +void m68k_op_move_16_ai_d(void); +void m68k_op_move_16_ai_a(void); +void m68k_op_move_16_ai_ai(void); +void m68k_op_move_16_ai_pi(void); +void m68k_op_move_16_ai_pd(void); +void m68k_op_move_16_ai_di(void); +void m68k_op_move_16_ai_ix(void); +void m68k_op_move_16_ai_aw(void); +void m68k_op_move_16_ai_al(void); +void m68k_op_move_16_ai_pcdi(void); +void m68k_op_move_16_ai_pcix(void); +void m68k_op_move_16_ai_i(void); +void m68k_op_move_16_pi_d(void); +void m68k_op_move_16_pi_a(void); +void m68k_op_move_16_pi_ai(void); +void m68k_op_move_16_pi_pi(void); +void m68k_op_move_16_pi_pd(void); +void m68k_op_move_16_pi_di(void); +void m68k_op_move_16_pi_ix(void); +void m68k_op_move_16_pi_aw(void); +void m68k_op_move_16_pi_al(void); +void m68k_op_move_16_pi_pcdi(void); +void m68k_op_move_16_pi_pcix(void); +void m68k_op_move_16_pi_i(void); +void m68k_op_move_16_pd_d(void); +void m68k_op_move_16_pd_a(void); +void m68k_op_move_16_pd_ai(void); +void m68k_op_move_16_pd_pi(void); +void m68k_op_move_16_pd_pd(void); +void m68k_op_move_16_pd_di(void); +void m68k_op_move_16_pd_ix(void); +void m68k_op_move_16_pd_aw(void); +void m68k_op_move_16_pd_al(void); +void m68k_op_move_16_pd_pcdi(void); +void m68k_op_move_16_pd_pcix(void); +void m68k_op_move_16_pd_i(void); +void m68k_op_move_16_di_d(void); +void m68k_op_move_16_di_a(void); +void m68k_op_move_16_di_ai(void); +void m68k_op_move_16_di_pi(void); +void m68k_op_move_16_di_pd(void); +void m68k_op_move_16_di_di(void); +void m68k_op_move_16_di_ix(void); +void m68k_op_move_16_di_aw(void); +void m68k_op_move_16_di_al(void); +void m68k_op_move_16_di_pcdi(void); +void m68k_op_move_16_di_pcix(void); +void m68k_op_move_16_di_i(void); +void m68k_op_move_16_ix_d(void); +void m68k_op_move_16_ix_a(void); +void m68k_op_move_16_ix_ai(void); +void m68k_op_move_16_ix_pi(void); +void m68k_op_move_16_ix_pd(void); +void m68k_op_move_16_ix_di(void); +void m68k_op_move_16_ix_ix(void); +void m68k_op_move_16_ix_aw(void); +void m68k_op_move_16_ix_al(void); +void m68k_op_move_16_ix_pcdi(void); +void m68k_op_move_16_ix_pcix(void); +void m68k_op_move_16_ix_i(void); +void m68k_op_move_16_aw_d(void); +void m68k_op_move_16_aw_a(void); +void m68k_op_move_16_aw_ai(void); +void m68k_op_move_16_aw_pi(void); +void m68k_op_move_16_aw_pd(void); +void m68k_op_move_16_aw_di(void); +void m68k_op_move_16_aw_ix(void); +void m68k_op_move_16_aw_aw(void); +void m68k_op_move_16_aw_al(void); +void m68k_op_move_16_aw_pcdi(void); +void m68k_op_move_16_aw_pcix(void); +void m68k_op_move_16_aw_i(void); +void m68k_op_move_16_al_d(void); +void m68k_op_move_16_al_a(void); +void m68k_op_move_16_al_ai(void); +void m68k_op_move_16_al_pi(void); +void m68k_op_move_16_al_pd(void); +void m68k_op_move_16_al_di(void); +void m68k_op_move_16_al_ix(void); +void m68k_op_move_16_al_aw(void); +void m68k_op_move_16_al_al(void); +void m68k_op_move_16_al_pcdi(void); +void m68k_op_move_16_al_pcix(void); +void m68k_op_move_16_al_i(void); +void m68k_op_move_32_d_d(void); +void m68k_op_move_32_d_a(void); +void m68k_op_move_32_d_ai(void); +void m68k_op_move_32_d_pi(void); +void m68k_op_move_32_d_pd(void); +void m68k_op_move_32_d_di(void); +void m68k_op_move_32_d_ix(void); +void m68k_op_move_32_d_aw(void); +void m68k_op_move_32_d_al(void); +void m68k_op_move_32_d_pcdi(void); +void m68k_op_move_32_d_pcix(void); +void m68k_op_move_32_d_i(void); +void m68k_op_move_32_ai_d(void); +void m68k_op_move_32_ai_a(void); +void m68k_op_move_32_ai_ai(void); +void m68k_op_move_32_ai_pi(void); +void m68k_op_move_32_ai_pd(void); +void m68k_op_move_32_ai_di(void); +void m68k_op_move_32_ai_ix(void); +void m68k_op_move_32_ai_aw(void); +void m68k_op_move_32_ai_al(void); +void m68k_op_move_32_ai_pcdi(void); +void m68k_op_move_32_ai_pcix(void); +void m68k_op_move_32_ai_i(void); +void m68k_op_move_32_pi_d(void); +void m68k_op_move_32_pi_a(void); +void m68k_op_move_32_pi_ai(void); +void m68k_op_move_32_pi_pi(void); +void m68k_op_move_32_pi_pd(void); +void m68k_op_move_32_pi_di(void); +void m68k_op_move_32_pi_ix(void); +void m68k_op_move_32_pi_aw(void); +void m68k_op_move_32_pi_al(void); +void m68k_op_move_32_pi_pcdi(void); +void m68k_op_move_32_pi_pcix(void); +void m68k_op_move_32_pi_i(void); +void m68k_op_move_32_pd_d(void); +void m68k_op_move_32_pd_a(void); +void m68k_op_move_32_pd_ai(void); +void m68k_op_move_32_pd_pi(void); +void m68k_op_move_32_pd_pd(void); +void m68k_op_move_32_pd_di(void); +void m68k_op_move_32_pd_ix(void); +void m68k_op_move_32_pd_aw(void); +void m68k_op_move_32_pd_al(void); +void m68k_op_move_32_pd_pcdi(void); +void m68k_op_move_32_pd_pcix(void); +void m68k_op_move_32_pd_i(void); +void m68k_op_move_32_di_d(void); +void m68k_op_move_32_di_a(void); +void m68k_op_move_32_di_ai(void); +void m68k_op_move_32_di_pi(void); +void m68k_op_move_32_di_pd(void); +void m68k_op_move_32_di_di(void); +void m68k_op_move_32_di_ix(void); +void m68k_op_move_32_di_aw(void); +void m68k_op_move_32_di_al(void); +void m68k_op_move_32_di_pcdi(void); +void m68k_op_move_32_di_pcix(void); +void m68k_op_move_32_di_i(void); +void m68k_op_move_32_ix_d(void); +void m68k_op_move_32_ix_a(void); +void m68k_op_move_32_ix_ai(void); +void m68k_op_move_32_ix_pi(void); +void m68k_op_move_32_ix_pd(void); +void m68k_op_move_32_ix_di(void); +void m68k_op_move_32_ix_ix(void); +void m68k_op_move_32_ix_aw(void); +void m68k_op_move_32_ix_al(void); +void m68k_op_move_32_ix_pcdi(void); +void m68k_op_move_32_ix_pcix(void); +void m68k_op_move_32_ix_i(void); +void m68k_op_move_32_aw_d(void); +void m68k_op_move_32_aw_a(void); +void m68k_op_move_32_aw_ai(void); +void m68k_op_move_32_aw_pi(void); +void m68k_op_move_32_aw_pd(void); +void m68k_op_move_32_aw_di(void); +void m68k_op_move_32_aw_ix(void); +void m68k_op_move_32_aw_aw(void); +void m68k_op_move_32_aw_al(void); +void m68k_op_move_32_aw_pcdi(void); +void m68k_op_move_32_aw_pcix(void); +void m68k_op_move_32_aw_i(void); +void m68k_op_move_32_al_d(void); +void m68k_op_move_32_al_a(void); +void m68k_op_move_32_al_ai(void); +void m68k_op_move_32_al_pi(void); +void m68k_op_move_32_al_pd(void); +void m68k_op_move_32_al_di(void); +void m68k_op_move_32_al_ix(void); +void m68k_op_move_32_al_aw(void); +void m68k_op_move_32_al_al(void); +void m68k_op_move_32_al_pcdi(void); +void m68k_op_move_32_al_pcix(void); +void m68k_op_move_32_al_i(void); +void m68k_op_movea_16_d(void); +void m68k_op_movea_16_a(void); +void m68k_op_movea_16_ai(void); +void m68k_op_movea_16_pi(void); +void m68k_op_movea_16_pd(void); +void m68k_op_movea_16_di(void); +void m68k_op_movea_16_ix(void); +void m68k_op_movea_16_aw(void); +void m68k_op_movea_16_al(void); +void m68k_op_movea_16_pcdi(void); +void m68k_op_movea_16_pcix(void); +void m68k_op_movea_16_i(void); +void m68k_op_movea_32_d(void); +void m68k_op_movea_32_a(void); +void m68k_op_movea_32_ai(void); +void m68k_op_movea_32_pi(void); +void m68k_op_movea_32_pd(void); +void m68k_op_movea_32_di(void); +void m68k_op_movea_32_ix(void); +void m68k_op_movea_32_aw(void); +void m68k_op_movea_32_al(void); +void m68k_op_movea_32_pcdi(void); +void m68k_op_movea_32_pcix(void); +void m68k_op_movea_32_i(void); +void m68k_op_move_16_frc_d(void); +void m68k_op_move_16_frc_ai(void); +void m68k_op_move_16_frc_pi(void); +void m68k_op_move_16_frc_pd(void); +void m68k_op_move_16_frc_di(void); +void m68k_op_move_16_frc_ix(void); +void m68k_op_move_16_frc_aw(void); +void m68k_op_move_16_frc_al(void); +void m68k_op_move_16_toc_d(void); +void m68k_op_move_16_toc_ai(void); +void m68k_op_move_16_toc_pi(void); +void m68k_op_move_16_toc_pd(void); +void m68k_op_move_16_toc_di(void); +void m68k_op_move_16_toc_ix(void); +void m68k_op_move_16_toc_aw(void); +void m68k_op_move_16_toc_al(void); +void m68k_op_move_16_toc_pcdi(void); +void m68k_op_move_16_toc_pcix(void); +void m68k_op_move_16_toc_i(void); +void m68k_op_move_16_frs_d(void); +void m68k_op_move_16_frs_ai(void); +void m68k_op_move_16_frs_pi(void); +void m68k_op_move_16_frs_pd(void); +void m68k_op_move_16_frs_di(void); +void m68k_op_move_16_frs_ix(void); +void m68k_op_move_16_frs_aw(void); +void m68k_op_move_16_frs_al(void); +void m68k_op_move_16_tos_d(void); +void m68k_op_move_16_tos_ai(void); +void m68k_op_move_16_tos_pi(void); +void m68k_op_move_16_tos_pd(void); +void m68k_op_move_16_tos_di(void); +void m68k_op_move_16_tos_ix(void); +void m68k_op_move_16_tos_aw(void); +void m68k_op_move_16_tos_al(void); +void m68k_op_move_16_tos_pcdi(void); +void m68k_op_move_16_tos_pcix(void); +void m68k_op_move_16_tos_i(void); +void m68k_op_move_32_fru(void); +void m68k_op_move_32_tou(void); +void m68k_op_movec_32_cr(void); +void m68k_op_movec_32_rc(void); +void m68k_op_movem_16_re_pd(void); +void m68k_op_movem_16_re_ai(void); +void m68k_op_movem_16_re_di(void); +void m68k_op_movem_16_re_ix(void); +void m68k_op_movem_16_re_aw(void); +void m68k_op_movem_16_re_al(void); +void m68k_op_movem_32_re_pd(void); +void m68k_op_movem_32_re_ai(void); +void m68k_op_movem_32_re_di(void); +void m68k_op_movem_32_re_ix(void); +void m68k_op_movem_32_re_aw(void); +void m68k_op_movem_32_re_al(void); +void m68k_op_movem_16_er_pi(void); +void m68k_op_movem_16_er_ai(void); +void m68k_op_movem_16_er_di(void); +void m68k_op_movem_16_er_ix(void); +void m68k_op_movem_16_er_aw(void); +void m68k_op_movem_16_er_al(void); +void m68k_op_movem_16_er_pcdi(void); +void m68k_op_movem_16_er_pcix(void); +void m68k_op_movem_32_er_pi(void); +void m68k_op_movem_32_er_ai(void); +void m68k_op_movem_32_er_di(void); +void m68k_op_movem_32_er_ix(void); +void m68k_op_movem_32_er_aw(void); +void m68k_op_movem_32_er_al(void); +void m68k_op_movem_32_er_pcdi(void); +void m68k_op_movem_32_er_pcix(void); +void m68k_op_movep_16_re(void); +void m68k_op_movep_32_re(void); +void m68k_op_movep_16_er(void); +void m68k_op_movep_32_er(void); +void m68k_op_moves_8_ai(void); +void m68k_op_moves_8_pi(void); +void m68k_op_moves_8_pi7(void); +void m68k_op_moves_8_pd(void); +void m68k_op_moves_8_pd7(void); +void m68k_op_moves_8_di(void); +void m68k_op_moves_8_ix(void); +void m68k_op_moves_8_aw(void); +void m68k_op_moves_8_al(void); +void m68k_op_moves_16_ai(void); +void m68k_op_moves_16_pi(void); +void m68k_op_moves_16_pd(void); +void m68k_op_moves_16_di(void); +void m68k_op_moves_16_ix(void); +void m68k_op_moves_16_aw(void); +void m68k_op_moves_16_al(void); +void m68k_op_moves_32_ai(void); +void m68k_op_moves_32_pi(void); +void m68k_op_moves_32_pd(void); +void m68k_op_moves_32_di(void); +void m68k_op_moves_32_ix(void); +void m68k_op_moves_32_aw(void); +void m68k_op_moves_32_al(void); +void m68k_op_moveq_32(void); +void m68k_op_muls_16_d(void); +void m68k_op_muls_16_ai(void); +void m68k_op_muls_16_pi(void); +void m68k_op_muls_16_pd(void); +void m68k_op_muls_16_di(void); +void m68k_op_muls_16_ix(void); +void m68k_op_muls_16_aw(void); +void m68k_op_muls_16_al(void); +void m68k_op_muls_16_pcdi(void); +void m68k_op_muls_16_pcix(void); +void m68k_op_muls_16_i(void); +void m68k_op_mulu_16_d(void); +void m68k_op_mulu_16_ai(void); +void m68k_op_mulu_16_pi(void); +void m68k_op_mulu_16_pd(void); +void m68k_op_mulu_16_di(void); +void m68k_op_mulu_16_ix(void); +void m68k_op_mulu_16_aw(void); +void m68k_op_mulu_16_al(void); +void m68k_op_mulu_16_pcdi(void); +void m68k_op_mulu_16_pcix(void); +void m68k_op_mulu_16_i(void); +void m68k_op_mull_32_d(void); +void m68k_op_mull_32_ai(void); +void m68k_op_mull_32_pi(void); +void m68k_op_mull_32_pd(void); +void m68k_op_mull_32_di(void); +void m68k_op_mull_32_ix(void); +void m68k_op_mull_32_aw(void); +void m68k_op_mull_32_al(void); +void m68k_op_mull_32_pcdi(void); +void m68k_op_mull_32_pcix(void); +void m68k_op_mull_32_i(void); +void m68k_op_nbcd_8_d(void); +void m68k_op_nbcd_8_ai(void); +void m68k_op_nbcd_8_pi(void); +void m68k_op_nbcd_8_pi7(void); +void m68k_op_nbcd_8_pd(void); +void m68k_op_nbcd_8_pd7(void); +void m68k_op_nbcd_8_di(void); +void m68k_op_nbcd_8_ix(void); +void m68k_op_nbcd_8_aw(void); +void m68k_op_nbcd_8_al(void); +void m68k_op_neg_8_d(void); +void m68k_op_neg_8_ai(void); +void m68k_op_neg_8_pi(void); +void m68k_op_neg_8_pi7(void); +void m68k_op_neg_8_pd(void); +void m68k_op_neg_8_pd7(void); +void m68k_op_neg_8_di(void); +void m68k_op_neg_8_ix(void); +void m68k_op_neg_8_aw(void); +void m68k_op_neg_8_al(void); +void m68k_op_neg_16_d(void); +void m68k_op_neg_16_ai(void); +void m68k_op_neg_16_pi(void); +void m68k_op_neg_16_pd(void); +void m68k_op_neg_16_di(void); +void m68k_op_neg_16_ix(void); +void m68k_op_neg_16_aw(void); +void m68k_op_neg_16_al(void); +void m68k_op_neg_32_d(void); +void m68k_op_neg_32_ai(void); +void m68k_op_neg_32_pi(void); +void m68k_op_neg_32_pd(void); +void m68k_op_neg_32_di(void); +void m68k_op_neg_32_ix(void); +void m68k_op_neg_32_aw(void); +void m68k_op_neg_32_al(void); +void m68k_op_negx_8_d(void); +void m68k_op_negx_8_ai(void); +void m68k_op_negx_8_pi(void); +void m68k_op_negx_8_pi7(void); +void m68k_op_negx_8_pd(void); +void m68k_op_negx_8_pd7(void); +void m68k_op_negx_8_di(void); +void m68k_op_negx_8_ix(void); +void m68k_op_negx_8_aw(void); +void m68k_op_negx_8_al(void); +void m68k_op_negx_16_d(void); +void m68k_op_negx_16_ai(void); +void m68k_op_negx_16_pi(void); +void m68k_op_negx_16_pd(void); +void m68k_op_negx_16_di(void); +void m68k_op_negx_16_ix(void); +void m68k_op_negx_16_aw(void); +void m68k_op_negx_16_al(void); +void m68k_op_negx_32_d(void); +void m68k_op_negx_32_ai(void); +void m68k_op_negx_32_pi(void); +void m68k_op_negx_32_pd(void); +void m68k_op_negx_32_di(void); +void m68k_op_negx_32_ix(void); +void m68k_op_negx_32_aw(void); +void m68k_op_negx_32_al(void); +void m68k_op_nop(void); +void m68k_op_not_8_d(void); +void m68k_op_not_8_ai(void); +void m68k_op_not_8_pi(void); +void m68k_op_not_8_pi7(void); +void m68k_op_not_8_pd(void); +void m68k_op_not_8_pd7(void); +void m68k_op_not_8_di(void); +void m68k_op_not_8_ix(void); +void m68k_op_not_8_aw(void); +void m68k_op_not_8_al(void); +void m68k_op_not_16_d(void); +void m68k_op_not_16_ai(void); +void m68k_op_not_16_pi(void); +void m68k_op_not_16_pd(void); +void m68k_op_not_16_di(void); +void m68k_op_not_16_ix(void); +void m68k_op_not_16_aw(void); +void m68k_op_not_16_al(void); +void m68k_op_not_32_d(void); +void m68k_op_not_32_ai(void); +void m68k_op_not_32_pi(void); +void m68k_op_not_32_pd(void); +void m68k_op_not_32_di(void); +void m68k_op_not_32_ix(void); +void m68k_op_not_32_aw(void); +void m68k_op_not_32_al(void); +void m68k_op_or_8_er_d(void); +void m68k_op_or_8_er_ai(void); +void m68k_op_or_8_er_pi(void); +void m68k_op_or_8_er_pi7(void); +void m68k_op_or_8_er_pd(void); +void m68k_op_or_8_er_pd7(void); +void m68k_op_or_8_er_di(void); +void m68k_op_or_8_er_ix(void); +void m68k_op_or_8_er_aw(void); +void m68k_op_or_8_er_al(void); +void m68k_op_or_8_er_pcdi(void); +void m68k_op_or_8_er_pcix(void); +void m68k_op_or_8_er_i(void); +void m68k_op_or_16_er_d(void); +void m68k_op_or_16_er_ai(void); +void m68k_op_or_16_er_pi(void); +void m68k_op_or_16_er_pd(void); +void m68k_op_or_16_er_di(void); +void m68k_op_or_16_er_ix(void); +void m68k_op_or_16_er_aw(void); +void m68k_op_or_16_er_al(void); +void m68k_op_or_16_er_pcdi(void); +void m68k_op_or_16_er_pcix(void); +void m68k_op_or_16_er_i(void); +void m68k_op_or_32_er_d(void); +void m68k_op_or_32_er_ai(void); +void m68k_op_or_32_er_pi(void); +void m68k_op_or_32_er_pd(void); +void m68k_op_or_32_er_di(void); +void m68k_op_or_32_er_ix(void); +void m68k_op_or_32_er_aw(void); +void m68k_op_or_32_er_al(void); +void m68k_op_or_32_er_pcdi(void); +void m68k_op_or_32_er_pcix(void); +void m68k_op_or_32_er_i(void); +void m68k_op_or_8_re_ai(void); +void m68k_op_or_8_re_pi(void); +void m68k_op_or_8_re_pi7(void); +void m68k_op_or_8_re_pd(void); +void m68k_op_or_8_re_pd7(void); +void m68k_op_or_8_re_di(void); +void m68k_op_or_8_re_ix(void); +void m68k_op_or_8_re_aw(void); +void m68k_op_or_8_re_al(void); +void m68k_op_or_16_re_ai(void); +void m68k_op_or_16_re_pi(void); +void m68k_op_or_16_re_pd(void); +void m68k_op_or_16_re_di(void); +void m68k_op_or_16_re_ix(void); +void m68k_op_or_16_re_aw(void); +void m68k_op_or_16_re_al(void); +void m68k_op_or_32_re_ai(void); +void m68k_op_or_32_re_pi(void); +void m68k_op_or_32_re_pd(void); +void m68k_op_or_32_re_di(void); +void m68k_op_or_32_re_ix(void); +void m68k_op_or_32_re_aw(void); +void m68k_op_or_32_re_al(void); +void m68k_op_ori_8_d(void); +void m68k_op_ori_8_ai(void); +void m68k_op_ori_8_pi(void); +void m68k_op_ori_8_pi7(void); +void m68k_op_ori_8_pd(void); +void m68k_op_ori_8_pd7(void); +void m68k_op_ori_8_di(void); +void m68k_op_ori_8_ix(void); +void m68k_op_ori_8_aw(void); +void m68k_op_ori_8_al(void); +void m68k_op_ori_16_d(void); +void m68k_op_ori_16_ai(void); +void m68k_op_ori_16_pi(void); +void m68k_op_ori_16_pd(void); +void m68k_op_ori_16_di(void); +void m68k_op_ori_16_ix(void); +void m68k_op_ori_16_aw(void); +void m68k_op_ori_16_al(void); +void m68k_op_ori_32_d(void); +void m68k_op_ori_32_ai(void); +void m68k_op_ori_32_pi(void); +void m68k_op_ori_32_pd(void); +void m68k_op_ori_32_di(void); +void m68k_op_ori_32_ix(void); +void m68k_op_ori_32_aw(void); +void m68k_op_ori_32_al(void); +void m68k_op_ori_16_toc(void); +void m68k_op_ori_16_tos(void); +void m68k_op_pack_16_rr(void); +void m68k_op_pack_16_mm_ax7(void); +void m68k_op_pack_16_mm_ay7(void); +void m68k_op_pack_16_mm_axy7(void); +void m68k_op_pack_16_mm(void); +void m68k_op_pea_32_ai(void); +void m68k_op_pea_32_di(void); +void m68k_op_pea_32_ix(void); +void m68k_op_pea_32_aw(void); +void m68k_op_pea_32_al(void); +void m68k_op_pea_32_pcdi(void); +void m68k_op_pea_32_pcix(void); +void m68k_op_reset(void); +void m68k_op_ror_8_s(void); +void m68k_op_ror_16_s(void); +void m68k_op_ror_32_s(void); +void m68k_op_ror_8_r(void); +void m68k_op_ror_16_r(void); +void m68k_op_ror_32_r(void); +void m68k_op_ror_16_ai(void); +void m68k_op_ror_16_pi(void); +void m68k_op_ror_16_pd(void); +void m68k_op_ror_16_di(void); +void m68k_op_ror_16_ix(void); +void m68k_op_ror_16_aw(void); +void m68k_op_ror_16_al(void); +void m68k_op_rol_8_s(void); +void m68k_op_rol_16_s(void); +void m68k_op_rol_32_s(void); +void m68k_op_rol_8_r(void); +void m68k_op_rol_16_r(void); +void m68k_op_rol_32_r(void); +void m68k_op_rol_16_ai(void); +void m68k_op_rol_16_pi(void); +void m68k_op_rol_16_pd(void); +void m68k_op_rol_16_di(void); +void m68k_op_rol_16_ix(void); +void m68k_op_rol_16_aw(void); +void m68k_op_rol_16_al(void); +void m68k_op_roxr_8_s(void); +void m68k_op_roxr_16_s(void); +void m68k_op_roxr_32_s(void); +void m68k_op_roxr_8_r(void); +void m68k_op_roxr_16_r(void); +void m68k_op_roxr_32_r(void); +void m68k_op_roxr_16_ai(void); +void m68k_op_roxr_16_pi(void); +void m68k_op_roxr_16_pd(void); +void m68k_op_roxr_16_di(void); +void m68k_op_roxr_16_ix(void); +void m68k_op_roxr_16_aw(void); +void m68k_op_roxr_16_al(void); +void m68k_op_roxl_8_s(void); +void m68k_op_roxl_16_s(void); +void m68k_op_roxl_32_s(void); +void m68k_op_roxl_8_r(void); +void m68k_op_roxl_16_r(void); +void m68k_op_roxl_32_r(void); +void m68k_op_roxl_16_ai(void); +void m68k_op_roxl_16_pi(void); +void m68k_op_roxl_16_pd(void); +void m68k_op_roxl_16_di(void); +void m68k_op_roxl_16_ix(void); +void m68k_op_roxl_16_aw(void); +void m68k_op_roxl_16_al(void); +void m68k_op_rtd_32(void); +void m68k_op_rte_32(void); +void m68k_op_rtm_32(void); +void m68k_op_rtr_32(void); +void m68k_op_rts_32(void); +void m68k_op_sbcd_8_rr(void); +void m68k_op_sbcd_8_mm_ax7(void); +void m68k_op_sbcd_8_mm_ay7(void); +void m68k_op_sbcd_8_mm_axy7(void); +void m68k_op_sbcd_8_mm(void); +void m68k_op_st_8_d(void); +void m68k_op_st_8_ai(void); +void m68k_op_st_8_pi(void); +void m68k_op_st_8_pi7(void); +void m68k_op_st_8_pd(void); +void m68k_op_st_8_pd7(void); +void m68k_op_st_8_di(void); +void m68k_op_st_8_ix(void); +void m68k_op_st_8_aw(void); +void m68k_op_st_8_al(void); +void m68k_op_sf_8_d(void); +void m68k_op_sf_8_ai(void); +void m68k_op_sf_8_pi(void); +void m68k_op_sf_8_pi7(void); +void m68k_op_sf_8_pd(void); +void m68k_op_sf_8_pd7(void); +void m68k_op_sf_8_di(void); +void m68k_op_sf_8_ix(void); +void m68k_op_sf_8_aw(void); +void m68k_op_sf_8_al(void); +void m68k_op_shi_8_d(void); +void m68k_op_sls_8_d(void); +void m68k_op_scc_8_d(void); +void m68k_op_scs_8_d(void); +void m68k_op_sne_8_d(void); +void m68k_op_seq_8_d(void); +void m68k_op_svc_8_d(void); +void m68k_op_svs_8_d(void); +void m68k_op_spl_8_d(void); +void m68k_op_smi_8_d(void); +void m68k_op_sge_8_d(void); +void m68k_op_slt_8_d(void); +void m68k_op_sgt_8_d(void); +void m68k_op_sle_8_d(void); +void m68k_op_shi_8_ai(void); +void m68k_op_shi_8_pi(void); +void m68k_op_shi_8_pi7(void); +void m68k_op_shi_8_pd(void); +void m68k_op_shi_8_pd7(void); +void m68k_op_shi_8_di(void); +void m68k_op_shi_8_ix(void); +void m68k_op_shi_8_aw(void); +void m68k_op_shi_8_al(void); +void m68k_op_sls_8_ai(void); +void m68k_op_sls_8_pi(void); +void m68k_op_sls_8_pi7(void); +void m68k_op_sls_8_pd(void); +void m68k_op_sls_8_pd7(void); +void m68k_op_sls_8_di(void); +void m68k_op_sls_8_ix(void); +void m68k_op_sls_8_aw(void); +void m68k_op_sls_8_al(void); +void m68k_op_scc_8_ai(void); +void m68k_op_scc_8_pi(void); +void m68k_op_scc_8_pi7(void); +void m68k_op_scc_8_pd(void); +void m68k_op_scc_8_pd7(void); +void m68k_op_scc_8_di(void); +void m68k_op_scc_8_ix(void); +void m68k_op_scc_8_aw(void); +void m68k_op_scc_8_al(void); +void m68k_op_scs_8_ai(void); +void m68k_op_scs_8_pi(void); +void m68k_op_scs_8_pi7(void); +void m68k_op_scs_8_pd(void); +void m68k_op_scs_8_pd7(void); +void m68k_op_scs_8_di(void); +void m68k_op_scs_8_ix(void); +void m68k_op_scs_8_aw(void); +void m68k_op_scs_8_al(void); +void m68k_op_sne_8_ai(void); +void m68k_op_sne_8_pi(void); +void m68k_op_sne_8_pi7(void); +void m68k_op_sne_8_pd(void); +void m68k_op_sne_8_pd7(void); +void m68k_op_sne_8_di(void); +void m68k_op_sne_8_ix(void); +void m68k_op_sne_8_aw(void); +void m68k_op_sne_8_al(void); +void m68k_op_seq_8_ai(void); +void m68k_op_seq_8_pi(void); +void m68k_op_seq_8_pi7(void); +void m68k_op_seq_8_pd(void); +void m68k_op_seq_8_pd7(void); +void m68k_op_seq_8_di(void); +void m68k_op_seq_8_ix(void); +void m68k_op_seq_8_aw(void); +void m68k_op_seq_8_al(void); +void m68k_op_svc_8_ai(void); +void m68k_op_svc_8_pi(void); +void m68k_op_svc_8_pi7(void); +void m68k_op_svc_8_pd(void); +void m68k_op_svc_8_pd7(void); +void m68k_op_svc_8_di(void); +void m68k_op_svc_8_ix(void); +void m68k_op_svc_8_aw(void); +void m68k_op_svc_8_al(void); +void m68k_op_svs_8_ai(void); +void m68k_op_svs_8_pi(void); +void m68k_op_svs_8_pi7(void); +void m68k_op_svs_8_pd(void); +void m68k_op_svs_8_pd7(void); +void m68k_op_svs_8_di(void); +void m68k_op_svs_8_ix(void); +void m68k_op_svs_8_aw(void); +void m68k_op_svs_8_al(void); +void m68k_op_spl_8_ai(void); +void m68k_op_spl_8_pi(void); +void m68k_op_spl_8_pi7(void); +void m68k_op_spl_8_pd(void); +void m68k_op_spl_8_pd7(void); +void m68k_op_spl_8_di(void); +void m68k_op_spl_8_ix(void); +void m68k_op_spl_8_aw(void); +void m68k_op_spl_8_al(void); +void m68k_op_smi_8_ai(void); +void m68k_op_smi_8_pi(void); +void m68k_op_smi_8_pi7(void); +void m68k_op_smi_8_pd(void); +void m68k_op_smi_8_pd7(void); +void m68k_op_smi_8_di(void); +void m68k_op_smi_8_ix(void); +void m68k_op_smi_8_aw(void); +void m68k_op_smi_8_al(void); +void m68k_op_sge_8_ai(void); +void m68k_op_sge_8_pi(void); +void m68k_op_sge_8_pi7(void); +void m68k_op_sge_8_pd(void); +void m68k_op_sge_8_pd7(void); +void m68k_op_sge_8_di(void); +void m68k_op_sge_8_ix(void); +void m68k_op_sge_8_aw(void); +void m68k_op_sge_8_al(void); +void m68k_op_slt_8_ai(void); +void m68k_op_slt_8_pi(void); +void m68k_op_slt_8_pi7(void); +void m68k_op_slt_8_pd(void); +void m68k_op_slt_8_pd7(void); +void m68k_op_slt_8_di(void); +void m68k_op_slt_8_ix(void); +void m68k_op_slt_8_aw(void); +void m68k_op_slt_8_al(void); +void m68k_op_sgt_8_ai(void); +void m68k_op_sgt_8_pi(void); +void m68k_op_sgt_8_pi7(void); +void m68k_op_sgt_8_pd(void); +void m68k_op_sgt_8_pd7(void); +void m68k_op_sgt_8_di(void); +void m68k_op_sgt_8_ix(void); +void m68k_op_sgt_8_aw(void); +void m68k_op_sgt_8_al(void); +void m68k_op_sle_8_ai(void); +void m68k_op_sle_8_pi(void); +void m68k_op_sle_8_pi7(void); +void m68k_op_sle_8_pd(void); +void m68k_op_sle_8_pd7(void); +void m68k_op_sle_8_di(void); +void m68k_op_sle_8_ix(void); +void m68k_op_sle_8_aw(void); +void m68k_op_sle_8_al(void); +void m68k_op_stop(void); +void m68k_op_sub_8_er_d(void); +void m68k_op_sub_8_er_ai(void); +void m68k_op_sub_8_er_pi(void); +void m68k_op_sub_8_er_pi7(void); +void m68k_op_sub_8_er_pd(void); +void m68k_op_sub_8_er_pd7(void); +void m68k_op_sub_8_er_di(void); +void m68k_op_sub_8_er_ix(void); +void m68k_op_sub_8_er_aw(void); +void m68k_op_sub_8_er_al(void); +void m68k_op_sub_8_er_pcdi(void); +void m68k_op_sub_8_er_pcix(void); +void m68k_op_sub_8_er_i(void); +void m68k_op_sub_16_er_d(void); +void m68k_op_sub_16_er_a(void); +void m68k_op_sub_16_er_ai(void); +void m68k_op_sub_16_er_pi(void); +void m68k_op_sub_16_er_pd(void); +void m68k_op_sub_16_er_di(void); +void m68k_op_sub_16_er_ix(void); +void m68k_op_sub_16_er_aw(void); +void m68k_op_sub_16_er_al(void); +void m68k_op_sub_16_er_pcdi(void); +void m68k_op_sub_16_er_pcix(void); +void m68k_op_sub_16_er_i(void); +void m68k_op_sub_32_er_d(void); +void m68k_op_sub_32_er_a(void); +void m68k_op_sub_32_er_ai(void); +void m68k_op_sub_32_er_pi(void); +void m68k_op_sub_32_er_pd(void); +void m68k_op_sub_32_er_di(void); +void m68k_op_sub_32_er_ix(void); +void m68k_op_sub_32_er_aw(void); +void m68k_op_sub_32_er_al(void); +void m68k_op_sub_32_er_pcdi(void); +void m68k_op_sub_32_er_pcix(void); +void m68k_op_sub_32_er_i(void); +void m68k_op_sub_8_re_ai(void); +void m68k_op_sub_8_re_pi(void); +void m68k_op_sub_8_re_pi7(void); +void m68k_op_sub_8_re_pd(void); +void m68k_op_sub_8_re_pd7(void); +void m68k_op_sub_8_re_di(void); +void m68k_op_sub_8_re_ix(void); +void m68k_op_sub_8_re_aw(void); +void m68k_op_sub_8_re_al(void); +void m68k_op_sub_16_re_ai(void); +void m68k_op_sub_16_re_pi(void); +void m68k_op_sub_16_re_pd(void); +void m68k_op_sub_16_re_di(void); +void m68k_op_sub_16_re_ix(void); +void m68k_op_sub_16_re_aw(void); +void m68k_op_sub_16_re_al(void); +void m68k_op_sub_32_re_ai(void); +void m68k_op_sub_32_re_pi(void); +void m68k_op_sub_32_re_pd(void); +void m68k_op_sub_32_re_di(void); +void m68k_op_sub_32_re_ix(void); +void m68k_op_sub_32_re_aw(void); +void m68k_op_sub_32_re_al(void); +void m68k_op_suba_16_d(void); +void m68k_op_suba_16_a(void); +void m68k_op_suba_16_ai(void); +void m68k_op_suba_16_pi(void); +void m68k_op_suba_16_pd(void); +void m68k_op_suba_16_di(void); +void m68k_op_suba_16_ix(void); +void m68k_op_suba_16_aw(void); +void m68k_op_suba_16_al(void); +void m68k_op_suba_16_pcdi(void); +void m68k_op_suba_16_pcix(void); +void m68k_op_suba_16_i(void); +void m68k_op_suba_32_d(void); +void m68k_op_suba_32_a(void); +void m68k_op_suba_32_ai(void); +void m68k_op_suba_32_pi(void); +void m68k_op_suba_32_pd(void); +void m68k_op_suba_32_di(void); +void m68k_op_suba_32_ix(void); +void m68k_op_suba_32_aw(void); +void m68k_op_suba_32_al(void); +void m68k_op_suba_32_pcdi(void); +void m68k_op_suba_32_pcix(void); +void m68k_op_suba_32_i(void); +void m68k_op_subi_8_d(void); +void m68k_op_subi_8_ai(void); +void m68k_op_subi_8_pi(void); +void m68k_op_subi_8_pi7(void); +void m68k_op_subi_8_pd(void); +void m68k_op_subi_8_pd7(void); +void m68k_op_subi_8_di(void); +void m68k_op_subi_8_ix(void); +void m68k_op_subi_8_aw(void); +void m68k_op_subi_8_al(void); +void m68k_op_subi_16_d(void); +void m68k_op_subi_16_ai(void); +void m68k_op_subi_16_pi(void); +void m68k_op_subi_16_pd(void); +void m68k_op_subi_16_di(void); +void m68k_op_subi_16_ix(void); +void m68k_op_subi_16_aw(void); +void m68k_op_subi_16_al(void); +void m68k_op_subi_32_d(void); +void m68k_op_subi_32_ai(void); +void m68k_op_subi_32_pi(void); +void m68k_op_subi_32_pd(void); +void m68k_op_subi_32_di(void); +void m68k_op_subi_32_ix(void); +void m68k_op_subi_32_aw(void); +void m68k_op_subi_32_al(void); +void m68k_op_subq_8_d(void); +void m68k_op_subq_8_ai(void); +void m68k_op_subq_8_pi(void); +void m68k_op_subq_8_pi7(void); +void m68k_op_subq_8_pd(void); +void m68k_op_subq_8_pd7(void); +void m68k_op_subq_8_di(void); +void m68k_op_subq_8_ix(void); +void m68k_op_subq_8_aw(void); +void m68k_op_subq_8_al(void); +void m68k_op_subq_16_d(void); +void m68k_op_subq_16_a(void); +void m68k_op_subq_16_ai(void); +void m68k_op_subq_16_pi(void); +void m68k_op_subq_16_pd(void); +void m68k_op_subq_16_di(void); +void m68k_op_subq_16_ix(void); +void m68k_op_subq_16_aw(void); +void m68k_op_subq_16_al(void); +void m68k_op_subq_32_d(void); +void m68k_op_subq_32_a(void); +void m68k_op_subq_32_ai(void); +void m68k_op_subq_32_pi(void); +void m68k_op_subq_32_pd(void); +void m68k_op_subq_32_di(void); +void m68k_op_subq_32_ix(void); +void m68k_op_subq_32_aw(void); +void m68k_op_subq_32_al(void); +void m68k_op_subx_8_rr(void); +void m68k_op_subx_16_rr(void); +void m68k_op_subx_32_rr(void); +void m68k_op_subx_8_mm_ax7(void); +void m68k_op_subx_8_mm_ay7(void); +void m68k_op_subx_8_mm_axy7(void); +void m68k_op_subx_8_mm(void); +void m68k_op_subx_16_mm(void); +void m68k_op_subx_32_mm(void); +void m68k_op_swap_32(void); +void m68k_op_tas_8_d(void); +void m68k_op_tas_8_ai(void); +void m68k_op_tas_8_pi(void); +void m68k_op_tas_8_pi7(void); +void m68k_op_tas_8_pd(void); +void m68k_op_tas_8_pd7(void); +void m68k_op_tas_8_di(void); +void m68k_op_tas_8_ix(void); +void m68k_op_tas_8_aw(void); +void m68k_op_tas_8_al(void); +void m68k_op_trap(void); +void m68k_op_trapt(void); +void m68k_op_trapt_16(void); +void m68k_op_trapt_32(void); +void m68k_op_trapf(void); +void m68k_op_trapf_16(void); +void m68k_op_trapf_32(void); +void m68k_op_traphi(void); +void m68k_op_trapls(void); +void m68k_op_trapcc(void); +void m68k_op_trapcs(void); +void m68k_op_trapne(void); +void m68k_op_trapeq(void); +void m68k_op_trapvc(void); +void m68k_op_trapvs(void); +void m68k_op_trappl(void); +void m68k_op_trapmi(void); +void m68k_op_trapge(void); +void m68k_op_traplt(void); +void m68k_op_trapgt(void); +void m68k_op_traple(void); +void m68k_op_traphi_16(void); +void m68k_op_trapls_16(void); +void m68k_op_trapcc_16(void); +void m68k_op_trapcs_16(void); +void m68k_op_trapne_16(void); +void m68k_op_trapeq_16(void); +void m68k_op_trapvc_16(void); +void m68k_op_trapvs_16(void); +void m68k_op_trappl_16(void); +void m68k_op_trapmi_16(void); +void m68k_op_trapge_16(void); +void m68k_op_traplt_16(void); +void m68k_op_trapgt_16(void); +void m68k_op_traple_16(void); +void m68k_op_traphi_32(void); +void m68k_op_trapls_32(void); +void m68k_op_trapcc_32(void); +void m68k_op_trapcs_32(void); +void m68k_op_trapne_32(void); +void m68k_op_trapeq_32(void); +void m68k_op_trapvc_32(void); +void m68k_op_trapvs_32(void); +void m68k_op_trappl_32(void); +void m68k_op_trapmi_32(void); +void m68k_op_trapge_32(void); +void m68k_op_traplt_32(void); +void m68k_op_trapgt_32(void); +void m68k_op_traple_32(void); +void m68k_op_trapv(void); +void m68k_op_tst_8_d(void); +void m68k_op_tst_8_ai(void); +void m68k_op_tst_8_pi(void); +void m68k_op_tst_8_pi7(void); +void m68k_op_tst_8_pd(void); +void m68k_op_tst_8_pd7(void); +void m68k_op_tst_8_di(void); +void m68k_op_tst_8_ix(void); +void m68k_op_tst_8_aw(void); +void m68k_op_tst_8_al(void); +void m68k_op_tst_8_pcdi(void); +void m68k_op_tst_8_pcix(void); +void m68k_op_tst_8_i(void); +void m68k_op_tst_16_d(void); +void m68k_op_tst_16_a(void); +void m68k_op_tst_16_ai(void); +void m68k_op_tst_16_pi(void); +void m68k_op_tst_16_pd(void); +void m68k_op_tst_16_di(void); +void m68k_op_tst_16_ix(void); +void m68k_op_tst_16_aw(void); +void m68k_op_tst_16_al(void); +void m68k_op_tst_16_pcdi(void); +void m68k_op_tst_16_pcix(void); +void m68k_op_tst_16_i(void); +void m68k_op_tst_32_d(void); +void m68k_op_tst_32_a(void); +void m68k_op_tst_32_ai(void); +void m68k_op_tst_32_pi(void); +void m68k_op_tst_32_pd(void); +void m68k_op_tst_32_di(void); +void m68k_op_tst_32_ix(void); +void m68k_op_tst_32_aw(void); +void m68k_op_tst_32_al(void); +void m68k_op_tst_32_pcdi(void); +void m68k_op_tst_32_pcix(void); +void m68k_op_tst_32_i(void); +void m68k_op_unlk_32_a7(void); +void m68k_op_unlk_32(void); +void m68k_op_unpk_16_rr(void); +void m68k_op_unpk_16_mm_ax7(void); +void m68k_op_unpk_16_mm_ay7(void); +void m68k_op_unpk_16_mm_axy7(void); +void m68k_op_unpk_16_mm(void); +/* Build the opcode handler table */ +void m68ki_build_opcode_table(void); + +extern const void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */ +extern const unsigned char m68ki_cycles[1][0x10000]; + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68KOPS__HEADER */ + + diff --git a/MCUME_teensy/teensygen/m68kops_pre.c b/MCUME_teensy/teensygen/m68kops_pre.c new file mode 100644 index 0000000..b9f7865 --- /dev/null +++ b/MCUME_teensy/teensygen/m68kops_pre.c @@ -0,0 +1,65546 @@ +#include "m68kops.h" +#include "arduinoproto.h" + +//Opcodes are built on the host, this does not need to do anything. +void m68ki_build_opcode_table() {} + +PROGMEM const void (*m68ki_instruction_jump_table[0x10000])(void) ={ + (void*)m68k_op_ori_8_d , + (void*)m68k_op_ori_8_d , + (void*)m68k_op_ori_8_d , + (void*)m68k_op_ori_8_d , + (void*)m68k_op_ori_8_d , + (void*)m68k_op_ori_8_d , + (void*)m68k_op_ori_8_d , + (void*)m68k_op_ori_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ori_8_ai , + (void*)m68k_op_ori_8_ai , + (void*)m68k_op_ori_8_ai , + (void*)m68k_op_ori_8_ai , + (void*)m68k_op_ori_8_ai , + (void*)m68k_op_ori_8_ai , + (void*)m68k_op_ori_8_ai , + (void*)m68k_op_ori_8_ai , + (void*)m68k_op_ori_8_pi , + (void*)m68k_op_ori_8_pi , + (void*)m68k_op_ori_8_pi , + (void*)m68k_op_ori_8_pi , + (void*)m68k_op_ori_8_pi , + (void*)m68k_op_ori_8_pi , + (void*)m68k_op_ori_8_pi , + (void*)m68k_op_ori_8_pi7 , + (void*)m68k_op_ori_8_pd , + (void*)m68k_op_ori_8_pd , + (void*)m68k_op_ori_8_pd , + (void*)m68k_op_ori_8_pd , + (void*)m68k_op_ori_8_pd , + (void*)m68k_op_ori_8_pd , + (void*)m68k_op_ori_8_pd , + (void*)m68k_op_ori_8_pd7 , + (void*)m68k_op_ori_8_di , + (void*)m68k_op_ori_8_di , + (void*)m68k_op_ori_8_di , + (void*)m68k_op_ori_8_di , + (void*)m68k_op_ori_8_di , + (void*)m68k_op_ori_8_di , + (void*)m68k_op_ori_8_di , + (void*)m68k_op_ori_8_di , + (void*)m68k_op_ori_8_ix , + (void*)m68k_op_ori_8_ix , + (void*)m68k_op_ori_8_ix , + (void*)m68k_op_ori_8_ix , + (void*)m68k_op_ori_8_ix , + (void*)m68k_op_ori_8_ix , + (void*)m68k_op_ori_8_ix , + (void*)m68k_op_ori_8_ix , + (void*)m68k_op_ori_8_aw , + (void*)m68k_op_ori_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ori_16_toc , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ori_16_d , + (void*)m68k_op_ori_16_d , + (void*)m68k_op_ori_16_d , + (void*)m68k_op_ori_16_d , + (void*)m68k_op_ori_16_d , + (void*)m68k_op_ori_16_d , + (void*)m68k_op_ori_16_d , + (void*)m68k_op_ori_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ori_16_ai , + (void*)m68k_op_ori_16_ai , + (void*)m68k_op_ori_16_ai , + (void*)m68k_op_ori_16_ai , + (void*)m68k_op_ori_16_ai , + (void*)m68k_op_ori_16_ai , + (void*)m68k_op_ori_16_ai , + (void*)m68k_op_ori_16_ai , + (void*)m68k_op_ori_16_pi , + (void*)m68k_op_ori_16_pi , + (void*)m68k_op_ori_16_pi , + (void*)m68k_op_ori_16_pi , + (void*)m68k_op_ori_16_pi , + (void*)m68k_op_ori_16_pi , + (void*)m68k_op_ori_16_pi , + (void*)m68k_op_ori_16_pi , + (void*)m68k_op_ori_16_pd , + (void*)m68k_op_ori_16_pd , + (void*)m68k_op_ori_16_pd , + (void*)m68k_op_ori_16_pd , + (void*)m68k_op_ori_16_pd , + (void*)m68k_op_ori_16_pd , + (void*)m68k_op_ori_16_pd , + (void*)m68k_op_ori_16_pd , + (void*)m68k_op_ori_16_di , + (void*)m68k_op_ori_16_di , + (void*)m68k_op_ori_16_di , + (void*)m68k_op_ori_16_di , + (void*)m68k_op_ori_16_di , + (void*)m68k_op_ori_16_di , + (void*)m68k_op_ori_16_di , + (void*)m68k_op_ori_16_di , + (void*)m68k_op_ori_16_ix , + (void*)m68k_op_ori_16_ix , + (void*)m68k_op_ori_16_ix , + (void*)m68k_op_ori_16_ix , + (void*)m68k_op_ori_16_ix , + (void*)m68k_op_ori_16_ix , + (void*)m68k_op_ori_16_ix , + (void*)m68k_op_ori_16_ix , + (void*)m68k_op_ori_16_aw , + (void*)m68k_op_ori_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ori_16_tos , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ori_32_d , + (void*)m68k_op_ori_32_d , + (void*)m68k_op_ori_32_d , + (void*)m68k_op_ori_32_d , + (void*)m68k_op_ori_32_d , + (void*)m68k_op_ori_32_d , + (void*)m68k_op_ori_32_d , + (void*)m68k_op_ori_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ori_32_ai , + (void*)m68k_op_ori_32_ai , + (void*)m68k_op_ori_32_ai , + (void*)m68k_op_ori_32_ai , + (void*)m68k_op_ori_32_ai , + (void*)m68k_op_ori_32_ai , + (void*)m68k_op_ori_32_ai , + (void*)m68k_op_ori_32_ai , + (void*)m68k_op_ori_32_pi , + (void*)m68k_op_ori_32_pi , + (void*)m68k_op_ori_32_pi , + (void*)m68k_op_ori_32_pi , + (void*)m68k_op_ori_32_pi , + (void*)m68k_op_ori_32_pi , + (void*)m68k_op_ori_32_pi , + (void*)m68k_op_ori_32_pi , + (void*)m68k_op_ori_32_pd , + (void*)m68k_op_ori_32_pd , + (void*)m68k_op_ori_32_pd , + (void*)m68k_op_ori_32_pd , + (void*)m68k_op_ori_32_pd , + (void*)m68k_op_ori_32_pd , + (void*)m68k_op_ori_32_pd , + (void*)m68k_op_ori_32_pd , + (void*)m68k_op_ori_32_di , + (void*)m68k_op_ori_32_di , + (void*)m68k_op_ori_32_di , + (void*)m68k_op_ori_32_di , + (void*)m68k_op_ori_32_di , + (void*)m68k_op_ori_32_di , + (void*)m68k_op_ori_32_di , + (void*)m68k_op_ori_32_di , + (void*)m68k_op_ori_32_ix , + (void*)m68k_op_ori_32_ix , + (void*)m68k_op_ori_32_ix , + (void*)m68k_op_ori_32_ix , + (void*)m68k_op_ori_32_ix , + (void*)m68k_op_ori_32_ix , + (void*)m68k_op_ori_32_ix , + (void*)m68k_op_ori_32_ix , + (void*)m68k_op_ori_32_aw , + (void*)m68k_op_ori_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk2cmp2_8_ai , + (void*)m68k_op_chk2cmp2_8_ai , + (void*)m68k_op_chk2cmp2_8_ai , + (void*)m68k_op_chk2cmp2_8_ai , + (void*)m68k_op_chk2cmp2_8_ai , + (void*)m68k_op_chk2cmp2_8_ai , + (void*)m68k_op_chk2cmp2_8_ai , + (void*)m68k_op_chk2cmp2_8_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk2cmp2_8_di , + (void*)m68k_op_chk2cmp2_8_di , + (void*)m68k_op_chk2cmp2_8_di , + (void*)m68k_op_chk2cmp2_8_di , + (void*)m68k_op_chk2cmp2_8_di , + (void*)m68k_op_chk2cmp2_8_di , + (void*)m68k_op_chk2cmp2_8_di , + (void*)m68k_op_chk2cmp2_8_di , + (void*)m68k_op_chk2cmp2_8_ix , + (void*)m68k_op_chk2cmp2_8_ix , + (void*)m68k_op_chk2cmp2_8_ix , + (void*)m68k_op_chk2cmp2_8_ix , + (void*)m68k_op_chk2cmp2_8_ix , + (void*)m68k_op_chk2cmp2_8_ix , + (void*)m68k_op_chk2cmp2_8_ix , + (void*)m68k_op_chk2cmp2_8_ix , + (void*)m68k_op_chk2cmp2_8_aw , + (void*)m68k_op_chk2cmp2_8_al , + (void*)m68k_op_chk2cmp2_8_pcdi , + (void*)m68k_op_chk2cmp2_8_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi7 , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd7 , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_aw , + (void*)m68k_op_btst_8_r_al , + (void*)m68k_op_btst_8_r_pcdi , + (void*)m68k_op_btst_8_r_pcix , + (void*)m68k_op_btst_8_r_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi7 , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd7 , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_aw , + (void*)m68k_op_bchg_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi7 , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd7 , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_aw , + (void*)m68k_op_bclr_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi7 , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd7 , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_aw , + (void*)m68k_op_bset_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_andi_8_d , + (void*)m68k_op_andi_8_d , + (void*)m68k_op_andi_8_d , + (void*)m68k_op_andi_8_d , + (void*)m68k_op_andi_8_d , + (void*)m68k_op_andi_8_d , + (void*)m68k_op_andi_8_d , + (void*)m68k_op_andi_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_andi_8_ai , + (void*)m68k_op_andi_8_ai , + (void*)m68k_op_andi_8_ai , + (void*)m68k_op_andi_8_ai , + (void*)m68k_op_andi_8_ai , + (void*)m68k_op_andi_8_ai , + (void*)m68k_op_andi_8_ai , + (void*)m68k_op_andi_8_ai , + (void*)m68k_op_andi_8_pi , + (void*)m68k_op_andi_8_pi , + (void*)m68k_op_andi_8_pi , + (void*)m68k_op_andi_8_pi , + (void*)m68k_op_andi_8_pi , + (void*)m68k_op_andi_8_pi , + (void*)m68k_op_andi_8_pi , + (void*)m68k_op_andi_8_pi7 , + (void*)m68k_op_andi_8_pd , + (void*)m68k_op_andi_8_pd , + (void*)m68k_op_andi_8_pd , + (void*)m68k_op_andi_8_pd , + (void*)m68k_op_andi_8_pd , + (void*)m68k_op_andi_8_pd , + (void*)m68k_op_andi_8_pd , + (void*)m68k_op_andi_8_pd7 , + (void*)m68k_op_andi_8_di , + (void*)m68k_op_andi_8_di , + (void*)m68k_op_andi_8_di , + (void*)m68k_op_andi_8_di , + (void*)m68k_op_andi_8_di , + (void*)m68k_op_andi_8_di , + (void*)m68k_op_andi_8_di , + (void*)m68k_op_andi_8_di , + (void*)m68k_op_andi_8_ix , + (void*)m68k_op_andi_8_ix , + (void*)m68k_op_andi_8_ix , + (void*)m68k_op_andi_8_ix , + (void*)m68k_op_andi_8_ix , + (void*)m68k_op_andi_8_ix , + (void*)m68k_op_andi_8_ix , + (void*)m68k_op_andi_8_ix , + (void*)m68k_op_andi_8_aw , + (void*)m68k_op_andi_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_andi_16_toc , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_andi_16_d , + (void*)m68k_op_andi_16_d , + (void*)m68k_op_andi_16_d , + (void*)m68k_op_andi_16_d , + (void*)m68k_op_andi_16_d , + (void*)m68k_op_andi_16_d , + (void*)m68k_op_andi_16_d , + (void*)m68k_op_andi_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_andi_16_ai , + (void*)m68k_op_andi_16_ai , + (void*)m68k_op_andi_16_ai , + (void*)m68k_op_andi_16_ai , + (void*)m68k_op_andi_16_ai , + (void*)m68k_op_andi_16_ai , + (void*)m68k_op_andi_16_ai , + (void*)m68k_op_andi_16_ai , + (void*)m68k_op_andi_16_pi , + (void*)m68k_op_andi_16_pi , + (void*)m68k_op_andi_16_pi , + (void*)m68k_op_andi_16_pi , + (void*)m68k_op_andi_16_pi , + (void*)m68k_op_andi_16_pi , + (void*)m68k_op_andi_16_pi , + (void*)m68k_op_andi_16_pi , + (void*)m68k_op_andi_16_pd , + (void*)m68k_op_andi_16_pd , + (void*)m68k_op_andi_16_pd , + (void*)m68k_op_andi_16_pd , + (void*)m68k_op_andi_16_pd , + (void*)m68k_op_andi_16_pd , + (void*)m68k_op_andi_16_pd , + (void*)m68k_op_andi_16_pd , + (void*)m68k_op_andi_16_di , + (void*)m68k_op_andi_16_di , + (void*)m68k_op_andi_16_di , + (void*)m68k_op_andi_16_di , + (void*)m68k_op_andi_16_di , + (void*)m68k_op_andi_16_di , + (void*)m68k_op_andi_16_di , + (void*)m68k_op_andi_16_di , + (void*)m68k_op_andi_16_ix , + (void*)m68k_op_andi_16_ix , + (void*)m68k_op_andi_16_ix , + (void*)m68k_op_andi_16_ix , + (void*)m68k_op_andi_16_ix , + (void*)m68k_op_andi_16_ix , + (void*)m68k_op_andi_16_ix , + (void*)m68k_op_andi_16_ix , + (void*)m68k_op_andi_16_aw , + (void*)m68k_op_andi_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_andi_16_tos , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_andi_32_d , + (void*)m68k_op_andi_32_d , + (void*)m68k_op_andi_32_d , + (void*)m68k_op_andi_32_d , + (void*)m68k_op_andi_32_d , + (void*)m68k_op_andi_32_d , + (void*)m68k_op_andi_32_d , + (void*)m68k_op_andi_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_andi_32_ai , + (void*)m68k_op_andi_32_ai , + (void*)m68k_op_andi_32_ai , + (void*)m68k_op_andi_32_ai , + (void*)m68k_op_andi_32_ai , + (void*)m68k_op_andi_32_ai , + (void*)m68k_op_andi_32_ai , + (void*)m68k_op_andi_32_ai , + (void*)m68k_op_andi_32_pi , + (void*)m68k_op_andi_32_pi , + (void*)m68k_op_andi_32_pi , + (void*)m68k_op_andi_32_pi , + (void*)m68k_op_andi_32_pi , + (void*)m68k_op_andi_32_pi , + (void*)m68k_op_andi_32_pi , + (void*)m68k_op_andi_32_pi , + (void*)m68k_op_andi_32_pd , + (void*)m68k_op_andi_32_pd , + (void*)m68k_op_andi_32_pd , + (void*)m68k_op_andi_32_pd , + (void*)m68k_op_andi_32_pd , + (void*)m68k_op_andi_32_pd , + (void*)m68k_op_andi_32_pd , + (void*)m68k_op_andi_32_pd , + (void*)m68k_op_andi_32_di , + (void*)m68k_op_andi_32_di , + (void*)m68k_op_andi_32_di , + (void*)m68k_op_andi_32_di , + (void*)m68k_op_andi_32_di , + (void*)m68k_op_andi_32_di , + (void*)m68k_op_andi_32_di , + (void*)m68k_op_andi_32_di , + (void*)m68k_op_andi_32_ix , + (void*)m68k_op_andi_32_ix , + (void*)m68k_op_andi_32_ix , + (void*)m68k_op_andi_32_ix , + (void*)m68k_op_andi_32_ix , + (void*)m68k_op_andi_32_ix , + (void*)m68k_op_andi_32_ix , + (void*)m68k_op_andi_32_ix , + (void*)m68k_op_andi_32_aw , + (void*)m68k_op_andi_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk2cmp2_16_ai , + (void*)m68k_op_chk2cmp2_16_ai , + (void*)m68k_op_chk2cmp2_16_ai , + (void*)m68k_op_chk2cmp2_16_ai , + (void*)m68k_op_chk2cmp2_16_ai , + (void*)m68k_op_chk2cmp2_16_ai , + (void*)m68k_op_chk2cmp2_16_ai , + (void*)m68k_op_chk2cmp2_16_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk2cmp2_16_di , + (void*)m68k_op_chk2cmp2_16_di , + (void*)m68k_op_chk2cmp2_16_di , + (void*)m68k_op_chk2cmp2_16_di , + (void*)m68k_op_chk2cmp2_16_di , + (void*)m68k_op_chk2cmp2_16_di , + (void*)m68k_op_chk2cmp2_16_di , + (void*)m68k_op_chk2cmp2_16_di , + (void*)m68k_op_chk2cmp2_16_ix , + (void*)m68k_op_chk2cmp2_16_ix , + (void*)m68k_op_chk2cmp2_16_ix , + (void*)m68k_op_chk2cmp2_16_ix , + (void*)m68k_op_chk2cmp2_16_ix , + (void*)m68k_op_chk2cmp2_16_ix , + (void*)m68k_op_chk2cmp2_16_ix , + (void*)m68k_op_chk2cmp2_16_ix , + (void*)m68k_op_chk2cmp2_16_aw , + (void*)m68k_op_chk2cmp2_16_al , + (void*)m68k_op_chk2cmp2_16_pcdi , + (void*)m68k_op_chk2cmp2_16_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi7 , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd7 , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_aw , + (void*)m68k_op_btst_8_r_al , + (void*)m68k_op_btst_8_r_pcdi , + (void*)m68k_op_btst_8_r_pcix , + (void*)m68k_op_btst_8_r_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi7 , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd7 , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_aw , + (void*)m68k_op_bchg_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi7 , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd7 , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_aw , + (void*)m68k_op_bclr_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi7 , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd7 , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_aw , + (void*)m68k_op_bset_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subi_8_d , + (void*)m68k_op_subi_8_d , + (void*)m68k_op_subi_8_d , + (void*)m68k_op_subi_8_d , + (void*)m68k_op_subi_8_d , + (void*)m68k_op_subi_8_d , + (void*)m68k_op_subi_8_d , + (void*)m68k_op_subi_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subi_8_ai , + (void*)m68k_op_subi_8_ai , + (void*)m68k_op_subi_8_ai , + (void*)m68k_op_subi_8_ai , + (void*)m68k_op_subi_8_ai , + (void*)m68k_op_subi_8_ai , + (void*)m68k_op_subi_8_ai , + (void*)m68k_op_subi_8_ai , + (void*)m68k_op_subi_8_pi , + (void*)m68k_op_subi_8_pi , + (void*)m68k_op_subi_8_pi , + (void*)m68k_op_subi_8_pi , + (void*)m68k_op_subi_8_pi , + (void*)m68k_op_subi_8_pi , + (void*)m68k_op_subi_8_pi , + (void*)m68k_op_subi_8_pi7 , + (void*)m68k_op_subi_8_pd , + (void*)m68k_op_subi_8_pd , + (void*)m68k_op_subi_8_pd , + (void*)m68k_op_subi_8_pd , + (void*)m68k_op_subi_8_pd , + (void*)m68k_op_subi_8_pd , + (void*)m68k_op_subi_8_pd , + (void*)m68k_op_subi_8_pd7 , + (void*)m68k_op_subi_8_di , + (void*)m68k_op_subi_8_di , + (void*)m68k_op_subi_8_di , + (void*)m68k_op_subi_8_di , + (void*)m68k_op_subi_8_di , + (void*)m68k_op_subi_8_di , + (void*)m68k_op_subi_8_di , + (void*)m68k_op_subi_8_di , + (void*)m68k_op_subi_8_ix , + (void*)m68k_op_subi_8_ix , + (void*)m68k_op_subi_8_ix , + (void*)m68k_op_subi_8_ix , + (void*)m68k_op_subi_8_ix , + (void*)m68k_op_subi_8_ix , + (void*)m68k_op_subi_8_ix , + (void*)m68k_op_subi_8_ix , + (void*)m68k_op_subi_8_aw , + (void*)m68k_op_subi_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subi_16_d , + (void*)m68k_op_subi_16_d , + (void*)m68k_op_subi_16_d , + (void*)m68k_op_subi_16_d , + (void*)m68k_op_subi_16_d , + (void*)m68k_op_subi_16_d , + (void*)m68k_op_subi_16_d , + (void*)m68k_op_subi_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subi_16_ai , + (void*)m68k_op_subi_16_ai , + (void*)m68k_op_subi_16_ai , + (void*)m68k_op_subi_16_ai , + (void*)m68k_op_subi_16_ai , + (void*)m68k_op_subi_16_ai , + (void*)m68k_op_subi_16_ai , + (void*)m68k_op_subi_16_ai , + (void*)m68k_op_subi_16_pi , + (void*)m68k_op_subi_16_pi , + (void*)m68k_op_subi_16_pi , + (void*)m68k_op_subi_16_pi , + (void*)m68k_op_subi_16_pi , + (void*)m68k_op_subi_16_pi , + (void*)m68k_op_subi_16_pi , + (void*)m68k_op_subi_16_pi , + (void*)m68k_op_subi_16_pd , + (void*)m68k_op_subi_16_pd , + (void*)m68k_op_subi_16_pd , + (void*)m68k_op_subi_16_pd , + (void*)m68k_op_subi_16_pd , + (void*)m68k_op_subi_16_pd , + (void*)m68k_op_subi_16_pd , + (void*)m68k_op_subi_16_pd , + (void*)m68k_op_subi_16_di , + (void*)m68k_op_subi_16_di , + (void*)m68k_op_subi_16_di , + (void*)m68k_op_subi_16_di , + (void*)m68k_op_subi_16_di , + (void*)m68k_op_subi_16_di , + (void*)m68k_op_subi_16_di , + (void*)m68k_op_subi_16_di , + (void*)m68k_op_subi_16_ix , + (void*)m68k_op_subi_16_ix , + (void*)m68k_op_subi_16_ix , + (void*)m68k_op_subi_16_ix , + (void*)m68k_op_subi_16_ix , + (void*)m68k_op_subi_16_ix , + (void*)m68k_op_subi_16_ix , + (void*)m68k_op_subi_16_ix , + (void*)m68k_op_subi_16_aw , + (void*)m68k_op_subi_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subi_32_d , + (void*)m68k_op_subi_32_d , + (void*)m68k_op_subi_32_d , + (void*)m68k_op_subi_32_d , + (void*)m68k_op_subi_32_d , + (void*)m68k_op_subi_32_d , + (void*)m68k_op_subi_32_d , + (void*)m68k_op_subi_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subi_32_ai , + (void*)m68k_op_subi_32_ai , + (void*)m68k_op_subi_32_ai , + (void*)m68k_op_subi_32_ai , + (void*)m68k_op_subi_32_ai , + (void*)m68k_op_subi_32_ai , + (void*)m68k_op_subi_32_ai , + (void*)m68k_op_subi_32_ai , + (void*)m68k_op_subi_32_pi , + (void*)m68k_op_subi_32_pi , + (void*)m68k_op_subi_32_pi , + (void*)m68k_op_subi_32_pi , + (void*)m68k_op_subi_32_pi , + (void*)m68k_op_subi_32_pi , + (void*)m68k_op_subi_32_pi , + (void*)m68k_op_subi_32_pi , + (void*)m68k_op_subi_32_pd , + (void*)m68k_op_subi_32_pd , + (void*)m68k_op_subi_32_pd , + (void*)m68k_op_subi_32_pd , + (void*)m68k_op_subi_32_pd , + (void*)m68k_op_subi_32_pd , + (void*)m68k_op_subi_32_pd , + (void*)m68k_op_subi_32_pd , + (void*)m68k_op_subi_32_di , + (void*)m68k_op_subi_32_di , + (void*)m68k_op_subi_32_di , + (void*)m68k_op_subi_32_di , + (void*)m68k_op_subi_32_di , + (void*)m68k_op_subi_32_di , + (void*)m68k_op_subi_32_di , + (void*)m68k_op_subi_32_di , + (void*)m68k_op_subi_32_ix , + (void*)m68k_op_subi_32_ix , + (void*)m68k_op_subi_32_ix , + (void*)m68k_op_subi_32_ix , + (void*)m68k_op_subi_32_ix , + (void*)m68k_op_subi_32_ix , + (void*)m68k_op_subi_32_ix , + (void*)m68k_op_subi_32_ix , + (void*)m68k_op_subi_32_aw , + (void*)m68k_op_subi_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk2cmp2_32_ai , + (void*)m68k_op_chk2cmp2_32_ai , + (void*)m68k_op_chk2cmp2_32_ai , + (void*)m68k_op_chk2cmp2_32_ai , + (void*)m68k_op_chk2cmp2_32_ai , + (void*)m68k_op_chk2cmp2_32_ai , + (void*)m68k_op_chk2cmp2_32_ai , + (void*)m68k_op_chk2cmp2_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk2cmp2_32_di , + (void*)m68k_op_chk2cmp2_32_di , + (void*)m68k_op_chk2cmp2_32_di , + (void*)m68k_op_chk2cmp2_32_di , + (void*)m68k_op_chk2cmp2_32_di , + (void*)m68k_op_chk2cmp2_32_di , + (void*)m68k_op_chk2cmp2_32_di , + (void*)m68k_op_chk2cmp2_32_di , + (void*)m68k_op_chk2cmp2_32_ix , + (void*)m68k_op_chk2cmp2_32_ix , + (void*)m68k_op_chk2cmp2_32_ix , + (void*)m68k_op_chk2cmp2_32_ix , + (void*)m68k_op_chk2cmp2_32_ix , + (void*)m68k_op_chk2cmp2_32_ix , + (void*)m68k_op_chk2cmp2_32_ix , + (void*)m68k_op_chk2cmp2_32_ix , + (void*)m68k_op_chk2cmp2_32_aw , + (void*)m68k_op_chk2cmp2_32_al , + (void*)m68k_op_chk2cmp2_32_pcdi , + (void*)m68k_op_chk2cmp2_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi7 , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd7 , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_aw , + (void*)m68k_op_btst_8_r_al , + (void*)m68k_op_btst_8_r_pcdi , + (void*)m68k_op_btst_8_r_pcix , + (void*)m68k_op_btst_8_r_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi7 , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd7 , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_aw , + (void*)m68k_op_bchg_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi7 , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd7 , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_aw , + (void*)m68k_op_bclr_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi7 , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd7 , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_aw , + (void*)m68k_op_bset_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addi_8_d , + (void*)m68k_op_addi_8_d , + (void*)m68k_op_addi_8_d , + (void*)m68k_op_addi_8_d , + (void*)m68k_op_addi_8_d , + (void*)m68k_op_addi_8_d , + (void*)m68k_op_addi_8_d , + (void*)m68k_op_addi_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addi_8_ai , + (void*)m68k_op_addi_8_ai , + (void*)m68k_op_addi_8_ai , + (void*)m68k_op_addi_8_ai , + (void*)m68k_op_addi_8_ai , + (void*)m68k_op_addi_8_ai , + (void*)m68k_op_addi_8_ai , + (void*)m68k_op_addi_8_ai , + (void*)m68k_op_addi_8_pi , + (void*)m68k_op_addi_8_pi , + (void*)m68k_op_addi_8_pi , + (void*)m68k_op_addi_8_pi , + (void*)m68k_op_addi_8_pi , + (void*)m68k_op_addi_8_pi , + (void*)m68k_op_addi_8_pi , + (void*)m68k_op_addi_8_pi7 , + (void*)m68k_op_addi_8_pd , + (void*)m68k_op_addi_8_pd , + (void*)m68k_op_addi_8_pd , + (void*)m68k_op_addi_8_pd , + (void*)m68k_op_addi_8_pd , + (void*)m68k_op_addi_8_pd , + (void*)m68k_op_addi_8_pd , + (void*)m68k_op_addi_8_pd7 , + (void*)m68k_op_addi_8_di , + (void*)m68k_op_addi_8_di , + (void*)m68k_op_addi_8_di , + (void*)m68k_op_addi_8_di , + (void*)m68k_op_addi_8_di , + (void*)m68k_op_addi_8_di , + (void*)m68k_op_addi_8_di , + (void*)m68k_op_addi_8_di , + (void*)m68k_op_addi_8_ix , + (void*)m68k_op_addi_8_ix , + (void*)m68k_op_addi_8_ix , + (void*)m68k_op_addi_8_ix , + (void*)m68k_op_addi_8_ix , + (void*)m68k_op_addi_8_ix , + (void*)m68k_op_addi_8_ix , + (void*)m68k_op_addi_8_ix , + (void*)m68k_op_addi_8_aw , + (void*)m68k_op_addi_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addi_16_d , + (void*)m68k_op_addi_16_d , + (void*)m68k_op_addi_16_d , + (void*)m68k_op_addi_16_d , + (void*)m68k_op_addi_16_d , + (void*)m68k_op_addi_16_d , + (void*)m68k_op_addi_16_d , + (void*)m68k_op_addi_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addi_16_ai , + (void*)m68k_op_addi_16_ai , + (void*)m68k_op_addi_16_ai , + (void*)m68k_op_addi_16_ai , + (void*)m68k_op_addi_16_ai , + (void*)m68k_op_addi_16_ai , + (void*)m68k_op_addi_16_ai , + (void*)m68k_op_addi_16_ai , + (void*)m68k_op_addi_16_pi , + (void*)m68k_op_addi_16_pi , + (void*)m68k_op_addi_16_pi , + (void*)m68k_op_addi_16_pi , + (void*)m68k_op_addi_16_pi , + (void*)m68k_op_addi_16_pi , + (void*)m68k_op_addi_16_pi , + (void*)m68k_op_addi_16_pi , + (void*)m68k_op_addi_16_pd , + (void*)m68k_op_addi_16_pd , + (void*)m68k_op_addi_16_pd , + (void*)m68k_op_addi_16_pd , + (void*)m68k_op_addi_16_pd , + (void*)m68k_op_addi_16_pd , + (void*)m68k_op_addi_16_pd , + (void*)m68k_op_addi_16_pd , + (void*)m68k_op_addi_16_di , + (void*)m68k_op_addi_16_di , + (void*)m68k_op_addi_16_di , + (void*)m68k_op_addi_16_di , + (void*)m68k_op_addi_16_di , + (void*)m68k_op_addi_16_di , + (void*)m68k_op_addi_16_di , + (void*)m68k_op_addi_16_di , + (void*)m68k_op_addi_16_ix , + (void*)m68k_op_addi_16_ix , + (void*)m68k_op_addi_16_ix , + (void*)m68k_op_addi_16_ix , + (void*)m68k_op_addi_16_ix , + (void*)m68k_op_addi_16_ix , + (void*)m68k_op_addi_16_ix , + (void*)m68k_op_addi_16_ix , + (void*)m68k_op_addi_16_aw , + (void*)m68k_op_addi_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addi_32_d , + (void*)m68k_op_addi_32_d , + (void*)m68k_op_addi_32_d , + (void*)m68k_op_addi_32_d , + (void*)m68k_op_addi_32_d , + (void*)m68k_op_addi_32_d , + (void*)m68k_op_addi_32_d , + (void*)m68k_op_addi_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addi_32_ai , + (void*)m68k_op_addi_32_ai , + (void*)m68k_op_addi_32_ai , + (void*)m68k_op_addi_32_ai , + (void*)m68k_op_addi_32_ai , + (void*)m68k_op_addi_32_ai , + (void*)m68k_op_addi_32_ai , + (void*)m68k_op_addi_32_ai , + (void*)m68k_op_addi_32_pi , + (void*)m68k_op_addi_32_pi , + (void*)m68k_op_addi_32_pi , + (void*)m68k_op_addi_32_pi , + (void*)m68k_op_addi_32_pi , + (void*)m68k_op_addi_32_pi , + (void*)m68k_op_addi_32_pi , + (void*)m68k_op_addi_32_pi , + (void*)m68k_op_addi_32_pd , + (void*)m68k_op_addi_32_pd , + (void*)m68k_op_addi_32_pd , + (void*)m68k_op_addi_32_pd , + (void*)m68k_op_addi_32_pd , + (void*)m68k_op_addi_32_pd , + (void*)m68k_op_addi_32_pd , + (void*)m68k_op_addi_32_pd , + (void*)m68k_op_addi_32_di , + (void*)m68k_op_addi_32_di , + (void*)m68k_op_addi_32_di , + (void*)m68k_op_addi_32_di , + (void*)m68k_op_addi_32_di , + (void*)m68k_op_addi_32_di , + (void*)m68k_op_addi_32_di , + (void*)m68k_op_addi_32_di , + (void*)m68k_op_addi_32_ix , + (void*)m68k_op_addi_32_ix , + (void*)m68k_op_addi_32_ix , + (void*)m68k_op_addi_32_ix , + (void*)m68k_op_addi_32_ix , + (void*)m68k_op_addi_32_ix , + (void*)m68k_op_addi_32_ix , + (void*)m68k_op_addi_32_ix , + (void*)m68k_op_addi_32_aw , + (void*)m68k_op_addi_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_rtm_32 , + (void*)m68k_op_callm_32_ai , + (void*)m68k_op_callm_32_ai , + (void*)m68k_op_callm_32_ai , + (void*)m68k_op_callm_32_ai , + (void*)m68k_op_callm_32_ai , + (void*)m68k_op_callm_32_ai , + (void*)m68k_op_callm_32_ai , + (void*)m68k_op_callm_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_callm_32_di , + (void*)m68k_op_callm_32_di , + (void*)m68k_op_callm_32_di , + (void*)m68k_op_callm_32_di , + (void*)m68k_op_callm_32_di , + (void*)m68k_op_callm_32_di , + (void*)m68k_op_callm_32_di , + (void*)m68k_op_callm_32_di , + (void*)m68k_op_callm_32_ix , + (void*)m68k_op_callm_32_ix , + (void*)m68k_op_callm_32_ix , + (void*)m68k_op_callm_32_ix , + (void*)m68k_op_callm_32_ix , + (void*)m68k_op_callm_32_ix , + (void*)m68k_op_callm_32_ix , + (void*)m68k_op_callm_32_ix , + (void*)m68k_op_callm_32_aw , + (void*)m68k_op_callm_32_al , + (void*)m68k_op_callm_32_pcdi , + (void*)m68k_op_callm_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi7 , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd7 , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_aw , + (void*)m68k_op_btst_8_r_al , + (void*)m68k_op_btst_8_r_pcdi , + (void*)m68k_op_btst_8_r_pcix , + (void*)m68k_op_btst_8_r_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi7 , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd7 , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_aw , + (void*)m68k_op_bchg_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi7 , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd7 , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_aw , + (void*)m68k_op_bclr_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi7 , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd7 , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_aw , + (void*)m68k_op_bset_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_32_s_d , + (void*)m68k_op_btst_32_s_d , + (void*)m68k_op_btst_32_s_d , + (void*)m68k_op_btst_32_s_d , + (void*)m68k_op_btst_32_s_d , + (void*)m68k_op_btst_32_s_d , + (void*)m68k_op_btst_32_s_d , + (void*)m68k_op_btst_32_s_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_8_s_ai , + (void*)m68k_op_btst_8_s_ai , + (void*)m68k_op_btst_8_s_ai , + (void*)m68k_op_btst_8_s_ai , + (void*)m68k_op_btst_8_s_ai , + (void*)m68k_op_btst_8_s_ai , + (void*)m68k_op_btst_8_s_ai , + (void*)m68k_op_btst_8_s_ai , + (void*)m68k_op_btst_8_s_pi , + (void*)m68k_op_btst_8_s_pi , + (void*)m68k_op_btst_8_s_pi , + (void*)m68k_op_btst_8_s_pi , + (void*)m68k_op_btst_8_s_pi , + (void*)m68k_op_btst_8_s_pi , + (void*)m68k_op_btst_8_s_pi , + (void*)m68k_op_btst_8_s_pi7 , + (void*)m68k_op_btst_8_s_pd , + (void*)m68k_op_btst_8_s_pd , + (void*)m68k_op_btst_8_s_pd , + (void*)m68k_op_btst_8_s_pd , + (void*)m68k_op_btst_8_s_pd , + (void*)m68k_op_btst_8_s_pd , + (void*)m68k_op_btst_8_s_pd , + (void*)m68k_op_btst_8_s_pd7 , + (void*)m68k_op_btst_8_s_di , + (void*)m68k_op_btst_8_s_di , + (void*)m68k_op_btst_8_s_di , + (void*)m68k_op_btst_8_s_di , + (void*)m68k_op_btst_8_s_di , + (void*)m68k_op_btst_8_s_di , + (void*)m68k_op_btst_8_s_di , + (void*)m68k_op_btst_8_s_di , + (void*)m68k_op_btst_8_s_ix , + (void*)m68k_op_btst_8_s_ix , + (void*)m68k_op_btst_8_s_ix , + (void*)m68k_op_btst_8_s_ix , + (void*)m68k_op_btst_8_s_ix , + (void*)m68k_op_btst_8_s_ix , + (void*)m68k_op_btst_8_s_ix , + (void*)m68k_op_btst_8_s_ix , + (void*)m68k_op_btst_8_s_aw , + (void*)m68k_op_btst_8_s_al , + (void*)m68k_op_btst_8_s_pcdi , + (void*)m68k_op_btst_8_s_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_32_s_d , + (void*)m68k_op_bchg_32_s_d , + (void*)m68k_op_bchg_32_s_d , + (void*)m68k_op_bchg_32_s_d , + (void*)m68k_op_bchg_32_s_d , + (void*)m68k_op_bchg_32_s_d , + (void*)m68k_op_bchg_32_s_d , + (void*)m68k_op_bchg_32_s_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_8_s_ai , + (void*)m68k_op_bchg_8_s_ai , + (void*)m68k_op_bchg_8_s_ai , + (void*)m68k_op_bchg_8_s_ai , + (void*)m68k_op_bchg_8_s_ai , + (void*)m68k_op_bchg_8_s_ai , + (void*)m68k_op_bchg_8_s_ai , + (void*)m68k_op_bchg_8_s_ai , + (void*)m68k_op_bchg_8_s_pi , + (void*)m68k_op_bchg_8_s_pi , + (void*)m68k_op_bchg_8_s_pi , + (void*)m68k_op_bchg_8_s_pi , + (void*)m68k_op_bchg_8_s_pi , + (void*)m68k_op_bchg_8_s_pi , + (void*)m68k_op_bchg_8_s_pi , + (void*)m68k_op_bchg_8_s_pi7 , + (void*)m68k_op_bchg_8_s_pd , + (void*)m68k_op_bchg_8_s_pd , + (void*)m68k_op_bchg_8_s_pd , + (void*)m68k_op_bchg_8_s_pd , + (void*)m68k_op_bchg_8_s_pd , + (void*)m68k_op_bchg_8_s_pd , + (void*)m68k_op_bchg_8_s_pd , + (void*)m68k_op_bchg_8_s_pd7 , + (void*)m68k_op_bchg_8_s_di , + (void*)m68k_op_bchg_8_s_di , + (void*)m68k_op_bchg_8_s_di , + (void*)m68k_op_bchg_8_s_di , + (void*)m68k_op_bchg_8_s_di , + (void*)m68k_op_bchg_8_s_di , + (void*)m68k_op_bchg_8_s_di , + (void*)m68k_op_bchg_8_s_di , + (void*)m68k_op_bchg_8_s_ix , + (void*)m68k_op_bchg_8_s_ix , + (void*)m68k_op_bchg_8_s_ix , + (void*)m68k_op_bchg_8_s_ix , + (void*)m68k_op_bchg_8_s_ix , + (void*)m68k_op_bchg_8_s_ix , + (void*)m68k_op_bchg_8_s_ix , + (void*)m68k_op_bchg_8_s_ix , + (void*)m68k_op_bchg_8_s_aw , + (void*)m68k_op_bchg_8_s_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_32_s_d , + (void*)m68k_op_bclr_32_s_d , + (void*)m68k_op_bclr_32_s_d , + (void*)m68k_op_bclr_32_s_d , + (void*)m68k_op_bclr_32_s_d , + (void*)m68k_op_bclr_32_s_d , + (void*)m68k_op_bclr_32_s_d , + (void*)m68k_op_bclr_32_s_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_8_s_ai , + (void*)m68k_op_bclr_8_s_ai , + (void*)m68k_op_bclr_8_s_ai , + (void*)m68k_op_bclr_8_s_ai , + (void*)m68k_op_bclr_8_s_ai , + (void*)m68k_op_bclr_8_s_ai , + (void*)m68k_op_bclr_8_s_ai , + (void*)m68k_op_bclr_8_s_ai , + (void*)m68k_op_bclr_8_s_pi , + (void*)m68k_op_bclr_8_s_pi , + (void*)m68k_op_bclr_8_s_pi , + (void*)m68k_op_bclr_8_s_pi , + (void*)m68k_op_bclr_8_s_pi , + (void*)m68k_op_bclr_8_s_pi , + (void*)m68k_op_bclr_8_s_pi , + (void*)m68k_op_bclr_8_s_pi7 , + (void*)m68k_op_bclr_8_s_pd , + (void*)m68k_op_bclr_8_s_pd , + (void*)m68k_op_bclr_8_s_pd , + (void*)m68k_op_bclr_8_s_pd , + (void*)m68k_op_bclr_8_s_pd , + (void*)m68k_op_bclr_8_s_pd , + (void*)m68k_op_bclr_8_s_pd , + (void*)m68k_op_bclr_8_s_pd7 , + (void*)m68k_op_bclr_8_s_di , + (void*)m68k_op_bclr_8_s_di , + (void*)m68k_op_bclr_8_s_di , + (void*)m68k_op_bclr_8_s_di , + (void*)m68k_op_bclr_8_s_di , + (void*)m68k_op_bclr_8_s_di , + (void*)m68k_op_bclr_8_s_di , + (void*)m68k_op_bclr_8_s_di , + (void*)m68k_op_bclr_8_s_ix , + (void*)m68k_op_bclr_8_s_ix , + (void*)m68k_op_bclr_8_s_ix , + (void*)m68k_op_bclr_8_s_ix , + (void*)m68k_op_bclr_8_s_ix , + (void*)m68k_op_bclr_8_s_ix , + (void*)m68k_op_bclr_8_s_ix , + (void*)m68k_op_bclr_8_s_ix , + (void*)m68k_op_bclr_8_s_aw , + (void*)m68k_op_bclr_8_s_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_32_s_d , + (void*)m68k_op_bset_32_s_d , + (void*)m68k_op_bset_32_s_d , + (void*)m68k_op_bset_32_s_d , + (void*)m68k_op_bset_32_s_d , + (void*)m68k_op_bset_32_s_d , + (void*)m68k_op_bset_32_s_d , + (void*)m68k_op_bset_32_s_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_8_s_ai , + (void*)m68k_op_bset_8_s_ai , + (void*)m68k_op_bset_8_s_ai , + (void*)m68k_op_bset_8_s_ai , + (void*)m68k_op_bset_8_s_ai , + (void*)m68k_op_bset_8_s_ai , + (void*)m68k_op_bset_8_s_ai , + (void*)m68k_op_bset_8_s_ai , + (void*)m68k_op_bset_8_s_pi , + (void*)m68k_op_bset_8_s_pi , + (void*)m68k_op_bset_8_s_pi , + (void*)m68k_op_bset_8_s_pi , + (void*)m68k_op_bset_8_s_pi , + (void*)m68k_op_bset_8_s_pi , + (void*)m68k_op_bset_8_s_pi , + (void*)m68k_op_bset_8_s_pi7 , + (void*)m68k_op_bset_8_s_pd , + (void*)m68k_op_bset_8_s_pd , + (void*)m68k_op_bset_8_s_pd , + (void*)m68k_op_bset_8_s_pd , + (void*)m68k_op_bset_8_s_pd , + (void*)m68k_op_bset_8_s_pd , + (void*)m68k_op_bset_8_s_pd , + (void*)m68k_op_bset_8_s_pd7 , + (void*)m68k_op_bset_8_s_di , + (void*)m68k_op_bset_8_s_di , + (void*)m68k_op_bset_8_s_di , + (void*)m68k_op_bset_8_s_di , + (void*)m68k_op_bset_8_s_di , + (void*)m68k_op_bset_8_s_di , + (void*)m68k_op_bset_8_s_di , + (void*)m68k_op_bset_8_s_di , + (void*)m68k_op_bset_8_s_ix , + (void*)m68k_op_bset_8_s_ix , + (void*)m68k_op_bset_8_s_ix , + (void*)m68k_op_bset_8_s_ix , + (void*)m68k_op_bset_8_s_ix , + (void*)m68k_op_bset_8_s_ix , + (void*)m68k_op_bset_8_s_ix , + (void*)m68k_op_bset_8_s_ix , + (void*)m68k_op_bset_8_s_aw , + (void*)m68k_op_bset_8_s_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi7 , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd7 , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_aw , + (void*)m68k_op_btst_8_r_al , + (void*)m68k_op_btst_8_r_pcdi , + (void*)m68k_op_btst_8_r_pcix , + (void*)m68k_op_btst_8_r_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi7 , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd7 , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_aw , + (void*)m68k_op_bchg_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi7 , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd7 , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_aw , + (void*)m68k_op_bclr_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi7 , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd7 , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_aw , + (void*)m68k_op_bset_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eori_8_d , + (void*)m68k_op_eori_8_d , + (void*)m68k_op_eori_8_d , + (void*)m68k_op_eori_8_d , + (void*)m68k_op_eori_8_d , + (void*)m68k_op_eori_8_d , + (void*)m68k_op_eori_8_d , + (void*)m68k_op_eori_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eori_8_ai , + (void*)m68k_op_eori_8_ai , + (void*)m68k_op_eori_8_ai , + (void*)m68k_op_eori_8_ai , + (void*)m68k_op_eori_8_ai , + (void*)m68k_op_eori_8_ai , + (void*)m68k_op_eori_8_ai , + (void*)m68k_op_eori_8_ai , + (void*)m68k_op_eori_8_pi , + (void*)m68k_op_eori_8_pi , + (void*)m68k_op_eori_8_pi , + (void*)m68k_op_eori_8_pi , + (void*)m68k_op_eori_8_pi , + (void*)m68k_op_eori_8_pi , + (void*)m68k_op_eori_8_pi , + (void*)m68k_op_eori_8_pi7 , + (void*)m68k_op_eori_8_pd , + (void*)m68k_op_eori_8_pd , + (void*)m68k_op_eori_8_pd , + (void*)m68k_op_eori_8_pd , + (void*)m68k_op_eori_8_pd , + (void*)m68k_op_eori_8_pd , + (void*)m68k_op_eori_8_pd , + (void*)m68k_op_eori_8_pd7 , + (void*)m68k_op_eori_8_di , + (void*)m68k_op_eori_8_di , + (void*)m68k_op_eori_8_di , + (void*)m68k_op_eori_8_di , + (void*)m68k_op_eori_8_di , + (void*)m68k_op_eori_8_di , + (void*)m68k_op_eori_8_di , + (void*)m68k_op_eori_8_di , + (void*)m68k_op_eori_8_ix , + (void*)m68k_op_eori_8_ix , + (void*)m68k_op_eori_8_ix , + (void*)m68k_op_eori_8_ix , + (void*)m68k_op_eori_8_ix , + (void*)m68k_op_eori_8_ix , + (void*)m68k_op_eori_8_ix , + (void*)m68k_op_eori_8_ix , + (void*)m68k_op_eori_8_aw , + (void*)m68k_op_eori_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eori_16_toc , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eori_16_d , + (void*)m68k_op_eori_16_d , + (void*)m68k_op_eori_16_d , + (void*)m68k_op_eori_16_d , + (void*)m68k_op_eori_16_d , + (void*)m68k_op_eori_16_d , + (void*)m68k_op_eori_16_d , + (void*)m68k_op_eori_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eori_16_ai , + (void*)m68k_op_eori_16_ai , + (void*)m68k_op_eori_16_ai , + (void*)m68k_op_eori_16_ai , + (void*)m68k_op_eori_16_ai , + (void*)m68k_op_eori_16_ai , + (void*)m68k_op_eori_16_ai , + (void*)m68k_op_eori_16_ai , + (void*)m68k_op_eori_16_pi , + (void*)m68k_op_eori_16_pi , + (void*)m68k_op_eori_16_pi , + (void*)m68k_op_eori_16_pi , + (void*)m68k_op_eori_16_pi , + (void*)m68k_op_eori_16_pi , + (void*)m68k_op_eori_16_pi , + (void*)m68k_op_eori_16_pi , + (void*)m68k_op_eori_16_pd , + (void*)m68k_op_eori_16_pd , + (void*)m68k_op_eori_16_pd , + (void*)m68k_op_eori_16_pd , + (void*)m68k_op_eori_16_pd , + (void*)m68k_op_eori_16_pd , + (void*)m68k_op_eori_16_pd , + (void*)m68k_op_eori_16_pd , + (void*)m68k_op_eori_16_di , + (void*)m68k_op_eori_16_di , + (void*)m68k_op_eori_16_di , + (void*)m68k_op_eori_16_di , + (void*)m68k_op_eori_16_di , + (void*)m68k_op_eori_16_di , + (void*)m68k_op_eori_16_di , + (void*)m68k_op_eori_16_di , + (void*)m68k_op_eori_16_ix , + (void*)m68k_op_eori_16_ix , + (void*)m68k_op_eori_16_ix , + (void*)m68k_op_eori_16_ix , + (void*)m68k_op_eori_16_ix , + (void*)m68k_op_eori_16_ix , + (void*)m68k_op_eori_16_ix , + (void*)m68k_op_eori_16_ix , + (void*)m68k_op_eori_16_aw , + (void*)m68k_op_eori_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eori_16_tos , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eori_32_d , + (void*)m68k_op_eori_32_d , + (void*)m68k_op_eori_32_d , + (void*)m68k_op_eori_32_d , + (void*)m68k_op_eori_32_d , + (void*)m68k_op_eori_32_d , + (void*)m68k_op_eori_32_d , + (void*)m68k_op_eori_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eori_32_ai , + (void*)m68k_op_eori_32_ai , + (void*)m68k_op_eori_32_ai , + (void*)m68k_op_eori_32_ai , + (void*)m68k_op_eori_32_ai , + (void*)m68k_op_eori_32_ai , + (void*)m68k_op_eori_32_ai , + (void*)m68k_op_eori_32_ai , + (void*)m68k_op_eori_32_pi , + (void*)m68k_op_eori_32_pi , + (void*)m68k_op_eori_32_pi , + (void*)m68k_op_eori_32_pi , + (void*)m68k_op_eori_32_pi , + (void*)m68k_op_eori_32_pi , + (void*)m68k_op_eori_32_pi , + (void*)m68k_op_eori_32_pi , + (void*)m68k_op_eori_32_pd , + (void*)m68k_op_eori_32_pd , + (void*)m68k_op_eori_32_pd , + (void*)m68k_op_eori_32_pd , + (void*)m68k_op_eori_32_pd , + (void*)m68k_op_eori_32_pd , + (void*)m68k_op_eori_32_pd , + (void*)m68k_op_eori_32_pd , + (void*)m68k_op_eori_32_di , + (void*)m68k_op_eori_32_di , + (void*)m68k_op_eori_32_di , + (void*)m68k_op_eori_32_di , + (void*)m68k_op_eori_32_di , + (void*)m68k_op_eori_32_di , + (void*)m68k_op_eori_32_di , + (void*)m68k_op_eori_32_di , + (void*)m68k_op_eori_32_ix , + (void*)m68k_op_eori_32_ix , + (void*)m68k_op_eori_32_ix , + (void*)m68k_op_eori_32_ix , + (void*)m68k_op_eori_32_ix , + (void*)m68k_op_eori_32_ix , + (void*)m68k_op_eori_32_ix , + (void*)m68k_op_eori_32_ix , + (void*)m68k_op_eori_32_aw , + (void*)m68k_op_eori_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cas_8_ai , + (void*)m68k_op_cas_8_ai , + (void*)m68k_op_cas_8_ai , + (void*)m68k_op_cas_8_ai , + (void*)m68k_op_cas_8_ai , + (void*)m68k_op_cas_8_ai , + (void*)m68k_op_cas_8_ai , + (void*)m68k_op_cas_8_ai , + (void*)m68k_op_cas_8_pi , + (void*)m68k_op_cas_8_pi , + (void*)m68k_op_cas_8_pi , + (void*)m68k_op_cas_8_pi , + (void*)m68k_op_cas_8_pi , + (void*)m68k_op_cas_8_pi , + (void*)m68k_op_cas_8_pi , + (void*)m68k_op_cas_8_pi7 , + (void*)m68k_op_cas_8_pd , + (void*)m68k_op_cas_8_pd , + (void*)m68k_op_cas_8_pd , + (void*)m68k_op_cas_8_pd , + (void*)m68k_op_cas_8_pd , + (void*)m68k_op_cas_8_pd , + (void*)m68k_op_cas_8_pd , + (void*)m68k_op_cas_8_pd7 , + (void*)m68k_op_cas_8_di , + (void*)m68k_op_cas_8_di , + (void*)m68k_op_cas_8_di , + (void*)m68k_op_cas_8_di , + (void*)m68k_op_cas_8_di , + (void*)m68k_op_cas_8_di , + (void*)m68k_op_cas_8_di , + (void*)m68k_op_cas_8_di , + (void*)m68k_op_cas_8_ix , + (void*)m68k_op_cas_8_ix , + (void*)m68k_op_cas_8_ix , + (void*)m68k_op_cas_8_ix , + (void*)m68k_op_cas_8_ix , + (void*)m68k_op_cas_8_ix , + (void*)m68k_op_cas_8_ix , + (void*)m68k_op_cas_8_ix , + (void*)m68k_op_cas_8_aw , + (void*)m68k_op_cas_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi7 , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd7 , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_aw , + (void*)m68k_op_btst_8_r_al , + (void*)m68k_op_btst_8_r_pcdi , + (void*)m68k_op_btst_8_r_pcix , + (void*)m68k_op_btst_8_r_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi7 , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd7 , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_aw , + (void*)m68k_op_bchg_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi7 , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd7 , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_aw , + (void*)m68k_op_bclr_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi7 , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd7 , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_aw , + (void*)m68k_op_bset_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpi_8_d , + (void*)m68k_op_cmpi_8_d , + (void*)m68k_op_cmpi_8_d , + (void*)m68k_op_cmpi_8_d , + (void*)m68k_op_cmpi_8_d , + (void*)m68k_op_cmpi_8_d , + (void*)m68k_op_cmpi_8_d , + (void*)m68k_op_cmpi_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpi_8_ai , + (void*)m68k_op_cmpi_8_ai , + (void*)m68k_op_cmpi_8_ai , + (void*)m68k_op_cmpi_8_ai , + (void*)m68k_op_cmpi_8_ai , + (void*)m68k_op_cmpi_8_ai , + (void*)m68k_op_cmpi_8_ai , + (void*)m68k_op_cmpi_8_ai , + (void*)m68k_op_cmpi_8_pi , + (void*)m68k_op_cmpi_8_pi , + (void*)m68k_op_cmpi_8_pi , + (void*)m68k_op_cmpi_8_pi , + (void*)m68k_op_cmpi_8_pi , + (void*)m68k_op_cmpi_8_pi , + (void*)m68k_op_cmpi_8_pi , + (void*)m68k_op_cmpi_8_pi7 , + (void*)m68k_op_cmpi_8_pd , + (void*)m68k_op_cmpi_8_pd , + (void*)m68k_op_cmpi_8_pd , + (void*)m68k_op_cmpi_8_pd , + (void*)m68k_op_cmpi_8_pd , + (void*)m68k_op_cmpi_8_pd , + (void*)m68k_op_cmpi_8_pd , + (void*)m68k_op_cmpi_8_pd7 , + (void*)m68k_op_cmpi_8_di , + (void*)m68k_op_cmpi_8_di , + (void*)m68k_op_cmpi_8_di , + (void*)m68k_op_cmpi_8_di , + (void*)m68k_op_cmpi_8_di , + (void*)m68k_op_cmpi_8_di , + (void*)m68k_op_cmpi_8_di , + (void*)m68k_op_cmpi_8_di , + (void*)m68k_op_cmpi_8_ix , + (void*)m68k_op_cmpi_8_ix , + (void*)m68k_op_cmpi_8_ix , + (void*)m68k_op_cmpi_8_ix , + (void*)m68k_op_cmpi_8_ix , + (void*)m68k_op_cmpi_8_ix , + (void*)m68k_op_cmpi_8_ix , + (void*)m68k_op_cmpi_8_ix , + (void*)m68k_op_cmpi_8_aw , + (void*)m68k_op_cmpi_8_al , + (void*)m68k_op_cmpi_8_pcdi , + (void*)m68k_op_cmpi_8_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpi_16_d , + (void*)m68k_op_cmpi_16_d , + (void*)m68k_op_cmpi_16_d , + (void*)m68k_op_cmpi_16_d , + (void*)m68k_op_cmpi_16_d , + (void*)m68k_op_cmpi_16_d , + (void*)m68k_op_cmpi_16_d , + (void*)m68k_op_cmpi_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpi_16_ai , + (void*)m68k_op_cmpi_16_ai , + (void*)m68k_op_cmpi_16_ai , + (void*)m68k_op_cmpi_16_ai , + (void*)m68k_op_cmpi_16_ai , + (void*)m68k_op_cmpi_16_ai , + (void*)m68k_op_cmpi_16_ai , + (void*)m68k_op_cmpi_16_ai , + (void*)m68k_op_cmpi_16_pi , + (void*)m68k_op_cmpi_16_pi , + (void*)m68k_op_cmpi_16_pi , + (void*)m68k_op_cmpi_16_pi , + (void*)m68k_op_cmpi_16_pi , + (void*)m68k_op_cmpi_16_pi , + (void*)m68k_op_cmpi_16_pi , + (void*)m68k_op_cmpi_16_pi , + (void*)m68k_op_cmpi_16_pd , + (void*)m68k_op_cmpi_16_pd , + (void*)m68k_op_cmpi_16_pd , + (void*)m68k_op_cmpi_16_pd , + (void*)m68k_op_cmpi_16_pd , + (void*)m68k_op_cmpi_16_pd , + (void*)m68k_op_cmpi_16_pd , + (void*)m68k_op_cmpi_16_pd , + (void*)m68k_op_cmpi_16_di , + (void*)m68k_op_cmpi_16_di , + (void*)m68k_op_cmpi_16_di , + (void*)m68k_op_cmpi_16_di , + (void*)m68k_op_cmpi_16_di , + (void*)m68k_op_cmpi_16_di , + (void*)m68k_op_cmpi_16_di , + (void*)m68k_op_cmpi_16_di , + (void*)m68k_op_cmpi_16_ix , + (void*)m68k_op_cmpi_16_ix , + (void*)m68k_op_cmpi_16_ix , + (void*)m68k_op_cmpi_16_ix , + (void*)m68k_op_cmpi_16_ix , + (void*)m68k_op_cmpi_16_ix , + (void*)m68k_op_cmpi_16_ix , + (void*)m68k_op_cmpi_16_ix , + (void*)m68k_op_cmpi_16_aw , + (void*)m68k_op_cmpi_16_al , + (void*)m68k_op_cmpi_16_pcdi , + (void*)m68k_op_cmpi_16_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpi_32_d , + (void*)m68k_op_cmpi_32_d , + (void*)m68k_op_cmpi_32_d , + (void*)m68k_op_cmpi_32_d , + (void*)m68k_op_cmpi_32_d , + (void*)m68k_op_cmpi_32_d , + (void*)m68k_op_cmpi_32_d , + (void*)m68k_op_cmpi_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpi_32_ai , + (void*)m68k_op_cmpi_32_ai , + (void*)m68k_op_cmpi_32_ai , + (void*)m68k_op_cmpi_32_ai , + (void*)m68k_op_cmpi_32_ai , + (void*)m68k_op_cmpi_32_ai , + (void*)m68k_op_cmpi_32_ai , + (void*)m68k_op_cmpi_32_ai , + (void*)m68k_op_cmpi_32_pi , + (void*)m68k_op_cmpi_32_pi , + (void*)m68k_op_cmpi_32_pi , + (void*)m68k_op_cmpi_32_pi , + (void*)m68k_op_cmpi_32_pi , + (void*)m68k_op_cmpi_32_pi , + (void*)m68k_op_cmpi_32_pi , + (void*)m68k_op_cmpi_32_pi , + (void*)m68k_op_cmpi_32_pd , + (void*)m68k_op_cmpi_32_pd , + (void*)m68k_op_cmpi_32_pd , + (void*)m68k_op_cmpi_32_pd , + (void*)m68k_op_cmpi_32_pd , + (void*)m68k_op_cmpi_32_pd , + (void*)m68k_op_cmpi_32_pd , + (void*)m68k_op_cmpi_32_pd , + (void*)m68k_op_cmpi_32_di , + (void*)m68k_op_cmpi_32_di , + (void*)m68k_op_cmpi_32_di , + (void*)m68k_op_cmpi_32_di , + (void*)m68k_op_cmpi_32_di , + (void*)m68k_op_cmpi_32_di , + (void*)m68k_op_cmpi_32_di , + (void*)m68k_op_cmpi_32_di , + (void*)m68k_op_cmpi_32_ix , + (void*)m68k_op_cmpi_32_ix , + (void*)m68k_op_cmpi_32_ix , + (void*)m68k_op_cmpi_32_ix , + (void*)m68k_op_cmpi_32_ix , + (void*)m68k_op_cmpi_32_ix , + (void*)m68k_op_cmpi_32_ix , + (void*)m68k_op_cmpi_32_ix , + (void*)m68k_op_cmpi_32_aw , + (void*)m68k_op_cmpi_32_al , + (void*)m68k_op_cmpi_32_pcdi , + (void*)m68k_op_cmpi_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cas_16_ai , + (void*)m68k_op_cas_16_ai , + (void*)m68k_op_cas_16_ai , + (void*)m68k_op_cas_16_ai , + (void*)m68k_op_cas_16_ai , + (void*)m68k_op_cas_16_ai , + (void*)m68k_op_cas_16_ai , + (void*)m68k_op_cas_16_ai , + (void*)m68k_op_cas_16_pi , + (void*)m68k_op_cas_16_pi , + (void*)m68k_op_cas_16_pi , + (void*)m68k_op_cas_16_pi , + (void*)m68k_op_cas_16_pi , + (void*)m68k_op_cas_16_pi , + (void*)m68k_op_cas_16_pi , + (void*)m68k_op_cas_16_pi , + (void*)m68k_op_cas_16_pd , + (void*)m68k_op_cas_16_pd , + (void*)m68k_op_cas_16_pd , + (void*)m68k_op_cas_16_pd , + (void*)m68k_op_cas_16_pd , + (void*)m68k_op_cas_16_pd , + (void*)m68k_op_cas_16_pd , + (void*)m68k_op_cas_16_pd , + (void*)m68k_op_cas_16_di , + (void*)m68k_op_cas_16_di , + (void*)m68k_op_cas_16_di , + (void*)m68k_op_cas_16_di , + (void*)m68k_op_cas_16_di , + (void*)m68k_op_cas_16_di , + (void*)m68k_op_cas_16_di , + (void*)m68k_op_cas_16_di , + (void*)m68k_op_cas_16_ix , + (void*)m68k_op_cas_16_ix , + (void*)m68k_op_cas_16_ix , + (void*)m68k_op_cas_16_ix , + (void*)m68k_op_cas_16_ix , + (void*)m68k_op_cas_16_ix , + (void*)m68k_op_cas_16_ix , + (void*)m68k_op_cas_16_ix , + (void*)m68k_op_cas_16_aw , + (void*)m68k_op_cas_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cas2_16 , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi7 , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd7 , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_aw , + (void*)m68k_op_btst_8_r_al , + (void*)m68k_op_btst_8_r_pcdi , + (void*)m68k_op_btst_8_r_pcix , + (void*)m68k_op_btst_8_r_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi7 , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd7 , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_aw , + (void*)m68k_op_bchg_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi7 , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd7 , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_aw , + (void*)m68k_op_bclr_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi7 , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd7 , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_aw , + (void*)m68k_op_bset_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_moves_8_ai , + (void*)m68k_op_moves_8_ai , + (void*)m68k_op_moves_8_ai , + (void*)m68k_op_moves_8_ai , + (void*)m68k_op_moves_8_ai , + (void*)m68k_op_moves_8_ai , + (void*)m68k_op_moves_8_ai , + (void*)m68k_op_moves_8_ai , + (void*)m68k_op_moves_8_pi , + (void*)m68k_op_moves_8_pi , + (void*)m68k_op_moves_8_pi , + (void*)m68k_op_moves_8_pi , + (void*)m68k_op_moves_8_pi , + (void*)m68k_op_moves_8_pi , + (void*)m68k_op_moves_8_pi , + (void*)m68k_op_moves_8_pi7 , + (void*)m68k_op_moves_8_pd , + (void*)m68k_op_moves_8_pd , + (void*)m68k_op_moves_8_pd , + (void*)m68k_op_moves_8_pd , + (void*)m68k_op_moves_8_pd , + (void*)m68k_op_moves_8_pd , + (void*)m68k_op_moves_8_pd , + (void*)m68k_op_moves_8_pd7 , + (void*)m68k_op_moves_8_di , + (void*)m68k_op_moves_8_di , + (void*)m68k_op_moves_8_di , + (void*)m68k_op_moves_8_di , + (void*)m68k_op_moves_8_di , + (void*)m68k_op_moves_8_di , + (void*)m68k_op_moves_8_di , + (void*)m68k_op_moves_8_di , + (void*)m68k_op_moves_8_ix , + (void*)m68k_op_moves_8_ix , + (void*)m68k_op_moves_8_ix , + (void*)m68k_op_moves_8_ix , + (void*)m68k_op_moves_8_ix , + (void*)m68k_op_moves_8_ix , + (void*)m68k_op_moves_8_ix , + (void*)m68k_op_moves_8_ix , + (void*)m68k_op_moves_8_aw , + (void*)m68k_op_moves_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_moves_16_ai , + (void*)m68k_op_moves_16_ai , + (void*)m68k_op_moves_16_ai , + (void*)m68k_op_moves_16_ai , + (void*)m68k_op_moves_16_ai , + (void*)m68k_op_moves_16_ai , + (void*)m68k_op_moves_16_ai , + (void*)m68k_op_moves_16_ai , + (void*)m68k_op_moves_16_pi , + (void*)m68k_op_moves_16_pi , + (void*)m68k_op_moves_16_pi , + (void*)m68k_op_moves_16_pi , + (void*)m68k_op_moves_16_pi , + (void*)m68k_op_moves_16_pi , + (void*)m68k_op_moves_16_pi , + (void*)m68k_op_moves_16_pi , + (void*)m68k_op_moves_16_pd , + (void*)m68k_op_moves_16_pd , + (void*)m68k_op_moves_16_pd , + (void*)m68k_op_moves_16_pd , + (void*)m68k_op_moves_16_pd , + (void*)m68k_op_moves_16_pd , + (void*)m68k_op_moves_16_pd , + (void*)m68k_op_moves_16_pd , + (void*)m68k_op_moves_16_di , + (void*)m68k_op_moves_16_di , + (void*)m68k_op_moves_16_di , + (void*)m68k_op_moves_16_di , + (void*)m68k_op_moves_16_di , + (void*)m68k_op_moves_16_di , + (void*)m68k_op_moves_16_di , + (void*)m68k_op_moves_16_di , + (void*)m68k_op_moves_16_ix , + (void*)m68k_op_moves_16_ix , + (void*)m68k_op_moves_16_ix , + (void*)m68k_op_moves_16_ix , + (void*)m68k_op_moves_16_ix , + (void*)m68k_op_moves_16_ix , + (void*)m68k_op_moves_16_ix , + (void*)m68k_op_moves_16_ix , + (void*)m68k_op_moves_16_aw , + (void*)m68k_op_moves_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_moves_32_ai , + (void*)m68k_op_moves_32_ai , + (void*)m68k_op_moves_32_ai , + (void*)m68k_op_moves_32_ai , + (void*)m68k_op_moves_32_ai , + (void*)m68k_op_moves_32_ai , + (void*)m68k_op_moves_32_ai , + (void*)m68k_op_moves_32_ai , + (void*)m68k_op_moves_32_pi , + (void*)m68k_op_moves_32_pi , + (void*)m68k_op_moves_32_pi , + (void*)m68k_op_moves_32_pi , + (void*)m68k_op_moves_32_pi , + (void*)m68k_op_moves_32_pi , + (void*)m68k_op_moves_32_pi , + (void*)m68k_op_moves_32_pi , + (void*)m68k_op_moves_32_pd , + (void*)m68k_op_moves_32_pd , + (void*)m68k_op_moves_32_pd , + (void*)m68k_op_moves_32_pd , + (void*)m68k_op_moves_32_pd , + (void*)m68k_op_moves_32_pd , + (void*)m68k_op_moves_32_pd , + (void*)m68k_op_moves_32_pd , + (void*)m68k_op_moves_32_di , + (void*)m68k_op_moves_32_di , + (void*)m68k_op_moves_32_di , + (void*)m68k_op_moves_32_di , + (void*)m68k_op_moves_32_di , + (void*)m68k_op_moves_32_di , + (void*)m68k_op_moves_32_di , + (void*)m68k_op_moves_32_di , + (void*)m68k_op_moves_32_ix , + (void*)m68k_op_moves_32_ix , + (void*)m68k_op_moves_32_ix , + (void*)m68k_op_moves_32_ix , + (void*)m68k_op_moves_32_ix , + (void*)m68k_op_moves_32_ix , + (void*)m68k_op_moves_32_ix , + (void*)m68k_op_moves_32_ix , + (void*)m68k_op_moves_32_aw , + (void*)m68k_op_moves_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cas_32_ai , + (void*)m68k_op_cas_32_ai , + (void*)m68k_op_cas_32_ai , + (void*)m68k_op_cas_32_ai , + (void*)m68k_op_cas_32_ai , + (void*)m68k_op_cas_32_ai , + (void*)m68k_op_cas_32_ai , + (void*)m68k_op_cas_32_ai , + (void*)m68k_op_cas_32_pi , + (void*)m68k_op_cas_32_pi , + (void*)m68k_op_cas_32_pi , + (void*)m68k_op_cas_32_pi , + (void*)m68k_op_cas_32_pi , + (void*)m68k_op_cas_32_pi , + (void*)m68k_op_cas_32_pi , + (void*)m68k_op_cas_32_pi , + (void*)m68k_op_cas_32_pd , + (void*)m68k_op_cas_32_pd , + (void*)m68k_op_cas_32_pd , + (void*)m68k_op_cas_32_pd , + (void*)m68k_op_cas_32_pd , + (void*)m68k_op_cas_32_pd , + (void*)m68k_op_cas_32_pd , + (void*)m68k_op_cas_32_pd , + (void*)m68k_op_cas_32_di , + (void*)m68k_op_cas_32_di , + (void*)m68k_op_cas_32_di , + (void*)m68k_op_cas_32_di , + (void*)m68k_op_cas_32_di , + (void*)m68k_op_cas_32_di , + (void*)m68k_op_cas_32_di , + (void*)m68k_op_cas_32_di , + (void*)m68k_op_cas_32_ix , + (void*)m68k_op_cas_32_ix , + (void*)m68k_op_cas_32_ix , + (void*)m68k_op_cas_32_ix , + (void*)m68k_op_cas_32_ix , + (void*)m68k_op_cas_32_ix , + (void*)m68k_op_cas_32_ix , + (void*)m68k_op_cas_32_ix , + (void*)m68k_op_cas_32_aw , + (void*)m68k_op_cas_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cas2_32 , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_btst_32_r_d , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_movep_16_er , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_ai , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi , + (void*)m68k_op_btst_8_r_pi7 , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd , + (void*)m68k_op_btst_8_r_pd7 , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_di , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_ix , + (void*)m68k_op_btst_8_r_aw , + (void*)m68k_op_btst_8_r_al , + (void*)m68k_op_btst_8_r_pcdi , + (void*)m68k_op_btst_8_r_pcix , + (void*)m68k_op_btst_8_r_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_bchg_32_r_d , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_movep_32_er , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_ai , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi , + (void*)m68k_op_bchg_8_r_pi7 , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd , + (void*)m68k_op_bchg_8_r_pd7 , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_di , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_ix , + (void*)m68k_op_bchg_8_r_aw , + (void*)m68k_op_bchg_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_bclr_32_r_d , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_movep_16_re , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_ai , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi , + (void*)m68k_op_bclr_8_r_pi7 , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd , + (void*)m68k_op_bclr_8_r_pd7 , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_di , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_ix , + (void*)m68k_op_bclr_8_r_aw , + (void*)m68k_op_bclr_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_bset_32_r_d , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_movep_32_re , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_ai , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi , + (void*)m68k_op_bset_8_r_pi7 , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd , + (void*)m68k_op_bset_8_r_pd7 , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_di , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_ix , + (void*)m68k_op_bset_8_r_aw , + (void*)m68k_op_bset_8_r_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi7 , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd7 , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_aw , + (void*)m68k_op_move_8_d_al , + (void*)m68k_op_move_8_d_pcdi , + (void*)m68k_op_move_8_d_pcix , + (void*)m68k_op_move_8_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi7 , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd7 , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_aw , + (void*)m68k_op_move_8_ai_al , + (void*)m68k_op_move_8_ai_pcdi , + (void*)m68k_op_move_8_ai_pcix , + (void*)m68k_op_move_8_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi7 , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd7 , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_aw , + (void*)m68k_op_move_8_pi_al , + (void*)m68k_op_move_8_pi_pcdi , + (void*)m68k_op_move_8_pi_pcix , + (void*)m68k_op_move_8_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi7 , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd7 , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_aw , + (void*)m68k_op_move_8_pd_al , + (void*)m68k_op_move_8_pd_pcdi , + (void*)m68k_op_move_8_pd_pcix , + (void*)m68k_op_move_8_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi7 , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd7 , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_aw , + (void*)m68k_op_move_8_di_al , + (void*)m68k_op_move_8_di_pcdi , + (void*)m68k_op_move_8_di_pcix , + (void*)m68k_op_move_8_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi7 , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd7 , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_aw , + (void*)m68k_op_move_8_ix_al , + (void*)m68k_op_move_8_ix_pcdi , + (void*)m68k_op_move_8_ix_pcix , + (void*)m68k_op_move_8_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_aw_d , + (void*)m68k_op_move_8_aw_d , + (void*)m68k_op_move_8_aw_d , + (void*)m68k_op_move_8_aw_d , + (void*)m68k_op_move_8_aw_d , + (void*)m68k_op_move_8_aw_d , + (void*)m68k_op_move_8_aw_d , + (void*)m68k_op_move_8_aw_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_aw_ai , + (void*)m68k_op_move_8_aw_ai , + (void*)m68k_op_move_8_aw_ai , + (void*)m68k_op_move_8_aw_ai , + (void*)m68k_op_move_8_aw_ai , + (void*)m68k_op_move_8_aw_ai , + (void*)m68k_op_move_8_aw_ai , + (void*)m68k_op_move_8_aw_ai , + (void*)m68k_op_move_8_aw_pi , + (void*)m68k_op_move_8_aw_pi , + (void*)m68k_op_move_8_aw_pi , + (void*)m68k_op_move_8_aw_pi , + (void*)m68k_op_move_8_aw_pi , + (void*)m68k_op_move_8_aw_pi , + (void*)m68k_op_move_8_aw_pi , + (void*)m68k_op_move_8_aw_pi7 , + (void*)m68k_op_move_8_aw_pd , + (void*)m68k_op_move_8_aw_pd , + (void*)m68k_op_move_8_aw_pd , + (void*)m68k_op_move_8_aw_pd , + (void*)m68k_op_move_8_aw_pd , + (void*)m68k_op_move_8_aw_pd , + (void*)m68k_op_move_8_aw_pd , + (void*)m68k_op_move_8_aw_pd7 , + (void*)m68k_op_move_8_aw_di , + (void*)m68k_op_move_8_aw_di , + (void*)m68k_op_move_8_aw_di , + (void*)m68k_op_move_8_aw_di , + (void*)m68k_op_move_8_aw_di , + (void*)m68k_op_move_8_aw_di , + (void*)m68k_op_move_8_aw_di , + (void*)m68k_op_move_8_aw_di , + (void*)m68k_op_move_8_aw_ix , + (void*)m68k_op_move_8_aw_ix , + (void*)m68k_op_move_8_aw_ix , + (void*)m68k_op_move_8_aw_ix , + (void*)m68k_op_move_8_aw_ix , + (void*)m68k_op_move_8_aw_ix , + (void*)m68k_op_move_8_aw_ix , + (void*)m68k_op_move_8_aw_ix , + (void*)m68k_op_move_8_aw_aw , + (void*)m68k_op_move_8_aw_al , + (void*)m68k_op_move_8_aw_pcdi , + (void*)m68k_op_move_8_aw_pcix , + (void*)m68k_op_move_8_aw_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi7 , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd7 , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_aw , + (void*)m68k_op_move_8_d_al , + (void*)m68k_op_move_8_d_pcdi , + (void*)m68k_op_move_8_d_pcix , + (void*)m68k_op_move_8_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi7 , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd7 , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_aw , + (void*)m68k_op_move_8_ai_al , + (void*)m68k_op_move_8_ai_pcdi , + (void*)m68k_op_move_8_ai_pcix , + (void*)m68k_op_move_8_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi7 , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd7 , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_aw , + (void*)m68k_op_move_8_pi_al , + (void*)m68k_op_move_8_pi_pcdi , + (void*)m68k_op_move_8_pi_pcix , + (void*)m68k_op_move_8_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi7 , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd7 , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_aw , + (void*)m68k_op_move_8_pd_al , + (void*)m68k_op_move_8_pd_pcdi , + (void*)m68k_op_move_8_pd_pcix , + (void*)m68k_op_move_8_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi7 , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd7 , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_aw , + (void*)m68k_op_move_8_di_al , + (void*)m68k_op_move_8_di_pcdi , + (void*)m68k_op_move_8_di_pcix , + (void*)m68k_op_move_8_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi7 , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd7 , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_aw , + (void*)m68k_op_move_8_ix_al , + (void*)m68k_op_move_8_ix_pcdi , + (void*)m68k_op_move_8_ix_pcix , + (void*)m68k_op_move_8_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_al_d , + (void*)m68k_op_move_8_al_d , + (void*)m68k_op_move_8_al_d , + (void*)m68k_op_move_8_al_d , + (void*)m68k_op_move_8_al_d , + (void*)m68k_op_move_8_al_d , + (void*)m68k_op_move_8_al_d , + (void*)m68k_op_move_8_al_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_al_ai , + (void*)m68k_op_move_8_al_ai , + (void*)m68k_op_move_8_al_ai , + (void*)m68k_op_move_8_al_ai , + (void*)m68k_op_move_8_al_ai , + (void*)m68k_op_move_8_al_ai , + (void*)m68k_op_move_8_al_ai , + (void*)m68k_op_move_8_al_ai , + (void*)m68k_op_move_8_al_pi , + (void*)m68k_op_move_8_al_pi , + (void*)m68k_op_move_8_al_pi , + (void*)m68k_op_move_8_al_pi , + (void*)m68k_op_move_8_al_pi , + (void*)m68k_op_move_8_al_pi , + (void*)m68k_op_move_8_al_pi , + (void*)m68k_op_move_8_al_pi7 , + (void*)m68k_op_move_8_al_pd , + (void*)m68k_op_move_8_al_pd , + (void*)m68k_op_move_8_al_pd , + (void*)m68k_op_move_8_al_pd , + (void*)m68k_op_move_8_al_pd , + (void*)m68k_op_move_8_al_pd , + (void*)m68k_op_move_8_al_pd , + (void*)m68k_op_move_8_al_pd7 , + (void*)m68k_op_move_8_al_di , + (void*)m68k_op_move_8_al_di , + (void*)m68k_op_move_8_al_di , + (void*)m68k_op_move_8_al_di , + (void*)m68k_op_move_8_al_di , + (void*)m68k_op_move_8_al_di , + (void*)m68k_op_move_8_al_di , + (void*)m68k_op_move_8_al_di , + (void*)m68k_op_move_8_al_ix , + (void*)m68k_op_move_8_al_ix , + (void*)m68k_op_move_8_al_ix , + (void*)m68k_op_move_8_al_ix , + (void*)m68k_op_move_8_al_ix , + (void*)m68k_op_move_8_al_ix , + (void*)m68k_op_move_8_al_ix , + (void*)m68k_op_move_8_al_ix , + (void*)m68k_op_move_8_al_aw , + (void*)m68k_op_move_8_al_al , + (void*)m68k_op_move_8_al_pcdi , + (void*)m68k_op_move_8_al_pcix , + (void*)m68k_op_move_8_al_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi7 , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd7 , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_aw , + (void*)m68k_op_move_8_d_al , + (void*)m68k_op_move_8_d_pcdi , + (void*)m68k_op_move_8_d_pcix , + (void*)m68k_op_move_8_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi7 , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd7 , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_aw , + (void*)m68k_op_move_8_ai_al , + (void*)m68k_op_move_8_ai_pcdi , + (void*)m68k_op_move_8_ai_pcix , + (void*)m68k_op_move_8_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi7 , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd7 , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_aw , + (void*)m68k_op_move_8_pi_al , + (void*)m68k_op_move_8_pi_pcdi , + (void*)m68k_op_move_8_pi_pcix , + (void*)m68k_op_move_8_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi7 , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd7 , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_aw , + (void*)m68k_op_move_8_pd_al , + (void*)m68k_op_move_8_pd_pcdi , + (void*)m68k_op_move_8_pd_pcix , + (void*)m68k_op_move_8_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi7 , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd7 , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_aw , + (void*)m68k_op_move_8_di_al , + (void*)m68k_op_move_8_di_pcdi , + (void*)m68k_op_move_8_di_pcix , + (void*)m68k_op_move_8_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi7 , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd7 , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_aw , + (void*)m68k_op_move_8_ix_al , + (void*)m68k_op_move_8_ix_pcdi , + (void*)m68k_op_move_8_ix_pcix , + (void*)m68k_op_move_8_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi7 , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd7 , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_aw , + (void*)m68k_op_move_8_d_al , + (void*)m68k_op_move_8_d_pcdi , + (void*)m68k_op_move_8_d_pcix , + (void*)m68k_op_move_8_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi7 , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd7 , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_aw , + (void*)m68k_op_move_8_ai_al , + (void*)m68k_op_move_8_ai_pcdi , + (void*)m68k_op_move_8_ai_pcix , + (void*)m68k_op_move_8_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi7 , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd7 , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_aw , + (void*)m68k_op_move_8_pi_al , + (void*)m68k_op_move_8_pi_pcdi , + (void*)m68k_op_move_8_pi_pcix , + (void*)m68k_op_move_8_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi7 , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd7 , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_aw , + (void*)m68k_op_move_8_pd_al , + (void*)m68k_op_move_8_pd_pcdi , + (void*)m68k_op_move_8_pd_pcix , + (void*)m68k_op_move_8_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi7 , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd7 , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_aw , + (void*)m68k_op_move_8_di_al , + (void*)m68k_op_move_8_di_pcdi , + (void*)m68k_op_move_8_di_pcix , + (void*)m68k_op_move_8_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi7 , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd7 , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_aw , + (void*)m68k_op_move_8_ix_al , + (void*)m68k_op_move_8_ix_pcdi , + (void*)m68k_op_move_8_ix_pcix , + (void*)m68k_op_move_8_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi7 , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd7 , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_aw , + (void*)m68k_op_move_8_d_al , + (void*)m68k_op_move_8_d_pcdi , + (void*)m68k_op_move_8_d_pcix , + (void*)m68k_op_move_8_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi7 , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd7 , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_aw , + (void*)m68k_op_move_8_ai_al , + (void*)m68k_op_move_8_ai_pcdi , + (void*)m68k_op_move_8_ai_pcix , + (void*)m68k_op_move_8_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi7 , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd7 , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_aw , + (void*)m68k_op_move_8_pi_al , + (void*)m68k_op_move_8_pi_pcdi , + (void*)m68k_op_move_8_pi_pcix , + (void*)m68k_op_move_8_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi7 , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd7 , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_aw , + (void*)m68k_op_move_8_pd_al , + (void*)m68k_op_move_8_pd_pcdi , + (void*)m68k_op_move_8_pd_pcix , + (void*)m68k_op_move_8_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi7 , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd7 , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_aw , + (void*)m68k_op_move_8_di_al , + (void*)m68k_op_move_8_di_pcdi , + (void*)m68k_op_move_8_di_pcix , + (void*)m68k_op_move_8_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi7 , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd7 , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_aw , + (void*)m68k_op_move_8_ix_al , + (void*)m68k_op_move_8_ix_pcdi , + (void*)m68k_op_move_8_ix_pcix , + (void*)m68k_op_move_8_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi7 , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd7 , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_aw , + (void*)m68k_op_move_8_d_al , + (void*)m68k_op_move_8_d_pcdi , + (void*)m68k_op_move_8_d_pcix , + (void*)m68k_op_move_8_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi7 , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd7 , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_aw , + (void*)m68k_op_move_8_ai_al , + (void*)m68k_op_move_8_ai_pcdi , + (void*)m68k_op_move_8_ai_pcix , + (void*)m68k_op_move_8_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi7 , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd7 , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_aw , + (void*)m68k_op_move_8_pi_al , + (void*)m68k_op_move_8_pi_pcdi , + (void*)m68k_op_move_8_pi_pcix , + (void*)m68k_op_move_8_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi7 , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd7 , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_aw , + (void*)m68k_op_move_8_pd_al , + (void*)m68k_op_move_8_pd_pcdi , + (void*)m68k_op_move_8_pd_pcix , + (void*)m68k_op_move_8_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi7 , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd7 , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_aw , + (void*)m68k_op_move_8_di_al , + (void*)m68k_op_move_8_di_pcdi , + (void*)m68k_op_move_8_di_pcix , + (void*)m68k_op_move_8_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi7 , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd7 , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_aw , + (void*)m68k_op_move_8_ix_al , + (void*)m68k_op_move_8_ix_pcdi , + (void*)m68k_op_move_8_ix_pcix , + (void*)m68k_op_move_8_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi7 , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd7 , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_aw , + (void*)m68k_op_move_8_d_al , + (void*)m68k_op_move_8_d_pcdi , + (void*)m68k_op_move_8_d_pcix , + (void*)m68k_op_move_8_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi7 , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd7 , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_aw , + (void*)m68k_op_move_8_ai_al , + (void*)m68k_op_move_8_ai_pcdi , + (void*)m68k_op_move_8_ai_pcix , + (void*)m68k_op_move_8_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_move_8_pi_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_ai , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi , + (void*)m68k_op_move_8_pi_pi7 , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd , + (void*)m68k_op_move_8_pi_pd7 , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_di , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_ix , + (void*)m68k_op_move_8_pi_aw , + (void*)m68k_op_move_8_pi_al , + (void*)m68k_op_move_8_pi_pcdi , + (void*)m68k_op_move_8_pi_pcix , + (void*)m68k_op_move_8_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_move_8_pd_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_ai , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi , + (void*)m68k_op_move_8_pd_pi7 , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd , + (void*)m68k_op_move_8_pd_pd7 , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_di , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_ix , + (void*)m68k_op_move_8_pd_aw , + (void*)m68k_op_move_8_pd_al , + (void*)m68k_op_move_8_pd_pcdi , + (void*)m68k_op_move_8_pd_pcix , + (void*)m68k_op_move_8_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi7 , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd7 , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_aw , + (void*)m68k_op_move_8_di_al , + (void*)m68k_op_move_8_di_pcdi , + (void*)m68k_op_move_8_di_pcix , + (void*)m68k_op_move_8_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi7 , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd7 , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_aw , + (void*)m68k_op_move_8_ix_al , + (void*)m68k_op_move_8_ix_pcdi , + (void*)m68k_op_move_8_ix_pcix , + (void*)m68k_op_move_8_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_move_8_d_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_ai , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi , + (void*)m68k_op_move_8_d_pi7 , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd , + (void*)m68k_op_move_8_d_pd7 , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_di , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_ix , + (void*)m68k_op_move_8_d_aw , + (void*)m68k_op_move_8_d_al , + (void*)m68k_op_move_8_d_pcdi , + (void*)m68k_op_move_8_d_pcix , + (void*)m68k_op_move_8_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_move_8_ai_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_ai , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi , + (void*)m68k_op_move_8_ai_pi7 , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd , + (void*)m68k_op_move_8_ai_pd7 , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_di , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_ix , + (void*)m68k_op_move_8_ai_aw , + (void*)m68k_op_move_8_ai_al , + (void*)m68k_op_move_8_ai_pcdi , + (void*)m68k_op_move_8_ai_pcix , + (void*)m68k_op_move_8_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi7_d , + (void*)m68k_op_move_8_pi7_d , + (void*)m68k_op_move_8_pi7_d , + (void*)m68k_op_move_8_pi7_d , + (void*)m68k_op_move_8_pi7_d , + (void*)m68k_op_move_8_pi7_d , + (void*)m68k_op_move_8_pi7_d , + (void*)m68k_op_move_8_pi7_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pi7_ai , + (void*)m68k_op_move_8_pi7_ai , + (void*)m68k_op_move_8_pi7_ai , + (void*)m68k_op_move_8_pi7_ai , + (void*)m68k_op_move_8_pi7_ai , + (void*)m68k_op_move_8_pi7_ai , + (void*)m68k_op_move_8_pi7_ai , + (void*)m68k_op_move_8_pi7_ai , + (void*)m68k_op_move_8_pi7_pi , + (void*)m68k_op_move_8_pi7_pi , + (void*)m68k_op_move_8_pi7_pi , + (void*)m68k_op_move_8_pi7_pi , + (void*)m68k_op_move_8_pi7_pi , + (void*)m68k_op_move_8_pi7_pi , + (void*)m68k_op_move_8_pi7_pi , + (void*)m68k_op_move_8_pi7_pi7 , + (void*)m68k_op_move_8_pi7_pd , + (void*)m68k_op_move_8_pi7_pd , + (void*)m68k_op_move_8_pi7_pd , + (void*)m68k_op_move_8_pi7_pd , + (void*)m68k_op_move_8_pi7_pd , + (void*)m68k_op_move_8_pi7_pd , + (void*)m68k_op_move_8_pi7_pd , + (void*)m68k_op_move_8_pi7_pd7 , + (void*)m68k_op_move_8_pi7_di , + (void*)m68k_op_move_8_pi7_di , + (void*)m68k_op_move_8_pi7_di , + (void*)m68k_op_move_8_pi7_di , + (void*)m68k_op_move_8_pi7_di , + (void*)m68k_op_move_8_pi7_di , + (void*)m68k_op_move_8_pi7_di , + (void*)m68k_op_move_8_pi7_di , + (void*)m68k_op_move_8_pi7_ix , + (void*)m68k_op_move_8_pi7_ix , + (void*)m68k_op_move_8_pi7_ix , + (void*)m68k_op_move_8_pi7_ix , + (void*)m68k_op_move_8_pi7_ix , + (void*)m68k_op_move_8_pi7_ix , + (void*)m68k_op_move_8_pi7_ix , + (void*)m68k_op_move_8_pi7_ix , + (void*)m68k_op_move_8_pi7_aw , + (void*)m68k_op_move_8_pi7_al , + (void*)m68k_op_move_8_pi7_pcdi , + (void*)m68k_op_move_8_pi7_pcix , + (void*)m68k_op_move_8_pi7_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd7_d , + (void*)m68k_op_move_8_pd7_d , + (void*)m68k_op_move_8_pd7_d , + (void*)m68k_op_move_8_pd7_d , + (void*)m68k_op_move_8_pd7_d , + (void*)m68k_op_move_8_pd7_d , + (void*)m68k_op_move_8_pd7_d , + (void*)m68k_op_move_8_pd7_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_pd7_ai , + (void*)m68k_op_move_8_pd7_ai , + (void*)m68k_op_move_8_pd7_ai , + (void*)m68k_op_move_8_pd7_ai , + (void*)m68k_op_move_8_pd7_ai , + (void*)m68k_op_move_8_pd7_ai , + (void*)m68k_op_move_8_pd7_ai , + (void*)m68k_op_move_8_pd7_ai , + (void*)m68k_op_move_8_pd7_pi , + (void*)m68k_op_move_8_pd7_pi , + (void*)m68k_op_move_8_pd7_pi , + (void*)m68k_op_move_8_pd7_pi , + (void*)m68k_op_move_8_pd7_pi , + (void*)m68k_op_move_8_pd7_pi , + (void*)m68k_op_move_8_pd7_pi , + (void*)m68k_op_move_8_pd7_pi7 , + (void*)m68k_op_move_8_pd7_pd , + (void*)m68k_op_move_8_pd7_pd , + (void*)m68k_op_move_8_pd7_pd , + (void*)m68k_op_move_8_pd7_pd , + (void*)m68k_op_move_8_pd7_pd , + (void*)m68k_op_move_8_pd7_pd , + (void*)m68k_op_move_8_pd7_pd , + (void*)m68k_op_move_8_pd7_pd7 , + (void*)m68k_op_move_8_pd7_di , + (void*)m68k_op_move_8_pd7_di , + (void*)m68k_op_move_8_pd7_di , + (void*)m68k_op_move_8_pd7_di , + (void*)m68k_op_move_8_pd7_di , + (void*)m68k_op_move_8_pd7_di , + (void*)m68k_op_move_8_pd7_di , + (void*)m68k_op_move_8_pd7_di , + (void*)m68k_op_move_8_pd7_ix , + (void*)m68k_op_move_8_pd7_ix , + (void*)m68k_op_move_8_pd7_ix , + (void*)m68k_op_move_8_pd7_ix , + (void*)m68k_op_move_8_pd7_ix , + (void*)m68k_op_move_8_pd7_ix , + (void*)m68k_op_move_8_pd7_ix , + (void*)m68k_op_move_8_pd7_ix , + (void*)m68k_op_move_8_pd7_aw , + (void*)m68k_op_move_8_pd7_al , + (void*)m68k_op_move_8_pd7_pcdi , + (void*)m68k_op_move_8_pd7_pcix , + (void*)m68k_op_move_8_pd7_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_move_8_di_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_ai , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi , + (void*)m68k_op_move_8_di_pi7 , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd , + (void*)m68k_op_move_8_di_pd7 , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_di , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_ix , + (void*)m68k_op_move_8_di_aw , + (void*)m68k_op_move_8_di_al , + (void*)m68k_op_move_8_di_pcdi , + (void*)m68k_op_move_8_di_pcix , + (void*)m68k_op_move_8_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_move_8_ix_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_ai , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi , + (void*)m68k_op_move_8_ix_pi7 , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd , + (void*)m68k_op_move_8_ix_pd7 , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_di , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_ix , + (void*)m68k_op_move_8_ix_aw , + (void*)m68k_op_move_8_ix_al , + (void*)m68k_op_move_8_ix_pcdi , + (void*)m68k_op_move_8_ix_pcix , + (void*)m68k_op_move_8_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_aw , + (void*)m68k_op_move_32_d_al , + (void*)m68k_op_move_32_d_pcdi , + (void*)m68k_op_move_32_d_pcix , + (void*)m68k_op_move_32_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_aw , + (void*)m68k_op_movea_32_al , + (void*)m68k_op_movea_32_pcdi , + (void*)m68k_op_movea_32_pcix , + (void*)m68k_op_movea_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_aw , + (void*)m68k_op_move_32_ai_al , + (void*)m68k_op_move_32_ai_pcdi , + (void*)m68k_op_move_32_ai_pcix , + (void*)m68k_op_move_32_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_aw , + (void*)m68k_op_move_32_pi_al , + (void*)m68k_op_move_32_pi_pcdi , + (void*)m68k_op_move_32_pi_pcix , + (void*)m68k_op_move_32_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_aw , + (void*)m68k_op_move_32_pd_al , + (void*)m68k_op_move_32_pd_pcdi , + (void*)m68k_op_move_32_pd_pcix , + (void*)m68k_op_move_32_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_aw , + (void*)m68k_op_move_32_di_al , + (void*)m68k_op_move_32_di_pcdi , + (void*)m68k_op_move_32_di_pcix , + (void*)m68k_op_move_32_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_aw , + (void*)m68k_op_move_32_ix_al , + (void*)m68k_op_move_32_ix_pcdi , + (void*)m68k_op_move_32_ix_pcix , + (void*)m68k_op_move_32_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_aw_d , + (void*)m68k_op_move_32_aw_d , + (void*)m68k_op_move_32_aw_d , + (void*)m68k_op_move_32_aw_d , + (void*)m68k_op_move_32_aw_d , + (void*)m68k_op_move_32_aw_d , + (void*)m68k_op_move_32_aw_d , + (void*)m68k_op_move_32_aw_d , + (void*)m68k_op_move_32_aw_a , + (void*)m68k_op_move_32_aw_a , + (void*)m68k_op_move_32_aw_a , + (void*)m68k_op_move_32_aw_a , + (void*)m68k_op_move_32_aw_a , + (void*)m68k_op_move_32_aw_a , + (void*)m68k_op_move_32_aw_a , + (void*)m68k_op_move_32_aw_a , + (void*)m68k_op_move_32_aw_ai , + (void*)m68k_op_move_32_aw_ai , + (void*)m68k_op_move_32_aw_ai , + (void*)m68k_op_move_32_aw_ai , + (void*)m68k_op_move_32_aw_ai , + (void*)m68k_op_move_32_aw_ai , + (void*)m68k_op_move_32_aw_ai , + (void*)m68k_op_move_32_aw_ai , + (void*)m68k_op_move_32_aw_pi , + (void*)m68k_op_move_32_aw_pi , + (void*)m68k_op_move_32_aw_pi , + (void*)m68k_op_move_32_aw_pi , + (void*)m68k_op_move_32_aw_pi , + (void*)m68k_op_move_32_aw_pi , + (void*)m68k_op_move_32_aw_pi , + (void*)m68k_op_move_32_aw_pi , + (void*)m68k_op_move_32_aw_pd , + (void*)m68k_op_move_32_aw_pd , + (void*)m68k_op_move_32_aw_pd , + (void*)m68k_op_move_32_aw_pd , + (void*)m68k_op_move_32_aw_pd , + (void*)m68k_op_move_32_aw_pd , + (void*)m68k_op_move_32_aw_pd , + (void*)m68k_op_move_32_aw_pd , + (void*)m68k_op_move_32_aw_di , + (void*)m68k_op_move_32_aw_di , + (void*)m68k_op_move_32_aw_di , + (void*)m68k_op_move_32_aw_di , + (void*)m68k_op_move_32_aw_di , + (void*)m68k_op_move_32_aw_di , + (void*)m68k_op_move_32_aw_di , + (void*)m68k_op_move_32_aw_di , + (void*)m68k_op_move_32_aw_ix , + (void*)m68k_op_move_32_aw_ix , + (void*)m68k_op_move_32_aw_ix , + (void*)m68k_op_move_32_aw_ix , + (void*)m68k_op_move_32_aw_ix , + (void*)m68k_op_move_32_aw_ix , + (void*)m68k_op_move_32_aw_ix , + (void*)m68k_op_move_32_aw_ix , + (void*)m68k_op_move_32_aw_aw , + (void*)m68k_op_move_32_aw_al , + (void*)m68k_op_move_32_aw_pcdi , + (void*)m68k_op_move_32_aw_pcix , + (void*)m68k_op_move_32_aw_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_aw , + (void*)m68k_op_move_32_d_al , + (void*)m68k_op_move_32_d_pcdi , + (void*)m68k_op_move_32_d_pcix , + (void*)m68k_op_move_32_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_aw , + (void*)m68k_op_movea_32_al , + (void*)m68k_op_movea_32_pcdi , + (void*)m68k_op_movea_32_pcix , + (void*)m68k_op_movea_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_aw , + (void*)m68k_op_move_32_ai_al , + (void*)m68k_op_move_32_ai_pcdi , + (void*)m68k_op_move_32_ai_pcix , + (void*)m68k_op_move_32_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_aw , + (void*)m68k_op_move_32_pi_al , + (void*)m68k_op_move_32_pi_pcdi , + (void*)m68k_op_move_32_pi_pcix , + (void*)m68k_op_move_32_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_aw , + (void*)m68k_op_move_32_pd_al , + (void*)m68k_op_move_32_pd_pcdi , + (void*)m68k_op_move_32_pd_pcix , + (void*)m68k_op_move_32_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_aw , + (void*)m68k_op_move_32_di_al , + (void*)m68k_op_move_32_di_pcdi , + (void*)m68k_op_move_32_di_pcix , + (void*)m68k_op_move_32_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_aw , + (void*)m68k_op_move_32_ix_al , + (void*)m68k_op_move_32_ix_pcdi , + (void*)m68k_op_move_32_ix_pcix , + (void*)m68k_op_move_32_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_al_d , + (void*)m68k_op_move_32_al_d , + (void*)m68k_op_move_32_al_d , + (void*)m68k_op_move_32_al_d , + (void*)m68k_op_move_32_al_d , + (void*)m68k_op_move_32_al_d , + (void*)m68k_op_move_32_al_d , + (void*)m68k_op_move_32_al_d , + (void*)m68k_op_move_32_al_a , + (void*)m68k_op_move_32_al_a , + (void*)m68k_op_move_32_al_a , + (void*)m68k_op_move_32_al_a , + (void*)m68k_op_move_32_al_a , + (void*)m68k_op_move_32_al_a , + (void*)m68k_op_move_32_al_a , + (void*)m68k_op_move_32_al_a , + (void*)m68k_op_move_32_al_ai , + (void*)m68k_op_move_32_al_ai , + (void*)m68k_op_move_32_al_ai , + (void*)m68k_op_move_32_al_ai , + (void*)m68k_op_move_32_al_ai , + (void*)m68k_op_move_32_al_ai , + (void*)m68k_op_move_32_al_ai , + (void*)m68k_op_move_32_al_ai , + (void*)m68k_op_move_32_al_pi , + (void*)m68k_op_move_32_al_pi , + (void*)m68k_op_move_32_al_pi , + (void*)m68k_op_move_32_al_pi , + (void*)m68k_op_move_32_al_pi , + (void*)m68k_op_move_32_al_pi , + (void*)m68k_op_move_32_al_pi , + (void*)m68k_op_move_32_al_pi , + (void*)m68k_op_move_32_al_pd , + (void*)m68k_op_move_32_al_pd , + (void*)m68k_op_move_32_al_pd , + (void*)m68k_op_move_32_al_pd , + (void*)m68k_op_move_32_al_pd , + (void*)m68k_op_move_32_al_pd , + (void*)m68k_op_move_32_al_pd , + (void*)m68k_op_move_32_al_pd , + (void*)m68k_op_move_32_al_di , + (void*)m68k_op_move_32_al_di , + (void*)m68k_op_move_32_al_di , + (void*)m68k_op_move_32_al_di , + (void*)m68k_op_move_32_al_di , + (void*)m68k_op_move_32_al_di , + (void*)m68k_op_move_32_al_di , + (void*)m68k_op_move_32_al_di , + (void*)m68k_op_move_32_al_ix , + (void*)m68k_op_move_32_al_ix , + (void*)m68k_op_move_32_al_ix , + (void*)m68k_op_move_32_al_ix , + (void*)m68k_op_move_32_al_ix , + (void*)m68k_op_move_32_al_ix , + (void*)m68k_op_move_32_al_ix , + (void*)m68k_op_move_32_al_ix , + (void*)m68k_op_move_32_al_aw , + (void*)m68k_op_move_32_al_al , + (void*)m68k_op_move_32_al_pcdi , + (void*)m68k_op_move_32_al_pcix , + (void*)m68k_op_move_32_al_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_aw , + (void*)m68k_op_move_32_d_al , + (void*)m68k_op_move_32_d_pcdi , + (void*)m68k_op_move_32_d_pcix , + (void*)m68k_op_move_32_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_aw , + (void*)m68k_op_movea_32_al , + (void*)m68k_op_movea_32_pcdi , + (void*)m68k_op_movea_32_pcix , + (void*)m68k_op_movea_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_aw , + (void*)m68k_op_move_32_ai_al , + (void*)m68k_op_move_32_ai_pcdi , + (void*)m68k_op_move_32_ai_pcix , + (void*)m68k_op_move_32_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_aw , + (void*)m68k_op_move_32_pi_al , + (void*)m68k_op_move_32_pi_pcdi , + (void*)m68k_op_move_32_pi_pcix , + (void*)m68k_op_move_32_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_aw , + (void*)m68k_op_move_32_pd_al , + (void*)m68k_op_move_32_pd_pcdi , + (void*)m68k_op_move_32_pd_pcix , + (void*)m68k_op_move_32_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_aw , + (void*)m68k_op_move_32_di_al , + (void*)m68k_op_move_32_di_pcdi , + (void*)m68k_op_move_32_di_pcix , + (void*)m68k_op_move_32_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_aw , + (void*)m68k_op_move_32_ix_al , + (void*)m68k_op_move_32_ix_pcdi , + (void*)m68k_op_move_32_ix_pcix , + (void*)m68k_op_move_32_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_aw , + (void*)m68k_op_move_32_d_al , + (void*)m68k_op_move_32_d_pcdi , + (void*)m68k_op_move_32_d_pcix , + (void*)m68k_op_move_32_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_aw , + (void*)m68k_op_movea_32_al , + (void*)m68k_op_movea_32_pcdi , + (void*)m68k_op_movea_32_pcix , + (void*)m68k_op_movea_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_aw , + (void*)m68k_op_move_32_ai_al , + (void*)m68k_op_move_32_ai_pcdi , + (void*)m68k_op_move_32_ai_pcix , + (void*)m68k_op_move_32_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_aw , + (void*)m68k_op_move_32_pi_al , + (void*)m68k_op_move_32_pi_pcdi , + (void*)m68k_op_move_32_pi_pcix , + (void*)m68k_op_move_32_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_aw , + (void*)m68k_op_move_32_pd_al , + (void*)m68k_op_move_32_pd_pcdi , + (void*)m68k_op_move_32_pd_pcix , + (void*)m68k_op_move_32_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_aw , + (void*)m68k_op_move_32_di_al , + (void*)m68k_op_move_32_di_pcdi , + (void*)m68k_op_move_32_di_pcix , + (void*)m68k_op_move_32_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_aw , + (void*)m68k_op_move_32_ix_al , + (void*)m68k_op_move_32_ix_pcdi , + (void*)m68k_op_move_32_ix_pcix , + (void*)m68k_op_move_32_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_aw , + (void*)m68k_op_move_32_d_al , + (void*)m68k_op_move_32_d_pcdi , + (void*)m68k_op_move_32_d_pcix , + (void*)m68k_op_move_32_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_aw , + (void*)m68k_op_movea_32_al , + (void*)m68k_op_movea_32_pcdi , + (void*)m68k_op_movea_32_pcix , + (void*)m68k_op_movea_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_aw , + (void*)m68k_op_move_32_ai_al , + (void*)m68k_op_move_32_ai_pcdi , + (void*)m68k_op_move_32_ai_pcix , + (void*)m68k_op_move_32_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_aw , + (void*)m68k_op_move_32_pi_al , + (void*)m68k_op_move_32_pi_pcdi , + (void*)m68k_op_move_32_pi_pcix , + (void*)m68k_op_move_32_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_aw , + (void*)m68k_op_move_32_pd_al , + (void*)m68k_op_move_32_pd_pcdi , + (void*)m68k_op_move_32_pd_pcix , + (void*)m68k_op_move_32_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_aw , + (void*)m68k_op_move_32_di_al , + (void*)m68k_op_move_32_di_pcdi , + (void*)m68k_op_move_32_di_pcix , + (void*)m68k_op_move_32_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_aw , + (void*)m68k_op_move_32_ix_al , + (void*)m68k_op_move_32_ix_pcdi , + (void*)m68k_op_move_32_ix_pcix , + (void*)m68k_op_move_32_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_aw , + (void*)m68k_op_move_32_d_al , + (void*)m68k_op_move_32_d_pcdi , + (void*)m68k_op_move_32_d_pcix , + (void*)m68k_op_move_32_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_aw , + (void*)m68k_op_movea_32_al , + (void*)m68k_op_movea_32_pcdi , + (void*)m68k_op_movea_32_pcix , + (void*)m68k_op_movea_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_aw , + (void*)m68k_op_move_32_ai_al , + (void*)m68k_op_move_32_ai_pcdi , + (void*)m68k_op_move_32_ai_pcix , + (void*)m68k_op_move_32_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_aw , + (void*)m68k_op_move_32_pi_al , + (void*)m68k_op_move_32_pi_pcdi , + (void*)m68k_op_move_32_pi_pcix , + (void*)m68k_op_move_32_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_aw , + (void*)m68k_op_move_32_pd_al , + (void*)m68k_op_move_32_pd_pcdi , + (void*)m68k_op_move_32_pd_pcix , + (void*)m68k_op_move_32_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_aw , + (void*)m68k_op_move_32_di_al , + (void*)m68k_op_move_32_di_pcdi , + (void*)m68k_op_move_32_di_pcix , + (void*)m68k_op_move_32_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_aw , + (void*)m68k_op_move_32_ix_al , + (void*)m68k_op_move_32_ix_pcdi , + (void*)m68k_op_move_32_ix_pcix , + (void*)m68k_op_move_32_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_aw , + (void*)m68k_op_move_32_d_al , + (void*)m68k_op_move_32_d_pcdi , + (void*)m68k_op_move_32_d_pcix , + (void*)m68k_op_move_32_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_aw , + (void*)m68k_op_movea_32_al , + (void*)m68k_op_movea_32_pcdi , + (void*)m68k_op_movea_32_pcix , + (void*)m68k_op_movea_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_aw , + (void*)m68k_op_move_32_ai_al , + (void*)m68k_op_move_32_ai_pcdi , + (void*)m68k_op_move_32_ai_pcix , + (void*)m68k_op_move_32_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_aw , + (void*)m68k_op_move_32_pi_al , + (void*)m68k_op_move_32_pi_pcdi , + (void*)m68k_op_move_32_pi_pcix , + (void*)m68k_op_move_32_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_aw , + (void*)m68k_op_move_32_pd_al , + (void*)m68k_op_move_32_pd_pcdi , + (void*)m68k_op_move_32_pd_pcix , + (void*)m68k_op_move_32_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_aw , + (void*)m68k_op_move_32_di_al , + (void*)m68k_op_move_32_di_pcdi , + (void*)m68k_op_move_32_di_pcix , + (void*)m68k_op_move_32_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_aw , + (void*)m68k_op_move_32_ix_al , + (void*)m68k_op_move_32_ix_pcdi , + (void*)m68k_op_move_32_ix_pcix , + (void*)m68k_op_move_32_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_d , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_a , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_ai , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pi , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_pd , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_di , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_ix , + (void*)m68k_op_move_32_d_aw , + (void*)m68k_op_move_32_d_al , + (void*)m68k_op_move_32_d_pcdi , + (void*)m68k_op_move_32_d_pcix , + (void*)m68k_op_move_32_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_d , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_a , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_ai , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pi , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_pd , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_di , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_ix , + (void*)m68k_op_movea_32_aw , + (void*)m68k_op_movea_32_al , + (void*)m68k_op_movea_32_pcdi , + (void*)m68k_op_movea_32_pcix , + (void*)m68k_op_movea_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_d , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_a , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_ai , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pi , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_pd , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_di , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_ix , + (void*)m68k_op_move_32_ai_aw , + (void*)m68k_op_move_32_ai_al , + (void*)m68k_op_move_32_ai_pcdi , + (void*)m68k_op_move_32_ai_pcix , + (void*)m68k_op_move_32_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_d , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_a , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_ai , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pi , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_pd , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_di , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_ix , + (void*)m68k_op_move_32_pi_aw , + (void*)m68k_op_move_32_pi_al , + (void*)m68k_op_move_32_pi_pcdi , + (void*)m68k_op_move_32_pi_pcix , + (void*)m68k_op_move_32_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_d , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_a , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_ai , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pi , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_pd , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_di , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_ix , + (void*)m68k_op_move_32_pd_aw , + (void*)m68k_op_move_32_pd_al , + (void*)m68k_op_move_32_pd_pcdi , + (void*)m68k_op_move_32_pd_pcix , + (void*)m68k_op_move_32_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_d , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_a , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_ai , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pi , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_pd , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_di , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_ix , + (void*)m68k_op_move_32_di_aw , + (void*)m68k_op_move_32_di_al , + (void*)m68k_op_move_32_di_pcdi , + (void*)m68k_op_move_32_di_pcix , + (void*)m68k_op_move_32_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_d , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_a , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_ai , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pi , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_pd , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_di , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_ix , + (void*)m68k_op_move_32_ix_aw , + (void*)m68k_op_move_32_ix_al , + (void*)m68k_op_move_32_ix_pcdi , + (void*)m68k_op_move_32_ix_pcix , + (void*)m68k_op_move_32_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_aw , + (void*)m68k_op_move_16_d_al , + (void*)m68k_op_move_16_d_pcdi , + (void*)m68k_op_move_16_d_pcix , + (void*)m68k_op_move_16_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_aw , + (void*)m68k_op_movea_16_al , + (void*)m68k_op_movea_16_pcdi , + (void*)m68k_op_movea_16_pcix , + (void*)m68k_op_movea_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_aw , + (void*)m68k_op_move_16_ai_al , + (void*)m68k_op_move_16_ai_pcdi , + (void*)m68k_op_move_16_ai_pcix , + (void*)m68k_op_move_16_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_aw , + (void*)m68k_op_move_16_pi_al , + (void*)m68k_op_move_16_pi_pcdi , + (void*)m68k_op_move_16_pi_pcix , + (void*)m68k_op_move_16_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_aw , + (void*)m68k_op_move_16_pd_al , + (void*)m68k_op_move_16_pd_pcdi , + (void*)m68k_op_move_16_pd_pcix , + (void*)m68k_op_move_16_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_aw , + (void*)m68k_op_move_16_di_al , + (void*)m68k_op_move_16_di_pcdi , + (void*)m68k_op_move_16_di_pcix , + (void*)m68k_op_move_16_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_aw , + (void*)m68k_op_move_16_ix_al , + (void*)m68k_op_move_16_ix_pcdi , + (void*)m68k_op_move_16_ix_pcix , + (void*)m68k_op_move_16_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_aw_d , + (void*)m68k_op_move_16_aw_d , + (void*)m68k_op_move_16_aw_d , + (void*)m68k_op_move_16_aw_d , + (void*)m68k_op_move_16_aw_d , + (void*)m68k_op_move_16_aw_d , + (void*)m68k_op_move_16_aw_d , + (void*)m68k_op_move_16_aw_d , + (void*)m68k_op_move_16_aw_a , + (void*)m68k_op_move_16_aw_a , + (void*)m68k_op_move_16_aw_a , + (void*)m68k_op_move_16_aw_a , + (void*)m68k_op_move_16_aw_a , + (void*)m68k_op_move_16_aw_a , + (void*)m68k_op_move_16_aw_a , + (void*)m68k_op_move_16_aw_a , + (void*)m68k_op_move_16_aw_ai , + (void*)m68k_op_move_16_aw_ai , + (void*)m68k_op_move_16_aw_ai , + (void*)m68k_op_move_16_aw_ai , + (void*)m68k_op_move_16_aw_ai , + (void*)m68k_op_move_16_aw_ai , + (void*)m68k_op_move_16_aw_ai , + (void*)m68k_op_move_16_aw_ai , + (void*)m68k_op_move_16_aw_pi , + (void*)m68k_op_move_16_aw_pi , + (void*)m68k_op_move_16_aw_pi , + (void*)m68k_op_move_16_aw_pi , + (void*)m68k_op_move_16_aw_pi , + (void*)m68k_op_move_16_aw_pi , + (void*)m68k_op_move_16_aw_pi , + (void*)m68k_op_move_16_aw_pi , + (void*)m68k_op_move_16_aw_pd , + (void*)m68k_op_move_16_aw_pd , + (void*)m68k_op_move_16_aw_pd , + (void*)m68k_op_move_16_aw_pd , + (void*)m68k_op_move_16_aw_pd , + (void*)m68k_op_move_16_aw_pd , + (void*)m68k_op_move_16_aw_pd , + (void*)m68k_op_move_16_aw_pd , + (void*)m68k_op_move_16_aw_di , + (void*)m68k_op_move_16_aw_di , + (void*)m68k_op_move_16_aw_di , + (void*)m68k_op_move_16_aw_di , + (void*)m68k_op_move_16_aw_di , + (void*)m68k_op_move_16_aw_di , + (void*)m68k_op_move_16_aw_di , + (void*)m68k_op_move_16_aw_di , + (void*)m68k_op_move_16_aw_ix , + (void*)m68k_op_move_16_aw_ix , + (void*)m68k_op_move_16_aw_ix , + (void*)m68k_op_move_16_aw_ix , + (void*)m68k_op_move_16_aw_ix , + (void*)m68k_op_move_16_aw_ix , + (void*)m68k_op_move_16_aw_ix , + (void*)m68k_op_move_16_aw_ix , + (void*)m68k_op_move_16_aw_aw , + (void*)m68k_op_move_16_aw_al , + (void*)m68k_op_move_16_aw_pcdi , + (void*)m68k_op_move_16_aw_pcix , + (void*)m68k_op_move_16_aw_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_aw , + (void*)m68k_op_move_16_d_al , + (void*)m68k_op_move_16_d_pcdi , + (void*)m68k_op_move_16_d_pcix , + (void*)m68k_op_move_16_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_aw , + (void*)m68k_op_movea_16_al , + (void*)m68k_op_movea_16_pcdi , + (void*)m68k_op_movea_16_pcix , + (void*)m68k_op_movea_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_aw , + (void*)m68k_op_move_16_ai_al , + (void*)m68k_op_move_16_ai_pcdi , + (void*)m68k_op_move_16_ai_pcix , + (void*)m68k_op_move_16_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_aw , + (void*)m68k_op_move_16_pi_al , + (void*)m68k_op_move_16_pi_pcdi , + (void*)m68k_op_move_16_pi_pcix , + (void*)m68k_op_move_16_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_aw , + (void*)m68k_op_move_16_pd_al , + (void*)m68k_op_move_16_pd_pcdi , + (void*)m68k_op_move_16_pd_pcix , + (void*)m68k_op_move_16_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_aw , + (void*)m68k_op_move_16_di_al , + (void*)m68k_op_move_16_di_pcdi , + (void*)m68k_op_move_16_di_pcix , + (void*)m68k_op_move_16_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_aw , + (void*)m68k_op_move_16_ix_al , + (void*)m68k_op_move_16_ix_pcdi , + (void*)m68k_op_move_16_ix_pcix , + (void*)m68k_op_move_16_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_al_d , + (void*)m68k_op_move_16_al_d , + (void*)m68k_op_move_16_al_d , + (void*)m68k_op_move_16_al_d , + (void*)m68k_op_move_16_al_d , + (void*)m68k_op_move_16_al_d , + (void*)m68k_op_move_16_al_d , + (void*)m68k_op_move_16_al_d , + (void*)m68k_op_move_16_al_a , + (void*)m68k_op_move_16_al_a , + (void*)m68k_op_move_16_al_a , + (void*)m68k_op_move_16_al_a , + (void*)m68k_op_move_16_al_a , + (void*)m68k_op_move_16_al_a , + (void*)m68k_op_move_16_al_a , + (void*)m68k_op_move_16_al_a , + (void*)m68k_op_move_16_al_ai , + (void*)m68k_op_move_16_al_ai , + (void*)m68k_op_move_16_al_ai , + (void*)m68k_op_move_16_al_ai , + (void*)m68k_op_move_16_al_ai , + (void*)m68k_op_move_16_al_ai , + (void*)m68k_op_move_16_al_ai , + (void*)m68k_op_move_16_al_ai , + (void*)m68k_op_move_16_al_pi , + (void*)m68k_op_move_16_al_pi , + (void*)m68k_op_move_16_al_pi , + (void*)m68k_op_move_16_al_pi , + (void*)m68k_op_move_16_al_pi , + (void*)m68k_op_move_16_al_pi , + (void*)m68k_op_move_16_al_pi , + (void*)m68k_op_move_16_al_pi , + (void*)m68k_op_move_16_al_pd , + (void*)m68k_op_move_16_al_pd , + (void*)m68k_op_move_16_al_pd , + (void*)m68k_op_move_16_al_pd , + (void*)m68k_op_move_16_al_pd , + (void*)m68k_op_move_16_al_pd , + (void*)m68k_op_move_16_al_pd , + (void*)m68k_op_move_16_al_pd , + (void*)m68k_op_move_16_al_di , + (void*)m68k_op_move_16_al_di , + (void*)m68k_op_move_16_al_di , + (void*)m68k_op_move_16_al_di , + (void*)m68k_op_move_16_al_di , + (void*)m68k_op_move_16_al_di , + (void*)m68k_op_move_16_al_di , + (void*)m68k_op_move_16_al_di , + (void*)m68k_op_move_16_al_ix , + (void*)m68k_op_move_16_al_ix , + (void*)m68k_op_move_16_al_ix , + (void*)m68k_op_move_16_al_ix , + (void*)m68k_op_move_16_al_ix , + (void*)m68k_op_move_16_al_ix , + (void*)m68k_op_move_16_al_ix , + (void*)m68k_op_move_16_al_ix , + (void*)m68k_op_move_16_al_aw , + (void*)m68k_op_move_16_al_al , + (void*)m68k_op_move_16_al_pcdi , + (void*)m68k_op_move_16_al_pcix , + (void*)m68k_op_move_16_al_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_aw , + (void*)m68k_op_move_16_d_al , + (void*)m68k_op_move_16_d_pcdi , + (void*)m68k_op_move_16_d_pcix , + (void*)m68k_op_move_16_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_aw , + (void*)m68k_op_movea_16_al , + (void*)m68k_op_movea_16_pcdi , + (void*)m68k_op_movea_16_pcix , + (void*)m68k_op_movea_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_aw , + (void*)m68k_op_move_16_ai_al , + (void*)m68k_op_move_16_ai_pcdi , + (void*)m68k_op_move_16_ai_pcix , + (void*)m68k_op_move_16_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_aw , + (void*)m68k_op_move_16_pi_al , + (void*)m68k_op_move_16_pi_pcdi , + (void*)m68k_op_move_16_pi_pcix , + (void*)m68k_op_move_16_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_aw , + (void*)m68k_op_move_16_pd_al , + (void*)m68k_op_move_16_pd_pcdi , + (void*)m68k_op_move_16_pd_pcix , + (void*)m68k_op_move_16_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_aw , + (void*)m68k_op_move_16_di_al , + (void*)m68k_op_move_16_di_pcdi , + (void*)m68k_op_move_16_di_pcix , + (void*)m68k_op_move_16_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_aw , + (void*)m68k_op_move_16_ix_al , + (void*)m68k_op_move_16_ix_pcdi , + (void*)m68k_op_move_16_ix_pcix , + (void*)m68k_op_move_16_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_aw , + (void*)m68k_op_move_16_d_al , + (void*)m68k_op_move_16_d_pcdi , + (void*)m68k_op_move_16_d_pcix , + (void*)m68k_op_move_16_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_aw , + (void*)m68k_op_movea_16_al , + (void*)m68k_op_movea_16_pcdi , + (void*)m68k_op_movea_16_pcix , + (void*)m68k_op_movea_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_aw , + (void*)m68k_op_move_16_ai_al , + (void*)m68k_op_move_16_ai_pcdi , + (void*)m68k_op_move_16_ai_pcix , + (void*)m68k_op_move_16_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_aw , + (void*)m68k_op_move_16_pi_al , + (void*)m68k_op_move_16_pi_pcdi , + (void*)m68k_op_move_16_pi_pcix , + (void*)m68k_op_move_16_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_aw , + (void*)m68k_op_move_16_pd_al , + (void*)m68k_op_move_16_pd_pcdi , + (void*)m68k_op_move_16_pd_pcix , + (void*)m68k_op_move_16_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_aw , + (void*)m68k_op_move_16_di_al , + (void*)m68k_op_move_16_di_pcdi , + (void*)m68k_op_move_16_di_pcix , + (void*)m68k_op_move_16_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_aw , + (void*)m68k_op_move_16_ix_al , + (void*)m68k_op_move_16_ix_pcdi , + (void*)m68k_op_move_16_ix_pcix , + (void*)m68k_op_move_16_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_aw , + (void*)m68k_op_move_16_d_al , + (void*)m68k_op_move_16_d_pcdi , + (void*)m68k_op_move_16_d_pcix , + (void*)m68k_op_move_16_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_aw , + (void*)m68k_op_movea_16_al , + (void*)m68k_op_movea_16_pcdi , + (void*)m68k_op_movea_16_pcix , + (void*)m68k_op_movea_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_aw , + (void*)m68k_op_move_16_ai_al , + (void*)m68k_op_move_16_ai_pcdi , + (void*)m68k_op_move_16_ai_pcix , + (void*)m68k_op_move_16_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_aw , + (void*)m68k_op_move_16_pi_al , + (void*)m68k_op_move_16_pi_pcdi , + (void*)m68k_op_move_16_pi_pcix , + (void*)m68k_op_move_16_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_aw , + (void*)m68k_op_move_16_pd_al , + (void*)m68k_op_move_16_pd_pcdi , + (void*)m68k_op_move_16_pd_pcix , + (void*)m68k_op_move_16_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_aw , + (void*)m68k_op_move_16_di_al , + (void*)m68k_op_move_16_di_pcdi , + (void*)m68k_op_move_16_di_pcix , + (void*)m68k_op_move_16_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_aw , + (void*)m68k_op_move_16_ix_al , + (void*)m68k_op_move_16_ix_pcdi , + (void*)m68k_op_move_16_ix_pcix , + (void*)m68k_op_move_16_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_aw , + (void*)m68k_op_move_16_d_al , + (void*)m68k_op_move_16_d_pcdi , + (void*)m68k_op_move_16_d_pcix , + (void*)m68k_op_move_16_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_aw , + (void*)m68k_op_movea_16_al , + (void*)m68k_op_movea_16_pcdi , + (void*)m68k_op_movea_16_pcix , + (void*)m68k_op_movea_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_aw , + (void*)m68k_op_move_16_ai_al , + (void*)m68k_op_move_16_ai_pcdi , + (void*)m68k_op_move_16_ai_pcix , + (void*)m68k_op_move_16_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_aw , + (void*)m68k_op_move_16_pi_al , + (void*)m68k_op_move_16_pi_pcdi , + (void*)m68k_op_move_16_pi_pcix , + (void*)m68k_op_move_16_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_aw , + (void*)m68k_op_move_16_pd_al , + (void*)m68k_op_move_16_pd_pcdi , + (void*)m68k_op_move_16_pd_pcix , + (void*)m68k_op_move_16_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_aw , + (void*)m68k_op_move_16_di_al , + (void*)m68k_op_move_16_di_pcdi , + (void*)m68k_op_move_16_di_pcix , + (void*)m68k_op_move_16_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_aw , + (void*)m68k_op_move_16_ix_al , + (void*)m68k_op_move_16_ix_pcdi , + (void*)m68k_op_move_16_ix_pcix , + (void*)m68k_op_move_16_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_aw , + (void*)m68k_op_move_16_d_al , + (void*)m68k_op_move_16_d_pcdi , + (void*)m68k_op_move_16_d_pcix , + (void*)m68k_op_move_16_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_aw , + (void*)m68k_op_movea_16_al , + (void*)m68k_op_movea_16_pcdi , + (void*)m68k_op_movea_16_pcix , + (void*)m68k_op_movea_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_aw , + (void*)m68k_op_move_16_ai_al , + (void*)m68k_op_move_16_ai_pcdi , + (void*)m68k_op_move_16_ai_pcix , + (void*)m68k_op_move_16_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_aw , + (void*)m68k_op_move_16_pi_al , + (void*)m68k_op_move_16_pi_pcdi , + (void*)m68k_op_move_16_pi_pcix , + (void*)m68k_op_move_16_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_aw , + (void*)m68k_op_move_16_pd_al , + (void*)m68k_op_move_16_pd_pcdi , + (void*)m68k_op_move_16_pd_pcix , + (void*)m68k_op_move_16_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_aw , + (void*)m68k_op_move_16_di_al , + (void*)m68k_op_move_16_di_pcdi , + (void*)m68k_op_move_16_di_pcix , + (void*)m68k_op_move_16_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_aw , + (void*)m68k_op_move_16_ix_al , + (void*)m68k_op_move_16_ix_pcdi , + (void*)m68k_op_move_16_ix_pcix , + (void*)m68k_op_move_16_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_d , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_a , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_ai , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pi , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_pd , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_di , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_ix , + (void*)m68k_op_move_16_d_aw , + (void*)m68k_op_move_16_d_al , + (void*)m68k_op_move_16_d_pcdi , + (void*)m68k_op_move_16_d_pcix , + (void*)m68k_op_move_16_d_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_d , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_a , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_ai , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pi , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_pd , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_di , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_ix , + (void*)m68k_op_movea_16_aw , + (void*)m68k_op_movea_16_al , + (void*)m68k_op_movea_16_pcdi , + (void*)m68k_op_movea_16_pcix , + (void*)m68k_op_movea_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_d , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_a , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_ai , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pi , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_pd , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_di , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_ix , + (void*)m68k_op_move_16_ai_aw , + (void*)m68k_op_move_16_ai_al , + (void*)m68k_op_move_16_ai_pcdi , + (void*)m68k_op_move_16_ai_pcix , + (void*)m68k_op_move_16_ai_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_d , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_a , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_ai , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pi , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_pd , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_di , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_ix , + (void*)m68k_op_move_16_pi_aw , + (void*)m68k_op_move_16_pi_al , + (void*)m68k_op_move_16_pi_pcdi , + (void*)m68k_op_move_16_pi_pcix , + (void*)m68k_op_move_16_pi_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_d , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_a , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_ai , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pi , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_pd , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_di , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_ix , + (void*)m68k_op_move_16_pd_aw , + (void*)m68k_op_move_16_pd_al , + (void*)m68k_op_move_16_pd_pcdi , + (void*)m68k_op_move_16_pd_pcix , + (void*)m68k_op_move_16_pd_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_d , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_a , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_ai , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pi , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_pd , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_di , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_ix , + (void*)m68k_op_move_16_di_aw , + (void*)m68k_op_move_16_di_al , + (void*)m68k_op_move_16_di_pcdi , + (void*)m68k_op_move_16_di_pcix , + (void*)m68k_op_move_16_di_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_d , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_a , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_ai , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pi , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_pd , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_di , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_ix , + (void*)m68k_op_move_16_ix_aw , + (void*)m68k_op_move_16_ix_al , + (void*)m68k_op_move_16_ix_pcdi , + (void*)m68k_op_move_16_ix_pcix , + (void*)m68k_op_move_16_ix_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_negx_8_d , + (void*)m68k_op_negx_8_d , + (void*)m68k_op_negx_8_d , + (void*)m68k_op_negx_8_d , + (void*)m68k_op_negx_8_d , + (void*)m68k_op_negx_8_d , + (void*)m68k_op_negx_8_d , + (void*)m68k_op_negx_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_negx_8_ai , + (void*)m68k_op_negx_8_ai , + (void*)m68k_op_negx_8_ai , + (void*)m68k_op_negx_8_ai , + (void*)m68k_op_negx_8_ai , + (void*)m68k_op_negx_8_ai , + (void*)m68k_op_negx_8_ai , + (void*)m68k_op_negx_8_ai , + (void*)m68k_op_negx_8_pi , + (void*)m68k_op_negx_8_pi , + (void*)m68k_op_negx_8_pi , + (void*)m68k_op_negx_8_pi , + (void*)m68k_op_negx_8_pi , + (void*)m68k_op_negx_8_pi , + (void*)m68k_op_negx_8_pi , + (void*)m68k_op_negx_8_pi7 , + (void*)m68k_op_negx_8_pd , + (void*)m68k_op_negx_8_pd , + (void*)m68k_op_negx_8_pd , + (void*)m68k_op_negx_8_pd , + (void*)m68k_op_negx_8_pd , + (void*)m68k_op_negx_8_pd , + (void*)m68k_op_negx_8_pd , + (void*)m68k_op_negx_8_pd7 , + (void*)m68k_op_negx_8_di , + (void*)m68k_op_negx_8_di , + (void*)m68k_op_negx_8_di , + (void*)m68k_op_negx_8_di , + (void*)m68k_op_negx_8_di , + (void*)m68k_op_negx_8_di , + (void*)m68k_op_negx_8_di , + (void*)m68k_op_negx_8_di , + (void*)m68k_op_negx_8_ix , + (void*)m68k_op_negx_8_ix , + (void*)m68k_op_negx_8_ix , + (void*)m68k_op_negx_8_ix , + (void*)m68k_op_negx_8_ix , + (void*)m68k_op_negx_8_ix , + (void*)m68k_op_negx_8_ix , + (void*)m68k_op_negx_8_ix , + (void*)m68k_op_negx_8_aw , + (void*)m68k_op_negx_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_negx_16_d , + (void*)m68k_op_negx_16_d , + (void*)m68k_op_negx_16_d , + (void*)m68k_op_negx_16_d , + (void*)m68k_op_negx_16_d , + (void*)m68k_op_negx_16_d , + (void*)m68k_op_negx_16_d , + (void*)m68k_op_negx_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_negx_16_ai , + (void*)m68k_op_negx_16_ai , + (void*)m68k_op_negx_16_ai , + (void*)m68k_op_negx_16_ai , + (void*)m68k_op_negx_16_ai , + (void*)m68k_op_negx_16_ai , + (void*)m68k_op_negx_16_ai , + (void*)m68k_op_negx_16_ai , + (void*)m68k_op_negx_16_pi , + (void*)m68k_op_negx_16_pi , + (void*)m68k_op_negx_16_pi , + (void*)m68k_op_negx_16_pi , + (void*)m68k_op_negx_16_pi , + (void*)m68k_op_negx_16_pi , + (void*)m68k_op_negx_16_pi , + (void*)m68k_op_negx_16_pi , + (void*)m68k_op_negx_16_pd , + (void*)m68k_op_negx_16_pd , + (void*)m68k_op_negx_16_pd , + (void*)m68k_op_negx_16_pd , + (void*)m68k_op_negx_16_pd , + (void*)m68k_op_negx_16_pd , + (void*)m68k_op_negx_16_pd , + (void*)m68k_op_negx_16_pd , + (void*)m68k_op_negx_16_di , + (void*)m68k_op_negx_16_di , + (void*)m68k_op_negx_16_di , + (void*)m68k_op_negx_16_di , + (void*)m68k_op_negx_16_di , + (void*)m68k_op_negx_16_di , + (void*)m68k_op_negx_16_di , + (void*)m68k_op_negx_16_di , + (void*)m68k_op_negx_16_ix , + (void*)m68k_op_negx_16_ix , + (void*)m68k_op_negx_16_ix , + (void*)m68k_op_negx_16_ix , + (void*)m68k_op_negx_16_ix , + (void*)m68k_op_negx_16_ix , + (void*)m68k_op_negx_16_ix , + (void*)m68k_op_negx_16_ix , + (void*)m68k_op_negx_16_aw , + (void*)m68k_op_negx_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_negx_32_d , + (void*)m68k_op_negx_32_d , + (void*)m68k_op_negx_32_d , + (void*)m68k_op_negx_32_d , + (void*)m68k_op_negx_32_d , + (void*)m68k_op_negx_32_d , + (void*)m68k_op_negx_32_d , + (void*)m68k_op_negx_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_negx_32_ai , + (void*)m68k_op_negx_32_ai , + (void*)m68k_op_negx_32_ai , + (void*)m68k_op_negx_32_ai , + (void*)m68k_op_negx_32_ai , + (void*)m68k_op_negx_32_ai , + (void*)m68k_op_negx_32_ai , + (void*)m68k_op_negx_32_ai , + (void*)m68k_op_negx_32_pi , + (void*)m68k_op_negx_32_pi , + (void*)m68k_op_negx_32_pi , + (void*)m68k_op_negx_32_pi , + (void*)m68k_op_negx_32_pi , + (void*)m68k_op_negx_32_pi , + (void*)m68k_op_negx_32_pi , + (void*)m68k_op_negx_32_pi , + (void*)m68k_op_negx_32_pd , + (void*)m68k_op_negx_32_pd , + (void*)m68k_op_negx_32_pd , + (void*)m68k_op_negx_32_pd , + (void*)m68k_op_negx_32_pd , + (void*)m68k_op_negx_32_pd , + (void*)m68k_op_negx_32_pd , + (void*)m68k_op_negx_32_pd , + (void*)m68k_op_negx_32_di , + (void*)m68k_op_negx_32_di , + (void*)m68k_op_negx_32_di , + (void*)m68k_op_negx_32_di , + (void*)m68k_op_negx_32_di , + (void*)m68k_op_negx_32_di , + (void*)m68k_op_negx_32_di , + (void*)m68k_op_negx_32_di , + (void*)m68k_op_negx_32_ix , + (void*)m68k_op_negx_32_ix , + (void*)m68k_op_negx_32_ix , + (void*)m68k_op_negx_32_ix , + (void*)m68k_op_negx_32_ix , + (void*)m68k_op_negx_32_ix , + (void*)m68k_op_negx_32_ix , + (void*)m68k_op_negx_32_ix , + (void*)m68k_op_negx_32_aw , + (void*)m68k_op_negx_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_frs_d , + (void*)m68k_op_move_16_frs_d , + (void*)m68k_op_move_16_frs_d , + (void*)m68k_op_move_16_frs_d , + (void*)m68k_op_move_16_frs_d , + (void*)m68k_op_move_16_frs_d , + (void*)m68k_op_move_16_frs_d , + (void*)m68k_op_move_16_frs_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_frs_ai , + (void*)m68k_op_move_16_frs_ai , + (void*)m68k_op_move_16_frs_ai , + (void*)m68k_op_move_16_frs_ai , + (void*)m68k_op_move_16_frs_ai , + (void*)m68k_op_move_16_frs_ai , + (void*)m68k_op_move_16_frs_ai , + (void*)m68k_op_move_16_frs_ai , + (void*)m68k_op_move_16_frs_pi , + (void*)m68k_op_move_16_frs_pi , + (void*)m68k_op_move_16_frs_pi , + (void*)m68k_op_move_16_frs_pi , + (void*)m68k_op_move_16_frs_pi , + (void*)m68k_op_move_16_frs_pi , + (void*)m68k_op_move_16_frs_pi , + (void*)m68k_op_move_16_frs_pi , + (void*)m68k_op_move_16_frs_pd , + (void*)m68k_op_move_16_frs_pd , + (void*)m68k_op_move_16_frs_pd , + (void*)m68k_op_move_16_frs_pd , + (void*)m68k_op_move_16_frs_pd , + (void*)m68k_op_move_16_frs_pd , + (void*)m68k_op_move_16_frs_pd , + (void*)m68k_op_move_16_frs_pd , + (void*)m68k_op_move_16_frs_di , + (void*)m68k_op_move_16_frs_di , + (void*)m68k_op_move_16_frs_di , + (void*)m68k_op_move_16_frs_di , + (void*)m68k_op_move_16_frs_di , + (void*)m68k_op_move_16_frs_di , + (void*)m68k_op_move_16_frs_di , + (void*)m68k_op_move_16_frs_di , + (void*)m68k_op_move_16_frs_ix , + (void*)m68k_op_move_16_frs_ix , + (void*)m68k_op_move_16_frs_ix , + (void*)m68k_op_move_16_frs_ix , + (void*)m68k_op_move_16_frs_ix , + (void*)m68k_op_move_16_frs_ix , + (void*)m68k_op_move_16_frs_ix , + (void*)m68k_op_move_16_frs_ix , + (void*)m68k_op_move_16_frs_aw , + (void*)m68k_op_move_16_frs_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_aw , + (void*)m68k_op_chk_32_al , + (void*)m68k_op_chk_32_pcdi , + (void*)m68k_op_chk_32_pcix , + (void*)m68k_op_chk_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_aw , + (void*)m68k_op_chk_16_al , + (void*)m68k_op_chk_16_pcdi , + (void*)m68k_op_chk_16_pcix , + (void*)m68k_op_chk_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_aw , + (void*)m68k_op_lea_32_al , + (void*)m68k_op_lea_32_pcdi , + (void*)m68k_op_lea_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_clr_8_d , + (void*)m68k_op_clr_8_d , + (void*)m68k_op_clr_8_d , + (void*)m68k_op_clr_8_d , + (void*)m68k_op_clr_8_d , + (void*)m68k_op_clr_8_d , + (void*)m68k_op_clr_8_d , + (void*)m68k_op_clr_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_clr_8_ai , + (void*)m68k_op_clr_8_ai , + (void*)m68k_op_clr_8_ai , + (void*)m68k_op_clr_8_ai , + (void*)m68k_op_clr_8_ai , + (void*)m68k_op_clr_8_ai , + (void*)m68k_op_clr_8_ai , + (void*)m68k_op_clr_8_ai , + (void*)m68k_op_clr_8_pi , + (void*)m68k_op_clr_8_pi , + (void*)m68k_op_clr_8_pi , + (void*)m68k_op_clr_8_pi , + (void*)m68k_op_clr_8_pi , + (void*)m68k_op_clr_8_pi , + (void*)m68k_op_clr_8_pi , + (void*)m68k_op_clr_8_pi7 , + (void*)m68k_op_clr_8_pd , + (void*)m68k_op_clr_8_pd , + (void*)m68k_op_clr_8_pd , + (void*)m68k_op_clr_8_pd , + (void*)m68k_op_clr_8_pd , + (void*)m68k_op_clr_8_pd , + (void*)m68k_op_clr_8_pd , + (void*)m68k_op_clr_8_pd7 , + (void*)m68k_op_clr_8_di , + (void*)m68k_op_clr_8_di , + (void*)m68k_op_clr_8_di , + (void*)m68k_op_clr_8_di , + (void*)m68k_op_clr_8_di , + (void*)m68k_op_clr_8_di , + (void*)m68k_op_clr_8_di , + (void*)m68k_op_clr_8_di , + (void*)m68k_op_clr_8_ix , + (void*)m68k_op_clr_8_ix , + (void*)m68k_op_clr_8_ix , + (void*)m68k_op_clr_8_ix , + (void*)m68k_op_clr_8_ix , + (void*)m68k_op_clr_8_ix , + (void*)m68k_op_clr_8_ix , + (void*)m68k_op_clr_8_ix , + (void*)m68k_op_clr_8_aw , + (void*)m68k_op_clr_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_clr_16_d , + (void*)m68k_op_clr_16_d , + (void*)m68k_op_clr_16_d , + (void*)m68k_op_clr_16_d , + (void*)m68k_op_clr_16_d , + (void*)m68k_op_clr_16_d , + (void*)m68k_op_clr_16_d , + (void*)m68k_op_clr_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_clr_16_ai , + (void*)m68k_op_clr_16_ai , + (void*)m68k_op_clr_16_ai , + (void*)m68k_op_clr_16_ai , + (void*)m68k_op_clr_16_ai , + (void*)m68k_op_clr_16_ai , + (void*)m68k_op_clr_16_ai , + (void*)m68k_op_clr_16_ai , + (void*)m68k_op_clr_16_pi , + (void*)m68k_op_clr_16_pi , + (void*)m68k_op_clr_16_pi , + (void*)m68k_op_clr_16_pi , + (void*)m68k_op_clr_16_pi , + (void*)m68k_op_clr_16_pi , + (void*)m68k_op_clr_16_pi , + (void*)m68k_op_clr_16_pi , + (void*)m68k_op_clr_16_pd , + (void*)m68k_op_clr_16_pd , + (void*)m68k_op_clr_16_pd , + (void*)m68k_op_clr_16_pd , + (void*)m68k_op_clr_16_pd , + (void*)m68k_op_clr_16_pd , + (void*)m68k_op_clr_16_pd , + (void*)m68k_op_clr_16_pd , + (void*)m68k_op_clr_16_di , + (void*)m68k_op_clr_16_di , + (void*)m68k_op_clr_16_di , + (void*)m68k_op_clr_16_di , + (void*)m68k_op_clr_16_di , + (void*)m68k_op_clr_16_di , + (void*)m68k_op_clr_16_di , + (void*)m68k_op_clr_16_di , + (void*)m68k_op_clr_16_ix , + (void*)m68k_op_clr_16_ix , + (void*)m68k_op_clr_16_ix , + (void*)m68k_op_clr_16_ix , + (void*)m68k_op_clr_16_ix , + (void*)m68k_op_clr_16_ix , + (void*)m68k_op_clr_16_ix , + (void*)m68k_op_clr_16_ix , + (void*)m68k_op_clr_16_aw , + (void*)m68k_op_clr_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_clr_32_d , + (void*)m68k_op_clr_32_d , + (void*)m68k_op_clr_32_d , + (void*)m68k_op_clr_32_d , + (void*)m68k_op_clr_32_d , + (void*)m68k_op_clr_32_d , + (void*)m68k_op_clr_32_d , + (void*)m68k_op_clr_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_clr_32_ai , + (void*)m68k_op_clr_32_ai , + (void*)m68k_op_clr_32_ai , + (void*)m68k_op_clr_32_ai , + (void*)m68k_op_clr_32_ai , + (void*)m68k_op_clr_32_ai , + (void*)m68k_op_clr_32_ai , + (void*)m68k_op_clr_32_ai , + (void*)m68k_op_clr_32_pi , + (void*)m68k_op_clr_32_pi , + (void*)m68k_op_clr_32_pi , + (void*)m68k_op_clr_32_pi , + (void*)m68k_op_clr_32_pi , + (void*)m68k_op_clr_32_pi , + (void*)m68k_op_clr_32_pi , + (void*)m68k_op_clr_32_pi , + (void*)m68k_op_clr_32_pd , + (void*)m68k_op_clr_32_pd , + (void*)m68k_op_clr_32_pd , + (void*)m68k_op_clr_32_pd , + (void*)m68k_op_clr_32_pd , + (void*)m68k_op_clr_32_pd , + (void*)m68k_op_clr_32_pd , + (void*)m68k_op_clr_32_pd , + (void*)m68k_op_clr_32_di , + (void*)m68k_op_clr_32_di , + (void*)m68k_op_clr_32_di , + (void*)m68k_op_clr_32_di , + (void*)m68k_op_clr_32_di , + (void*)m68k_op_clr_32_di , + (void*)m68k_op_clr_32_di , + (void*)m68k_op_clr_32_di , + (void*)m68k_op_clr_32_ix , + (void*)m68k_op_clr_32_ix , + (void*)m68k_op_clr_32_ix , + (void*)m68k_op_clr_32_ix , + (void*)m68k_op_clr_32_ix , + (void*)m68k_op_clr_32_ix , + (void*)m68k_op_clr_32_ix , + (void*)m68k_op_clr_32_ix , + (void*)m68k_op_clr_32_aw , + (void*)m68k_op_clr_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_frc_d , + (void*)m68k_op_move_16_frc_d , + (void*)m68k_op_move_16_frc_d , + (void*)m68k_op_move_16_frc_d , + (void*)m68k_op_move_16_frc_d , + (void*)m68k_op_move_16_frc_d , + (void*)m68k_op_move_16_frc_d , + (void*)m68k_op_move_16_frc_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_frc_ai , + (void*)m68k_op_move_16_frc_ai , + (void*)m68k_op_move_16_frc_ai , + (void*)m68k_op_move_16_frc_ai , + (void*)m68k_op_move_16_frc_ai , + (void*)m68k_op_move_16_frc_ai , + (void*)m68k_op_move_16_frc_ai , + (void*)m68k_op_move_16_frc_ai , + (void*)m68k_op_move_16_frc_pi , + (void*)m68k_op_move_16_frc_pi , + (void*)m68k_op_move_16_frc_pi , + (void*)m68k_op_move_16_frc_pi , + (void*)m68k_op_move_16_frc_pi , + (void*)m68k_op_move_16_frc_pi , + (void*)m68k_op_move_16_frc_pi , + (void*)m68k_op_move_16_frc_pi , + (void*)m68k_op_move_16_frc_pd , + (void*)m68k_op_move_16_frc_pd , + (void*)m68k_op_move_16_frc_pd , + (void*)m68k_op_move_16_frc_pd , + (void*)m68k_op_move_16_frc_pd , + (void*)m68k_op_move_16_frc_pd , + (void*)m68k_op_move_16_frc_pd , + (void*)m68k_op_move_16_frc_pd , + (void*)m68k_op_move_16_frc_di , + (void*)m68k_op_move_16_frc_di , + (void*)m68k_op_move_16_frc_di , + (void*)m68k_op_move_16_frc_di , + (void*)m68k_op_move_16_frc_di , + (void*)m68k_op_move_16_frc_di , + (void*)m68k_op_move_16_frc_di , + (void*)m68k_op_move_16_frc_di , + (void*)m68k_op_move_16_frc_ix , + (void*)m68k_op_move_16_frc_ix , + (void*)m68k_op_move_16_frc_ix , + (void*)m68k_op_move_16_frc_ix , + (void*)m68k_op_move_16_frc_ix , + (void*)m68k_op_move_16_frc_ix , + (void*)m68k_op_move_16_frc_ix , + (void*)m68k_op_move_16_frc_ix , + (void*)m68k_op_move_16_frc_aw , + (void*)m68k_op_move_16_frc_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_aw , + (void*)m68k_op_chk_32_al , + (void*)m68k_op_chk_32_pcdi , + (void*)m68k_op_chk_32_pcix , + (void*)m68k_op_chk_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_aw , + (void*)m68k_op_chk_16_al , + (void*)m68k_op_chk_16_pcdi , + (void*)m68k_op_chk_16_pcix , + (void*)m68k_op_chk_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_aw , + (void*)m68k_op_lea_32_al , + (void*)m68k_op_lea_32_pcdi , + (void*)m68k_op_lea_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_neg_8_d , + (void*)m68k_op_neg_8_d , + (void*)m68k_op_neg_8_d , + (void*)m68k_op_neg_8_d , + (void*)m68k_op_neg_8_d , + (void*)m68k_op_neg_8_d , + (void*)m68k_op_neg_8_d , + (void*)m68k_op_neg_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_neg_8_ai , + (void*)m68k_op_neg_8_ai , + (void*)m68k_op_neg_8_ai , + (void*)m68k_op_neg_8_ai , + (void*)m68k_op_neg_8_ai , + (void*)m68k_op_neg_8_ai , + (void*)m68k_op_neg_8_ai , + (void*)m68k_op_neg_8_ai , + (void*)m68k_op_neg_8_pi , + (void*)m68k_op_neg_8_pi , + (void*)m68k_op_neg_8_pi , + (void*)m68k_op_neg_8_pi , + (void*)m68k_op_neg_8_pi , + (void*)m68k_op_neg_8_pi , + (void*)m68k_op_neg_8_pi , + (void*)m68k_op_neg_8_pi7 , + (void*)m68k_op_neg_8_pd , + (void*)m68k_op_neg_8_pd , + (void*)m68k_op_neg_8_pd , + (void*)m68k_op_neg_8_pd , + (void*)m68k_op_neg_8_pd , + (void*)m68k_op_neg_8_pd , + (void*)m68k_op_neg_8_pd , + (void*)m68k_op_neg_8_pd7 , + (void*)m68k_op_neg_8_di , + (void*)m68k_op_neg_8_di , + (void*)m68k_op_neg_8_di , + (void*)m68k_op_neg_8_di , + (void*)m68k_op_neg_8_di , + (void*)m68k_op_neg_8_di , + (void*)m68k_op_neg_8_di , + (void*)m68k_op_neg_8_di , + (void*)m68k_op_neg_8_ix , + (void*)m68k_op_neg_8_ix , + (void*)m68k_op_neg_8_ix , + (void*)m68k_op_neg_8_ix , + (void*)m68k_op_neg_8_ix , + (void*)m68k_op_neg_8_ix , + (void*)m68k_op_neg_8_ix , + (void*)m68k_op_neg_8_ix , + (void*)m68k_op_neg_8_aw , + (void*)m68k_op_neg_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_neg_16_d , + (void*)m68k_op_neg_16_d , + (void*)m68k_op_neg_16_d , + (void*)m68k_op_neg_16_d , + (void*)m68k_op_neg_16_d , + (void*)m68k_op_neg_16_d , + (void*)m68k_op_neg_16_d , + (void*)m68k_op_neg_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_neg_16_ai , + (void*)m68k_op_neg_16_ai , + (void*)m68k_op_neg_16_ai , + (void*)m68k_op_neg_16_ai , + (void*)m68k_op_neg_16_ai , + (void*)m68k_op_neg_16_ai , + (void*)m68k_op_neg_16_ai , + (void*)m68k_op_neg_16_ai , + (void*)m68k_op_neg_16_pi , + (void*)m68k_op_neg_16_pi , + (void*)m68k_op_neg_16_pi , + (void*)m68k_op_neg_16_pi , + (void*)m68k_op_neg_16_pi , + (void*)m68k_op_neg_16_pi , + (void*)m68k_op_neg_16_pi , + (void*)m68k_op_neg_16_pi , + (void*)m68k_op_neg_16_pd , + (void*)m68k_op_neg_16_pd , + (void*)m68k_op_neg_16_pd , + (void*)m68k_op_neg_16_pd , + (void*)m68k_op_neg_16_pd , + (void*)m68k_op_neg_16_pd , + (void*)m68k_op_neg_16_pd , + (void*)m68k_op_neg_16_pd , + (void*)m68k_op_neg_16_di , + (void*)m68k_op_neg_16_di , + (void*)m68k_op_neg_16_di , + (void*)m68k_op_neg_16_di , + (void*)m68k_op_neg_16_di , + (void*)m68k_op_neg_16_di , + (void*)m68k_op_neg_16_di , + (void*)m68k_op_neg_16_di , + (void*)m68k_op_neg_16_ix , + (void*)m68k_op_neg_16_ix , + (void*)m68k_op_neg_16_ix , + (void*)m68k_op_neg_16_ix , + (void*)m68k_op_neg_16_ix , + (void*)m68k_op_neg_16_ix , + (void*)m68k_op_neg_16_ix , + (void*)m68k_op_neg_16_ix , + (void*)m68k_op_neg_16_aw , + (void*)m68k_op_neg_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_neg_32_d , + (void*)m68k_op_neg_32_d , + (void*)m68k_op_neg_32_d , + (void*)m68k_op_neg_32_d , + (void*)m68k_op_neg_32_d , + (void*)m68k_op_neg_32_d , + (void*)m68k_op_neg_32_d , + (void*)m68k_op_neg_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_neg_32_ai , + (void*)m68k_op_neg_32_ai , + (void*)m68k_op_neg_32_ai , + (void*)m68k_op_neg_32_ai , + (void*)m68k_op_neg_32_ai , + (void*)m68k_op_neg_32_ai , + (void*)m68k_op_neg_32_ai , + (void*)m68k_op_neg_32_ai , + (void*)m68k_op_neg_32_pi , + (void*)m68k_op_neg_32_pi , + (void*)m68k_op_neg_32_pi , + (void*)m68k_op_neg_32_pi , + (void*)m68k_op_neg_32_pi , + (void*)m68k_op_neg_32_pi , + (void*)m68k_op_neg_32_pi , + (void*)m68k_op_neg_32_pi , + (void*)m68k_op_neg_32_pd , + (void*)m68k_op_neg_32_pd , + (void*)m68k_op_neg_32_pd , + (void*)m68k_op_neg_32_pd , + (void*)m68k_op_neg_32_pd , + (void*)m68k_op_neg_32_pd , + (void*)m68k_op_neg_32_pd , + (void*)m68k_op_neg_32_pd , + (void*)m68k_op_neg_32_di , + (void*)m68k_op_neg_32_di , + (void*)m68k_op_neg_32_di , + (void*)m68k_op_neg_32_di , + (void*)m68k_op_neg_32_di , + (void*)m68k_op_neg_32_di , + (void*)m68k_op_neg_32_di , + (void*)m68k_op_neg_32_di , + (void*)m68k_op_neg_32_ix , + (void*)m68k_op_neg_32_ix , + (void*)m68k_op_neg_32_ix , + (void*)m68k_op_neg_32_ix , + (void*)m68k_op_neg_32_ix , + (void*)m68k_op_neg_32_ix , + (void*)m68k_op_neg_32_ix , + (void*)m68k_op_neg_32_ix , + (void*)m68k_op_neg_32_aw , + (void*)m68k_op_neg_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_toc_d , + (void*)m68k_op_move_16_toc_d , + (void*)m68k_op_move_16_toc_d , + (void*)m68k_op_move_16_toc_d , + (void*)m68k_op_move_16_toc_d , + (void*)m68k_op_move_16_toc_d , + (void*)m68k_op_move_16_toc_d , + (void*)m68k_op_move_16_toc_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_toc_ai , + (void*)m68k_op_move_16_toc_ai , + (void*)m68k_op_move_16_toc_ai , + (void*)m68k_op_move_16_toc_ai , + (void*)m68k_op_move_16_toc_ai , + (void*)m68k_op_move_16_toc_ai , + (void*)m68k_op_move_16_toc_ai , + (void*)m68k_op_move_16_toc_ai , + (void*)m68k_op_move_16_toc_pi , + (void*)m68k_op_move_16_toc_pi , + (void*)m68k_op_move_16_toc_pi , + (void*)m68k_op_move_16_toc_pi , + (void*)m68k_op_move_16_toc_pi , + (void*)m68k_op_move_16_toc_pi , + (void*)m68k_op_move_16_toc_pi , + (void*)m68k_op_move_16_toc_pi , + (void*)m68k_op_move_16_toc_pd , + (void*)m68k_op_move_16_toc_pd , + (void*)m68k_op_move_16_toc_pd , + (void*)m68k_op_move_16_toc_pd , + (void*)m68k_op_move_16_toc_pd , + (void*)m68k_op_move_16_toc_pd , + (void*)m68k_op_move_16_toc_pd , + (void*)m68k_op_move_16_toc_pd , + (void*)m68k_op_move_16_toc_di , + (void*)m68k_op_move_16_toc_di , + (void*)m68k_op_move_16_toc_di , + (void*)m68k_op_move_16_toc_di , + (void*)m68k_op_move_16_toc_di , + (void*)m68k_op_move_16_toc_di , + (void*)m68k_op_move_16_toc_di , + (void*)m68k_op_move_16_toc_di , + (void*)m68k_op_move_16_toc_ix , + (void*)m68k_op_move_16_toc_ix , + (void*)m68k_op_move_16_toc_ix , + (void*)m68k_op_move_16_toc_ix , + (void*)m68k_op_move_16_toc_ix , + (void*)m68k_op_move_16_toc_ix , + (void*)m68k_op_move_16_toc_ix , + (void*)m68k_op_move_16_toc_ix , + (void*)m68k_op_move_16_toc_aw , + (void*)m68k_op_move_16_toc_al , + (void*)m68k_op_move_16_toc_pcdi , + (void*)m68k_op_move_16_toc_pcix , + (void*)m68k_op_move_16_toc_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_aw , + (void*)m68k_op_chk_32_al , + (void*)m68k_op_chk_32_pcdi , + (void*)m68k_op_chk_32_pcix , + (void*)m68k_op_chk_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_aw , + (void*)m68k_op_chk_16_al , + (void*)m68k_op_chk_16_pcdi , + (void*)m68k_op_chk_16_pcix , + (void*)m68k_op_chk_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_aw , + (void*)m68k_op_lea_32_al , + (void*)m68k_op_lea_32_pcdi , + (void*)m68k_op_lea_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_not_8_d , + (void*)m68k_op_not_8_d , + (void*)m68k_op_not_8_d , + (void*)m68k_op_not_8_d , + (void*)m68k_op_not_8_d , + (void*)m68k_op_not_8_d , + (void*)m68k_op_not_8_d , + (void*)m68k_op_not_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_not_8_ai , + (void*)m68k_op_not_8_ai , + (void*)m68k_op_not_8_ai , + (void*)m68k_op_not_8_ai , + (void*)m68k_op_not_8_ai , + (void*)m68k_op_not_8_ai , + (void*)m68k_op_not_8_ai , + (void*)m68k_op_not_8_ai , + (void*)m68k_op_not_8_pi , + (void*)m68k_op_not_8_pi , + (void*)m68k_op_not_8_pi , + (void*)m68k_op_not_8_pi , + (void*)m68k_op_not_8_pi , + (void*)m68k_op_not_8_pi , + (void*)m68k_op_not_8_pi , + (void*)m68k_op_not_8_pi7 , + (void*)m68k_op_not_8_pd , + (void*)m68k_op_not_8_pd , + (void*)m68k_op_not_8_pd , + (void*)m68k_op_not_8_pd , + (void*)m68k_op_not_8_pd , + (void*)m68k_op_not_8_pd , + (void*)m68k_op_not_8_pd , + (void*)m68k_op_not_8_pd7 , + (void*)m68k_op_not_8_di , + (void*)m68k_op_not_8_di , + (void*)m68k_op_not_8_di , + (void*)m68k_op_not_8_di , + (void*)m68k_op_not_8_di , + (void*)m68k_op_not_8_di , + (void*)m68k_op_not_8_di , + (void*)m68k_op_not_8_di , + (void*)m68k_op_not_8_ix , + (void*)m68k_op_not_8_ix , + (void*)m68k_op_not_8_ix , + (void*)m68k_op_not_8_ix , + (void*)m68k_op_not_8_ix , + (void*)m68k_op_not_8_ix , + (void*)m68k_op_not_8_ix , + (void*)m68k_op_not_8_ix , + (void*)m68k_op_not_8_aw , + (void*)m68k_op_not_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_not_16_d , + (void*)m68k_op_not_16_d , + (void*)m68k_op_not_16_d , + (void*)m68k_op_not_16_d , + (void*)m68k_op_not_16_d , + (void*)m68k_op_not_16_d , + (void*)m68k_op_not_16_d , + (void*)m68k_op_not_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_not_16_ai , + (void*)m68k_op_not_16_ai , + (void*)m68k_op_not_16_ai , + (void*)m68k_op_not_16_ai , + (void*)m68k_op_not_16_ai , + (void*)m68k_op_not_16_ai , + (void*)m68k_op_not_16_ai , + (void*)m68k_op_not_16_ai , + (void*)m68k_op_not_16_pi , + (void*)m68k_op_not_16_pi , + (void*)m68k_op_not_16_pi , + (void*)m68k_op_not_16_pi , + (void*)m68k_op_not_16_pi , + (void*)m68k_op_not_16_pi , + (void*)m68k_op_not_16_pi , + (void*)m68k_op_not_16_pi , + (void*)m68k_op_not_16_pd , + (void*)m68k_op_not_16_pd , + (void*)m68k_op_not_16_pd , + (void*)m68k_op_not_16_pd , + (void*)m68k_op_not_16_pd , + (void*)m68k_op_not_16_pd , + (void*)m68k_op_not_16_pd , + (void*)m68k_op_not_16_pd , + (void*)m68k_op_not_16_di , + (void*)m68k_op_not_16_di , + (void*)m68k_op_not_16_di , + (void*)m68k_op_not_16_di , + (void*)m68k_op_not_16_di , + (void*)m68k_op_not_16_di , + (void*)m68k_op_not_16_di , + (void*)m68k_op_not_16_di , + (void*)m68k_op_not_16_ix , + (void*)m68k_op_not_16_ix , + (void*)m68k_op_not_16_ix , + (void*)m68k_op_not_16_ix , + (void*)m68k_op_not_16_ix , + (void*)m68k_op_not_16_ix , + (void*)m68k_op_not_16_ix , + (void*)m68k_op_not_16_ix , + (void*)m68k_op_not_16_aw , + (void*)m68k_op_not_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_not_32_d , + (void*)m68k_op_not_32_d , + (void*)m68k_op_not_32_d , + (void*)m68k_op_not_32_d , + (void*)m68k_op_not_32_d , + (void*)m68k_op_not_32_d , + (void*)m68k_op_not_32_d , + (void*)m68k_op_not_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_not_32_ai , + (void*)m68k_op_not_32_ai , + (void*)m68k_op_not_32_ai , + (void*)m68k_op_not_32_ai , + (void*)m68k_op_not_32_ai , + (void*)m68k_op_not_32_ai , + (void*)m68k_op_not_32_ai , + (void*)m68k_op_not_32_ai , + (void*)m68k_op_not_32_pi , + (void*)m68k_op_not_32_pi , + (void*)m68k_op_not_32_pi , + (void*)m68k_op_not_32_pi , + (void*)m68k_op_not_32_pi , + (void*)m68k_op_not_32_pi , + (void*)m68k_op_not_32_pi , + (void*)m68k_op_not_32_pi , + (void*)m68k_op_not_32_pd , + (void*)m68k_op_not_32_pd , + (void*)m68k_op_not_32_pd , + (void*)m68k_op_not_32_pd , + (void*)m68k_op_not_32_pd , + (void*)m68k_op_not_32_pd , + (void*)m68k_op_not_32_pd , + (void*)m68k_op_not_32_pd , + (void*)m68k_op_not_32_di , + (void*)m68k_op_not_32_di , + (void*)m68k_op_not_32_di , + (void*)m68k_op_not_32_di , + (void*)m68k_op_not_32_di , + (void*)m68k_op_not_32_di , + (void*)m68k_op_not_32_di , + (void*)m68k_op_not_32_di , + (void*)m68k_op_not_32_ix , + (void*)m68k_op_not_32_ix , + (void*)m68k_op_not_32_ix , + (void*)m68k_op_not_32_ix , + (void*)m68k_op_not_32_ix , + (void*)m68k_op_not_32_ix , + (void*)m68k_op_not_32_ix , + (void*)m68k_op_not_32_ix , + (void*)m68k_op_not_32_aw , + (void*)m68k_op_not_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_tos_d , + (void*)m68k_op_move_16_tos_d , + (void*)m68k_op_move_16_tos_d , + (void*)m68k_op_move_16_tos_d , + (void*)m68k_op_move_16_tos_d , + (void*)m68k_op_move_16_tos_d , + (void*)m68k_op_move_16_tos_d , + (void*)m68k_op_move_16_tos_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_move_16_tos_ai , + (void*)m68k_op_move_16_tos_ai , + (void*)m68k_op_move_16_tos_ai , + (void*)m68k_op_move_16_tos_ai , + (void*)m68k_op_move_16_tos_ai , + (void*)m68k_op_move_16_tos_ai , + (void*)m68k_op_move_16_tos_ai , + (void*)m68k_op_move_16_tos_ai , + (void*)m68k_op_move_16_tos_pi , + (void*)m68k_op_move_16_tos_pi , + (void*)m68k_op_move_16_tos_pi , + (void*)m68k_op_move_16_tos_pi , + (void*)m68k_op_move_16_tos_pi , + (void*)m68k_op_move_16_tos_pi , + (void*)m68k_op_move_16_tos_pi , + (void*)m68k_op_move_16_tos_pi , + (void*)m68k_op_move_16_tos_pd , + (void*)m68k_op_move_16_tos_pd , + (void*)m68k_op_move_16_tos_pd , + (void*)m68k_op_move_16_tos_pd , + (void*)m68k_op_move_16_tos_pd , + (void*)m68k_op_move_16_tos_pd , + (void*)m68k_op_move_16_tos_pd , + (void*)m68k_op_move_16_tos_pd , + (void*)m68k_op_move_16_tos_di , + (void*)m68k_op_move_16_tos_di , + (void*)m68k_op_move_16_tos_di , + (void*)m68k_op_move_16_tos_di , + (void*)m68k_op_move_16_tos_di , + (void*)m68k_op_move_16_tos_di , + (void*)m68k_op_move_16_tos_di , + (void*)m68k_op_move_16_tos_di , + (void*)m68k_op_move_16_tos_ix , + (void*)m68k_op_move_16_tos_ix , + (void*)m68k_op_move_16_tos_ix , + (void*)m68k_op_move_16_tos_ix , + (void*)m68k_op_move_16_tos_ix , + (void*)m68k_op_move_16_tos_ix , + (void*)m68k_op_move_16_tos_ix , + (void*)m68k_op_move_16_tos_ix , + (void*)m68k_op_move_16_tos_aw , + (void*)m68k_op_move_16_tos_al , + (void*)m68k_op_move_16_tos_pcdi , + (void*)m68k_op_move_16_tos_pcix , + (void*)m68k_op_move_16_tos_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_aw , + (void*)m68k_op_chk_32_al , + (void*)m68k_op_chk_32_pcdi , + (void*)m68k_op_chk_32_pcix , + (void*)m68k_op_chk_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_aw , + (void*)m68k_op_chk_16_al , + (void*)m68k_op_chk_16_pcdi , + (void*)m68k_op_chk_16_pcix , + (void*)m68k_op_chk_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_aw , + (void*)m68k_op_lea_32_al , + (void*)m68k_op_lea_32_pcdi , + (void*)m68k_op_lea_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_nbcd_8_d , + (void*)m68k_op_nbcd_8_d , + (void*)m68k_op_nbcd_8_d , + (void*)m68k_op_nbcd_8_d , + (void*)m68k_op_nbcd_8_d , + (void*)m68k_op_nbcd_8_d , + (void*)m68k_op_nbcd_8_d , + (void*)m68k_op_nbcd_8_d , + (void*)m68k_op_link_32 , + (void*)m68k_op_link_32 , + (void*)m68k_op_link_32 , + (void*)m68k_op_link_32 , + (void*)m68k_op_link_32 , + (void*)m68k_op_link_32 , + (void*)m68k_op_link_32 , + (void*)m68k_op_link_32_a7 , + (void*)m68k_op_nbcd_8_ai , + (void*)m68k_op_nbcd_8_ai , + (void*)m68k_op_nbcd_8_ai , + (void*)m68k_op_nbcd_8_ai , + (void*)m68k_op_nbcd_8_ai , + (void*)m68k_op_nbcd_8_ai , + (void*)m68k_op_nbcd_8_ai , + (void*)m68k_op_nbcd_8_ai , + (void*)m68k_op_nbcd_8_pi , + (void*)m68k_op_nbcd_8_pi , + (void*)m68k_op_nbcd_8_pi , + (void*)m68k_op_nbcd_8_pi , + (void*)m68k_op_nbcd_8_pi , + (void*)m68k_op_nbcd_8_pi , + (void*)m68k_op_nbcd_8_pi , + (void*)m68k_op_nbcd_8_pi7 , + (void*)m68k_op_nbcd_8_pd , + (void*)m68k_op_nbcd_8_pd , + (void*)m68k_op_nbcd_8_pd , + (void*)m68k_op_nbcd_8_pd , + (void*)m68k_op_nbcd_8_pd , + (void*)m68k_op_nbcd_8_pd , + (void*)m68k_op_nbcd_8_pd , + (void*)m68k_op_nbcd_8_pd7 , + (void*)m68k_op_nbcd_8_di , + (void*)m68k_op_nbcd_8_di , + (void*)m68k_op_nbcd_8_di , + (void*)m68k_op_nbcd_8_di , + (void*)m68k_op_nbcd_8_di , + (void*)m68k_op_nbcd_8_di , + (void*)m68k_op_nbcd_8_di , + (void*)m68k_op_nbcd_8_di , + (void*)m68k_op_nbcd_8_ix , + (void*)m68k_op_nbcd_8_ix , + (void*)m68k_op_nbcd_8_ix , + (void*)m68k_op_nbcd_8_ix , + (void*)m68k_op_nbcd_8_ix , + (void*)m68k_op_nbcd_8_ix , + (void*)m68k_op_nbcd_8_ix , + (void*)m68k_op_nbcd_8_ix , + (void*)m68k_op_nbcd_8_aw , + (void*)m68k_op_nbcd_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_swap_32 , + (void*)m68k_op_swap_32 , + (void*)m68k_op_swap_32 , + (void*)m68k_op_swap_32 , + (void*)m68k_op_swap_32 , + (void*)m68k_op_swap_32 , + (void*)m68k_op_swap_32 , + (void*)m68k_op_swap_32 , + (void*)m68k_op_bkpt , + (void*)m68k_op_bkpt , + (void*)m68k_op_bkpt , + (void*)m68k_op_bkpt , + (void*)m68k_op_bkpt , + (void*)m68k_op_bkpt , + (void*)m68k_op_bkpt , + (void*)m68k_op_bkpt , + (void*)m68k_op_pea_32_ai , + (void*)m68k_op_pea_32_ai , + (void*)m68k_op_pea_32_ai , + (void*)m68k_op_pea_32_ai , + (void*)m68k_op_pea_32_ai , + (void*)m68k_op_pea_32_ai , + (void*)m68k_op_pea_32_ai , + (void*)m68k_op_pea_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_pea_32_di , + (void*)m68k_op_pea_32_di , + (void*)m68k_op_pea_32_di , + (void*)m68k_op_pea_32_di , + (void*)m68k_op_pea_32_di , + (void*)m68k_op_pea_32_di , + (void*)m68k_op_pea_32_di , + (void*)m68k_op_pea_32_di , + (void*)m68k_op_pea_32_ix , + (void*)m68k_op_pea_32_ix , + (void*)m68k_op_pea_32_ix , + (void*)m68k_op_pea_32_ix , + (void*)m68k_op_pea_32_ix , + (void*)m68k_op_pea_32_ix , + (void*)m68k_op_pea_32_ix , + (void*)m68k_op_pea_32_ix , + (void*)m68k_op_pea_32_aw , + (void*)m68k_op_pea_32_al , + (void*)m68k_op_pea_32_pcdi , + (void*)m68k_op_pea_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ext_16 , + (void*)m68k_op_ext_16 , + (void*)m68k_op_ext_16 , + (void*)m68k_op_ext_16 , + (void*)m68k_op_ext_16 , + (void*)m68k_op_ext_16 , + (void*)m68k_op_ext_16 , + (void*)m68k_op_ext_16 , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movem_16_re_ai , + (void*)m68k_op_movem_16_re_ai , + (void*)m68k_op_movem_16_re_ai , + (void*)m68k_op_movem_16_re_ai , + (void*)m68k_op_movem_16_re_ai , + (void*)m68k_op_movem_16_re_ai , + (void*)m68k_op_movem_16_re_ai , + (void*)m68k_op_movem_16_re_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movem_16_re_pd , + (void*)m68k_op_movem_16_re_pd , + (void*)m68k_op_movem_16_re_pd , + (void*)m68k_op_movem_16_re_pd , + (void*)m68k_op_movem_16_re_pd , + (void*)m68k_op_movem_16_re_pd , + (void*)m68k_op_movem_16_re_pd , + (void*)m68k_op_movem_16_re_pd , + (void*)m68k_op_movem_16_re_di , + (void*)m68k_op_movem_16_re_di , + (void*)m68k_op_movem_16_re_di , + (void*)m68k_op_movem_16_re_di , + (void*)m68k_op_movem_16_re_di , + (void*)m68k_op_movem_16_re_di , + (void*)m68k_op_movem_16_re_di , + (void*)m68k_op_movem_16_re_di , + (void*)m68k_op_movem_16_re_ix , + (void*)m68k_op_movem_16_re_ix , + (void*)m68k_op_movem_16_re_ix , + (void*)m68k_op_movem_16_re_ix , + (void*)m68k_op_movem_16_re_ix , + (void*)m68k_op_movem_16_re_ix , + (void*)m68k_op_movem_16_re_ix , + (void*)m68k_op_movem_16_re_ix , + (void*)m68k_op_movem_16_re_aw , + (void*)m68k_op_movem_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ext_32 , + (void*)m68k_op_ext_32 , + (void*)m68k_op_ext_32 , + (void*)m68k_op_ext_32 , + (void*)m68k_op_ext_32 , + (void*)m68k_op_ext_32 , + (void*)m68k_op_ext_32 , + (void*)m68k_op_ext_32 , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movem_32_re_ai , + (void*)m68k_op_movem_32_re_ai , + (void*)m68k_op_movem_32_re_ai , + (void*)m68k_op_movem_32_re_ai , + (void*)m68k_op_movem_32_re_ai , + (void*)m68k_op_movem_32_re_ai , + (void*)m68k_op_movem_32_re_ai , + (void*)m68k_op_movem_32_re_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movem_32_re_pd , + (void*)m68k_op_movem_32_re_pd , + (void*)m68k_op_movem_32_re_pd , + (void*)m68k_op_movem_32_re_pd , + (void*)m68k_op_movem_32_re_pd , + (void*)m68k_op_movem_32_re_pd , + (void*)m68k_op_movem_32_re_pd , + (void*)m68k_op_movem_32_re_pd , + (void*)m68k_op_movem_32_re_di , + (void*)m68k_op_movem_32_re_di , + (void*)m68k_op_movem_32_re_di , + (void*)m68k_op_movem_32_re_di , + (void*)m68k_op_movem_32_re_di , + (void*)m68k_op_movem_32_re_di , + (void*)m68k_op_movem_32_re_di , + (void*)m68k_op_movem_32_re_di , + (void*)m68k_op_movem_32_re_ix , + (void*)m68k_op_movem_32_re_ix , + (void*)m68k_op_movem_32_re_ix , + (void*)m68k_op_movem_32_re_ix , + (void*)m68k_op_movem_32_re_ix , + (void*)m68k_op_movem_32_re_ix , + (void*)m68k_op_movem_32_re_ix , + (void*)m68k_op_movem_32_re_ix , + (void*)m68k_op_movem_32_re_aw , + (void*)m68k_op_movem_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_aw , + (void*)m68k_op_chk_32_al , + (void*)m68k_op_chk_32_pcdi , + (void*)m68k_op_chk_32_pcix , + (void*)m68k_op_chk_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_aw , + (void*)m68k_op_chk_16_al , + (void*)m68k_op_chk_16_pcdi , + (void*)m68k_op_chk_16_pcix , + (void*)m68k_op_chk_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_extb_32 , + (void*)m68k_op_extb_32 , + (void*)m68k_op_extb_32 , + (void*)m68k_op_extb_32 , + (void*)m68k_op_extb_32 , + (void*)m68k_op_extb_32 , + (void*)m68k_op_extb_32 , + (void*)m68k_op_extb_32 , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_aw , + (void*)m68k_op_lea_32_al , + (void*)m68k_op_lea_32_pcdi , + (void*)m68k_op_lea_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_tst_8_d , + (void*)m68k_op_tst_8_d , + (void*)m68k_op_tst_8_d , + (void*)m68k_op_tst_8_d , + (void*)m68k_op_tst_8_d , + (void*)m68k_op_tst_8_d , + (void*)m68k_op_tst_8_d , + (void*)m68k_op_tst_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_tst_8_ai , + (void*)m68k_op_tst_8_ai , + (void*)m68k_op_tst_8_ai , + (void*)m68k_op_tst_8_ai , + (void*)m68k_op_tst_8_ai , + (void*)m68k_op_tst_8_ai , + (void*)m68k_op_tst_8_ai , + (void*)m68k_op_tst_8_ai , + (void*)m68k_op_tst_8_pi , + (void*)m68k_op_tst_8_pi , + (void*)m68k_op_tst_8_pi , + (void*)m68k_op_tst_8_pi , + (void*)m68k_op_tst_8_pi , + (void*)m68k_op_tst_8_pi , + (void*)m68k_op_tst_8_pi , + (void*)m68k_op_tst_8_pi7 , + (void*)m68k_op_tst_8_pd , + (void*)m68k_op_tst_8_pd , + (void*)m68k_op_tst_8_pd , + (void*)m68k_op_tst_8_pd , + (void*)m68k_op_tst_8_pd , + (void*)m68k_op_tst_8_pd , + (void*)m68k_op_tst_8_pd , + (void*)m68k_op_tst_8_pd7 , + (void*)m68k_op_tst_8_di , + (void*)m68k_op_tst_8_di , + (void*)m68k_op_tst_8_di , + (void*)m68k_op_tst_8_di , + (void*)m68k_op_tst_8_di , + (void*)m68k_op_tst_8_di , + (void*)m68k_op_tst_8_di , + (void*)m68k_op_tst_8_di , + (void*)m68k_op_tst_8_ix , + (void*)m68k_op_tst_8_ix , + (void*)m68k_op_tst_8_ix , + (void*)m68k_op_tst_8_ix , + (void*)m68k_op_tst_8_ix , + (void*)m68k_op_tst_8_ix , + (void*)m68k_op_tst_8_ix , + (void*)m68k_op_tst_8_ix , + (void*)m68k_op_tst_8_aw , + (void*)m68k_op_tst_8_al , + (void*)m68k_op_tst_8_pcdi , + (void*)m68k_op_tst_8_pcix , + (void*)m68k_op_tst_8_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_tst_16_d , + (void*)m68k_op_tst_16_d , + (void*)m68k_op_tst_16_d , + (void*)m68k_op_tst_16_d , + (void*)m68k_op_tst_16_d , + (void*)m68k_op_tst_16_d , + (void*)m68k_op_tst_16_d , + (void*)m68k_op_tst_16_d , + (void*)m68k_op_tst_16_a , + (void*)m68k_op_tst_16_a , + (void*)m68k_op_tst_16_a , + (void*)m68k_op_tst_16_a , + (void*)m68k_op_tst_16_a , + (void*)m68k_op_tst_16_a , + (void*)m68k_op_tst_16_a , + (void*)m68k_op_tst_16_a , + (void*)m68k_op_tst_16_ai , + (void*)m68k_op_tst_16_ai , + (void*)m68k_op_tst_16_ai , + (void*)m68k_op_tst_16_ai , + (void*)m68k_op_tst_16_ai , + (void*)m68k_op_tst_16_ai , + (void*)m68k_op_tst_16_ai , + (void*)m68k_op_tst_16_ai , + (void*)m68k_op_tst_16_pi , + (void*)m68k_op_tst_16_pi , + (void*)m68k_op_tst_16_pi , + (void*)m68k_op_tst_16_pi , + (void*)m68k_op_tst_16_pi , + (void*)m68k_op_tst_16_pi , + (void*)m68k_op_tst_16_pi , + (void*)m68k_op_tst_16_pi , + (void*)m68k_op_tst_16_pd , + (void*)m68k_op_tst_16_pd , + (void*)m68k_op_tst_16_pd , + (void*)m68k_op_tst_16_pd , + (void*)m68k_op_tst_16_pd , + (void*)m68k_op_tst_16_pd , + (void*)m68k_op_tst_16_pd , + (void*)m68k_op_tst_16_pd , + (void*)m68k_op_tst_16_di , + (void*)m68k_op_tst_16_di , + (void*)m68k_op_tst_16_di , + (void*)m68k_op_tst_16_di , + (void*)m68k_op_tst_16_di , + (void*)m68k_op_tst_16_di , + (void*)m68k_op_tst_16_di , + (void*)m68k_op_tst_16_di , + (void*)m68k_op_tst_16_ix , + (void*)m68k_op_tst_16_ix , + (void*)m68k_op_tst_16_ix , + (void*)m68k_op_tst_16_ix , + (void*)m68k_op_tst_16_ix , + (void*)m68k_op_tst_16_ix , + (void*)m68k_op_tst_16_ix , + (void*)m68k_op_tst_16_ix , + (void*)m68k_op_tst_16_aw , + (void*)m68k_op_tst_16_al , + (void*)m68k_op_tst_16_pcdi , + (void*)m68k_op_tst_16_pcix , + (void*)m68k_op_tst_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_tst_32_d , + (void*)m68k_op_tst_32_d , + (void*)m68k_op_tst_32_d , + (void*)m68k_op_tst_32_d , + (void*)m68k_op_tst_32_d , + (void*)m68k_op_tst_32_d , + (void*)m68k_op_tst_32_d , + (void*)m68k_op_tst_32_d , + (void*)m68k_op_tst_32_a , + (void*)m68k_op_tst_32_a , + (void*)m68k_op_tst_32_a , + (void*)m68k_op_tst_32_a , + (void*)m68k_op_tst_32_a , + (void*)m68k_op_tst_32_a , + (void*)m68k_op_tst_32_a , + (void*)m68k_op_tst_32_a , + (void*)m68k_op_tst_32_ai , + (void*)m68k_op_tst_32_ai , + (void*)m68k_op_tst_32_ai , + (void*)m68k_op_tst_32_ai , + (void*)m68k_op_tst_32_ai , + (void*)m68k_op_tst_32_ai , + (void*)m68k_op_tst_32_ai , + (void*)m68k_op_tst_32_ai , + (void*)m68k_op_tst_32_pi , + (void*)m68k_op_tst_32_pi , + (void*)m68k_op_tst_32_pi , + (void*)m68k_op_tst_32_pi , + (void*)m68k_op_tst_32_pi , + (void*)m68k_op_tst_32_pi , + (void*)m68k_op_tst_32_pi , + (void*)m68k_op_tst_32_pi , + (void*)m68k_op_tst_32_pd , + (void*)m68k_op_tst_32_pd , + (void*)m68k_op_tst_32_pd , + (void*)m68k_op_tst_32_pd , + (void*)m68k_op_tst_32_pd , + (void*)m68k_op_tst_32_pd , + (void*)m68k_op_tst_32_pd , + (void*)m68k_op_tst_32_pd , + (void*)m68k_op_tst_32_di , + (void*)m68k_op_tst_32_di , + (void*)m68k_op_tst_32_di , + (void*)m68k_op_tst_32_di , + (void*)m68k_op_tst_32_di , + (void*)m68k_op_tst_32_di , + (void*)m68k_op_tst_32_di , + (void*)m68k_op_tst_32_di , + (void*)m68k_op_tst_32_ix , + (void*)m68k_op_tst_32_ix , + (void*)m68k_op_tst_32_ix , + (void*)m68k_op_tst_32_ix , + (void*)m68k_op_tst_32_ix , + (void*)m68k_op_tst_32_ix , + (void*)m68k_op_tst_32_ix , + (void*)m68k_op_tst_32_ix , + (void*)m68k_op_tst_32_aw , + (void*)m68k_op_tst_32_al , + (void*)m68k_op_tst_32_pcdi , + (void*)m68k_op_tst_32_pcix , + (void*)m68k_op_tst_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_tas_8_d , + (void*)m68k_op_tas_8_d , + (void*)m68k_op_tas_8_d , + (void*)m68k_op_tas_8_d , + (void*)m68k_op_tas_8_d , + (void*)m68k_op_tas_8_d , + (void*)m68k_op_tas_8_d , + (void*)m68k_op_tas_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_tas_8_ai , + (void*)m68k_op_tas_8_ai , + (void*)m68k_op_tas_8_ai , + (void*)m68k_op_tas_8_ai , + (void*)m68k_op_tas_8_ai , + (void*)m68k_op_tas_8_ai , + (void*)m68k_op_tas_8_ai , + (void*)m68k_op_tas_8_ai , + (void*)m68k_op_tas_8_pi , + (void*)m68k_op_tas_8_pi , + (void*)m68k_op_tas_8_pi , + (void*)m68k_op_tas_8_pi , + (void*)m68k_op_tas_8_pi , + (void*)m68k_op_tas_8_pi , + (void*)m68k_op_tas_8_pi , + (void*)m68k_op_tas_8_pi7 , + (void*)m68k_op_tas_8_pd , + (void*)m68k_op_tas_8_pd , + (void*)m68k_op_tas_8_pd , + (void*)m68k_op_tas_8_pd , + (void*)m68k_op_tas_8_pd , + (void*)m68k_op_tas_8_pd , + (void*)m68k_op_tas_8_pd , + (void*)m68k_op_tas_8_pd7 , + (void*)m68k_op_tas_8_di , + (void*)m68k_op_tas_8_di , + (void*)m68k_op_tas_8_di , + (void*)m68k_op_tas_8_di , + (void*)m68k_op_tas_8_di , + (void*)m68k_op_tas_8_di , + (void*)m68k_op_tas_8_di , + (void*)m68k_op_tas_8_di , + (void*)m68k_op_tas_8_ix , + (void*)m68k_op_tas_8_ix , + (void*)m68k_op_tas_8_ix , + (void*)m68k_op_tas_8_ix , + (void*)m68k_op_tas_8_ix , + (void*)m68k_op_tas_8_ix , + (void*)m68k_op_tas_8_ix , + (void*)m68k_op_tas_8_ix , + (void*)m68k_op_tas_8_aw , + (void*)m68k_op_tas_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_aw , + (void*)m68k_op_chk_32_al , + (void*)m68k_op_chk_32_pcdi , + (void*)m68k_op_chk_32_pcix , + (void*)m68k_op_chk_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_aw , + (void*)m68k_op_chk_16_al , + (void*)m68k_op_chk_16_pcdi , + (void*)m68k_op_chk_16_pcix , + (void*)m68k_op_chk_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_aw , + (void*)m68k_op_lea_32_al , + (void*)m68k_op_lea_32_pcdi , + (void*)m68k_op_lea_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mull_32_d , + (void*)m68k_op_mull_32_d , + (void*)m68k_op_mull_32_d , + (void*)m68k_op_mull_32_d , + (void*)m68k_op_mull_32_d , + (void*)m68k_op_mull_32_d , + (void*)m68k_op_mull_32_d , + (void*)m68k_op_mull_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mull_32_ai , + (void*)m68k_op_mull_32_ai , + (void*)m68k_op_mull_32_ai , + (void*)m68k_op_mull_32_ai , + (void*)m68k_op_mull_32_ai , + (void*)m68k_op_mull_32_ai , + (void*)m68k_op_mull_32_ai , + (void*)m68k_op_mull_32_ai , + (void*)m68k_op_mull_32_pi , + (void*)m68k_op_mull_32_pi , + (void*)m68k_op_mull_32_pi , + (void*)m68k_op_mull_32_pi , + (void*)m68k_op_mull_32_pi , + (void*)m68k_op_mull_32_pi , + (void*)m68k_op_mull_32_pi , + (void*)m68k_op_mull_32_pi , + (void*)m68k_op_mull_32_pd , + (void*)m68k_op_mull_32_pd , + (void*)m68k_op_mull_32_pd , + (void*)m68k_op_mull_32_pd , + (void*)m68k_op_mull_32_pd , + (void*)m68k_op_mull_32_pd , + (void*)m68k_op_mull_32_pd , + (void*)m68k_op_mull_32_pd , + (void*)m68k_op_mull_32_di , + (void*)m68k_op_mull_32_di , + (void*)m68k_op_mull_32_di , + (void*)m68k_op_mull_32_di , + (void*)m68k_op_mull_32_di , + (void*)m68k_op_mull_32_di , + (void*)m68k_op_mull_32_di , + (void*)m68k_op_mull_32_di , + (void*)m68k_op_mull_32_ix , + (void*)m68k_op_mull_32_ix , + (void*)m68k_op_mull_32_ix , + (void*)m68k_op_mull_32_ix , + (void*)m68k_op_mull_32_ix , + (void*)m68k_op_mull_32_ix , + (void*)m68k_op_mull_32_ix , + (void*)m68k_op_mull_32_ix , + (void*)m68k_op_mull_32_aw , + (void*)m68k_op_mull_32_al , + (void*)m68k_op_mull_32_pcdi , + (void*)m68k_op_mull_32_pcix , + (void*)m68k_op_mull_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divl_32_d , + (void*)m68k_op_divl_32_d , + (void*)m68k_op_divl_32_d , + (void*)m68k_op_divl_32_d , + (void*)m68k_op_divl_32_d , + (void*)m68k_op_divl_32_d , + (void*)m68k_op_divl_32_d , + (void*)m68k_op_divl_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divl_32_ai , + (void*)m68k_op_divl_32_ai , + (void*)m68k_op_divl_32_ai , + (void*)m68k_op_divl_32_ai , + (void*)m68k_op_divl_32_ai , + (void*)m68k_op_divl_32_ai , + (void*)m68k_op_divl_32_ai , + (void*)m68k_op_divl_32_ai , + (void*)m68k_op_divl_32_pi , + (void*)m68k_op_divl_32_pi , + (void*)m68k_op_divl_32_pi , + (void*)m68k_op_divl_32_pi , + (void*)m68k_op_divl_32_pi , + (void*)m68k_op_divl_32_pi , + (void*)m68k_op_divl_32_pi , + (void*)m68k_op_divl_32_pi , + (void*)m68k_op_divl_32_pd , + (void*)m68k_op_divl_32_pd , + (void*)m68k_op_divl_32_pd , + (void*)m68k_op_divl_32_pd , + (void*)m68k_op_divl_32_pd , + (void*)m68k_op_divl_32_pd , + (void*)m68k_op_divl_32_pd , + (void*)m68k_op_divl_32_pd , + (void*)m68k_op_divl_32_di , + (void*)m68k_op_divl_32_di , + (void*)m68k_op_divl_32_di , + (void*)m68k_op_divl_32_di , + (void*)m68k_op_divl_32_di , + (void*)m68k_op_divl_32_di , + (void*)m68k_op_divl_32_di , + (void*)m68k_op_divl_32_di , + (void*)m68k_op_divl_32_ix , + (void*)m68k_op_divl_32_ix , + (void*)m68k_op_divl_32_ix , + (void*)m68k_op_divl_32_ix , + (void*)m68k_op_divl_32_ix , + (void*)m68k_op_divl_32_ix , + (void*)m68k_op_divl_32_ix , + (void*)m68k_op_divl_32_ix , + (void*)m68k_op_divl_32_aw , + (void*)m68k_op_divl_32_al , + (void*)m68k_op_divl_32_pcdi , + (void*)m68k_op_divl_32_pcix , + (void*)m68k_op_divl_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movem_16_er_ai , + (void*)m68k_op_movem_16_er_ai , + (void*)m68k_op_movem_16_er_ai , + (void*)m68k_op_movem_16_er_ai , + (void*)m68k_op_movem_16_er_ai , + (void*)m68k_op_movem_16_er_ai , + (void*)m68k_op_movem_16_er_ai , + (void*)m68k_op_movem_16_er_ai , + (void*)m68k_op_movem_16_er_pi , + (void*)m68k_op_movem_16_er_pi , + (void*)m68k_op_movem_16_er_pi , + (void*)m68k_op_movem_16_er_pi , + (void*)m68k_op_movem_16_er_pi , + (void*)m68k_op_movem_16_er_pi , + (void*)m68k_op_movem_16_er_pi , + (void*)m68k_op_movem_16_er_pi , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movem_16_er_di , + (void*)m68k_op_movem_16_er_di , + (void*)m68k_op_movem_16_er_di , + (void*)m68k_op_movem_16_er_di , + (void*)m68k_op_movem_16_er_di , + (void*)m68k_op_movem_16_er_di , + (void*)m68k_op_movem_16_er_di , + (void*)m68k_op_movem_16_er_di , + (void*)m68k_op_movem_16_er_ix , + (void*)m68k_op_movem_16_er_ix , + (void*)m68k_op_movem_16_er_ix , + (void*)m68k_op_movem_16_er_ix , + (void*)m68k_op_movem_16_er_ix , + (void*)m68k_op_movem_16_er_ix , + (void*)m68k_op_movem_16_er_ix , + (void*)m68k_op_movem_16_er_ix , + (void*)m68k_op_movem_16_er_aw , + (void*)m68k_op_movem_16_er_al , + (void*)m68k_op_movem_16_er_pcdi , + (void*)m68k_op_movem_16_er_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movem_32_er_ai , + (void*)m68k_op_movem_32_er_ai , + (void*)m68k_op_movem_32_er_ai , + (void*)m68k_op_movem_32_er_ai , + (void*)m68k_op_movem_32_er_ai , + (void*)m68k_op_movem_32_er_ai , + (void*)m68k_op_movem_32_er_ai , + (void*)m68k_op_movem_32_er_ai , + (void*)m68k_op_movem_32_er_pi , + (void*)m68k_op_movem_32_er_pi , + (void*)m68k_op_movem_32_er_pi , + (void*)m68k_op_movem_32_er_pi , + (void*)m68k_op_movem_32_er_pi , + (void*)m68k_op_movem_32_er_pi , + (void*)m68k_op_movem_32_er_pi , + (void*)m68k_op_movem_32_er_pi , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movem_32_er_di , + (void*)m68k_op_movem_32_er_di , + (void*)m68k_op_movem_32_er_di , + (void*)m68k_op_movem_32_er_di , + (void*)m68k_op_movem_32_er_di , + (void*)m68k_op_movem_32_er_di , + (void*)m68k_op_movem_32_er_di , + (void*)m68k_op_movem_32_er_di , + (void*)m68k_op_movem_32_er_ix , + (void*)m68k_op_movem_32_er_ix , + (void*)m68k_op_movem_32_er_ix , + (void*)m68k_op_movem_32_er_ix , + (void*)m68k_op_movem_32_er_ix , + (void*)m68k_op_movem_32_er_ix , + (void*)m68k_op_movem_32_er_ix , + (void*)m68k_op_movem_32_er_ix , + (void*)m68k_op_movem_32_er_aw , + (void*)m68k_op_movem_32_er_al , + (void*)m68k_op_movem_32_er_pcdi , + (void*)m68k_op_movem_32_er_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_aw , + (void*)m68k_op_chk_32_al , + (void*)m68k_op_chk_32_pcdi , + (void*)m68k_op_chk_32_pcix , + (void*)m68k_op_chk_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_aw , + (void*)m68k_op_chk_16_al , + (void*)m68k_op_chk_16_pcdi , + (void*)m68k_op_chk_16_pcix , + (void*)m68k_op_chk_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_aw , + (void*)m68k_op_lea_32_al , + (void*)m68k_op_lea_32_pcdi , + (void*)m68k_op_lea_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_trap , + (void*)m68k_op_link_16 , + (void*)m68k_op_link_16 , + (void*)m68k_op_link_16 , + (void*)m68k_op_link_16 , + (void*)m68k_op_link_16 , + (void*)m68k_op_link_16 , + (void*)m68k_op_link_16 , + (void*)m68k_op_link_16_a7 , + (void*)m68k_op_unlk_32 , + (void*)m68k_op_unlk_32 , + (void*)m68k_op_unlk_32 , + (void*)m68k_op_unlk_32 , + (void*)m68k_op_unlk_32 , + (void*)m68k_op_unlk_32 , + (void*)m68k_op_unlk_32 , + (void*)m68k_op_unlk_32_a7 , + (void*)m68k_op_move_32_tou , + (void*)m68k_op_move_32_tou , + (void*)m68k_op_move_32_tou , + (void*)m68k_op_move_32_tou , + (void*)m68k_op_move_32_tou , + (void*)m68k_op_move_32_tou , + (void*)m68k_op_move_32_tou , + (void*)m68k_op_move_32_tou , + (void*)m68k_op_move_32_fru , + (void*)m68k_op_move_32_fru , + (void*)m68k_op_move_32_fru , + (void*)m68k_op_move_32_fru , + (void*)m68k_op_move_32_fru , + (void*)m68k_op_move_32_fru , + (void*)m68k_op_move_32_fru , + (void*)m68k_op_move_32_fru , + (void*)m68k_op_reset , + (void*)m68k_op_nop , + (void*)m68k_op_stop , + (void*)m68k_op_rte_32 , + (void*)m68k_op_rtd_32 , + (void*)m68k_op_rts_32 , + (void*)m68k_op_trapv , + (void*)m68k_op_rtr_32 , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_movec_32_cr , + (void*)m68k_op_movec_32_rc , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_jsr_32_ai , + (void*)m68k_op_jsr_32_ai , + (void*)m68k_op_jsr_32_ai , + (void*)m68k_op_jsr_32_ai , + (void*)m68k_op_jsr_32_ai , + (void*)m68k_op_jsr_32_ai , + (void*)m68k_op_jsr_32_ai , + (void*)m68k_op_jsr_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_jsr_32_di , + (void*)m68k_op_jsr_32_di , + (void*)m68k_op_jsr_32_di , + (void*)m68k_op_jsr_32_di , + (void*)m68k_op_jsr_32_di , + (void*)m68k_op_jsr_32_di , + (void*)m68k_op_jsr_32_di , + (void*)m68k_op_jsr_32_di , + (void*)m68k_op_jsr_32_ix , + (void*)m68k_op_jsr_32_ix , + (void*)m68k_op_jsr_32_ix , + (void*)m68k_op_jsr_32_ix , + (void*)m68k_op_jsr_32_ix , + (void*)m68k_op_jsr_32_ix , + (void*)m68k_op_jsr_32_ix , + (void*)m68k_op_jsr_32_ix , + (void*)m68k_op_jsr_32_aw , + (void*)m68k_op_jsr_32_al , + (void*)m68k_op_jsr_32_pcdi , + (void*)m68k_op_jsr_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_jmp_32_ai , + (void*)m68k_op_jmp_32_ai , + (void*)m68k_op_jmp_32_ai , + (void*)m68k_op_jmp_32_ai , + (void*)m68k_op_jmp_32_ai , + (void*)m68k_op_jmp_32_ai , + (void*)m68k_op_jmp_32_ai , + (void*)m68k_op_jmp_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_jmp_32_di , + (void*)m68k_op_jmp_32_di , + (void*)m68k_op_jmp_32_di , + (void*)m68k_op_jmp_32_di , + (void*)m68k_op_jmp_32_di , + (void*)m68k_op_jmp_32_di , + (void*)m68k_op_jmp_32_di , + (void*)m68k_op_jmp_32_di , + (void*)m68k_op_jmp_32_ix , + (void*)m68k_op_jmp_32_ix , + (void*)m68k_op_jmp_32_ix , + (void*)m68k_op_jmp_32_ix , + (void*)m68k_op_jmp_32_ix , + (void*)m68k_op_jmp_32_ix , + (void*)m68k_op_jmp_32_ix , + (void*)m68k_op_jmp_32_ix , + (void*)m68k_op_jmp_32_aw , + (void*)m68k_op_jmp_32_al , + (void*)m68k_op_jmp_32_pcdi , + (void*)m68k_op_jmp_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_chk_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_ai , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pi , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_pd , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_di , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_ix , + (void*)m68k_op_chk_32_aw , + (void*)m68k_op_chk_32_al , + (void*)m68k_op_chk_32_pcdi , + (void*)m68k_op_chk_32_pcix , + (void*)m68k_op_chk_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_chk_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_ai , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pi , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_pd , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_di , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_ix , + (void*)m68k_op_chk_16_aw , + (void*)m68k_op_chk_16_al , + (void*)m68k_op_chk_16_pcdi , + (void*)m68k_op_chk_16_pcix , + (void*)m68k_op_chk_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_lea_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_di , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_ix , + (void*)m68k_op_lea_32_aw , + (void*)m68k_op_lea_32_al , + (void*)m68k_op_lea_32_pcdi , + (void*)m68k_op_lea_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi7 , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd7 , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_aw , + (void*)m68k_op_addq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_aw , + (void*)m68k_op_addq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_aw , + (void*)m68k_op_addq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_st_8_d , + (void*)m68k_op_st_8_d , + (void*)m68k_op_st_8_d , + (void*)m68k_op_st_8_d , + (void*)m68k_op_st_8_d , + (void*)m68k_op_st_8_d , + (void*)m68k_op_st_8_d , + (void*)m68k_op_st_8_d , + (void*)m68k_op_dbt_16 , + (void*)m68k_op_dbt_16 , + (void*)m68k_op_dbt_16 , + (void*)m68k_op_dbt_16 , + (void*)m68k_op_dbt_16 , + (void*)m68k_op_dbt_16 , + (void*)m68k_op_dbt_16 , + (void*)m68k_op_dbt_16 , + (void*)m68k_op_st_8_ai , + (void*)m68k_op_st_8_ai , + (void*)m68k_op_st_8_ai , + (void*)m68k_op_st_8_ai , + (void*)m68k_op_st_8_ai , + (void*)m68k_op_st_8_ai , + (void*)m68k_op_st_8_ai , + (void*)m68k_op_st_8_ai , + (void*)m68k_op_st_8_pi , + (void*)m68k_op_st_8_pi , + (void*)m68k_op_st_8_pi , + (void*)m68k_op_st_8_pi , + (void*)m68k_op_st_8_pi , + (void*)m68k_op_st_8_pi , + (void*)m68k_op_st_8_pi , + (void*)m68k_op_st_8_pi7 , + (void*)m68k_op_st_8_pd , + (void*)m68k_op_st_8_pd , + (void*)m68k_op_st_8_pd , + (void*)m68k_op_st_8_pd , + (void*)m68k_op_st_8_pd , + (void*)m68k_op_st_8_pd , + (void*)m68k_op_st_8_pd , + (void*)m68k_op_st_8_pd7 , + (void*)m68k_op_st_8_di , + (void*)m68k_op_st_8_di , + (void*)m68k_op_st_8_di , + (void*)m68k_op_st_8_di , + (void*)m68k_op_st_8_di , + (void*)m68k_op_st_8_di , + (void*)m68k_op_st_8_di , + (void*)m68k_op_st_8_di , + (void*)m68k_op_st_8_ix , + (void*)m68k_op_st_8_ix , + (void*)m68k_op_st_8_ix , + (void*)m68k_op_st_8_ix , + (void*)m68k_op_st_8_ix , + (void*)m68k_op_st_8_ix , + (void*)m68k_op_st_8_ix , + (void*)m68k_op_st_8_ix , + (void*)m68k_op_st_8_aw , + (void*)m68k_op_st_8_al , + (void*)m68k_op_trapt_16 , + (void*)m68k_op_trapt_32 , + (void*)m68k_op_trapt , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi7 , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd7 , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_aw , + (void*)m68k_op_subq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_aw , + (void*)m68k_op_subq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_aw , + (void*)m68k_op_subq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sf_8_d , + (void*)m68k_op_sf_8_d , + (void*)m68k_op_sf_8_d , + (void*)m68k_op_sf_8_d , + (void*)m68k_op_sf_8_d , + (void*)m68k_op_sf_8_d , + (void*)m68k_op_sf_8_d , + (void*)m68k_op_sf_8_d , + (void*)m68k_op_dbf_16 , + (void*)m68k_op_dbf_16 , + (void*)m68k_op_dbf_16 , + (void*)m68k_op_dbf_16 , + (void*)m68k_op_dbf_16 , + (void*)m68k_op_dbf_16 , + (void*)m68k_op_dbf_16 , + (void*)m68k_op_dbf_16 , + (void*)m68k_op_sf_8_ai , + (void*)m68k_op_sf_8_ai , + (void*)m68k_op_sf_8_ai , + (void*)m68k_op_sf_8_ai , + (void*)m68k_op_sf_8_ai , + (void*)m68k_op_sf_8_ai , + (void*)m68k_op_sf_8_ai , + (void*)m68k_op_sf_8_ai , + (void*)m68k_op_sf_8_pi , + (void*)m68k_op_sf_8_pi , + (void*)m68k_op_sf_8_pi , + (void*)m68k_op_sf_8_pi , + (void*)m68k_op_sf_8_pi , + (void*)m68k_op_sf_8_pi , + (void*)m68k_op_sf_8_pi , + (void*)m68k_op_sf_8_pi7 , + (void*)m68k_op_sf_8_pd , + (void*)m68k_op_sf_8_pd , + (void*)m68k_op_sf_8_pd , + (void*)m68k_op_sf_8_pd , + (void*)m68k_op_sf_8_pd , + (void*)m68k_op_sf_8_pd , + (void*)m68k_op_sf_8_pd , + (void*)m68k_op_sf_8_pd7 , + (void*)m68k_op_sf_8_di , + (void*)m68k_op_sf_8_di , + (void*)m68k_op_sf_8_di , + (void*)m68k_op_sf_8_di , + (void*)m68k_op_sf_8_di , + (void*)m68k_op_sf_8_di , + (void*)m68k_op_sf_8_di , + (void*)m68k_op_sf_8_di , + (void*)m68k_op_sf_8_ix , + (void*)m68k_op_sf_8_ix , + (void*)m68k_op_sf_8_ix , + (void*)m68k_op_sf_8_ix , + (void*)m68k_op_sf_8_ix , + (void*)m68k_op_sf_8_ix , + (void*)m68k_op_sf_8_ix , + (void*)m68k_op_sf_8_ix , + (void*)m68k_op_sf_8_aw , + (void*)m68k_op_sf_8_al , + (void*)m68k_op_trapf_16 , + (void*)m68k_op_trapf_32 , + (void*)m68k_op_trapf , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi7 , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd7 , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_aw , + (void*)m68k_op_addq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_aw , + (void*)m68k_op_addq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_aw , + (void*)m68k_op_addq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_shi_8_d , + (void*)m68k_op_shi_8_d , + (void*)m68k_op_shi_8_d , + (void*)m68k_op_shi_8_d , + (void*)m68k_op_shi_8_d , + (void*)m68k_op_shi_8_d , + (void*)m68k_op_shi_8_d , + (void*)m68k_op_shi_8_d , + (void*)m68k_op_dbhi_16 , + (void*)m68k_op_dbhi_16 , + (void*)m68k_op_dbhi_16 , + (void*)m68k_op_dbhi_16 , + (void*)m68k_op_dbhi_16 , + (void*)m68k_op_dbhi_16 , + (void*)m68k_op_dbhi_16 , + (void*)m68k_op_dbhi_16 , + (void*)m68k_op_shi_8_ai , + (void*)m68k_op_shi_8_ai , + (void*)m68k_op_shi_8_ai , + (void*)m68k_op_shi_8_ai , + (void*)m68k_op_shi_8_ai , + (void*)m68k_op_shi_8_ai , + (void*)m68k_op_shi_8_ai , + (void*)m68k_op_shi_8_ai , + (void*)m68k_op_shi_8_pi , + (void*)m68k_op_shi_8_pi , + (void*)m68k_op_shi_8_pi , + (void*)m68k_op_shi_8_pi , + (void*)m68k_op_shi_8_pi , + (void*)m68k_op_shi_8_pi , + (void*)m68k_op_shi_8_pi , + (void*)m68k_op_shi_8_pi7 , + (void*)m68k_op_shi_8_pd , + (void*)m68k_op_shi_8_pd , + (void*)m68k_op_shi_8_pd , + (void*)m68k_op_shi_8_pd , + (void*)m68k_op_shi_8_pd , + (void*)m68k_op_shi_8_pd , + (void*)m68k_op_shi_8_pd , + (void*)m68k_op_shi_8_pd7 , + (void*)m68k_op_shi_8_di , + (void*)m68k_op_shi_8_di , + (void*)m68k_op_shi_8_di , + (void*)m68k_op_shi_8_di , + (void*)m68k_op_shi_8_di , + (void*)m68k_op_shi_8_di , + (void*)m68k_op_shi_8_di , + (void*)m68k_op_shi_8_di , + (void*)m68k_op_shi_8_ix , + (void*)m68k_op_shi_8_ix , + (void*)m68k_op_shi_8_ix , + (void*)m68k_op_shi_8_ix , + (void*)m68k_op_shi_8_ix , + (void*)m68k_op_shi_8_ix , + (void*)m68k_op_shi_8_ix , + (void*)m68k_op_shi_8_ix , + (void*)m68k_op_shi_8_aw , + (void*)m68k_op_shi_8_al , + (void*)m68k_op_traphi_16 , + (void*)m68k_op_traphi_32 , + (void*)m68k_op_traphi , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi7 , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd7 , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_aw , + (void*)m68k_op_subq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_aw , + (void*)m68k_op_subq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_aw , + (void*)m68k_op_subq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sls_8_d , + (void*)m68k_op_sls_8_d , + (void*)m68k_op_sls_8_d , + (void*)m68k_op_sls_8_d , + (void*)m68k_op_sls_8_d , + (void*)m68k_op_sls_8_d , + (void*)m68k_op_sls_8_d , + (void*)m68k_op_sls_8_d , + (void*)m68k_op_dbls_16 , + (void*)m68k_op_dbls_16 , + (void*)m68k_op_dbls_16 , + (void*)m68k_op_dbls_16 , + (void*)m68k_op_dbls_16 , + (void*)m68k_op_dbls_16 , + (void*)m68k_op_dbls_16 , + (void*)m68k_op_dbls_16 , + (void*)m68k_op_sls_8_ai , + (void*)m68k_op_sls_8_ai , + (void*)m68k_op_sls_8_ai , + (void*)m68k_op_sls_8_ai , + (void*)m68k_op_sls_8_ai , + (void*)m68k_op_sls_8_ai , + (void*)m68k_op_sls_8_ai , + (void*)m68k_op_sls_8_ai , + (void*)m68k_op_sls_8_pi , + (void*)m68k_op_sls_8_pi , + (void*)m68k_op_sls_8_pi , + (void*)m68k_op_sls_8_pi , + (void*)m68k_op_sls_8_pi , + (void*)m68k_op_sls_8_pi , + (void*)m68k_op_sls_8_pi , + (void*)m68k_op_sls_8_pi7 , + (void*)m68k_op_sls_8_pd , + (void*)m68k_op_sls_8_pd , + (void*)m68k_op_sls_8_pd , + (void*)m68k_op_sls_8_pd , + (void*)m68k_op_sls_8_pd , + (void*)m68k_op_sls_8_pd , + (void*)m68k_op_sls_8_pd , + (void*)m68k_op_sls_8_pd7 , + (void*)m68k_op_sls_8_di , + (void*)m68k_op_sls_8_di , + (void*)m68k_op_sls_8_di , + (void*)m68k_op_sls_8_di , + (void*)m68k_op_sls_8_di , + (void*)m68k_op_sls_8_di , + (void*)m68k_op_sls_8_di , + (void*)m68k_op_sls_8_di , + (void*)m68k_op_sls_8_ix , + (void*)m68k_op_sls_8_ix , + (void*)m68k_op_sls_8_ix , + (void*)m68k_op_sls_8_ix , + (void*)m68k_op_sls_8_ix , + (void*)m68k_op_sls_8_ix , + (void*)m68k_op_sls_8_ix , + (void*)m68k_op_sls_8_ix , + (void*)m68k_op_sls_8_aw , + (void*)m68k_op_sls_8_al , + (void*)m68k_op_trapls_16 , + (void*)m68k_op_trapls_32 , + (void*)m68k_op_trapls , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi7 , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd7 , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_aw , + (void*)m68k_op_addq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_aw , + (void*)m68k_op_addq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_aw , + (void*)m68k_op_addq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_scc_8_d , + (void*)m68k_op_scc_8_d , + (void*)m68k_op_scc_8_d , + (void*)m68k_op_scc_8_d , + (void*)m68k_op_scc_8_d , + (void*)m68k_op_scc_8_d , + (void*)m68k_op_scc_8_d , + (void*)m68k_op_scc_8_d , + (void*)m68k_op_dbcc_16 , + (void*)m68k_op_dbcc_16 , + (void*)m68k_op_dbcc_16 , + (void*)m68k_op_dbcc_16 , + (void*)m68k_op_dbcc_16 , + (void*)m68k_op_dbcc_16 , + (void*)m68k_op_dbcc_16 , + (void*)m68k_op_dbcc_16 , + (void*)m68k_op_scc_8_ai , + (void*)m68k_op_scc_8_ai , + (void*)m68k_op_scc_8_ai , + (void*)m68k_op_scc_8_ai , + (void*)m68k_op_scc_8_ai , + (void*)m68k_op_scc_8_ai , + (void*)m68k_op_scc_8_ai , + (void*)m68k_op_scc_8_ai , + (void*)m68k_op_scc_8_pi , + (void*)m68k_op_scc_8_pi , + (void*)m68k_op_scc_8_pi , + (void*)m68k_op_scc_8_pi , + (void*)m68k_op_scc_8_pi , + (void*)m68k_op_scc_8_pi , + (void*)m68k_op_scc_8_pi , + (void*)m68k_op_scc_8_pi7 , + (void*)m68k_op_scc_8_pd , + (void*)m68k_op_scc_8_pd , + (void*)m68k_op_scc_8_pd , + (void*)m68k_op_scc_8_pd , + (void*)m68k_op_scc_8_pd , + (void*)m68k_op_scc_8_pd , + (void*)m68k_op_scc_8_pd , + (void*)m68k_op_scc_8_pd7 , + (void*)m68k_op_scc_8_di , + (void*)m68k_op_scc_8_di , + (void*)m68k_op_scc_8_di , + (void*)m68k_op_scc_8_di , + (void*)m68k_op_scc_8_di , + (void*)m68k_op_scc_8_di , + (void*)m68k_op_scc_8_di , + (void*)m68k_op_scc_8_di , + (void*)m68k_op_scc_8_ix , + (void*)m68k_op_scc_8_ix , + (void*)m68k_op_scc_8_ix , + (void*)m68k_op_scc_8_ix , + (void*)m68k_op_scc_8_ix , + (void*)m68k_op_scc_8_ix , + (void*)m68k_op_scc_8_ix , + (void*)m68k_op_scc_8_ix , + (void*)m68k_op_scc_8_aw , + (void*)m68k_op_scc_8_al , + (void*)m68k_op_trapcc_16 , + (void*)m68k_op_trapcc_32 , + (void*)m68k_op_trapcc , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi7 , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd7 , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_aw , + (void*)m68k_op_subq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_aw , + (void*)m68k_op_subq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_aw , + (void*)m68k_op_subq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_scs_8_d , + (void*)m68k_op_scs_8_d , + (void*)m68k_op_scs_8_d , + (void*)m68k_op_scs_8_d , + (void*)m68k_op_scs_8_d , + (void*)m68k_op_scs_8_d , + (void*)m68k_op_scs_8_d , + (void*)m68k_op_scs_8_d , + (void*)m68k_op_dbcs_16 , + (void*)m68k_op_dbcs_16 , + (void*)m68k_op_dbcs_16 , + (void*)m68k_op_dbcs_16 , + (void*)m68k_op_dbcs_16 , + (void*)m68k_op_dbcs_16 , + (void*)m68k_op_dbcs_16 , + (void*)m68k_op_dbcs_16 , + (void*)m68k_op_scs_8_ai , + (void*)m68k_op_scs_8_ai , + (void*)m68k_op_scs_8_ai , + (void*)m68k_op_scs_8_ai , + (void*)m68k_op_scs_8_ai , + (void*)m68k_op_scs_8_ai , + (void*)m68k_op_scs_8_ai , + (void*)m68k_op_scs_8_ai , + (void*)m68k_op_scs_8_pi , + (void*)m68k_op_scs_8_pi , + (void*)m68k_op_scs_8_pi , + (void*)m68k_op_scs_8_pi , + (void*)m68k_op_scs_8_pi , + (void*)m68k_op_scs_8_pi , + (void*)m68k_op_scs_8_pi , + (void*)m68k_op_scs_8_pi7 , + (void*)m68k_op_scs_8_pd , + (void*)m68k_op_scs_8_pd , + (void*)m68k_op_scs_8_pd , + (void*)m68k_op_scs_8_pd , + (void*)m68k_op_scs_8_pd , + (void*)m68k_op_scs_8_pd , + (void*)m68k_op_scs_8_pd , + (void*)m68k_op_scs_8_pd7 , + (void*)m68k_op_scs_8_di , + (void*)m68k_op_scs_8_di , + (void*)m68k_op_scs_8_di , + (void*)m68k_op_scs_8_di , + (void*)m68k_op_scs_8_di , + (void*)m68k_op_scs_8_di , + (void*)m68k_op_scs_8_di , + (void*)m68k_op_scs_8_di , + (void*)m68k_op_scs_8_ix , + (void*)m68k_op_scs_8_ix , + (void*)m68k_op_scs_8_ix , + (void*)m68k_op_scs_8_ix , + (void*)m68k_op_scs_8_ix , + (void*)m68k_op_scs_8_ix , + (void*)m68k_op_scs_8_ix , + (void*)m68k_op_scs_8_ix , + (void*)m68k_op_scs_8_aw , + (void*)m68k_op_scs_8_al , + (void*)m68k_op_trapcs_16 , + (void*)m68k_op_trapcs_32 , + (void*)m68k_op_trapcs , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi7 , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd7 , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_aw , + (void*)m68k_op_addq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_aw , + (void*)m68k_op_addq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_aw , + (void*)m68k_op_addq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sne_8_d , + (void*)m68k_op_sne_8_d , + (void*)m68k_op_sne_8_d , + (void*)m68k_op_sne_8_d , + (void*)m68k_op_sne_8_d , + (void*)m68k_op_sne_8_d , + (void*)m68k_op_sne_8_d , + (void*)m68k_op_sne_8_d , + (void*)m68k_op_dbne_16 , + (void*)m68k_op_dbne_16 , + (void*)m68k_op_dbne_16 , + (void*)m68k_op_dbne_16 , + (void*)m68k_op_dbne_16 , + (void*)m68k_op_dbne_16 , + (void*)m68k_op_dbne_16 , + (void*)m68k_op_dbne_16 , + (void*)m68k_op_sne_8_ai , + (void*)m68k_op_sne_8_ai , + (void*)m68k_op_sne_8_ai , + (void*)m68k_op_sne_8_ai , + (void*)m68k_op_sne_8_ai , + (void*)m68k_op_sne_8_ai , + (void*)m68k_op_sne_8_ai , + (void*)m68k_op_sne_8_ai , + (void*)m68k_op_sne_8_pi , + (void*)m68k_op_sne_8_pi , + (void*)m68k_op_sne_8_pi , + (void*)m68k_op_sne_8_pi , + (void*)m68k_op_sne_8_pi , + (void*)m68k_op_sne_8_pi , + (void*)m68k_op_sne_8_pi , + (void*)m68k_op_sne_8_pi7 , + (void*)m68k_op_sne_8_pd , + (void*)m68k_op_sne_8_pd , + (void*)m68k_op_sne_8_pd , + (void*)m68k_op_sne_8_pd , + (void*)m68k_op_sne_8_pd , + (void*)m68k_op_sne_8_pd , + (void*)m68k_op_sne_8_pd , + (void*)m68k_op_sne_8_pd7 , + (void*)m68k_op_sne_8_di , + (void*)m68k_op_sne_8_di , + (void*)m68k_op_sne_8_di , + (void*)m68k_op_sne_8_di , + (void*)m68k_op_sne_8_di , + (void*)m68k_op_sne_8_di , + (void*)m68k_op_sne_8_di , + (void*)m68k_op_sne_8_di , + (void*)m68k_op_sne_8_ix , + (void*)m68k_op_sne_8_ix , + (void*)m68k_op_sne_8_ix , + (void*)m68k_op_sne_8_ix , + (void*)m68k_op_sne_8_ix , + (void*)m68k_op_sne_8_ix , + (void*)m68k_op_sne_8_ix , + (void*)m68k_op_sne_8_ix , + (void*)m68k_op_sne_8_aw , + (void*)m68k_op_sne_8_al , + (void*)m68k_op_trapne_16 , + (void*)m68k_op_trapne_32 , + (void*)m68k_op_trapne , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi7 , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd7 , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_aw , + (void*)m68k_op_subq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_aw , + (void*)m68k_op_subq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_aw , + (void*)m68k_op_subq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_seq_8_d , + (void*)m68k_op_seq_8_d , + (void*)m68k_op_seq_8_d , + (void*)m68k_op_seq_8_d , + (void*)m68k_op_seq_8_d , + (void*)m68k_op_seq_8_d , + (void*)m68k_op_seq_8_d , + (void*)m68k_op_seq_8_d , + (void*)m68k_op_dbeq_16 , + (void*)m68k_op_dbeq_16 , + (void*)m68k_op_dbeq_16 , + (void*)m68k_op_dbeq_16 , + (void*)m68k_op_dbeq_16 , + (void*)m68k_op_dbeq_16 , + (void*)m68k_op_dbeq_16 , + (void*)m68k_op_dbeq_16 , + (void*)m68k_op_seq_8_ai , + (void*)m68k_op_seq_8_ai , + (void*)m68k_op_seq_8_ai , + (void*)m68k_op_seq_8_ai , + (void*)m68k_op_seq_8_ai , + (void*)m68k_op_seq_8_ai , + (void*)m68k_op_seq_8_ai , + (void*)m68k_op_seq_8_ai , + (void*)m68k_op_seq_8_pi , + (void*)m68k_op_seq_8_pi , + (void*)m68k_op_seq_8_pi , + (void*)m68k_op_seq_8_pi , + (void*)m68k_op_seq_8_pi , + (void*)m68k_op_seq_8_pi , + (void*)m68k_op_seq_8_pi , + (void*)m68k_op_seq_8_pi7 , + (void*)m68k_op_seq_8_pd , + (void*)m68k_op_seq_8_pd , + (void*)m68k_op_seq_8_pd , + (void*)m68k_op_seq_8_pd , + (void*)m68k_op_seq_8_pd , + (void*)m68k_op_seq_8_pd , + (void*)m68k_op_seq_8_pd , + (void*)m68k_op_seq_8_pd7 , + (void*)m68k_op_seq_8_di , + (void*)m68k_op_seq_8_di , + (void*)m68k_op_seq_8_di , + (void*)m68k_op_seq_8_di , + (void*)m68k_op_seq_8_di , + (void*)m68k_op_seq_8_di , + (void*)m68k_op_seq_8_di , + (void*)m68k_op_seq_8_di , + (void*)m68k_op_seq_8_ix , + (void*)m68k_op_seq_8_ix , + (void*)m68k_op_seq_8_ix , + (void*)m68k_op_seq_8_ix , + (void*)m68k_op_seq_8_ix , + (void*)m68k_op_seq_8_ix , + (void*)m68k_op_seq_8_ix , + (void*)m68k_op_seq_8_ix , + (void*)m68k_op_seq_8_aw , + (void*)m68k_op_seq_8_al , + (void*)m68k_op_trapeq_16 , + (void*)m68k_op_trapeq_32 , + (void*)m68k_op_trapeq , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi7 , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd7 , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_aw , + (void*)m68k_op_addq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_aw , + (void*)m68k_op_addq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_aw , + (void*)m68k_op_addq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_svc_8_d , + (void*)m68k_op_svc_8_d , + (void*)m68k_op_svc_8_d , + (void*)m68k_op_svc_8_d , + (void*)m68k_op_svc_8_d , + (void*)m68k_op_svc_8_d , + (void*)m68k_op_svc_8_d , + (void*)m68k_op_svc_8_d , + (void*)m68k_op_dbvc_16 , + (void*)m68k_op_dbvc_16 , + (void*)m68k_op_dbvc_16 , + (void*)m68k_op_dbvc_16 , + (void*)m68k_op_dbvc_16 , + (void*)m68k_op_dbvc_16 , + (void*)m68k_op_dbvc_16 , + (void*)m68k_op_dbvc_16 , + (void*)m68k_op_svc_8_ai , + (void*)m68k_op_svc_8_ai , + (void*)m68k_op_svc_8_ai , + (void*)m68k_op_svc_8_ai , + (void*)m68k_op_svc_8_ai , + (void*)m68k_op_svc_8_ai , + (void*)m68k_op_svc_8_ai , + (void*)m68k_op_svc_8_ai , + (void*)m68k_op_svc_8_pi , + (void*)m68k_op_svc_8_pi , + (void*)m68k_op_svc_8_pi , + (void*)m68k_op_svc_8_pi , + (void*)m68k_op_svc_8_pi , + (void*)m68k_op_svc_8_pi , + (void*)m68k_op_svc_8_pi , + (void*)m68k_op_svc_8_pi7 , + (void*)m68k_op_svc_8_pd , + (void*)m68k_op_svc_8_pd , + (void*)m68k_op_svc_8_pd , + (void*)m68k_op_svc_8_pd , + (void*)m68k_op_svc_8_pd , + (void*)m68k_op_svc_8_pd , + (void*)m68k_op_svc_8_pd , + (void*)m68k_op_svc_8_pd7 , + (void*)m68k_op_svc_8_di , + (void*)m68k_op_svc_8_di , + (void*)m68k_op_svc_8_di , + (void*)m68k_op_svc_8_di , + (void*)m68k_op_svc_8_di , + (void*)m68k_op_svc_8_di , + (void*)m68k_op_svc_8_di , + (void*)m68k_op_svc_8_di , + (void*)m68k_op_svc_8_ix , + (void*)m68k_op_svc_8_ix , + (void*)m68k_op_svc_8_ix , + (void*)m68k_op_svc_8_ix , + (void*)m68k_op_svc_8_ix , + (void*)m68k_op_svc_8_ix , + (void*)m68k_op_svc_8_ix , + (void*)m68k_op_svc_8_ix , + (void*)m68k_op_svc_8_aw , + (void*)m68k_op_svc_8_al , + (void*)m68k_op_trapvc_16 , + (void*)m68k_op_trapvc_32 , + (void*)m68k_op_trapvc , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi7 , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd7 , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_aw , + (void*)m68k_op_subq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_aw , + (void*)m68k_op_subq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_aw , + (void*)m68k_op_subq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_svs_8_d , + (void*)m68k_op_svs_8_d , + (void*)m68k_op_svs_8_d , + (void*)m68k_op_svs_8_d , + (void*)m68k_op_svs_8_d , + (void*)m68k_op_svs_8_d , + (void*)m68k_op_svs_8_d , + (void*)m68k_op_svs_8_d , + (void*)m68k_op_dbvs_16 , + (void*)m68k_op_dbvs_16 , + (void*)m68k_op_dbvs_16 , + (void*)m68k_op_dbvs_16 , + (void*)m68k_op_dbvs_16 , + (void*)m68k_op_dbvs_16 , + (void*)m68k_op_dbvs_16 , + (void*)m68k_op_dbvs_16 , + (void*)m68k_op_svs_8_ai , + (void*)m68k_op_svs_8_ai , + (void*)m68k_op_svs_8_ai , + (void*)m68k_op_svs_8_ai , + (void*)m68k_op_svs_8_ai , + (void*)m68k_op_svs_8_ai , + (void*)m68k_op_svs_8_ai , + (void*)m68k_op_svs_8_ai , + (void*)m68k_op_svs_8_pi , + (void*)m68k_op_svs_8_pi , + (void*)m68k_op_svs_8_pi , + (void*)m68k_op_svs_8_pi , + (void*)m68k_op_svs_8_pi , + (void*)m68k_op_svs_8_pi , + (void*)m68k_op_svs_8_pi , + (void*)m68k_op_svs_8_pi7 , + (void*)m68k_op_svs_8_pd , + (void*)m68k_op_svs_8_pd , + (void*)m68k_op_svs_8_pd , + (void*)m68k_op_svs_8_pd , + (void*)m68k_op_svs_8_pd , + (void*)m68k_op_svs_8_pd , + (void*)m68k_op_svs_8_pd , + (void*)m68k_op_svs_8_pd7 , + (void*)m68k_op_svs_8_di , + (void*)m68k_op_svs_8_di , + (void*)m68k_op_svs_8_di , + (void*)m68k_op_svs_8_di , + (void*)m68k_op_svs_8_di , + (void*)m68k_op_svs_8_di , + (void*)m68k_op_svs_8_di , + (void*)m68k_op_svs_8_di , + (void*)m68k_op_svs_8_ix , + (void*)m68k_op_svs_8_ix , + (void*)m68k_op_svs_8_ix , + (void*)m68k_op_svs_8_ix , + (void*)m68k_op_svs_8_ix , + (void*)m68k_op_svs_8_ix , + (void*)m68k_op_svs_8_ix , + (void*)m68k_op_svs_8_ix , + (void*)m68k_op_svs_8_aw , + (void*)m68k_op_svs_8_al , + (void*)m68k_op_trapvs_16 , + (void*)m68k_op_trapvs_32 , + (void*)m68k_op_trapvs , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi7 , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd7 , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_aw , + (void*)m68k_op_addq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_aw , + (void*)m68k_op_addq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_aw , + (void*)m68k_op_addq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_spl_8_d , + (void*)m68k_op_spl_8_d , + (void*)m68k_op_spl_8_d , + (void*)m68k_op_spl_8_d , + (void*)m68k_op_spl_8_d , + (void*)m68k_op_spl_8_d , + (void*)m68k_op_spl_8_d , + (void*)m68k_op_spl_8_d , + (void*)m68k_op_dbpl_16 , + (void*)m68k_op_dbpl_16 , + (void*)m68k_op_dbpl_16 , + (void*)m68k_op_dbpl_16 , + (void*)m68k_op_dbpl_16 , + (void*)m68k_op_dbpl_16 , + (void*)m68k_op_dbpl_16 , + (void*)m68k_op_dbpl_16 , + (void*)m68k_op_spl_8_ai , + (void*)m68k_op_spl_8_ai , + (void*)m68k_op_spl_8_ai , + (void*)m68k_op_spl_8_ai , + (void*)m68k_op_spl_8_ai , + (void*)m68k_op_spl_8_ai , + (void*)m68k_op_spl_8_ai , + (void*)m68k_op_spl_8_ai , + (void*)m68k_op_spl_8_pi , + (void*)m68k_op_spl_8_pi , + (void*)m68k_op_spl_8_pi , + (void*)m68k_op_spl_8_pi , + (void*)m68k_op_spl_8_pi , + (void*)m68k_op_spl_8_pi , + (void*)m68k_op_spl_8_pi , + (void*)m68k_op_spl_8_pi7 , + (void*)m68k_op_spl_8_pd , + (void*)m68k_op_spl_8_pd , + (void*)m68k_op_spl_8_pd , + (void*)m68k_op_spl_8_pd , + (void*)m68k_op_spl_8_pd , + (void*)m68k_op_spl_8_pd , + (void*)m68k_op_spl_8_pd , + (void*)m68k_op_spl_8_pd7 , + (void*)m68k_op_spl_8_di , + (void*)m68k_op_spl_8_di , + (void*)m68k_op_spl_8_di , + (void*)m68k_op_spl_8_di , + (void*)m68k_op_spl_8_di , + (void*)m68k_op_spl_8_di , + (void*)m68k_op_spl_8_di , + (void*)m68k_op_spl_8_di , + (void*)m68k_op_spl_8_ix , + (void*)m68k_op_spl_8_ix , + (void*)m68k_op_spl_8_ix , + (void*)m68k_op_spl_8_ix , + (void*)m68k_op_spl_8_ix , + (void*)m68k_op_spl_8_ix , + (void*)m68k_op_spl_8_ix , + (void*)m68k_op_spl_8_ix , + (void*)m68k_op_spl_8_aw , + (void*)m68k_op_spl_8_al , + (void*)m68k_op_trappl_16 , + (void*)m68k_op_trappl_32 , + (void*)m68k_op_trappl , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi7 , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd7 , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_aw , + (void*)m68k_op_subq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_aw , + (void*)m68k_op_subq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_aw , + (void*)m68k_op_subq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_smi_8_d , + (void*)m68k_op_smi_8_d , + (void*)m68k_op_smi_8_d , + (void*)m68k_op_smi_8_d , + (void*)m68k_op_smi_8_d , + (void*)m68k_op_smi_8_d , + (void*)m68k_op_smi_8_d , + (void*)m68k_op_smi_8_d , + (void*)m68k_op_dbmi_16 , + (void*)m68k_op_dbmi_16 , + (void*)m68k_op_dbmi_16 , + (void*)m68k_op_dbmi_16 , + (void*)m68k_op_dbmi_16 , + (void*)m68k_op_dbmi_16 , + (void*)m68k_op_dbmi_16 , + (void*)m68k_op_dbmi_16 , + (void*)m68k_op_smi_8_ai , + (void*)m68k_op_smi_8_ai , + (void*)m68k_op_smi_8_ai , + (void*)m68k_op_smi_8_ai , + (void*)m68k_op_smi_8_ai , + (void*)m68k_op_smi_8_ai , + (void*)m68k_op_smi_8_ai , + (void*)m68k_op_smi_8_ai , + (void*)m68k_op_smi_8_pi , + (void*)m68k_op_smi_8_pi , + (void*)m68k_op_smi_8_pi , + (void*)m68k_op_smi_8_pi , + (void*)m68k_op_smi_8_pi , + (void*)m68k_op_smi_8_pi , + (void*)m68k_op_smi_8_pi , + (void*)m68k_op_smi_8_pi7 , + (void*)m68k_op_smi_8_pd , + (void*)m68k_op_smi_8_pd , + (void*)m68k_op_smi_8_pd , + (void*)m68k_op_smi_8_pd , + (void*)m68k_op_smi_8_pd , + (void*)m68k_op_smi_8_pd , + (void*)m68k_op_smi_8_pd , + (void*)m68k_op_smi_8_pd7 , + (void*)m68k_op_smi_8_di , + (void*)m68k_op_smi_8_di , + (void*)m68k_op_smi_8_di , + (void*)m68k_op_smi_8_di , + (void*)m68k_op_smi_8_di , + (void*)m68k_op_smi_8_di , + (void*)m68k_op_smi_8_di , + (void*)m68k_op_smi_8_di , + (void*)m68k_op_smi_8_ix , + (void*)m68k_op_smi_8_ix , + (void*)m68k_op_smi_8_ix , + (void*)m68k_op_smi_8_ix , + (void*)m68k_op_smi_8_ix , + (void*)m68k_op_smi_8_ix , + (void*)m68k_op_smi_8_ix , + (void*)m68k_op_smi_8_ix , + (void*)m68k_op_smi_8_aw , + (void*)m68k_op_smi_8_al , + (void*)m68k_op_trapmi_16 , + (void*)m68k_op_trapmi_32 , + (void*)m68k_op_trapmi , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi7 , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd7 , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_aw , + (void*)m68k_op_addq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_aw , + (void*)m68k_op_addq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_aw , + (void*)m68k_op_addq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sge_8_d , + (void*)m68k_op_sge_8_d , + (void*)m68k_op_sge_8_d , + (void*)m68k_op_sge_8_d , + (void*)m68k_op_sge_8_d , + (void*)m68k_op_sge_8_d , + (void*)m68k_op_sge_8_d , + (void*)m68k_op_sge_8_d , + (void*)m68k_op_dbge_16 , + (void*)m68k_op_dbge_16 , + (void*)m68k_op_dbge_16 , + (void*)m68k_op_dbge_16 , + (void*)m68k_op_dbge_16 , + (void*)m68k_op_dbge_16 , + (void*)m68k_op_dbge_16 , + (void*)m68k_op_dbge_16 , + (void*)m68k_op_sge_8_ai , + (void*)m68k_op_sge_8_ai , + (void*)m68k_op_sge_8_ai , + (void*)m68k_op_sge_8_ai , + (void*)m68k_op_sge_8_ai , + (void*)m68k_op_sge_8_ai , + (void*)m68k_op_sge_8_ai , + (void*)m68k_op_sge_8_ai , + (void*)m68k_op_sge_8_pi , + (void*)m68k_op_sge_8_pi , + (void*)m68k_op_sge_8_pi , + (void*)m68k_op_sge_8_pi , + (void*)m68k_op_sge_8_pi , + (void*)m68k_op_sge_8_pi , + (void*)m68k_op_sge_8_pi , + (void*)m68k_op_sge_8_pi7 , + (void*)m68k_op_sge_8_pd , + (void*)m68k_op_sge_8_pd , + (void*)m68k_op_sge_8_pd , + (void*)m68k_op_sge_8_pd , + (void*)m68k_op_sge_8_pd , + (void*)m68k_op_sge_8_pd , + (void*)m68k_op_sge_8_pd , + (void*)m68k_op_sge_8_pd7 , + (void*)m68k_op_sge_8_di , + (void*)m68k_op_sge_8_di , + (void*)m68k_op_sge_8_di , + (void*)m68k_op_sge_8_di , + (void*)m68k_op_sge_8_di , + (void*)m68k_op_sge_8_di , + (void*)m68k_op_sge_8_di , + (void*)m68k_op_sge_8_di , + (void*)m68k_op_sge_8_ix , + (void*)m68k_op_sge_8_ix , + (void*)m68k_op_sge_8_ix , + (void*)m68k_op_sge_8_ix , + (void*)m68k_op_sge_8_ix , + (void*)m68k_op_sge_8_ix , + (void*)m68k_op_sge_8_ix , + (void*)m68k_op_sge_8_ix , + (void*)m68k_op_sge_8_aw , + (void*)m68k_op_sge_8_al , + (void*)m68k_op_trapge_16 , + (void*)m68k_op_trapge_32 , + (void*)m68k_op_trapge , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi7 , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd7 , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_aw , + (void*)m68k_op_subq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_aw , + (void*)m68k_op_subq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_aw , + (void*)m68k_op_subq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_slt_8_d , + (void*)m68k_op_slt_8_d , + (void*)m68k_op_slt_8_d , + (void*)m68k_op_slt_8_d , + (void*)m68k_op_slt_8_d , + (void*)m68k_op_slt_8_d , + (void*)m68k_op_slt_8_d , + (void*)m68k_op_slt_8_d , + (void*)m68k_op_dblt_16 , + (void*)m68k_op_dblt_16 , + (void*)m68k_op_dblt_16 , + (void*)m68k_op_dblt_16 , + (void*)m68k_op_dblt_16 , + (void*)m68k_op_dblt_16 , + (void*)m68k_op_dblt_16 , + (void*)m68k_op_dblt_16 , + (void*)m68k_op_slt_8_ai , + (void*)m68k_op_slt_8_ai , + (void*)m68k_op_slt_8_ai , + (void*)m68k_op_slt_8_ai , + (void*)m68k_op_slt_8_ai , + (void*)m68k_op_slt_8_ai , + (void*)m68k_op_slt_8_ai , + (void*)m68k_op_slt_8_ai , + (void*)m68k_op_slt_8_pi , + (void*)m68k_op_slt_8_pi , + (void*)m68k_op_slt_8_pi , + (void*)m68k_op_slt_8_pi , + (void*)m68k_op_slt_8_pi , + (void*)m68k_op_slt_8_pi , + (void*)m68k_op_slt_8_pi , + (void*)m68k_op_slt_8_pi7 , + (void*)m68k_op_slt_8_pd , + (void*)m68k_op_slt_8_pd , + (void*)m68k_op_slt_8_pd , + (void*)m68k_op_slt_8_pd , + (void*)m68k_op_slt_8_pd , + (void*)m68k_op_slt_8_pd , + (void*)m68k_op_slt_8_pd , + (void*)m68k_op_slt_8_pd7 , + (void*)m68k_op_slt_8_di , + (void*)m68k_op_slt_8_di , + (void*)m68k_op_slt_8_di , + (void*)m68k_op_slt_8_di , + (void*)m68k_op_slt_8_di , + (void*)m68k_op_slt_8_di , + (void*)m68k_op_slt_8_di , + (void*)m68k_op_slt_8_di , + (void*)m68k_op_slt_8_ix , + (void*)m68k_op_slt_8_ix , + (void*)m68k_op_slt_8_ix , + (void*)m68k_op_slt_8_ix , + (void*)m68k_op_slt_8_ix , + (void*)m68k_op_slt_8_ix , + (void*)m68k_op_slt_8_ix , + (void*)m68k_op_slt_8_ix , + (void*)m68k_op_slt_8_aw , + (void*)m68k_op_slt_8_al , + (void*)m68k_op_traplt_16 , + (void*)m68k_op_traplt_32 , + (void*)m68k_op_traplt , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_addq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_ai , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi , + (void*)m68k_op_addq_8_pi7 , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd , + (void*)m68k_op_addq_8_pd7 , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_di , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_ix , + (void*)m68k_op_addq_8_aw , + (void*)m68k_op_addq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_d , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_a , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_ai , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pi , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_pd , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_di , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_ix , + (void*)m68k_op_addq_16_aw , + (void*)m68k_op_addq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_d , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_a , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_ai , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pi , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_pd , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_di , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_ix , + (void*)m68k_op_addq_32_aw , + (void*)m68k_op_addq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sgt_8_d , + (void*)m68k_op_sgt_8_d , + (void*)m68k_op_sgt_8_d , + (void*)m68k_op_sgt_8_d , + (void*)m68k_op_sgt_8_d , + (void*)m68k_op_sgt_8_d , + (void*)m68k_op_sgt_8_d , + (void*)m68k_op_sgt_8_d , + (void*)m68k_op_dbgt_16 , + (void*)m68k_op_dbgt_16 , + (void*)m68k_op_dbgt_16 , + (void*)m68k_op_dbgt_16 , + (void*)m68k_op_dbgt_16 , + (void*)m68k_op_dbgt_16 , + (void*)m68k_op_dbgt_16 , + (void*)m68k_op_dbgt_16 , + (void*)m68k_op_sgt_8_ai , + (void*)m68k_op_sgt_8_ai , + (void*)m68k_op_sgt_8_ai , + (void*)m68k_op_sgt_8_ai , + (void*)m68k_op_sgt_8_ai , + (void*)m68k_op_sgt_8_ai , + (void*)m68k_op_sgt_8_ai , + (void*)m68k_op_sgt_8_ai , + (void*)m68k_op_sgt_8_pi , + (void*)m68k_op_sgt_8_pi , + (void*)m68k_op_sgt_8_pi , + (void*)m68k_op_sgt_8_pi , + (void*)m68k_op_sgt_8_pi , + (void*)m68k_op_sgt_8_pi , + (void*)m68k_op_sgt_8_pi , + (void*)m68k_op_sgt_8_pi7 , + (void*)m68k_op_sgt_8_pd , + (void*)m68k_op_sgt_8_pd , + (void*)m68k_op_sgt_8_pd , + (void*)m68k_op_sgt_8_pd , + (void*)m68k_op_sgt_8_pd , + (void*)m68k_op_sgt_8_pd , + (void*)m68k_op_sgt_8_pd , + (void*)m68k_op_sgt_8_pd7 , + (void*)m68k_op_sgt_8_di , + (void*)m68k_op_sgt_8_di , + (void*)m68k_op_sgt_8_di , + (void*)m68k_op_sgt_8_di , + (void*)m68k_op_sgt_8_di , + (void*)m68k_op_sgt_8_di , + (void*)m68k_op_sgt_8_di , + (void*)m68k_op_sgt_8_di , + (void*)m68k_op_sgt_8_ix , + (void*)m68k_op_sgt_8_ix , + (void*)m68k_op_sgt_8_ix , + (void*)m68k_op_sgt_8_ix , + (void*)m68k_op_sgt_8_ix , + (void*)m68k_op_sgt_8_ix , + (void*)m68k_op_sgt_8_ix , + (void*)m68k_op_sgt_8_ix , + (void*)m68k_op_sgt_8_aw , + (void*)m68k_op_sgt_8_al , + (void*)m68k_op_trapgt_16 , + (void*)m68k_op_trapgt_32 , + (void*)m68k_op_trapgt , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_subq_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_ai , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi , + (void*)m68k_op_subq_8_pi7 , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd , + (void*)m68k_op_subq_8_pd7 , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_di , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_ix , + (void*)m68k_op_subq_8_aw , + (void*)m68k_op_subq_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_d , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_a , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_ai , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pi , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_pd , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_di , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_ix , + (void*)m68k_op_subq_16_aw , + (void*)m68k_op_subq_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_d , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_a , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_ai , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pi , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_pd , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_di , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_ix , + (void*)m68k_op_subq_32_aw , + (void*)m68k_op_subq_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sle_8_d , + (void*)m68k_op_sle_8_d , + (void*)m68k_op_sle_8_d , + (void*)m68k_op_sle_8_d , + (void*)m68k_op_sle_8_d , + (void*)m68k_op_sle_8_d , + (void*)m68k_op_sle_8_d , + (void*)m68k_op_sle_8_d , + (void*)m68k_op_dble_16 , + (void*)m68k_op_dble_16 , + (void*)m68k_op_dble_16 , + (void*)m68k_op_dble_16 , + (void*)m68k_op_dble_16 , + (void*)m68k_op_dble_16 , + (void*)m68k_op_dble_16 , + (void*)m68k_op_dble_16 , + (void*)m68k_op_sle_8_ai , + (void*)m68k_op_sle_8_ai , + (void*)m68k_op_sle_8_ai , + (void*)m68k_op_sle_8_ai , + (void*)m68k_op_sle_8_ai , + (void*)m68k_op_sle_8_ai , + (void*)m68k_op_sle_8_ai , + (void*)m68k_op_sle_8_ai , + (void*)m68k_op_sle_8_pi , + (void*)m68k_op_sle_8_pi , + (void*)m68k_op_sle_8_pi , + (void*)m68k_op_sle_8_pi , + (void*)m68k_op_sle_8_pi , + (void*)m68k_op_sle_8_pi , + (void*)m68k_op_sle_8_pi , + (void*)m68k_op_sle_8_pi7 , + (void*)m68k_op_sle_8_pd , + (void*)m68k_op_sle_8_pd , + (void*)m68k_op_sle_8_pd , + (void*)m68k_op_sle_8_pd , + (void*)m68k_op_sle_8_pd , + (void*)m68k_op_sle_8_pd , + (void*)m68k_op_sle_8_pd , + (void*)m68k_op_sle_8_pd7 , + (void*)m68k_op_sle_8_di , + (void*)m68k_op_sle_8_di , + (void*)m68k_op_sle_8_di , + (void*)m68k_op_sle_8_di , + (void*)m68k_op_sle_8_di , + (void*)m68k_op_sle_8_di , + (void*)m68k_op_sle_8_di , + (void*)m68k_op_sle_8_di , + (void*)m68k_op_sle_8_ix , + (void*)m68k_op_sle_8_ix , + (void*)m68k_op_sle_8_ix , + (void*)m68k_op_sle_8_ix , + (void*)m68k_op_sle_8_ix , + (void*)m68k_op_sle_8_ix , + (void*)m68k_op_sle_8_ix , + (void*)m68k_op_sle_8_ix , + (void*)m68k_op_sle_8_aw , + (void*)m68k_op_sle_8_al , + (void*)m68k_op_traple_16 , + (void*)m68k_op_traple_32 , + (void*)m68k_op_traple , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bra_16 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + 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(void*)m68k_op_bra_8 , + (void*)m68k_op_bra_8 , + (void*)m68k_op_bra_32 , + (void*)m68k_op_bsr_16 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , 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+ (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , + (void*)m68k_op_bsr_8 , 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(void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + (void*)m68k_op_bls_8 , + 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+ (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_8 , + (void*)m68k_op_beq_32 , + (void*)m68k_op_bvc_16 , + (void*)m68k_op_bvc_8 , + (void*)m68k_op_bvc_8 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(void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_8 , + (void*)m68k_op_bvs_32 , + (void*)m68k_op_bpl_16 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_8 , + (void*)m68k_op_bpl_32 , + (void*)m68k_op_bmi_16 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_8 , + (void*)m68k_op_bmi_32 , + (void*)m68k_op_bge_16 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_8 , + (void*)m68k_op_bge_32 , + (void*)m68k_op_blt_16 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_8 , + (void*)m68k_op_blt_32 , + (void*)m68k_op_bgt_16 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_8 , + (void*)m68k_op_bgt_32 , + (void*)m68k_op_ble_16 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + (void*)m68k_op_ble_8 , + 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(void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi7 , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd7 , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_aw , + (void*)m68k_op_or_8_er_al , + (void*)m68k_op_or_8_er_pcdi , + (void*)m68k_op_or_8_er_pcix , + (void*)m68k_op_or_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_aw , + (void*)m68k_op_or_16_er_al , + (void*)m68k_op_or_16_er_pcdi , + (void*)m68k_op_or_16_er_pcix , + (void*)m68k_op_or_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_aw , + (void*)m68k_op_or_32_er_al , + (void*)m68k_op_or_32_er_pcdi , + (void*)m68k_op_or_32_er_pcix , + (void*)m68k_op_or_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_aw , + (void*)m68k_op_divu_16_al , + (void*)m68k_op_divu_16_pcdi , + (void*)m68k_op_divu_16_pcix , + (void*)m68k_op_divu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm_ay7 , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi7 , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd7 , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_aw , + (void*)m68k_op_or_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm_ay7 , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_aw , + (void*)m68k_op_or_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm_ay7 , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_aw , + (void*)m68k_op_or_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_aw , + (void*)m68k_op_divs_16_al , + (void*)m68k_op_divs_16_pcdi , + (void*)m68k_op_divs_16_pcix , + (void*)m68k_op_divs_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi7 , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd7 , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_aw , + (void*)m68k_op_or_8_er_al , + (void*)m68k_op_or_8_er_pcdi , + (void*)m68k_op_or_8_er_pcix , + (void*)m68k_op_or_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_aw , + (void*)m68k_op_or_16_er_al , + (void*)m68k_op_or_16_er_pcdi , + (void*)m68k_op_or_16_er_pcix , + (void*)m68k_op_or_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_aw , + (void*)m68k_op_or_32_er_al , + (void*)m68k_op_or_32_er_pcdi , + (void*)m68k_op_or_32_er_pcix , + (void*)m68k_op_or_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_aw , + (void*)m68k_op_divu_16_al , + (void*)m68k_op_divu_16_pcdi , + (void*)m68k_op_divu_16_pcix , + (void*)m68k_op_divu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm_ay7 , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi7 , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd7 , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_aw , + (void*)m68k_op_or_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm_ay7 , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_aw , + (void*)m68k_op_or_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm_ay7 , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_aw , + (void*)m68k_op_or_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_aw , + (void*)m68k_op_divs_16_al , + (void*)m68k_op_divs_16_pcdi , + (void*)m68k_op_divs_16_pcix , + (void*)m68k_op_divs_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi7 , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd7 , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_aw , + (void*)m68k_op_or_8_er_al , + (void*)m68k_op_or_8_er_pcdi , + (void*)m68k_op_or_8_er_pcix , + (void*)m68k_op_or_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_aw , + (void*)m68k_op_or_16_er_al , + (void*)m68k_op_or_16_er_pcdi , + (void*)m68k_op_or_16_er_pcix , + (void*)m68k_op_or_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_aw , + (void*)m68k_op_or_32_er_al , + (void*)m68k_op_or_32_er_pcdi , + (void*)m68k_op_or_32_er_pcix , + (void*)m68k_op_or_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_aw , + (void*)m68k_op_divu_16_al , + (void*)m68k_op_divu_16_pcdi , + (void*)m68k_op_divu_16_pcix , + (void*)m68k_op_divu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm_ay7 , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi7 , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd7 , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_aw , + (void*)m68k_op_or_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm_ay7 , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_aw , + (void*)m68k_op_or_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm_ay7 , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_aw , + (void*)m68k_op_or_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_aw , + (void*)m68k_op_divs_16_al , + (void*)m68k_op_divs_16_pcdi , + (void*)m68k_op_divs_16_pcix , + (void*)m68k_op_divs_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi7 , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd7 , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_aw , + (void*)m68k_op_or_8_er_al , + (void*)m68k_op_or_8_er_pcdi , + (void*)m68k_op_or_8_er_pcix , + (void*)m68k_op_or_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_aw , + (void*)m68k_op_or_16_er_al , + (void*)m68k_op_or_16_er_pcdi , + (void*)m68k_op_or_16_er_pcix , + (void*)m68k_op_or_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_aw , + (void*)m68k_op_or_32_er_al , + (void*)m68k_op_or_32_er_pcdi , + (void*)m68k_op_or_32_er_pcix , + (void*)m68k_op_or_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_aw , + (void*)m68k_op_divu_16_al , + (void*)m68k_op_divu_16_pcdi , + (void*)m68k_op_divu_16_pcix , + (void*)m68k_op_divu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm_ay7 , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi7 , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd7 , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_aw , + (void*)m68k_op_or_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm_ay7 , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_aw , + (void*)m68k_op_or_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm_ay7 , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_aw , + (void*)m68k_op_or_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_aw , + (void*)m68k_op_divs_16_al , + (void*)m68k_op_divs_16_pcdi , + (void*)m68k_op_divs_16_pcix , + (void*)m68k_op_divs_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi7 , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd7 , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_aw , + (void*)m68k_op_or_8_er_al , + (void*)m68k_op_or_8_er_pcdi , + (void*)m68k_op_or_8_er_pcix , + (void*)m68k_op_or_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_aw , + (void*)m68k_op_or_16_er_al , + (void*)m68k_op_or_16_er_pcdi , + (void*)m68k_op_or_16_er_pcix , + (void*)m68k_op_or_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_aw , + (void*)m68k_op_or_32_er_al , + (void*)m68k_op_or_32_er_pcdi , + (void*)m68k_op_or_32_er_pcix , + (void*)m68k_op_or_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_aw , + (void*)m68k_op_divu_16_al , + (void*)m68k_op_divu_16_pcdi , + (void*)m68k_op_divu_16_pcix , + (void*)m68k_op_divu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm_ay7 , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi7 , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd7 , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_aw , + (void*)m68k_op_or_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm_ay7 , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_aw , + (void*)m68k_op_or_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm_ay7 , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_aw , + (void*)m68k_op_or_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_aw , + (void*)m68k_op_divs_16_al , + (void*)m68k_op_divs_16_pcdi , + (void*)m68k_op_divs_16_pcix , + (void*)m68k_op_divs_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi7 , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd7 , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_aw , + (void*)m68k_op_or_8_er_al , + (void*)m68k_op_or_8_er_pcdi , + (void*)m68k_op_or_8_er_pcix , + (void*)m68k_op_or_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_aw , + (void*)m68k_op_or_16_er_al , + (void*)m68k_op_or_16_er_pcdi , + (void*)m68k_op_or_16_er_pcix , + (void*)m68k_op_or_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_aw , + (void*)m68k_op_or_32_er_al , + (void*)m68k_op_or_32_er_pcdi , + (void*)m68k_op_or_32_er_pcix , + (void*)m68k_op_or_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_aw , + (void*)m68k_op_divu_16_al , + (void*)m68k_op_divu_16_pcdi , + (void*)m68k_op_divu_16_pcix , + (void*)m68k_op_divu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm_ay7 , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi7 , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd7 , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_aw , + (void*)m68k_op_or_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm_ay7 , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_aw , + (void*)m68k_op_or_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm_ay7 , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_aw , + (void*)m68k_op_or_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_aw , + (void*)m68k_op_divs_16_al , + (void*)m68k_op_divs_16_pcdi , + (void*)m68k_op_divs_16_pcix , + (void*)m68k_op_divs_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi7 , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd7 , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_aw , + (void*)m68k_op_or_8_er_al , + (void*)m68k_op_or_8_er_pcdi , + (void*)m68k_op_or_8_er_pcix , + (void*)m68k_op_or_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_aw , + (void*)m68k_op_or_16_er_al , + (void*)m68k_op_or_16_er_pcdi , + (void*)m68k_op_or_16_er_pcix , + (void*)m68k_op_or_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_aw , + (void*)m68k_op_or_32_er_al , + (void*)m68k_op_or_32_er_pcdi , + (void*)m68k_op_or_32_er_pcix , + (void*)m68k_op_or_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_aw , + (void*)m68k_op_divu_16_al , + (void*)m68k_op_divu_16_pcdi , + (void*)m68k_op_divu_16_pcix , + (void*)m68k_op_divu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm , + (void*)m68k_op_sbcd_8_mm_ay7 , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi7 , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd7 , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_aw , + (void*)m68k_op_or_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm , + (void*)m68k_op_pack_16_mm_ay7 , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_aw , + (void*)m68k_op_or_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm , + (void*)m68k_op_unpk_16_mm_ay7 , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_aw , + (void*)m68k_op_or_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_aw , + (void*)m68k_op_divs_16_al , + (void*)m68k_op_divs_16_pcdi , + (void*)m68k_op_divs_16_pcix , + (void*)m68k_op_divs_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_or_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_ai , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi , + (void*)m68k_op_or_8_er_pi7 , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd , + (void*)m68k_op_or_8_er_pd7 , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_di , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_ix , + (void*)m68k_op_or_8_er_aw , + (void*)m68k_op_or_8_er_al , + (void*)m68k_op_or_8_er_pcdi , + (void*)m68k_op_or_8_er_pcix , + (void*)m68k_op_or_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_or_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_ai , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pi , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_pd , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_di , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_ix , + (void*)m68k_op_or_16_er_aw , + (void*)m68k_op_or_16_er_al , + (void*)m68k_op_or_16_er_pcdi , + (void*)m68k_op_or_16_er_pcix , + (void*)m68k_op_or_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_or_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_ai , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pi , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_pd , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_di , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_ix , + (void*)m68k_op_or_32_er_aw , + (void*)m68k_op_or_32_er_al , + (void*)m68k_op_or_32_er_pcdi , + (void*)m68k_op_or_32_er_pcix , + (void*)m68k_op_or_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_divu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_ai , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pi , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_pd , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_di , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_ix , + (void*)m68k_op_divu_16_aw , + (void*)m68k_op_divu_16_al , + (void*)m68k_op_divu_16_pcdi , + (void*)m68k_op_divu_16_pcix , + (void*)m68k_op_divu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_rr , + (void*)m68k_op_sbcd_8_mm_ax7 , + (void*)m68k_op_sbcd_8_mm_ax7 , + (void*)m68k_op_sbcd_8_mm_ax7 , + (void*)m68k_op_sbcd_8_mm_ax7 , + (void*)m68k_op_sbcd_8_mm_ax7 , + (void*)m68k_op_sbcd_8_mm_ax7 , + (void*)m68k_op_sbcd_8_mm_ax7 , + (void*)m68k_op_sbcd_8_mm_axy7 , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_ai , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi , + (void*)m68k_op_or_8_re_pi7 , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd , + (void*)m68k_op_or_8_re_pd7 , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_di , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_ix , + (void*)m68k_op_or_8_re_aw , + (void*)m68k_op_or_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_rr , + (void*)m68k_op_pack_16_mm_ax7 , + (void*)m68k_op_pack_16_mm_ax7 , + (void*)m68k_op_pack_16_mm_ax7 , + (void*)m68k_op_pack_16_mm_ax7 , + (void*)m68k_op_pack_16_mm_ax7 , + (void*)m68k_op_pack_16_mm_ax7 , + (void*)m68k_op_pack_16_mm_ax7 , + (void*)m68k_op_pack_16_mm_axy7 , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_ai , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pi , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_pd , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_di , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_ix , + (void*)m68k_op_or_16_re_aw , + (void*)m68k_op_or_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_rr , + (void*)m68k_op_unpk_16_mm_ax7 , + (void*)m68k_op_unpk_16_mm_ax7 , + (void*)m68k_op_unpk_16_mm_ax7 , + (void*)m68k_op_unpk_16_mm_ax7 , + (void*)m68k_op_unpk_16_mm_ax7 , + (void*)m68k_op_unpk_16_mm_ax7 , + (void*)m68k_op_unpk_16_mm_ax7 , + (void*)m68k_op_unpk_16_mm_axy7 , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_ai , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pi , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_pd , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_di , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_ix , + (void*)m68k_op_or_32_re_aw , + (void*)m68k_op_or_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_divs_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_ai , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pi , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_pd , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_di , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_ix , + (void*)m68k_op_divs_16_aw , + (void*)m68k_op_divs_16_al , + (void*)m68k_op_divs_16_pcdi , + (void*)m68k_op_divs_16_pcix , + (void*)m68k_op_divs_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi7 , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd7 , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_aw , + (void*)m68k_op_sub_8_er_al , + (void*)m68k_op_sub_8_er_pcdi , + (void*)m68k_op_sub_8_er_pcix , + (void*)m68k_op_sub_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_aw , + (void*)m68k_op_sub_16_er_al , + (void*)m68k_op_sub_16_er_pcdi , + (void*)m68k_op_sub_16_er_pcix , + (void*)m68k_op_sub_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_aw , + (void*)m68k_op_sub_32_er_al , + (void*)m68k_op_sub_32_er_pcdi , + (void*)m68k_op_sub_32_er_pcix , + (void*)m68k_op_sub_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_aw , + (void*)m68k_op_suba_16_al , + (void*)m68k_op_suba_16_pcdi , + (void*)m68k_op_suba_16_pcix , + (void*)m68k_op_suba_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm_ay7 , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi7 , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd7 , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_aw , + (void*)m68k_op_sub_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_aw , + (void*)m68k_op_sub_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_aw , + (void*)m68k_op_sub_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_aw , + (void*)m68k_op_suba_32_al , + (void*)m68k_op_suba_32_pcdi , + (void*)m68k_op_suba_32_pcix , + (void*)m68k_op_suba_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi7 , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd7 , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_aw , + (void*)m68k_op_sub_8_er_al , + (void*)m68k_op_sub_8_er_pcdi , + (void*)m68k_op_sub_8_er_pcix , + (void*)m68k_op_sub_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_aw , + (void*)m68k_op_sub_16_er_al , + (void*)m68k_op_sub_16_er_pcdi , + (void*)m68k_op_sub_16_er_pcix , + (void*)m68k_op_sub_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_aw , + (void*)m68k_op_sub_32_er_al , + (void*)m68k_op_sub_32_er_pcdi , + (void*)m68k_op_sub_32_er_pcix , + (void*)m68k_op_sub_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_aw , + (void*)m68k_op_suba_16_al , + (void*)m68k_op_suba_16_pcdi , + (void*)m68k_op_suba_16_pcix , + (void*)m68k_op_suba_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm_ay7 , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi7 , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd7 , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_aw , + (void*)m68k_op_sub_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_aw , + (void*)m68k_op_sub_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_aw , + (void*)m68k_op_sub_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_aw , + (void*)m68k_op_suba_32_al , + (void*)m68k_op_suba_32_pcdi , + (void*)m68k_op_suba_32_pcix , + (void*)m68k_op_suba_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi7 , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd7 , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_aw , + (void*)m68k_op_sub_8_er_al , + (void*)m68k_op_sub_8_er_pcdi , + (void*)m68k_op_sub_8_er_pcix , + (void*)m68k_op_sub_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_aw , + (void*)m68k_op_sub_16_er_al , + (void*)m68k_op_sub_16_er_pcdi , + (void*)m68k_op_sub_16_er_pcix , + (void*)m68k_op_sub_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_aw , + (void*)m68k_op_sub_32_er_al , + (void*)m68k_op_sub_32_er_pcdi , + (void*)m68k_op_sub_32_er_pcix , + (void*)m68k_op_sub_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_aw , + (void*)m68k_op_suba_16_al , + (void*)m68k_op_suba_16_pcdi , + (void*)m68k_op_suba_16_pcix , + (void*)m68k_op_suba_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm_ay7 , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi7 , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd7 , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_aw , + (void*)m68k_op_sub_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_aw , + (void*)m68k_op_sub_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_aw , + (void*)m68k_op_sub_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_aw , + (void*)m68k_op_suba_32_al , + (void*)m68k_op_suba_32_pcdi , + (void*)m68k_op_suba_32_pcix , + (void*)m68k_op_suba_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi7 , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd7 , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_aw , + (void*)m68k_op_sub_8_er_al , + (void*)m68k_op_sub_8_er_pcdi , + (void*)m68k_op_sub_8_er_pcix , + (void*)m68k_op_sub_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_aw , + (void*)m68k_op_sub_16_er_al , + (void*)m68k_op_sub_16_er_pcdi , + (void*)m68k_op_sub_16_er_pcix , + (void*)m68k_op_sub_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_aw , + (void*)m68k_op_sub_32_er_al , + (void*)m68k_op_sub_32_er_pcdi , + (void*)m68k_op_sub_32_er_pcix , + (void*)m68k_op_sub_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_aw , + (void*)m68k_op_suba_16_al , + (void*)m68k_op_suba_16_pcdi , + (void*)m68k_op_suba_16_pcix , + (void*)m68k_op_suba_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm_ay7 , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi7 , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd7 , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_aw , + (void*)m68k_op_sub_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_aw , + (void*)m68k_op_sub_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_aw , + (void*)m68k_op_sub_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_aw , + (void*)m68k_op_suba_32_al , + (void*)m68k_op_suba_32_pcdi , + (void*)m68k_op_suba_32_pcix , + (void*)m68k_op_suba_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi7 , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd7 , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_aw , + (void*)m68k_op_sub_8_er_al , + (void*)m68k_op_sub_8_er_pcdi , + (void*)m68k_op_sub_8_er_pcix , + (void*)m68k_op_sub_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_aw , + (void*)m68k_op_sub_16_er_al , + (void*)m68k_op_sub_16_er_pcdi , + (void*)m68k_op_sub_16_er_pcix , + (void*)m68k_op_sub_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_aw , + (void*)m68k_op_sub_32_er_al , + (void*)m68k_op_sub_32_er_pcdi , + (void*)m68k_op_sub_32_er_pcix , + (void*)m68k_op_sub_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_aw , + (void*)m68k_op_suba_16_al , + (void*)m68k_op_suba_16_pcdi , + (void*)m68k_op_suba_16_pcix , + (void*)m68k_op_suba_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm_ay7 , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi7 , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd7 , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_aw , + (void*)m68k_op_sub_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_aw , + (void*)m68k_op_sub_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_aw , + (void*)m68k_op_sub_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_aw , + (void*)m68k_op_suba_32_al , + (void*)m68k_op_suba_32_pcdi , + (void*)m68k_op_suba_32_pcix , + (void*)m68k_op_suba_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi7 , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd7 , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_aw , + (void*)m68k_op_sub_8_er_al , + (void*)m68k_op_sub_8_er_pcdi , + (void*)m68k_op_sub_8_er_pcix , + (void*)m68k_op_sub_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_aw , + (void*)m68k_op_sub_16_er_al , + (void*)m68k_op_sub_16_er_pcdi , + (void*)m68k_op_sub_16_er_pcix , + (void*)m68k_op_sub_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_aw , + (void*)m68k_op_sub_32_er_al , + (void*)m68k_op_sub_32_er_pcdi , + (void*)m68k_op_sub_32_er_pcix , + (void*)m68k_op_sub_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_aw , + (void*)m68k_op_suba_16_al , + (void*)m68k_op_suba_16_pcdi , + (void*)m68k_op_suba_16_pcix , + (void*)m68k_op_suba_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm_ay7 , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi7 , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd7 , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_aw , + (void*)m68k_op_sub_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_aw , + (void*)m68k_op_sub_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_aw , + (void*)m68k_op_sub_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_aw , + (void*)m68k_op_suba_32_al , + (void*)m68k_op_suba_32_pcdi , + (void*)m68k_op_suba_32_pcix , + (void*)m68k_op_suba_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi7 , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd7 , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_aw , + (void*)m68k_op_sub_8_er_al , + (void*)m68k_op_sub_8_er_pcdi , + (void*)m68k_op_sub_8_er_pcix , + (void*)m68k_op_sub_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_aw , + (void*)m68k_op_sub_16_er_al , + (void*)m68k_op_sub_16_er_pcdi , + (void*)m68k_op_sub_16_er_pcix , + (void*)m68k_op_sub_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_aw , + (void*)m68k_op_sub_32_er_al , + (void*)m68k_op_sub_32_er_pcdi , + (void*)m68k_op_sub_32_er_pcix , + (void*)m68k_op_sub_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_aw , + (void*)m68k_op_suba_16_al , + (void*)m68k_op_suba_16_pcdi , + (void*)m68k_op_suba_16_pcix , + (void*)m68k_op_suba_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm , + (void*)m68k_op_subx_8_mm_ay7 , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi7 , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd7 , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_aw , + (void*)m68k_op_sub_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_aw , + (void*)m68k_op_sub_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_aw , + (void*)m68k_op_sub_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_aw , + (void*)m68k_op_suba_32_al , + (void*)m68k_op_suba_32_pcdi , + (void*)m68k_op_suba_32_pcix , + (void*)m68k_op_suba_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_sub_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_ai , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi , + (void*)m68k_op_sub_8_er_pi7 , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd , + (void*)m68k_op_sub_8_er_pd7 , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_di , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_ix , + (void*)m68k_op_sub_8_er_aw , + (void*)m68k_op_sub_8_er_al , + (void*)m68k_op_sub_8_er_pcdi , + (void*)m68k_op_sub_8_er_pcix , + (void*)m68k_op_sub_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_d , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_a , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_ai , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pi , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_pd , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_di , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_ix , + (void*)m68k_op_sub_16_er_aw , + (void*)m68k_op_sub_16_er_al , + (void*)m68k_op_sub_16_er_pcdi , + (void*)m68k_op_sub_16_er_pcix , + (void*)m68k_op_sub_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_d , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_a , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_ai , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pi , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_pd , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_di , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_ix , + (void*)m68k_op_sub_32_er_aw , + (void*)m68k_op_sub_32_er_al , + (void*)m68k_op_sub_32_er_pcdi , + (void*)m68k_op_sub_32_er_pcix , + (void*)m68k_op_sub_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_d , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_a , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_ai , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pi , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_pd , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_di , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_ix , + (void*)m68k_op_suba_16_aw , + (void*)m68k_op_suba_16_al , + (void*)m68k_op_suba_16_pcdi , + (void*)m68k_op_suba_16_pcix , + (void*)m68k_op_suba_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_rr , + (void*)m68k_op_subx_8_mm_ax7 , + (void*)m68k_op_subx_8_mm_ax7 , + (void*)m68k_op_subx_8_mm_ax7 , + (void*)m68k_op_subx_8_mm_ax7 , + (void*)m68k_op_subx_8_mm_ax7 , + (void*)m68k_op_subx_8_mm_ax7 , + (void*)m68k_op_subx_8_mm_ax7 , + (void*)m68k_op_subx_8_mm_axy7 , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_ai , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi , + (void*)m68k_op_sub_8_re_pi7 , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd , + (void*)m68k_op_sub_8_re_pd7 , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_di , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_ix , + (void*)m68k_op_sub_8_re_aw , + (void*)m68k_op_sub_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_rr , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_subx_16_mm , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_ai , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pi , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_pd , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_di , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_ix , + (void*)m68k_op_sub_16_re_aw , + (void*)m68k_op_sub_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_rr , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_subx_32_mm , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_ai , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pi , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_pd , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_di , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_ix , + (void*)m68k_op_sub_32_re_aw , + (void*)m68k_op_sub_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_d , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_a , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_ai , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pi , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_pd , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_di , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_ix , + (void*)m68k_op_suba_32_aw , + (void*)m68k_op_suba_32_al , + (void*)m68k_op_suba_32_pcdi , + (void*)m68k_op_suba_32_pcix , + (void*)m68k_op_suba_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + (void*)m68k_op_1010 , + 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+ (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_aw , + (void*)m68k_op_cmp_32_al , + (void*)m68k_op_cmp_32_pcdi , + (void*)m68k_op_cmp_32_pcix , + (void*)m68k_op_cmp_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_aw , + (void*)m68k_op_cmpa_16_al , + (void*)m68k_op_cmpa_16_pcdi , + (void*)m68k_op_cmpa_16_pcix , + (void*)m68k_op_cmpa_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8_ay7 , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi7 , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd7 , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_aw , + (void*)m68k_op_eor_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_aw , + (void*)m68k_op_eor_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_aw , + (void*)m68k_op_eor_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_aw , + (void*)m68k_op_cmpa_32_al , + (void*)m68k_op_cmpa_32_pcdi , + (void*)m68k_op_cmpa_32_pcix , + (void*)m68k_op_cmpa_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi7 , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd7 , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_aw , + (void*)m68k_op_cmp_8_al , + (void*)m68k_op_cmp_8_pcdi , + (void*)m68k_op_cmp_8_pcix , + (void*)m68k_op_cmp_8_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_aw , + (void*)m68k_op_cmp_16_al , + (void*)m68k_op_cmp_16_pcdi , + (void*)m68k_op_cmp_16_pcix , + (void*)m68k_op_cmp_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_aw , + (void*)m68k_op_cmp_32_al , + (void*)m68k_op_cmp_32_pcdi , + (void*)m68k_op_cmp_32_pcix , + (void*)m68k_op_cmp_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_aw , + (void*)m68k_op_cmpa_16_al , + (void*)m68k_op_cmpa_16_pcdi , + (void*)m68k_op_cmpa_16_pcix , + (void*)m68k_op_cmpa_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8_ay7 , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi7 , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd7 , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_aw , + (void*)m68k_op_eor_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_aw , + (void*)m68k_op_eor_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_aw , + (void*)m68k_op_eor_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_aw , + (void*)m68k_op_cmpa_32_al , + (void*)m68k_op_cmpa_32_pcdi , + (void*)m68k_op_cmpa_32_pcix , + (void*)m68k_op_cmpa_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi7 , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd7 , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_aw , + (void*)m68k_op_cmp_8_al , + (void*)m68k_op_cmp_8_pcdi , + (void*)m68k_op_cmp_8_pcix , + (void*)m68k_op_cmp_8_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_aw , + (void*)m68k_op_cmp_16_al , + (void*)m68k_op_cmp_16_pcdi , + (void*)m68k_op_cmp_16_pcix , + (void*)m68k_op_cmp_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_aw , + (void*)m68k_op_cmp_32_al , + (void*)m68k_op_cmp_32_pcdi , + (void*)m68k_op_cmp_32_pcix , + (void*)m68k_op_cmp_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_aw , + (void*)m68k_op_cmpa_16_al , + (void*)m68k_op_cmpa_16_pcdi , + (void*)m68k_op_cmpa_16_pcix , + (void*)m68k_op_cmpa_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8_ay7 , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi7 , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd7 , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_aw , + (void*)m68k_op_eor_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_aw , + (void*)m68k_op_eor_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_aw , + (void*)m68k_op_eor_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_aw , + (void*)m68k_op_cmpa_32_al , + (void*)m68k_op_cmpa_32_pcdi , + (void*)m68k_op_cmpa_32_pcix , + (void*)m68k_op_cmpa_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi7 , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd7 , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_aw , + (void*)m68k_op_cmp_8_al , + (void*)m68k_op_cmp_8_pcdi , + (void*)m68k_op_cmp_8_pcix , + (void*)m68k_op_cmp_8_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_aw , + (void*)m68k_op_cmp_16_al , + (void*)m68k_op_cmp_16_pcdi , + (void*)m68k_op_cmp_16_pcix , + (void*)m68k_op_cmp_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_aw , + (void*)m68k_op_cmp_32_al , + (void*)m68k_op_cmp_32_pcdi , + (void*)m68k_op_cmp_32_pcix , + (void*)m68k_op_cmp_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_aw , + (void*)m68k_op_cmpa_16_al , + (void*)m68k_op_cmpa_16_pcdi , + (void*)m68k_op_cmpa_16_pcix , + (void*)m68k_op_cmpa_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8_ay7 , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi7 , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd7 , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_aw , + (void*)m68k_op_eor_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_aw , + (void*)m68k_op_eor_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_aw , + (void*)m68k_op_eor_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_aw , + (void*)m68k_op_cmpa_32_al , + (void*)m68k_op_cmpa_32_pcdi , + (void*)m68k_op_cmpa_32_pcix , + (void*)m68k_op_cmpa_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi7 , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd7 , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_aw , + (void*)m68k_op_cmp_8_al , + (void*)m68k_op_cmp_8_pcdi , + (void*)m68k_op_cmp_8_pcix , + (void*)m68k_op_cmp_8_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_aw , + (void*)m68k_op_cmp_16_al , + (void*)m68k_op_cmp_16_pcdi , + (void*)m68k_op_cmp_16_pcix , + (void*)m68k_op_cmp_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_aw , + (void*)m68k_op_cmp_32_al , + (void*)m68k_op_cmp_32_pcdi , + (void*)m68k_op_cmp_32_pcix , + (void*)m68k_op_cmp_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_aw , + (void*)m68k_op_cmpa_16_al , + (void*)m68k_op_cmpa_16_pcdi , + (void*)m68k_op_cmpa_16_pcix , + (void*)m68k_op_cmpa_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8_ay7 , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi7 , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd7 , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_aw , + (void*)m68k_op_eor_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_aw , + (void*)m68k_op_eor_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_aw , + (void*)m68k_op_eor_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_aw , + (void*)m68k_op_cmpa_32_al , + (void*)m68k_op_cmpa_32_pcdi , + (void*)m68k_op_cmpa_32_pcix , + (void*)m68k_op_cmpa_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi7 , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd7 , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_aw , + (void*)m68k_op_cmp_8_al , + (void*)m68k_op_cmp_8_pcdi , + (void*)m68k_op_cmp_8_pcix , + (void*)m68k_op_cmp_8_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_aw , + (void*)m68k_op_cmp_16_al , + (void*)m68k_op_cmp_16_pcdi , + (void*)m68k_op_cmp_16_pcix , + (void*)m68k_op_cmp_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_aw , + (void*)m68k_op_cmp_32_al , + (void*)m68k_op_cmp_32_pcdi , + (void*)m68k_op_cmp_32_pcix , + (void*)m68k_op_cmp_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_aw , + (void*)m68k_op_cmpa_16_al , + (void*)m68k_op_cmpa_16_pcdi , + (void*)m68k_op_cmpa_16_pcix , + (void*)m68k_op_cmpa_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8_ay7 , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi7 , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd7 , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_aw , + (void*)m68k_op_eor_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_aw , + (void*)m68k_op_eor_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_aw , + (void*)m68k_op_eor_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_aw , + (void*)m68k_op_cmpa_32_al , + (void*)m68k_op_cmpa_32_pcdi , + (void*)m68k_op_cmpa_32_pcix , + (void*)m68k_op_cmpa_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi7 , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd7 , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_aw , + (void*)m68k_op_cmp_8_al , + (void*)m68k_op_cmp_8_pcdi , + (void*)m68k_op_cmp_8_pcix , + (void*)m68k_op_cmp_8_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_aw , + (void*)m68k_op_cmp_16_al , + (void*)m68k_op_cmp_16_pcdi , + (void*)m68k_op_cmp_16_pcix , + (void*)m68k_op_cmp_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_aw , + (void*)m68k_op_cmp_32_al , + (void*)m68k_op_cmp_32_pcdi , + (void*)m68k_op_cmp_32_pcix , + (void*)m68k_op_cmp_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_aw , + (void*)m68k_op_cmpa_16_al , + (void*)m68k_op_cmpa_16_pcdi , + (void*)m68k_op_cmpa_16_pcix , + (void*)m68k_op_cmpa_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8 , + (void*)m68k_op_cmpm_8_ay7 , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi7 , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd7 , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_aw , + (void*)m68k_op_eor_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_aw , + (void*)m68k_op_eor_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_aw , + (void*)m68k_op_eor_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_aw , + (void*)m68k_op_cmpa_32_al , + (void*)m68k_op_cmpa_32_pcdi , + (void*)m68k_op_cmpa_32_pcix , + (void*)m68k_op_cmpa_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_cmp_8_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_ai , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi , + (void*)m68k_op_cmp_8_pi7 , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd , + (void*)m68k_op_cmp_8_pd7 , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_di , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_ix , + (void*)m68k_op_cmp_8_aw , + (void*)m68k_op_cmp_8_al , + (void*)m68k_op_cmp_8_pcdi , + (void*)m68k_op_cmp_8_pcix , + (void*)m68k_op_cmp_8_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_d , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_a , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_ai , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pi , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_pd , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_di , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_ix , + (void*)m68k_op_cmp_16_aw , + (void*)m68k_op_cmp_16_al , + (void*)m68k_op_cmp_16_pcdi , + (void*)m68k_op_cmp_16_pcix , + (void*)m68k_op_cmp_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_d , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_a , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_ai , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pi , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_pd , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_di , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_ix , + (void*)m68k_op_cmp_32_aw , + (void*)m68k_op_cmp_32_al , + (void*)m68k_op_cmp_32_pcdi , + (void*)m68k_op_cmp_32_pcix , + (void*)m68k_op_cmp_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_d , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_a , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_ai , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pi , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_pd , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_di , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_ix , + (void*)m68k_op_cmpa_16_aw , + (void*)m68k_op_cmpa_16_al , + (void*)m68k_op_cmpa_16_pcdi , + (void*)m68k_op_cmpa_16_pcix , + (void*)m68k_op_cmpa_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_eor_8_d , + (void*)m68k_op_cmpm_8_ax7 , + (void*)m68k_op_cmpm_8_ax7 , + (void*)m68k_op_cmpm_8_ax7 , + (void*)m68k_op_cmpm_8_ax7 , + (void*)m68k_op_cmpm_8_ax7 , + (void*)m68k_op_cmpm_8_ax7 , + (void*)m68k_op_cmpm_8_ax7 , + (void*)m68k_op_cmpm_8_axy7 , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_ai , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi , + (void*)m68k_op_eor_8_pi7 , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd , + (void*)m68k_op_eor_8_pd7 , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_di , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_ix , + (void*)m68k_op_eor_8_aw , + (void*)m68k_op_eor_8_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_eor_16_d , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_cmpm_16 , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_ai , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pi , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_pd , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_di , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_ix , + (void*)m68k_op_eor_16_aw , + (void*)m68k_op_eor_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_eor_32_d , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_cmpm_32 , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_ai , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pi , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_pd , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_di , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_ix , + (void*)m68k_op_eor_32_aw , + (void*)m68k_op_eor_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_d , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_a , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_ai , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pi , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_pd , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_di , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_ix , + (void*)m68k_op_cmpa_32_aw , + (void*)m68k_op_cmpa_32_al , + (void*)m68k_op_cmpa_32_pcdi , + (void*)m68k_op_cmpa_32_pcix , + (void*)m68k_op_cmpa_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi7 , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd7 , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_aw , + (void*)m68k_op_and_8_er_al , + (void*)m68k_op_and_8_er_pcdi , + (void*)m68k_op_and_8_er_pcix , + (void*)m68k_op_and_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_aw , + (void*)m68k_op_and_16_er_al , + (void*)m68k_op_and_16_er_pcdi , + (void*)m68k_op_and_16_er_pcix , + (void*)m68k_op_and_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_aw , + (void*)m68k_op_and_32_er_al , + (void*)m68k_op_and_32_er_pcdi , + (void*)m68k_op_and_32_er_pcix , + (void*)m68k_op_and_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_aw , + (void*)m68k_op_mulu_16_al , + (void*)m68k_op_mulu_16_pcdi , + (void*)m68k_op_mulu_16_pcix , + (void*)m68k_op_mulu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm_ay7 , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi7 , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd7 , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_aw , + (void*)m68k_op_and_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_aw , + (void*)m68k_op_and_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_aw , + (void*)m68k_op_and_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_aw , + (void*)m68k_op_muls_16_al , + (void*)m68k_op_muls_16_pcdi , + (void*)m68k_op_muls_16_pcix , + (void*)m68k_op_muls_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi7 , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd7 , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_aw , + (void*)m68k_op_and_8_er_al , + (void*)m68k_op_and_8_er_pcdi , + (void*)m68k_op_and_8_er_pcix , + (void*)m68k_op_and_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_aw , + (void*)m68k_op_and_16_er_al , + (void*)m68k_op_and_16_er_pcdi , + (void*)m68k_op_and_16_er_pcix , + (void*)m68k_op_and_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_aw , + (void*)m68k_op_and_32_er_al , + (void*)m68k_op_and_32_er_pcdi , + (void*)m68k_op_and_32_er_pcix , + (void*)m68k_op_and_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_aw , + (void*)m68k_op_mulu_16_al , + (void*)m68k_op_mulu_16_pcdi , + (void*)m68k_op_mulu_16_pcix , + (void*)m68k_op_mulu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm_ay7 , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi7 , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd7 , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_aw , + (void*)m68k_op_and_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_aw , + (void*)m68k_op_and_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_aw , + (void*)m68k_op_and_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_aw , + (void*)m68k_op_muls_16_al , + (void*)m68k_op_muls_16_pcdi , + (void*)m68k_op_muls_16_pcix , + (void*)m68k_op_muls_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi7 , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd7 , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_aw , + (void*)m68k_op_and_8_er_al , + (void*)m68k_op_and_8_er_pcdi , + (void*)m68k_op_and_8_er_pcix , + (void*)m68k_op_and_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_aw , + (void*)m68k_op_and_16_er_al , + (void*)m68k_op_and_16_er_pcdi , + (void*)m68k_op_and_16_er_pcix , + (void*)m68k_op_and_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_aw , + (void*)m68k_op_and_32_er_al , + (void*)m68k_op_and_32_er_pcdi , + (void*)m68k_op_and_32_er_pcix , + (void*)m68k_op_and_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_aw , + (void*)m68k_op_mulu_16_al , + (void*)m68k_op_mulu_16_pcdi , + (void*)m68k_op_mulu_16_pcix , + (void*)m68k_op_mulu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm_ay7 , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi7 , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd7 , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_aw , + (void*)m68k_op_and_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_aw , + (void*)m68k_op_and_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_aw , + (void*)m68k_op_and_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_aw , + (void*)m68k_op_muls_16_al , + (void*)m68k_op_muls_16_pcdi , + (void*)m68k_op_muls_16_pcix , + (void*)m68k_op_muls_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi7 , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd7 , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_aw , + (void*)m68k_op_and_8_er_al , + (void*)m68k_op_and_8_er_pcdi , + (void*)m68k_op_and_8_er_pcix , + (void*)m68k_op_and_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_aw , + (void*)m68k_op_and_16_er_al , + (void*)m68k_op_and_16_er_pcdi , + (void*)m68k_op_and_16_er_pcix , + (void*)m68k_op_and_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_aw , + (void*)m68k_op_and_32_er_al , + (void*)m68k_op_and_32_er_pcdi , + (void*)m68k_op_and_32_er_pcix , + (void*)m68k_op_and_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_aw , + (void*)m68k_op_mulu_16_al , + (void*)m68k_op_mulu_16_pcdi , + (void*)m68k_op_mulu_16_pcix , + (void*)m68k_op_mulu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm_ay7 , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi7 , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd7 , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_aw , + (void*)m68k_op_and_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_aw , + (void*)m68k_op_and_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_aw , + (void*)m68k_op_and_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_aw , + (void*)m68k_op_muls_16_al , + (void*)m68k_op_muls_16_pcdi , + (void*)m68k_op_muls_16_pcix , + (void*)m68k_op_muls_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi7 , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd7 , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_aw , + (void*)m68k_op_and_8_er_al , + (void*)m68k_op_and_8_er_pcdi , + (void*)m68k_op_and_8_er_pcix , + (void*)m68k_op_and_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_aw , + (void*)m68k_op_and_16_er_al , + (void*)m68k_op_and_16_er_pcdi , + (void*)m68k_op_and_16_er_pcix , + (void*)m68k_op_and_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_aw , + (void*)m68k_op_and_32_er_al , + (void*)m68k_op_and_32_er_pcdi , + (void*)m68k_op_and_32_er_pcix , + (void*)m68k_op_and_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_aw , + (void*)m68k_op_mulu_16_al , + (void*)m68k_op_mulu_16_pcdi , + (void*)m68k_op_mulu_16_pcix , + (void*)m68k_op_mulu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm_ay7 , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi7 , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd7 , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_aw , + (void*)m68k_op_and_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_aw , + (void*)m68k_op_and_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_aw , + (void*)m68k_op_and_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_aw , + (void*)m68k_op_muls_16_al , + (void*)m68k_op_muls_16_pcdi , + (void*)m68k_op_muls_16_pcix , + (void*)m68k_op_muls_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi7 , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd7 , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_aw , + (void*)m68k_op_and_8_er_al , + (void*)m68k_op_and_8_er_pcdi , + (void*)m68k_op_and_8_er_pcix , + (void*)m68k_op_and_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_aw , + (void*)m68k_op_and_16_er_al , + (void*)m68k_op_and_16_er_pcdi , + (void*)m68k_op_and_16_er_pcix , + (void*)m68k_op_and_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_aw , + (void*)m68k_op_and_32_er_al , + (void*)m68k_op_and_32_er_pcdi , + (void*)m68k_op_and_32_er_pcix , + (void*)m68k_op_and_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_aw , + (void*)m68k_op_mulu_16_al , + (void*)m68k_op_mulu_16_pcdi , + (void*)m68k_op_mulu_16_pcix , + (void*)m68k_op_mulu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm_ay7 , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi7 , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd7 , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_aw , + (void*)m68k_op_and_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_aw , + (void*)m68k_op_and_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_aw , + (void*)m68k_op_and_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_aw , + (void*)m68k_op_muls_16_al , + (void*)m68k_op_muls_16_pcdi , + (void*)m68k_op_muls_16_pcix , + (void*)m68k_op_muls_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi7 , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd7 , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_aw , + (void*)m68k_op_and_8_er_al , + (void*)m68k_op_and_8_er_pcdi , + (void*)m68k_op_and_8_er_pcix , + (void*)m68k_op_and_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_aw , + (void*)m68k_op_and_16_er_al , + (void*)m68k_op_and_16_er_pcdi , + (void*)m68k_op_and_16_er_pcix , + (void*)m68k_op_and_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_aw , + (void*)m68k_op_and_32_er_al , + (void*)m68k_op_and_32_er_pcdi , + (void*)m68k_op_and_32_er_pcix , + (void*)m68k_op_and_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_aw , + (void*)m68k_op_mulu_16_al , + (void*)m68k_op_mulu_16_pcdi , + (void*)m68k_op_mulu_16_pcix , + (void*)m68k_op_mulu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm , + (void*)m68k_op_abcd_8_mm_ay7 , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi7 , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd7 , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_aw , + (void*)m68k_op_and_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_aw , + (void*)m68k_op_and_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_aw , + (void*)m68k_op_and_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_aw , + (void*)m68k_op_muls_16_al , + (void*)m68k_op_muls_16_pcdi , + (void*)m68k_op_muls_16_pcix , + (void*)m68k_op_muls_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_and_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_ai , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi , + (void*)m68k_op_and_8_er_pi7 , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd , + (void*)m68k_op_and_8_er_pd7 , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_di , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_ix , + (void*)m68k_op_and_8_er_aw , + (void*)m68k_op_and_8_er_al , + (void*)m68k_op_and_8_er_pcdi , + (void*)m68k_op_and_8_er_pcix , + (void*)m68k_op_and_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_and_16_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_ai , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pi , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_pd , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_di , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_ix , + (void*)m68k_op_and_16_er_aw , + (void*)m68k_op_and_16_er_al , + (void*)m68k_op_and_16_er_pcdi , + (void*)m68k_op_and_16_er_pcix , + (void*)m68k_op_and_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_and_32_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_ai , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pi , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_pd , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_di , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_ix , + (void*)m68k_op_and_32_er_aw , + (void*)m68k_op_and_32_er_al , + (void*)m68k_op_and_32_er_pcdi , + (void*)m68k_op_and_32_er_pcix , + (void*)m68k_op_and_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_mulu_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_ai , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pi , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_pd , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_di , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_ix , + (void*)m68k_op_mulu_16_aw , + (void*)m68k_op_mulu_16_al , + (void*)m68k_op_mulu_16_pcdi , + (void*)m68k_op_mulu_16_pcix , + (void*)m68k_op_mulu_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_rr , + (void*)m68k_op_abcd_8_mm_ax7 , + (void*)m68k_op_abcd_8_mm_ax7 , + (void*)m68k_op_abcd_8_mm_ax7 , + (void*)m68k_op_abcd_8_mm_ax7 , + (void*)m68k_op_abcd_8_mm_ax7 , + (void*)m68k_op_abcd_8_mm_ax7 , + (void*)m68k_op_abcd_8_mm_ax7 , + (void*)m68k_op_abcd_8_mm_axy7 , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_ai , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi , + (void*)m68k_op_and_8_re_pi7 , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd , + (void*)m68k_op_and_8_re_pd7 , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_di , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_ix , + (void*)m68k_op_and_8_re_aw , + (void*)m68k_op_and_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_dd , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_exg_32_aa , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_ai , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pi , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_pd , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_di , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_ix , + (void*)m68k_op_and_16_re_aw , + (void*)m68k_op_and_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_exg_32_da , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_ai , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pi , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_pd , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_di , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_ix , + (void*)m68k_op_and_32_re_aw , + (void*)m68k_op_and_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_muls_16_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_ai , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pi , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_pd , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_di , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_ix , + (void*)m68k_op_muls_16_aw , + (void*)m68k_op_muls_16_al , + (void*)m68k_op_muls_16_pcdi , + (void*)m68k_op_muls_16_pcix , + (void*)m68k_op_muls_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi7 , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd7 , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_aw , + (void*)m68k_op_add_8_er_al , + (void*)m68k_op_add_8_er_pcdi , + (void*)m68k_op_add_8_er_pcix , + (void*)m68k_op_add_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_aw , + (void*)m68k_op_add_16_er_al , + (void*)m68k_op_add_16_er_pcdi , + (void*)m68k_op_add_16_er_pcix , + (void*)m68k_op_add_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_aw , + (void*)m68k_op_add_32_er_al , + (void*)m68k_op_add_32_er_pcdi , + (void*)m68k_op_add_32_er_pcix , + (void*)m68k_op_add_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_aw , + (void*)m68k_op_adda_16_al , + (void*)m68k_op_adda_16_pcdi , + (void*)m68k_op_adda_16_pcix , + (void*)m68k_op_adda_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm_ay7 , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi7 , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd7 , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_aw , + (void*)m68k_op_add_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_aw , + (void*)m68k_op_add_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_aw , + (void*)m68k_op_add_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_aw , + (void*)m68k_op_adda_32_al , + (void*)m68k_op_adda_32_pcdi , + (void*)m68k_op_adda_32_pcix , + (void*)m68k_op_adda_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi7 , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd7 , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_aw , + (void*)m68k_op_add_8_er_al , + (void*)m68k_op_add_8_er_pcdi , + (void*)m68k_op_add_8_er_pcix , + (void*)m68k_op_add_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_aw , + (void*)m68k_op_add_16_er_al , + (void*)m68k_op_add_16_er_pcdi , + (void*)m68k_op_add_16_er_pcix , + (void*)m68k_op_add_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_aw , + (void*)m68k_op_add_32_er_al , + (void*)m68k_op_add_32_er_pcdi , + (void*)m68k_op_add_32_er_pcix , + (void*)m68k_op_add_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_aw , + (void*)m68k_op_adda_16_al , + (void*)m68k_op_adda_16_pcdi , + (void*)m68k_op_adda_16_pcix , + (void*)m68k_op_adda_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm_ay7 , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi7 , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd7 , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_aw , + (void*)m68k_op_add_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_aw , + (void*)m68k_op_add_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_aw , + (void*)m68k_op_add_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_aw , + (void*)m68k_op_adda_32_al , + (void*)m68k_op_adda_32_pcdi , + (void*)m68k_op_adda_32_pcix , + (void*)m68k_op_adda_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi7 , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd7 , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_aw , + (void*)m68k_op_add_8_er_al , + (void*)m68k_op_add_8_er_pcdi , + (void*)m68k_op_add_8_er_pcix , + (void*)m68k_op_add_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_aw , + (void*)m68k_op_add_16_er_al , + (void*)m68k_op_add_16_er_pcdi , + (void*)m68k_op_add_16_er_pcix , + (void*)m68k_op_add_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_aw , + (void*)m68k_op_add_32_er_al , + (void*)m68k_op_add_32_er_pcdi , + (void*)m68k_op_add_32_er_pcix , + (void*)m68k_op_add_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_aw , + (void*)m68k_op_adda_16_al , + (void*)m68k_op_adda_16_pcdi , + (void*)m68k_op_adda_16_pcix , + (void*)m68k_op_adda_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm_ay7 , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi7 , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd7 , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_aw , + (void*)m68k_op_add_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_aw , + (void*)m68k_op_add_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_aw , + (void*)m68k_op_add_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_aw , + (void*)m68k_op_adda_32_al , + (void*)m68k_op_adda_32_pcdi , + (void*)m68k_op_adda_32_pcix , + (void*)m68k_op_adda_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi7 , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd7 , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_aw , + (void*)m68k_op_add_8_er_al , + (void*)m68k_op_add_8_er_pcdi , + (void*)m68k_op_add_8_er_pcix , + (void*)m68k_op_add_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_aw , + (void*)m68k_op_add_16_er_al , + (void*)m68k_op_add_16_er_pcdi , + (void*)m68k_op_add_16_er_pcix , + (void*)m68k_op_add_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_aw , + (void*)m68k_op_add_32_er_al , + (void*)m68k_op_add_32_er_pcdi , + (void*)m68k_op_add_32_er_pcix , + (void*)m68k_op_add_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_aw , + (void*)m68k_op_adda_16_al , + (void*)m68k_op_adda_16_pcdi , + (void*)m68k_op_adda_16_pcix , + (void*)m68k_op_adda_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm_ay7 , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi7 , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd7 , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_aw , + (void*)m68k_op_add_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_aw , + (void*)m68k_op_add_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_aw , + (void*)m68k_op_add_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_aw , + (void*)m68k_op_adda_32_al , + (void*)m68k_op_adda_32_pcdi , + (void*)m68k_op_adda_32_pcix , + (void*)m68k_op_adda_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi7 , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd7 , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_aw , + (void*)m68k_op_add_8_er_al , + (void*)m68k_op_add_8_er_pcdi , + (void*)m68k_op_add_8_er_pcix , + (void*)m68k_op_add_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_aw , + (void*)m68k_op_add_16_er_al , + (void*)m68k_op_add_16_er_pcdi , + (void*)m68k_op_add_16_er_pcix , + (void*)m68k_op_add_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_aw , + (void*)m68k_op_add_32_er_al , + (void*)m68k_op_add_32_er_pcdi , + (void*)m68k_op_add_32_er_pcix , + (void*)m68k_op_add_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_aw , + (void*)m68k_op_adda_16_al , + (void*)m68k_op_adda_16_pcdi , + (void*)m68k_op_adda_16_pcix , + (void*)m68k_op_adda_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm_ay7 , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi7 , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd7 , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_aw , + (void*)m68k_op_add_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_aw , + (void*)m68k_op_add_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_aw , + (void*)m68k_op_add_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_aw , + (void*)m68k_op_adda_32_al , + (void*)m68k_op_adda_32_pcdi , + (void*)m68k_op_adda_32_pcix , + (void*)m68k_op_adda_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi7 , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd7 , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_aw , + (void*)m68k_op_add_8_er_al , + (void*)m68k_op_add_8_er_pcdi , + (void*)m68k_op_add_8_er_pcix , + (void*)m68k_op_add_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_aw , + (void*)m68k_op_add_16_er_al , + (void*)m68k_op_add_16_er_pcdi , + (void*)m68k_op_add_16_er_pcix , + (void*)m68k_op_add_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_aw , + (void*)m68k_op_add_32_er_al , + (void*)m68k_op_add_32_er_pcdi , + (void*)m68k_op_add_32_er_pcix , + (void*)m68k_op_add_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_aw , + (void*)m68k_op_adda_16_al , + (void*)m68k_op_adda_16_pcdi , + (void*)m68k_op_adda_16_pcix , + (void*)m68k_op_adda_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm_ay7 , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi7 , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd7 , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_aw , + (void*)m68k_op_add_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_aw , + (void*)m68k_op_add_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_aw , + (void*)m68k_op_add_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_aw , + (void*)m68k_op_adda_32_al , + (void*)m68k_op_adda_32_pcdi , + (void*)m68k_op_adda_32_pcix , + (void*)m68k_op_adda_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi7 , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd7 , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_aw , + (void*)m68k_op_add_8_er_al , + (void*)m68k_op_add_8_er_pcdi , + (void*)m68k_op_add_8_er_pcix , + (void*)m68k_op_add_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_aw , + (void*)m68k_op_add_16_er_al , + (void*)m68k_op_add_16_er_pcdi , + (void*)m68k_op_add_16_er_pcix , + (void*)m68k_op_add_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_aw , + (void*)m68k_op_add_32_er_al , + (void*)m68k_op_add_32_er_pcdi , + (void*)m68k_op_add_32_er_pcix , + (void*)m68k_op_add_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_aw , + (void*)m68k_op_adda_16_al , + (void*)m68k_op_adda_16_pcdi , + (void*)m68k_op_adda_16_pcix , + (void*)m68k_op_adda_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm , + (void*)m68k_op_addx_8_mm_ay7 , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi7 , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd7 , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_aw , + (void*)m68k_op_add_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_aw , + (void*)m68k_op_add_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_aw , + (void*)m68k_op_add_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_aw , + (void*)m68k_op_adda_32_al , + (void*)m68k_op_adda_32_pcdi , + (void*)m68k_op_adda_32_pcix , + (void*)m68k_op_adda_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_add_8_er_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_ai , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi , + (void*)m68k_op_add_8_er_pi7 , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd , + (void*)m68k_op_add_8_er_pd7 , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_di , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_ix , + (void*)m68k_op_add_8_er_aw , + (void*)m68k_op_add_8_er_al , + (void*)m68k_op_add_8_er_pcdi , + (void*)m68k_op_add_8_er_pcix , + (void*)m68k_op_add_8_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_d , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_a , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_ai , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pi , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_pd , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_di , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_ix , + (void*)m68k_op_add_16_er_aw , + (void*)m68k_op_add_16_er_al , + (void*)m68k_op_add_16_er_pcdi , + (void*)m68k_op_add_16_er_pcix , + (void*)m68k_op_add_16_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_d , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_a , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_ai , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pi , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_pd , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_di , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_ix , + (void*)m68k_op_add_32_er_aw , + (void*)m68k_op_add_32_er_al , + (void*)m68k_op_add_32_er_pcdi , + (void*)m68k_op_add_32_er_pcix , + (void*)m68k_op_add_32_er_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_d , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_a , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_ai , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pi , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_pd , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_di , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_ix , + (void*)m68k_op_adda_16_aw , + (void*)m68k_op_adda_16_al , + (void*)m68k_op_adda_16_pcdi , + (void*)m68k_op_adda_16_pcix , + (void*)m68k_op_adda_16_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_rr , + (void*)m68k_op_addx_8_mm_ax7 , + (void*)m68k_op_addx_8_mm_ax7 , + (void*)m68k_op_addx_8_mm_ax7 , + (void*)m68k_op_addx_8_mm_ax7 , + (void*)m68k_op_addx_8_mm_ax7 , + (void*)m68k_op_addx_8_mm_ax7 , + (void*)m68k_op_addx_8_mm_ax7 , + (void*)m68k_op_addx_8_mm_axy7 , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_ai , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi , + (void*)m68k_op_add_8_re_pi7 , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd , + (void*)m68k_op_add_8_re_pd7 , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_di , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_ix , + (void*)m68k_op_add_8_re_aw , + (void*)m68k_op_add_8_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_rr , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_addx_16_mm , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_ai , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pi , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_pd , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_di , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_ix , + (void*)m68k_op_add_16_re_aw , + (void*)m68k_op_add_16_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_rr , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_addx_32_mm , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_ai , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pi , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_pd , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_di , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_ix , + (void*)m68k_op_add_32_re_aw , + (void*)m68k_op_add_32_re_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_d , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_a , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_ai , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pi , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_pd , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_di , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_ix , + (void*)m68k_op_adda_32_aw , + (void*)m68k_op_adda_32_al , + (void*)m68k_op_adda_32_pcdi , + (void*)m68k_op_adda_32_pcix , + (void*)m68k_op_adda_32_i , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asr_16_ai , + (void*)m68k_op_asr_16_ai , + (void*)m68k_op_asr_16_ai , + (void*)m68k_op_asr_16_ai , + (void*)m68k_op_asr_16_ai , + (void*)m68k_op_asr_16_ai , + (void*)m68k_op_asr_16_ai , + (void*)m68k_op_asr_16_ai , + (void*)m68k_op_asr_16_pi , + (void*)m68k_op_asr_16_pi , + (void*)m68k_op_asr_16_pi , + (void*)m68k_op_asr_16_pi , + (void*)m68k_op_asr_16_pi , + (void*)m68k_op_asr_16_pi , + (void*)m68k_op_asr_16_pi , + (void*)m68k_op_asr_16_pi , + (void*)m68k_op_asr_16_pd , + (void*)m68k_op_asr_16_pd , + (void*)m68k_op_asr_16_pd , + (void*)m68k_op_asr_16_pd , + (void*)m68k_op_asr_16_pd , + (void*)m68k_op_asr_16_pd , + (void*)m68k_op_asr_16_pd , + (void*)m68k_op_asr_16_pd , + (void*)m68k_op_asr_16_di , + (void*)m68k_op_asr_16_di , + (void*)m68k_op_asr_16_di , + (void*)m68k_op_asr_16_di , + (void*)m68k_op_asr_16_di , + (void*)m68k_op_asr_16_di , + (void*)m68k_op_asr_16_di , + (void*)m68k_op_asr_16_di , + (void*)m68k_op_asr_16_ix , + (void*)m68k_op_asr_16_ix , + (void*)m68k_op_asr_16_ix , + (void*)m68k_op_asr_16_ix , + (void*)m68k_op_asr_16_ix , + (void*)m68k_op_asr_16_ix , + (void*)m68k_op_asr_16_ix , + (void*)m68k_op_asr_16_ix , + (void*)m68k_op_asr_16_aw , + (void*)m68k_op_asr_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asl_16_ai , + (void*)m68k_op_asl_16_ai , + (void*)m68k_op_asl_16_ai , + (void*)m68k_op_asl_16_ai , + (void*)m68k_op_asl_16_ai , + (void*)m68k_op_asl_16_ai , + (void*)m68k_op_asl_16_ai , + (void*)m68k_op_asl_16_ai , + (void*)m68k_op_asl_16_pi , + (void*)m68k_op_asl_16_pi , + (void*)m68k_op_asl_16_pi , + (void*)m68k_op_asl_16_pi , + (void*)m68k_op_asl_16_pi , + (void*)m68k_op_asl_16_pi , + (void*)m68k_op_asl_16_pi , + (void*)m68k_op_asl_16_pi , + (void*)m68k_op_asl_16_pd , + (void*)m68k_op_asl_16_pd , + (void*)m68k_op_asl_16_pd , + (void*)m68k_op_asl_16_pd , + (void*)m68k_op_asl_16_pd , + (void*)m68k_op_asl_16_pd , + (void*)m68k_op_asl_16_pd , + (void*)m68k_op_asl_16_pd , + (void*)m68k_op_asl_16_di , + (void*)m68k_op_asl_16_di , + (void*)m68k_op_asl_16_di , + (void*)m68k_op_asl_16_di , + (void*)m68k_op_asl_16_di , + (void*)m68k_op_asl_16_di , + (void*)m68k_op_asl_16_di , + (void*)m68k_op_asl_16_di , + (void*)m68k_op_asl_16_ix , + (void*)m68k_op_asl_16_ix , + (void*)m68k_op_asl_16_ix , + (void*)m68k_op_asl_16_ix , + (void*)m68k_op_asl_16_ix , + (void*)m68k_op_asl_16_ix , + (void*)m68k_op_asl_16_ix , + (void*)m68k_op_asl_16_ix , + (void*)m68k_op_asl_16_aw , + (void*)m68k_op_asl_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lsr_16_ai , + (void*)m68k_op_lsr_16_ai , + (void*)m68k_op_lsr_16_ai , + (void*)m68k_op_lsr_16_ai , + (void*)m68k_op_lsr_16_ai , + (void*)m68k_op_lsr_16_ai , + (void*)m68k_op_lsr_16_ai , + (void*)m68k_op_lsr_16_ai , + (void*)m68k_op_lsr_16_pi , + (void*)m68k_op_lsr_16_pi , + (void*)m68k_op_lsr_16_pi , + (void*)m68k_op_lsr_16_pi , + (void*)m68k_op_lsr_16_pi , + (void*)m68k_op_lsr_16_pi , + (void*)m68k_op_lsr_16_pi , + (void*)m68k_op_lsr_16_pi , + (void*)m68k_op_lsr_16_pd , + (void*)m68k_op_lsr_16_pd , + (void*)m68k_op_lsr_16_pd , + (void*)m68k_op_lsr_16_pd , + (void*)m68k_op_lsr_16_pd , + (void*)m68k_op_lsr_16_pd , + (void*)m68k_op_lsr_16_pd , + (void*)m68k_op_lsr_16_pd , + (void*)m68k_op_lsr_16_di , + (void*)m68k_op_lsr_16_di , + (void*)m68k_op_lsr_16_di , + (void*)m68k_op_lsr_16_di , + (void*)m68k_op_lsr_16_di , + (void*)m68k_op_lsr_16_di , + (void*)m68k_op_lsr_16_di , + (void*)m68k_op_lsr_16_di , + (void*)m68k_op_lsr_16_ix , + (void*)m68k_op_lsr_16_ix , + (void*)m68k_op_lsr_16_ix , + (void*)m68k_op_lsr_16_ix , + (void*)m68k_op_lsr_16_ix , + (void*)m68k_op_lsr_16_ix , + (void*)m68k_op_lsr_16_ix , + (void*)m68k_op_lsr_16_ix , + (void*)m68k_op_lsr_16_aw , + (void*)m68k_op_lsr_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_lsl_16_ai , + (void*)m68k_op_lsl_16_ai , + (void*)m68k_op_lsl_16_ai , + (void*)m68k_op_lsl_16_ai , + (void*)m68k_op_lsl_16_ai , + (void*)m68k_op_lsl_16_ai , + (void*)m68k_op_lsl_16_ai , + (void*)m68k_op_lsl_16_ai , + (void*)m68k_op_lsl_16_pi , + (void*)m68k_op_lsl_16_pi , + (void*)m68k_op_lsl_16_pi , + (void*)m68k_op_lsl_16_pi , + (void*)m68k_op_lsl_16_pi , + (void*)m68k_op_lsl_16_pi , + (void*)m68k_op_lsl_16_pi , + (void*)m68k_op_lsl_16_pi , + (void*)m68k_op_lsl_16_pd , + (void*)m68k_op_lsl_16_pd , + (void*)m68k_op_lsl_16_pd , + (void*)m68k_op_lsl_16_pd , + (void*)m68k_op_lsl_16_pd , + (void*)m68k_op_lsl_16_pd , + (void*)m68k_op_lsl_16_pd , + (void*)m68k_op_lsl_16_pd , + (void*)m68k_op_lsl_16_di , + (void*)m68k_op_lsl_16_di , + (void*)m68k_op_lsl_16_di , + (void*)m68k_op_lsl_16_di , + (void*)m68k_op_lsl_16_di , + (void*)m68k_op_lsl_16_di , + (void*)m68k_op_lsl_16_di , + (void*)m68k_op_lsl_16_di , + (void*)m68k_op_lsl_16_ix , + (void*)m68k_op_lsl_16_ix , + (void*)m68k_op_lsl_16_ix , + (void*)m68k_op_lsl_16_ix , + (void*)m68k_op_lsl_16_ix , + (void*)m68k_op_lsl_16_ix , + (void*)m68k_op_lsl_16_ix , + (void*)m68k_op_lsl_16_ix , + (void*)m68k_op_lsl_16_aw , + (void*)m68k_op_lsl_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_roxr_16_ai , + (void*)m68k_op_roxr_16_ai , + (void*)m68k_op_roxr_16_ai , + (void*)m68k_op_roxr_16_ai , + (void*)m68k_op_roxr_16_ai , + (void*)m68k_op_roxr_16_ai , + (void*)m68k_op_roxr_16_ai , + (void*)m68k_op_roxr_16_ai , + (void*)m68k_op_roxr_16_pi , + (void*)m68k_op_roxr_16_pi , + (void*)m68k_op_roxr_16_pi , + (void*)m68k_op_roxr_16_pi , + (void*)m68k_op_roxr_16_pi , + (void*)m68k_op_roxr_16_pi , + (void*)m68k_op_roxr_16_pi , + (void*)m68k_op_roxr_16_pi , + (void*)m68k_op_roxr_16_pd , + (void*)m68k_op_roxr_16_pd , + (void*)m68k_op_roxr_16_pd , + (void*)m68k_op_roxr_16_pd , + (void*)m68k_op_roxr_16_pd , + (void*)m68k_op_roxr_16_pd , + (void*)m68k_op_roxr_16_pd , + (void*)m68k_op_roxr_16_pd , + (void*)m68k_op_roxr_16_di , + (void*)m68k_op_roxr_16_di , + (void*)m68k_op_roxr_16_di , + (void*)m68k_op_roxr_16_di , + (void*)m68k_op_roxr_16_di , + (void*)m68k_op_roxr_16_di , + (void*)m68k_op_roxr_16_di , + (void*)m68k_op_roxr_16_di , + (void*)m68k_op_roxr_16_ix , + (void*)m68k_op_roxr_16_ix , + (void*)m68k_op_roxr_16_ix , + (void*)m68k_op_roxr_16_ix , + (void*)m68k_op_roxr_16_ix , + (void*)m68k_op_roxr_16_ix , + (void*)m68k_op_roxr_16_ix , + (void*)m68k_op_roxr_16_ix , + (void*)m68k_op_roxr_16_aw , + (void*)m68k_op_roxr_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_roxl_16_ai , + (void*)m68k_op_roxl_16_ai , + (void*)m68k_op_roxl_16_ai , + (void*)m68k_op_roxl_16_ai , + (void*)m68k_op_roxl_16_ai , + (void*)m68k_op_roxl_16_ai , + (void*)m68k_op_roxl_16_ai , + (void*)m68k_op_roxl_16_ai , + (void*)m68k_op_roxl_16_pi , + (void*)m68k_op_roxl_16_pi , + (void*)m68k_op_roxl_16_pi , + (void*)m68k_op_roxl_16_pi , + (void*)m68k_op_roxl_16_pi , + (void*)m68k_op_roxl_16_pi , + (void*)m68k_op_roxl_16_pi , + (void*)m68k_op_roxl_16_pi , + (void*)m68k_op_roxl_16_pd , + (void*)m68k_op_roxl_16_pd , + (void*)m68k_op_roxl_16_pd , + (void*)m68k_op_roxl_16_pd , + (void*)m68k_op_roxl_16_pd , + (void*)m68k_op_roxl_16_pd , + (void*)m68k_op_roxl_16_pd , + (void*)m68k_op_roxl_16_pd , + (void*)m68k_op_roxl_16_di , + (void*)m68k_op_roxl_16_di , + (void*)m68k_op_roxl_16_di , + (void*)m68k_op_roxl_16_di , + (void*)m68k_op_roxl_16_di , + (void*)m68k_op_roxl_16_di , + (void*)m68k_op_roxl_16_di , + (void*)m68k_op_roxl_16_di , + (void*)m68k_op_roxl_16_ix , + (void*)m68k_op_roxl_16_ix , + (void*)m68k_op_roxl_16_ix , + (void*)m68k_op_roxl_16_ix , + (void*)m68k_op_roxl_16_ix , + (void*)m68k_op_roxl_16_ix , + (void*)m68k_op_roxl_16_ix , + (void*)m68k_op_roxl_16_ix , + (void*)m68k_op_roxl_16_aw , + (void*)m68k_op_roxl_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_ror_16_ai , + (void*)m68k_op_ror_16_ai , + (void*)m68k_op_ror_16_ai , + (void*)m68k_op_ror_16_ai , + (void*)m68k_op_ror_16_ai , + (void*)m68k_op_ror_16_ai , + (void*)m68k_op_ror_16_ai , + (void*)m68k_op_ror_16_ai , + (void*)m68k_op_ror_16_pi , + (void*)m68k_op_ror_16_pi , + (void*)m68k_op_ror_16_pi , + (void*)m68k_op_ror_16_pi , + (void*)m68k_op_ror_16_pi , + (void*)m68k_op_ror_16_pi , + (void*)m68k_op_ror_16_pi , + (void*)m68k_op_ror_16_pi , + (void*)m68k_op_ror_16_pd , + (void*)m68k_op_ror_16_pd , + (void*)m68k_op_ror_16_pd , + (void*)m68k_op_ror_16_pd , + (void*)m68k_op_ror_16_pd , + (void*)m68k_op_ror_16_pd , + (void*)m68k_op_ror_16_pd , + (void*)m68k_op_ror_16_pd , + (void*)m68k_op_ror_16_di , + (void*)m68k_op_ror_16_di , + (void*)m68k_op_ror_16_di , + (void*)m68k_op_ror_16_di , + (void*)m68k_op_ror_16_di , + (void*)m68k_op_ror_16_di , + (void*)m68k_op_ror_16_di , + (void*)m68k_op_ror_16_di , + (void*)m68k_op_ror_16_ix , + (void*)m68k_op_ror_16_ix , + (void*)m68k_op_ror_16_ix , + (void*)m68k_op_ror_16_ix , + (void*)m68k_op_ror_16_ix , + (void*)m68k_op_ror_16_ix , + (void*)m68k_op_ror_16_ix , + (void*)m68k_op_ror_16_ix , + (void*)m68k_op_ror_16_aw , + (void*)m68k_op_ror_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_rol_16_ai , + (void*)m68k_op_rol_16_ai , + (void*)m68k_op_rol_16_ai , + (void*)m68k_op_rol_16_ai , + (void*)m68k_op_rol_16_ai , + (void*)m68k_op_rol_16_ai , + (void*)m68k_op_rol_16_ai , + (void*)m68k_op_rol_16_ai , + (void*)m68k_op_rol_16_pi , + (void*)m68k_op_rol_16_pi , + (void*)m68k_op_rol_16_pi , + (void*)m68k_op_rol_16_pi , + (void*)m68k_op_rol_16_pi , + (void*)m68k_op_rol_16_pi , + (void*)m68k_op_rol_16_pi , + (void*)m68k_op_rol_16_pi , + (void*)m68k_op_rol_16_pd , + (void*)m68k_op_rol_16_pd , + (void*)m68k_op_rol_16_pd , + (void*)m68k_op_rol_16_pd , + (void*)m68k_op_rol_16_pd , + (void*)m68k_op_rol_16_pd , + (void*)m68k_op_rol_16_pd , + (void*)m68k_op_rol_16_pd , + (void*)m68k_op_rol_16_di , + (void*)m68k_op_rol_16_di , + (void*)m68k_op_rol_16_di , + (void*)m68k_op_rol_16_di , + (void*)m68k_op_rol_16_di , + (void*)m68k_op_rol_16_di , + (void*)m68k_op_rol_16_di , + (void*)m68k_op_rol_16_di , + (void*)m68k_op_rol_16_ix , + (void*)m68k_op_rol_16_ix , + (void*)m68k_op_rol_16_ix , + (void*)m68k_op_rol_16_ix , + (void*)m68k_op_rol_16_ix , + (void*)m68k_op_rol_16_ix , + (void*)m68k_op_rol_16_ix , + (void*)m68k_op_rol_16_ix , + (void*)m68k_op_rol_16_aw , + (void*)m68k_op_rol_16_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_bftst_32_d , + (void*)m68k_op_bftst_32_d , + (void*)m68k_op_bftst_32_d , + (void*)m68k_op_bftst_32_d , + (void*)m68k_op_bftst_32_d , + (void*)m68k_op_bftst_32_d , + (void*)m68k_op_bftst_32_d , + (void*)m68k_op_bftst_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bftst_32_ai , + (void*)m68k_op_bftst_32_ai , + (void*)m68k_op_bftst_32_ai , + (void*)m68k_op_bftst_32_ai , + (void*)m68k_op_bftst_32_ai , + (void*)m68k_op_bftst_32_ai , + (void*)m68k_op_bftst_32_ai , + (void*)m68k_op_bftst_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bftst_32_di , + (void*)m68k_op_bftst_32_di , + (void*)m68k_op_bftst_32_di , + (void*)m68k_op_bftst_32_di , + (void*)m68k_op_bftst_32_di , + (void*)m68k_op_bftst_32_di , + (void*)m68k_op_bftst_32_di , + (void*)m68k_op_bftst_32_di , + (void*)m68k_op_bftst_32_ix , + (void*)m68k_op_bftst_32_ix , + (void*)m68k_op_bftst_32_ix , + (void*)m68k_op_bftst_32_ix , + (void*)m68k_op_bftst_32_ix , + (void*)m68k_op_bftst_32_ix , + (void*)m68k_op_bftst_32_ix , + (void*)m68k_op_bftst_32_ix , + (void*)m68k_op_bftst_32_aw , + (void*)m68k_op_bftst_32_al , + (void*)m68k_op_bftst_32_pcdi , + (void*)m68k_op_bftst_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_bfextu_32_d , + (void*)m68k_op_bfextu_32_d , + (void*)m68k_op_bfextu_32_d , + (void*)m68k_op_bfextu_32_d , + (void*)m68k_op_bfextu_32_d , + (void*)m68k_op_bfextu_32_d , + (void*)m68k_op_bfextu_32_d , + (void*)m68k_op_bfextu_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfextu_32_ai , + (void*)m68k_op_bfextu_32_ai , + (void*)m68k_op_bfextu_32_ai , + (void*)m68k_op_bfextu_32_ai , + (void*)m68k_op_bfextu_32_ai , + (void*)m68k_op_bfextu_32_ai , + (void*)m68k_op_bfextu_32_ai , + (void*)m68k_op_bfextu_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfextu_32_di , + (void*)m68k_op_bfextu_32_di , + (void*)m68k_op_bfextu_32_di , + (void*)m68k_op_bfextu_32_di , + (void*)m68k_op_bfextu_32_di , + (void*)m68k_op_bfextu_32_di , + (void*)m68k_op_bfextu_32_di , + (void*)m68k_op_bfextu_32_di , + (void*)m68k_op_bfextu_32_ix , + (void*)m68k_op_bfextu_32_ix , + (void*)m68k_op_bfextu_32_ix , + (void*)m68k_op_bfextu_32_ix , + (void*)m68k_op_bfextu_32_ix , + (void*)m68k_op_bfextu_32_ix , + (void*)m68k_op_bfextu_32_ix , + (void*)m68k_op_bfextu_32_ix , + (void*)m68k_op_bfextu_32_aw , + (void*)m68k_op_bfextu_32_al , + (void*)m68k_op_bfextu_32_pcdi , + (void*)m68k_op_bfextu_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_bfchg_32_d , + (void*)m68k_op_bfchg_32_d , + (void*)m68k_op_bfchg_32_d , + (void*)m68k_op_bfchg_32_d , + (void*)m68k_op_bfchg_32_d , + (void*)m68k_op_bfchg_32_d , + (void*)m68k_op_bfchg_32_d , + (void*)m68k_op_bfchg_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfchg_32_ai , + (void*)m68k_op_bfchg_32_ai , + (void*)m68k_op_bfchg_32_ai , + (void*)m68k_op_bfchg_32_ai , + (void*)m68k_op_bfchg_32_ai , + (void*)m68k_op_bfchg_32_ai , + (void*)m68k_op_bfchg_32_ai , + (void*)m68k_op_bfchg_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfchg_32_di , + (void*)m68k_op_bfchg_32_di , + (void*)m68k_op_bfchg_32_di , + (void*)m68k_op_bfchg_32_di , + (void*)m68k_op_bfchg_32_di , + (void*)m68k_op_bfchg_32_di , + (void*)m68k_op_bfchg_32_di , + (void*)m68k_op_bfchg_32_di , + (void*)m68k_op_bfchg_32_ix , + (void*)m68k_op_bfchg_32_ix , + (void*)m68k_op_bfchg_32_ix , + (void*)m68k_op_bfchg_32_ix , + (void*)m68k_op_bfchg_32_ix , + (void*)m68k_op_bfchg_32_ix , + (void*)m68k_op_bfchg_32_ix , + (void*)m68k_op_bfchg_32_ix , + (void*)m68k_op_bfchg_32_aw , + (void*)m68k_op_bfchg_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_bfexts_32_d , + (void*)m68k_op_bfexts_32_d , + (void*)m68k_op_bfexts_32_d , + (void*)m68k_op_bfexts_32_d , + (void*)m68k_op_bfexts_32_d , + (void*)m68k_op_bfexts_32_d , + (void*)m68k_op_bfexts_32_d , + (void*)m68k_op_bfexts_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfexts_32_ai , + (void*)m68k_op_bfexts_32_ai , + (void*)m68k_op_bfexts_32_ai , + (void*)m68k_op_bfexts_32_ai , + (void*)m68k_op_bfexts_32_ai , + (void*)m68k_op_bfexts_32_ai , + (void*)m68k_op_bfexts_32_ai , + (void*)m68k_op_bfexts_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfexts_32_di , + (void*)m68k_op_bfexts_32_di , + (void*)m68k_op_bfexts_32_di , + (void*)m68k_op_bfexts_32_di , + (void*)m68k_op_bfexts_32_di , + (void*)m68k_op_bfexts_32_di , + (void*)m68k_op_bfexts_32_di , + (void*)m68k_op_bfexts_32_di , + (void*)m68k_op_bfexts_32_ix , + (void*)m68k_op_bfexts_32_ix , + (void*)m68k_op_bfexts_32_ix , + (void*)m68k_op_bfexts_32_ix , + (void*)m68k_op_bfexts_32_ix , + (void*)m68k_op_bfexts_32_ix , + (void*)m68k_op_bfexts_32_ix , + (void*)m68k_op_bfexts_32_ix , + (void*)m68k_op_bfexts_32_aw , + (void*)m68k_op_bfexts_32_al , + (void*)m68k_op_bfexts_32_pcdi , + (void*)m68k_op_bfexts_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_bfclr_32_d , + (void*)m68k_op_bfclr_32_d , + (void*)m68k_op_bfclr_32_d , + (void*)m68k_op_bfclr_32_d , + (void*)m68k_op_bfclr_32_d , + (void*)m68k_op_bfclr_32_d , + (void*)m68k_op_bfclr_32_d , + (void*)m68k_op_bfclr_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfclr_32_ai , + (void*)m68k_op_bfclr_32_ai , + (void*)m68k_op_bfclr_32_ai , + (void*)m68k_op_bfclr_32_ai , + (void*)m68k_op_bfclr_32_ai , + (void*)m68k_op_bfclr_32_ai , + (void*)m68k_op_bfclr_32_ai , + (void*)m68k_op_bfclr_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfclr_32_di , + (void*)m68k_op_bfclr_32_di , + (void*)m68k_op_bfclr_32_di , + (void*)m68k_op_bfclr_32_di , + (void*)m68k_op_bfclr_32_di , + (void*)m68k_op_bfclr_32_di , + (void*)m68k_op_bfclr_32_di , + (void*)m68k_op_bfclr_32_di , + (void*)m68k_op_bfclr_32_ix , + (void*)m68k_op_bfclr_32_ix , + (void*)m68k_op_bfclr_32_ix , + (void*)m68k_op_bfclr_32_ix , + (void*)m68k_op_bfclr_32_ix , + (void*)m68k_op_bfclr_32_ix , + (void*)m68k_op_bfclr_32_ix , + (void*)m68k_op_bfclr_32_ix , + (void*)m68k_op_bfclr_32_aw , + (void*)m68k_op_bfclr_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_bfffo_32_d , + (void*)m68k_op_bfffo_32_d , + (void*)m68k_op_bfffo_32_d , + (void*)m68k_op_bfffo_32_d , + (void*)m68k_op_bfffo_32_d , + (void*)m68k_op_bfffo_32_d , + (void*)m68k_op_bfffo_32_d , + (void*)m68k_op_bfffo_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfffo_32_ai , + (void*)m68k_op_bfffo_32_ai , + (void*)m68k_op_bfffo_32_ai , + (void*)m68k_op_bfffo_32_ai , + (void*)m68k_op_bfffo_32_ai , + (void*)m68k_op_bfffo_32_ai , + (void*)m68k_op_bfffo_32_ai , + (void*)m68k_op_bfffo_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfffo_32_di , + (void*)m68k_op_bfffo_32_di , + (void*)m68k_op_bfffo_32_di , + (void*)m68k_op_bfffo_32_di , + (void*)m68k_op_bfffo_32_di , + (void*)m68k_op_bfffo_32_di , + (void*)m68k_op_bfffo_32_di , + (void*)m68k_op_bfffo_32_di , + (void*)m68k_op_bfffo_32_ix , + (void*)m68k_op_bfffo_32_ix , + (void*)m68k_op_bfffo_32_ix , + (void*)m68k_op_bfffo_32_ix , + (void*)m68k_op_bfffo_32_ix , + (void*)m68k_op_bfffo_32_ix , + (void*)m68k_op_bfffo_32_ix , + (void*)m68k_op_bfffo_32_ix , + (void*)m68k_op_bfffo_32_aw , + (void*)m68k_op_bfffo_32_al , + (void*)m68k_op_bfffo_32_pcdi , + (void*)m68k_op_bfffo_32_pcix , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_asr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_lsr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_roxr_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_ror_8_s , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_asr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_lsr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_roxr_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_ror_8_r , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_asr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_lsr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_roxr_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_ror_16_s , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_asr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_lsr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_roxr_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_ror_16_r , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_asr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_lsr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_roxr_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_ror_32_s , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_asr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_lsr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_roxr_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_ror_32_r , + (void*)m68k_op_bfset_32_d , + (void*)m68k_op_bfset_32_d , + (void*)m68k_op_bfset_32_d , + (void*)m68k_op_bfset_32_d , + (void*)m68k_op_bfset_32_d , + (void*)m68k_op_bfset_32_d , + (void*)m68k_op_bfset_32_d , + (void*)m68k_op_bfset_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfset_32_ai , + (void*)m68k_op_bfset_32_ai , + (void*)m68k_op_bfset_32_ai , + (void*)m68k_op_bfset_32_ai , + (void*)m68k_op_bfset_32_ai , + (void*)m68k_op_bfset_32_ai , + (void*)m68k_op_bfset_32_ai , + (void*)m68k_op_bfset_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfset_32_di , + (void*)m68k_op_bfset_32_di , + (void*)m68k_op_bfset_32_di , + (void*)m68k_op_bfset_32_di , + (void*)m68k_op_bfset_32_di , + (void*)m68k_op_bfset_32_di , + (void*)m68k_op_bfset_32_di , + (void*)m68k_op_bfset_32_di , + (void*)m68k_op_bfset_32_ix , + (void*)m68k_op_bfset_32_ix , + (void*)m68k_op_bfset_32_ix , + (void*)m68k_op_bfset_32_ix , + (void*)m68k_op_bfset_32_ix , + (void*)m68k_op_bfset_32_ix , + (void*)m68k_op_bfset_32_ix , + (void*)m68k_op_bfset_32_ix , + (void*)m68k_op_bfset_32_aw , + (void*)m68k_op_bfset_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_asl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_lsl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_roxl_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_rol_8_s , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_asl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_lsl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_roxl_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_rol_8_r , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_asl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_lsl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_roxl_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_rol_16_s , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_asl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_lsl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_roxl_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_rol_16_r , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_asl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_lsl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_roxl_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_rol_32_s , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_asl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_lsl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_roxl_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_rol_32_r , + (void*)m68k_op_bfins_32_d , + (void*)m68k_op_bfins_32_d , + (void*)m68k_op_bfins_32_d , + (void*)m68k_op_bfins_32_d , + (void*)m68k_op_bfins_32_d , + (void*)m68k_op_bfins_32_d , + (void*)m68k_op_bfins_32_d , + (void*)m68k_op_bfins_32_d , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfins_32_ai , + (void*)m68k_op_bfins_32_ai , + (void*)m68k_op_bfins_32_ai , + (void*)m68k_op_bfins_32_ai , + (void*)m68k_op_bfins_32_ai , + (void*)m68k_op_bfins_32_ai , + (void*)m68k_op_bfins_32_ai , + (void*)m68k_op_bfins_32_ai , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_bfins_32_di , + (void*)m68k_op_bfins_32_di , + (void*)m68k_op_bfins_32_di , + (void*)m68k_op_bfins_32_di , + (void*)m68k_op_bfins_32_di , + (void*)m68k_op_bfins_32_di , + (void*)m68k_op_bfins_32_di , + (void*)m68k_op_bfins_32_di , + (void*)m68k_op_bfins_32_ix , + (void*)m68k_op_bfins_32_ix , + (void*)m68k_op_bfins_32_ix , + (void*)m68k_op_bfins_32_ix , + (void*)m68k_op_bfins_32_ix , + (void*)m68k_op_bfins_32_ix , + (void*)m68k_op_bfins_32_ix , + (void*)m68k_op_bfins_32_ix , + (void*)m68k_op_bfins_32_aw , + (void*)m68k_op_bfins_32_al , + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_illegal, + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpgen_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpdbcc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cpscc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cptrapcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_cpbcc_32 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , + (void*)m68k_op_1111 , +}; + + diff --git a/MCUME_teensy/teensygen/macros.h b/MCUME_teensy/teensygen/macros.h new file mode 100644 index 0000000..15762f7 --- /dev/null +++ b/MCUME_teensy/teensygen/macros.h @@ -0,0 +1,24 @@ + +#ifndef _MACROS_H_ +#define _MACROS_H_ + + +#define READ_BYTE(BASE, ADDR) (BASE)[(ADDR)^1] +#define READ_WORD(BASE, ADDR) (((BASE)[(ADDR)+1]<<8) | \ + (BASE)[(ADDR)]) +#define READ_LONG(BASE, ADDR) (((BASE)[(ADDR)+1]<<24) | \ + ((BASE)[(ADDR)+0]<<16) | \ + ((BASE)[(ADDR)+3]<<8) | \ + (BASE)[(ADDR)+2]) + +#define WRITE_BYTE(BASE, ADDR, VAL) (BASE)[(ADDR)^1] = (VAL)&0xff +#define WRITE_WORD(BASE, ADDR, VAL) (BASE)[(ADDR)+1] = ((VAL)>>8) & 0xff; \ + (BASE)[ADDR] = (VAL)&0xff +#define WRITE_LONG(BASE, ADDR, VAL) (BASE)[(ADDR)+1] = ((VAL)>>24) & 0xff; \ + (BASE)[(ADDR)+0] = ((VAL)>>16)&0xff; \ + (BASE)[(ADDR)+3] = ((VAL)>>8)&0xff; \ + (BASE)[(ADDR)+2] = (VAL)&0xff + + +#endif /* _MACROS_H_ */ + diff --git a/MCUME_teensy/teensygen/mem68k.c b/MCUME_teensy/teensygen/mem68k.c new file mode 100644 index 0000000..bb2c262 --- /dev/null +++ b/MCUME_teensy/teensygen/mem68k.c @@ -0,0 +1,715 @@ + +#include "shared.h" + +unsigned int m68k_read_bus_8(unsigned int address) +{ + uint16 temp = m68k_read_bus_16(address); + return ((address & 1) ? (temp & 0xFF) : (temp >> 8)); +} + +unsigned int m68k_read_bus_16(unsigned int address) +{ + uint16 temp = 0x4e71; + + if(address >= 0xC00000) + { + return (temp); + } + else + { + return (temp & 0xFF00); + } +} + +void m68k_unused_w(unsigned int address, unsigned int value) +{ +//error("Unused %08X = %08X (%08X)\n", address, value, Turbo68KReadPC()); +} + +void m68k_unused_8_w(unsigned int address, unsigned int value) +{ +//error("Unused %08X = %02X (%08X)\n", address, value, Turbo68KReadPC()); +} + +void m68k_unused_16_w(unsigned int address, unsigned int value) +{ +//error("Unused %08X = %04X (%08X)\n", address, value, Turbo68KReadPC()); +} + +/* + Functions to handle memory accesses which cause the Genesis to halt + either temporarily (press RESET button to restart) or unrecoverably + (cycle power to restart). +*/ + +void m68k_lockup_w_8(unsigned int address, unsigned int value) +{ + error("Lockup %08X = %02X (%08X)\n", address, value, m68k_get_reg(NULL, M68K_REG_PC)); + gen_running = 0; + m68k_end_timeslice(); +} + +void m68k_lockup_w_16(unsigned int address, unsigned int value) +{ + error("Lockup %08X = %04X (%08X)\n", address, value, m68k_get_reg(NULL, M68K_REG_PC)); + gen_running = 0; + m68k_end_timeslice(); +} + +unsigned int m68k_lockup_r_8(unsigned int address) +{ + error("Lockup %08X.b (%08X)\n", address, m68k_get_reg(NULL, M68K_REG_PC)); + gen_running = 0; + m68k_end_timeslice(); + return -1; +} + +unsigned int m68k_lockup_r_16(unsigned int address) +{ + error("Lockup %08X.w (%08X)\n", address, m68k_get_reg(NULL, M68K_REG_PC)); + gen_running = 0; + m68k_end_timeslice(); + return -1; +} + +/*--------------------------------------------------------------------------*/ +/* 68000 memory handlers */ +/*--------------------------------------------------------------------------*/ + +unsigned int m68k_read_memory_8(unsigned int address) +{ + switch((address >> 21) & 7) + { + case 0: /* ROM */ + case 1: + return readb_swap_rom(address); + + case 7: /* RAM */ + return READ_BYTE(work_ram, address & 0xFFFF); + + case 5: /* Z80 & I/O */ + if(address <= 0xA0FFFF) + { + if(zbusack == 1) + { + /* Z80 controls Z bus */ + return (m68k_read_bus_8(address)); + } + else + { + /* Read data from Z bus */ + switch(address & 0x6000) + { + case 0x0000: /* RAM */ + case 0x2000: + return (zram[(address & 0x1FFF)]); + + case 0x4000: /* YM2612 */ + return (fm_read(address & 3)); + + case 0x6000: /* Unused */ + switch(address & 0xFF00) + { + case 0x7F00: /* VDP */ + m68k_lockup_r_8(address); + + default: /* Unused */ + return (0xFF); + } + break; + } + } + } + else + { + switch((address >> 8) & 0xFF) + { + case 0x00: /* I/O CHIP */ + if(address <= 0xA1001F) + { + return (gen_io_r((address >> 1) & 0x0F)); + } + else + { + return (m68k_read_bus_8(address)); + } + break; + + case 0x10: /* MEMORY MODE */ + return (m68k_read_bus_8(address)); + + case 0x11: /* BUSACK */ + if((address & 1) == 0) + { + return (gen_busack_r() | (m68k_read_bus_8(address) & 0xFE)); + } + else + return (m68k_read_bus_8(address)); + + case 0x12: /* RESET */ + return (m68k_read_bus_8(address)); + + case 0x13: /* TIME */ + return (m68k_read_bus_8(address)); + + case 0x20: /* UNKNOWN */ + return (m68k_read_bus_8(address)); + + case 0x30: /* UNKNOWN */ + return (m68k_read_bus_8(address)); + + default: /* Unused */ + return (m68k_lockup_r_8(address)); + } + } + break; + + case 6: /* VDP */ + if((address & 0xE700E0) == 0xC00000) + { + switch(address & 0x1F) + { + case 0x00: /* DATA */ + case 0x02: + return (vdp_data_r() >> 8); + + case 0x01: /* DATA */ + case 0x03: + return (vdp_data_r() & 0xFF); + + case 0x04: /* CTRL */ + case 0x06: + return ((m68k_read_bus_8(address) & 0xFC) | (vdp_ctrl_r() >> 8)); + + case 0x05: /* CTRL */ + case 0x07: + return (vdp_ctrl_r() & 0xFF); + + case 0x08: /* HVC */ + case 0x0A: + case 0x0C: + case 0x0E: + return (vdp_hvc_r() >> 8); + + case 0x09: /* HVC */ + case 0x0B: + case 0x0D: + case 0x0F: + return (vdp_hvc_r() & 0xFF); + + case 0x10: /* PSG */ + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + return (m68k_lockup_r_8(address)); + + case 0x18: /* Unused */ + case 0x19: + case 0x1A: + case 0x1B: + case 0x1C: + case 0x1D: + case 0x1E: + case 0x1F: + return (m68k_read_bus_8(address)); + } + } + else + { + /* Unused */ + return (m68k_lockup_r_8(address)); + } + break; + + case 2: /* Unused */ + case 3: + return (m68k_read_bus_8(address)); + + case 4: /* Unused */ + return (m68k_lockup_r_8(address)); + } + + return -1; +} + + +unsigned int m68k_read_memory_16(unsigned int address) +{ + switch((address >> 21) & 7) + { + + case 0: /* ROM */ + case 1: + return readw_swap_rom(address); + + case 7: /* RAM */ + return READ_WORD(work_ram, address & 0xFFFF); + + case 5: /* Z80 & I/O */ + if(address <= 0xA0FFFF) + { + if(zbusack == 1) + { + return (m68k_read_bus_16(address)); + } + else + { + uint8 temp; + + switch(address & 0x6000) + { + case 0x0000: /* RAM */ + case 0x2000: + temp = zram[address & 0x1FFF]; + return (temp << 8 | temp); + + case 0x4000: /* YM2612 */ + temp = fm_read(address & 3); + return (temp << 8 | temp); + + case 0x6000: + switch(address & 0xFF00) + { + case 0x7F00: /* VDP */ + m68k_lockup_r_16(address); + + default: /* Unused */ + return (0xFFFF); + } + break; + } + } + } + else + { + if(address <= 0xA1001F) + { + uint8 temp = gen_io_r((address >> 1) & 0x0F); + return (temp << 8 | temp); + } + else + { + switch((address >> 8) & 0xFF) + { + case 0x10: /* MEMORY MODE */ + return (m68k_read_bus_16(address)); + + case 0x11: /* BUSACK */ + return ((m68k_read_bus_16(address) & 0xFEFF) | (gen_busack_r() << 8)); + + case 0x12: /* RESET */ + return (m68k_read_bus_16(address)); + + case 0x13: /* TIME */ + return (m68k_read_bus_16(address)); + + case 0x20: /* UNKNOWN */ + return (m68k_read_bus_16(address)); + + case 0x30: /* UNKNOWN */ + return (m68k_read_bus_16(address)); + + default: /* Unused */ + return (m68k_lockup_r_16(address)); + } + } + } + break; + + case 6: + if((address & 0xE700E0) == 0xC00000) + { + switch(address & 0x1F) + { + case 0x00: /* DATA */ + case 0x02: + return (vdp_data_r()); + + case 0x04: /* CTRL */ + case 0x06: + return (vdp_ctrl_r() | (m68k_read_bus_16(address) & 0xFC00)); + + case 0x08: /* HVC */ + case 0x0A: + case 0x0C: + case 0x0E: + return (vdp_hvc_r()); + + case 0x10: /* PSG */ + case 0x12: + case 0x14: + case 0x16: + return (m68k_lockup_r_16(address)); + + case 0x18: /* Unused */ + case 0x1A: + case 0x1C: + case 0x1E: + return (m68k_read_bus_16(address)); + } + } + else + { + return (m68k_lockup_r_16(address)); + } + break; + + case 2: + case 3: + return (m68k_read_bus_16(address)); + + case 4: + return (m68k_lockup_r_16(address)); + } + + return (0xA5A5); +} + + +unsigned int m68k_read_memory_32(unsigned int address) +{ + /* Split into 2 reads */ + return (m68k_read_memory_16(address + 0) << 16 | m68k_read_memory_16(address + 2)); +} + + +void m68k_write_memory_8(unsigned int address, unsigned int value) +{ + switch((address >> 21) & 7) + { + case 7: + WRITE_BYTE(work_ram, address & 0xFFFF, value); + return; + + case 6: + if((address & 0xE700E0) == 0xC00000) + { + switch(address & 0x1F) + { + case 0x00: /* DATA */ + case 0x01: + case 0x02: + case 0x03: + vdp_data_w(value << 8 | value); + return; + + case 0x04: /* CTRL */ + case 0x05: + case 0x06: + case 0x07: + vdp_ctrl_w(value << 8 | value); + return; + + case 0x08: /* HVC */ + case 0x09: + case 0x0A: + case 0x0B: + case 0x0C: + case 0x0D: + case 0x0E: + case 0x0F: + m68k_lockup_w_8(address, value); + return; + + case 0x10: /* PSG */ + case 0x12: + case 0x14: + case 0x16: + m68k_unused_8_w(address, value); + return; + + case 0x11: /* PSG */ + case 0x13: + case 0x15: + case 0x17: + psg_write(value); + return; + + case 0x18: /* Unused */ + case 0x19: + case 0x1A: + case 0x1B: + case 0x1C: + case 0x1D: + case 0x1E: + case 0x1F: + m68k_unused_8_w(address, value); + return; + } + } + else + { + m68k_lockup_w_8(address, value); + return; + } + + case 5: + if(address <= 0xA0FFFF) + { + if(zbusack == 1) + { + m68k_unused_8_w(address, value); + return; + } + else + { + switch(address & 0x6000) + { + case 0x0000: + case 0x2000: + zram[(address & 0x1FFF)] = value; + return; + + case 0x4000: + fm_write(address & 3, value); + return; + + case 0x6000: + switch(address & 0xFF00) + { + case 0x6000: /* BANK */ + gen_bank_w(value & 1); + return; + + case 0x7F00: /* VDP */ + m68k_lockup_w_8(address, value); + return; + + default: /* Unused */ + m68k_unused_8_w(address, value); + return; + } + break; + } + } + } + else + { + if(address <= 0xA1001F) + { + /* I/O chip only gets /LWR */ + if(address & 1) + gen_io_w((address >> 1) & 0x0F, value); + return; + } + else + { + /* Bus control chip registers */ + switch((address >> 8) & 0xFF) + { + case 0x10: /* MEMORY MODE */ + m68k_unused_8_w(address, value); + return; + + case 0x11: /* BUSREQ */ + if((address & 1) == 0) + { + gen_busreq_w(value & 1); + } + else + { + m68k_unused_8_w(address, value); + } + return; + + case 0x12: /* RESET */ + gen_reset_w(value & 1); + return; + + case 0x13: /* TIME */ + m68k_unused_8_w(address, value); + return; + + case 0x20: /* UNKNOWN */ + m68k_unused_8_w(address, value); + return; + + case 0x30: /* UNKNOWN */ + m68k_unused_8_w(address, value); + return; + + default: /* Unused */ + m68k_lockup_w_8(address, value); + return; + } + } + } + break; + + + case 0: /* ROM */ + case 1: /* ROM */ + m68k_unused_8_w(address, value); + return; + + case 2: /* Unused */ + case 3: + m68k_unused_8_w(address, value); + return; + + case 4: /* Unused */ + m68k_lockup_w_8(address, value); + return; + } + +} + + + + +void m68k_write_memory_16(unsigned int address, unsigned int value) +{ + switch((address >> 21) & 7) + { + case 0: /* ROM */ + case 1: /* ROM */ + m68k_unused_16_w(address, value); + return; + + case 2: /* Unused */ + case 3: + m68k_unused_16_w(address, value); + return; + + case 4: /* Unused */ + m68k_lockup_w_16(address, value); + return; + + case 5: /* Z80 area, I/O chip, miscellaneous. */ + if(address <= 0xA0FFFF) + { + /* Writes are ignored when the Z80 hogs the Z-bus */ + if(zbusack == 1) { + m68k_unused_8_w(address, value); + return; + } + + /* Write into Z80 address space */ + switch(address & 0x6000) + { + case 0x0000: /* Work RAM */ + case 0x2000: /* Work RAM */ + zram[(address & 0x1FFF)] = (value >> 8) & 0xFF; + return; + + case 0x4000: /* YM2612 */ + fm_write(address & 3, (value >> 8) & 0xFF); + return; + + case 0x6000: /* Bank register and VDP */ + switch(address & 0x7F00) + { + case 0x6000: /* Bank register */ + gen_bank_w((value >> 8) & 1); + return; + + case 0x7F00: /* VDP registers */ + m68k_lockup_w_16(address, value); + return; + + default: /* Unused */ + m68k_unused_8_w(address, value); + return; + } + break; + } + } + else + { + /* I/O chip */ + if(address <= 0xA1001F) + { + gen_io_w((address >> 1) & 0x0F, value & 0x00FF); + return; + } + else + { + /* Bus control chip registers */ + switch((address >> 8) & 0xFF) + { + case 0x10: /* MEMORY MODE */ + m68k_unused_16_w(address, value); + return; + + case 0x11: /* BUSREQ */ + gen_busreq_w((value >> 8) & 1); + return; + + case 0x12: /* RESET */ + gen_reset_w((value >> 8) & 1); + return; + + case 0x13: /* TIME */ + m68k_unused_16_w(address, value); + return; + + case 0x20: /* UNKNOWN */ + m68k_unused_16_w(address, value); + return; + + case 0x30: /* UNKNOWN */ + m68k_unused_16_w(address, value); + return; + + default: /* Unused */ + m68k_lockup_w_16(address, value); + return; + } + } + } + break; + + case 6: /* VDP */ + if((address & 0xE700E0) == 0xC00000) + { + switch(address & 0x1C) + { + case 0x00: /* DATA */ + vdp_data_w(value); + return; + + case 0x04: /* CTRL */ + vdp_ctrl_w(value); + return; + + case 0x08: /* HV counter */ + case 0x0C: /* HV counter */ + m68k_lockup_w_16(address, value); + return; + + case 0x10: /* PSG */ + case 0x14: /* PSG */ + psg_write(value & 0xFF); + return; + + case 0x18: /* Unused */ + case 0x1C: /* Unused */ + m68k_unused_8_w(address, value); + return; + } + } + else + { + /* Invalid address */ + m68k_lockup_w_16(address, value); + } + break; + + case 7: /* Work RAM */ + WRITE_WORD(work_ram, address & 0xFFFF, value); + return; + } +} + + +void m68k_write_memory_32(unsigned int address, unsigned int value) +{ + /* Split into 2 writes */ + m68k_write_memory_16(address, (value >> 16) & 0xFFFF); + m68k_write_memory_16(address + 2, value & 0xFFFF); +} + diff --git a/MCUME_teensy/teensygen/mem68k.h b/MCUME_teensy/teensygen/mem68k.h new file mode 100644 index 0000000..e9c54bd --- /dev/null +++ b/MCUME_teensy/teensygen/mem68k.h @@ -0,0 +1,15 @@ + +#ifndef _MEM68K_H_ +#define _MEM68K_H_ + +/* Function prototypes */ +unsigned int m68k_read_bus_8(unsigned int address); +unsigned int m68k_read_bus_16(unsigned int address); +void m68k_unused_w(unsigned int address, unsigned int value); + +void m68k_lockup_w_8(unsigned int address, unsigned int value); +void m68k_lockup_w_16(unsigned int address, unsigned int value); +unsigned int m68k_lockup_r_8(unsigned int address); +unsigned int m68k_lockup_r_16(unsigned int address); + +#endif /* _MEM68K_H_ */ diff --git a/MCUME_teensy/teensygen/membnk.c b/MCUME_teensy/teensygen/membnk.c new file mode 100644 index 0000000..f056f57 --- /dev/null +++ b/MCUME_teensy/teensygen/membnk.c @@ -0,0 +1,327 @@ +/* + membnk.c -- + Memory handlers Z80 access to the banked V-bus address space. +*/ + +#include "shared.h" + + +void z80_write_banked_memory(unsigned int address, unsigned int data) +{ + switch((address >> 21) & 7) + { + case 0: /* Cartridge ROM */ + case 1: + z80bank_unused_w(address, data); + return; + + case 2: /* Unused */ + case 3: + z80bank_unused_w(address, data); + return; + + case 4: /* Unused (lockup) */ + z80bank_lockup_w(address, data); + return; + + case 5: /* Z80, I/O chip, etc. */ + if(address <= 0xA0FFFF) + { + z80bank_lockup_w(address, data); + return; + } + else + { + switch((address >> 8) & 0xFF) + { + case 0x00: /* I/O chip */ + if(address <= 0xA1001F) + gen_io_w((address >> 1) & 0x0F, data); + else + z80bank_unused_w(address, data); + return; + + case 0x10: /* DRAM refresh */ + z80bank_unused_w(address, data); + return; + + case 0x11: /* /BUSREQ */ + if(address & 1) + z80bank_unused_w(address, data); + else + gen_busreq_w(data & 1); + return; + + case 0x12: /* /RESET (w) */ + if(address & 1) + z80bank_unused_w(address, data); + else + gen_reset_w(data & 1); + return; + + case 0x13: /* /TIME region */ + z80bank_unused_w(address, data); + return; + + case 0x20: /* ? */ + z80bank_unused_w(address, data); + return; + + case 0x30: /* ? */ + z80bank_unused_w(address, data); + return; + + default: /* Invalid */ + z80bank_lockup_w(address, data); + return; + } + } + return; + + case 6: /* VDP */ + z80bank_vdp_w(address, data); + return; + + case 7: /* Work RAM */ + WRITE_BYTE(work_ram, address & 0xFFFF, data); + return; + } +} + + +int z80_read_banked_memory(unsigned int address) +{ + switch((address >> 21) & 7) + { + case 0: /* Cartridge ROM */ + case 1: + return readb_swap_rom(address); + + case 2: /* Unused */ + case 3: + return z80bank_unused_r(address); + + case 4: /* Unused (lockup) */ + return z80bank_lockup_r(address); + + case 5: /* Z80, I/O chip, etc.*/ + if(address <= 0xA0FFFF) + { + return z80bank_lockup_r(address); + } + else + { + switch((address >> 8) & 0xFF) + { + case 0x00: /* I/O chip */ + if(address <= 0xA1001F) + return gen_io_r((address >> 1) & 0x0F); + else + return z80bank_unused_r(address); + break; + + case 0x10: /* Unused */ + return z80bank_unused_r(address); + + case 0x11: /* /BUSACK from Z80 */ + /* The Z80 can't read this bit (it would be halted + when the bit was zero) so we always return '1'. */ + return 0xFF; + + case 0x12: /* Unused */ + return z80bank_unused_r(address); + + case 0x13: /* /TIME region */ + return z80bank_unused_r(address); + + case 0x20: /* Unused */ + return z80bank_unused_r(address); + + case 0x30: /* Unused */ + return z80bank_unused_r(address); + + default: /* Lockup */ + return z80bank_lockup_r(address); + } + } + break; + + case 6: /* VDP */ + return z80bank_vdp_r(address); + + case 7: /* Work RAM - can't be read on some Genesis models (!) */ + return 0xFF; + } + + return (-1); +} + + +void z80bank_vdp_w(int address, int data) +{ +// if((address & 0xE700E0) == 0xC00000) + if((address & 0xE700E0) == 0xC0000) + { + switch(address & 0x1F) + { + case 0x00: /* Data port */ + case 0x01: + case 0x02: + case 0x03: + vdp_data_w(data << 8 | data); + return; + + case 0x04: /* Control port */ + case 0x05: + case 0x06: + case 0x07: + vdp_ctrl_w(data << 8 | data); + return; + + case 0x08: /* Lockup (HVC) */ + case 0x09: + case 0x0A: + case 0x0B: + case 0x0C: + case 0x0D: + case 0x0E: + case 0x0F: + z80bank_lockup_w(address, data); + return; + + case 0x10: /* Unused */ + case 0x12: + case 0x14: + case 0x16: + z80bank_unused_w(address, data); + return; + + case 0x11: /* PSG */ + case 0x13: + case 0x15: + case 0x17: + psg_write(data); + return; + + case 0x18: /* Unused */ + case 0x19: + case 0x1A: + case 0x1B: + z80bank_unused_w(address, data); + return; + + case 0x1C: /* Test register */ + case 0x1D: + case 0x1E: + case 0x1F: + vdp_test_w(data << 8 | data); + return; + } + } + else + { + /* Invalid VDP address */ + z80bank_lockup_w(address, data); + return; + } +} + + +int z80bank_vdp_r(int address) +{ +// if((address & 0xE700E0) == 0xC00000) + if((address & 0xE700E0) == 0xC0000) + { + switch(address & 0x1F) + { + case 0x00: /* Data */ + case 0x02: + return (vdp_data_r() >> 8) & 0xFF; + + case 0x01: /* Data */ + case 0x03: + return vdp_data_r() & 0xFF; + + case 0x04: /* Control */ + case 0x06: + return (0xFC | (vdp_ctrl_r() >> 8)) & 0xFF; + + case 0x05: /* Control */ + case 0x07: + return vdp_ctrl_r() & 0xFF; + + case 0x08: /* HVC */ + case 0x0A: + case 0x0C: + case 0x0E: + return (vdp_hvc_r() >> 8) & 0xFF; + + case 0x09: /* HVC */ + case 0x0B: + case 0x0D: + case 0x0F: + return vdp_hvc_r() & 0xFF; + + case 0x10: /* Lockup */ + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + return z80bank_lockup_r(address); + + case 0x18: /* Unused */ + case 0x19: + case 0x1A: + case 0x1B: + case 0x1C: + case 0x1D: + case 0x1E: + case 0x1F: + return (z80bank_unused_r(address) | 0xFF); + } + } + else + { + /* Invalid VDP address */ + return z80bank_lockup_r(address); + } + + return 0xFF; +} + + + + +/* + Handlers for access to unused addresses and those which make the + machine lock up. +*/ +void z80bank_unused_w(int address, int data) +{ + error("Z80 bank unused write %06X = %02X (%04X)\n", address, data, z80_get_reg(Z80_PC)); +} + +int z80bank_unused_r(int address) +{ + error("Z80 bank unused read %06X (%04X)\n", address, z80_get_reg(Z80_PC)); + return (address & 1) ? 0x00 : 0xFF; +} + +void z80bank_lockup_w(int address, int data) +{ + error("Z80 bank lockup write %06X = %02X (%04X)\n", address, data, z80_get_reg(Z80_PC)); + gen_running = 0; + z80_end_timeslice(); +} + +int z80bank_lockup_r(int address) +{ + error("Z80 bank lockup read %06X (%04X)\n", address, z80_get_reg(Z80_PC)); + gen_running = 0; + z80_end_timeslice(); + return 0xFF; +} + diff --git a/MCUME_teensy/teensygen/membnk.h b/MCUME_teensy/teensygen/membnk.h new file mode 100644 index 0000000..1afc9b6 --- /dev/null +++ b/MCUME_teensy/teensygen/membnk.h @@ -0,0 +1,17 @@ + +#ifndef _MEMBNK_H_ +#define _MEMBNK_H_ + +/* Function prototypes */ +void z80_write_banked_memory(unsigned int address, unsigned int data); +int z80_read_banked_memory(unsigned int address); + +void z80bank_vdp_w(int address, int data); +int z80bank_vdp_r(int address); + +void z80bank_unused_w(int address, int data); +int z80bank_unused_r(int address); +void z80bank_lockup_w(int address, int data); +int z80bank_lockup_r(int address); + +#endif /* _MEMBNK_H_ */ diff --git a/MCUME_teensy/teensygen/memory.c b/MCUME_teensy/teensygen/memory.c new file mode 100644 index 0000000..9b69047 --- /dev/null +++ b/MCUME_teensy/teensygen/memory.c @@ -0,0 +1,47 @@ +#include "shared.h" + + +//uint8 lwork_ram[WORK_RAM_SIZE]; /* 68K work RAM */ +//uint8 lzram[Z_RAM_SIZE]; /* Z80 work RAM */ + +//uint8 lvram[VRAM_SIZE]; +uint8 lbg_name_dirty[BGNAMEDIRTY_SIZE]; +uint16 lbg_name_list[BGNAME_SIZE]; +//uint8 lbg_pattern_cache[BGPATTERN_CACH_SIZE]; + +uint8 * vram;// = &lvram[0]; +uint8 * bg_name_dirty = &lbg_name_dirty[0]; +uint16 * bg_name_list = &lbg_name_list[0]; +uint8 * bg_pattern_cache; // = &lbg_pattern_cache[0]; + + +uint8 * work_ram; // = &lwork_ram[0]; +uint8 * zram; // = &lzram[0]; + + + +void mem_init(void) { + bg_pattern_cache = emu_Malloc(BGPATTERN_CACH_SIZE); + vram = emu_Malloc(VRAM_SIZE); + work_ram = emu_Malloc(WORK_RAM_SIZE); + zram = emu_Malloc(Z_RAM_SIZE); + //bg_pattern_cache = emu_Malloc(BGPATTERN_CACH_SIZE+1)&0xFFFFFFFE; + //vram = emu_Malloc(VRAM_SIZE+1)&0xFFFFFFFE; + //work_ram = emu_Malloc(WORK_RAM_SIZE+1)&0xFFFFFFFE; + //zram = emu_Malloc(Z_RAM_SIZE+1)&0xFFFFFFFE; +} + + +int mem_test(void) { +// for (int i=0x40000;i 0) { + write_rom(dst++, read_rom(src++)); + size--; + } +} diff --git a/MCUME_teensy/teensygen/memory.h b/MCUME_teensy/teensygen/memory.h new file mode 100644 index 0000000..4247bac --- /dev/null +++ b/MCUME_teensy/teensygen/memory.h @@ -0,0 +1,35 @@ +#ifndef _MEMORY_H_ +#define _MEMORY_H_ + +#include "shared.h" + +#define WORK_RAM_SIZE 0x10000 +#define Z_RAM_SIZE 0x2000 + +#define VRAM_SIZE 0x10000 +#define BGNAMEDIRTY_SIZE 0x800 +#define BGNAME_SIZE 0x800 +#define BGPATTERN_CACH_SIZE 0x40000 + + +//extern uint8 * cart_rom; +extern uint8 * work_ram; /* 68K work RAM */ +extern uint8 * zram; /* Z80 work RAM */ + +extern uint8 * vram; +extern uint8 * bg_name_dirty; +extern uint16 * bg_name_list; +extern uint8 * bg_pattern_cache; + + +extern void mem_init(void); +extern int mem_test(void); +extern uint8 rom_version(void); +extern uint8 readb_rom(int address); +extern uint8 readb_swap_rom(int address); +extern uint16 readw_swap_rom(int address); +extern void write_rom(int address, uint8 val); + +extern void memcpy_rom(int dst, int src, int size); + +#endif diff --git a/MCUME_teensy/teensygen/memvdp.c b/MCUME_teensy/teensygen/memvdp.c new file mode 100644 index 0000000..f8d2b3b --- /dev/null +++ b/MCUME_teensy/teensygen/memvdp.c @@ -0,0 +1,54 @@ +/* + memvdp.c -- + Memory handlers for when the VDP reads the V-bus during DMA. +*/ + +#include "shared.h" + +unsigned int vdp_dma_r(unsigned int address) +{ + switch((address >> 21) & 7) + { + case 0: /* Cartridge ROM */ + case 1: + return readw_swap_rom(address); + + case 2: /* Unused */ + case 3: + return 0xFF00; + + case 4: /* Work RAM */ + case 6: + case 7: + return READ_WORD(work_ram, address & 0xFFFF); + + case 5: /* Z80 area and I/O chip */ + + /* Z80 area always returns $FFFF */ + if(address <= 0xA0FFFF) + { + /* Return $FFFF only when the Z80 isn't hogging the Z-bus. + (e.g. Z80 isn't reset and 68000 has the bus) */ + return (zbusack == 0) + ? 0xFFFF + : READ_WORD(work_ram, address & 0xFFFF); + } + else + + /* The I/O chip and work RAM try to drive the data bus which + results in both values being combined in random ways when read. + We return the I/O chip values which seem to have precedence, */ + if(address <= 0xA1001F) + { + uint8 temp = gen_io_r((address >> 1) & 0x0F); + return (temp << 8 | temp); + } + else + + /* All remaining locations access work RAM */ + return READ_WORD(work_ram, address & 0xFFFF); + } + + return -1; +} + diff --git a/MCUME_teensy/teensygen/memvdp.h b/MCUME_teensy/teensygen/memvdp.h new file mode 100644 index 0000000..3e784b9 --- /dev/null +++ b/MCUME_teensy/teensygen/memvdp.h @@ -0,0 +1,8 @@ + +#ifndef _MEMVDP_H_ +#define _MEMVDP_H_ + +/* Function prototypes */ +unsigned int vdp_dma_r(unsigned int address); + +#endif /* _MEMVDP_H_ */ diff --git a/MCUME_teensy/teensygen/memz80.c b/MCUME_teensy/teensygen/memz80.c new file mode 100644 index 0000000..34abfc9 --- /dev/null +++ b/MCUME_teensy/teensygen/memz80.c @@ -0,0 +1,250 @@ +/* + memz80.c -- + Memory handlers for Z80 memory and port access, and the Z80 to + VDP interface. +*/ + +#define LOG_PORT 0 /* 1= Log Z80 I/O port accesses */ + +#include "shared.h" + + +unsigned int cpu_readmem16(unsigned int address) +{ + switch((address >> 13) & 7) + { + case 0: /* Work RAM */ + case 1: + return zram[address & 0x1FFF]; + + case 2: /* YM2612 */ + return fm_read(address & 3); + + case 3: /* VDP */ + if((address & 0xFF00) == 0x7F00) + return z80_vdp_r(address); + return 0xFF; + + default: /* V-bus bank */ + return z80_read_banked_memory(zbank | (address & 0x7FFF)); + } + + return 0xFF; +} + + +void cpu_writemem16(unsigned int address, unsigned int data) +{ + switch((address >> 13) & 7) + { + case 0: /* Work RAM */ + case 1: + zram[address & 0x1FFF] = data; + return; + + case 2: /* YM2612 */ + fm_write(address & 3, data); + return; + + case 3: /* Bank register and VDP */ + switch(address & 0xFF00) + { + case 0x6000: + gen_bank_w(data & 1); + return; + + case 0x7F00: + z80_vdp_w(address, data); + return; + + default: + z80_unused_w(address, data); + return; + } + return; + + default: /* V-bus bank */ + z80_write_banked_memory(zbank | (address & 0x7FFF), data); + return; + } +} + + +int z80_vdp_r(int address) +{ + switch(address & 0xFF) + { + case 0x00: /* VDP data port */ + case 0x02: + return (vdp_data_r() >> 8) & 0xFF; + + case 0x01: /* VDP data port */ + case 0x03: + return (vdp_data_r() & 0xFF); + + case 0x04: /* VDP control port */ + case 0x06: + return (0xFF | ((vdp_ctrl_r() >> 8) & 3)); + + case 0x05: /* VDP control port */ + case 0x07: + return (vdp_ctrl_r() & 0xFF); + + case 0x08: /* HV counter */ + case 0x0A: + case 0x0C: + case 0x0E: + return (vdp_hvc_r() >> 8) & 0xFF; + + case 0x09: /* HV counter */ + case 0x0B: + case 0x0D: + case 0x0F: + return (vdp_hvc_r() & 0xFF); + + case 0x10: /* Unused (PSG) */ + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + return z80_lockup_r(address); + + case 0x18: /* Unused */ + case 0x19: + case 0x1A: + case 0x1B: + return z80_unused_r(address); + + case 0x1C: /* Unused (test register) */ + case 0x1D: + case 0x1E: + case 0x1F: + return z80_unused_r(address); + + default: /* Invalid VDP addresses */ + return z80_lockup_r(address); + } + + return 0xFF; +} + + +void z80_vdp_w(int address, int data) +{ + switch(address & 0xFF) + { + case 0x00: /* VDP data port */ + case 0x01: + case 0x02: + case 0x03: + vdp_data_w(data << 8 | data); + return; + + case 0x04: /* VDP control port */ + case 0x05: + case 0x06: + case 0x07: + vdp_ctrl_w(data << 8 | data); + return; + + case 0x08: /* Unused (HV counter) */ + case 0x09: + case 0x0A: + case 0x0B: + case 0x0C: + case 0x0D: + case 0x0E: + case 0x0F: + z80_lockup_w(address, data); + return; + + case 0x11: /* PSG */ + case 0x13: + case 0x15: + case 0x17: + psg_write(data); + return; + + case 0x10: /* Unused */ + case 0x12: + case 0x14: + case 0x16: + z80_unused_w(address, data); + + case 0x18: /* Unused */ + case 0x19: + case 0x1A: + case 0x1B: + z80_unused_w(address, data); + return; + + case 0x1C: /* Test register */ + case 0x1D: + case 0x1E: + case 0x1F: + vdp_test_w(data << 8 | data); + return; + + default: /* Invalid VDP addresses */ + z80_lockup_w(address, data); + return; + } +} + + +/* + Port handlers. Ports are unused when not in Mark III compatability mode. + + Games that access ports anyway: + - Thunder Force IV reads port $BF in it's interrupt handler. +*/ + +unsigned int cpu_readport16(unsigned int port) +{ +#if LOG_PORT + error("Z80 read port %04X (%04X)\n", port, z80_get_reg(Z80_PC)); +#endif + return 0xFF; +} + +void cpu_writeport16(unsigned int port, unsigned int data) +{ +#if LOG_PORT + error("Z80 write %02X to port %04X (%04X)\n", data, port, z80_get_reg(Z80_PC)); +#endif +} + + +/* + Handlers for access to unused addresses and those which make the + machine lock up. +*/ +void z80_unused_w(int address, int data) +{ + error("Z80 unused write %04X = %02X (%04X)\n", address, data, z80_get_reg(Z80_PC)); +} + +int z80_unused_r(int address) +{ + error("Z80 unused read %04X (%04X)\n", address, z80_get_reg(Z80_PC)); + return 0xFF; +} + +void z80_lockup_w(int address, int data) +{ + error("Z80 lockup write %04X = %02X (%04X)\n", address, data, z80_get_reg(Z80_PC)); + gen_running = 0; + z80_end_timeslice(); +} + +int z80_lockup_r(int address) +{ + error("Z80 lockup read %04X (%04X)\n", address, z80_get_reg(Z80_PC)); + gen_running = 0; + z80_end_timeslice(); + return 0xFF; +} + diff --git a/MCUME_teensy/teensygen/memz80.h b/MCUME_teensy/teensygen/memz80.h new file mode 100644 index 0000000..82b2139 --- /dev/null +++ b/MCUME_teensy/teensygen/memz80.h @@ -0,0 +1,17 @@ + +#ifndef _MEMZ80_H_ +#define _MEMZ80_H_ + +/* Function prototypes */ +unsigned int cpu_readmem16(unsigned int address); +void cpu_writemem16(unsigned int address, unsigned int data); +unsigned int cpu_readport16(unsigned int port); +void cpu_writeport16(unsigned int port, unsigned int data); +void z80_unused_w(int address, int data); +int z80_unused_r(int address); +void z80_lockup_w(int address, int data); +int z80_lockup_r(int address); +int z80_vdp_r(int address); +void z80_vdp_w(int address, int data); + +#endif /* _MEMZ80_H_ */ diff --git a/MCUME_teensy/teensygen/musashi34/m68k.h b/MCUME_teensy/teensygen/musashi34/m68k.h new file mode 100644 index 0000000..e2f0b27 --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68k.h @@ -0,0 +1,358 @@ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.4 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef M68K__HEADER +#define M68K__HEADER + + +/* ======================================================================== */ +/* ============================= CONFIGURATION ============================ */ +/* ======================================================================== */ + +/* Import the configuration for this build */ +#include "m68kconf.h" + + +/* ======================================================================== */ +/* ============================ GENERAL DEFINES =========================== */ + +/* ======================================================================== */ + +/* There are 7 levels of interrupt to the 68K. + * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). + */ +#define M68K_IRQ_NONE 0 +#define M68K_IRQ_1 1 +#define M68K_IRQ_2 2 +#define M68K_IRQ_3 3 +#define M68K_IRQ_4 4 +#define M68K_IRQ_5 5 +#define M68K_IRQ_6 6 +#define M68K_IRQ_7 7 + + +/* Special interrupt acknowledge values. + * Use these as special returns from the interrupt acknowledge callback + * (specified later in this header). + */ + +/* Causes an interrupt autovector (0x18 + interrupt level) to be taken. + * This happens in a real 68K if VPA or AVEC is asserted during an interrupt + * acknowledge cycle instead of DTACK. + */ +#define M68K_INT_ACK_AUTOVECTOR 0xffffffff + +/* Causes the spurious interrupt vector (0x18) to be taken + * This happens in a real 68K if BERR is asserted during the interrupt + * acknowledge cycle (i.e. no devices responded to the acknowledge). + */ +#define M68K_INT_ACK_SPURIOUS 0xfffffffe + + +/* CPU types for use in m68k_set_cpu_type() */ +enum +{ + M68K_CPU_TYPE_INVALID, + M68K_CPU_TYPE_68000, + M68K_CPU_TYPE_68010, + M68K_CPU_TYPE_68EC020, + M68K_CPU_TYPE_68020, + M68K_CPU_TYPE_68030, /* Supported by disassembler ONLY */ + M68K_CPU_TYPE_68040 /* Supported by disassembler ONLY */ +}; + +/* Registers used by m68k_get_reg() and m68k_set_reg() */ +typedef enum +{ + /* Real registers */ + M68K_REG_D0, /* Data registers */ + M68K_REG_D1, + M68K_REG_D2, + M68K_REG_D3, + M68K_REG_D4, + M68K_REG_D5, + M68K_REG_D6, + M68K_REG_D7, + M68K_REG_A0, /* Address registers */ + M68K_REG_A1, + M68K_REG_A2, + M68K_REG_A3, + M68K_REG_A4, + M68K_REG_A5, + M68K_REG_A6, + M68K_REG_A7, + M68K_REG_PC, /* Program Counter */ + M68K_REG_SR, /* Status Register */ + M68K_REG_SP, /* The current Stack Pointer (located in A7) */ + M68K_REG_USP, /* User Stack Pointer */ + M68K_REG_ISP, /* Interrupt Stack Pointer */ + M68K_REG_MSP, /* Master Stack Pointer */ + M68K_REG_SFC, /* Source Function Code */ + M68K_REG_DFC, /* Destination Function Code */ + M68K_REG_VBR, /* Vector Base Register */ + M68K_REG_CACR, /* Cache Control Register */ + M68K_REG_CAAR, /* Cache Address Register */ + + /* Assumed registers */ + /* These are cheat registers which emulate the 1-longword prefetch + * present in the 68000 and 68010. + */ + M68K_REG_PREF_ADDR, /* Last prefetch address */ + M68K_REG_PREF_DATA, /* Last prefetch data */ + + /* Convenience registers */ + M68K_REG_PPC, /* Previous value in the program counter */ + M68K_REG_IR, /* Instruction register */ + M68K_REG_CPU_TYPE /* Type of CPU being run */ +} m68k_register_t; + +/* ======================================================================== */ +/* ====================== FUNCTIONS CALLED BY THE CPU ===================== */ +/* ======================================================================== */ + +/* You will have to implement these functions */ + +/* read/write functions called by the CPU to access memory. + * while values used are 32 bits, only the appropriate number + * of bits are relevant (i.e. in write_memory_8, only the lower 8 bits + * of value should be written to memory). + * + * NOTE: I have separated the immediate and PC-relative memory fetches + * from the other memory fetches because some systems require + * differentiation between PROGRAM and DATA fetches (usually + * for security setups such as encryption). + * This separation can either be achieved by setting + * M68K_SEPARATE_READS in m68kconf.h and defining + * the read functions, or by setting M68K_EMULATE_FC and + * making a function code callback function. + * Using the callback offers better emulation coverage + * because you can also monitor whether the CPU is in SYSTEM or + * USER mode, but it is also slower. + */ + +/* Read from anywhere */ +unsigned int m68k_read_memory_8(unsigned int address); +unsigned int m68k_read_memory_16(unsigned int address); +unsigned int m68k_read_memory_32(unsigned int address); + +/* Read data immediately following the PC */ +unsigned int m68k_read_immediate_16(unsigned int address); +unsigned int m68k_read_immediate_32(unsigned int address); + +/* Read data relative to the PC */ +unsigned int m68k_read_pcrelative_8(unsigned int address); +unsigned int m68k_read_pcrelative_16(unsigned int address); +unsigned int m68k_read_pcrelative_32(unsigned int address); + +/* Memory access for the disassembler */ +unsigned int m68k_read_disassembler_8 (unsigned int address); +unsigned int m68k_read_disassembler_16 (unsigned int address); +unsigned int m68k_read_disassembler_32 (unsigned int address); + +/* Write to anywhere */ +void m68k_write_memory_8(unsigned int address, unsigned int value); +void m68k_write_memory_16(unsigned int address, unsigned int value); +void m68k_write_memory_32(unsigned int address, unsigned int value); + +/* Special call to simulate undocumented 68k behavior when move.l with a + * predecrement destination mode is executed. + * To simulate real 68k behavior, first write the high word to + * [address+2], and then write the low word to [address]. + * + * Enable this functionality with M68K_SIMULATE_PD_WRITES in m68kconf.h. + */ +void m68k_write_memory_32_pd(unsigned int address, unsigned int value); + + + +/* ======================================================================== */ +/* ============================== CALLBACKS =============================== */ +/* ======================================================================== */ + +/* These functions allow you to set callbacks to the host when specific events + * occur. Note that you must enable the corresponding value in m68kconf.h + * in order for these to do anything useful. + * Note: I have defined default callbacks which are used if you have enabled + * the corresponding #define in m68kconf.h but either haven't assigned a + * callback or have assigned a callback of NULL. + */ + +/* Set the callback for an interrupt acknowledge. + * You must enable M68K_EMULATE_INT_ACK in m68kconf.h. + * The CPU will call the callback with the interrupt level being acknowledged. + * The host program must return either a vector from 0x02-0xff, or one of the + * special interrupt acknowledge values specified earlier in this header. + * If this is not implemented, the CPU will always assume an autovectored + * interrupt, and will automatically clear the interrupt request when it + * services the interrupt. + * Default behavior: return M68K_INT_ACK_AUTOVECTOR. + */ +void m68k_set_int_ack_callback(int (*callback)(int int_level)); + + +/* Set the callback for a breakpoint acknowledge (68010+). + * You must enable M68K_EMULATE_BKPT_ACK in m68kconf.h. + * The CPU will call the callback with whatever was in the data field of the + * BKPT instruction for 68020+, or 0 for 68010. + * Default behavior: do nothing. + */ +void m68k_set_bkpt_ack_callback(void (*callback)(unsigned int data)); + + +/* Set the callback for the RESET instruction. + * You must enable M68K_EMULATE_RESET in m68kconf.h. + * The CPU calls this callback every time it encounters a RESET instruction. + * Default behavior: do nothing. + */ +void m68k_set_reset_instr_callback(void (*callback)(void)); + + +/* Set the callback for informing of a large PC change. + * You must enable M68K_MONITOR_PC in m68kconf.h. + * The CPU calls this callback with the new PC value every time the PC changes + * by a large value (currently set for changes by longwords). + * Default behavior: do nothing. + */ +void m68k_set_pc_changed_callback(void (*callback)(unsigned int new_pc)); + + +/* Set the callback for CPU function code changes. + * You must enable M68K_EMULATE_FC in m68kconf.h. + * The CPU calls this callback with the function code before every memory + * access to set the CPU's function code according to what kind of memory + * access it is (supervisor/user, program/data and such). + * Default behavior: do nothing. + */ +void m68k_set_fc_callback(void (*callback)(unsigned int new_fc)); + + +/* Set a callback for the instruction cycle of the CPU. + * You must enable M68K_INSTRUCTION_HOOK in m68kconf.h. + * The CPU calls this callback just before fetching the opcode in the + * instruction cycle. + * Default behavior: do nothing. + */ +void m68k_set_instr_hook_callback(void (*callback)(void)); + + + +/* ======================================================================== */ +/* ====================== FUNCTIONS TO ACCESS THE CPU ===================== */ +/* ======================================================================== */ + +/* Use this function to set the CPU type you want to emulate. + * Currently supported types are: M68K_CPU_TYPE_68000, M68K_CPU_TYPE_68010, + * M68K_CPU_TYPE_EC020, and M68K_CPU_TYPE_68020. + */ +void m68k_set_cpu_type(unsigned int cpu_type); + +/* Do whatever initialisations the core requires. Should be called + * at least once at init time. + */ +void m68k_init(void); + +/* Pulse the RESET pin on the CPU. + * You *MUST* reset the CPU at least once to initialize the emulation + * Note: If you didn't call m68k_set_cpu_type() before resetting + * the CPU for the first time, the CPU will be set to + * M68K_CPU_TYPE_68000. + */ +void m68k_pulse_reset(void); + +/* execute num_cycles worth of instructions. returns number of cycles used */ +int m68k_execute(int num_cycles); + +/* These functions let you read/write/modify the number of cycles left to run + * while m68k_execute() is running. + * These are useful if the 68k accesses a memory-mapped port on another device + * that requires immediate processing by another CPU. + */ +int m68k_cycles_run(void); /* Number of cycles run so far */ +int m68k_cycles_remaining(void); /* Number of cycles left */ +void m68k_modify_timeslice(int cycles); /* Modify cycles left */ +void m68k_end_timeslice(void); /* End timeslice now */ + +/* Set the IPL0-IPL2 pins on the CPU (IRQ). + * A transition from < 7 to 7 will cause a non-maskable interrupt (NMI). + * Setting IRQ to 0 will clear an interrupt request. + */ +void m68k_set_irq(unsigned int int_level); + + +/* Halt the CPU as if you pulsed the HALT pin. */ +void m68k_pulse_halt(void); + + +/* Context switching to allow multiple CPUs */ + +/* Get the size of the cpu context in bytes */ +unsigned int m68k_context_size(void); + +/* Get a cpu context */ +unsigned int m68k_get_context(void* dst); + +/* set the current cpu context */ +void m68k_set_context(void* dst); + +/* Register the CPU state information */ +void m68k_state_register(const char *type); + + +/* Peek at the internals of a CPU context. This can either be a context + * retrieved using m68k_get_context() or the currently running context. + * If context is NULL, the currently running CPU context will be used. + */ +unsigned int m68k_get_reg(void* context, m68k_register_t reg); + +/* Poke values into the internals of the currently running CPU context */ +void m68k_set_reg(m68k_register_t reg, unsigned int value); + +/* Check if an instruction is valid for the specified CPU type */ +unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type); + +/* Disassemble 1 instruction using the epecified CPU type at pc. Stores + * disassembly in str_buff and returns the size of the instruction in bytes. + */ +unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type); + + +/* ======================================================================== */ +/* ============================== MAME STUFF ============================== */ +/* ======================================================================== */ + +#if M68K_COMPILE_FOR_MAME == OPT_ON +#include "m68kmame.h" +#endif /* M68K_COMPILE_FOR_MAME */ + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68K__HEADER */ diff --git a/MCUME_teensy/teensygen/musashi34/m68kconf.h b/MCUME_teensy/teensygen/musashi34/m68kconf.h new file mode 100644 index 0000000..5f71c38 --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68kconf.h @@ -0,0 +1,189 @@ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.4 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + + +#ifndef M68KCONF__HEADER +#define M68KCONF__HEADER + + +/* Configuration switches. + * Use OPT_SPECIFY_HANDLER for configuration options that allow callbacks. + * OPT_SPECIFY_HANDLER causes the core to link directly to the function + * or macro you specify, rather than using callback functions whose pointer + * must be passed in using m68k_set_xxx_callback(). + */ +#define OPT_OFF 0 +#define OPT_ON 1 +#define OPT_SPECIFY_HANDLER 2 + + +/* ======================================================================== */ +/* ============================== MAME STUFF ============================== */ +/* ======================================================================== */ + +/* If you're compiling this for MAME, only change M68K_COMPILE_FOR_MAME + * to OPT_ON and use m68kmame.h to configure the 68k core. + */ +#ifndef M68K_COMPILE_FOR_MAME +#define M68K_COMPILE_FOR_MAME OPT_OFF +#endif /* M68K_COMPILE_FOR_MAME */ + + +#if M68K_COMPILE_FOR_MAME == OPT_OFF + + +/* ======================================================================== */ +/* ============================= CONFIGURATION ============================ */ +/* ======================================================================== */ + +/* Turn on if you want to use the following M68K variants */ +#define M68K_EMULATE_010 OPT_ON +#define M68K_EMULATE_EC020 OPT_ON +#define M68K_EMULATE_020 OPT_ON + + +/* If ON, the CPU will call m68k_read_immediate_xx() for immediate addressing + * and m68k_read_pcrelative_xx() for PC-relative addressing. + * If off, all read requests from the CPU will be redirected to m68k_read_xx() + */ +#define M68K_SEPARATE_READS OPT_OFF + + +/* If ON, the CPU will call m68k_write_32_pd() when it executes move.l with a + * predecrement destination EA mode instead of m68k_write_32(). + * To simulate real 68k behavior, m68k_write_32_pd() must first write the high + * word to [address+2], and then write the low word to [address]. + */ +#define M68K_SIMULATE_PD_WRITES OPT_OFF + +/* If ON, CPU will call the interrupt acknowledge callback when it services an + * interrupt. + * If off, all interrupts will be autovectored and all interrupt requests will + * auto-clear when the interrupt is serviced. + */ +#define M68K_EMULATE_INT_ACK OPT_SPECIFY_HANDLER +#define M68K_INT_ACK_CALLBACK(A) vdp_int_ack_callback(A) + + +/* If ON, CPU will call the breakpoint acknowledge callback when it encounters + * a breakpoint instruction and it is running a 68010+. + */ +#define M68K_EMULATE_BKPT_ACK OPT_OFF +#define M68K_BKPT_ACK_CALLBACK() your_bkpt_ack_handler_function() + + +/* If ON, the CPU will monitor the trace flags and take trace exceptions + */ +#define M68K_EMULATE_TRACE OPT_OFF + + +/* If ON, CPU will call the output reset callback when it encounters a reset + * instruction. + */ +#define M68K_EMULATE_RESET OPT_OFF +#define M68K_RESET_CALLBACK() your_reset_handler_function() + + +/* If ON, CPU will call the set fc callback on every memory access to + * differentiate between user/supervisor, program/data access like a real + * 68000 would. This should be enabled and the callback should be set if you + * want to properly emulate the m68010 or higher. (moves uses function codes + * to read/write data from different address spaces) + */ +#define M68K_EMULATE_FC OPT_OFF +#define M68K_SET_FC_CALLBACK(A) your_set_fc_handler_function(A) + + +/* If ON, CPU will call the pc changed callback when it changes the PC by a + * large value. This allows host programs to be nicer when it comes to + * fetching immediate data and instructions on a banked memory system. + */ +#define M68K_MONITOR_PC OPT_OFF +#define M68K_SET_PC_CALLBACK(A) your_pc_changed_handler_function(A) + + +/* If ON, CPU will call the instruction hook callback before every + * instruction. + */ +//#define M68K_INSTRUCTION_HOOK OPT_SPECIFY_HANDLER +#define M68K_INSTRUCTION_HOOK OPT_OFF +#define M68K_INSTRUCTION_CALLBACK() your_instruction_hook_function() + + +/* If ON, the CPU will emulate the 4-byte prefetch queue of a real 68000 */ +#define M68K_EMULATE_PREFETCH OPT_OFF + + +/* If ON, the CPU will generate address error exceptions if it tries to + * access a word or longword at an odd address. + * NOTE: This is only emulated properly for 68000 mode. + */ +#define M68K_EMULATE_ADDRESS_ERROR OPT_OFF + + +/* Turn ON to enable logging of illegal instruction calls. + * M68K_LOG_FILEHANDLE must be #defined to a stdio file stream. + * Turn on M68K_LOG_1010_1111 to log all 1010 and 1111 calls. + */ +#define M68K_LOG_ENABLE OPT_OFF +#define M68K_LOG_1010_1111 OPT_OFF +#define M68K_LOG_FILEHANDLE some_file_handle + + +/* ----------------------------- COMPATIBILITY ---------------------------- */ + +/* The following options set optimizations that violate the current ANSI + * standard, but will be compliant under the forthcoming C9X standard. + */ + + +/* If ON, the enulation core will use 64-bit integers to speed up some + * operations. +*/ +#define M68K_USE_64_BIT OPT_OFF + + +/* Set to your compiler's static inline keyword to enable it, or + * set it to blank to disable it. + * If you define INLINE in the makefile, it will override this value. + * NOTE: not enabling inline functions will SEVERELY slow down emulation. + */ +#ifndef INLINE +#define INLINE static __inline__ +#endif /* INLINE */ + +#endif /* M68K_COMPILE_FOR_MAME */ + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68KCONF__HEADER */ diff --git a/MCUME_teensy/teensygen/musashi34/m68kcpu.c b/MCUME_teensy/teensygen/musashi34/m68kcpu.c new file mode 100644 index 0000000..845fffd --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68kcpu.c @@ -0,0 +1,882 @@ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.4 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + +/* ======================================================================== */ +/* ================================= NOTES ================================ */ +/* ======================================================================== */ + + + +/* ======================================================================== */ +/* ================================ INCLUDES ============================== */ +/* ======================================================================== */ + +#include "m68kops.h" +#include "m68kcpu.h" + +/* ======================================================================== */ +/* ================================= DATA ================================= */ +/* ======================================================================== */ + +int m68ki_initial_cycles; +int m68ki_remaining_cycles = 0; /* Number of clocks remaining */ +uint m68ki_tracing = 0; +uint m68ki_address_space; + +#ifdef M68K_LOG_ENABLE +char* m68ki_cpu_names[9] = +{ + "Invalid CPU", + "M68000", + "M68010", + "Invalid CPU", + "M68EC020" + "Invalid CPU", + "Invalid CPU", + "Invalid CPU", + "M68020" +}; +#endif /* M68K_LOG_ENABLE */ + +/* The CPU core */ +m68ki_cpu_core m68ki_cpu = {0}; + +#if M68K_EMULATE_ADDRESS_ERROR +jmp_buf m68ki_address_error_trap; +#endif /* M68K_EMULATE_ADDRESS_ERROR */ + +uint m68ki_aerr_address; +uint m68ki_aerr_write_mode; +uint m68ki_aerr_fc; + +/* Used by shift & rotate instructions */ +const uint8 m68ki_shift_8_table[65] = +{ + 0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff +}; +const uint16 m68ki_shift_16_table[65] = +{ + 0x0000, 0x8000, 0xc000, 0xe000, 0xf000, 0xf800, 0xfc00, 0xfe00, 0xff00, + 0xff80, 0xffc0, 0xffe0, 0xfff0, 0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff +}; +const uint m68ki_shift_32_table[65] = +{ + 0x00000000, 0x80000000, 0xc0000000, 0xe0000000, 0xf0000000, 0xf8000000, + 0xfc000000, 0xfe000000, 0xff000000, 0xff800000, 0xffc00000, 0xffe00000, + 0xfff00000, 0xfff80000, 0xfffc0000, 0xfffe0000, 0xffff0000, 0xffff8000, + 0xffffc000, 0xffffe000, 0xfffff000, 0xfffff800, 0xfffffc00, 0xfffffe00, + 0xffffff00, 0xffffff80, 0xffffffc0, 0xffffffe0, 0xfffffff0, 0xfffffff8, + 0xfffffffc, 0xfffffffe, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff +}; + + +/* Number of clock cycles to use for exception processing. + * I used 4 for any vectors that are undocumented for processing times. + */ +uint8 m68ki_exception_cycle_table[3][256] = +{ + { /* 000 */ + 4, /* 0: Reset - Initial Stack Pointer */ + 4, /* 1: Reset - Initial Program Counter */ + 50, /* 2: Bus Error (unemulated) */ + 50, /* 3: Address Error (unemulated) */ + 34, /* 4: Illegal Instruction */ + 38, /* 5: Divide by Zero -- ASG: changed from 42 */ + 40, /* 6: CHK -- ASG: chanaged from 44 */ + 34, /* 7: TRAPV */ + 34, /* 8: Privilege Violation */ + 34, /* 9: Trace */ + 34, /* 10: 1010 */ + 34, /* 11: 1111 */ + 4, /* 12: RESERVED */ + 4, /* 13: Coprocessor Protocol Violation (unemulated) */ + 4, /* 14: Format Error */ + 44, /* 15: Uninitialized Interrupt */ + 4, /* 16: RESERVED */ + 4, /* 17: RESERVED */ + 4, /* 18: RESERVED */ + 4, /* 19: RESERVED */ + 4, /* 20: RESERVED */ + 4, /* 21: RESERVED */ + 4, /* 22: RESERVED */ + 4, /* 23: RESERVED */ + 44, /* 24: Spurious Interrupt */ + 44, /* 25: Level 1 Interrupt Autovector */ + 44, /* 26: Level 2 Interrupt Autovector */ + 44, /* 27: Level 3 Interrupt Autovector */ + 44, /* 28: Level 4 Interrupt Autovector */ + 44, /* 29: Level 5 Interrupt Autovector */ + 44, /* 30: Level 6 Interrupt Autovector */ + 44, /* 31: Level 7 Interrupt Autovector */ + 34, /* 32: TRAP #0 -- ASG: chanaged from 38 */ + 34, /* 33: TRAP #1 */ + 34, /* 34: TRAP #2 */ + 34, /* 35: TRAP #3 */ + 34, /* 36: TRAP #4 */ + 34, /* 37: TRAP #5 */ + 34, /* 38: TRAP #6 */ + 34, /* 39: TRAP #7 */ + 34, /* 40: TRAP #8 */ + 34, /* 41: TRAP #9 */ + 34, /* 42: TRAP #10 */ + 34, /* 43: TRAP #11 */ + 34, /* 44: TRAP #12 */ + 34, /* 45: TRAP #13 */ + 34, /* 46: TRAP #14 */ + 34, /* 47: TRAP #15 */ + 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */ + 4, /* 49: FP Inexact Result (unemulated) */ + 4, /* 50: FP Divide by Zero (unemulated) */ + 4, /* 51: FP Underflow (unemulated) */ + 4, /* 52: FP Operand Error (unemulated) */ + 4, /* 53: FP Overflow (unemulated) */ + 4, /* 54: FP Signaling NAN (unemulated) */ + 4, /* 55: FP Unimplemented Data Type (unemulated) */ + 4, /* 56: MMU Configuration Error (unemulated) */ + 4, /* 57: MMU Illegal Operation Error (unemulated) */ + 4, /* 58: MMU Access Level Violation Error (unemulated) */ + 4, /* 59: RESERVED */ + 4, /* 60: RESERVED */ + 4, /* 61: RESERVED */ + 4, /* 62: RESERVED */ + 4, /* 63: RESERVED */ + /* 64-255: User Defined */ + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 + }, + { /* 010 */ + 4, /* 0: Reset - Initial Stack Pointer */ + 4, /* 1: Reset - Initial Program Counter */ + 126, /* 2: Bus Error (unemulated) */ + 126, /* 3: Address Error (unemulated) */ + 38, /* 4: Illegal Instruction */ + 44, /* 5: Divide by Zero */ + 44, /* 6: CHK */ + 34, /* 7: TRAPV */ + 38, /* 8: Privilege Violation */ + 38, /* 9: Trace */ + 4, /* 10: 1010 */ + 4, /* 11: 1111 */ + 4, /* 12: RESERVED */ + 4, /* 13: Coprocessor Protocol Violation (unemulated) */ + 4, /* 14: Format Error */ + 44, /* 15: Uninitialized Interrupt */ + 4, /* 16: RESERVED */ + 4, /* 17: RESERVED */ + 4, /* 18: RESERVED */ + 4, /* 19: RESERVED */ + 4, /* 20: RESERVED */ + 4, /* 21: RESERVED */ + 4, /* 22: RESERVED */ + 4, /* 23: RESERVED */ + 46, /* 24: Spurious Interrupt */ + 46, /* 25: Level 1 Interrupt Autovector */ + 46, /* 26: Level 2 Interrupt Autovector */ + 46, /* 27: Level 3 Interrupt Autovector */ + 46, /* 28: Level 4 Interrupt Autovector */ + 46, /* 29: Level 5 Interrupt Autovector */ + 46, /* 30: Level 6 Interrupt Autovector */ + 46, /* 31: Level 7 Interrupt Autovector */ + 38, /* 32: TRAP #0 */ + 38, /* 33: TRAP #1 */ + 38, /* 34: TRAP #2 */ + 38, /* 35: TRAP #3 */ + 38, /* 36: TRAP #4 */ + 38, /* 37: TRAP #5 */ + 38, /* 38: TRAP #6 */ + 38, /* 39: TRAP #7 */ + 38, /* 40: TRAP #8 */ + 38, /* 41: TRAP #9 */ + 38, /* 42: TRAP #10 */ + 38, /* 43: TRAP #11 */ + 38, /* 44: TRAP #12 */ + 38, /* 45: TRAP #13 */ + 38, /* 46: TRAP #14 */ + 38, /* 47: TRAP #15 */ + 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */ + 4, /* 49: FP Inexact Result (unemulated) */ + 4, /* 50: FP Divide by Zero (unemulated) */ + 4, /* 51: FP Underflow (unemulated) */ + 4, /* 52: FP Operand Error (unemulated) */ + 4, /* 53: FP Overflow (unemulated) */ + 4, /* 54: FP Signaling NAN (unemulated) */ + 4, /* 55: FP Unimplemented Data Type (unemulated) */ + 4, /* 56: MMU Configuration Error (unemulated) */ + 4, /* 57: MMU Illegal Operation Error (unemulated) */ + 4, /* 58: MMU Access Level Violation Error (unemulated) */ + 4, /* 59: RESERVED */ + 4, /* 60: RESERVED */ + 4, /* 61: RESERVED */ + 4, /* 62: RESERVED */ + 4, /* 63: RESERVED */ + /* 64-255: User Defined */ + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 + }, + { /* 020 */ + 4, /* 0: Reset - Initial Stack Pointer */ + 4, /* 1: Reset - Initial Program Counter */ + 50, /* 2: Bus Error (unemulated) */ + 50, /* 3: Address Error (unemulated) */ + 20, /* 4: Illegal Instruction */ + 38, /* 5: Divide by Zero */ + 40, /* 6: CHK */ + 20, /* 7: TRAPV */ + 34, /* 8: Privilege Violation */ + 25, /* 9: Trace */ + 20, /* 10: 1010 */ + 20, /* 11: 1111 */ + 4, /* 12: RESERVED */ + 4, /* 13: Coprocessor Protocol Violation (unemulated) */ + 4, /* 14: Format Error */ + 30, /* 15: Uninitialized Interrupt */ + 4, /* 16: RESERVED */ + 4, /* 17: RESERVED */ + 4, /* 18: RESERVED */ + 4, /* 19: RESERVED */ + 4, /* 20: RESERVED */ + 4, /* 21: RESERVED */ + 4, /* 22: RESERVED */ + 4, /* 23: RESERVED */ + 30, /* 24: Spurious Interrupt */ + 30, /* 25: Level 1 Interrupt Autovector */ + 30, /* 26: Level 2 Interrupt Autovector */ + 30, /* 27: Level 3 Interrupt Autovector */ + 30, /* 28: Level 4 Interrupt Autovector */ + 30, /* 29: Level 5 Interrupt Autovector */ + 30, /* 30: Level 6 Interrupt Autovector */ + 30, /* 31: Level 7 Interrupt Autovector */ + 20, /* 32: TRAP #0 */ + 20, /* 33: TRAP #1 */ + 20, /* 34: TRAP #2 */ + 20, /* 35: TRAP #3 */ + 20, /* 36: TRAP #4 */ + 20, /* 37: TRAP #5 */ + 20, /* 38: TRAP #6 */ + 20, /* 39: TRAP #7 */ + 20, /* 40: TRAP #8 */ + 20, /* 41: TRAP #9 */ + 20, /* 42: TRAP #10 */ + 20, /* 43: TRAP #11 */ + 20, /* 44: TRAP #12 */ + 20, /* 45: TRAP #13 */ + 20, /* 46: TRAP #14 */ + 20, /* 47: TRAP #15 */ + 4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */ + 4, /* 49: FP Inexact Result (unemulated) */ + 4, /* 50: FP Divide by Zero (unemulated) */ + 4, /* 51: FP Underflow (unemulated) */ + 4, /* 52: FP Operand Error (unemulated) */ + 4, /* 53: FP Overflow (unemulated) */ + 4, /* 54: FP Signaling NAN (unemulated) */ + 4, /* 55: FP Unimplemented Data Type (unemulated) */ + 4, /* 56: MMU Configuration Error (unemulated) */ + 4, /* 57: MMU Illegal Operation Error (unemulated) */ + 4, /* 58: MMU Access Level Violation Error (unemulated) */ + 4, /* 59: RESERVED */ + 4, /* 60: RESERVED */ + 4, /* 61: RESERVED */ + 4, /* 62: RESERVED */ + 4, /* 63: RESERVED */ + /* 64-255: User Defined */ + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, + 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 + } +}; + +uint8 m68ki_ea_idx_cycle_table[64] = +{ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, /* ..01.000 no memory indirect, base NULL */ + 5, /* ..01..01 memory indirect, base NULL, outer NULL */ + 7, /* ..01..10 memory indirect, base NULL, outer 16 */ + 7, /* ..01..11 memory indirect, base NULL, outer 32 */ + 0, 5, 7, 7, 0, 5, 7, 7, 0, 5, 7, 7, + 2, /* ..10.000 no memory indirect, base 16 */ + 7, /* ..10..01 memory indirect, base 16, outer NULL */ + 9, /* ..10..10 memory indirect, base 16, outer 16 */ + 9, /* ..10..11 memory indirect, base 16, outer 32 */ + 0, 7, 9, 9, 0, 7, 9, 9, 0, 7, 9, 9, + 6, /* ..11.000 no memory indirect, base 32 */ + 11, /* ..11..01 memory indirect, base 32, outer NULL */ + 13, /* ..11..10 memory indirect, base 32, outer 16 */ + 13, /* ..11..11 memory indirect, base 32, outer 32 */ + 0, 11, 13, 13, 0, 11, 13, 13, 0, 11, 13, 13 +}; + + + +/* ======================================================================== */ +/* =============================== CALLBACKS ============================== */ +/* ======================================================================== */ + +/* Default callbacks used if the callback hasn't been set yet, or if the + * callback is set to NULL + */ + +/* Interrupt acknowledge */ +static int default_int_ack_callback_data; +static int default_int_ack_callback(int int_level) +{ + default_int_ack_callback_data = int_level; + CPU_INT_LEVEL = 0; + return M68K_INT_ACK_AUTOVECTOR; +} + +/* Breakpoint acknowledge */ +static unsigned int default_bkpt_ack_callback_data; +static void default_bkpt_ack_callback(unsigned int data) +{ + default_bkpt_ack_callback_data = data; +} + +/* Called when a reset instruction is executed */ +static void default_reset_instr_callback(void) +{ +} + +/* Called when the program counter changed by a large value */ +static unsigned int default_pc_changed_callback_data; +static void default_pc_changed_callback(unsigned int new_pc) +{ + default_pc_changed_callback_data = new_pc; +} + +/* Called every time there's bus activity (read/write to/from memory */ +static unsigned int default_set_fc_callback_data; +static void default_set_fc_callback(unsigned int new_fc) +{ + default_set_fc_callback_data = new_fc; +} + +/* Called every instruction cycle prior to execution */ +static void default_instr_hook_callback(void) +{ +} + + +#if M68K_EMULATE_ADDRESS_ERROR + #include + jmp_buf m68ki_aerr_trap; +#endif /* M68K_EMULATE_ADDRESS_ERROR */ + + +/* ======================================================================== */ +/* ================================= API ================================== */ +/* ======================================================================== */ + +/* Access the internals of the CPU */ +unsigned int m68k_get_reg(void* context, m68k_register_t regnum) +{ + m68ki_cpu_core* cpu = context != NULL ?(m68ki_cpu_core*)context : &m68ki_cpu; + + switch(regnum) + { + case M68K_REG_D0: return cpu->dar[0]; + case M68K_REG_D1: return cpu->dar[1]; + case M68K_REG_D2: return cpu->dar[2]; + case M68K_REG_D3: return cpu->dar[3]; + case M68K_REG_D4: return cpu->dar[4]; + case M68K_REG_D5: return cpu->dar[5]; + case M68K_REG_D6: return cpu->dar[6]; + case M68K_REG_D7: return cpu->dar[7]; + case M68K_REG_A0: return cpu->dar[8]; + case M68K_REG_A1: return cpu->dar[9]; + case M68K_REG_A2: return cpu->dar[10]; + case M68K_REG_A3: return cpu->dar[11]; + case M68K_REG_A4: return cpu->dar[12]; + case M68K_REG_A5: return cpu->dar[13]; + case M68K_REG_A6: return cpu->dar[14]; + case M68K_REG_A7: return cpu->dar[15]; + case M68K_REG_PC: return MASK_OUT_ABOVE_32(cpu->pc); + case M68K_REG_SR: return cpu->t1_flag | + cpu->t0_flag | + (cpu->s_flag << 11) | + (cpu->m_flag << 11) | + cpu->int_mask | + ((cpu->x_flag & XFLAG_SET) >> 4) | + ((cpu->n_flag & NFLAG_SET) >> 4) | + ((!cpu->not_z_flag) << 2) | + ((cpu->v_flag & VFLAG_SET) >> 6) | + ((cpu->c_flag & CFLAG_SET) >> 8); + case M68K_REG_SP: return cpu->dar[15]; + case M68K_REG_USP: return cpu->s_flag ? cpu->sp[0] : cpu->dar[15]; + case M68K_REG_ISP: return cpu->s_flag && !cpu->m_flag ? cpu->dar[15] : cpu->sp[4]; + case M68K_REG_MSP: return cpu->s_flag && cpu->m_flag ? cpu->dar[15] : cpu->sp[6]; + case M68K_REG_SFC: return cpu->sfc; + case M68K_REG_DFC: return cpu->dfc; + case M68K_REG_VBR: return cpu->vbr; + case M68K_REG_CACR: return cpu->cacr; + case M68K_REG_CAAR: return cpu->caar; + case M68K_REG_PREF_ADDR: return cpu->pref_addr; + case M68K_REG_PREF_DATA: return cpu->pref_data; + case M68K_REG_PPC: return MASK_OUT_ABOVE_32(cpu->ppc); + case M68K_REG_IR: return cpu->ir; + case M68K_REG_CPU_TYPE: + switch(cpu->cpu_type) + { + case CPU_TYPE_000: return (unsigned int)M68K_CPU_TYPE_68000; + case CPU_TYPE_010: return (unsigned int)M68K_CPU_TYPE_68010; + case CPU_TYPE_EC020: return (unsigned int)M68K_CPU_TYPE_68EC020; + case CPU_TYPE_020: return (unsigned int)M68K_CPU_TYPE_68020; + } + return M68K_CPU_TYPE_INVALID; + default: return 0; + } + return 0; +} + +void m68k_set_reg(m68k_register_t regnum, unsigned int value) +{ + switch(regnum) + { + case M68K_REG_D0: REG_D[0] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D1: REG_D[1] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D2: REG_D[2] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D3: REG_D[3] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D4: REG_D[4] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D5: REG_D[5] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D6: REG_D[6] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_D7: REG_D[7] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A0: REG_A[0] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A1: REG_A[1] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A2: REG_A[2] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A3: REG_A[3] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A4: REG_A[4] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A5: REG_A[5] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A6: REG_A[6] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_A7: REG_A[7] = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_PC: m68ki_jump(MASK_OUT_ABOVE_32(value)); return; + case M68K_REG_SR: m68ki_set_sr(value); return; + case M68K_REG_SP: REG_SP = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_USP: if(FLAG_S) + REG_USP = MASK_OUT_ABOVE_32(value); + else + REG_SP = MASK_OUT_ABOVE_32(value); + return; + case M68K_REG_ISP: if(FLAG_S && !FLAG_M) + REG_SP = MASK_OUT_ABOVE_32(value); + else + REG_ISP = MASK_OUT_ABOVE_32(value); + return; + case M68K_REG_MSP: if(FLAG_S && FLAG_M) + REG_SP = MASK_OUT_ABOVE_32(value); + else + REG_MSP = MASK_OUT_ABOVE_32(value); + return; + case M68K_REG_VBR: REG_VBR = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_SFC: REG_SFC = value & 7; return; + case M68K_REG_DFC: REG_DFC = value & 7; return; + case M68K_REG_CACR: REG_CACR = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_CAAR: REG_CAAR = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_PPC: REG_PPC = MASK_OUT_ABOVE_32(value); return; + case M68K_REG_IR: REG_IR = MASK_OUT_ABOVE_16(value); return; + case M68K_REG_CPU_TYPE: m68k_set_cpu_type(value); return; + default: return; + } +} + +/* Set the callbacks */ +void m68k_set_int_ack_callback(int (*callback)(int int_level)) +{ + CALLBACK_INT_ACK = callback ? callback : default_int_ack_callback; +} + +void m68k_set_bkpt_ack_callback(void (*callback)(unsigned int data)) +{ + CALLBACK_BKPT_ACK = callback ? callback : default_bkpt_ack_callback; +} + +void m68k_set_reset_instr_callback(void (*callback)(void)) +{ + CALLBACK_RESET_INSTR = callback ? callback : default_reset_instr_callback; +} + +void m68k_set_pc_changed_callback(void (*callback)(unsigned int new_pc)) +{ + CALLBACK_PC_CHANGED = callback ? callback : default_pc_changed_callback; +} + +void m68k_set_fc_callback(void (*callback)(unsigned int new_fc)) +{ + CALLBACK_SET_FC = callback ? callback : default_set_fc_callback; +} + +void m68k_set_instr_hook_callback(void (*callback)(void)) +{ + CALLBACK_INSTR_HOOK = callback ? callback : default_instr_hook_callback; +} + +#include +/* Set the CPU type. */ +void m68k_set_cpu_type(unsigned int cpu_type) +{ + switch(cpu_type) + { + case M68K_CPU_TYPE_68000: + CPU_TYPE = CPU_TYPE_000; + CPU_ADDRESS_MASK = 0x00ffffff; + CPU_SR_MASK = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */ + CYC_INSTRUCTION = m68ki_cycles[0]; + CYC_EXCEPTION = m68ki_exception_cycle_table[0]; + CYC_BCC_NOTAKE_B = -2; + CYC_BCC_NOTAKE_W = 2; + CYC_DBCC_F_NOEXP = -2; + CYC_DBCC_F_EXP = 2; + CYC_SCC_R_TRUE = 2; + CYC_MOVEM_W = 2; + CYC_MOVEM_L = 3; + CYC_SHIFT = 1; + CYC_RESET = 132; + return; + case M68K_CPU_TYPE_68010: + CPU_TYPE = CPU_TYPE_010; + CPU_ADDRESS_MASK = 0x00ffffff; + CPU_SR_MASK = 0xa71f; /* T1 -- S -- -- I2 I1 I0 -- -- -- X N Z V C */ + CYC_INSTRUCTION = m68ki_cycles[1]; + CYC_EXCEPTION = m68ki_exception_cycle_table[1]; + CYC_BCC_NOTAKE_B = -4; + CYC_BCC_NOTAKE_W = 0; + CYC_DBCC_F_NOEXP = 0; + CYC_DBCC_F_EXP = 6; + CYC_SCC_R_TRUE = 0; + CYC_MOVEM_W = 2; + CYC_MOVEM_L = 3; + CYC_SHIFT = 1; + CYC_RESET = 130; + return; + case M68K_CPU_TYPE_68EC020: + CPU_TYPE = CPU_TYPE_EC020; + CPU_ADDRESS_MASK = 0x00ffffff; + CPU_SR_MASK = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */ + CYC_INSTRUCTION = m68ki_cycles[2]; + CYC_EXCEPTION = m68ki_exception_cycle_table[2]; + CYC_BCC_NOTAKE_B = -2; + CYC_BCC_NOTAKE_W = 0; + CYC_DBCC_F_NOEXP = 0; + CYC_DBCC_F_EXP = 4; + CYC_SCC_R_TRUE = 0; + CYC_MOVEM_W = 2; + CYC_MOVEM_L = 2; + CYC_SHIFT = 0; + CYC_RESET = 518; + return; + case M68K_CPU_TYPE_68020: + CPU_TYPE = CPU_TYPE_020; + CPU_ADDRESS_MASK = 0xffffffff; + CPU_SR_MASK = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */ + CYC_INSTRUCTION = m68ki_cycles[2]; + CYC_EXCEPTION = m68ki_exception_cycle_table[2]; + CYC_BCC_NOTAKE_B = -2; + CYC_BCC_NOTAKE_W = 0; + CYC_DBCC_F_NOEXP = 0; + CYC_DBCC_F_EXP = 4; + CYC_SCC_R_TRUE = 0; + CYC_MOVEM_W = 2; + CYC_MOVEM_L = 2; + CYC_SHIFT = 0; + CYC_RESET = 518; + return; + } +} + +/* Execute some instructions until we use up num_cycles clock cycles */ +/* ASG: removed per-instruction interrupt checks */ +int m68k_execute(int num_cycles) +{ + /* Make sure we're not stopped */ + if(!CPU_STOPPED) + { + /* Set our pool of clock cycles available */ + SET_CYCLES(num_cycles); + m68ki_initial_cycles = num_cycles; + + /* ASG: update cycles */ + USE_CYCLES(CPU_INT_CYCLES); + CPU_INT_CYCLES = 0; + + /* Return point if we had an address error */ + m68ki_set_address_error_trap(); /* auto-disable (see m68kcpu.h) */ + + /* Main loop. Keep going until we run out of clock cycles */ + do + { + /* Set tracing accodring to T1. (T0 is done inside instruction) */ + m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */ + + /* Set the address space for reads */ + m68ki_use_data_space(); /* auto-disable (see m68kcpu.h) */ + + /* Call external hook to peek at CPU */ + m68ki_instr_hook(); /* auto-disable (see m68kcpu.h) */ + + /* Record previous program counter */ + REG_PPC = REG_PC; + + /* Read an instruction and call its handler */ + REG_IR = m68ki_read_imm_16(); + m68ki_instruction_jump_table[REG_IR](); + USE_CYCLES(CYC_INSTRUCTION[REG_IR]); + + /* Trace m68k_exception, if necessary */ + m68ki_exception_if_trace(); /* auto-disable (see m68kcpu.h) */ + } while(GET_CYCLES() > 0); + + /* set previous PC to current PC for the next entry into the loop */ + REG_PPC = REG_PC; + + /* ASG: update cycles */ + USE_CYCLES(CPU_INT_CYCLES); + CPU_INT_CYCLES = 0; + + /* return how many clocks we used */ + return m68ki_initial_cycles - GET_CYCLES(); + } + + /* We get here if the CPU is stopped or halted */ + SET_CYCLES(0); + CPU_INT_CYCLES = 0; + + return num_cycles; +} + + +int m68k_cycles_run(void) +{ + return m68ki_initial_cycles - GET_CYCLES(); +} + +int m68k_cycles_remaining(void) +{ + return GET_CYCLES(); +} + +/* Change the timeslice */ +void m68k_modify_timeslice(int cycles) +{ + m68ki_initial_cycles += cycles; + ADD_CYCLES(cycles); +} + + +void m68k_end_timeslice(void) +{ + m68ki_initial_cycles = GET_CYCLES(); + SET_CYCLES(0); +} + + +/* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */ +/* KS: Modified so that IPL* bits match with mask positions in the SR + * and cleaned out remenants of the interrupt controller. + */ +void m68k_set_irq(unsigned int int_level) +{ + uint old_level = CPU_INT_LEVEL; + CPU_INT_LEVEL = int_level << 8; + + /* A transition from < 7 to 7 always interrupts (NMI) */ + /* Note: Level 7 can also level trigger like a normal IRQ */ + if(old_level != 0x0700 && CPU_INT_LEVEL == 0x0700) + m68ki_exception_interrupt(7); /* Edge triggered level 7 (NMI) */ + else + m68ki_check_interrupts(); /* Level triggered (IRQ) */ +} + +void m68k_init(void) +{ + static uint emulation_initialized = 0; + + /* The first call to this function initializes the opcode handler jump table */ + if(!emulation_initialized) + { + m68ki_build_opcode_table(); + emulation_initialized = 1; + } + + m68k_set_int_ack_callback(NULL); + m68k_set_bkpt_ack_callback(NULL); + m68k_set_reset_instr_callback(NULL); + m68k_set_pc_changed_callback(NULL); + m68k_set_fc_callback(NULL); + m68k_set_instr_hook_callback(NULL); +} + +/* Pulse the RESET line on the CPU */ +void m68k_pulse_reset(void) +{ + /* Clear all stop levels and eat up all remaining cycles */ + CPU_STOPPED = 0; + SET_CYCLES(0); + + CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET; + CPU_INSTR_MODE = INSTRUCTION_YES; + + /* Turn off tracing */ + FLAG_T1 = FLAG_T0 = 0; + m68ki_clear_trace(); + /* Interrupt mask to level 7 */ + FLAG_INT_MASK = 0x0700; + /* Reset VBR */ + REG_VBR = 0; + /* Go to supervisor mode */ + m68ki_set_sm_flag(SFLAG_SET | MFLAG_CLEAR); + + /* Invalidate the prefetch queue */ +#if M68K_EMULATE_PREFETCH + /* Set to arbitrary number since our first fetch is from 0 */ + CPU_PREF_ADDR = 0x1000; +#endif /* M68K_EMULATE_PREFETCH */ + + /* Read the initial stack pointer and program counter */ + m68ki_jump(0); + REG_SP = m68ki_read_imm_32(); + REG_PC = m68ki_read_imm_32(); + m68ki_jump(REG_PC); + + CPU_RUN_MODE = RUN_MODE_NORMAL; +} + +/* Pulse the HALT line on the CPU */ +void m68k_pulse_halt(void) +{ + CPU_STOPPED |= STOP_LEVEL_HALT; +} + + +/* Get and set the current CPU context */ +/* This is to allow for multiple CPUs */ +unsigned int m68k_context_size() +{ + return sizeof(m68ki_cpu_core); +} + +unsigned int m68k_get_context(void* dst) +{ + if(dst) *(m68ki_cpu_core*)dst = m68ki_cpu; + return sizeof(m68ki_cpu_core); +} + +void m68k_set_context(void* src) +{ + if(src) m68ki_cpu = *(m68ki_cpu_core*)src; +} + + + +/* ======================================================================== */ +/* ============================== MAME STUFF ============================== */ +/* ======================================================================== */ + +#if M68K_COMPILE_FOR_MAME == OPT_ON + +#include "state.h" + +static struct { + UINT16 sr; + int stopped; + int halted; +} m68k_substate; + +static void m68k_prepare_substate(void) +{ + m68k_substate.sr = m68ki_get_sr(); + m68k_substate.stopped = (CPU_STOPPED & STOP_LEVEL_STOP) != 0; + m68k_substate.halted = (CPU_STOPPED & STOP_LEVEL_HALT) != 0; +} + +static void m68k_post_load(void) +{ + m68ki_set_sr_noint_nosp(m68k_substate.sr); + CPU_STOPPED = m68k_substate.stopped ? STOP_LEVEL_STOP : 0 + | m68k_substate.halted ? STOP_LEVEL_HALT : 0; + m68ki_jump(REG_PC); +} + +void m68k_state_register(const char *type) +{ + int cpu = cpu_getactivecpu(); + + state_save_register_UINT32(type, cpu, "D" , REG_D, 8); + state_save_register_UINT32(type, cpu, "A" , REG_A, 8); + state_save_register_UINT32(type, cpu, "PPC" , ®_PPC, 1); + state_save_register_UINT32(type, cpu, "PC" , ®_PC, 1); + state_save_register_UINT32(type, cpu, "USP" , ®_USP, 1); + state_save_register_UINT32(type, cpu, "ISP" , ®_ISP, 1); + state_save_register_UINT32(type, cpu, "MSP" , ®_MSP, 1); + state_save_register_UINT32(type, cpu, "VBR" , ®_VBR, 1); + state_save_register_UINT32(type, cpu, "SFC" , ®_SFC, 1); + state_save_register_UINT32(type, cpu, "DFC" , ®_DFC, 1); + state_save_register_UINT32(type, cpu, "CACR" , ®_CACR, 1); + state_save_register_UINT32(type, cpu, "CAAR" , ®_CAAR, 1); + state_save_register_UINT16(type, cpu, "SR" , &m68k_substate.sr, 1); + state_save_register_UINT32(type, cpu, "INT_LEVEL" , &CPU_INT_LEVEL, 1); + state_save_register_UINT32(type, cpu, "INT_CYCLES", &CPU_INT_CYCLES, 1); + state_save_register_int (type, cpu, "STOPPED" , &m68k_substate.stopped); + state_save_register_int (type, cpu, "HALTED" , &m68k_substate.halted); + state_save_register_UINT32(type, cpu, "PREF_ADDR" , &CPU_PREF_ADDR, 1); + state_save_register_UINT32(type, cpu, "PREF_DATA" , &CPU_PREF_DATA, 1); + state_save_register_func_presave(m68k_prepare_substate); + state_save_register_func_postload(m68k_post_load); +} + +#endif /* M68K_COMPILE_FOR_MAME */ + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ diff --git a/MCUME_teensy/teensygen/musashi34/m68kcpu.h b/MCUME_teensy/teensygen/musashi34/m68kcpu.h new file mode 100644 index 0000000..91e5e72 --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68kcpu.h @@ -0,0 +1,1986 @@ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.4 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + + + +#ifndef M68KCPU__HEADER +#define M68KCPU__HEADER + +#include "m68k.h" +#include + +#if M68K_EMULATE_ADDRESS_ERROR +#include +#endif /* M68K_EMULATE_ADDRESS_ERROR */ + +/* ======================================================================== */ +/* ==================== ARCHITECTURE-DEPENDANT DEFINES ==================== */ +/* ======================================================================== */ + +/* Check for > 32bit sizes */ +#if UINT_MAX > 0xffffffff + #define M68K_INT_GT_32_BIT 1 +#else + #define M68K_INT_GT_32_BIT 0 +#endif + +/* Data types used in this emulation core */ +#undef sint8 +#undef sint16 +#undef sint32 +#undef sint64 +#undef uint8 +#undef uint16 +#undef uint32 +#undef uint64 +#undef sint +#undef uint + +#define sint8 signed char /* ASG: changed from char to signed char */ +#define sint16 signed short +#define sint32 signed long +#define uint8 unsigned char +#define uint16 unsigned short +#define uint32 unsigned long + +/* signed and unsigned int must be at least 32 bits wide */ +#define sint signed int +//newlib typedefs this +//#define uint unsigned int +typedef unsigned int uint; + +#if M68K_USE_64_BIT +#define sint64 signed long long +#define uint64 unsigned long long +#else +#define sint64 sint32 +#define uint64 uint32 +#endif /* M68K_USE_64_BIT */ + + + +/* Allow for architectures that don't have 8-bit sizes */ +#if UCHAR_MAX == 0xff + #define MAKE_INT_8(A) (sint8)(A) +#else + #undef sint8 + #define sint8 signed int + #undef uint8 + #define uint8 unsigned int + INLINE sint MAKE_INT_8(uint value) + { + return (value & 0x80) ? value | ~0xff : value & 0xff; + } +#endif /* UCHAR_MAX == 0xff */ + + +/* Allow for architectures that don't have 16-bit sizes */ +#if USHRT_MAX == 0xffff + #define MAKE_INT_16(A) (sint16)(A) +#else + #undef sint16 + #define sint16 signed int + #undef uint16 + #define uint16 unsigned int + INLINE sint MAKE_INT_16(uint value) + { + return (value & 0x8000) ? value | ~0xffff : value & 0xffff; + } +#endif /* USHRT_MAX == 0xffff */ + + +/* Allow for architectures that don't have 32-bit sizes */ +#if ULONG_MAX == 0xffffffff + #define MAKE_INT_32(A) (sint32)(A) +#else + #undef sint32 + #define sint32 signed int + #undef uint32 + #define uint32 unsigned int + INLINE sint MAKE_INT_32(uint value) + { + return (value & 0x80000000) ? value | ~0xffffffff : value & 0xffffffff; + } +#endif /* ULONG_MAX == 0xffffffff */ + + + + +/* ======================================================================== */ +/* ============================ GENERAL DEFINES =========================== */ +/* ======================================================================== */ + +/* Exception Vectors handled by emulation */ +#define EXCEPTION_BUS_ERROR 2 /* This one is not emulated! */ +#define EXCEPTION_ADDRESS_ERROR 3 /* This one is partially emulated (doesn't stack a proper frame yet) */ +#define EXCEPTION_ILLEGAL_INSTRUCTION 4 +#define EXCEPTION_ZERO_DIVIDE 5 +#define EXCEPTION_CHK 6 +#define EXCEPTION_TRAPV 7 +#define EXCEPTION_PRIVILEGE_VIOLATION 8 +#define EXCEPTION_TRACE 9 +#define EXCEPTION_1010 10 +#define EXCEPTION_1111 11 +#define EXCEPTION_FORMAT_ERROR 14 +#define EXCEPTION_UNINITIALIZED_INTERRUPT 15 +#define EXCEPTION_SPURIOUS_INTERRUPT 24 +#define EXCEPTION_INTERRUPT_AUTOVECTOR 24 +#define EXCEPTION_TRAP_BASE 32 + +/* Function codes set by CPU during data/address bus activity */ +#define FUNCTION_CODE_USER_DATA 1 +#define FUNCTION_CODE_USER_PROGRAM 2 +#define FUNCTION_CODE_SUPERVISOR_DATA 5 +#define FUNCTION_CODE_SUPERVISOR_PROGRAM 6 +#define FUNCTION_CODE_CPU_SPACE 7 + +/* CPU types for deciding what to emulate */ +#define CPU_TYPE_000 1 +#define CPU_TYPE_010 2 +#define CPU_TYPE_EC020 4 +#define CPU_TYPE_020 8 + +/* Different ways to stop the CPU */ +#define STOP_LEVEL_STOP 1 +#define STOP_LEVEL_HALT 2 + +/* Used for 68000 address error processing */ +#define INSTRUCTION_YES 0 +#define INSTRUCTION_NO 0x08 +#define MODE_READ 0x10 +#define MODE_WRITE 0 + +#define RUN_MODE_NORMAL 0 +#define RUN_MODE_BERR_AERR_RESET 1 + +#ifndef NULL +#define NULL ((void*)0) +#endif + +/* ======================================================================== */ +/* ================================ MACROS ================================ */ +/* ======================================================================== */ + + +/* ---------------------------- General Macros ---------------------------- */ + +/* Bit Isolation Macros */ +#define BIT_0(A) ((A) & 0x00000001) +#define BIT_1(A) ((A) & 0x00000002) +#define BIT_2(A) ((A) & 0x00000004) +#define BIT_3(A) ((A) & 0x00000008) +#define BIT_4(A) ((A) & 0x00000010) +#define BIT_5(A) ((A) & 0x00000020) +#define BIT_6(A) ((A) & 0x00000040) +#define BIT_7(A) ((A) & 0x00000080) +#define BIT_8(A) ((A) & 0x00000100) +#define BIT_9(A) ((A) & 0x00000200) +#define BIT_A(A) ((A) & 0x00000400) +#define BIT_B(A) ((A) & 0x00000800) +#define BIT_C(A) ((A) & 0x00001000) +#define BIT_D(A) ((A) & 0x00002000) +#define BIT_E(A) ((A) & 0x00004000) +#define BIT_F(A) ((A) & 0x00008000) +#define BIT_10(A) ((A) & 0x00010000) +#define BIT_11(A) ((A) & 0x00020000) +#define BIT_12(A) ((A) & 0x00040000) +#define BIT_13(A) ((A) & 0x00080000) +#define BIT_14(A) ((A) & 0x00100000) +#define BIT_15(A) ((A) & 0x00200000) +#define BIT_16(A) ((A) & 0x00400000) +#define BIT_17(A) ((A) & 0x00800000) +#define BIT_18(A) ((A) & 0x01000000) +#define BIT_19(A) ((A) & 0x02000000) +#define BIT_1A(A) ((A) & 0x04000000) +#define BIT_1B(A) ((A) & 0x08000000) +#define BIT_1C(A) ((A) & 0x10000000) +#define BIT_1D(A) ((A) & 0x20000000) +#define BIT_1E(A) ((A) & 0x40000000) +#define BIT_1F(A) ((A) & 0x80000000) + +/* Get the most significant bit for specific sizes */ +#define GET_MSB_8(A) ((A) & 0x80) +#define GET_MSB_9(A) ((A) & 0x100) +#define GET_MSB_16(A) ((A) & 0x8000) +#define GET_MSB_17(A) ((A) & 0x10000) +#define GET_MSB_32(A) ((A) & 0x80000000) +#if M68K_USE_64_BIT +#define GET_MSB_33(A) ((A) & 0x100000000) +#endif /* M68K_USE_64_BIT */ + +/* Isolate nibbles */ +#define LOW_NIBBLE(A) ((A) & 0x0f) +#define HIGH_NIBBLE(A) ((A) & 0xf0) + +/* These are used to isolate 8, 16, and 32 bit sizes */ +#define MASK_OUT_ABOVE_2(A) ((A) & 3) +#define MASK_OUT_ABOVE_8(A) ((A) & 0xff) +#define MASK_OUT_ABOVE_16(A) ((A) & 0xffff) +#define MASK_OUT_BELOW_2(A) ((A) & ~3) +#define MASK_OUT_BELOW_8(A) ((A) & ~0xff) +#define MASK_OUT_BELOW_16(A) ((A) & ~0xffff) + +/* No need to mask if we are 32 bit */ +#if M68K_INT_GT_32_BIT || M68K_USE_64_BIT + #define MASK_OUT_ABOVE_32(A) ((A) & 0xffffffff) + #define MASK_OUT_BELOW_32(A) ((A) & ~0xffffffff) +#else + #define MASK_OUT_ABOVE_32(A) (A) + #define MASK_OUT_BELOW_32(A) 0 +#endif /* M68K_INT_GT_32_BIT || M68K_USE_64_BIT */ + +/* Simulate address lines of 68k family */ +#define ADDRESS_68K(A) ((A)&CPU_ADDRESS_MASK) + + +/* Shift & Rotate Macros. */ +#define LSL(A, C) ((A) << (C)) +#define LSR(A, C) ((A) >> (C)) + +/* Some > 32-bit optimizations */ +#if M68K_INT_GT_32_BIT + /* Shift left and right */ + #define LSR_32(A, C) ((A) >> (C)) + #define LSL_32(A, C) ((A) << (C)) +#else + /* We have to do this because the morons at ANSI decided that shifts + * by >= data size are undefined. + */ + #define LSR_32(A, C) ((C) < 32 ? (A) >> (C) : 0) + #define LSL_32(A, C) ((C) < 32 ? (A) << (C) : 0) +#endif /* M68K_INT_GT_32_BIT */ + +#if M68K_USE_64_BIT + #define LSL_32_64(A, C) ((A) << (C)) + #define LSR_32_64(A, C) ((A) >> (C)) + #define ROL_33_64(A, C) (LSL_32_64(A, C) | LSR_32_64(A, 33-(C))) + #define ROR_33_64(A, C) (LSR_32_64(A, C) | LSL_32_64(A, 33-(C))) +#endif /* M68K_USE_64_BIT */ + +#define ROL_8(A, C) MASK_OUT_ABOVE_8(LSL(A, C) | LSR(A, 8-(C))) +#define ROL_9(A, C) (LSL(A, C) | LSR(A, 9-(C))) +#define ROL_16(A, C) MASK_OUT_ABOVE_16(LSL(A, C) | LSR(A, 16-(C))) +#define ROL_17(A, C) (LSL(A, C) | LSR(A, 17-(C))) +#define ROL_32(A, C) MASK_OUT_ABOVE_32(LSL_32(A, C) | LSR_32(A, 32-(C))) +#define ROL_33(A, C) (LSL_32(A, C) | LSR_32(A, 33-(C))) + +#define ROR_8(A, C) MASK_OUT_ABOVE_8(LSR(A, C) | LSL(A, 8-(C))) +#define ROR_9(A, C) (LSR(A, C) | LSL(A, 9-(C))) +#define ROR_16(A, C) MASK_OUT_ABOVE_16(LSR(A, C) | LSL(A, 16-(C))) +#define ROR_17(A, C) (LSR(A, C) | LSL(A, 17-(C))) +#define ROR_32(A, C) MASK_OUT_ABOVE_32(LSR_32(A, C) | LSL_32(A, 32-(C))) +#define ROR_33(A, C) (LSR_32(A, C) | LSL_32(A, 33-(C))) + + + +/* ------------------------------ CPU Access ------------------------------ */ + +/* Access the CPU registers */ +#define CPU_TYPE m68ki_cpu.cpu_type + +#define REG_DA m68ki_cpu.dar /* easy access to data and address regs */ +#define REG_D m68ki_cpu.dar +#define REG_A (m68ki_cpu.dar+8) +#define REG_PPC m68ki_cpu.ppc +#define REG_PC m68ki_cpu.pc +#define REG_SP_BASE m68ki_cpu.sp +#define REG_USP m68ki_cpu.sp[0] +#define REG_ISP m68ki_cpu.sp[4] +#define REG_MSP m68ki_cpu.sp[6] +#define REG_SP m68ki_cpu.dar[15] +#define REG_VBR m68ki_cpu.vbr +#define REG_SFC m68ki_cpu.sfc +#define REG_DFC m68ki_cpu.dfc +#define REG_CACR m68ki_cpu.cacr +#define REG_CAAR m68ki_cpu.caar +#define REG_IR m68ki_cpu.ir + +#define FLAG_T1 m68ki_cpu.t1_flag +#define FLAG_T0 m68ki_cpu.t0_flag +#define FLAG_S m68ki_cpu.s_flag +#define FLAG_M m68ki_cpu.m_flag +#define FLAG_X m68ki_cpu.x_flag +#define FLAG_N m68ki_cpu.n_flag +#define FLAG_Z m68ki_cpu.not_z_flag +#define FLAG_V m68ki_cpu.v_flag +#define FLAG_C m68ki_cpu.c_flag +#define FLAG_INT_MASK m68ki_cpu.int_mask + +#define CPU_INT_LEVEL m68ki_cpu.int_level /* ASG: changed from CPU_INTS_PENDING */ +#define CPU_INT_CYCLES m68ki_cpu.int_cycles /* ASG */ +#define CPU_STOPPED m68ki_cpu.stopped +#define CPU_PREF_ADDR m68ki_cpu.pref_addr +#define CPU_PREF_DATA m68ki_cpu.pref_data +#define CPU_ADDRESS_MASK m68ki_cpu.address_mask +#define CPU_SR_MASK m68ki_cpu.sr_mask +#define CPU_INSTR_MODE m68ki_cpu.instr_mode +#define CPU_RUN_MODE m68ki_cpu.run_mode + +#define CYC_INSTRUCTION m68ki_cpu.cyc_instruction +#define CYC_EXCEPTION m68ki_cpu.cyc_exception +#define CYC_BCC_NOTAKE_B m68ki_cpu.cyc_bcc_notake_b +#define CYC_BCC_NOTAKE_W m68ki_cpu.cyc_bcc_notake_w +#define CYC_DBCC_F_NOEXP m68ki_cpu.cyc_dbcc_f_noexp +#define CYC_DBCC_F_EXP m68ki_cpu.cyc_dbcc_f_exp +#define CYC_SCC_R_TRUE m68ki_cpu.cyc_scc_r_true +#define CYC_MOVEM_W m68ki_cpu.cyc_movem_w +#define CYC_MOVEM_L m68ki_cpu.cyc_movem_l +#define CYC_SHIFT m68ki_cpu.cyc_shift +#define CYC_RESET m68ki_cpu.cyc_reset + + +#define CALLBACK_INT_ACK m68ki_cpu.int_ack_callback +#define CALLBACK_BKPT_ACK m68ki_cpu.bkpt_ack_callback +#define CALLBACK_RESET_INSTR m68ki_cpu.reset_instr_callback +#define CALLBACK_PC_CHANGED m68ki_cpu.pc_changed_callback +#define CALLBACK_SET_FC m68ki_cpu.set_fc_callback +#define CALLBACK_INSTR_HOOK m68ki_cpu.instr_hook_callback + + + +/* ----------------------------- Configuration ---------------------------- */ + +/* These defines are dependant on the configuration defines in m68kconf.h */ + +/* Disable certain comparisons if we're not using all CPU types */ +#if M68K_EMULATE_020 + #define CPU_TYPE_IS_020_PLUS(A) ((A) & CPU_TYPE_020) + #define CPU_TYPE_IS_020_LESS(A) 1 +#else + #define CPU_TYPE_IS_020_PLUS(A) 0 + #define CPU_TYPE_IS_020_LESS(A) 1 +#endif + +#if M68K_EMULATE_EC020 + #define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020)) + #define CPU_TYPE_IS_EC020_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_010 | CPU_TYPE_EC020)) +#else + #define CPU_TYPE_IS_EC020_PLUS(A) CPU_TYPE_IS_020_PLUS(A) + #define CPU_TYPE_IS_EC020_LESS(A) CPU_TYPE_IS_020_LESS(A) +#endif + +#if M68K_EMULATE_010 + #define CPU_TYPE_IS_010(A) ((A) == CPU_TYPE_010) + #define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020)) + #define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_010)) +#else + #define CPU_TYPE_IS_010(A) 0 + #define CPU_TYPE_IS_010_PLUS(A) CPU_TYPE_IS_EC020_PLUS(A) + #define CPU_TYPE_IS_010_LESS(A) CPU_TYPE_IS_EC020_LESS(A) +#endif + +#if M68K_EMULATE_020 || M68K_EMULATE_EC020 + #define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020)) +#else + #define CPU_TYPE_IS_020_VARIANT(A) 0 +#endif + +#if M68K_EMULATE_020 || M68K_EMULATE_EC020 || M68K_EMULATE_010 + #define CPU_TYPE_IS_000(A) ((A) == CPU_TYPE_000) +#else + #define CPU_TYPE_IS_000(A) 1 +#endif + + +#if !M68K_SEPARATE_READS +#define m68k_read_immediate_16(A) m68ki_read_program_16(A) +#define m68k_read_immediate_32(A) m68ki_read_program_32(A) + +#define m68k_read_pcrelative_8(A) m68ki_read_program_8(A) +#define m68k_read_pcrelative_16(A) m68ki_read_program_16(A) +#define m68k_read_pcrelative_32(A) m68ki_read_program_32(A) +#endif /* M68K_SEPARATE_READS */ + + +/* Enable or disable callback functions */ +#if M68K_EMULATE_INT_ACK + #if M68K_EMULATE_INT_ACK == OPT_SPECIFY_HANDLER + #define m68ki_int_ack(A) M68K_INT_ACK_CALLBACK(A) + #else + #define m68ki_int_ack(A) CALLBACK_INT_ACK(A) + #endif +#else + /* Default action is to used autovector mode, which is most common */ + #define m68ki_int_ack(A) M68K_INT_ACK_AUTOVECTOR +#endif /* M68K_EMULATE_INT_ACK */ + +#if M68K_EMULATE_BKPT_ACK + #if M68K_EMULATE_BKPT_ACK == OPT_SPECIFY_HANDLER + #define m68ki_bkpt_ack(A) M68K_BKPT_ACK_CALLBACK(A) + #else + #define m68ki_bkpt_ack(A) CALLBACK_BKPT_ACK(A) + #endif +#else + #define m68ki_bkpt_ack(A) +#endif /* M68K_EMULATE_BKPT_ACK */ + +#if M68K_EMULATE_RESET + #if M68K_EMULATE_RESET == OPT_SPECIFY_HANDLER + #define m68ki_output_reset() M68K_RESET_CALLBACK() + #else + #define m68ki_output_reset() CALLBACK_RESET_INSTR() + #endif +#else + #define m68ki_output_reset() +#endif /* M68K_EMULATE_RESET */ + +#if M68K_INSTRUCTION_HOOK + #if M68K_INSTRUCTION_HOOK == OPT_SPECIFY_HANDLER + #define m68ki_instr_hook() M68K_INSTRUCTION_CALLBACK() + #else + #define m68ki_instr_hook() CALLBACK_INSTR_HOOK() + #endif +#else + #define m68ki_instr_hook() +#endif /* M68K_INSTRUCTION_HOOK */ + +#if M68K_MONITOR_PC + #if M68K_MONITOR_PC == OPT_SPECIFY_HANDLER + #define m68ki_pc_changed(A) M68K_SET_PC_CALLBACK(ADDRESS_68K(A)) + #else + #define m68ki_pc_changed(A) CALLBACK_PC_CHANGED(ADDRESS_68K(A)) + #endif +#else + #define m68ki_pc_changed(A) +#endif /* M68K_MONITOR_PC */ + + +/* Enable or disable function code emulation */ +#if M68K_EMULATE_FC + #if M68K_EMULATE_FC == OPT_SPECIFY_HANDLER + #define m68ki_set_fc(A) M68K_SET_FC_CALLBACK(A) + #else + #define m68ki_set_fc(A) CALLBACK_SET_FC(A) + #endif + #define m68ki_use_data_space() m68ki_address_space = FUNCTION_CODE_USER_DATA + #define m68ki_use_program_space() m68ki_address_space = FUNCTION_CODE_USER_PROGRAM + #define m68ki_get_address_space() m68ki_address_space +#else + #define m68ki_set_fc(A) + #define m68ki_use_data_space() + #define m68ki_use_program_space() + #define m68ki_get_address_space() FUNCTION_CODE_USER_DATA +#endif /* M68K_EMULATE_FC */ + + +/* Enable or disable trace emulation */ +#if M68K_EMULATE_TRACE + /* Initiates trace checking before each instruction (t1) */ + #define m68ki_trace_t1() m68ki_tracing = FLAG_T1 + /* adds t0 to trace checking if we encounter change of flow */ + #define m68ki_trace_t0() m68ki_tracing |= FLAG_T0 + /* Clear all tracing */ + #define m68ki_clear_trace() m68ki_tracing = 0 + /* Cause a trace exception if we are tracing */ + #define m68ki_exception_if_trace() if(m68ki_tracing) m68ki_exception_trace() +#else + #define m68ki_trace_t1() + #define m68ki_trace_t0() + #define m68ki_clear_trace() + #define m68ki_exception_if_trace() +#endif /* M68K_EMULATE_TRACE */ + + + +/* Address error */ +#if M68K_EMULATE_ADDRESS_ERROR + #include + extern jmp_buf m68ki_aerr_trap; + + #define m68ki_set_address_error_trap() \ + if(setjmp(m68ki_aerr_trap) != 0) \ + { \ + m68ki_exception_address_error(); \ + if(CPU_STOPPED) \ + { \ + SET_CYCLES(0); \ + CPU_INT_CYCLES = 0; \ + return m68ki_initial_cycles; \ + } \ + /* ensure we don't re-enter execution loop after an + address error if there's no more cycles remaining */ \ + if(GET_CYCLES() <= 0) \ + { \ + /* return how many clocks we used */ \ + return m68ki_initial_cycles - GET_CYCLES(); \ + } \ + } + + #define m68ki_check_address_error(ADDR, WRITE_MODE, FC) \ + if((ADDR)&1) \ + { \ + m68ki_aerr_address = ADDR; \ + m68ki_aerr_write_mode = WRITE_MODE; \ + m68ki_aerr_fc = FC; \ + longjmp(m68ki_aerr_trap, 1); \ + } +#else + #define m68ki_set_address_error_trap() + #define m68ki_check_address_error(ADDR, WRITE_MODE, FC) +#endif /* M68K_ADDRESS_ERROR */ + +/* Logging */ +#if M68K_LOG_ENABLE + #include + extern FILE* M68K_LOG_FILEHANDLE + extern char* m68ki_cpu_names[]; + + #define M68K_DO_LOG(A) if(M68K_LOG_FILEHANDLE) fprintf A + #if M68K_LOG_1010_1111 + #define M68K_DO_LOG_EMU(A) if(M68K_LOG_FILEHANDLE) fprintf A + #else + #define M68K_DO_LOG_EMU(A) + #endif +#else + #define M68K_DO_LOG(A) + #define M68K_DO_LOG_EMU(A) +#endif + + + +/* -------------------------- EA / Operand Access ------------------------- */ + +/* + * The general instruction format follows this pattern: + * .... XXX. .... .YYY + * where XXX is register X and YYY is register Y + */ +/* Data Register Isolation */ +#define DX (REG_D[(REG_IR >> 9) & 7]) +#define DY (REG_D[REG_IR & 7]) +/* Address Register Isolation */ +#define AX (REG_A[(REG_IR >> 9) & 7]) +#define AY (REG_A[REG_IR & 7]) + + +/* Effective Address Calculations */ +#define EA_AY_AI_8() AY /* address register indirect */ +#define EA_AY_AI_16() EA_AY_AI_8() +#define EA_AY_AI_32() EA_AY_AI_8() +#define EA_AY_PI_8() (AY++) /* postincrement (size = byte) */ +#define EA_AY_PI_16() ((AY+=2)-2) /* postincrement (size = word) */ +#define EA_AY_PI_32() ((AY+=4)-4) /* postincrement (size = long) */ +#define EA_AY_PD_8() (--AY) /* predecrement (size = byte) */ +#define EA_AY_PD_16() (AY-=2) /* predecrement (size = word) */ +#define EA_AY_PD_32() (AY-=4) /* predecrement (size = long) */ +#define EA_AY_DI_8() (AY+MAKE_INT_16(m68ki_read_imm_16())) /* displacement */ +#define EA_AY_DI_16() EA_AY_DI_8() +#define EA_AY_DI_32() EA_AY_DI_8() +#define EA_AY_IX_8() m68ki_get_ea_ix(AY) /* indirect + index */ +#define EA_AY_IX_16() EA_AY_IX_8() +#define EA_AY_IX_32() EA_AY_IX_8() + +#define EA_AX_AI_8() AX +#define EA_AX_AI_16() EA_AX_AI_8() +#define EA_AX_AI_32() EA_AX_AI_8() +#define EA_AX_PI_8() (AX++) +#define EA_AX_PI_16() ((AX+=2)-2) +#define EA_AX_PI_32() ((AX+=4)-4) +#define EA_AX_PD_8() (--AX) +#define EA_AX_PD_16() (AX-=2) +#define EA_AX_PD_32() (AX-=4) +#define EA_AX_DI_8() (AX+MAKE_INT_16(m68ki_read_imm_16())) +#define EA_AX_DI_16() EA_AX_DI_8() +#define EA_AX_DI_32() EA_AX_DI_8() +#define EA_AX_IX_8() m68ki_get_ea_ix(AX) +#define EA_AX_IX_16() EA_AX_IX_8() +#define EA_AX_IX_32() EA_AX_IX_8() + +#define EA_A7_PI_8() ((REG_A[7]+=2)-2) +#define EA_A7_PD_8() (REG_A[7]-=2) + +#define EA_AW_8() MAKE_INT_16(m68ki_read_imm_16()) /* absolute word */ +#define EA_AW_16() EA_AW_8() +#define EA_AW_32() EA_AW_8() +#define EA_AL_8() m68ki_read_imm_32() /* absolute long */ +#define EA_AL_16() EA_AL_8() +#define EA_AL_32() EA_AL_8() +#define EA_PCDI_8() m68ki_get_ea_pcdi() /* pc indirect + displacement */ +#define EA_PCDI_16() EA_PCDI_8() +#define EA_PCDI_32() EA_PCDI_8() +#define EA_PCIX_8() m68ki_get_ea_pcix() /* pc indirect + index */ +#define EA_PCIX_16() EA_PCIX_8() +#define EA_PCIX_32() EA_PCIX_8() + + +#define OPER_I_8() m68ki_read_imm_8() +#define OPER_I_16() m68ki_read_imm_16() +#define OPER_I_32() m68ki_read_imm_32() + + + +/* --------------------------- Status Register ---------------------------- */ + +/* Flag Calculation Macros */ +#define CFLAG_8(A) (A) +#define CFLAG_16(A) ((A)>>8) + +#if M68K_INT_GT_32_BIT + #define CFLAG_ADD_32(S, D, R) ((R)>>24) + #define CFLAG_SUB_32(S, D, R) ((R)>>24) +#else + #define CFLAG_ADD_32(S, D, R) (((S & D) | (~R & (S | D)))>>23) + #define CFLAG_SUB_32(S, D, R) (((S & R) | (~D & (S | R)))>>23) +#endif /* M68K_INT_GT_32_BIT */ + +#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R)) +#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8) +#define VFLAG_ADD_32(S, D, R) (((S^R) & (D^R))>>24) + +#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D)) +#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8) +#define VFLAG_SUB_32(S, D, R) (((S^D) & (R^D))>>24) + +#define NFLAG_8(A) (A) +#define NFLAG_16(A) ((A)>>8) +#define NFLAG_32(A) ((A)>>24) +#define NFLAG_64(A) ((A)>>56) + +#define ZFLAG_8(A) MASK_OUT_ABOVE_8(A) +#define ZFLAG_16(A) MASK_OUT_ABOVE_16(A) +#define ZFLAG_32(A) MASK_OUT_ABOVE_32(A) + + +/* Flag values */ +#define NFLAG_SET 0x80 +#define NFLAG_CLEAR 0 +#define CFLAG_SET 0x100 +#define CFLAG_CLEAR 0 +#define XFLAG_SET 0x100 +#define XFLAG_CLEAR 0 +#define VFLAG_SET 0x80 +#define VFLAG_CLEAR 0 +#define ZFLAG_SET 0 +#define ZFLAG_CLEAR 0xffffffff + +#define SFLAG_SET 4 +#define SFLAG_CLEAR 0 +#define MFLAG_SET 2 +#define MFLAG_CLEAR 0 + +/* Turn flag values into 1 or 0 */ +#define XFLAG_AS_1() ((FLAG_X>>8)&1) +#define NFLAG_AS_1() ((FLAG_N>>7)&1) +#define VFLAG_AS_1() ((FLAG_V>>7)&1) +#define ZFLAG_AS_1() (!FLAG_Z) +#define CFLAG_AS_1() ((FLAG_C>>8)&1) + + +/* Conditions */ +#define COND_CS() (FLAG_C&0x100) +#define COND_CC() (!COND_CS()) +#define COND_VS() (FLAG_V&0x80) +#define COND_VC() (!COND_VS()) +#define COND_NE() FLAG_Z +#define COND_EQ() (!COND_NE()) +#define COND_MI() (FLAG_N&0x80) +#define COND_PL() (!COND_MI()) +#define COND_LT() ((FLAG_N^FLAG_V)&0x80) +#define COND_GE() (!COND_LT()) +#define COND_HI() (COND_CC() && COND_NE()) +#define COND_LS() (COND_CS() || COND_EQ()) +#define COND_GT() (COND_GE() && COND_NE()) +#define COND_LE() (COND_LT() || COND_EQ()) + +/* Reversed conditions */ +#define COND_NOT_CS() COND_CC() +#define COND_NOT_CC() COND_CS() +#define COND_NOT_VS() COND_VC() +#define COND_NOT_VC() COND_VS() +#define COND_NOT_NE() COND_EQ() +#define COND_NOT_EQ() COND_NE() +#define COND_NOT_MI() COND_PL() +#define COND_NOT_PL() COND_MI() +#define COND_NOT_LT() COND_GE() +#define COND_NOT_GE() COND_LT() +#define COND_NOT_HI() COND_LS() +#define COND_NOT_LS() COND_HI() +#define COND_NOT_GT() COND_LE() +#define COND_NOT_LE() COND_GT() + +/* Not real conditions, but here for convenience */ +#define COND_XS() (FLAG_X&0x100) +#define COND_XC() (!COND_XS) + + +/* Get the condition code register */ +#define m68ki_get_ccr() ((COND_XS() >> 4) | \ + (COND_MI() >> 4) | \ + (COND_EQ() << 2) | \ + (COND_VS() >> 6) | \ + (COND_CS() >> 8)) + +/* Get the status register */ +#define m68ki_get_sr() ( FLAG_T1 | \ + FLAG_T0 | \ + (FLAG_S << 11) | \ + (FLAG_M << 11) | \ + FLAG_INT_MASK | \ + m68ki_get_ccr()) + + + +/* ---------------------------- Cycle Counting ---------------------------- */ + +#define ADD_CYCLES(A) m68ki_remaining_cycles += (A) +#define USE_CYCLES(A) m68ki_remaining_cycles -= (A) +#define SET_CYCLES(A) m68ki_remaining_cycles = A +#define GET_CYCLES() m68ki_remaining_cycles +#define USE_ALL_CYCLES() m68ki_remaining_cycles %= CYC_INSTRUCTION[REG_IR] + + + +/* ----------------------------- Read / Write ----------------------------- */ + +/* Read from the current address space */ +#define m68ki_read_8(A) m68ki_read_8_fc (A, FLAG_S | m68ki_get_address_space()) +#define m68ki_read_16(A) m68ki_read_16_fc(A, FLAG_S | m68ki_get_address_space()) +#define m68ki_read_32(A) m68ki_read_32_fc(A, FLAG_S | m68ki_get_address_space()) + +/* Write to the current data space */ +#define m68ki_write_8(A, V) m68ki_write_8_fc (A, FLAG_S | FUNCTION_CODE_USER_DATA, V) +#define m68ki_write_16(A, V) m68ki_write_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) +#define m68ki_write_32(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) + +#if M68K_SIMULATE_PD_WRITES +#define m68ki_write_32_pd(A, V) m68ki_write_32_pd_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) +#else +#define m68ki_write_32_pd(A, V) m68ki_write_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA, V) +#endif + +/* map read immediate 8 to read immediate 16 */ +#define m68ki_read_imm_8() MASK_OUT_ABOVE_8(m68ki_read_imm_16()) + +/* Map PC-relative reads */ +#define m68ki_read_pcrel_8(A) m68k_read_pcrelative_8(A) +#define m68ki_read_pcrel_16(A) m68k_read_pcrelative_16(A) +#define m68ki_read_pcrel_32(A) m68k_read_pcrelative_32(A) + +/* Read from the program space */ +#define m68ki_read_program_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM) +#define m68ki_read_program_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM) +#define m68ki_read_program_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_PROGRAM) + +/* Read from the data space */ +#define m68ki_read_data_8(A) m68ki_read_8_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA) +#define m68ki_read_data_16(A) m68ki_read_16_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA) +#define m68ki_read_data_32(A) m68ki_read_32_fc(A, FLAG_S | FUNCTION_CODE_USER_DATA) + + + +/* ======================================================================== */ +/* =============================== PROTOTYPES ============================= */ +/* ======================================================================== */ + +typedef struct +{ + uint cpu_type; /* CPU Type: 68000, 68010, 68EC020, or 68020 */ + uint dar[16]; /* Data and Address Registers */ + uint ppc; /* Previous program counter */ + uint pc; /* Program Counter */ + uint sp[7]; /* User, Interrupt, and Master Stack Pointers */ + uint vbr; /* Vector Base Register (m68010+) */ + uint sfc; /* Source Function Code Register (m68010+) */ + uint dfc; /* Destination Function Code Register (m68010+) */ + uint cacr; /* Cache Control Register (m68020, unemulated) */ + uint caar; /* Cache Address Register (m68020, unemulated) */ + uint ir; /* Instruction Register */ + uint t1_flag; /* Trace 1 */ + uint t0_flag; /* Trace 0 */ + uint s_flag; /* Supervisor */ + uint m_flag; /* Master/Interrupt state */ + uint x_flag; /* Extend */ + uint n_flag; /* Negative */ + uint not_z_flag; /* Zero, inverted for speedups */ + uint v_flag; /* Overflow */ + uint c_flag; /* Carry */ + uint int_mask; /* I0-I2 */ + uint int_level; /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */ + uint int_cycles; /* ASG: extra cycles from generated interrupts */ + uint stopped; /* Stopped state */ + uint pref_addr; /* Last prefetch address */ + uint pref_data; /* Data in the prefetch queue */ + uint address_mask; /* Available address pins */ + uint sr_mask; /* Implemented status register bits */ + uint instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */ + uint run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */ + + /* Clocks required for instructions / exceptions */ + uint cyc_bcc_notake_b; + uint cyc_bcc_notake_w; + uint cyc_dbcc_f_noexp; + uint cyc_dbcc_f_exp; + uint cyc_scc_r_true; + uint cyc_movem_w; + uint cyc_movem_l; + uint cyc_shift; + uint cyc_reset; + uint8* cyc_instruction; + uint8* cyc_exception; + + /* Callbacks to host */ + int (*int_ack_callback)(int int_line); /* Interrupt Acknowledge */ + void (*bkpt_ack_callback)(unsigned int data); /* Breakpoint Acknowledge */ + void (*reset_instr_callback)(void); /* Called when a RESET instruction is encountered */ + void (*pc_changed_callback)(unsigned int new_pc); /* Called when the PC changes by a large amount */ + void (*set_fc_callback)(unsigned int new_fc); /* Called when the CPU function code changes */ + void (*instr_hook_callback)(void); /* Called every instruction cycle prior to execution */ + +} m68ki_cpu_core; + + +extern m68ki_cpu_core m68ki_cpu; +extern sint m68ki_remaining_cycles; +extern uint m68ki_tracing; +extern const uint8 m68ki_shift_8_table[]; +extern const uint16 m68ki_shift_16_table[]; +extern const uint m68ki_shift_32_table[]; +extern uint8 m68ki_exception_cycle_table[][256]; +extern uint m68ki_address_space; +extern uint8 m68ki_ea_idx_cycle_table[]; + +extern uint m68ki_aerr_address; +extern uint m68ki_aerr_write_mode; +extern uint m68ki_aerr_fc; + +/* Read data immediately after the program counter */ +INLINE uint m68ki_read_imm_16(void); +INLINE uint m68ki_read_imm_32(void); + +/* Read data with specific function code */ +INLINE uint m68ki_read_8_fc (uint address, uint fc); +INLINE uint m68ki_read_16_fc (uint address, uint fc); +INLINE uint m68ki_read_32_fc (uint address, uint fc); + +/* Write data with specific function code */ +INLINE void m68ki_write_8_fc (uint address, uint fc, uint value); +INLINE void m68ki_write_16_fc(uint address, uint fc, uint value); +INLINE void m68ki_write_32_fc(uint address, uint fc, uint value); +#if M68K_SIMULATE_PD_WRITES +INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value); +#endif /* M68K_SIMULATE_PD_WRITES */ + +/* Indexed and PC-relative ea fetching */ +INLINE uint m68ki_get_ea_pcdi(void); +INLINE uint m68ki_get_ea_pcix(void); +INLINE uint m68ki_get_ea_ix(uint An); + +/* Operand fetching */ +INLINE uint OPER_AY_AI_8(void); +INLINE uint OPER_AY_AI_16(void); +INLINE uint OPER_AY_AI_32(void); +INLINE uint OPER_AY_PI_8(void); +INLINE uint OPER_AY_PI_16(void); +INLINE uint OPER_AY_PI_32(void); +INLINE uint OPER_AY_PD_8(void); +INLINE uint OPER_AY_PD_16(void); +INLINE uint OPER_AY_PD_32(void); +INLINE uint OPER_AY_DI_8(void); +INLINE uint OPER_AY_DI_16(void); +INLINE uint OPER_AY_DI_32(void); +INLINE uint OPER_AY_IX_8(void); +INLINE uint OPER_AY_IX_16(void); +INLINE uint OPER_AY_IX_32(void); + +INLINE uint OPER_AX_AI_8(void); +INLINE uint OPER_AX_AI_16(void); +INLINE uint OPER_AX_AI_32(void); +INLINE uint OPER_AX_PI_8(void); +INLINE uint OPER_AX_PI_16(void); +INLINE uint OPER_AX_PI_32(void); +INLINE uint OPER_AX_PD_8(void); +INLINE uint OPER_AX_PD_16(void); +INLINE uint OPER_AX_PD_32(void); +INLINE uint OPER_AX_DI_8(void); +INLINE uint OPER_AX_DI_16(void); +INLINE uint OPER_AX_DI_32(void); +INLINE uint OPER_AX_IX_8(void); +INLINE uint OPER_AX_IX_16(void); +INLINE uint OPER_AX_IX_32(void); + +INLINE uint OPER_A7_PI_8(void); +INLINE uint OPER_A7_PD_8(void); + +INLINE uint OPER_AW_8(void); +INLINE uint OPER_AW_16(void); +INLINE uint OPER_AW_32(void); +INLINE uint OPER_AL_8(void); +INLINE uint OPER_AL_16(void); +INLINE uint OPER_AL_32(void); +INLINE uint OPER_PCDI_8(void); +INLINE uint OPER_PCDI_16(void); +INLINE uint OPER_PCDI_32(void); +INLINE uint OPER_PCIX_8(void); +INLINE uint OPER_PCIX_16(void); +INLINE uint OPER_PCIX_32(void); + +/* Stack operations */ +INLINE void m68ki_push_16(uint value); +INLINE void m68ki_push_32(uint value); +INLINE uint m68ki_pull_16(void); +INLINE uint m68ki_pull_32(void); + +/* Program flow operations */ +INLINE void m68ki_jump(uint new_pc); +INLINE void m68ki_jump_vector(uint vector); +INLINE void m68ki_branch_8(uint offset); +INLINE void m68ki_branch_16(uint offset); +INLINE void m68ki_branch_32(uint offset); + +/* Status register operations. */ +INLINE void m68ki_set_s_flag(uint value); /* Only bit 2 of value should be set (i.e. 4 or 0) */ +INLINE void m68ki_set_sm_flag(uint value); /* only bits 1 and 2 of value should be set */ +INLINE void m68ki_set_ccr(uint value); /* set the condition code register */ +INLINE void m68ki_set_sr(uint value); /* set the status register */ +INLINE void m68ki_set_sr_noint(uint value); /* set the status register */ + +/* Exception processing */ +INLINE uint m68ki_init_exception(void); /* Initial exception processing */ + +INLINE void m68ki_stack_frame_3word(uint pc, uint sr); /* Stack various frame types */ +INLINE void m68ki_stack_frame_buserr(uint sr); + +INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector); +INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector); +INLINE void m68ki_stack_frame_0010(uint sr, uint vector); +INLINE void m68ki_stack_frame_1000(uint pc, uint sr, uint vector); +INLINE void m68ki_stack_frame_1010(uint sr, uint vector, uint pc); +INLINE void m68ki_stack_frame_1011(uint sr, uint vector, uint pc); + +INLINE void m68ki_exception_trap(uint vector); +INLINE void m68ki_exception_trapN(uint vector); +INLINE void m68ki_exception_trace(void); +INLINE void m68ki_exception_privilege_violation(void); +INLINE void m68ki_exception_1010(void); +INLINE void m68ki_exception_1111(void); +INLINE void m68ki_exception_illegal(void); +INLINE void m68ki_exception_format_error(void); +INLINE void m68ki_exception_address_error(void); +INLINE void m68ki_exception_interrupt(uint int_level); +INLINE void m68ki_check_interrupts(void); /* ASG: check for interrupts */ + +/* quick disassembly (used for logging) */ +char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type); + + +/* ======================================================================== */ +/* =========================== UTILITY FUNCTIONS ========================== */ +/* ======================================================================== */ + + +/* ---------------------------- Read Immediate ---------------------------- */ + +/* Handles all immediate reads, does address error check, function code setting, + * and prefetching if they are enabled in m68kconf.h + */ +INLINE uint m68ki_read_imm_16(void) +{ + m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ +#if M68K_EMULATE_PREFETCH + if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR) + { + CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC); + CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR)); + } + REG_PC += 2; + return MASK_OUT_ABOVE_16(CPU_PREF_DATA >> ((2-((REG_PC-2)&2))<<3)); +#else + REG_PC += 2; + return m68k_read_immediate_16(ADDRESS_68K(REG_PC-2)); +#endif /* M68K_EMULATE_PREFETCH */ +} +INLINE uint m68ki_read_imm_32(void) +{ +#if M68K_EMULATE_PREFETCH + uint temp_val; + + m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR) + { + CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC); + CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR)); + } + temp_val = CPU_PREF_DATA; + REG_PC += 2; + if(MASK_OUT_BELOW_2(REG_PC) != CPU_PREF_ADDR) + { + CPU_PREF_ADDR = MASK_OUT_BELOW_2(REG_PC); + CPU_PREF_DATA = m68k_read_immediate_32(ADDRESS_68K(CPU_PREF_ADDR)); + temp_val = MASK_OUT_ABOVE_32((temp_val << 16) | (CPU_PREF_DATA >> 16)); + } + REG_PC += 2; + + return temp_val; +#else + m68ki_set_fc(FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(REG_PC, MODE_READ, FLAG_S | FUNCTION_CODE_USER_PROGRAM); /* auto-disable (see m68kcpu.h) */ + REG_PC += 4; + return m68k_read_immediate_32(ADDRESS_68K(REG_PC-4)); +#endif /* M68K_EMULATE_PREFETCH */ +} + + + +/* ------------------------- Top level read/write ------------------------- */ + +/* Handles all memory accesses (except for immediate reads if they are + * configured to use separate functions in m68kconf.h). + * All memory accesses must go through these top level functions. + * These functions will also check for address error and set the function + * code if they are enabled in m68kconf.h. + */ +INLINE uint m68ki_read_8_fc(uint address, uint fc) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + return m68k_read_memory_8(ADDRESS_68K(address)); +} +INLINE uint m68ki_read_16_fc(uint address, uint fc) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */ + return m68k_read_memory_16(ADDRESS_68K(address)); +} +INLINE uint m68ki_read_32_fc(uint address, uint fc) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(address, MODE_READ, fc); /* auto-disable (see m68kcpu.h) */ + return m68k_read_memory_32(ADDRESS_68K(address)); +} + +INLINE void m68ki_write_8_fc(uint address, uint fc, uint value) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68k_write_memory_8(ADDRESS_68K(address), value); +} +INLINE void m68ki_write_16_fc(uint address, uint fc, uint value) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */ + m68k_write_memory_16(ADDRESS_68K(address), value); +} +INLINE void m68ki_write_32_fc(uint address, uint fc, uint value) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */ + m68k_write_memory_32(ADDRESS_68K(address), value); +} + +#if M68K_SIMULATE_PD_WRITES +INLINE void m68ki_write_32_pd_fc(uint address, uint fc, uint value) +{ + m68ki_set_fc(fc); /* auto-disable (see m68kcpu.h) */ + m68ki_check_address_error(address, MODE_WRITE, fc); /* auto-disable (see m68kcpu.h) */ + m68k_write_memory_32_pd(ADDRESS_68K(address), value); +} +#endif + + +/* --------------------- Effective Address Calculation -------------------- */ + +/* The program counter relative addressing modes cause operands to be + * retrieved from program space, not data space. + */ +INLINE uint m68ki_get_ea_pcdi(void) +{ + uint old_pc = REG_PC; + m68ki_use_program_space(); /* auto-disable */ + return old_pc + MAKE_INT_16(m68ki_read_imm_16()); +} + + +INLINE uint m68ki_get_ea_pcix(void) +{ + m68ki_use_program_space(); /* auto-disable */ + return m68ki_get_ea_ix(REG_PC); +} + +/* Indexed addressing modes are encoded as follows: + * + * Base instruction format: + * F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 + * x x x x x x x x x x | 1 1 0 | BASE REGISTER (An) + * + * Base instruction format for destination EA in move instructions: + * F E D C | B A 9 | 8 7 6 | 5 4 3 2 1 0 + * x x x x | BASE REG | 1 1 0 | X X X X X X (An) + * + * Brief extension format: + * F | E D C | B | A 9 | 8 | 7 6 5 4 3 2 1 0 + * D/A | REGISTER | W/L | SCALE | 0 | DISPLACEMENT + * + * Full extension format: + * F E D C B A 9 8 7 6 5 4 3 2 1 0 + * D/A | REGISTER | W/L | SCALE | 1 | BS | IS | BD SIZE | 0 | I/IS + * BASE DISPLACEMENT (0, 16, 32 bit) (bd) + * OUTER DISPLACEMENT (0, 16, 32 bit) (od) + * + * D/A: 0 = Dn, 1 = An (Xn) + * W/L: 0 = W (sign extend), 1 = L (.SIZE) + * SCALE: 00=1, 01=2, 10=4, 11=8 (*SCALE) + * BS: 0=add base reg, 1=suppress base reg (An suppressed) + * IS: 0=add index, 1=suppress index (Xn suppressed) + * BD SIZE: 00=reserved, 01=NULL, 10=Word, 11=Long (size of bd) + * + * IS I/IS Operation + * 0 000 No Memory Indirect + * 0 001 indir prex with null outer + * 0 010 indir prex with word outer + * 0 011 indir prex with long outer + * 0 100 reserved + * 0 101 indir postx with null outer + * 0 110 indir postx with word outer + * 0 111 indir postx with long outer + * 1 000 no memory indirect + * 1 001 mem indir with null outer + * 1 010 mem indir with word outer + * 1 011 mem indir with long outer + * 1 100-111 reserved + */ +INLINE uint m68ki_get_ea_ix(uint An) +{ + /* An = base register */ + uint extension = m68ki_read_imm_16(); + uint Xn = 0; /* Index register */ + uint bd = 0; /* Base Displacement */ + uint od = 0; /* Outer Displacement */ + + if(CPU_TYPE_IS_010_LESS(CPU_TYPE)) + { + /* Calculate index */ + Xn = REG_DA[extension>>12]; /* Xn */ + if(!BIT_B(extension)) /* W/L */ + Xn = MAKE_INT_16(Xn); + + /* Add base register and displacement and return */ + return An + Xn + MAKE_INT_8(extension); + } + + /* Brief extension format */ + if(!BIT_8(extension)) + { + /* Calculate index */ + Xn = REG_DA[extension>>12]; /* Xn */ + if(!BIT_B(extension)) /* W/L */ + Xn = MAKE_INT_16(Xn); + /* Add scale if proper CPU type */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + Xn <<= (extension>>9) & 3; /* SCALE */ + + /* Add base register and displacement and return */ + return An + Xn + MAKE_INT_8(extension); + } + + /* Full extension format */ + + USE_CYCLES(m68ki_ea_idx_cycle_table[extension&0x3f]); + + /* Check if base register is present */ + if(BIT_7(extension)) /* BS */ + An = 0; /* An */ + + /* Check if index is present */ + if(!BIT_6(extension)) /* IS */ + { + Xn = REG_DA[extension>>12]; /* Xn */ + if(!BIT_B(extension)) /* W/L */ + Xn = MAKE_INT_16(Xn); + Xn <<= (extension>>9) & 3; /* SCALE */ + } + + /* Check if base displacement is present */ + if(BIT_5(extension)) /* BD SIZE */ + bd = BIT_4(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16()); + + /* If no indirect action, we are done */ + if(!(extension&7)) /* No Memory Indirect */ + return An + bd + Xn; + + /* Check if outer displacement is present */ + if(BIT_1(extension)) /* I/IS: od */ + od = BIT_0(extension) ? m68ki_read_imm_32() : MAKE_INT_16(m68ki_read_imm_16()); + + /* Postindex */ + if(BIT_2(extension)) /* I/IS: 0 = preindex, 1 = postindex */ + return m68ki_read_32(An + bd) + Xn + od; + + /* Preindex */ + return m68ki_read_32(An + bd + Xn) + od; +} + + +/* Fetch operands */ +INLINE uint OPER_AY_AI_8(void) {uint ea = EA_AY_AI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_AI_16(void) {uint ea = EA_AY_AI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_AI_32(void) {uint ea = EA_AY_AI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AY_PI_8(void) {uint ea = EA_AY_PI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_PI_16(void) {uint ea = EA_AY_PI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_PI_32(void) {uint ea = EA_AY_PI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AY_PD_8(void) {uint ea = EA_AY_PD_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_PD_16(void) {uint ea = EA_AY_PD_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_PD_32(void) {uint ea = EA_AY_PD_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AY_DI_8(void) {uint ea = EA_AY_DI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_DI_16(void) {uint ea = EA_AY_DI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_DI_32(void) {uint ea = EA_AY_DI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AY_IX_8(void) {uint ea = EA_AY_IX_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AY_IX_16(void) {uint ea = EA_AY_IX_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AY_IX_32(void) {uint ea = EA_AY_IX_32(); return m68ki_read_32(ea);} + +INLINE uint OPER_AX_AI_8(void) {uint ea = EA_AX_AI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_AI_16(void) {uint ea = EA_AX_AI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_AI_32(void) {uint ea = EA_AX_AI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AX_PI_8(void) {uint ea = EA_AX_PI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_PI_16(void) {uint ea = EA_AX_PI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_PI_32(void) {uint ea = EA_AX_PI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AX_PD_8(void) {uint ea = EA_AX_PD_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_PD_16(void) {uint ea = EA_AX_PD_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_PD_32(void) {uint ea = EA_AX_PD_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AX_DI_8(void) {uint ea = EA_AX_DI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_DI_16(void) {uint ea = EA_AX_DI_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_DI_32(void) {uint ea = EA_AX_DI_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AX_IX_8(void) {uint ea = EA_AX_IX_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AX_IX_16(void) {uint ea = EA_AX_IX_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AX_IX_32(void) {uint ea = EA_AX_IX_32(); return m68ki_read_32(ea);} + +INLINE uint OPER_A7_PI_8(void) {uint ea = EA_A7_PI_8(); return m68ki_read_8(ea); } +INLINE uint OPER_A7_PD_8(void) {uint ea = EA_A7_PD_8(); return m68ki_read_8(ea); } + +INLINE uint OPER_AW_8(void) {uint ea = EA_AW_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AW_16(void) {uint ea = EA_AW_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AW_32(void) {uint ea = EA_AW_32(); return m68ki_read_32(ea);} +INLINE uint OPER_AL_8(void) {uint ea = EA_AL_8(); return m68ki_read_8(ea); } +INLINE uint OPER_AL_16(void) {uint ea = EA_AL_16(); return m68ki_read_16(ea);} +INLINE uint OPER_AL_32(void) {uint ea = EA_AL_32(); return m68ki_read_32(ea);} +INLINE uint OPER_PCDI_8(void) {uint ea = EA_PCDI_8(); return m68ki_read_pcrel_8(ea); } +INLINE uint OPER_PCDI_16(void) {uint ea = EA_PCDI_16(); return m68ki_read_pcrel_16(ea);} +INLINE uint OPER_PCDI_32(void) {uint ea = EA_PCDI_32(); return m68ki_read_pcrel_32(ea);} +INLINE uint OPER_PCIX_8(void) {uint ea = EA_PCIX_8(); return m68ki_read_pcrel_8(ea); } +INLINE uint OPER_PCIX_16(void) {uint ea = EA_PCIX_16(); return m68ki_read_pcrel_16(ea);} +INLINE uint OPER_PCIX_32(void) {uint ea = EA_PCIX_32(); return m68ki_read_pcrel_32(ea);} + + + +/* ---------------------------- Stack Functions --------------------------- */ + +/* Push/pull data from the stack */ +INLINE void m68ki_push_16(uint value) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); + m68ki_write_16(REG_SP, value); +} + +INLINE void m68ki_push_32(uint value) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); + m68ki_write_32(REG_SP, value); +} + +INLINE uint m68ki_pull_16(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); + return m68ki_read_16(REG_SP-2); +} + +INLINE uint m68ki_pull_32(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); + return m68ki_read_32(REG_SP-4); +} + + +/* Increment/decrement the stack as if doing a push/pull but + * don't do any memory access. + */ +INLINE void m68ki_fake_push_16(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 2); +} + +INLINE void m68ki_fake_push_32(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP - 4); +} + +INLINE void m68ki_fake_pull_16(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 2); +} + +INLINE void m68ki_fake_pull_32(void) +{ + REG_SP = MASK_OUT_ABOVE_32(REG_SP + 4); +} + + +/* ----------------------------- Program Flow ----------------------------- */ + +/* Jump to a new program location or vector. + * These functions will also call the pc_changed callback if it was enabled + * in m68kconf.h. + */ +INLINE void m68ki_jump(uint new_pc) +{ + REG_PC = new_pc; + m68ki_pc_changed(REG_PC); +} + +INLINE void m68ki_jump_vector(uint vector) +{ + REG_PC = (vector<<2) + REG_VBR; + REG_PC = m68ki_read_data_32(REG_PC); + m68ki_pc_changed(REG_PC); +} + + +/* Branch to a new memory location. + * The 32-bit branch will call pc_changed if it was enabled in m68kconf.h. + * So far I've found no problems with not calling pc_changed for 8 or 16 + * bit branches. + */ +INLINE void m68ki_branch_8(uint offset) +{ + REG_PC += MAKE_INT_8(offset); +} + +INLINE void m68ki_branch_16(uint offset) +{ + REG_PC += MAKE_INT_16(offset); +} + +INLINE void m68ki_branch_32(uint offset) +{ + REG_PC += offset; + m68ki_pc_changed(REG_PC); +} + + + +/* ---------------------------- Status Register --------------------------- */ + +/* Set the S flag and change the active stack pointer. + * Note that value MUST be 4 or 0. + */ +INLINE void m68ki_set_s_flag(uint value) +{ + /* Backup the old stack pointer */ + REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP; + /* Set the S flag */ + FLAG_S = value; + /* Set the new stack pointer */ + REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)]; +} + +/* Set the S and M flags and change the active stack pointer. + * Note that value MUST be 0, 2, 4, or 6 (bit2 = S, bit1 = M). + */ +INLINE void m68ki_set_sm_flag(uint value) +{ + /* Backup the old stack pointer */ + REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)] = REG_SP; + /* Set the S and M flags */ + FLAG_S = value & SFLAG_SET; + FLAG_M = value & MFLAG_SET; + /* Set the new stack pointer */ + REG_SP = REG_SP_BASE[FLAG_S | ((FLAG_S>>1) & FLAG_M)]; +} + +/* Set the S and M flags. Don't touch the stack pointer. */ +INLINE void m68ki_set_sm_flag_nosp(uint value) +{ + /* Set the S and M flags */ + FLAG_S = value & SFLAG_SET; + FLAG_M = value & MFLAG_SET; +} + + +/* Set the condition code register */ +INLINE void m68ki_set_ccr(uint value) +{ + FLAG_X = BIT_4(value) << 4; + FLAG_N = BIT_3(value) << 4; + FLAG_Z = !BIT_2(value); + FLAG_V = BIT_1(value) << 6; + FLAG_C = BIT_0(value) << 8; +} + +/* Set the status register but don't check for interrupts */ +INLINE void m68ki_set_sr_noint(uint value) +{ + /* Mask out the "unimplemented" bits */ + value &= CPU_SR_MASK; + + /* Now set the status register */ + FLAG_T1 = BIT_F(value); + FLAG_T0 = BIT_E(value); + FLAG_INT_MASK = value & 0x0700; + m68ki_set_ccr(value); + m68ki_set_sm_flag((value >> 11) & 6); +} + +/* Set the status register but don't check for interrupts nor + * change the stack pointer + */ +INLINE void m68ki_set_sr_noint_nosp(uint value) +{ + /* Mask out the "unimplemented" bits */ + value &= CPU_SR_MASK; + + /* Now set the status register */ + FLAG_T1 = BIT_F(value); + FLAG_T0 = BIT_E(value); + FLAG_INT_MASK = value & 0x0700; + m68ki_set_ccr(value); + m68ki_set_sm_flag_nosp((value >> 11) & 6); +} + +/* Set the status register and check for interrupts */ +INLINE void m68ki_set_sr(uint value) +{ + m68ki_set_sr_noint(value); + m68ki_check_interrupts(); +} + + +/* ------------------------- Exception Processing ------------------------- */ + +/* Initiate exception processing */ +INLINE uint m68ki_init_exception(void) +{ + /* Save the old status register */ + uint sr = m68ki_get_sr(); + + /* Turn off trace flag, clear pending traces */ + FLAG_T1 = FLAG_T0 = 0; + m68ki_clear_trace(); + /* Enter supervisor mode */ + m68ki_set_s_flag(SFLAG_SET); + + return sr; +} + +/* 3 word stack frame (68000 only) */ +INLINE void m68ki_stack_frame_3word(uint pc, uint sr) +{ + m68ki_push_32(pc); + m68ki_push_16(sr); +} + +/* Format 0 stack frame. + * This is the standard stack frame for 68010+. + */ +INLINE void m68ki_stack_frame_0000(uint pc, uint sr, uint vector) +{ + /* Stack a 3-word frame if we are 68000 */ + if(CPU_TYPE == CPU_TYPE_000) + { + m68ki_stack_frame_3word(pc, sr); + return; + } + m68ki_push_16(vector<<2); + m68ki_push_32(pc); + m68ki_push_16(sr); +} + +/* Format 1 stack frame (68020). + * For 68020, this is the 4 word throwaway frame. + */ +INLINE void m68ki_stack_frame_0001(uint pc, uint sr, uint vector) +{ + m68ki_push_16(0x1000 | (vector<<2)); + m68ki_push_32(pc); + m68ki_push_16(sr); +} + +/* Format 2 stack frame. + * This is used only by 68020 for trap exceptions. + */ +INLINE void m68ki_stack_frame_0010(uint sr, uint vector) +{ + m68ki_push_32(REG_PPC); + m68ki_push_16(0x2000 | (vector<<2)); + m68ki_push_32(REG_PC); + m68ki_push_16(sr); +} + + +/* Bus error stack frame (68000 only). + */ +INLINE void m68ki_stack_frame_buserr(uint sr) +{ + m68ki_push_32(REG_PC); + m68ki_push_16(sr); + m68ki_push_16(REG_IR); + m68ki_push_32(m68ki_aerr_address); /* access address */ + /* 0 0 0 0 0 0 0 0 0 0 0 R/W I/N FC + * R/W 0 = write, 1 = read + * I/N 0 = instruction, 1 = not + * FC 3-bit function code + */ + m68ki_push_16(m68ki_aerr_write_mode | CPU_INSTR_MODE | m68ki_aerr_fc); +} + +/* Format 8 stack frame (68010). + * 68010 only. This is the 29 word bus/address error frame. + */ +void m68ki_stack_frame_1000(uint pc, uint sr, uint vector) +{ + /* VERSION + * NUMBER + * INTERNAL INFORMATION, 16 WORDS + */ + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + m68ki_fake_push_32(); + + /* INSTRUCTION INPUT BUFFER */ + m68ki_push_16(0); + + /* UNUSED, RESERVED (not written) */ + m68ki_fake_push_16(); + + /* DATA INPUT BUFFER */ + m68ki_push_16(0); + + /* UNUSED, RESERVED (not written) */ + m68ki_fake_push_16(); + + /* DATA OUTPUT BUFFER */ + m68ki_push_16(0); + + /* UNUSED, RESERVED (not written) */ + m68ki_fake_push_16(); + + /* FAULT ADDRESS */ + m68ki_push_32(0); + + /* SPECIAL STATUS WORD */ + m68ki_push_16(0); + + /* 1000, VECTOR OFFSET */ + m68ki_push_16(0x8000 | (vector<<2)); + + /* PROGRAM COUNTER */ + m68ki_push_32(pc); + + /* STATUS REGISTER */ + m68ki_push_16(sr); +} + +/* Format A stack frame (short bus fault). + * This is used only by 68020 for bus fault and address error + * if the error happens at an instruction boundary. + * PC stacked is address of next instruction. + */ +void m68ki_stack_frame_1010(uint sr, uint vector, uint pc) +{ + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* DATA OUTPUT BUFFER (2 words) */ + m68ki_push_32(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* DATA CYCLE FAULT ADDRESS (2 words) */ + m68ki_push_32(0); + + /* INSTRUCTION PIPE STAGE B */ + m68ki_push_16(0); + + /* INSTRUCTION PIPE STAGE C */ + m68ki_push_16(0); + + /* SPECIAL STATUS REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* 1010, VECTOR OFFSET */ + m68ki_push_16(0xa000 | (vector<<2)); + + /* PROGRAM COUNTER */ + m68ki_push_32(pc); + + /* STATUS REGISTER */ + m68ki_push_16(sr); +} + +/* Format B stack frame (long bus fault). + * This is used only by 68020 for bus fault and address error + * if the error happens during instruction execution. + * PC stacked is address of instruction in progress. + */ +void m68ki_stack_frame_1011(uint sr, uint vector, uint pc) +{ + /* INTERNAL REGISTERS (18 words) */ + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + m68ki_push_32(0); + + /* VERSION# (4 bits), INTERNAL INFORMATION */ + m68ki_push_16(0); + + /* INTERNAL REGISTERS (3 words) */ + m68ki_push_32(0); + m68ki_push_16(0); + + /* DATA INTPUT BUFFER (2 words) */ + m68ki_push_32(0); + + /* INTERNAL REGISTERS (2 words) */ + m68ki_push_32(0); + + /* STAGE B ADDRESS (2 words) */ + m68ki_push_32(0); + + /* INTERNAL REGISTER (4 words) */ + m68ki_push_32(0); + m68ki_push_32(0); + + /* DATA OUTPUT BUFFER (2 words) */ + m68ki_push_32(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* DATA CYCLE FAULT ADDRESS (2 words) */ + m68ki_push_32(0); + + /* INSTRUCTION PIPE STAGE B */ + m68ki_push_16(0); + + /* INSTRUCTION PIPE STAGE C */ + m68ki_push_16(0); + + /* SPECIAL STATUS REGISTER */ + m68ki_push_16(0); + + /* INTERNAL REGISTER */ + m68ki_push_16(0); + + /* 1011, VECTOR OFFSET */ + m68ki_push_16(0xb000 | (vector<<2)); + + /* PROGRAM COUNTER */ + m68ki_push_32(pc); + + /* STATUS REGISTER */ + m68ki_push_16(sr); +} + + +/* Used for Group 2 exceptions. + * These stack a type 2 frame on the 020. + */ +INLINE void m68ki_exception_trap(uint vector) +{ + uint sr = m68ki_init_exception(); + + if(CPU_TYPE_IS_010_LESS(CPU_TYPE)) + m68ki_stack_frame_0000(REG_PC, sr, vector); + else + m68ki_stack_frame_0010(sr, vector); + + m68ki_jump_vector(vector); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[vector] - CYC_INSTRUCTION[REG_IR]); +} + +/* Trap#n stacks a 0 frame but behaves like group2 otherwise */ +INLINE void m68ki_exception_trapN(uint vector) +{ + uint sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PC, sr, vector); + m68ki_jump_vector(vector); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[vector] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for trace mode */ +INLINE void m68ki_exception_trace(void) +{ + uint sr = m68ki_init_exception(); + + if(CPU_TYPE_IS_010_LESS(CPU_TYPE)) + { + #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON + if(CPU_TYPE_IS_000(CPU_TYPE)) + { + CPU_INSTR_MODE = INSTRUCTION_NO; + } + #endif /* M68K_EMULATE_ADDRESS_ERROR */ + m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_TRACE); + } + else + m68ki_stack_frame_0010(sr, EXCEPTION_TRACE); + + m68ki_jump_vector(EXCEPTION_TRACE); + + /* Trace nullifies a STOP instruction */ + CPU_STOPPED &= ~STOP_LEVEL_STOP; + + /* Use up some clock cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_TRACE]); +} + +/* Exception for privilege violation */ +INLINE void m68ki_exception_privilege_violation(void) +{ + uint sr = m68ki_init_exception(); + + #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON + if(CPU_TYPE_IS_000(CPU_TYPE)) + { + CPU_INSTR_MODE = INSTRUCTION_NO; + } + #endif /* M68K_EMULATE_ADDRESS_ERROR */ + + m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_PRIVILEGE_VIOLATION); + m68ki_jump_vector(EXCEPTION_PRIVILEGE_VIOLATION); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_PRIVILEGE_VIOLATION] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for A-Line instructions */ +INLINE void m68ki_exception_1010(void) +{ + uint sr; +#if M68K_LOG_1010_1111 == OPT_ON + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1010 instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, + m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); +#endif + + sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1010); + m68ki_jump_vector(EXCEPTION_1010); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1010] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for F-Line instructions */ +INLINE void m68ki_exception_1111(void) +{ + uint sr; + +#if M68K_LOG_1010_1111 == OPT_ON + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: called 1111 instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, + m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); +#endif + + sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_1111); + m68ki_jump_vector(EXCEPTION_1111); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_1111] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for illegal instructions */ +INLINE void m68ki_exception_illegal(void) +{ + uint sr; + + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: illegal instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PPC), REG_IR, + m68ki_disassemble_quick(ADDRESS_68K(REG_PPC)))); + + sr = m68ki_init_exception(); + + #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON + if(CPU_TYPE_IS_000(CPU_TYPE)) + { + CPU_INSTR_MODE = INSTRUCTION_NO; + } + #endif /* M68K_EMULATE_ADDRESS_ERROR */ + + m68ki_stack_frame_0000(REG_PPC, sr, EXCEPTION_ILLEGAL_INSTRUCTION); + m68ki_jump_vector(EXCEPTION_ILLEGAL_INSTRUCTION); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ILLEGAL_INSTRUCTION] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for format errror in RTE */ +INLINE void m68ki_exception_format_error(void) +{ + uint sr = m68ki_init_exception(); + m68ki_stack_frame_0000(REG_PC, sr, EXCEPTION_FORMAT_ERROR); + m68ki_jump_vector(EXCEPTION_FORMAT_ERROR); + + /* Use up some clock cycles and undo the instruction's cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_FORMAT_ERROR] - CYC_INSTRUCTION[REG_IR]); +} + +/* Exception for address error */ +INLINE void m68ki_exception_address_error(void) +{ + uint sr = m68ki_init_exception(); + + /* If we were processing a bus error, address error, or reset, + * this is a catastrophic failure. + * Halt the CPU + */ + if(CPU_RUN_MODE == RUN_MODE_BERR_AERR_RESET) + { +m68k_read_memory_8(0x00ffff01); + CPU_STOPPED = STOP_LEVEL_HALT; + return; + } + CPU_RUN_MODE = RUN_MODE_BERR_AERR_RESET; + + /* Note: This is implemented for 68000 only! */ + m68ki_stack_frame_buserr(sr); + + m68ki_jump_vector(EXCEPTION_ADDRESS_ERROR); + + /* Use up some clock cycles. Note that we don't need to undo the + instruction's cycles here as we've longjmp:ed directly from the + instruction handler without passing the part of the excecute loop + that deducts instruction cycles */ + USE_CYCLES(CYC_EXCEPTION[EXCEPTION_ADDRESS_ERROR]); +} + + +/* Service an interrupt request and start exception processing */ +void m68ki_exception_interrupt(uint int_level) +{ + uint vector; + uint sr; + uint new_pc; + + #if M68K_EMULATE_ADDRESS_ERROR == OPT_ON + if(CPU_TYPE_IS_000(CPU_TYPE)) + { + CPU_INSTR_MODE = INSTRUCTION_NO; + } + #endif /* M68K_EMULATE_ADDRESS_ERROR */ + + /* Turn off the stopped state */ + CPU_STOPPED &= ~STOP_LEVEL_STOP; + + /* If we are halted, don't do anything */ + if(CPU_STOPPED) + return; + + /* Acknowledge the interrupt */ + vector = m68ki_int_ack(int_level); + + /* Get the interrupt vector */ + if(vector == M68K_INT_ACK_AUTOVECTOR) + /* Use the autovectors. This is the most commonly used implementation */ + vector = EXCEPTION_INTERRUPT_AUTOVECTOR+int_level; + else if(vector == M68K_INT_ACK_SPURIOUS) + /* Called if no devices respond to the interrupt acknowledge */ + vector = EXCEPTION_SPURIOUS_INTERRUPT; + else if(vector > 255) + { + M68K_DO_LOG_EMU((M68K_LOG_FILEHANDLE "%s at %08x: Interrupt acknowledge returned invalid vector $%x\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC), vector)); + return; + } + + /* Start exception processing */ + sr = m68ki_init_exception(); + + /* Set the interrupt mask to the level of the one being serviced */ + FLAG_INT_MASK = int_level<<8; + + /* Get the new PC */ + new_pc = m68ki_read_data_32((vector<<2) + REG_VBR); + + /* If vector is uninitialized, call the uninitialized interrupt vector */ + if(new_pc == 0) + new_pc = m68ki_read_data_32((EXCEPTION_UNINITIALIZED_INTERRUPT<<2) + REG_VBR); + + /* Generate a stack frame */ + m68ki_stack_frame_0000(REG_PC, sr, vector); + if(FLAG_M && CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Create throwaway frame */ + m68ki_set_sm_flag(FLAG_S); /* clear M */ + sr |= 0x2000; /* Same as SR in master stack frame except S is forced high */ + m68ki_stack_frame_0001(REG_PC, sr, vector); + } + + m68ki_jump(new_pc); + + /* Defer cycle counting until later */ + CPU_INT_CYCLES += CYC_EXCEPTION[vector]; + +#if !M68K_EMULATE_INT_ACK + /* Automatically clear IRQ if we are not using an acknowledge scheme */ + CPU_INT_LEVEL = 0; +#endif /* M68K_EMULATE_INT_ACK */ +} + + +/* ASG: Check for interrupts */ +INLINE void m68ki_check_interrupts(void) +{ + if(CPU_INT_LEVEL > FLAG_INT_MASK) + m68ki_exception_interrupt(CPU_INT_LEVEL>>8); +} + + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68KCPU__HEADER */ diff --git a/MCUME_teensy/teensygen/musashi34/m68kdasm.c b/MCUME_teensy/teensygen/musashi34/m68kdasm.c new file mode 100644 index 0000000..146da47 --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68kdasm.c @@ -0,0 +1,3477 @@ +/* ======================================================================== */ +/* ========================= LICENSING & COPYRIGHT ======================== */ +/* ======================================================================== */ +/* + * MUSASHI + * Version 3.4 + * + * A portable Motorola M680x0 processor emulation engine. + * Copyright 1998-2001 Karl Stenerud. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + + + +/* ======================================================================== */ +/* ================================ INCLUDES ============================== */ +/* ======================================================================== */ + +#include +#include +#include +#include "m68k.h" + +#ifndef DECL_SPEC +#define DECL_SPEC +#endif + +/* ======================================================================== */ +/* ============================ GENERAL DEFINES =========================== */ +/* ======================================================================== */ + +/* unsigned int and int must be at least 32 bits wide */ +#undef uint +#define uint unsigned int + +/* Bit Isolation Functions */ +#define BIT_0(A) ((A) & 0x00000001) +#define BIT_1(A) ((A) & 0x00000002) +#define BIT_2(A) ((A) & 0x00000004) +#define BIT_3(A) ((A) & 0x00000008) +#define BIT_4(A) ((A) & 0x00000010) +#define BIT_5(A) ((A) & 0x00000020) +#define BIT_6(A) ((A) & 0x00000040) +#define BIT_7(A) ((A) & 0x00000080) +#define BIT_8(A) ((A) & 0x00000100) +#define BIT_9(A) ((A) & 0x00000200) +#define BIT_A(A) ((A) & 0x00000400) +#define BIT_B(A) ((A) & 0x00000800) +#define BIT_C(A) ((A) & 0x00001000) +#define BIT_D(A) ((A) & 0x00002000) +#define BIT_E(A) ((A) & 0x00004000) +#define BIT_F(A) ((A) & 0x00008000) +#define BIT_10(A) ((A) & 0x00010000) +#define BIT_11(A) ((A) & 0x00020000) +#define BIT_12(A) ((A) & 0x00040000) +#define BIT_13(A) ((A) & 0x00080000) +#define BIT_14(A) ((A) & 0x00100000) +#define BIT_15(A) ((A) & 0x00200000) +#define BIT_16(A) ((A) & 0x00400000) +#define BIT_17(A) ((A) & 0x00800000) +#define BIT_18(A) ((A) & 0x01000000) +#define BIT_19(A) ((A) & 0x02000000) +#define BIT_1A(A) ((A) & 0x04000000) +#define BIT_1B(A) ((A) & 0x08000000) +#define BIT_1C(A) ((A) & 0x10000000) +#define BIT_1D(A) ((A) & 0x20000000) +#define BIT_1E(A) ((A) & 0x40000000) +#define BIT_1F(A) ((A) & 0x80000000) + +/* These are the CPU types understood by this disassembler */ +#define TYPE_68000 1 +#define TYPE_68010 2 +#define TYPE_68020 4 +#define TYPE_68030 8 +#define TYPE_68040 16 + +#define M68000_ONLY TYPE_68000 + +#define M68010_ONLY TYPE_68010 +#define M68010_LESS (TYPE_68000 | TYPE_68010) +#define M68010_PLUS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040) + +#define M68020_ONLY TYPE_68020 +#define M68020_LESS (TYPE_68010 | TYPE_68020) +#define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040) + +#define M68030_ONLY TYPE_68030 +#define M68030_LESS (TYPE_68010 | TYPE_68020 | TYPE_68030) +#define M68030_PLUS (TYPE_68030 | TYPE_68040) + +#define M68040_PLUS TYPE_68040 + + +/* Extension word formats */ +#define EXT_8BIT_DISPLACEMENT(A) ((A)&0xff) +#define EXT_FULL(A) BIT_8(A) +#define EXT_EFFECTIVE_ZERO(A) (((A)&0xe4) == 0xc4 || ((A)&0xe2) == 0xc0) +#define EXT_BASE_REGISTER_PRESENT(A) (!BIT_7(A)) +#define EXT_INDEX_REGISTER_PRESENT(A) (!BIT_6(A)) +#define EXT_INDEX_REGISTER(A) (((A)>>12)&7) +#define EXT_INDEX_PRE_POST(A) (EXT_INDEX_PRESENT(A) && (A)&3) +#define EXT_INDEX_PRE(A) (EXT_INDEX_PRESENT(A) && ((A)&7) < 4 && ((A)&7) != 0) +#define EXT_INDEX_POST(A) (EXT_INDEX_PRESENT(A) && ((A)&7) > 4) +#define EXT_INDEX_SCALE(A) (((A)>>9)&3) +#define EXT_INDEX_LONG(A) BIT_B(A) +#define EXT_INDEX_AR(A) BIT_F(A) +#define EXT_BASE_DISPLACEMENT_PRESENT(A) (((A)&0x30) > 0x10) +#define EXT_BASE_DISPLACEMENT_WORD(A) (((A)&0x30) == 0x20) +#define EXT_BASE_DISPLACEMENT_LONG(A) (((A)&0x30) == 0x30) +#define EXT_OUTER_DISPLACEMENT_PRESENT(A) (((A)&3) > 1 && ((A)&0x47) < 0x44) +#define EXT_OUTER_DISPLACEMENT_WORD(A) (((A)&3) == 2 && ((A)&0x47) < 0x44) +#define EXT_OUTER_DISPLACEMENT_LONG(A) (((A)&3) == 3 && ((A)&0x47) < 0x44) + + + +/* ======================================================================== */ +/* =============================== PROTOTYPES ============================= */ +/* ======================================================================== */ + +/* Read data at the PC and increment PC */ +uint read_imm_8(void); +uint read_imm_16(void); +uint read_imm_32(void); + +/* Read data at the PC but don't imcrement the PC */ +uint peek_imm_8(void); +uint peek_imm_16(void); +uint peek_imm_32(void); + +/* make signed integers 100% portably */ +static int make_int_8(int value); +static int make_int_16(int value); + +/* make a string of a hex value */ +static char* make_signed_hex_str_8(uint val); +static char* make_signed_hex_str_16(uint val); +static char* make_signed_hex_str_32(uint val); + +/* make string of ea mode */ +static char* get_ea_mode_str(uint instruction, uint size); + +char* get_ea_mode_str_8(uint instruction); +char* get_ea_mode_str_16(uint instruction); +char* get_ea_mode_str_32(uint instruction); + +/* make string of immediate value */ +static char* get_imm_str_s(uint size); +static char* get_imm_str_u(uint size); + +char* get_imm_str_s8(void); +char* get_imm_str_s16(void); +char* get_imm_str_s32(void); + +/* Stuff to build the opcode handler jump table */ +static void build_opcode_table(void); +static int valid_ea(uint opcode, uint mask); +static int DECL_SPEC compare_nof_true_bits(const void *aptr, const void *bptr); + +/* used to build opcode handler jump table */ +typedef struct +{ + void (*opcode_handler)(void); /* handler function */ + uint mask; /* mask on opcode */ + uint match; /* what to match after masking */ + uint ea_mask; /* what ea modes are allowed */ +} opcode_struct; + + + +/* ======================================================================== */ +/* ================================= DATA ================================= */ +/* ======================================================================== */ + +/* Opcode handler jump table */ +static void (*g_instruction_table[0x10000])(void); +/* Flag if disassembler initialized */ +static int g_initialized = 0; + +/* Address mask to simulate address lines */ +static unsigned int g_address_mask = 0xffffffff; + +static char g_dasm_str[100]; /* string to hold disassembly */ +static char g_helper_str[100]; /* string to hold helpful info */ +static uint g_cpu_pc; /* program counter */ +static uint g_cpu_ir; /* instruction register */ +static uint g_cpu_type; + +/* used by ops like asr, ror, addq, etc */ +static uint g_3bit_qdata_table[8] = {8, 1, 2, 3, 4, 5, 6, 7}; + +static uint g_5bit_data_table[32] = +{ + 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 +}; + +static char* g_cc[16] = +{"t", "f", "hi", "ls", "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi", "ge", "lt", "gt", "le"}; + +static char* g_cpcc[64] = +{/* 000 001 010 011 100 101 110 111 */ + "f", "eq", "ogt", "oge", "olt", "ole", "ogl", "or", /* 000 */ + "un", "ueq", "ugt", "uge", "ult", "ule", "ne", "t", /* 001 */ + "sf", "seq", "gt", "ge", "lt", "le", "gl" "gle", /* 010 */ + "ngle", "ngl", "nle", "nlt", "nge", "ngt", "sne", "st", /* 011 */ + "?", "?", "?", "?", "?", "?", "?", "?", /* 100 */ + "?", "?", "?", "?", "?", "?", "?", "?", /* 101 */ + "?", "?", "?", "?", "?", "?", "?", "?", /* 110 */ + "?", "?", "?", "?", "?", "?", "?", "?" /* 111 */ +}; + + +/* ======================================================================== */ +/* =========================== UTILITY FUNCTIONS ========================== */ +/* ======================================================================== */ + +#define LIMIT_CPU_TYPES(ALLOWED_CPU_TYPES) \ + if(!(g_cpu_type & ALLOWED_CPU_TYPES)) \ + { \ + d68000_illegal(); \ + return; \ + } + +#define read_imm_8() (m68k_read_disassembler_16(((g_cpu_pc+=2)-2)&g_address_mask)&0xff) +#define read_imm_16() m68k_read_disassembler_16(((g_cpu_pc+=2)-2)&g_address_mask) +#define read_imm_32() m68k_read_disassembler_32(((g_cpu_pc+=4)-4)&g_address_mask) + +#define peek_imm_8() (m68k_read_disassembler_16(g_cpu_pc & g_address_mask)&0xff) +#define peek_imm_16() m68k_read_disassembler_16(g_cpu_pc & g_address_mask) +#define peek_imm_32() m68k_read_disassembler_32(g_cpu_pc & g_address_mask) + +/* Fake a split interface */ +#define get_ea_mode_str_8(instruction) get_ea_mode_str(instruction, 0) +#define get_ea_mode_str_16(instruction) get_ea_mode_str(instruction, 1) +#define get_ea_mode_str_32(instruction) get_ea_mode_str(instruction, 2) + +#define get_imm_str_s8() get_imm_str_s(0) +#define get_imm_str_s16() get_imm_str_s(1) +#define get_imm_str_s32() get_imm_str_s(2) + +#define get_imm_str_u8() get_imm_str_u(0) +#define get_imm_str_u16() get_imm_str_u(1) +#define get_imm_str_u32() get_imm_str_u(2) + + +/* 100% portable signed int generators */ +static int make_int_8(int value) +{ + return (value & 0x80) ? value | ~0xff : value & 0xff; +} + +static int make_int_16(int value) +{ + return (value & 0x8000) ? value | ~0xffff : value & 0xffff; +} + + +/* Get string representation of hex values */ +static char* make_signed_hex_str_8(uint val) +{ + static char str[20]; + + val &= 0xff; + + if(val == 0x80) + sprintf(str, "-$80"); + else if(val & 0x80) + sprintf(str, "-$%x", (0-val) & 0x7f); + else + sprintf(str, "$%x", val & 0x7f); + + return str; +} + +static char* make_signed_hex_str_16(uint val) +{ + static char str[20]; + + val &= 0xffff; + + if(val == 0x8000) + sprintf(str, "-$8000"); + else if(val & 0x8000) + sprintf(str, "-$%x", (0-val) & 0x7fff); + else + sprintf(str, "$%x", val & 0x7fff); + + return str; +} + +static char* make_signed_hex_str_32(uint val) +{ + static char str[20]; + + val &= 0xffffffff; + + if(val == 0x80000000) + sprintf(str, "-$80000000"); + else if(val & 0x80000000) + sprintf(str, "-$%x", (0-val) & 0x7fffffff); + else + sprintf(str, "$%x", val & 0x7fffffff); + + return str; +} + + +/* make string of immediate value */ +static char* get_imm_str_s(uint size) +{ + static char str[15]; + if(size == 0) + sprintf(str, "#%s", make_signed_hex_str_8(read_imm_8())); + else if(size == 1) + sprintf(str, "#%s", make_signed_hex_str_16(read_imm_16())); + else + sprintf(str, "#%s", make_signed_hex_str_32(read_imm_32())); + return str; +} + +static char* get_imm_str_u(uint size) +{ + static char str[15]; + if(size == 0) + sprintf(str, "#$%x", read_imm_8() & 0xff); + else if(size == 1) + sprintf(str, "#$%x", read_imm_16() & 0xffff); + else + sprintf(str, "#$%x", read_imm_32() & 0xffffffff); + return str; +} + +/* Make string of effective address mode */ +static char* get_ea_mode_str(uint instruction, uint size) +{ + static char b1[64]; + static char b2[64]; + static char* mode = b2; + uint extension; + uint base; + uint outer; + char base_reg[4]; + char index_reg[8]; + uint preindex; + uint postindex; + uint comma = 0; + uint temp_value; + + /* Switch buffers so we don't clobber on a double-call to this function */ + mode = mode == b1 ? b2 : b1; + + switch(instruction & 0x3f) + { + case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: + /* data register direct */ + sprintf(mode, "D%d", instruction&7); + break; + case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: + /* address register direct */ + sprintf(mode, "A%d", instruction&7); + break; + case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: + /* address register indirect */ + sprintf(mode, "(A%d)", instruction&7); + break; + case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: + /* address register indirect with postincrement */ + sprintf(mode, "(A%d)+", instruction&7); + break; + case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: + /* address register indirect with predecrement */ + sprintf(mode, "-(A%d)", instruction&7); + break; + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: + /* address register indirect with displacement*/ + sprintf(mode, "(%s,A%d)", make_signed_hex_str_16(read_imm_16()), instruction&7); + break; + case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: + /* address register indirect with index */ + extension = read_imm_16(); + + if(EXT_FULL(extension)) + { + if(EXT_EFFECTIVE_ZERO(extension)) + { + strcpy(mode, "0"); + break; + } + base = EXT_BASE_DISPLACEMENT_PRESENT(extension) ? (EXT_BASE_DISPLACEMENT_LONG(extension) ? read_imm_32() : read_imm_16()) : 0; + outer = EXT_OUTER_DISPLACEMENT_PRESENT(extension) ? (EXT_OUTER_DISPLACEMENT_LONG(extension) ? read_imm_32() : read_imm_16()) : 0; + if(EXT_BASE_REGISTER_PRESENT(extension)) + sprintf(base_reg, "A%d", instruction&7); + else + *base_reg = 0; + if(EXT_INDEX_REGISTER_PRESENT(extension)) + { + sprintf(index_reg, "%c%d.%c", EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w'); + if(EXT_INDEX_SCALE(extension)) + sprintf(index_reg+strlen(index_reg), "*%d", 1 << EXT_INDEX_SCALE(extension)); + } + else + *index_reg = 0; + preindex = (extension&7) > 0 && (extension&7) < 4; + postindex = (extension&7) > 4; + + strcpy(mode, "("); + if(preindex || postindex) + strcat(mode, "["); + if(base) + { + strcat(mode, make_signed_hex_str_16(base)); + comma = 1; + } + if(*base_reg) + { + if(comma) + strcat(mode, ","); + strcat(mode, base_reg); + comma = 1; + } + if(postindex) + { + strcat(mode, "]"); + comma = 1; + } + if(*index_reg) + { + if(comma) + strcat(mode, ","); + strcat(mode, index_reg); + comma = 1; + } + if(preindex) + { + strcat(mode, "]"); + comma = 1; + } + if(outer) + { + if(comma) + strcat(mode, ","); + strcat(mode, make_signed_hex_str_16(outer)); + } + strcat(mode, ")"); + break; + } + + if(EXT_8BIT_DISPLACEMENT(extension) == 0) + sprintf(mode, "(A%d,%c%d.%c", instruction&7, EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w'); + else + sprintf(mode, "(%s,A%d,%c%d.%c", make_signed_hex_str_8(extension), instruction&7, EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w'); + if(EXT_INDEX_SCALE(extension)) + sprintf(mode+strlen(mode), "*%d", 1 << EXT_INDEX_SCALE(extension)); + strcat(mode, ")"); + break; + case 0x38: + /* absolute short address */ + sprintf(mode, "$%x.w", read_imm_16()); + break; + case 0x39: + /* absolute long address */ + sprintf(mode, "$%x.l", read_imm_32()); + break; + case 0x3a: + /* program counter with displacement */ + temp_value = read_imm_16(); + sprintf(mode, "(%s,PC)", make_signed_hex_str_16(temp_value)); + sprintf(g_helper_str, "; ($%x)", (make_int_16(temp_value) + g_cpu_pc-2) & 0xffffffff); + break; + case 0x3b: + /* program counter with index */ + extension = read_imm_16(); + + if(EXT_FULL(extension)) + { + if(EXT_EFFECTIVE_ZERO(extension)) + { + strcpy(mode, "0"); + break; + } + base = EXT_BASE_DISPLACEMENT_PRESENT(extension) ? (EXT_BASE_DISPLACEMENT_LONG(extension) ? read_imm_32() : read_imm_16()) : 0; + outer = EXT_OUTER_DISPLACEMENT_PRESENT(extension) ? (EXT_OUTER_DISPLACEMENT_LONG(extension) ? read_imm_32() : read_imm_16()) : 0; + if(EXT_BASE_REGISTER_PRESENT(extension)) + strcpy(base_reg, "PC"); + else + *base_reg = 0; + if(EXT_INDEX_REGISTER_PRESENT(extension)) + { + sprintf(index_reg, "%c%d.%c", EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w'); + if(EXT_INDEX_SCALE(extension)) + sprintf(index_reg+strlen(index_reg), "*%d", 1 << EXT_INDEX_SCALE(extension)); + } + else + *index_reg = 0; + preindex = (extension&7) > 0 && (extension&7) < 4; + postindex = (extension&7) > 4; + + strcpy(mode, "("); + if(preindex || postindex) + strcat(mode, "["); + if(base) + { + strcat(mode, make_signed_hex_str_16(base)); + comma = 1; + } + if(*base_reg) + { + if(comma) + strcat(mode, ","); + strcat(mode, base_reg); + comma = 1; + } + if(postindex) + { + strcat(mode, "]"); + comma = 1; + } + if(*index_reg) + { + if(comma) + strcat(mode, ","); + strcat(mode, index_reg); + comma = 1; + } + if(preindex) + { + strcat(mode, "]"); + comma = 1; + } + if(outer) + { + if(comma) + strcat(mode, ","); + strcat(mode, make_signed_hex_str_16(outer)); + } + strcat(mode, ")"); + break; + } + + if(EXT_8BIT_DISPLACEMENT(extension) == 0) + sprintf(mode, "(PC,%c%d.%c", EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w'); + else + sprintf(mode, "(%s,PC,%c%d.%c", make_signed_hex_str_8(extension), EXT_INDEX_AR(extension) ? 'A' : 'D', EXT_INDEX_REGISTER(extension), EXT_INDEX_LONG(extension) ? 'l' : 'w'); + if(EXT_INDEX_SCALE(extension)) + sprintf(mode+strlen(mode), "*%d", 1 << EXT_INDEX_SCALE(extension)); + strcat(mode, ")"); + break; + case 0x3c: + /* Immediate */ + sprintf(mode, "%s", get_imm_str_u(size)); + break; + default: + sprintf(mode, "INVALID %x", instruction & 0x3f); + } + return mode; +} + + + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ +/* Instruction handler function names follow this convention: + * + * d68000_NAME_EXTENSIONS(void) + * where NAME is the name of the opcode it handles and EXTENSIONS are any + * extensions for special instances of that opcode. + * + * Examples: + * d68000_add_er_8(): add opcode, from effective address to register, + * size = byte + * + * d68000_asr_s_8(): arithmetic shift right, static count, size = byte + * + * + * Common extensions: + * 8 : size = byte + * 16 : size = word + * 32 : size = long + * rr : register to register + * mm : memory to memory + * r : register + * s : static + * er : effective address -> register + * re : register -> effective address + * ea : using effective address mode of operation + * d : data register direct + * a : address register direct + * ai : address register indirect + * pi : address register indirect with postincrement + * pd : address register indirect with predecrement + * di : address register indirect with displacement + * ix : address register indirect with index + * aw : absolute word + * al : absolute long + */ + +static void d68000_illegal(void) +{ + sprintf(g_dasm_str, "dc.w $%04x; ILLEGAL", g_cpu_ir); +} + +static void d68000_1010(void) +{ + sprintf(g_dasm_str, "dc.w $%04x; opcode 1010", g_cpu_ir); +} + + +static void d68000_1111(void) +{ + sprintf(g_dasm_str, "dc.w $%04x; opcode 1111", g_cpu_ir); +} + + +static void d68000_abcd_rr(void) +{ + sprintf(g_dasm_str, "abcd D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + + +static void d68000_abcd_mm(void) +{ + sprintf(g_dasm_str, "abcd -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_add_er_8(void) +{ + sprintf(g_dasm_str, "add.b %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7); +} + + +static void d68000_add_er_16(void) +{ + sprintf(g_dasm_str, "add.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_add_er_32(void) +{ + sprintf(g_dasm_str, "add.l %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_add_re_8(void) +{ + sprintf(g_dasm_str, "add.b D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_add_re_16(void) +{ + sprintf(g_dasm_str, "add.w D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_add_re_32(void) +{ + sprintf(g_dasm_str, "add.l D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_adda_16(void) +{ + sprintf(g_dasm_str, "adda.w %s, A%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_adda_32(void) +{ + sprintf(g_dasm_str, "adda.l %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_addi_8(void) +{ + char* str = get_imm_str_s8(); + sprintf(g_dasm_str, "addi.b %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_addi_16(void) +{ + char* str = get_imm_str_s16(); + sprintf(g_dasm_str, "addi.w %s, %s", str, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_addi_32(void) +{ + char* str = get_imm_str_s32(); + sprintf(g_dasm_str, "addi.l %s, %s", str, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_addq_8(void) +{ + sprintf(g_dasm_str, "addq.b #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_addq_16(void) +{ + sprintf(g_dasm_str, "addq.w #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_addq_32(void) +{ + sprintf(g_dasm_str, "addq.l #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_addx_rr_8(void) +{ + sprintf(g_dasm_str, "addx.b D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_addx_rr_16(void) +{ + sprintf(g_dasm_str, "addx.w D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_addx_rr_32(void) +{ + sprintf(g_dasm_str, "addx.l D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_addx_mm_8(void) +{ + sprintf(g_dasm_str, "addx.b -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_addx_mm_16(void) +{ + sprintf(g_dasm_str, "addx.w -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_addx_mm_32(void) +{ + sprintf(g_dasm_str, "addx.l -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_and_er_8(void) +{ + sprintf(g_dasm_str, "and.b %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_and_er_16(void) +{ + sprintf(g_dasm_str, "and.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_and_er_32(void) +{ + sprintf(g_dasm_str, "and.l %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_and_re_8(void) +{ + sprintf(g_dasm_str, "and.b D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_and_re_16(void) +{ + sprintf(g_dasm_str, "and.w D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_and_re_32(void) +{ + sprintf(g_dasm_str, "and.l D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_andi_8(void) +{ + char* str = get_imm_str_u8(); + sprintf(g_dasm_str, "andi.b %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_andi_16(void) +{ + char* str = get_imm_str_u16(); + sprintf(g_dasm_str, "andi.w %s, %s", str, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_andi_32(void) +{ + char* str = get_imm_str_u32(); + sprintf(g_dasm_str, "andi.l %s, %s", str, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_andi_to_ccr(void) +{ + sprintf(g_dasm_str, "andi %s, CCR", get_imm_str_u8()); +} + +static void d68000_andi_to_sr(void) +{ + sprintf(g_dasm_str, "andi %s, SR", get_imm_str_u16()); +} + +static void d68000_asr_s_8(void) +{ + sprintf(g_dasm_str, "asr.b #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_asr_s_16(void) +{ + sprintf(g_dasm_str, "asr.w #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_asr_s_32(void) +{ + sprintf(g_dasm_str, "asr.l #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_asr_r_8(void) +{ + sprintf(g_dasm_str, "asr.b D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_asr_r_16(void) +{ + sprintf(g_dasm_str, "asr.w D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_asr_r_32(void) +{ + sprintf(g_dasm_str, "asr.l D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_asr_ea(void) +{ + sprintf(g_dasm_str, "asr.w %s", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_asl_s_8(void) +{ + sprintf(g_dasm_str, "asl.b #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_asl_s_16(void) +{ + sprintf(g_dasm_str, "asl.w #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_asl_s_32(void) +{ + sprintf(g_dasm_str, "asl.l #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_asl_r_8(void) +{ + sprintf(g_dasm_str, "asl.b D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_asl_r_16(void) +{ + sprintf(g_dasm_str, "asl.w D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_asl_r_32(void) +{ + sprintf(g_dasm_str, "asl.l D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_asl_ea(void) +{ + sprintf(g_dasm_str, "asl.w %s", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_bcc_8(void) +{ + uint temp_pc = g_cpu_pc; + sprintf(g_dasm_str, "b%-2s %x", g_cc[(g_cpu_ir>>8)&0xf], temp_pc + make_int_8(g_cpu_ir)); +} + +static void d68000_bcc_16(void) +{ + uint temp_pc = g_cpu_pc; + sprintf(g_dasm_str, "b%-2s %x", g_cc[(g_cpu_ir>>8)&0xf], temp_pc + make_int_16(read_imm_16())); +} + +static void d68020_bcc_32(void) +{ + uint temp_pc = g_cpu_pc; + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "b%-2s %x; (2+)", g_cc[(g_cpu_ir>>8)&0xf], temp_pc + read_imm_32()); +} + +static void d68000_bchg_r(void) +{ + sprintf(g_dasm_str, "bchg D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_bchg_s(void) +{ + char* str = get_imm_str_u8(); + sprintf(g_dasm_str, "bchg %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_bclr_r(void) +{ + sprintf(g_dasm_str, "bclr D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_bclr_s(void) +{ + char* str = get_imm_str_u8(); + sprintf(g_dasm_str, "bclr %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68010_bkpt(void) +{ + LIMIT_CPU_TYPES(M68010_PLUS); + sprintf(g_dasm_str, "bkpt #%d; (1+)", g_cpu_ir&7); +} + +static void d68020_bfchg(void) +{ + uint extension; + char offset[3]; + char width[3]; + + LIMIT_CPU_TYPES(M68020_PLUS); + + extension = read_imm_16(); + + if(BIT_B(extension)) + sprintf(offset, "D%d", (extension>>6)&7); + else + sprintf(offset, "%d", (extension>>6)&31); + if(BIT_5(extension)) + sprintf(width, "D%d", extension&7); + else + sprintf(width, "%d", g_5bit_data_table[extension&31]); + sprintf(g_dasm_str, "bfchg %s {%s:%s}; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width); +} + +static void d68020_bfclr(void) +{ + uint extension; + char offset[3]; + char width[3]; + + LIMIT_CPU_TYPES(M68020_PLUS); + + extension = read_imm_16(); + + if(BIT_B(extension)) + sprintf(offset, "D%d", (extension>>6)&7); + else + sprintf(offset, "%d", (extension>>6)&31); + if(BIT_5(extension)) + sprintf(width, "D%d", extension&7); + else + sprintf(width, "%d", g_5bit_data_table[extension&31]); + sprintf(g_dasm_str, "bfclr %s {%s:%s}; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width); +} + +static void d68020_bfexts(void) +{ + uint extension; + char offset[3]; + char width[3]; + + LIMIT_CPU_TYPES(M68020_PLUS); + + extension = read_imm_16(); + + if(BIT_B(extension)) + sprintf(offset, "D%d", (extension>>6)&7); + else + sprintf(offset, "%d", (extension>>6)&31); + if(BIT_5(extension)) + sprintf(width, "D%d", extension&7); + else + sprintf(width, "%d", g_5bit_data_table[extension&31]); + sprintf(g_dasm_str, "bfexts %s {%s:%s}, D%d; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width, (extension>>12)&7); +} + +static void d68020_bfextu(void) +{ + uint extension; + char offset[3]; + char width[3]; + + LIMIT_CPU_TYPES(M68020_PLUS); + + extension = read_imm_16(); + + if(BIT_B(extension)) + sprintf(offset, "D%d", (extension>>6)&7); + else + sprintf(offset, "%d", (extension>>6)&31); + if(BIT_5(extension)) + sprintf(width, "D%d", extension&7); + else + sprintf(width, "%d", g_5bit_data_table[extension&31]); + sprintf(g_dasm_str, "bfextu %s {%s:%s}, D%d; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width, (extension>>12)&7); +} + +static void d68020_bfffo(void) +{ + uint extension; + char offset[3]; + char width[3]; + + LIMIT_CPU_TYPES(M68020_PLUS); + + extension = read_imm_16(); + + if(BIT_B(extension)) + sprintf(offset, "D%d", (extension>>6)&7); + else + sprintf(offset, "%d", (extension>>6)&31); + if(BIT_5(extension)) + sprintf(width, "D%d", extension&7); + else + sprintf(width, "%d", g_5bit_data_table[extension&31]); + sprintf(g_dasm_str, "bfffo %s {%s:%s}, D%d; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width, (extension>>12)&7); +} + +static void d68020_bfins(void) +{ + uint extension; + char offset[3]; + char width[3]; + + LIMIT_CPU_TYPES(M68020_PLUS); + + extension = read_imm_16(); + + if(BIT_B(extension)) + sprintf(offset, "D%d", (extension>>6)&7); + else + sprintf(offset, "%d", (extension>>6)&31); + if(BIT_5(extension)) + sprintf(width, "D%d", extension&7); + else + sprintf(width, "%d", g_5bit_data_table[extension&31]); + sprintf(g_dasm_str, "bfins D%d, %s {%s:%s}; (2+)", (extension>>12)&7, get_ea_mode_str_8(g_cpu_ir), offset, width); +} + +static void d68020_bfset(void) +{ + uint extension; + char offset[3]; + char width[3]; + + LIMIT_CPU_TYPES(M68020_PLUS); + + extension = read_imm_16(); + + if(BIT_B(extension)) + sprintf(offset, "D%d", (extension>>6)&7); + else + sprintf(offset, "%d", (extension>>6)&31); + if(BIT_5(extension)) + sprintf(width, "D%d", extension&7); + else + sprintf(width, "%d", g_5bit_data_table[extension&31]); + sprintf(g_dasm_str, "bfset %s {%s:%s}; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width); +} + +static void d68020_bftst(void) +{ + uint extension; + char offset[3]; + char width[3]; + + LIMIT_CPU_TYPES(M68020_PLUS); + + extension = read_imm_16(); + + if(BIT_B(extension)) + sprintf(offset, "D%d", (extension>>6)&7); + else + sprintf(offset, "%d", (extension>>6)&31); + if(BIT_5(extension)) + sprintf(width, "D%d", extension&7); + else + sprintf(width, "%d", g_5bit_data_table[extension&31]); + sprintf(g_dasm_str, "bftst %s {%s:%s}; (2+)", get_ea_mode_str_8(g_cpu_ir), offset, width); +} + +static void d68000_bra_8(void) +{ + uint temp_pc = g_cpu_pc; + sprintf(g_dasm_str, "bra %x", temp_pc + make_int_8(g_cpu_ir)); +} + +static void d68000_bra_16(void) +{ + uint temp_pc = g_cpu_pc; + sprintf(g_dasm_str, "bra %x", temp_pc + make_int_16(read_imm_16())); +} + +static void d68020_bra_32(void) +{ + uint temp_pc = g_cpu_pc; + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "bra %x; (2+)", temp_pc + read_imm_32()); +} + +static void d68000_bset_r(void) +{ + sprintf(g_dasm_str, "bset D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_bset_s(void) +{ + char* str = get_imm_str_u8(); + sprintf(g_dasm_str, "bset %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_bsr_8(void) +{ + uint temp_pc = g_cpu_pc; + sprintf(g_dasm_str, "bsr %x", temp_pc + make_int_8(g_cpu_ir)); +} + +static void d68000_bsr_16(void) +{ + uint temp_pc = g_cpu_pc; + sprintf(g_dasm_str, "bsr %x", temp_pc + make_int_16(read_imm_16())); +} + +static void d68020_bsr_32(void) +{ + uint temp_pc = g_cpu_pc; + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "bsr %x; (2+)", temp_pc + peek_imm_32()); +} + +static void d68000_btst_r(void) +{ + sprintf(g_dasm_str, "btst D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_btst_s(void) +{ + char* str = get_imm_str_u8(); + sprintf(g_dasm_str, "btst %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_callm(void) +{ + char* str; + LIMIT_CPU_TYPES(M68020_ONLY); + str = get_imm_str_u8(); + + sprintf(g_dasm_str, "callm %s, %s; (2)", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_cas_8(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + sprintf(g_dasm_str, "cas.b D%d, D%d, %s; (2+)", extension&7, (extension>>6)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_cas_16(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + sprintf(g_dasm_str, "cas.w D%d, D%d, %s; (2+)", extension&7, (extension>>6)&7, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68020_cas_32(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + sprintf(g_dasm_str, "cas.l D%d, D%d, %s; (2+)", extension&7, (extension>>6)&7, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68020_cas2_16(void) +{ +/* CAS2 Dc1:Dc2,Du1:Dc2:(Rn1):(Rn2) +f e d c b a 9 8 7 6 5 4 3 2 1 0 + DARn1 0 0 0 Du1 0 0 0 Dc1 + DARn2 0 0 0 Du2 0 0 0 Dc2 +*/ + + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_32(); + sprintf(g_dasm_str, "cas2.w D%d:D%d, D%d:D%d, (%c%d):(%c%d); (2+)", + (extension>>16)&7, extension&7, (extension>>22)&7, (extension>>6)&7, + BIT_1F(extension) ? 'A' : 'D', (extension>>28)&7, + BIT_F(extension) ? 'A' : 'D', (extension>>12)&7); +} + +static void d68020_cas2_32(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_32(); + sprintf(g_dasm_str, "cas2.l D%d:D%d, D%d:D%d, (%c%d):(%c%d); (2+)", + (extension>>16)&7, extension&7, (extension>>22)&7, (extension>>6)&7, + BIT_1F(extension) ? 'A' : 'D', (extension>>28)&7, + BIT_F(extension) ? 'A' : 'D', (extension>>12)&7); +} + +static void d68000_chk_16(void) +{ + sprintf(g_dasm_str, "chk.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68020_chk_32(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "chk.l %s, D%d; (2+)", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68020_chk2_cmp2_8(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + sprintf(g_dasm_str, "%s.b %s, %c%d; (2+)", BIT_B(extension) ? "chk2" : "cmp2", get_ea_mode_str_8(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7); +} + +static void d68020_chk2_cmp2_16(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + sprintf(g_dasm_str, "%s.w %s, %c%d; (2+)", BIT_B(extension) ? "chk2" : "cmp2", get_ea_mode_str_16(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7); +} + +static void d68020_chk2_cmp2_32(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + sprintf(g_dasm_str, "%s.l %s, %c%d; (2+)", BIT_B(extension) ? "chk2" : "cmp2", get_ea_mode_str_32(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7); +} + +static void d68040_cinv(void) +{ + LIMIT_CPU_TYPES(M68040_PLUS); + switch((g_cpu_ir>>3)&3) + { + case 0: + sprintf(g_dasm_str, "cinv (illegal scope); (4)"); + break; + case 1: + sprintf(g_dasm_str, "cinvl %d, (A%d); (4)", (g_cpu_ir>>6)&3, g_cpu_ir&7); + break; + case 2: + sprintf(g_dasm_str, "cinvp %d, (A%d); (4)", (g_cpu_ir>>6)&3, g_cpu_ir&7); + break; + case 3: + sprintf(g_dasm_str, "cinva %d; (4)", (g_cpu_ir>>6)&3); + break; + } +} + +static void d68000_clr_8(void) +{ + sprintf(g_dasm_str, "clr.b %s", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_clr_16(void) +{ + sprintf(g_dasm_str, "clr.w %s", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_clr_32(void) +{ + sprintf(g_dasm_str, "clr.l %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_cmp_8(void) +{ + sprintf(g_dasm_str, "cmp.b %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_cmp_16(void) +{ + sprintf(g_dasm_str, "cmp.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_cmp_32(void) +{ + sprintf(g_dasm_str, "cmp.l %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_cmpa_16(void) +{ + sprintf(g_dasm_str, "cmpa.w %s, A%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_cmpa_32(void) +{ + sprintf(g_dasm_str, "cmpa.l %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_cmpi_8(void) +{ + char* str = get_imm_str_s8(); + sprintf(g_dasm_str, "cmpi.b %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_cmpi_pcdi_8(void) +{ + char* str; + LIMIT_CPU_TYPES(M68010_PLUS); + str = get_imm_str_s8(); + sprintf(g_dasm_str, "cmpi.b %s, %s; (2+)", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_cmpi_pcix_8(void) +{ + char* str; + LIMIT_CPU_TYPES(M68010_PLUS); + str = get_imm_str_s8(); + sprintf(g_dasm_str, "cmpi.b %s, %s; (2+)", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_cmpi_16(void) +{ + char* str; + str = get_imm_str_s16(); + sprintf(g_dasm_str, "cmpi.w %s, %s", str, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68020_cmpi_pcdi_16(void) +{ + char* str; + LIMIT_CPU_TYPES(M68010_PLUS); + str = get_imm_str_s16(); + sprintf(g_dasm_str, "cmpi.w %s, %s; (2+)", str, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68020_cmpi_pcix_16(void) +{ + char* str; + LIMIT_CPU_TYPES(M68010_PLUS); + str = get_imm_str_s16(); + sprintf(g_dasm_str, "cmpi.w %s, %s; (2+)", str, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_cmpi_32(void) +{ + char* str; + str = get_imm_str_s32(); + sprintf(g_dasm_str, "cmpi.l %s, %s", str, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68020_cmpi_pcdi_32(void) +{ + char* str; + LIMIT_CPU_TYPES(M68010_PLUS); + str = get_imm_str_s32(); + sprintf(g_dasm_str, "cmpi.l %s, %s; (2+)", str, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68020_cmpi_pcix_32(void) +{ + char* str; + LIMIT_CPU_TYPES(M68010_PLUS); + str = get_imm_str_s32(); + sprintf(g_dasm_str, "cmpi.l %s, %s; (2+)", str, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_cmpm_8(void) +{ + sprintf(g_dasm_str, "cmpm.b (A%d)+, (A%d)+", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_cmpm_16(void) +{ + sprintf(g_dasm_str, "cmpm.w (A%d)+, (A%d)+", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_cmpm_32(void) +{ + sprintf(g_dasm_str, "cmpm.l (A%d)+, (A%d)+", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68020_cpbcc_16(void) +{ + uint extension; + uint new_pc = g_cpu_pc; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + new_pc += make_int_16(peek_imm_16()); + sprintf(g_dasm_str, "%db%-4s %s; %x (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[g_cpu_ir&0x3f], get_imm_str_s16(), new_pc, extension); +} + +static void d68020_cpbcc_32(void) +{ + uint extension; + uint new_pc = g_cpu_pc; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + new_pc += peek_imm_32(); + sprintf(g_dasm_str, "%db%-4s %s; %x (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[g_cpu_ir&0x3f], get_imm_str_s16(), new_pc, extension); +} + +static void d68020_cpdbcc(void) +{ + uint extension1; + uint extension2; + uint new_pc = g_cpu_pc; + LIMIT_CPU_TYPES(M68020_PLUS); + extension1 = read_imm_16(); + extension2 = read_imm_16(); + new_pc += make_int_16(peek_imm_16()); + sprintf(g_dasm_str, "%ddb%-4s D%d,%s; %x (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], g_cpu_ir&7, get_imm_str_s16(), new_pc, extension2); +} + +static void d68020_cpgen(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "%dgen %s; (2-3)", (g_cpu_ir>>9)&7, get_imm_str_u32()); +} + +static void d68020_cprestore(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "%drestore %s; (2-3)", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_cpsave(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "%dsave %s; (2-3)", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_cpscc(void) +{ + uint extension1; + uint extension2; + LIMIT_CPU_TYPES(M68020_PLUS); + extension1 = read_imm_16(); + extension2 = read_imm_16(); + sprintf(g_dasm_str, "%ds%-4s %s; (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], get_ea_mode_str_8(g_cpu_ir), extension2); +} + +static void d68020_cptrapcc_0(void) +{ + uint extension1; + uint extension2; + LIMIT_CPU_TYPES(M68020_PLUS); + extension1 = read_imm_16(); + extension2 = read_imm_16(); + sprintf(g_dasm_str, "%dtrap%-4s; (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], extension2); +} + +static void d68020_cptrapcc_16(void) +{ + uint extension1; + uint extension2; + LIMIT_CPU_TYPES(M68020_PLUS); + extension1 = read_imm_16(); + extension2 = read_imm_16(); + sprintf(g_dasm_str, "%dtrap%-4s %s; (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], get_imm_str_u16(), extension2); +} + +static void d68020_cptrapcc_32(void) +{ + uint extension1; + uint extension2; + LIMIT_CPU_TYPES(M68020_PLUS); + extension1 = read_imm_16(); + extension2 = read_imm_16(); + sprintf(g_dasm_str, "%dtrap%-4s %s; (extension = %x) (2-3)", (g_cpu_ir>>9)&7, g_cpcc[extension1&0x3f], get_imm_str_u32(), extension2); +} + +static void d68040_cpush(void) +{ + LIMIT_CPU_TYPES(M68040_PLUS); + switch((g_cpu_ir>>3)&3) + { + case 0: + sprintf(g_dasm_str, "cpush (illegal scope); (4)"); + break; + case 1: + sprintf(g_dasm_str, "cpushl %d, (A%d); (4)", (g_cpu_ir>>6)&3, g_cpu_ir&7); + break; + case 2: + sprintf(g_dasm_str, "cpushp %d, (A%d); (4)", (g_cpu_ir>>6)&3, g_cpu_ir&7); + break; + case 3: + sprintf(g_dasm_str, "cpusha %d; (4)", (g_cpu_ir>>6)&3); + break; + } +} + +static void d68000_dbra(void) +{ + uint temp_pc = g_cpu_pc; + sprintf(g_dasm_str, "dbra D%d, %x", g_cpu_ir & 7, temp_pc + make_int_16(read_imm_16())); +} + +static void d68000_dbcc(void) +{ + uint temp_pc = g_cpu_pc; + sprintf(g_dasm_str, "db%-2s D%d, %x", g_cc[(g_cpu_ir>>8)&0xf], g_cpu_ir & 7, temp_pc + make_int_16(read_imm_16())); +} + +static void d68000_divs(void) +{ + sprintf(g_dasm_str, "divs.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_divu(void) +{ + sprintf(g_dasm_str, "divu.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68020_divl(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + + if(BIT_A(extension)) + sprintf(g_dasm_str, "div%c.l %s, D%d:D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), extension&7, (extension>>12)&7); + else if((extension&7) == ((extension>>12)&7)) + sprintf(g_dasm_str, "div%c.l %s, D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), (extension>>12)&7); + else + sprintf(g_dasm_str, "div%cl.l %s, D%d:D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), extension&7, (extension>>12)&7); +} + +static void d68000_eor_8(void) +{ + sprintf(g_dasm_str, "eor.b D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_eor_16(void) +{ + sprintf(g_dasm_str, "eor.w D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_eor_32(void) +{ + sprintf(g_dasm_str, "eor.l D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_eori_8(void) +{ + char* str = get_imm_str_u8(); + sprintf(g_dasm_str, "eori.b %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_eori_16(void) +{ + char* str = get_imm_str_u16(); + sprintf(g_dasm_str, "eori.w %s, %s", str, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_eori_32(void) +{ + char* str = get_imm_str_u32(); + sprintf(g_dasm_str, "eori.l %s, %s", str, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_eori_to_ccr(void) +{ + sprintf(g_dasm_str, "eori %s, CCR", get_imm_str_u8()); +} + +static void d68000_eori_to_sr(void) +{ + sprintf(g_dasm_str, "eori %s, SR", get_imm_str_u16()); +} + +static void d68000_exg_dd(void) +{ + sprintf(g_dasm_str, "exg D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_exg_aa(void) +{ + sprintf(g_dasm_str, "exg A%d, A%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_exg_da(void) +{ + sprintf(g_dasm_str, "exg D%d, A%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_ext_16(void) +{ + sprintf(g_dasm_str, "ext.w D%d", g_cpu_ir&7); +} + +static void d68000_ext_32(void) +{ + sprintf(g_dasm_str, "ext.l D%d", g_cpu_ir&7); +} + +static void d68020_extb_32(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "extb.l D%d; (2+)", g_cpu_ir&7); +} + +static void d68000_jmp(void) +{ + sprintf(g_dasm_str, "jmp %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_jsr(void) +{ + sprintf(g_dasm_str, "jsr %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_lea(void) +{ + sprintf(g_dasm_str, "lea %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_link_16(void) +{ + sprintf(g_dasm_str, "link A%d, %s", g_cpu_ir&7, get_imm_str_s16()); +} + +static void d68020_link_32(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "link A%d, %s; (2+)", g_cpu_ir&7, get_imm_str_s32()); +} + +static void d68000_lsr_s_8(void) +{ + sprintf(g_dasm_str, "lsr.b #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_lsr_s_16(void) +{ + sprintf(g_dasm_str, "lsr.w #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_lsr_s_32(void) +{ + sprintf(g_dasm_str, "lsr.l #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_lsr_r_8(void) +{ + sprintf(g_dasm_str, "lsr.b D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_lsr_r_16(void) +{ + sprintf(g_dasm_str, "lsr.w D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_lsr_r_32(void) +{ + sprintf(g_dasm_str, "lsr.l D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_lsr_ea(void) +{ + sprintf(g_dasm_str, "lsr.w %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_lsl_s_8(void) +{ + sprintf(g_dasm_str, "lsl.b #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_lsl_s_16(void) +{ + sprintf(g_dasm_str, "lsl.w #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_lsl_s_32(void) +{ + sprintf(g_dasm_str, "lsl.l #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_lsl_r_8(void) +{ + sprintf(g_dasm_str, "lsl.b D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_lsl_r_16(void) +{ + sprintf(g_dasm_str, "lsl.w D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_lsl_r_32(void) +{ + sprintf(g_dasm_str, "lsl.l D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_lsl_ea(void) +{ + sprintf(g_dasm_str, "lsl.w %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_move_8(void) +{ + char* str = get_ea_mode_str_8(g_cpu_ir); + sprintf(g_dasm_str, "move.b %s, %s", str, get_ea_mode_str_8(((g_cpu_ir>>9) & 7) | ((g_cpu_ir>>3) & 0x38))); +} + +static void d68000_move_16(void) +{ + char* str = get_ea_mode_str_16(g_cpu_ir); + sprintf(g_dasm_str, "move.w %s, %s", str, get_ea_mode_str_16(((g_cpu_ir>>9) & 7) | ((g_cpu_ir>>3) & 0x38))); +} + +static void d68000_move_32(void) +{ + char* str = get_ea_mode_str_32(g_cpu_ir); + sprintf(g_dasm_str, "move.l %s, %s", str, get_ea_mode_str_32(((g_cpu_ir>>9) & 7) | ((g_cpu_ir>>3) & 0x38))); +} + +static void d68000_movea_16(void) +{ + sprintf(g_dasm_str, "movea.w %s, A%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_movea_32(void) +{ + sprintf(g_dasm_str, "movea.l %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_move_to_ccr(void) +{ + sprintf(g_dasm_str, "move %s, CCR", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68010_move_fr_ccr(void) +{ + LIMIT_CPU_TYPES(M68010_PLUS); + sprintf(g_dasm_str, "move CCR, %s; (1+)", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_move_fr_sr(void) +{ + sprintf(g_dasm_str, "move SR, %s", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_move_to_sr(void) +{ + sprintf(g_dasm_str, "move %s, SR", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_move_fr_usp(void) +{ + sprintf(g_dasm_str, "move USP, A%d", g_cpu_ir&7); +} + +static void d68000_move_to_usp(void) +{ + sprintf(g_dasm_str, "move A%d, USP", g_cpu_ir&7); +} + +static void d68010_movec(void) +{ + uint extension; + char* reg_name; + char* processor; + LIMIT_CPU_TYPES(M68010_PLUS); + extension = read_imm_16(); + + switch(extension & 0xfff) + { + case 0x000: + reg_name = "SFC"; + processor = "1+"; + break; + case 0x001: + reg_name = "DFC"; + processor = "1+"; + break; + case 0x800: + reg_name = "USP"; + processor = "1+"; + break; + case 0x801: + reg_name = "VBR"; + processor = "1+"; + break; + case 0x002: + reg_name = "CACR"; + processor = "2+"; + break; + case 0x802: + reg_name = "CAAR"; + processor = "2,3"; + break; + case 0x803: + reg_name = "MSP"; + processor = "2+"; + break; + case 0x804: + reg_name = "ISP"; + processor = "2+"; + break; + case 0x003: + reg_name = "TC"; + processor = "4+"; + break; + case 0x004: + reg_name = "ITT0"; + processor = "4+"; + break; + case 0x005: + reg_name = "ITT1"; + processor = "4+"; + break; + case 0x006: + reg_name = "DTT0"; + processor = "4+"; + break; + case 0x007: + reg_name = "DTT1"; + processor = "4+"; + break; + case 0x805: + reg_name = "MMUSR"; + processor = "4+"; + break; + case 0x806: + reg_name = "URP"; + processor = "4+"; + break; + case 0x807: + reg_name = "SRP"; + processor = "4+"; + break; + default: + reg_name = make_signed_hex_str_16(extension & 0xfff); + processor = "?"; + } + + if(BIT_1(g_cpu_ir)) + sprintf(g_dasm_str, "movec %c%d, %s; (%s)", BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, reg_name, processor); + else + sprintf(g_dasm_str, "movec %s, %c%d; (%s)", reg_name, BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, processor); +} + +static void d68000_movem_pd_16(void) +{ + uint data = read_imm_16(); + char buffer[40]; + uint first; + uint run_length; + uint i; + + buffer[0] = 0; + for(i=0;i<8;i++) + { + if(data&(1<<(15-i))) + { + first = i; + run_length = 0; + while(i<7 && (data&(1<<(15-(i+1))))) + { + i++; + run_length++; + } + if(buffer[0] != 0) + strcat(buffer, "/"); + sprintf(buffer+strlen(buffer), "D%d", first); + if(run_length > 0) + sprintf(buffer+strlen(buffer), "-D%d", first + run_length); + } + } + for(i=0;i<8;i++) + { + if(data&(1<<(7-i))) + { + first = i; + run_length = 0; + while(i<7 && (data&(1<<(7-(i+1))))) + { + i++; + run_length++; + } + if(buffer[0] != 0) + strcat(buffer, "/"); + sprintf(buffer+strlen(buffer), "A%d", first); + if(run_length > 0) + sprintf(buffer+strlen(buffer), "-A%d", first + run_length); + } + } + sprintf(g_dasm_str, "movem.w %s, %s", buffer, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_movem_pd_32(void) +{ + uint data = read_imm_16(); + char buffer[40]; + uint first; + uint run_length; + uint i; + + buffer[0] = 0; + for(i=0;i<8;i++) + { + if(data&(1<<(15-i))) + { + first = i; + run_length = 0; + while(i<7 && (data&(1<<(15-(i+1))))) + { + i++; + run_length++; + } + if(buffer[0] != 0) + strcat(buffer, "/"); + sprintf(buffer+strlen(buffer), "D%d", first); + if(run_length > 0) + sprintf(buffer+strlen(buffer), "-D%d", first + run_length); + } + } + for(i=0;i<8;i++) + { + if(data&(1<<(7-i))) + { + first = i; + run_length = 0; + while(i<7 && (data&(1<<(7-(i+1))))) + { + i++; + run_length++; + } + if(buffer[0] != 0) + strcat(buffer, "/"); + sprintf(buffer+strlen(buffer), "A%d", first); + if(run_length > 0) + sprintf(buffer+strlen(buffer), "-A%d", first + run_length); + } + } + sprintf(g_dasm_str, "movem.l %s, %s", buffer, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_movem_er_16(void) +{ + uint data = read_imm_16(); + char buffer[40]; + uint first; + uint run_length; + uint i; + + buffer[0] = 0; + for(i=0;i<8;i++) + { + if(data&(1< 0) + sprintf(buffer+strlen(buffer), "-D%d", first + run_length); + } + } + for(i=0;i<8;i++) + { + if(data&(1<<(i+8))) + { + first = i; + run_length = 0; + while(i<7 && (data&(1<<(i+8+1)))) + { + i++; + run_length++; + } + if(buffer[0] != 0) + strcat(buffer, "/"); + sprintf(buffer+strlen(buffer), "A%d", first); + if(run_length > 0) + sprintf(buffer+strlen(buffer), "-A%d", first + run_length); + } + } + sprintf(g_dasm_str, "movem.w %s, %s", get_ea_mode_str_16(g_cpu_ir), buffer); +} + +static void d68000_movem_er_32(void) +{ + uint data = read_imm_16(); + char buffer[40]; + uint first; + uint run_length; + uint i; + + buffer[0] = 0; + for(i=0;i<8;i++) + { + if(data&(1< 0) + sprintf(buffer+strlen(buffer), "-D%d", first + run_length); + } + } + for(i=0;i<8;i++) + { + if(data&(1<<(i+8))) + { + first = i; + run_length = 0; + while(i<7 && (data&(1<<(i+8+1)))) + { + i++; + run_length++; + } + if(buffer[0] != 0) + strcat(buffer, "/"); + sprintf(buffer+strlen(buffer), "A%d", first); + if(run_length > 0) + sprintf(buffer+strlen(buffer), "-A%d", first + run_length); + } + } + sprintf(g_dasm_str, "movem.l %s, %s", get_ea_mode_str_32(g_cpu_ir), buffer); +} + +static void d68000_movem_re_16(void) +{ + uint data = read_imm_16(); + char buffer[40]; + uint first; + uint run_length; + uint i; + + buffer[0] = 0; + for(i=0;i<8;i++) + { + if(data&(1< 0) + sprintf(buffer+strlen(buffer), "-D%d", first + run_length); + } + } + for(i=0;i<8;i++) + { + if(data&(1<<(i+8))) + { + first = i; + run_length = 0; + while(i<7 && (data&(1<<(i+8+1)))) + { + i++; + run_length++; + } + if(buffer[0] != 0) + strcat(buffer, "/"); + sprintf(buffer+strlen(buffer), "A%d", first); + if(run_length > 0) + sprintf(buffer+strlen(buffer), "-A%d", first + run_length); + } + } + sprintf(g_dasm_str, "movem.w %s, %s", buffer, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_movem_re_32(void) +{ + uint data = read_imm_16(); + char buffer[40]; + uint first; + uint run_length; + uint i; + + buffer[0] = 0; + for(i=0;i<8;i++) + { + if(data&(1< 0) + sprintf(buffer+strlen(buffer), "-D%d", first + run_length); + } + } + for(i=0;i<8;i++) + { + if(data&(1<<(i+8))) + { + first = i; + run_length = 0; + while(i<7 && (data&(1<<(i+8+1)))) + { + i++; + run_length++; + } + if(buffer[0] != 0) + strcat(buffer, "/"); + sprintf(buffer+strlen(buffer), "A%d", first); + if(run_length > 0) + sprintf(buffer+strlen(buffer), "-A%d", first + run_length); + } + } + sprintf(g_dasm_str, "movem.l %s, %s", buffer, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_movep_re_16(void) +{ + sprintf(g_dasm_str, "movep.w D%d, ($%x,A%d)", (g_cpu_ir>>9)&7, read_imm_16(), g_cpu_ir&7); +} + +static void d68000_movep_re_32(void) +{ + sprintf(g_dasm_str, "movep.l D%d, ($%x,A%d)", (g_cpu_ir>>9)&7, read_imm_16(), g_cpu_ir&7); +} + +static void d68000_movep_er_16(void) +{ + sprintf(g_dasm_str, "movep.w ($%x,A%d), D%d", read_imm_16(), g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_movep_er_32(void) +{ + sprintf(g_dasm_str, "movep.l ($%x,A%d), D%d", read_imm_16(), g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68010_moves_8(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68010_PLUS); + extension = read_imm_16(); + if(BIT_B(extension)) + sprintf(g_dasm_str, "moves.b %c%d, %s; (1+)", BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, get_ea_mode_str_8(g_cpu_ir)); + else + sprintf(g_dasm_str, "moves.b %s, %c%d; (1+)", get_ea_mode_str_8(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7); +} + +static void d68010_moves_16(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68010_PLUS); + extension = read_imm_16(); + if(BIT_B(extension)) + sprintf(g_dasm_str, "moves.w %c%d, %s; (1+)", BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, get_ea_mode_str_16(g_cpu_ir)); + else + sprintf(g_dasm_str, "moves.w %s, %c%d; (1+)", get_ea_mode_str_16(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7); +} + +static void d68010_moves_32(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68010_PLUS); + extension = read_imm_16(); + if(BIT_B(extension)) + sprintf(g_dasm_str, "moves.l %c%d, %s; (1+)", BIT_F(extension) ? 'A' : 'D', (extension>>12)&7, get_ea_mode_str_32(g_cpu_ir)); + else + sprintf(g_dasm_str, "moves.l %s, %c%d; (1+)", get_ea_mode_str_32(g_cpu_ir), BIT_F(extension) ? 'A' : 'D', (extension>>12)&7); +} + +static void d68000_moveq(void) +{ + sprintf(g_dasm_str, "moveq #%s, D%d", make_signed_hex_str_8(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68040_move16_pi_pi(void) +{ + LIMIT_CPU_TYPES(M68040_PLUS); + sprintf(g_dasm_str, "move16 (A%d)+, (A%d)+; (4)", g_cpu_ir&7, (read_imm_16()>>12)&7); +} + +static void d68040_move16_pi_al(void) +{ + LIMIT_CPU_TYPES(M68040_PLUS); + sprintf(g_dasm_str, "move16 (A%d)+, %s; (4)", g_cpu_ir&7, get_imm_str_u32()); +} + +static void d68040_move16_al_pi(void) +{ + LIMIT_CPU_TYPES(M68040_PLUS); + sprintf(g_dasm_str, "move16 %s, (A%d)+; (4)", get_imm_str_u32(), g_cpu_ir&7); +} + +static void d68040_move16_ai_al(void) +{ + LIMIT_CPU_TYPES(M68040_PLUS); + sprintf(g_dasm_str, "move16 (A%d), %s; (4)", g_cpu_ir&7, get_imm_str_u32()); +} + +static void d68040_move16_al_ai(void) +{ + LIMIT_CPU_TYPES(M68040_PLUS); + sprintf(g_dasm_str, "move16 %s, (A%d); (4)", get_imm_str_u32(), g_cpu_ir&7); +} + +static void d68000_muls(void) +{ + sprintf(g_dasm_str, "muls.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_mulu(void) +{ + sprintf(g_dasm_str, "mulu.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68020_mull(void) +{ + uint extension; + LIMIT_CPU_TYPES(M68020_PLUS); + extension = read_imm_16(); + + if(BIT_A(extension)) + sprintf(g_dasm_str, "mul%c.l %s, D%d:D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), extension&7, (extension>>12)&7); + else + sprintf(g_dasm_str, "mul%c.l %s, D%d; (2+)", BIT_B(extension) ? 's' : 'u', get_ea_mode_str_32(g_cpu_ir), (extension>>12)&7); +} + +static void d68000_nbcd(void) +{ + sprintf(g_dasm_str, "nbcd %s", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_neg_8(void) +{ + sprintf(g_dasm_str, "neg.b %s", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_neg_16(void) +{ + sprintf(g_dasm_str, "neg.w %s", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_neg_32(void) +{ + sprintf(g_dasm_str, "neg.l %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_negx_8(void) +{ + sprintf(g_dasm_str, "negx.b %s", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_negx_16(void) +{ + sprintf(g_dasm_str, "negx.w %s", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_negx_32(void) +{ + sprintf(g_dasm_str, "negx.l %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_nop(void) +{ + sprintf(g_dasm_str, "nop"); +} + +static void d68000_not_8(void) +{ + sprintf(g_dasm_str, "not.b %s", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_not_16(void) +{ + sprintf(g_dasm_str, "not.w %s", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_not_32(void) +{ + sprintf(g_dasm_str, "not.l %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_or_er_8(void) +{ + sprintf(g_dasm_str, "or.b %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_or_er_16(void) +{ + sprintf(g_dasm_str, "or.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_or_er_32(void) +{ + sprintf(g_dasm_str, "or.l %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_or_re_8(void) +{ + sprintf(g_dasm_str, "or.b D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_or_re_16(void) +{ + sprintf(g_dasm_str, "or.w D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_or_re_32(void) +{ + sprintf(g_dasm_str, "or.l D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_ori_8(void) +{ + char* str = get_imm_str_u8(); + sprintf(g_dasm_str, "ori.b %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_ori_16(void) +{ + char* str = get_imm_str_u16(); + sprintf(g_dasm_str, "ori.w %s, %s", str, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_ori_32(void) +{ + char* str = get_imm_str_u32(); + sprintf(g_dasm_str, "ori.l %s, %s", str, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_ori_to_ccr(void) +{ + sprintf(g_dasm_str, "ori %s, CCR", get_imm_str_u8()); +} + +static void d68000_ori_to_sr(void) +{ + sprintf(g_dasm_str, "ori %s, SR", get_imm_str_u16()); +} + +static void d68020_pack_rr(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "pack D%d, D%d, %s; (2+)", g_cpu_ir&7, (g_cpu_ir>>9)&7, get_imm_str_u16()); +} + +static void d68020_pack_mm(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "pack -(A%d), -(A%d), %s; (2+)", g_cpu_ir&7, (g_cpu_ir>>9)&7, get_imm_str_u16()); +} + +static void d68000_pea(void) +{ + sprintf(g_dasm_str, "pea %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_reset(void) +{ + sprintf(g_dasm_str, "reset"); +} + +static void d68000_ror_s_8(void) +{ + sprintf(g_dasm_str, "ror.b #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_ror_s_16(void) +{ + sprintf(g_dasm_str, "ror.w #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7],g_cpu_ir&7); +} + +static void d68000_ror_s_32(void) +{ + sprintf(g_dasm_str, "ror.l #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_ror_r_8(void) +{ + sprintf(g_dasm_str, "ror.b D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_ror_r_16(void) +{ + sprintf(g_dasm_str, "ror.w D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_ror_r_32(void) +{ + sprintf(g_dasm_str, "ror.l D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_ror_ea(void) +{ + sprintf(g_dasm_str, "ror.w %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_rol_s_8(void) +{ + sprintf(g_dasm_str, "rol.b #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_rol_s_16(void) +{ + sprintf(g_dasm_str, "rol.w #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_rol_s_32(void) +{ + sprintf(g_dasm_str, "rol.l #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_rol_r_8(void) +{ + sprintf(g_dasm_str, "rol.b D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_rol_r_16(void) +{ + sprintf(g_dasm_str, "rol.w D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_rol_r_32(void) +{ + sprintf(g_dasm_str, "rol.l D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_rol_ea(void) +{ + sprintf(g_dasm_str, "rol.w %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_roxr_s_8(void) +{ + sprintf(g_dasm_str, "roxr.b #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_roxr_s_16(void) +{ + sprintf(g_dasm_str, "roxr.w #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + + +static void d68000_roxr_s_32(void) +{ + sprintf(g_dasm_str, "roxr.l #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_roxr_r_8(void) +{ + sprintf(g_dasm_str, "roxr.b D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_roxr_r_16(void) +{ + sprintf(g_dasm_str, "roxr.w D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_roxr_r_32(void) +{ + sprintf(g_dasm_str, "roxr.l D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_roxr_ea(void) +{ + sprintf(g_dasm_str, "roxr.w %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_roxl_s_8(void) +{ + sprintf(g_dasm_str, "roxl.b #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_roxl_s_16(void) +{ + sprintf(g_dasm_str, "roxl.w #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_roxl_s_32(void) +{ + sprintf(g_dasm_str, "roxl.l #%d, D%d", g_3bit_qdata_table[(g_cpu_ir>>9)&7], g_cpu_ir&7); +} + +static void d68000_roxl_r_8(void) +{ + sprintf(g_dasm_str, "roxl.b D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_roxl_r_16(void) +{ + sprintf(g_dasm_str, "roxl.w D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_roxl_r_32(void) +{ + sprintf(g_dasm_str, "roxl.l D%d, D%d", (g_cpu_ir>>9)&7, g_cpu_ir&7); +} + +static void d68000_roxl_ea(void) +{ + sprintf(g_dasm_str, "roxl.w %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68010_rtd(void) +{ + LIMIT_CPU_TYPES(M68010_PLUS); + sprintf(g_dasm_str, "rtd %s; (1+)", get_imm_str_s16()); +} + +static void d68000_rte(void) +{ + sprintf(g_dasm_str, "rte"); +} + +static void d68020_rtm(void) +{ + LIMIT_CPU_TYPES(M68020_ONLY); + sprintf(g_dasm_str, "rtm %c%d; (2+)", BIT_3(g_cpu_ir) ? 'A' : 'D', g_cpu_ir&7); +} + +static void d68000_rtr(void) +{ + sprintf(g_dasm_str, "rtr"); +} + +static void d68000_rts(void) +{ + sprintf(g_dasm_str, "rts"); +} + +static void d68000_sbcd_rr(void) +{ + sprintf(g_dasm_str, "sbcd D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_sbcd_mm(void) +{ + sprintf(g_dasm_str, "sbcd -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_scc(void) +{ + sprintf(g_dasm_str, "s%-2s %s", g_cc[(g_cpu_ir>>8)&0xf], get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_stop(void) +{ + sprintf(g_dasm_str, "stop %s", get_imm_str_s16()); +} + +static void d68000_sub_er_8(void) +{ + sprintf(g_dasm_str, "sub.b %s, D%d", get_ea_mode_str_8(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_sub_er_16(void) +{ + sprintf(g_dasm_str, "sub.w %s, D%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_sub_er_32(void) +{ + sprintf(g_dasm_str, "sub.l %s, D%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_sub_re_8(void) +{ + sprintf(g_dasm_str, "sub.b D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_sub_re_16(void) +{ + sprintf(g_dasm_str, "sub.w D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_sub_re_32(void) +{ + sprintf(g_dasm_str, "sub.l D%d, %s", (g_cpu_ir>>9)&7, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_suba_16(void) +{ + sprintf(g_dasm_str, "suba.w %s, A%d", get_ea_mode_str_16(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_suba_32(void) +{ + sprintf(g_dasm_str, "suba.l %s, A%d", get_ea_mode_str_32(g_cpu_ir), (g_cpu_ir>>9)&7); +} + +static void d68000_subi_8(void) +{ + char* str = get_imm_str_s8(); + sprintf(g_dasm_str, "subi.b %s, %s", str, get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_subi_16(void) +{ + char* str = get_imm_str_s16(); + sprintf(g_dasm_str, "subi.w %s, %s", str, get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_subi_32(void) +{ + char* str = get_imm_str_s32(); + sprintf(g_dasm_str, "subi.l %s, %s", str, get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_subq_8(void) +{ + sprintf(g_dasm_str, "subq.b #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_subq_16(void) +{ + sprintf(g_dasm_str, "subq.w #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_subq_32(void) +{ + sprintf(g_dasm_str, "subq.l #%d, %s", g_3bit_qdata_table[(g_cpu_ir>>9)&7], get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_subx_rr_8(void) +{ + sprintf(g_dasm_str, "subx.b D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_subx_rr_16(void) +{ + sprintf(g_dasm_str, "subx.w D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_subx_rr_32(void) +{ + sprintf(g_dasm_str, "subx.l D%d, D%d", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_subx_mm_8(void) +{ + sprintf(g_dasm_str, "subx.b -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_subx_mm_16(void) +{ + sprintf(g_dasm_str, "subx.w -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_subx_mm_32(void) +{ + sprintf(g_dasm_str, "subx.l -(A%d), -(A%d)", g_cpu_ir&7, (g_cpu_ir>>9)&7); +} + +static void d68000_swap(void) +{ + sprintf(g_dasm_str, "swap D%d", g_cpu_ir&7); +} + +static void d68000_tas(void) +{ + sprintf(g_dasm_str, "tas %s", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_trap(void) +{ + sprintf(g_dasm_str, "trap #$%x", g_cpu_ir&0xf); +} + +static void d68020_trapcc_0(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "trap%-2s; (2+)", g_cc[(g_cpu_ir>>8)&0xf]); +} + +static void d68020_trapcc_16(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "trap%-2s %s; (2+)", g_cc[(g_cpu_ir>>8)&0xf], get_imm_str_u16()); +} + +static void d68020_trapcc_32(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "trap%-2s %s; (2+)", g_cc[(g_cpu_ir>>8)&0xf], get_imm_str_u32()); +} + +static void d68000_trapv(void) +{ + sprintf(g_dasm_str, "trapv"); +} + +static void d68000_tst_8(void) +{ + sprintf(g_dasm_str, "tst.b %s", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_tst_pcdi_8(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.b %s; (2+)", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_tst_pcix_8(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.b %s; (2+)", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68020_tst_i_8(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.b %s; (2+)", get_ea_mode_str_8(g_cpu_ir)); +} + +static void d68000_tst_16(void) +{ + sprintf(g_dasm_str, "tst.w %s", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68020_tst_a_16(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.w %s; (2+)", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68020_tst_pcdi_16(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.w %s; (2+)", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68020_tst_pcix_16(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.w %s; (2+)", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68020_tst_i_16(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.w %s; (2+)", get_ea_mode_str_16(g_cpu_ir)); +} + +static void d68000_tst_32(void) +{ + sprintf(g_dasm_str, "tst.l %s", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68020_tst_a_32(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.l %s; (2+)", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68020_tst_pcdi_32(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.l %s; (2+)", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68020_tst_pcix_32(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.l %s; (2+)", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68020_tst_i_32(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "tst.l %s; (2+)", get_ea_mode_str_32(g_cpu_ir)); +} + +static void d68000_unlk(void) +{ + sprintf(g_dasm_str, "unlk A%d", g_cpu_ir&7); +} + +static void d68020_unpk_rr(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "unpk D%d, D%d, %s; (2+)", g_cpu_ir&7, (g_cpu_ir>>9)&7, get_imm_str_u16()); +} + +static void d68020_unpk_mm(void) +{ + LIMIT_CPU_TYPES(M68020_PLUS); + sprintf(g_dasm_str, "unpk -(A%d), -(A%d), %s; (2+)", g_cpu_ir&7, (g_cpu_ir>>9)&7, get_imm_str_u16()); +} + + + +/* ======================================================================== */ +/* ======================= INSTRUCTION TABLE BUILDER ====================== */ +/* ======================================================================== */ + +/* EA Masks: +800 = data register direct +400 = address register direct +200 = address register indirect +100 = ARI postincrement + 80 = ARI pre-decrement + 40 = ARI displacement + 20 = ARI index + 10 = absolute short + 8 = absolute long + 4 = immediate / sr + 2 = pc displacement + 1 = pc idx +*/ + +static opcode_struct g_opcode_info[] = +{ +/* opcode handler mask match ea mask */ + {d68000_1010 , 0xf000, 0xa000, 0x000}, + {d68000_1111 , 0xf000, 0xf000, 0x000}, + {d68000_abcd_rr , 0xf1f8, 0xc100, 0x000}, + {d68000_abcd_mm , 0xf1f8, 0xc108, 0x000}, + {d68000_add_er_8 , 0xf1c0, 0xd000, 0xbff}, + {d68000_add_er_16 , 0xf1c0, 0xd040, 0xfff}, + {d68000_add_er_32 , 0xf1c0, 0xd080, 0xfff}, + {d68000_add_re_8 , 0xf1c0, 0xd100, 0x3f8}, + {d68000_add_re_16 , 0xf1c0, 0xd140, 0x3f8}, + {d68000_add_re_32 , 0xf1c0, 0xd180, 0x3f8}, + {d68000_adda_16 , 0xf1c0, 0xd0c0, 0xfff}, + {d68000_adda_32 , 0xf1c0, 0xd1c0, 0xfff}, + {d68000_addi_8 , 0xffc0, 0x0600, 0xbf8}, + {d68000_addi_16 , 0xffc0, 0x0640, 0xbf8}, + {d68000_addi_32 , 0xffc0, 0x0680, 0xbf8}, + {d68000_addq_8 , 0xf1c0, 0x5000, 0xbf8}, + {d68000_addq_16 , 0xf1c0, 0x5040, 0xff8}, + {d68000_addq_32 , 0xf1c0, 0x5080, 0xff8}, + {d68000_addx_rr_8 , 0xf1f8, 0xd100, 0x000}, + {d68000_addx_rr_16 , 0xf1f8, 0xd140, 0x000}, + {d68000_addx_rr_32 , 0xf1f8, 0xd180, 0x000}, + {d68000_addx_mm_8 , 0xf1f8, 0xd108, 0x000}, + {d68000_addx_mm_16 , 0xf1f8, 0xd148, 0x000}, + {d68000_addx_mm_32 , 0xf1f8, 0xd188, 0x000}, + {d68000_and_er_8 , 0xf1c0, 0xc000, 0xbff}, + {d68000_and_er_16 , 0xf1c0, 0xc040, 0xbff}, + {d68000_and_er_32 , 0xf1c0, 0xc080, 0xbff}, + {d68000_and_re_8 , 0xf1c0, 0xc100, 0x3f8}, + {d68000_and_re_16 , 0xf1c0, 0xc140, 0x3f8}, + {d68000_and_re_32 , 0xf1c0, 0xc180, 0x3f8}, + {d68000_andi_to_ccr , 0xffff, 0x023c, 0x000}, + {d68000_andi_to_sr , 0xffff, 0x027c, 0x000}, + {d68000_andi_8 , 0xffc0, 0x0200, 0xbf8}, + {d68000_andi_16 , 0xffc0, 0x0240, 0xbf8}, + {d68000_andi_32 , 0xffc0, 0x0280, 0xbf8}, + {d68000_asr_s_8 , 0xf1f8, 0xe000, 0x000}, + {d68000_asr_s_16 , 0xf1f8, 0xe040, 0x000}, + {d68000_asr_s_32 , 0xf1f8, 0xe080, 0x000}, + {d68000_asr_r_8 , 0xf1f8, 0xe020, 0x000}, + {d68000_asr_r_16 , 0xf1f8, 0xe060, 0x000}, + {d68000_asr_r_32 , 0xf1f8, 0xe0a0, 0x000}, + {d68000_asr_ea , 0xffc0, 0xe0c0, 0x3f8}, + {d68000_asl_s_8 , 0xf1f8, 0xe100, 0x000}, + {d68000_asl_s_16 , 0xf1f8, 0xe140, 0x000}, + {d68000_asl_s_32 , 0xf1f8, 0xe180, 0x000}, + {d68000_asl_r_8 , 0xf1f8, 0xe120, 0x000}, + {d68000_asl_r_16 , 0xf1f8, 0xe160, 0x000}, + {d68000_asl_r_32 , 0xf1f8, 0xe1a0, 0x000}, + {d68000_asl_ea , 0xffc0, 0xe1c0, 0x3f8}, + {d68000_bcc_8 , 0xf000, 0x6000, 0x000}, + {d68000_bcc_16 , 0xf0ff, 0x6000, 0x000}, + {d68020_bcc_32 , 0xf0ff, 0x60ff, 0x000}, + {d68000_bchg_r , 0xf1c0, 0x0140, 0xbf8}, + {d68000_bchg_s , 0xffc0, 0x0840, 0xbf8}, + {d68000_bclr_r , 0xf1c0, 0x0180, 0xbf8}, + {d68000_bclr_s , 0xffc0, 0x0880, 0xbf8}, + {d68020_bfchg , 0xffc0, 0xeac0, 0xa78}, + {d68020_bfclr , 0xffc0, 0xecc0, 0xa78}, + {d68020_bfexts , 0xffc0, 0xebc0, 0xa7b}, + {d68020_bfextu , 0xffc0, 0xe9c0, 0xa7b}, + {d68020_bfffo , 0xffc0, 0xedc0, 0xa7b}, + {d68020_bfins , 0xffc0, 0xefc0, 0xa78}, + {d68020_bfset , 0xffc0, 0xeec0, 0xa78}, + {d68020_bftst , 0xffc0, 0xe8c0, 0xa7b}, + {d68010_bkpt , 0xfff8, 0x4848, 0x000}, + {d68000_bra_8 , 0xff00, 0x6000, 0x000}, + {d68000_bra_16 , 0xffff, 0x6000, 0x000}, + {d68020_bra_32 , 0xffff, 0x60ff, 0x000}, + {d68000_bset_r , 0xf1c0, 0x01c0, 0xbf8}, + {d68000_bset_s , 0xffc0, 0x08c0, 0xbf8}, + {d68000_bsr_8 , 0xff00, 0x6100, 0x000}, + {d68000_bsr_16 , 0xffff, 0x6100, 0x000}, + {d68020_bsr_32 , 0xffff, 0x61ff, 0x000}, + {d68000_btst_r , 0xf1c0, 0x0100, 0xbff}, + {d68000_btst_s , 0xffc0, 0x0800, 0xbfb}, + {d68020_callm , 0xffc0, 0x06c0, 0x27b}, + {d68020_cas_8 , 0xffc0, 0x0ac0, 0x3f8}, + {d68020_cas_16 , 0xffc0, 0x0cc0, 0x3f8}, + {d68020_cas_32 , 0xffc0, 0x0ec0, 0x3f8}, + {d68020_cas2_16 , 0xffff, 0x0cfc, 0x000}, + {d68020_cas2_32 , 0xffff, 0x0efc, 0x000}, + {d68000_chk_16 , 0xf1c0, 0x4180, 0xbff}, + {d68020_chk_32 , 0xf1c0, 0x4100, 0xbff}, + {d68020_chk2_cmp2_8 , 0xffc0, 0x00c0, 0x27b}, + {d68020_chk2_cmp2_16 , 0xffc0, 0x02c0, 0x27b}, + {d68020_chk2_cmp2_32 , 0xffc0, 0x04c0, 0x27b}, + {d68040_cinv , 0xff20, 0xf400, 0x000}, + {d68000_clr_8 , 0xffc0, 0x4200, 0xbf8}, + {d68000_clr_16 , 0xffc0, 0x4240, 0xbf8}, + {d68000_clr_32 , 0xffc0, 0x4280, 0xbf8}, + {d68000_cmp_8 , 0xf1c0, 0xb000, 0xbff}, + {d68000_cmp_16 , 0xf1c0, 0xb040, 0xfff}, + {d68000_cmp_32 , 0xf1c0, 0xb080, 0xfff}, + {d68000_cmpa_16 , 0xf1c0, 0xb0c0, 0xfff}, + {d68000_cmpa_32 , 0xf1c0, 0xb1c0, 0xfff}, + {d68000_cmpi_8 , 0xffc0, 0x0c00, 0xbf8}, + {d68020_cmpi_pcdi_8 , 0xffff, 0x0c3a, 0x000}, + {d68020_cmpi_pcix_8 , 0xffff, 0x0c3b, 0x000}, + {d68000_cmpi_16 , 0xffc0, 0x0c40, 0xbf8}, + {d68020_cmpi_pcdi_16 , 0xffff, 0x0c7a, 0x000}, + {d68020_cmpi_pcix_16 , 0xffff, 0x0c7b, 0x000}, + {d68000_cmpi_32 , 0xffc0, 0x0c80, 0xbf8}, + {d68020_cmpi_pcdi_32 , 0xffff, 0x0cba, 0x000}, + {d68020_cmpi_pcix_32 , 0xffff, 0x0cbb, 0x000}, + {d68000_cmpm_8 , 0xf1f8, 0xb108, 0x000}, + {d68000_cmpm_16 , 0xf1f8, 0xb148, 0x000}, + {d68000_cmpm_32 , 0xf1f8, 0xb188, 0x000}, + {d68020_cpbcc_16 , 0xf1c0, 0xf080, 0x000}, + {d68020_cpbcc_32 , 0xf1c0, 0xf0c0, 0x000}, + {d68020_cpdbcc , 0xf1f8, 0xf048, 0x000}, + {d68020_cpgen , 0xf1c0, 0xf000, 0x000}, + {d68020_cprestore , 0xf1c0, 0xf140, 0x37f}, + {d68020_cpsave , 0xf1c0, 0xf100, 0x2f8}, + {d68020_cpscc , 0xf1c0, 0xf040, 0xbf8}, + {d68020_cptrapcc_0 , 0xf1ff, 0xf07c, 0x000}, + {d68020_cptrapcc_16 , 0xf1ff, 0xf07a, 0x000}, + {d68020_cptrapcc_32 , 0xf1ff, 0xf07b, 0x000}, + {d68040_cpush , 0xff20, 0xf420, 0x000}, + {d68000_dbcc , 0xf0f8, 0x50c8, 0x000}, + {d68000_dbra , 0xfff8, 0x51c8, 0x000}, + {d68000_divs , 0xf1c0, 0x81c0, 0xbff}, + {d68000_divu , 0xf1c0, 0x80c0, 0xbff}, + {d68020_divl , 0xffc0, 0x4c40, 0xbff}, + {d68000_eor_8 , 0xf1c0, 0xb100, 0xbf8}, + {d68000_eor_16 , 0xf1c0, 0xb140, 0xbf8}, + {d68000_eor_32 , 0xf1c0, 0xb180, 0xbf8}, + {d68000_eori_to_ccr , 0xffff, 0x0a3c, 0x000}, + {d68000_eori_to_sr , 0xffff, 0x0a7c, 0x000}, + {d68000_eori_8 , 0xffc0, 0x0a00, 0xbf8}, + {d68000_eori_16 , 0xffc0, 0x0a40, 0xbf8}, + {d68000_eori_32 , 0xffc0, 0x0a80, 0xbf8}, + {d68000_exg_dd , 0xf1f8, 0xc140, 0x000}, + {d68000_exg_aa , 0xf1f8, 0xc148, 0x000}, + {d68000_exg_da , 0xf1f8, 0xc188, 0x000}, + {d68020_extb_32 , 0xfff8, 0x49c0, 0x000}, + {d68000_ext_16 , 0xfff8, 0x4880, 0x000}, + {d68000_ext_32 , 0xfff8, 0x48c0, 0x000}, + {d68000_illegal , 0xffff, 0x4afc, 0x000}, + {d68000_jmp , 0xffc0, 0x4ec0, 0x27b}, + {d68000_jsr , 0xffc0, 0x4e80, 0x27b}, + {d68000_lea , 0xf1c0, 0x41c0, 0x27b}, + {d68000_link_16 , 0xfff8, 0x4e50, 0x000}, + {d68020_link_32 , 0xfff8, 0x4808, 0x000}, + {d68000_lsr_s_8 , 0xf1f8, 0xe008, 0x000}, + {d68000_lsr_s_16 , 0xf1f8, 0xe048, 0x000}, + {d68000_lsr_s_32 , 0xf1f8, 0xe088, 0x000}, + {d68000_lsr_r_8 , 0xf1f8, 0xe028, 0x000}, + {d68000_lsr_r_16 , 0xf1f8, 0xe068, 0x000}, + {d68000_lsr_r_32 , 0xf1f8, 0xe0a8, 0x000}, + {d68000_lsr_ea , 0xffc0, 0xe2c0, 0x3f8}, + {d68000_lsl_s_8 , 0xf1f8, 0xe108, 0x000}, + {d68000_lsl_s_16 , 0xf1f8, 0xe148, 0x000}, + {d68000_lsl_s_32 , 0xf1f8, 0xe188, 0x000}, + {d68000_lsl_r_8 , 0xf1f8, 0xe128, 0x000}, + {d68000_lsl_r_16 , 0xf1f8, 0xe168, 0x000}, + {d68000_lsl_r_32 , 0xf1f8, 0xe1a8, 0x000}, + {d68000_lsl_ea , 0xffc0, 0xe3c0, 0x3f8}, + {d68000_move_8 , 0xf000, 0x1000, 0xbff}, + {d68000_move_16 , 0xf000, 0x3000, 0xfff}, + {d68000_move_32 , 0xf000, 0x2000, 0xfff}, + {d68000_movea_16 , 0xf1c0, 0x3040, 0xfff}, + {d68000_movea_32 , 0xf1c0, 0x2040, 0xfff}, + {d68000_move_to_ccr , 0xffc0, 0x44c0, 0xbff}, + {d68010_move_fr_ccr , 0xffc0, 0x42c0, 0xbf8}, + {d68000_move_to_sr , 0xffc0, 0x46c0, 0xbff}, + {d68000_move_fr_sr , 0xffc0, 0x40c0, 0xbf8}, + {d68000_move_to_usp , 0xfff8, 0x4e60, 0x000}, + {d68000_move_fr_usp , 0xfff8, 0x4e68, 0x000}, + {d68010_movec , 0xfffe, 0x4e7a, 0x000}, + {d68000_movem_pd_16 , 0xfff8, 0x48a0, 0x000}, + {d68000_movem_pd_32 , 0xfff8, 0x48e0, 0x000}, + {d68000_movem_re_16 , 0xffc0, 0x4880, 0x2f8}, + {d68000_movem_re_32 , 0xffc0, 0x48c0, 0x2f8}, + {d68000_movem_er_16 , 0xffc0, 0x4c80, 0x37b}, + {d68000_movem_er_32 , 0xffc0, 0x4cc0, 0x37b}, + {d68000_movep_er_16 , 0xf1f8, 0x0108, 0x000}, + {d68000_movep_er_32 , 0xf1f8, 0x0148, 0x000}, + {d68000_movep_re_16 , 0xf1f8, 0x0188, 0x000}, + {d68000_movep_re_32 , 0xf1f8, 0x01c8, 0x000}, + {d68010_moves_8 , 0xffc0, 0x0e00, 0x3f8}, + {d68010_moves_16 , 0xffc0, 0x0e40, 0x3f8}, + {d68010_moves_32 , 0xffc0, 0x0e80, 0x3f8}, + {d68000_moveq , 0xf100, 0x7000, 0x000}, + {d68040_move16_pi_pi , 0xfff8, 0xf620, 0x000}, + {d68040_move16_pi_al , 0xfff8, 0xf600, 0x000}, + {d68040_move16_al_pi , 0xfff8, 0xf608, 0x000}, + {d68040_move16_ai_al , 0xfff8, 0xf610, 0x000}, + {d68040_move16_al_ai , 0xfff8, 0xf618, 0x000}, + {d68000_muls , 0xf1c0, 0xc1c0, 0xbff}, + {d68000_mulu , 0xf1c0, 0xc0c0, 0xbff}, + {d68020_mull , 0xffc0, 0x4c00, 0xbff}, + {d68000_nbcd , 0xffc0, 0x4800, 0xbf8}, + {d68000_neg_8 , 0xffc0, 0x4400, 0xbf8}, + {d68000_neg_16 , 0xffc0, 0x4440, 0xbf8}, + {d68000_neg_32 , 0xffc0, 0x4480, 0xbf8}, + {d68000_negx_8 , 0xffc0, 0x4000, 0xbf8}, + {d68000_negx_16 , 0xffc0, 0x4040, 0xbf8}, + {d68000_negx_32 , 0xffc0, 0x4080, 0xbf8}, + {d68000_nop , 0xffff, 0x4e71, 0x000}, + {d68000_not_8 , 0xffc0, 0x4600, 0xbf8}, + {d68000_not_16 , 0xffc0, 0x4640, 0xbf8}, + {d68000_not_32 , 0xffc0, 0x4680, 0xbf8}, + {d68000_or_er_8 , 0xf1c0, 0x8000, 0xbff}, + {d68000_or_er_16 , 0xf1c0, 0x8040, 0xbff}, + {d68000_or_er_32 , 0xf1c0, 0x8080, 0xbff}, + {d68000_or_re_8 , 0xf1c0, 0x8100, 0x3f8}, + {d68000_or_re_16 , 0xf1c0, 0x8140, 0x3f8}, + {d68000_or_re_32 , 0xf1c0, 0x8180, 0x3f8}, + {d68000_ori_to_ccr , 0xffff, 0x003c, 0x000}, + {d68000_ori_to_sr , 0xffff, 0x007c, 0x000}, + {d68000_ori_8 , 0xffc0, 0x0000, 0xbf8}, + {d68000_ori_16 , 0xffc0, 0x0040, 0xbf8}, + {d68000_ori_32 , 0xffc0, 0x0080, 0xbf8}, + {d68020_pack_rr , 0xf1f8, 0x8140, 0x000}, + {d68020_pack_mm , 0xf1f8, 0x8148, 0x000}, + {d68000_pea , 0xffc0, 0x4840, 0x27b}, + {d68000_reset , 0xffff, 0x4e70, 0x000}, + {d68000_ror_s_8 , 0xf1f8, 0xe018, 0x000}, + {d68000_ror_s_16 , 0xf1f8, 0xe058, 0x000}, + {d68000_ror_s_32 , 0xf1f8, 0xe098, 0x000}, + {d68000_ror_r_8 , 0xf1f8, 0xe038, 0x000}, + {d68000_ror_r_16 , 0xf1f8, 0xe078, 0x000}, + {d68000_ror_r_32 , 0xf1f8, 0xe0b8, 0x000}, + {d68000_ror_ea , 0xffc0, 0xe6c0, 0x3f8}, + {d68000_rol_s_8 , 0xf1f8, 0xe118, 0x000}, + {d68000_rol_s_16 , 0xf1f8, 0xe158, 0x000}, + {d68000_rol_s_32 , 0xf1f8, 0xe198, 0x000}, + {d68000_rol_r_8 , 0xf1f8, 0xe138, 0x000}, + {d68000_rol_r_16 , 0xf1f8, 0xe178, 0x000}, + {d68000_rol_r_32 , 0xf1f8, 0xe1b8, 0x000}, + {d68000_rol_ea , 0xffc0, 0xe7c0, 0x3f8}, + {d68000_roxr_s_8 , 0xf1f8, 0xe010, 0x000}, + {d68000_roxr_s_16 , 0xf1f8, 0xe050, 0x000}, + {d68000_roxr_s_32 , 0xf1f8, 0xe090, 0x000}, + {d68000_roxr_r_8 , 0xf1f8, 0xe030, 0x000}, + {d68000_roxr_r_16 , 0xf1f8, 0xe070, 0x000}, + {d68000_roxr_r_32 , 0xf1f8, 0xe0b0, 0x000}, + {d68000_roxr_ea , 0xffc0, 0xe4c0, 0x3f8}, + {d68000_roxl_s_8 , 0xf1f8, 0xe110, 0x000}, + {d68000_roxl_s_16 , 0xf1f8, 0xe150, 0x000}, + {d68000_roxl_s_32 , 0xf1f8, 0xe190, 0x000}, + {d68000_roxl_r_8 , 0xf1f8, 0xe130, 0x000}, + {d68000_roxl_r_16 , 0xf1f8, 0xe170, 0x000}, + {d68000_roxl_r_32 , 0xf1f8, 0xe1b0, 0x000}, + {d68000_roxl_ea , 0xffc0, 0xe5c0, 0x3f8}, + {d68010_rtd , 0xffff, 0x4e74, 0x000}, + {d68000_rte , 0xffff, 0x4e73, 0x000}, + {d68020_rtm , 0xfff0, 0x06c0, 0x000}, + {d68000_rtr , 0xffff, 0x4e77, 0x000}, + {d68000_rts , 0xffff, 0x4e75, 0x000}, + {d68000_sbcd_rr , 0xf1f8, 0x8100, 0x000}, + {d68000_sbcd_mm , 0xf1f8, 0x8108, 0x000}, + {d68000_scc , 0xf0c0, 0x50c0, 0xbf8}, + {d68000_stop , 0xffff, 0x4e72, 0x000}, + {d68000_sub_er_8 , 0xf1c0, 0x9000, 0xbff}, + {d68000_sub_er_16 , 0xf1c0, 0x9040, 0xfff}, + {d68000_sub_er_32 , 0xf1c0, 0x9080, 0xfff}, + {d68000_sub_re_8 , 0xf1c0, 0x9100, 0x3f8}, + {d68000_sub_re_16 , 0xf1c0, 0x9140, 0x3f8}, + {d68000_sub_re_32 , 0xf1c0, 0x9180, 0x3f8}, + {d68000_suba_16 , 0xf1c0, 0x90c0, 0xfff}, + {d68000_suba_32 , 0xf1c0, 0x91c0, 0xfff}, + {d68000_subi_8 , 0xffc0, 0x0400, 0xbf8}, + {d68000_subi_16 , 0xffc0, 0x0440, 0xbf8}, + {d68000_subi_32 , 0xffc0, 0x0480, 0xbf8}, + {d68000_subq_8 , 0xf1c0, 0x5100, 0xbf8}, + {d68000_subq_16 , 0xf1c0, 0x5140, 0xff8}, + {d68000_subq_32 , 0xf1c0, 0x5180, 0xff8}, + {d68000_subx_rr_8 , 0xf1f8, 0x9100, 0x000}, + {d68000_subx_rr_16 , 0xf1f8, 0x9140, 0x000}, + {d68000_subx_rr_32 , 0xf1f8, 0x9180, 0x000}, + {d68000_subx_mm_8 , 0xf1f8, 0x9108, 0x000}, + {d68000_subx_mm_16 , 0xf1f8, 0x9148, 0x000}, + {d68000_subx_mm_32 , 0xf1f8, 0x9188, 0x000}, + {d68000_swap , 0xfff8, 0x4840, 0x000}, + {d68000_tas , 0xffc0, 0x4ac0, 0xbf8}, + {d68000_trap , 0xfff0, 0x4e40, 0x000}, + {d68020_trapcc_0 , 0xf0ff, 0x50fc, 0x000}, + {d68020_trapcc_16 , 0xf0ff, 0x50fa, 0x000}, + {d68020_trapcc_32 , 0xf0ff, 0x50fb, 0x000}, + {d68000_trapv , 0xffff, 0x4e76, 0x000}, + {d68000_tst_8 , 0xffc0, 0x4a00, 0xbf8}, + {d68020_tst_pcdi_8 , 0xffff, 0x4a3a, 0x000}, + {d68020_tst_pcix_8 , 0xffff, 0x4a3b, 0x000}, + {d68020_tst_i_8 , 0xffff, 0x4a3c, 0x000}, + {d68000_tst_16 , 0xffc0, 0x4a40, 0xbf8}, + {d68020_tst_a_16 , 0xfff8, 0x4a48, 0x000}, + {d68020_tst_pcdi_16 , 0xffff, 0x4a7a, 0x000}, + {d68020_tst_pcix_16 , 0xffff, 0x4a7b, 0x000}, + {d68020_tst_i_16 , 0xffff, 0x4a7c, 0x000}, + {d68000_tst_32 , 0xffc0, 0x4a80, 0xbf8}, + {d68020_tst_a_32 , 0xfff8, 0x4a88, 0x000}, + {d68020_tst_pcdi_32 , 0xffff, 0x4aba, 0x000}, + {d68020_tst_pcix_32 , 0xffff, 0x4abb, 0x000}, + {d68020_tst_i_32 , 0xffff, 0x4abc, 0x000}, + {d68000_unlk , 0xfff8, 0x4e58, 0x000}, + {d68020_unpk_rr , 0xf1f8, 0x8180, 0x000}, + {d68020_unpk_mm , 0xf1f8, 0x8188, 0x000}, + {0, 0, 0, 0} +}; + +/* Check if opcode is using a valid ea mode */ +static int valid_ea(uint opcode, uint mask) +{ + if(mask == 0) + return 1; + + switch(opcode & 0x3f) + { + case 0x00: case 0x01: case 0x02: case 0x03: + case 0x04: case 0x05: case 0x06: case 0x07: + return (mask & 0x800) != 0; + case 0x08: case 0x09: case 0x0a: case 0x0b: + case 0x0c: case 0x0d: case 0x0e: case 0x0f: + return (mask & 0x400) != 0; + case 0x10: case 0x11: case 0x12: case 0x13: + case 0x14: case 0x15: case 0x16: case 0x17: + return (mask & 0x200) != 0; + case 0x18: case 0x19: case 0x1a: case 0x1b: + case 0x1c: case 0x1d: case 0x1e: case 0x1f: + return (mask & 0x100) != 0; + case 0x20: case 0x21: case 0x22: case 0x23: + case 0x24: case 0x25: case 0x26: case 0x27: + return (mask & 0x080) != 0; + case 0x28: case 0x29: case 0x2a: case 0x2b: + case 0x2c: case 0x2d: case 0x2e: case 0x2f: + return (mask & 0x040) != 0; + case 0x30: case 0x31: case 0x32: case 0x33: + case 0x34: case 0x35: case 0x36: case 0x37: + return (mask & 0x020) != 0; + case 0x38: + return (mask & 0x010) != 0; + case 0x39: + return (mask & 0x008) != 0; + case 0x3a: + return (mask & 0x002) != 0; + case 0x3b: + return (mask & 0x001) != 0; + case 0x3c: + return (mask & 0x004) != 0; + } + return 0; + +} + +/* Used by qsort */ +static int DECL_SPEC compare_nof_true_bits(const void *aptr, const void *bptr) +{ + uint a = ((const opcode_struct*)aptr)->mask; + uint b = ((const opcode_struct*)bptr)->mask; + + a = ((a & 0xAAAA) >> 1) + (a & 0x5555); + a = ((a & 0xCCCC) >> 2) + (a & 0x3333); + a = ((a & 0xF0F0) >> 4) + (a & 0x0F0F); + a = ((a & 0xFF00) >> 8) + (a & 0x00FF); + + b = ((b & 0xAAAA) >> 1) + (b & 0x5555); + b = ((b & 0xCCCC) >> 2) + (b & 0x3333); + b = ((b & 0xF0F0) >> 4) + (b & 0x0F0F); + b = ((b & 0xFF00) >> 8) + (b & 0x00FF); + + return b - a; /* reversed to get greatest to least sorting */ +} + +/* build the opcode handler jump table */ +static void build_opcode_table(void) +{ + uint i; + uint opcode; + opcode_struct* ostruct; + uint opcode_info_length = 0; + + for(ostruct = g_opcode_info;ostruct->opcode_handler != 0;ostruct++) + opcode_info_length++; + + qsort((void *)g_opcode_info, opcode_info_length, sizeof(g_opcode_info[0]), compare_nof_true_bits); + + for(i=0;i<0x10000;i++) + { + g_instruction_table[i] = d68000_illegal; /* default to illegal */ + opcode = i; + /* search through opcode info for a match */ + for(ostruct = g_opcode_info;ostruct->opcode_handler != 0;ostruct++) + { + /* match opcode mask and allowed ea modes */ + if((opcode & ostruct->mask) == ostruct->match) + { + /* Handle destination ea for move instructions */ + if((ostruct->opcode_handler == d68000_move_8 || + ostruct->opcode_handler == d68000_move_16 || + ostruct->opcode_handler == d68000_move_32) && + !valid_ea(((opcode>>9)&7) | ((opcode>>3)&0x38), 0xbf8)) + continue; + if(valid_ea(opcode, ostruct->ea_mask)) + { + g_instruction_table[i] = ostruct->opcode_handler; + break; + } + } + } + } +} + + + +/* ======================================================================== */ +/* ================================= API ================================== */ +/* ======================================================================== */ + +/* Disasemble one instruction at pc and store in str_buff */ +unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned int cpu_type) +{ + if(!g_initialized) + { + build_opcode_table(); + g_initialized = 1; + } + switch(cpu_type) + { + case M68K_CPU_TYPE_68000: + g_cpu_type = TYPE_68000; + g_address_mask = 0x00ffffff; + break; + case M68K_CPU_TYPE_68010: + g_cpu_type = TYPE_68010; + g_address_mask = 0x00ffffff; + break; + case M68K_CPU_TYPE_68EC020: + g_cpu_type = TYPE_68020; + g_address_mask = 0x00ffffff; + break; + case M68K_CPU_TYPE_68020: + g_cpu_type = TYPE_68020; + g_address_mask = 0xffffffff; + break; + case M68K_CPU_TYPE_68030: + g_cpu_type = TYPE_68030; + g_address_mask = 0xffffffff; + break; + case M68K_CPU_TYPE_68040: + g_cpu_type = TYPE_68040; + g_address_mask = 0xffffffff; + break; + default: + return 0; + } + + g_cpu_pc = pc; + g_helper_str[0] = 0; + g_cpu_ir = read_imm_16(); + g_instruction_table[g_cpu_ir](); + sprintf(str_buff, "%s%s", g_dasm_str, g_helper_str); + return g_cpu_pc - pc; +} + +char* m68ki_disassemble_quick(unsigned int pc, unsigned int cpu_type) +{ + static char buff[100]; + buff[0] = 0; + m68k_disassemble(buff, pc, cpu_type); + return buff; +} + +/* Check if the instruction is a valid one */ +unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cpu_type) +{ + if(!g_initialized) + { + build_opcode_table(); + g_initialized = 1; + } + + instruction &= 0xffff; + if(g_instruction_table[instruction] == d68000_illegal) + return 0; + + switch(cpu_type) + { + case M68K_CPU_TYPE_68000: + if(g_instruction_table[instruction] == d68010_bkpt) + return 0; + if(g_instruction_table[instruction] == d68010_move_fr_ccr) + return 0; + if(g_instruction_table[instruction] == d68010_movec) + return 0; + if(g_instruction_table[instruction] == d68010_moves_8) + return 0; + if(g_instruction_table[instruction] == d68010_moves_16) + return 0; + if(g_instruction_table[instruction] == d68010_moves_32) + return 0; + if(g_instruction_table[instruction] == d68010_rtd) + return 0; + case M68K_CPU_TYPE_68010: + if(g_instruction_table[instruction] == d68020_bcc_32) + return 0; + if(g_instruction_table[instruction] == d68020_bfchg) + return 0; + if(g_instruction_table[instruction] == d68020_bfclr) + return 0; + if(g_instruction_table[instruction] == d68020_bfexts) + return 0; + if(g_instruction_table[instruction] == d68020_bfextu) + return 0; + if(g_instruction_table[instruction] == d68020_bfffo) + return 0; + if(g_instruction_table[instruction] == d68020_bfins) + return 0; + if(g_instruction_table[instruction] == d68020_bfset) + return 0; + if(g_instruction_table[instruction] == d68020_bftst) + return 0; + if(g_instruction_table[instruction] == d68020_bra_32) + return 0; + if(g_instruction_table[instruction] == d68020_bsr_32) + return 0; + if(g_instruction_table[instruction] == d68020_callm) + return 0; + if(g_instruction_table[instruction] == d68020_cas_8) + return 0; + if(g_instruction_table[instruction] == d68020_cas_16) + return 0; + if(g_instruction_table[instruction] == d68020_cas_32) + return 0; + if(g_instruction_table[instruction] == d68020_cas2_16) + return 0; + if(g_instruction_table[instruction] == d68020_cas2_32) + return 0; + if(g_instruction_table[instruction] == d68020_chk_32) + return 0; + if(g_instruction_table[instruction] == d68020_chk2_cmp2_8) + return 0; + if(g_instruction_table[instruction] == d68020_chk2_cmp2_16) + return 0; + if(g_instruction_table[instruction] == d68020_chk2_cmp2_32) + return 0; + if(g_instruction_table[instruction] == d68020_cmpi_pcdi_8) + return 0; + if(g_instruction_table[instruction] == d68020_cmpi_pcix_8) + return 0; + if(g_instruction_table[instruction] == d68020_cmpi_pcdi_16) + return 0; + if(g_instruction_table[instruction] == d68020_cmpi_pcix_16) + return 0; + if(g_instruction_table[instruction] == d68020_cmpi_pcdi_32) + return 0; + if(g_instruction_table[instruction] == d68020_cmpi_pcix_32) + return 0; + if(g_instruction_table[instruction] == d68020_cpbcc_16) + return 0; + if(g_instruction_table[instruction] == d68020_cpbcc_32) + return 0; + if(g_instruction_table[instruction] == d68020_cpdbcc) + return 0; + if(g_instruction_table[instruction] == d68020_cpgen) + return 0; + if(g_instruction_table[instruction] == d68020_cprestore) + return 0; + if(g_instruction_table[instruction] == d68020_cpsave) + return 0; + if(g_instruction_table[instruction] == d68020_cpscc) + return 0; + if(g_instruction_table[instruction] == d68020_cptrapcc_0) + return 0; + if(g_instruction_table[instruction] == d68020_cptrapcc_16) + return 0; + if(g_instruction_table[instruction] == d68020_cptrapcc_32) + return 0; + if(g_instruction_table[instruction] == d68020_divl) + return 0; + if(g_instruction_table[instruction] == d68020_extb_32) + return 0; + if(g_instruction_table[instruction] == d68020_link_32) + return 0; + if(g_instruction_table[instruction] == d68020_mull) + return 0; + if(g_instruction_table[instruction] == d68020_pack_rr) + return 0; + if(g_instruction_table[instruction] == d68020_pack_mm) + return 0; + if(g_instruction_table[instruction] == d68020_rtm) + return 0; + if(g_instruction_table[instruction] == d68020_trapcc_0) + return 0; + if(g_instruction_table[instruction] == d68020_trapcc_16) + return 0; + if(g_instruction_table[instruction] == d68020_trapcc_32) + return 0; + if(g_instruction_table[instruction] == d68020_tst_pcdi_8) + return 0; + if(g_instruction_table[instruction] == d68020_tst_pcix_8) + return 0; + if(g_instruction_table[instruction] == d68020_tst_i_8) + return 0; + if(g_instruction_table[instruction] == d68020_tst_a_16) + return 0; + if(g_instruction_table[instruction] == d68020_tst_pcdi_16) + return 0; + if(g_instruction_table[instruction] == d68020_tst_pcix_16) + return 0; + if(g_instruction_table[instruction] == d68020_tst_i_16) + return 0; + if(g_instruction_table[instruction] == d68020_tst_a_32) + return 0; + if(g_instruction_table[instruction] == d68020_tst_pcdi_32) + return 0; + if(g_instruction_table[instruction] == d68020_tst_pcix_32) + return 0; + if(g_instruction_table[instruction] == d68020_tst_i_32) + return 0; + if(g_instruction_table[instruction] == d68020_unpk_rr) + return 0; + if(g_instruction_table[instruction] == d68020_unpk_mm) + return 0; + case M68K_CPU_TYPE_68EC020: + case M68K_CPU_TYPE_68020: + case M68K_CPU_TYPE_68030: + if(g_instruction_table[instruction] == d68040_cinv) + return 0; + if(g_instruction_table[instruction] == d68040_cpush) + return 0; + if(g_instruction_table[instruction] == d68040_move16_pi_pi) + return 0; + if(g_instruction_table[instruction] == d68040_move16_pi_al) + return 0; + if(g_instruction_table[instruction] == d68040_move16_al_pi) + return 0; + if(g_instruction_table[instruction] == d68040_move16_ai_al) + return 0; + if(g_instruction_table[instruction] == d68040_move16_al_ai) + return 0; + } + if(cpu_type != M68K_CPU_TYPE_68020 && cpu_type != M68K_CPU_TYPE_68EC020 && + (g_instruction_table[instruction] == d68020_callm || + g_instruction_table[instruction] == d68020_rtm)) + return 0; + + return 1; +} + + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ diff --git a/MCUME_teensy/teensygen/musashi34/m68kopac.c b/MCUME_teensy/teensygen/musashi34/m68kopac.c new file mode 100644 index 0000000..3bdacfd --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68kopac.c @@ -0,0 +1,12062 @@ +#include "m68kcpu.h" + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ + + +void m68k_op_1010(void) +{ + m68ki_exception_1010(); +} + + +void m68k_op_1111(void) +{ + m68ki_exception_1111(); +} + + +void m68k_op_abcd_8_rr(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_abcd_8_mm_ax7(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_abcd_8_mm_ay7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_abcd_8_mm_axy7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_abcd_8_mm(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res += 6; + res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res -= 0xa0; + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_add_8_er_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pi7(void) +{ + uint* r_dst = &DX; + uint src = OPER_A7_PI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pd7(void) +{ + uint* r_dst = &DX; + uint src = OPER_A7_PD_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_8_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_a(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(AY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_16_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_add_32_er_d(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_a(void) +{ + uint* r_dst = &DX; + uint src = AY; + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_32_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_add_8_re_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_aw(void) +{ + uint ea = EA_AW_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_8_re_al(void) +{ + uint ea = EA_AL_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_aw(void) +{ + uint ea = EA_AW_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_16_re_al(void) +{ + uint ea = EA_AL_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_di(void) +{ + uint ea = EA_AY_DI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_aw(void) +{ + uint ea = EA_AW_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_add_32_re_al(void) +{ + uint ea = EA_AL_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_adda_16_d(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY)); +} + + +void m68k_op_adda_16_a(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY)); +} + + +void m68k_op_adda_16_ai(void) +{ + signed short src = MAKE_INT_16(OPER_AY_AI_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_16_pi(void) +{ + signed short src = MAKE_INT_16(OPER_AY_PI_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_16_pd(void) +{ + signed short src = MAKE_INT_16(OPER_AY_PD_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_16_di(void) +{ + signed short src = MAKE_INT_16(OPER_AY_DI_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_16_ix(void) +{ + signed short src = MAKE_INT_16(OPER_AY_IX_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_16_aw(void) +{ + signed short src = MAKE_INT_16(OPER_AW_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_16_al(void) +{ + signed short src = MAKE_INT_16(OPER_AL_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_16_pcdi(void) +{ + signed short src = MAKE_INT_16(OPER_PCDI_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_16_pcix(void) +{ + signed short src = MAKE_INT_16(OPER_PCIX_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_16_i(void) +{ + signed short src = MAKE_INT_16(OPER_I_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_d(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY); +} + + +void m68k_op_adda_32_a(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY); +} + + +void m68k_op_adda_32_ai(void) +{ + uint src = OPER_AY_AI_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_pi(void) +{ + uint src = OPER_AY_PI_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_pd(void) +{ + uint src = OPER_AY_PD_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_di(void) +{ + uint src = OPER_AY_DI_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_ix(void) +{ + uint src = OPER_AY_IX_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_aw(void) +{ + uint src = OPER_AW_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_al(void) +{ + uint src = OPER_AL_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_pcdi(void) +{ + uint src = OPER_PCDI_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_pcix(void) +{ + uint src = OPER_PCIX_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_adda_32_i(void) +{ + uint src = OPER_I_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + src); +} + + +void m68k_op_addi_8_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_addi_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addi_16_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_addi_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addi_32_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_32(); + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_addi_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addi_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_8_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_addq_8_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_pi7(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_pd7(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_8_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst; + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_addq_16_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_addq_16_a(void) +{ + uint* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); +} + + +void m68k_op_addq_16_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_16_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst; + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_addq_32_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = *r_dst; + uint res = src + dst; + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_addq_32_a(void) +{ + uint* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1); +} + + +void m68k_op_addq_32_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addq_32_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst; + + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_addx_8_rr(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_addx_16_rr(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +void m68k_op_addx_32_rr(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + *r_dst = res; +} + + +void m68k_op_addx_8_mm_ax7(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_addx_8_mm_ay7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_addx_8_mm_axy7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_addx_8_mm(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_V = VFLAG_ADD_8(src, dst, res); + FLAG_X = FLAG_C = CFLAG_8(res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_addx_16_mm(void) +{ + uint src = OPER_AY_PD_16(); + uint ea = EA_AX_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_V = VFLAG_ADD_16(src, dst, res); + FLAG_X = FLAG_C = CFLAG_16(res); + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_addx_32_mm(void) +{ + uint src = OPER_AY_PD_32(); + uint ea = EA_AX_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = src + dst + XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_ADD_32(src, dst, res); + FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_8_er_d(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_ai(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_AI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pi(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pi7(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pd(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_PD_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pd7(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_A7_PD_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_di(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_DI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_ix(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AY_IX_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_aw(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AW_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_al(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_AL_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pcdi(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCDI_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_pcix(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_PCIX_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_er_i(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DX &= (OPER_I_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_d(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_ai(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_AI_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_pi(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PI_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_pd(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_PD_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_di(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_DI_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_ix(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AY_IX_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_aw(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AW_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_al(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_AL_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_pcdi(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCDI_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_pcix(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_PCIX_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_16_er_i(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DX &= (OPER_I_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_d(void) +{ + FLAG_Z = DX &= DY; + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_ai(void) +{ + FLAG_Z = DX &= OPER_AY_AI_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_pi(void) +{ + FLAG_Z = DX &= OPER_AY_PI_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_pd(void) +{ + FLAG_Z = DX &= OPER_AY_PD_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_di(void) +{ + FLAG_Z = DX &= OPER_AY_DI_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_ix(void) +{ + FLAG_Z = DX &= OPER_AY_IX_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_aw(void) +{ + FLAG_Z = DX &= OPER_AW_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_al(void) +{ + FLAG_Z = DX &= OPER_AL_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_pcdi(void) +{ + FLAG_Z = DX &= OPER_PCDI_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_pcix(void) +{ + FLAG_Z = DX &= OPER_PCIX_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_32_er_i(void) +{ + FLAG_Z = DX &= OPER_I_32(); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_and_8_re_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_di(void) +{ + uint ea = EA_AY_DI_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_aw(void) +{ + uint ea = EA_AW_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_8_re_al(void) +{ + uint ea = EA_AL_8(); + uint res = DX & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_di(void) +{ + uint ea = EA_AY_DI_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_aw(void) +{ + uint ea = EA_AW_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_16_re_al(void) +{ + uint ea = EA_AL_16(); + uint res = DX & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_and_32_re_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_di(void) +{ + uint ea = EA_AY_DI_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_aw(void) +{ + uint ea = EA_AW_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_and_32_re_al(void) +{ + uint ea = EA_AL_32(); + uint res = DX & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_8_d(void) +{ + FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00)); + + FLAG_N = NFLAG_8(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_andi_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint res = src & m68ki_read_8(ea); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_8(ea, res); +} + + +void m68k_op_andi_16_d(void) +{ + FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000)); + + FLAG_N = NFLAG_16(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_andi_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint res = src & m68ki_read_16(ea); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_16(ea, res); +} + + +void m68k_op_andi_32_d(void) +{ + FLAG_Z = DY &= (OPER_I_32()); + + FLAG_N = NFLAG_32(FLAG_Z); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_andi_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint res = src & m68ki_read_32(ea); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + + m68ki_write_32(ea, res); +} + + +void m68k_op_andi_16_toc(void) +{ + m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16()); +} + + +void m68k_op_andi_16_tos(void) +{ + if(FLAG_S) + { + uint src = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68ki_get_sr() & src); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_asr_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = src >> shift; + + if(GET_MSB_8(src)) + res |= m68ki_shift_8_table[shift]; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_X = FLAG_C = src << (9-shift); +} + + +void m68k_op_asr_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = src >> shift; + + if(GET_MSB_16(src)) + res |= m68ki_shift_16_table[shift]; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_X = FLAG_C = src << (9-shift); +} + + +void m68k_op_asr_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = src >> shift; + + if(GET_MSB_32(src)) + res |= m68ki_shift_32_table[shift]; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_X = FLAG_C = src << (9-shift); +} + + +void m68k_op_asr_8_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = src >> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> (shift - 1))<<8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + if(GET_MSB_16(src)) + { + *r_dst |= 0xffff; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_asr_32_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = *r_dst; + uint res = src >> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> (shift - 1))<<8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + if(GET_MSB_32(src)) + { + *r_dst = 0xffffffff; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_asr_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asr_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + if(GET_MSB_16(src)) + res |= 0x8000; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = FLAG_X = src << 8; +} + + +void m68k_op_asl_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = MASK_OUT_ABOVE_8(src << shift); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_X = FLAG_C = src << shift; + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + src &= m68ki_shift_8_table[shift + 1]; + FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7; +} + + +void m68k_op_asl_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = MASK_OUT_ABOVE_16(src << shift); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> (8-shift); + src &= m68ki_shift_16_table[shift + 1]; + FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; +} + + +void m68k_op_asl_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32(src << shift); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> (24-shift); + src &= m68ki_shift_32_table[shift + 1]; + FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; +} + + +void m68k_op_asl_8_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + { + USE_CYCLES(shift<> 8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + src &= m68ki_shift_16_table[shift + 1]; + FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7; + return; + } + + *r_dst &= 0xffff0000; + FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = (!(src == 0))<<7; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_asl_32_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + { + USE_CYCLES(shift<> (32 - shift)) << 8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + src &= m68ki_shift_32_table[shift + 1]; + FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7; + return; + } + + *r_dst = 0; + FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = (!(src == 0))<<7; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_asl_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_asl_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + src &= 0xc000; + FLAG_V = (!(src == 0 || src == 0xc000))<<7; +} + + +void m68k_op_bhi_8(void) +{ + if(COND_HI()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bls_8(void) +{ + if(COND_LS()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bcc_8(void) +{ + if(COND_CC()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bcs_8(void) +{ + if(COND_CS()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bne_8(void) +{ + if(COND_NE()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_beq_8(void) +{ + if(COND_EQ()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bvc_8(void) +{ + if(COND_VC()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bvs_8(void) +{ + if(COND_VS()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bpl_8(void) +{ + if(COND_PL()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bmi_8(void) +{ + if(COND_MI()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bge_8(void) +{ + if(COND_GE()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_blt_8(void) +{ + if(COND_LT()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bgt_8(void) +{ + if(COND_GT()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_ble_8(void) +{ + if(COND_LE()) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + return; + } + USE_CYCLES(CYC_BCC_NOTAKE_B); +} + + +void m68k_op_bhi_16(void) +{ + if(COND_HI()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bls_16(void) +{ + if(COND_LS()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bcc_16(void) +{ + if(COND_CC()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bcs_16(void) +{ + if(COND_CS()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bne_16(void) +{ + if(COND_NE()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_beq_16(void) +{ + if(COND_EQ()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bvc_16(void) +{ + if(COND_VC()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bvs_16(void) +{ + if(COND_VS()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bpl_16(void) +{ + if(COND_PL()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bmi_16(void) +{ + if(COND_MI()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bge_16(void) +{ + if(COND_GE()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_blt_16(void) +{ + if(COND_LT()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bgt_16(void) +{ + if(COND_GT()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_ble_16(void) +{ + if(COND_LE()) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_BCC_NOTAKE_W); +} + + +void m68k_op_bhi_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_HI()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bls_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LS()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CC()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bcs_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CS()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bne_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_NE()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_beq_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_EQ()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bvc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VC()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bvs_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VS()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bpl_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_PL()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bmi_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_MI()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bge_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GE()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_blt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LT()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bgt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GT()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_ble_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LE()) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bchg_32_r_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (DX & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst ^= mask; +} + + +void m68k_op_bchg_8_r_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_r_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_32_s_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (OPER_I_8() & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst ^= mask; +} + + +void m68k_op_bchg_8_s_ai(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_pi(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_pi7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_pd(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_pd7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_di(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_ix(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_aw(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bchg_8_s_al(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src ^ mask); +} + + +void m68k_op_bclr_32_r_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (DX & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst &= ~mask; +} + + +void m68k_op_bclr_8_r_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_r_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_32_s_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (OPER_I_8() & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst &= ~mask; +} + + +void m68k_op_bclr_8_s_ai(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_pi(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_pi7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_pd(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_pd7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_di(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_ix(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_aw(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bclr_8_s_al(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src & ~mask); +} + + +void m68k_op_bfchg_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + FLAG_N = NFLAG_32(*data<>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfchg_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfchg_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfchg_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfchg_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long ^ mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte ^ mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + FLAG_N = NFLAG_32(*data<>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfclr_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long & ~mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte & ~mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint64 data = DY; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2>>12)&7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_PCDI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfexts_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_PCIX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data = MAKE_INT_32(data) >> (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint64 data = DY; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + FLAG_N = NFLAG_32(data); + data >>= 32 - width; + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2>>12)&7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_PCDI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfextu_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint data; + uint ea = EA_PCIX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + REG_D[(word2 >> 12) & 7] = data; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint64 data = DY; + uint bit; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + offset &= 31; + width = ((width-1) & 31) + 1; + + data = ROL_32(data, offset); + FLAG_N = NFLAG_32(data); + data >>= 32 - width; + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_PCDI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfffo_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + sint local_offset; + uint width = word2; + uint data; + uint bit; + uint ea = EA_PCIX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + local_offset = offset % 8; + if(local_offset < 0) + { + local_offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + data = m68ki_read_32(ea); + data = MASK_OUT_ABOVE_32(data< 32) + data |= (m68ki_read_8(ea+4) << local_offset) >> 8; + + FLAG_N = NFLAG_32(data); + data >>= (32 - width); + + FLAG_Z = data; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1) + offset++; + + REG_D[(word2>>12)&7] = offset; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + uint64 insert = REG_D[(word2>>12)&7]; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + insert = MASK_OUT_ABOVE_32(insert << (32 - width)); + FLAG_N = NFLAG_32(insert); + FLAG_Z = insert; + insert = ROR_32(insert, offset); + + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + *data &= ~mask; + *data |= insert; + + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfins_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint insert_base = REG_D[(word2>>12)&7]; + uint insert_long; + uint insert_byte; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width)); + FLAG_N = NFLAG_32(insert_base); + FLAG_Z = insert_base; + insert_long = insert_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, (data_long & ~mask_long) | insert_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + insert_byte = MASK_OUT_ABOVE_8(insert_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + FLAG_N = NFLAG_32(*data<>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bfset_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = NFLAG_32(data_long << offset); + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + m68ki_write_32(ea, data_long | mask_long); + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + m68ki_write_8(ea+4, data_byte | mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint offset = (word2>>6)&31; + uint width = word2; + uint* data = &DY; + uint64 mask; + + + if(BIT_B(word2)) + offset = REG_D[offset&7]; + if(BIT_5(word2)) + width = REG_D[width&7]; + + + offset &= 31; + width = ((width-1) & 31) + 1; + + + mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask = ROR_32(mask, offset); + + FLAG_N = NFLAG_32(*data<>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_AI_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_DI_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AY_IX_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AW_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_AL_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_PCDI_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bftst_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + sint offset = (word2>>6)&31; + uint width = word2; + uint mask_base; + uint data_long; + uint mask_long; + uint data_byte = 0; + uint mask_byte = 0; + uint ea = EA_PCIX_8(); + + if(BIT_B(word2)) + offset = MAKE_INT_32(REG_D[offset&7]); + if(BIT_5(word2)) + width = REG_D[width&7]; + + /* Offset is signed so we have to use ugly math =( */ + ea += offset / 8; + offset %= 8; + if(offset < 0) + { + offset += 8; + ea--; + } + width = ((width-1) & 31) + 1; + + + mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width)); + mask_long = mask_base >> offset; + + data_long = m68ki_read_32(ea); + FLAG_N = ((data_long & (0x80000000 >> offset))<>24; + FLAG_Z = data_long & mask_long; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + + if((width + offset) > 32) + { + mask_byte = MASK_OUT_ABOVE_8(mask_base); + data_byte = m68ki_read_8(ea+4); + FLAG_Z |= (data_byte & mask_byte); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bkpt(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */ + } + m68ki_exception_illegal(); +} + + +void m68k_op_bra_8(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_bra_16(void) +{ + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_bra_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint offset = OPER_I_32(); + REG_PC -= 4; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_32(offset); + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_bset_32_r_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (DX & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst |= mask; +} + + +void m68k_op_bset_8_r_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_r_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint mask = 1 << (DX & 7); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_32_s_d(void) +{ + uint* r_dst = &DY; + uint mask = 1 << (OPER_I_8() & 0x1f); + + FLAG_Z = *r_dst & mask; + *r_dst |= mask; +} + + +void m68k_op_bset_8_s_ai(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_pi(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_pi7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_pd(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_pd7(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_di(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_ix(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_aw(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bset_8_s_al(void) +{ + uint mask = 1 << (OPER_I_8() & 7); + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + + FLAG_Z = src & mask; + m68ki_write_8(ea, src | mask); +} + + +void m68k_op_bsr_8(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR)); +} + + +void m68k_op_bsr_16(void) +{ + uint offset = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + REG_PC -= 2; + m68ki_branch_16(offset); +} + + +void m68k_op_bsr_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint offset = OPER_I_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + REG_PC -= 4; + m68ki_branch_32(offset); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_btst_32_r_d(void) +{ + FLAG_Z = DY & (1 << (DX & 0x1f)); +} + + +void m68k_op_btst_8_r_ai(void) +{ + FLAG_Z = OPER_AY_AI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pi(void) +{ + FLAG_Z = OPER_AY_PI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pi7(void) +{ + FLAG_Z = OPER_A7_PI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pd(void) +{ + FLAG_Z = OPER_AY_PD_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pd7(void) +{ + FLAG_Z = OPER_A7_PD_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_di(void) +{ + FLAG_Z = OPER_AY_DI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_ix(void) +{ + FLAG_Z = OPER_AY_IX_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_aw(void) +{ + FLAG_Z = OPER_AW_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_al(void) +{ + FLAG_Z = OPER_AL_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pcdi(void) +{ + FLAG_Z = OPER_PCDI_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_pcix(void) +{ + FLAG_Z = OPER_PCIX_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_8_r_i(void) +{ + FLAG_Z = OPER_I_8() & (1 << (DX & 7)); +} + + +void m68k_op_btst_32_s_d(void) +{ + FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f)); +} + + +void m68k_op_btst_8_s_ai(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_AI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pi(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_PI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pi7(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_A7_PI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pd(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_PD_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pd7(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_A7_PD_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_di(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_DI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_ix(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AY_IX_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_aw(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AW_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_al(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_AL_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pcdi(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_PCDI_8() & (1 << bit); +} + + +void m68k_op_btst_8_s_pcix(void) +{ + uint bit = OPER_I_8() & 7; + + FLAG_Z = OPER_PCIX_8() & (1 << bit); +} + + +void m68k_op_callm_32_ai(void) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AY_AI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_di(void) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AY_DI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_ix(void) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AY_IX_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_aw(void) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AW_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_al(void) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_AL_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_pcdi(void) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_PCDI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_callm_32_pcix(void) +{ + /* note: watch out for pcrelative modes */ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + uint ea = EA_PCIX_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_PC += 2; +(void)ea; /* just to avoid an 'unused variable' warning */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_pi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_pi7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_A7_PI_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_pd(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_pd7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_A7_PD_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_8_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_8(); + uint dest = m68ki_read_8(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_8(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(*compare, dest, res); + FLAG_C = CFLAG_8(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_8(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_pi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_pd(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_16_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_16(); + uint dest = m68ki_read_16(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - MASK_OUT_ABOVE_16(*compare); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(*compare, dest, res); + FLAG_C = CFLAG_16(res); + + if(COND_NE()) + *compare = MASK_OUT_BELOW_16(*compare) | dest; + else + { + USE_CYCLES(3); + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7])); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_pi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_pd(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_32(); + uint dest = m68ki_read_32(ea); + uint* compare = ®_D[word2 & 7]; + uint res = dest - *compare; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(*compare, dest, res); + FLAG_C = CFLAG_SUB_32(*compare, dest, res); + + if(COND_NE()) + *compare = dest; + else + { + USE_CYCLES(3); + m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]); + } + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas2_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_32(); + uint* compare1 = ®_D[(word2 >> 16) & 7]; + uint ea1 = REG_DA[(word2 >> 28) & 15]; + uint dest1 = m68ki_read_16(ea1); + uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1); + uint* compare2 = ®_D[word2 & 7]; + uint ea2 = REG_DA[(word2 >> 12) & 15]; + uint dest2 = m68ki_read_16(ea2); + uint res2; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_16(res1); + FLAG_Z = MASK_OUT_ABOVE_16(res1); + FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1); + FLAG_C = CFLAG_16(res1); + + if(COND_EQ()) + { + res2 = dest2 - MASK_OUT_ABOVE_16(*compare2); + + FLAG_N = NFLAG_16(res2); + FLAG_Z = MASK_OUT_ABOVE_16(res2); + FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2); + FLAG_C = CFLAG_16(res2); + + if(COND_EQ()) + { + USE_CYCLES(3); + m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]); + m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]); + return; + } + } + *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1; + *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cas2_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_32(); + uint* compare1 = ®_D[(word2 >> 16) & 7]; + uint ea1 = REG_DA[(word2 >> 28) & 15]; + uint dest1 = m68ki_read_32(ea1); + uint res1 = dest1 - *compare1; + uint* compare2 = ®_D[word2 & 7]; + uint ea2 = REG_DA[(word2 >> 12) & 15]; + uint dest2 = m68ki_read_32(ea2); + uint res2; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + FLAG_N = NFLAG_32(res1); + FLAG_Z = MASK_OUT_ABOVE_32(res1); + FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1); + FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1); + + if(COND_EQ()) + { + res2 = dest2 - *compare2; + + FLAG_N = NFLAG_32(res2); + FLAG_Z = MASK_OUT_ABOVE_32(res2); + FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2); + FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2); + + if(COND_EQ()) + { + USE_CYCLES(3); + m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]); + m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]); + return; + } + } + *compare1 = dest1; + *compare2 = dest2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_16_d(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(DY); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_ai(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_AI_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_pi(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_PI_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_pd(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_PD_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_di(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_DI_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_ix(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AY_IX_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_aw(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AW_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_al(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_AL_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_pcdi(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_PCDI_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_pcix(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_PCIX_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_16_i(void) +{ + sint src = MAKE_INT_16(DX); + sint bound = MAKE_INT_16(OPER_I_16()); + + FLAG_Z = ZFLAG_16(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); +} + + +void m68k_op_chk_32_d(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(DY); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_AI_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_pi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_PI_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_pd(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_PD_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_DI_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AY_IX_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AW_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_AL_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_PCDI_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_PCIX_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk_32_i(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + sint src = MAKE_INT_32(DX); + sint bound = MAKE_INT_32(OPER_I_32()); + + FLAG_Z = ZFLAG_32(src); /* Undocumented */ + FLAG_V = VFLAG_CLEAR; /* Undocumented */ + FLAG_C = CFLAG_CLEAR; /* Undocumented */ + + if(src >= 0 && src <= bound) + { + return; + } + FLAG_N = (src < 0)<<7; + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xff; + uint ea = EA_PCDI_8(); + uint lower_bound = m68ki_read_pcrel_8(ea); + uint upper_bound = m68ki_read_pcrel_8(ea + 1); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xff; + uint ea = EA_PCIX_8(); + uint lower_bound = m68ki_read_pcrel_8(ea); + uint upper_bound = m68ki_read_pcrel_8(ea + 1); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xff; + uint ea = EA_AY_AI_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xff; + uint ea = EA_AY_DI_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xff; + uint ea = EA_AY_IX_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xff; + uint ea = EA_AW_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_8_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xff; + uint ea = EA_AL_8(); + uint lower_bound = m68ki_read_8(ea); + uint upper_bound = m68ki_read_8(ea + 1); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound); + else + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; + uint ea = EA_PCDI_16(); + uint lower_bound = m68ki_read_pcrel_16(ea); + uint upper_bound = m68ki_read_pcrel_16(ea + 2); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + FLAG_C = upper_bound - compare; + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; + uint ea = EA_PCIX_16(); + uint lower_bound = m68ki_read_pcrel_16(ea); + uint upper_bound = m68ki_read_pcrel_16(ea + 2); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + FLAG_C = upper_bound - compare; + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; + uint ea = EA_AY_AI_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 2); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + FLAG_C = compare - lower_bound; + + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + FLAG_C = upper_bound - compare; + + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; + uint ea = EA_AY_DI_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 2); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + FLAG_C = compare - lower_bound; + + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + FLAG_C = upper_bound - compare; + + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; + uint ea = EA_AY_IX_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 2); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + FLAG_C = compare - lower_bound; + + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + FLAG_C = upper_bound - compare; + + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; + uint ea = EA_AW_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 2); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + FLAG_C = compare - lower_bound; + + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + FLAG_C = upper_bound - compare; + + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_16_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]&0xffff; + uint ea = EA_AL_16(); + uint lower_bound = m68ki_read_16(ea); + uint upper_bound = m68ki_read_16(ea + 2); + + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound); + else + FLAG_C = compare - lower_bound; + + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + if(!BIT_F(word2)) + FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare); + else + FLAG_C = upper_bound - compare; + + FLAG_C = CFLAG_16(FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_PCDI_32(); + uint lower_bound = m68ki_read_pcrel_32(ea); + uint upper_bound = m68ki_read_pcrel_32(ea + 4); + + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_PCIX_32(); + uint lower_bound = m68ki_read_pcrel_32(ea); + uint upper_bound = m68ki_read_pcrel_32(ea + 4); + + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_ai(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_AI_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 4); + + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_di(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_DI_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 4); + + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_ix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AY_IX_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 4); + + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_aw(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AW_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 4); + + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_chk2cmp2_32_al(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint compare = REG_DA[(word2 >> 12) & 15]; + uint ea = EA_AL_32(); + uint lower_bound = m68ki_read_32(ea); + uint upper_bound = m68ki_read_32(ea + 4); + + FLAG_C = compare - lower_bound; + FLAG_Z = !((upper_bound==compare) | (lower_bound==compare)); + FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C); + if(COND_CS()) + { + if(BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + + FLAG_C = upper_bound - compare; + FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C); + if(COND_CS() && BIT_B(word2)) + m68ki_exception_trap(EXCEPTION_CHK); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_clr_8_d(void) +{ + DY &= 0xffffff00; + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_8_al(void) +{ + m68ki_write_8(EA_AL_8(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_d(void) +{ + DY &= 0xffff0000; + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_ai(void) +{ + m68ki_write_16(EA_AY_AI_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_pi(void) +{ + m68ki_write_16(EA_AY_PI_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_pd(void) +{ + m68ki_write_16(EA_AY_PD_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_di(void) +{ + m68ki_write_16(EA_AY_DI_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_ix(void) +{ + m68ki_write_16(EA_AY_IX_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_aw(void) +{ + m68ki_write_16(EA_AW_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_16_al(void) +{ + m68ki_write_16(EA_AL_16(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_d(void) +{ + DY = 0; + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_ai(void) +{ + m68ki_write_32(EA_AY_AI_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_pi(void) +{ + m68ki_write_32(EA_AY_PI_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_pd(void) +{ + m68ki_write_32(EA_AY_PD_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_di(void) +{ + m68ki_write_32(EA_AY_DI_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_ix(void) +{ + m68ki_write_32(EA_AY_IX_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_aw(void) +{ + m68ki_write_32(EA_AW_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_clr_32_al(void) +{ + m68ki_write_32(EA_AL_32(), 0); + + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; +} + + +void m68k_op_cmp_8_d(void) +{ + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_ai(void) +{ + uint src = OPER_AY_AI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pi(void) +{ + uint src = OPER_AY_PI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pi7(void) +{ + uint src = OPER_A7_PI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pd(void) +{ + uint src = OPER_AY_PD_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pd7(void) +{ + uint src = OPER_A7_PD_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_di(void) +{ + uint src = OPER_AY_DI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_ix(void) +{ + uint src = OPER_AY_IX_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_aw(void) +{ + uint src = OPER_AW_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_al(void) +{ + uint src = OPER_AL_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pcdi(void) +{ + uint src = OPER_PCDI_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_pcix(void) +{ + uint src = OPER_PCIX_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_8_i(void) +{ + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(DX); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmp_16_d(void) +{ + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_a(void) +{ + uint src = MASK_OUT_ABOVE_16(AY); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_ai(void) +{ + uint src = OPER_AY_AI_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_pi(void) +{ + uint src = OPER_AY_PI_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_pd(void) +{ + uint src = OPER_AY_PD_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_di(void) +{ + uint src = OPER_AY_DI_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_ix(void) +{ + uint src = OPER_AY_IX_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_aw(void) +{ + uint src = OPER_AW_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_al(void) +{ + uint src = OPER_AL_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_pcdi(void) +{ + uint src = OPER_PCDI_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_pcix(void) +{ + uint src = OPER_PCIX_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_16_i(void) +{ + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(DX); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmp_32_d(void) +{ + uint src = DY; + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_a(void) +{ + uint src = AY; + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_ai(void) +{ + uint src = OPER_AY_AI_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_pi(void) +{ + uint src = OPER_AY_PI_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_pd(void) +{ + uint src = OPER_AY_PD_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_di(void) +{ + uint src = OPER_AY_DI_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_ix(void) +{ + uint src = OPER_AY_IX_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_aw(void) +{ + uint src = OPER_AW_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_al(void) +{ + uint src = OPER_AL_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_pcdi(void) +{ + uint src = OPER_PCDI_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_pcix(void) +{ + uint src = OPER_PCIX_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmp_32_i(void) +{ + uint src = OPER_I_32(); + uint dst = DX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_d(void) +{ + uint src = MAKE_INT_16(DY); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_a(void) +{ + uint src = MAKE_INT_16(AY); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_ai(void) +{ + uint src = MAKE_INT_16(OPER_AY_AI_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_pi(void) +{ + uint src = MAKE_INT_16(OPER_AY_PI_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_pd(void) +{ + uint src = MAKE_INT_16(OPER_AY_PD_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_di(void) +{ + uint src = MAKE_INT_16(OPER_AY_DI_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_ix(void) +{ + uint src = MAKE_INT_16(OPER_AY_IX_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_aw(void) +{ + uint src = MAKE_INT_16(OPER_AW_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_al(void) +{ + uint src = MAKE_INT_16(OPER_AL_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_pcdi(void) +{ + uint src = MAKE_INT_16(OPER_PCDI_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_pcix(void) +{ + uint src = MAKE_INT_16(OPER_PCIX_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_16_i(void) +{ + uint src = MAKE_INT_16(OPER_I_16()); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_d(void) +{ + uint src = DY; + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_a(void) +{ + uint src = AY; + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_ai(void) +{ + uint src = OPER_AY_AI_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_pi(void) +{ + uint src = OPER_AY_PI_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_pd(void) +{ + uint src = OPER_AY_PD_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_di(void) +{ + uint src = OPER_AY_DI_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_ix(void) +{ + uint src = OPER_AY_IX_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_aw(void) +{ + uint src = OPER_AW_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_al(void) +{ + uint src = OPER_AL_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_pcdi(void) +{ + uint src = OPER_PCDI_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_pcix(void) +{ + uint src = OPER_PCIX_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpa_32_i(void) +{ + uint src = OPER_I_32(); + uint dst = AX; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_8_d(void) +{ + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(DY); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_ai(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_AI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pi(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pi7(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_A7_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pd(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_PD_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pd7(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_A7_PD_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_di(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_DI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_ix(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AY_IX_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_aw(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AW_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_al(void) +{ + uint src = OPER_I_8(); + uint dst = OPER_AL_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpi_8_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_8(); + uint dst = OPER_PCDI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_8_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_8(); + uint dst = OPER_PCIX_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_16_d(void) +{ + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(DY); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_ai(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_AI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_pi(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_PI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_pd(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_PD_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_di(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_DI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_ix(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AY_IX_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_aw(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AW_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_al(void) +{ + uint src = OPER_I_16(); + uint dst = OPER_AL_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpi_16_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_16(); + uint dst = OPER_PCDI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_16_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_16(); + uint dst = OPER_PCIX_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_32_d(void) +{ + uint src = OPER_I_32(); + uint dst = DY; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_ai(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_AI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_pi(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_PI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_pd(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_PD_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_di(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_DI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_ix(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AY_IX_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_aw(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AW_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_al(void) +{ + uint src = OPER_I_32(); + uint dst = OPER_AL_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cmpi_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_32(); + uint dst = OPER_PCDI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpi_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_I_32(); + uint dst = OPER_PCIX_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_cmpm_8_ax7(void) +{ + uint src = OPER_AY_PI_8(); + uint dst = OPER_A7_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpm_8_ay7(void) +{ + uint src = OPER_A7_PI_8(); + uint dst = OPER_AX_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpm_8_axy7(void) +{ + uint src = OPER_A7_PI_8(); + uint dst = OPER_A7_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpm_8(void) +{ + uint src = OPER_AY_PI_8(); + uint dst = OPER_AX_PI_8(); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_C = CFLAG_8(res); +} + + +void m68k_op_cmpm_16(void) +{ + uint src = OPER_AY_PI_16(); + uint dst = OPER_AX_PI_16(); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_C = CFLAG_16(res); +} + + +void m68k_op_cmpm_32(void) +{ + uint src = OPER_AY_PI_32(); + uint dst = OPER_AX_PI_32(); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_C = CFLAG_SUB_32(src, dst, res); +} + + +void m68k_op_cpbcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +void m68k_op_cpdbcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +void m68k_op_cpgen_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +void m68k_op_cpscc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +void m68k_op_cptrapcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_1111(); +} + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + diff --git a/MCUME_teensy/teensygen/musashi34/m68kopdm.c b/MCUME_teensy/teensygen/musashi34/m68kopdm.c new file mode 100644 index 0000000..7b15722 --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68kopdm.c @@ -0,0 +1,13223 @@ +#include "m68kcpu.h" + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ + + +void m68k_op_dbt_16(void) +{ + REG_PC += 2; +} + + +void m68k_op_dbf_16(void) +{ + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); +} + + +void m68k_op_dbhi_16(void) +{ + if(COND_NOT_HI()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbls_16(void) +{ + if(COND_NOT_LS()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbcc_16(void) +{ + if(COND_NOT_CC()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbcs_16(void) +{ + if(COND_NOT_CS()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbne_16(void) +{ + if(COND_NOT_NE()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbeq_16(void) +{ + if(COND_NOT_EQ()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbvc_16(void) +{ + if(COND_NOT_VC()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbvs_16(void) +{ + if(COND_NOT_VS()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbpl_16(void) +{ + if(COND_NOT_PL()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbmi_16(void) +{ + if(COND_NOT_MI()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbge_16(void) +{ + if(COND_NOT_GE()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dblt_16(void) +{ + if(COND_NOT_LT()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dbgt_16(void) +{ + if(COND_NOT_GT()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_dble_16(void) +{ + if(COND_NOT_LE()) + { + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(*r_dst - 1); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + if(res != 0xffff) + { + uint offset = OPER_I_16(); + REG_PC -= 2; + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_branch_16(offset); + USE_CYCLES(CYC_DBCC_F_NOEXP); + return; + } + REG_PC += 2; + USE_CYCLES(CYC_DBCC_F_EXP); + return; + } + REG_PC += 2; +} + + +void m68k_op_divs_16_d(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(DY); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_ai(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_AI_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_pi(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_PI_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_pd(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_PD_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_di(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_DI_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_ix(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AY_IX_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_aw(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AW_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_al(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_AL_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_pcdi(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_PCDI_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_pcix(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_PCIX_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divs_16_i(void) +{ + uint* r_dst = &DX; + sint src = MAKE_INT_16(OPER_I_16()); + sint quotient; + sint remainder; + + if(src != 0) + { + if((uint32)*r_dst == 0x80000000 && src == -1) + { + FLAG_Z = 0; + FLAG_N = NFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = 0; + return; + } + + quotient = MAKE_INT_32(*r_dst) / src; + remainder = MAKE_INT_32(*r_dst) % src; + + if(quotient == MAKE_INT_16(quotient)) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divu_16_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_16(); + + if(src != 0) + { + uint quotient = *r_dst / src; + uint remainder = *r_dst % src; + + if(quotient < 0x10000) + { + FLAG_Z = quotient; + FLAG_N = NFLAG_16(quotient); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16)); + return; + } + FLAG_V = VFLAG_SET; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); +} + + +void m68k_op_divl_32_d(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = DY; + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = DY; + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_ai(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_AI_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_AI_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_pi(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_PI_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_PI_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_pd(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_PD_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_PD_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_di(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_DI_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_DI_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_ix(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AY_IX_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AY_IX_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_aw(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AW_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AW_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_al(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_AL_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_AL_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_pcdi(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_PCDI_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_PCDI_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_pcix(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_PCIX_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_PCIX_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_divl_32_i(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 divisor = OPER_I_32(); + uint64 dividend = 0; + uint64 quotient = 0; + uint64 remainder = 0; + + if(divisor != 0) + { + if(BIT_A(word2)) /* 64 bit */ + { + dividend = REG_D[word2 & 7]; + dividend <<= 32; + dividend |= REG_D[(word2 >> 12) & 7]; + + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor)); + if((sint64)quotient != (sint64)((sint32)quotient)) + { + FLAG_V = VFLAG_SET; + return; + } + } + else /* unsigned */ + { + quotient = dividend / divisor; + if(quotient > 0xffffffff) + { + FLAG_V = VFLAG_SET; + return; + } + remainder = dividend % divisor; + } + } + else /* 32 bit */ + { + dividend = REG_D[(word2 >> 12) & 7]; + if(BIT_B(word2)) /* signed */ + { + quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor)); + remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor)); + } + else /* unsigned */ + { + quotient = dividend / divisor; + remainder = dividend % divisor; + } + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint divisor = OPER_I_32(); + uint dividend_hi = REG_D[word2 & 7]; + uint dividend_lo = REG_D[(word2 >> 12) & 7]; + uint quotient = 0; + uint remainder = 0; + uint dividend_neg = 0; + uint divisor_neg = 0; + sint i; + uint overflow; + + if(divisor != 0) + { + /* quad / long : long quotient, long remainder */ + if(BIT_A(word2)) + { + if(BIT_B(word2)) /* signed */ + { + /* special case in signed divide */ + if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + REG_D[word2 & 7] = 0; + REG_D[(word2 >> 12) & 7] = 0x80000000; + + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + if(GET_MSB_32(dividend_hi)) + { + dividend_neg = 1; + dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0)); + dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo); + } + if(GET_MSB_32(divisor)) + { + divisor_neg = 1; + divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor); + + } + } + + /* if the upper long is greater than the divisor, we're overflowing. */ + if(dividend_hi >= divisor) + { + FLAG_V = VFLAG_SET; + return; + } + + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + remainder = (remainder << 1) + ((dividend_hi >> i) & 1); + if(remainder >= divisor) + { + remainder -= divisor; + quotient++; + } + } + for(i = 31; i >= 0; i--) + { + quotient <<= 1; + overflow = GET_MSB_32(remainder); + remainder = (remainder << 1) + ((dividend_lo >> i) & 1); + if(remainder >= divisor || overflow) + { + remainder -= divisor; + quotient++; + } + } + + if(BIT_B(word2)) /* signed */ + { + if(quotient > 0x7fffffff) + { + FLAG_V = VFLAG_SET; + return; + } + if(dividend_neg) + { + remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder); + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + if(divisor_neg) + quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient); + } + + REG_D[word2 & 7] = remainder; + REG_D[(word2 >> 12) & 7] = quotient; + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + + /* long / long: long quotient, maybe long remainder */ + if(BIT_B(word2)) /* signed */ + { + /* Special case in divide */ + if(dividend_lo == 0x80000000 && divisor == 0xffffffff) + { + FLAG_N = NFLAG_SET; + FLAG_Z = ZFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + REG_D[(word2 >> 12) & 7] = 0x80000000; + REG_D[word2 & 7] = 0; + return; + } + REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor); + } + else + { + REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor); + quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor); + } + + FLAG_N = NFLAG_32(quotient); + FLAG_Z = quotient; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE); + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_eor_8_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX)); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_aw(void) +{ + uint ea = EA_AW_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_8_al(void) +{ + uint ea = EA_AL_8(); + uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX)); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_aw(void) +{ + uint ea = EA_AW_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_16_al(void) +{ + uint ea = EA_AL_16(); + uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_d(void) +{ + uint res = DY ^= DX; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_di(void) +{ + uint ea = EA_AY_DI_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_aw(void) +{ + uint ea = EA_AW_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eor_32_al(void) +{ + uint ea = EA_AL_32(); + uint res = DX ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8()); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint res = src ^ m68ki_read_8(ea); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16()); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint res = src ^ m68ki_read_16(ea); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_d(void) +{ + uint res = DY ^= OPER_I_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint res = src ^ m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_eori_16_toc(void) +{ + m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16()); +} + + +void m68k_op_eori_16_tos(void) +{ + if(FLAG_S) + { + uint src = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68ki_get_sr() ^ src); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_exg_32_dd(void) +{ + uint* reg_a = &DX; + uint* reg_b = &DY; + uint tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +void m68k_op_exg_32_aa(void) +{ + uint* reg_a = &AX; + uint* reg_b = &AY; + uint tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +void m68k_op_exg_32_da(void) +{ + uint* reg_a = &DX; + uint* reg_b = &AY; + uint tmp = *reg_a; + *reg_a = *reg_b; + *reg_b = tmp; +} + + +void m68k_op_ext_16(void) +{ + uint* r_dst = &DY; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0); + + FLAG_N = NFLAG_16(*r_dst); + FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_ext_32(void) +{ + uint* r_dst = &DY; + + *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0); + + FLAG_N = NFLAG_32(*r_dst); + FLAG_Z = *r_dst; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_extb_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint* r_dst = &DY; + + *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0); + + FLAG_N = NFLAG_32(*r_dst); + FLAG_Z = *r_dst; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_illegal(void) +{ + m68ki_exception_illegal(); +} + + +void m68k_op_jmp_32_ai(void) +{ + m68ki_jump(EA_AY_AI_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_di(void) +{ + m68ki_jump(EA_AY_DI_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_ix(void) +{ + m68ki_jump(EA_AY_IX_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_aw(void) +{ + m68ki_jump(EA_AW_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_al(void) +{ + m68ki_jump(EA_AL_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_pcdi(void) +{ + m68ki_jump(EA_PCDI_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jmp_32_pcix(void) +{ + m68ki_jump(EA_PCIX_32()); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(REG_PC == REG_PPC) + USE_ALL_CYCLES(); +} + + +void m68k_op_jsr_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_di(void) +{ + uint ea = EA_AY_DI_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_aw(void) +{ + uint ea = EA_AW_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_al(void) +{ + uint ea = EA_AL_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_pcdi(void) +{ + uint ea = EA_PCDI_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_jsr_32_pcix(void) +{ + uint ea = EA_PCIX_32(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_push_32(REG_PC); + m68ki_jump(ea); +} + + +void m68k_op_lea_32_ai(void) +{ + AX = EA_AY_AI_32(); +} + + +void m68k_op_lea_32_di(void) +{ + AX = EA_AY_DI_32(); +} + + +void m68k_op_lea_32_ix(void) +{ + AX = EA_AY_IX_32(); +} + + +void m68k_op_lea_32_aw(void) +{ + AX = EA_AW_32(); +} + + +void m68k_op_lea_32_al(void) +{ + AX = EA_AL_32(); +} + + +void m68k_op_lea_32_pcdi(void) +{ + AX = EA_PCDI_32(); +} + + +void m68k_op_lea_32_pcix(void) +{ + AX = EA_PCIX_32(); +} + + +void m68k_op_link_16_a7(void) +{ + REG_A[7] -= 4; + m68ki_write_32(REG_A[7], REG_A[7]); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); +} + + +void m68k_op_link_16(void) +{ + uint* r_dst = &AY; + + m68ki_push_32(*r_dst); + *r_dst = REG_A[7]; + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); +} + + +void m68k_op_link_32_a7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_A[7] -= 4; + m68ki_write_32(REG_A[7], REG_A[7]); + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_link_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint* r_dst = &AY; + + m68ki_push_32(*r_dst); + *r_dst = REG_A[7]; + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_lsr_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = src >> shift; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_X = FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = src >> shift; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_X = FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = src >> shift; + + *r_dst = res; + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_X = FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_8_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = src >> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> (shift - 1))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + FLAG_X = XFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_32_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = *r_dst; + uint res = src >> shift; + + if(shift != 0) + { + USE_CYCLES(shift<> (shift - 1))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0); + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsr_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = src >> 1; + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_CLEAR; + FLAG_Z = res; + FLAG_C = FLAG_X = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = MASK_OUT_ABOVE_8(src << shift); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src << shift; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = MASK_OUT_ABOVE_16(src << shift); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> (8-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32(src << shift); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> (24-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_8_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = MASK_OUT_ABOVE_8(src << shift); + + if(shift != 0) + { + USE_CYCLES(shift<> 8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst &= 0xffff0000; + FLAG_X = XFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_32_r(void) +{ + uint* r_dst = &DY; + uint shift = DX & 0x3f; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32(src << shift); + + if(shift != 0) + { + USE_CYCLES(shift<> (32 - shift)) << 8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + *r_dst = 0; + FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8; + FLAG_N = NFLAG_CLEAR; + FLAG_Z = ZFLAG_SET; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_lsl_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(src << 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_X = FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_move_8_d_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_di(void) +{ + uint res = OPER_AY_DI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_aw(void) +{ + uint res = OPER_AW_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_al(void) +{ + uint res = OPER_AL_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_d_i(void) +{ + uint res = OPER_I_8(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ai_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_AI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi7_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_A7_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pi_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_PI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd7_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_A7_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_pd_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_PD_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_di_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_DI_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_ix_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AX_IX_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_aw_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AW_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_ai(void) +{ + uint res = OPER_AY_AI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pi(void) +{ + uint res = OPER_AY_PI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pi7(void) +{ + uint res = OPER_A7_PI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pd(void) +{ + uint res = OPER_AY_PD_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pd7(void) +{ + uint res = OPER_A7_PD_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_di(void) +{ + uint res = OPER_AY_DI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_ix(void) +{ + uint res = OPER_AY_IX_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_aw(void) +{ + uint res = OPER_AW_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_al(void) +{ + uint res = OPER_AL_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pcdi(void) +{ + uint res = OPER_PCDI_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_pcix(void) +{ + uint res = OPER_PCIX_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_8_al_i(void) +{ + uint res = OPER_I_8(); + uint ea = EA_AL_8(); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_di(void) +{ + uint res = OPER_AY_DI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_aw(void) +{ + uint res = OPER_AW_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_al(void) +{ + uint res = OPER_AL_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_d_i(void) +{ + uint res = OPER_I_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ai_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_AI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pi_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_PI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_pd_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_PD_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_di_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_DI_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_ix_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AX_IX_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_aw_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AW_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_a(void) +{ + uint res = MASK_OUT_ABOVE_16(AY); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_ai(void) +{ + uint res = OPER_AY_AI_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_pi(void) +{ + uint res = OPER_AY_PI_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_pd(void) +{ + uint res = OPER_AY_PD_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_di(void) +{ + uint res = OPER_AY_DI_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_ix(void) +{ + uint res = OPER_AY_IX_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_aw(void) +{ + uint res = OPER_AW_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_al(void) +{ + uint res = OPER_AL_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_pcdi(void) +{ + uint res = OPER_PCDI_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_pcix(void) +{ + uint res = OPER_PCIX_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_16_al_i(void) +{ + uint res = OPER_I_16(); + uint ea = EA_AL_16(); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_d(void) +{ + uint res = DY; + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_a(void) +{ + uint res = AY; + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_di(void) +{ + uint res = OPER_AY_DI_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_aw(void) +{ + uint res = OPER_AW_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_al(void) +{ + uint res = OPER_AL_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_d_i(void) +{ + uint res = OPER_I_32(); + uint* r_dst = &DX; + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_d(void) +{ + uint res = DY; + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_a(void) +{ + uint res = AY; + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ai_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_AI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_d(void) +{ + uint res = DY; + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_a(void) +{ + uint res = AY; + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pi_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_PI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_d(void) +{ + uint res = DY; + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_a(void) +{ + uint res = AY; + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_pd_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_PD_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_d(void) +{ + uint res = DY; + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_a(void) +{ + uint res = AY; + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_di_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_DI_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_d(void) +{ + uint res = DY; + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_a(void) +{ + uint res = AY; + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_ix_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AX_IX_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_d(void) +{ + uint res = DY; + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_a(void) +{ + uint res = AY; + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_aw_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AW_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_d(void) +{ + uint res = DY; + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_a(void) +{ + uint res = AY; + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_ai(void) +{ + uint res = OPER_AY_AI_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_pi(void) +{ + uint res = OPER_AY_PI_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_pd(void) +{ + uint res = OPER_AY_PD_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_di(void) +{ + uint res = OPER_AY_DI_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_ix(void) +{ + uint res = OPER_AY_IX_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_aw(void) +{ + uint res = OPER_AW_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_al(void) +{ + uint res = OPER_AL_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_pcdi(void) +{ + uint res = OPER_PCDI_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_pcix(void) +{ + uint res = OPER_PCIX_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_move_32_al_i(void) +{ + uint res = OPER_I_32(); + uint ea = EA_AL_32(); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_movea_16_d(void) +{ + AX = MAKE_INT_16(DY); +} + + +void m68k_op_movea_16_a(void) +{ + AX = MAKE_INT_16(AY); +} + + +void m68k_op_movea_16_ai(void) +{ + AX = MAKE_INT_16(OPER_AY_AI_16()); +} + + +void m68k_op_movea_16_pi(void) +{ + AX = MAKE_INT_16(OPER_AY_PI_16()); +} + + +void m68k_op_movea_16_pd(void) +{ + AX = MAKE_INT_16(OPER_AY_PD_16()); +} + + +void m68k_op_movea_16_di(void) +{ + AX = MAKE_INT_16(OPER_AY_DI_16()); +} + + +void m68k_op_movea_16_ix(void) +{ + AX = MAKE_INT_16(OPER_AY_IX_16()); +} + + +void m68k_op_movea_16_aw(void) +{ + AX = MAKE_INT_16(OPER_AW_16()); +} + + +void m68k_op_movea_16_al(void) +{ + AX = MAKE_INT_16(OPER_AL_16()); +} + + +void m68k_op_movea_16_pcdi(void) +{ + AX = MAKE_INT_16(OPER_PCDI_16()); +} + + +void m68k_op_movea_16_pcix(void) +{ + AX = MAKE_INT_16(OPER_PCIX_16()); +} + + +void m68k_op_movea_16_i(void) +{ + AX = MAKE_INT_16(OPER_I_16()); +} + + +void m68k_op_movea_32_d(void) +{ + AX = DY; +} + + +void m68k_op_movea_32_a(void) +{ + AX = AY; +} + + +void m68k_op_movea_32_ai(void) +{ + AX = OPER_AY_AI_32(); +} + + +void m68k_op_movea_32_pi(void) +{ + AX = OPER_AY_PI_32(); +} + + +void m68k_op_movea_32_pd(void) +{ + AX = OPER_AY_PD_32(); +} + + +void m68k_op_movea_32_di(void) +{ + AX = OPER_AY_DI_32(); +} + + +void m68k_op_movea_32_ix(void) +{ + AX = OPER_AY_IX_32(); +} + + +void m68k_op_movea_32_aw(void) +{ + AX = OPER_AW_32(); +} + + +void m68k_op_movea_32_al(void) +{ + AX = OPER_AL_32(); +} + + +void m68k_op_movea_32_pcdi(void) +{ + AX = OPER_PCDI_32(); +} + + +void m68k_op_movea_32_pcix(void) +{ + AX = OPER_PCIX_32(); +} + + +void m68k_op_movea_32_i(void) +{ + AX = OPER_I_32(); +} + + +void m68k_op_move_16_frc_d(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_ai(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_AI_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_pi(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_PI_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_pd(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_PD_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_di(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_DI_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_ix(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AY_IX_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_aw(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AW_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_frc_al(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + m68ki_write_16(EA_AL_16(), m68ki_get_ccr()); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_move_16_toc_d(void) +{ + m68ki_set_ccr(DY); +} + + +void m68k_op_move_16_toc_ai(void) +{ + m68ki_set_ccr(OPER_AY_AI_16()); +} + + +void m68k_op_move_16_toc_pi(void) +{ + m68ki_set_ccr(OPER_AY_PI_16()); +} + + +void m68k_op_move_16_toc_pd(void) +{ + m68ki_set_ccr(OPER_AY_PD_16()); +} + + +void m68k_op_move_16_toc_di(void) +{ + m68ki_set_ccr(OPER_AY_DI_16()); +} + + +void m68k_op_move_16_toc_ix(void) +{ + m68ki_set_ccr(OPER_AY_IX_16()); +} + + +void m68k_op_move_16_toc_aw(void) +{ + m68ki_set_ccr(OPER_AW_16()); +} + + +void m68k_op_move_16_toc_al(void) +{ + m68ki_set_ccr(OPER_AL_16()); +} + + +void m68k_op_move_16_toc_pcdi(void) +{ + m68ki_set_ccr(OPER_PCDI_16()); +} + + +void m68k_op_move_16_toc_pcix(void) +{ + m68ki_set_ccr(OPER_PCIX_16()); +} + + +void m68k_op_move_16_toc_i(void) +{ + m68ki_set_ccr(OPER_I_16()); +} + + +void m68k_op_move_16_frs_d(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr(); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_ai(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_AI_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_pi(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_PI_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_pd(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_PD_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_di(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_DI_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_ix(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AY_IX_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_aw(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AW_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_frs_al(void) +{ + if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */ + { + uint ea = EA_AL_16(); + m68ki_write_16(ea, m68ki_get_sr()); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_d(void) +{ + if(FLAG_S) + { + m68ki_set_sr(DY); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_ai(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_AI_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_pi(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_PI_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_pd(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_PD_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_di(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_DI_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_ix(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AY_IX_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_aw(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AW_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_al(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_AL_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_pcdi(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_PCDI_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_pcix(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_PCIX_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_16_tos_i(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(new_sr); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_32_fru(void) +{ + if(FLAG_S) + { + AY = REG_USP; + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_move_32_tou(void) +{ + if(FLAG_S) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_USP = AY; + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_movec_32_cr(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + switch (word2 & 0xfff) + { + case 0x000: /* SFC */ + REG_DA[(word2 >> 12) & 15] = REG_SFC; + return; + case 0x001: /* DFC */ + REG_DA[(word2 >> 12) & 15] = REG_DFC; + return; + case 0x002: /* CACR */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_DA[(word2 >> 12) & 15] = REG_CACR; + return; + } + return; + case 0x800: /* USP */ + REG_DA[(word2 >> 12) & 15] = REG_USP; + return; + case 0x801: /* VBR */ + REG_DA[(word2 >> 12) & 15] = REG_VBR; + return; + case 0x802: /* CAAR */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_DA[(word2 >> 12) & 15] = REG_CAAR; + return; + } + m68ki_exception_illegal(); + break; + case 0x803: /* MSP */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP; + return; + } + m68ki_exception_illegal(); + return; + case 0x804: /* ISP */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP; + return; + } + m68ki_exception_illegal(); + return; + default: + m68ki_exception_illegal(); + return; + } + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_movec_32_rc(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + switch (word2 & 0xfff) + { + case 0x000: /* SFC */ + REG_SFC = REG_DA[(word2 >> 12) & 15] & 7; + return; + case 0x001: /* DFC */ + REG_DFC = REG_DA[(word2 >> 12) & 15] & 7; + return; + case 0x002: /* CACR */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_CACR = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(); + return; + case 0x800: /* USP */ + REG_USP = REG_DA[(word2 >> 12) & 15]; + return; + case 0x801: /* VBR */ + REG_VBR = REG_DA[(word2 >> 12) & 15]; + return; + case 0x802: /* CAAR */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_CAAR = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(); + return; + case 0x803: /* MSP */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* we are in supervisor mode so just check for M flag */ + if(!FLAG_M) + { + REG_MSP = REG_DA[(word2 >> 12) & 15]; + return; + } + REG_SP = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(); + return; + case 0x804: /* ISP */ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(!FLAG_M) + { + REG_SP = REG_DA[(word2 >> 12) & 15]; + return; + } + REG_ISP = REG_DA[(word2 >> 12) & 15]; + return; + } + m68ki_exception_illegal(); + return; + default: + m68ki_exception_illegal(); + return; + } + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_movem_16_re_pd(void) +{ + uint i = 0; + uint register_list = OPER_I_16(); + uint ea = AY; + uint count = 0; + + for(; i < 16; i++) + if(register_list & (1 << i)) + { + ea -= 2; + m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i])); + count++; + } + AY = ea; + + USE_CYCLES(count<> 8)); + m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src)); +} + + +void m68k_op_movep_32_re(void) +{ + uint ea = EA_AY_DI_32(); + uint src = DX; + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24)); + m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16)); + m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8)); + m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src)); +} + + +void m68k_op_movep_16_er(void) +{ + uint ea = EA_AY_DI_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2)); +} + + +void m68k_op_movep_32_er(void) +{ + uint ea = EA_AY_DI_32(); + + DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16) + + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6); +} + + +void m68k_op_moves_8_ai(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_pi(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_pi7(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_A7_PI_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_pd(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_pd7(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_A7_PD_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_di(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_ix(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_aw(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_8_al(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_8(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_ai(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_pi(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_pd(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_di(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_ix(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_aw(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_16_al(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_16(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15])); + return; + } + if(BIT_F(word2)) /* Memory to address register */ + { + REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC)); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to data register */ + REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_ai(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_AI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_pi(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_pd(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_PD_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_di(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_DI_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_ix(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AY_IX_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_aw(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AW_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moves_32_al(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + if(FLAG_S) + { + uint word2 = OPER_I_16(); + uint ea = EA_AL_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + if(BIT_B(word2)) /* Register to memory */ + { + m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + /* Memory to register */ + REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC); + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + USE_CYCLES(2); + return; + } + m68ki_exception_privilege_violation(); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_moveq_32(void) +{ + uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR)); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_d(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_ai(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_AI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_pi(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_pd(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_PD_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_di(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_DI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_ix(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AY_IX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_aw(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AW_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_al(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_AL_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_pcdi(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCDI_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_pcix(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_PCIX_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_muls_16_i(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(OPER_I_16()) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst))); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_d(void) +{ + uint* r_dst = &DX; + uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_ai(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_AI_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_pi(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_PI_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_pd(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_PD_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_di(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_DI_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_ix(void) +{ + uint* r_dst = &DX; + uint res = OPER_AY_IX_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_aw(void) +{ + uint* r_dst = &DX; + uint res = OPER_AW_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_al(void) +{ + uint* r_dst = &DX; + uint res = OPER_AL_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_pcdi(void) +{ + uint* r_dst = &DX; + uint res = OPER_PCDI_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_pcix(void) +{ + uint* r_dst = &DX; + uint res = OPER_PCIX_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mulu_16_i(void) +{ + uint* r_dst = &DX; + uint res = OPER_I_16() * MASK_OUT_ABOVE_16(*r_dst); + + *r_dst = res; + + FLAG_Z = res; + FLAG_N = NFLAG_32(res); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_mull_32_d(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = DY; + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = DY; + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_ai(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_AI_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_AI_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_pi(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_PI_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_PI_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_pd(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_PD_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_PD_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_di(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_DI_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_DI_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_ix(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AY_IX_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AY_IX_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_aw(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AW_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AW_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_al(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_AL_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_AL_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_pcdi(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_PCDI_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_PCDI_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_pcix(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_PCIX_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_PCIX_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +void m68k_op_mull_32_i(void) +{ +#if M68K_USE_64_BIT + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint64 src = OPER_I_32(); + uint64 dst = REG_D[(word2 >> 12) & 7]; + uint64 res; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + res = (sint64)((sint32)src) * (sint64)((sint32)dst); + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = ((sint64)res != (sint32)res)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + + res = src * dst; + if(!BIT_A(word2)) + { + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_N = NFLAG_32(res); + FLAG_V = (res > 0xffffffff)<<7; + REG_D[(word2 >> 12) & 7] = FLAG_Z; + return; + } + FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32); + FLAG_N = NFLAG_64(res); + FLAG_V = VFLAG_CLEAR; + REG_D[word2 & 7] = (res >> 32); + REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res); + return; + } + m68ki_exception_illegal(); + +#else + + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint word2 = OPER_I_16(); + uint src = OPER_I_32(); + uint dst = REG_D[(word2 >> 12) & 7]; + uint neg = GET_MSB_32(src ^ dst); + uint src1; + uint src2; + uint dst1; + uint dst2; + uint r1; + uint r2; + uint r3; + uint r4; + uint lo; + uint hi; + + FLAG_C = CFLAG_CLEAR; + + if(BIT_B(word2)) /* signed */ + { + if(GET_MSB_32(src)) + src = (uint)MASK_OUT_ABOVE_32(-(sint)src); + if(GET_MSB_32(dst)) + dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst); + } + + src1 = MASK_OUT_ABOVE_16(src); + src2 = src>>16; + dst1 = MASK_OUT_ABOVE_16(dst); + dst2 = dst>>16; + + + r1 = src1 * dst1; + r2 = src1 * dst2; + r3 = src2 * dst1; + r4 = src2 * dst2; + + lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16); + hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16); + + if(BIT_B(word2) && neg) + { + hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0)); + lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo); + } + + if(BIT_A(word2)) + { + REG_D[word2 & 7] = hi; + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(hi); + FLAG_Z = hi | lo; + FLAG_V = VFLAG_CLEAR; + return; + } + + REG_D[(word2 >> 12) & 7] = lo; + FLAG_N = NFLAG_32(lo); + FLAG_Z = lo; + if(BIT_B(word2)) + FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7; + else + FLAG_V = (hi != 0) << 7; + return; + } + m68ki_exception_illegal(); + +#endif +} + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + diff --git a/MCUME_teensy/teensygen/musashi34/m68kopnz.c b/MCUME_teensy/teensygen/musashi34/m68kopnz.c new file mode 100644 index 0000000..a2ffbf6 --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68kopnz.c @@ -0,0 +1,8817 @@ +#include "m68kcpu.h" + +/* ======================================================================== */ +/* ========================= INSTRUCTION HANDLERS ========================= */ +/* ======================================================================== */ + + +void m68k_op_nbcd_8_d(void) +{ + uint* r_dst = &DY; + uint dst = *r_dst; + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_nbcd_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_nbcd_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_nbcd_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_nbcd_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_nbcd_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_nbcd_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_nbcd_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_nbcd_8_aw(void) +{ + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_nbcd_8_al(void) +{ + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1()); + + if(res != 0x9a) + { + FLAG_V = ~res; /* Undefined V behavior */ + + if((res & 0x0f) == 0xa) + res = (res & 0xf0) + 0x10; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + + m68ki_write_8(ea, MASK_OUT_ABOVE_8(res)); + + FLAG_Z |= res; + FLAG_C = CFLAG_SET; + FLAG_X = XFLAG_SET; + } + else + { + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + FLAG_X = XFLAG_CLEAR; + } + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ +} + + +void m68k_op_neg_8_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_8(*r_dst); + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = *r_dst & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_neg_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_8_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_8(res); + FLAG_C = FLAG_X = CFLAG_8(res); + FLAG_V = src & res; + FLAG_Z = MASK_OUT_ABOVE_8(res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_neg_16_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_16(*r_dst); + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (*r_dst & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_neg_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_16(res); + FLAG_C = FLAG_X = CFLAG_16(res); + FLAG_V = (src & res)>>8; + FLAG_Z = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_neg_32_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - *r_dst; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res); + FLAG_V = (*r_dst & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_neg_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_di(void) +{ + uint ea = EA_AY_DI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_aw(void) +{ + uint ea = EA_AW_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_neg_32_al(void) +{ + uint ea = EA_AL_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - src; + + FLAG_N = NFLAG_32(res); + FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + FLAG_Z = MASK_OUT_ABOVE_32(res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_negx_8_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = *r_dst & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_negx_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_aw(void) +{ + uint ea = EA_AW_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_8_al(void) +{ + uint ea = EA_AL_8(); + uint src = m68ki_read_8(ea); + uint res = 0 - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = src & res; + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_negx_16_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (*r_dst & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +void m68k_op_negx_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = (src & res)>>8; + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_negx_32_d(void) +{ + uint* r_dst = &DY; + uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res); + FLAG_V = (*r_dst & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + *r_dst = res; +} + + +void m68k_op_negx_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_di(void) +{ + uint ea = EA_AY_DI_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_aw(void) +{ + uint ea = EA_AW_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_negx_32_al(void) +{ + uint ea = EA_AL_32(); + uint src = m68ki_read_32(ea); + uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res); + FLAG_V = (src & res)>>24; + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_nop(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ +} + + +void m68k_op_not_8_d(void) +{ + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_8(~*r_dst); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_aw(void) +{ + uint ea = EA_AW_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_8_al(void) +{ + uint ea = EA_AL_8(); + uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_d(void) +{ + uint* r_dst = &DY; + uint res = MASK_OUT_ABOVE_16(~*r_dst); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_aw(void) +{ + uint ea = EA_AW_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_16_al(void) +{ + uint ea = EA_AL_16(); + uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_d(void) +{ + uint* r_dst = &DY; + uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_di(void) +{ + uint ea = EA_AY_DI_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_aw(void) +{ + uint ea = EA_AW_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_not_32_al(void) +{ + uint ea = EA_AL_32(); + uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea)); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_d(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY))); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_ai(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_AI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pi(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pi7(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pd(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_PD_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pd7(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_A7_PD_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_di(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_DI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_ix(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AY_IX_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_aw(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AW_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_al(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_AL_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pcdi(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCDI_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_pcix(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_PCIX_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_er_i(void) +{ + uint res = MASK_OUT_ABOVE_8((DX |= OPER_I_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_d(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY))); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_ai(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_AI_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_pi(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PI_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_pd(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_PD_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_di(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_DI_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_ix(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AY_IX_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_aw(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AW_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_al(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_AL_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_pcdi(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCDI_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_pcix(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_PCIX_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_er_i(void) +{ + uint res = MASK_OUT_ABOVE_16((DX |= OPER_I_16())); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_d(void) +{ + uint res = DX |= DY; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_ai(void) +{ + uint res = DX |= OPER_AY_AI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_pi(void) +{ + uint res = DX |= OPER_AY_PI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_pd(void) +{ + uint res = DX |= OPER_AY_PD_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_di(void) +{ + uint res = DX |= OPER_AY_DI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_ix(void) +{ + uint res = DX |= OPER_AY_IX_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_aw(void) +{ + uint res = DX |= OPER_AW_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_al(void) +{ + uint res = DX |= OPER_AL_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_pcdi(void) +{ + uint res = DX |= OPER_PCDI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_pcix(void) +{ + uint res = DX |= OPER_PCIX_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_er_i(void) +{ + uint res = DX |= OPER_I_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_di(void) +{ + uint ea = EA_AY_DI_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_aw(void) +{ + uint ea = EA_AW_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_8_re_al(void) +{ + uint ea = EA_AL_8(); + uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_di(void) +{ + uint ea = EA_AY_DI_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_aw(void) +{ + uint ea = EA_AW_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_16_re_al(void) +{ + uint ea = EA_AL_16(); + uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_di(void) +{ + uint ea = EA_AY_DI_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_aw(void) +{ + uint ea = EA_AW_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_or_32_re_al(void) +{ + uint ea = EA_AL_32(); + uint res = DX | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_d(void) +{ + uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8())); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea)); + + m68ki_write_8(ea, res); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16()); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_d(void) +{ + uint res = DY |= OPER_I_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint res = src | m68ki_read_32(ea); + + m68ki_write_32(ea, res); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ori_16_toc(void) +{ + m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16()); +} + + +void m68k_op_ori_16_tos(void) +{ + if(FLAG_S) + { + uint src = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_sr(m68ki_get_sr() | src); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_pack_16_rr(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: DX and DY are reversed in Motorola's docs */ + uint src = DY + OPER_I_16(); + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pack_16_mm_ax7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint ea_src = EA_AY_PD_8(); + uint src = m68ki_read_8(ea_src); + ea_src = EA_AY_PD_8(); + src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); + + m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pack_16_mm_ay7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint ea_src = EA_A7_PD_8(); + uint src = m68ki_read_8(ea_src); + ea_src = EA_A7_PD_8(); + src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); + + m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pack_16_mm_axy7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint ea_src = EA_A7_PD_8(); + uint src = m68ki_read_8(ea_src); + ea_src = EA_A7_PD_8(); + src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); + + m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pack_16_mm(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint ea_src = EA_AY_PD_8(); + uint src = m68ki_read_8(ea_src); + ea_src = EA_AY_PD_8(); + src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16(); + + m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f)); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_pea_32_ai(void) +{ + uint ea = EA_AY_AI_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_di(void) +{ + uint ea = EA_AY_DI_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_ix(void) +{ + uint ea = EA_AY_IX_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_aw(void) +{ + uint ea = EA_AW_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_al(void) +{ + uint ea = EA_AL_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_pcdi(void) +{ + uint ea = EA_PCDI_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_pea_32_pcix(void) +{ + uint ea = EA_PCIX_32(); + + m68ki_push_32(ea); +} + + +void m68k_op_reset(void) +{ + if(FLAG_S) + { + m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */ + USE_CYCLES(CYC_RESET); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_ror_8_s(void) +{ + uint* r_dst = &DY; + uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint shift = orig_shift & 7; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROR_8(src, shift); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = src << (9-orig_shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = ROR_16(src, shift); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint64 src = *r_dst; + uint res = ROR_32(src, shift); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = src << (9-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_8_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift & 7; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROR_8(src, shift); + + if(orig_shift != 0) + { + USE_CYCLES(orig_shift<> ((shift - 1) & 15)) << 8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_32_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift & 31; + uint64 src = *r_dst; + uint res = ROR_32(src, shift); + + if(orig_shift != 0) + { + USE_CYCLES(orig_shift<> ((shift - 1) & 31)) << 8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_ror_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_16(src, 1); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src << 8; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_8_s(void) +{ + uint* r_dst = &DY; + uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint shift = orig_shift & 7; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROL_8(src, shift); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_C = src << orig_shift; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = ROL_16(src, shift); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> (8-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_32_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint64 src = *r_dst; + uint res = ROL_32(src, shift); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_C = src >> (24-shift); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_8_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift & 7; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROL_8(src, shift); + + if(orig_shift != 0) + { + USE_CYCLES(orig_shift<> 8; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + FLAG_C = (src & 1)<<8; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_16(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_32_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift & 31; + uint64 src = *r_dst; + uint res = ROL_32(src, shift); + + if(orig_shift != 0) + { + USE_CYCLES(orig_shift<> (32 - shift)) << 8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = CFLAG_CLEAR; + FLAG_N = NFLAG_32(src); + FLAG_Z = src; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rol_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1)); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_C = src >> 7; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift); + + FLAG_C = FLAG_X = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_32_s(void) +{ +#if M68K_USE_64_BIT + + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint64 src = *r_dst; + uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); + + res = ROR_33_64(res, shift); + + FLAG_C = FLAG_X = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + +#else + + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift))); + uint new_x_flag = src & (1 << (shift - 1)); + + *r_dst = res; + + FLAG_C = FLAG_X = (new_x_flag != 0)<<8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + +#endif +} + + +void m68k_op_roxr_8_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + uint shift = orig_shift % 9; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift); + + USE_CYCLES(orig_shift<> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = FLAG_X; + FLAG_N = NFLAG_16(*r_dst); + FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_32_r(void) +{ +#if M68K_USE_64_BIT + + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + uint shift = orig_shift % 33; + uint64 src = *r_dst; + uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); + + res = ROR_33_64(res, shift); + + USE_CYCLES(orig_shift<> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = FLAG_X; + FLAG_N = NFLAG_32(*r_dst); + FLAG_Z = *r_dst; + FLAG_V = VFLAG_CLEAR; + +#else + + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift % 33; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift))); + uint new_x_flag = src & (1 << (shift - 1)); + + if(orig_shift != 0) + USE_CYCLES(orig_shift<> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxr_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_8_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift); + + FLAG_C = FLAG_X = res; + res = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_s(void) +{ + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = MASK_OUT_ABOVE_16(*r_dst); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_32_s(void) +{ +#if M68K_USE_64_BIT + + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint64 src = *r_dst; + uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); + + res = ROL_33_64(res, shift); + + FLAG_C = FLAG_X = res >> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + +#else + + uint* r_dst = &DY; + uint shift = (((REG_IR >> 9) - 1) & 7) + 1; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1))); + uint new_x_flag = src & (1 << (32 - shift)); + + *r_dst = res; + + FLAG_C = FLAG_X = (new_x_flag != 0)<<8; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + +#endif +} + + +void m68k_op_roxl_8_r(void) +{ + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + + + if(orig_shift != 0) + { + uint shift = orig_shift % 9; + uint src = MASK_OUT_ABOVE_8(*r_dst); + uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift); + + USE_CYCLES(orig_shift<> 8; + res = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = FLAG_X; + FLAG_N = NFLAG_16(*r_dst); + FLAG_Z = MASK_OUT_ABOVE_16(*r_dst); + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_32_r(void) +{ +#if M68K_USE_64_BIT + + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + + if(orig_shift != 0) + { + uint shift = orig_shift % 33; + uint64 src = *r_dst; + uint64 res = src | (((uint64)XFLAG_AS_1()) << 32); + + res = ROL_33_64(res, shift); + + USE_CYCLES(orig_shift<> 24; + res = MASK_OUT_ABOVE_32(res); + + *r_dst = res; + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + return; + } + + FLAG_C = FLAG_X; + FLAG_N = NFLAG_32(*r_dst); + FLAG_Z = *r_dst; + FLAG_V = VFLAG_CLEAR; + +#else + + uint* r_dst = &DY; + uint orig_shift = DX & 0x3f; + uint shift = orig_shift % 33; + uint src = *r_dst; + uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1))); + uint new_x_flag = src & (1 << (32 - shift)); + + if(orig_shift != 0) + USE_CYCLES(orig_shift<> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_aw(void) +{ + uint ea = EA_AW_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_roxl_16_al(void) +{ + uint ea = EA_AL_16(); + uint src = m68ki_read_16(ea); + uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1); + + FLAG_C = FLAG_X = res >> 8; + res = MASK_OUT_ABOVE_16(res); + + m68ki_write_16(ea, res); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_rtd_32(void) +{ + if(CPU_TYPE_IS_010_PLUS(CPU_TYPE)) + { + uint new_pc = m68ki_pull_32(); + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16())); + m68ki_jump(new_pc); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_rte_32(void) +{ + if(FLAG_S) + { + uint new_sr; + uint new_pc; + uint format_word; + + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + + if(CPU_TYPE_IS_000(CPU_TYPE)) + { + new_sr = m68ki_pull_16(); + new_pc = m68ki_pull_32(); + m68ki_jump(new_pc); + m68ki_set_sr(new_sr); + + CPU_INSTR_MODE = INSTRUCTION_YES; + CPU_RUN_MODE = RUN_MODE_NORMAL; + + return; + } + + if(CPU_TYPE_IS_010(CPU_TYPE)) + { + format_word = m68ki_read_16(REG_A[7]+6) >> 12; + if(format_word == 0) + { + new_sr = m68ki_pull_16(); + new_pc = m68ki_pull_32(); + m68ki_fake_pull_16(); /* format word */ + m68ki_jump(new_pc); + m68ki_set_sr(new_sr); + CPU_INSTR_MODE = INSTRUCTION_YES; + CPU_RUN_MODE = RUN_MODE_NORMAL; + return; + } + CPU_INSTR_MODE = INSTRUCTION_YES; + CPU_RUN_MODE = RUN_MODE_NORMAL; + /* Not handling bus fault (9) */ + m68ki_exception_format_error(); + return; + } + + /* Otherwise it's 020 */ +rte_loop: + format_word = m68ki_read_16(REG_A[7]+6) >> 12; + switch(format_word) + { + case 0: /* Normal */ + new_sr = m68ki_pull_16(); + new_pc = m68ki_pull_32(); + m68ki_fake_pull_16(); /* format word */ + m68ki_jump(new_pc); + m68ki_set_sr(new_sr); + CPU_INSTR_MODE = INSTRUCTION_YES; + CPU_RUN_MODE = RUN_MODE_NORMAL; + return; + case 1: /* Throwaway */ + new_sr = m68ki_pull_16(); + m68ki_fake_pull_32(); /* program counter */ + m68ki_fake_pull_16(); /* format word */ + m68ki_set_sr_noint(new_sr); + goto rte_loop; + case 2: /* Trap */ + new_sr = m68ki_pull_16(); + new_pc = m68ki_pull_32(); + m68ki_fake_pull_16(); /* format word */ + m68ki_fake_pull_32(); /* address */ + m68ki_jump(new_pc); + m68ki_set_sr(new_sr); + CPU_INSTR_MODE = INSTRUCTION_YES; + CPU_RUN_MODE = RUN_MODE_NORMAL; + return; + } + /* Not handling long or short bus fault */ + CPU_INSTR_MODE = INSTRUCTION_YES; + CPU_RUN_MODE = RUN_MODE_NORMAL; + m68ki_exception_format_error(); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_rtm_32(void) +{ + if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE)) + { + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n", + m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR, + m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2)))); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_rtr_32(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_set_ccr(m68ki_pull_16()); + m68ki_jump(m68ki_pull_32()); +} + + +void m68k_op_rts_32(void) +{ + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + m68ki_jump(m68ki_pull_32()); +} + + +void m68k_op_sbcd_8_rr(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_sbcd_8_mm_ax7(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_sbcd_8_mm_ay7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_sbcd_8_mm_axy7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_sbcd_8_mm(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1(); + + FLAG_V = ~res; /* Undefined V behavior */ + + if(res > 9) + res -= 6; + res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src); + FLAG_X = FLAG_C = (res > 0x99) << 8; + if(FLAG_C) + res += 0xa0; + + res = MASK_OUT_ABOVE_8(res); + + FLAG_V &= res; /* Undefined V behavior part II */ + FLAG_N = NFLAG_8(res); /* Undefined N behavior */ + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_st_8_d(void) +{ + DY |= 0xff; +} + + +void m68k_op_st_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), 0xff); +} + + +void m68k_op_st_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), 0xff); +} + + +void m68k_op_st_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), 0xff); +} + + +void m68k_op_st_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), 0xff); +} + + +void m68k_op_st_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), 0xff); +} + + +void m68k_op_st_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), 0xff); +} + + +void m68k_op_st_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), 0xff); +} + + +void m68k_op_st_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), 0xff); +} + + +void m68k_op_st_8_al(void) +{ + m68ki_write_8(EA_AL_8(), 0xff); +} + + +void m68k_op_sf_8_d(void) +{ + DY &= 0xffffff00; +} + + +void m68k_op_sf_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), 0); +} + + +void m68k_op_sf_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), 0); +} + + +void m68k_op_sf_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), 0); +} + + +void m68k_op_sf_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), 0); +} + + +void m68k_op_sf_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), 0); +} + + +void m68k_op_sf_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), 0); +} + + +void m68k_op_sf_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), 0); +} + + +void m68k_op_sf_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), 0); +} + + +void m68k_op_sf_8_al(void) +{ + m68ki_write_8(EA_AL_8(), 0); +} + + +void m68k_op_shi_8_d(void) +{ + if(COND_HI()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sls_8_d(void) +{ + if(COND_LS()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_scc_8_d(void) +{ + if(COND_CC()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_scs_8_d(void) +{ + if(COND_CS()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sne_8_d(void) +{ + if(COND_NE()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_seq_8_d(void) +{ + if(COND_EQ()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_svc_8_d(void) +{ + if(COND_VC()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_svs_8_d(void) +{ + if(COND_VS()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_spl_8_d(void) +{ + if(COND_PL()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_smi_8_d(void) +{ + if(COND_MI()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sge_8_d(void) +{ + if(COND_GE()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_slt_8_d(void) +{ + if(COND_LT()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sgt_8_d(void) +{ + if(COND_GT()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_sle_8_d(void) +{ + if(COND_LE()) + { + DY |= 0xff; + USE_CYCLES(CYC_SCC_R_TRUE); + return; + } + DY &= 0xffffff00; +} + + +void m68k_op_shi_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_shi_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_HI() ? 0xff : 0); +} + + +void m68k_op_sls_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_sls_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_LS() ? 0xff : 0); +} + + +void m68k_op_scc_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scc_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_CC() ? 0xff : 0); +} + + +void m68k_op_scs_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_scs_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_CS() ? 0xff : 0); +} + + +void m68k_op_sne_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_sne_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_NE() ? 0xff : 0); +} + + +void m68k_op_seq_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_seq_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_EQ() ? 0xff : 0); +} + + +void m68k_op_svc_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svc_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_VC() ? 0xff : 0); +} + + +void m68k_op_svs_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_svs_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_VS() ? 0xff : 0); +} + + +void m68k_op_spl_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_spl_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_PL() ? 0xff : 0); +} + + +void m68k_op_smi_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_smi_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_MI() ? 0xff : 0); +} + + +void m68k_op_sge_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_sge_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_GE() ? 0xff : 0); +} + + +void m68k_op_slt_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_slt_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_LT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sgt_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_GT() ? 0xff : 0); +} + + +void m68k_op_sle_8_ai(void) +{ + m68ki_write_8(EA_AY_AI_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_pi(void) +{ + m68ki_write_8(EA_AY_PI_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_pi7(void) +{ + m68ki_write_8(EA_A7_PI_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_pd(void) +{ + m68ki_write_8(EA_AY_PD_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_pd7(void) +{ + m68ki_write_8(EA_A7_PD_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_di(void) +{ + m68ki_write_8(EA_AY_DI_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_ix(void) +{ + m68ki_write_8(EA_AY_IX_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_aw(void) +{ + m68ki_write_8(EA_AW_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_sle_8_al(void) +{ + m68ki_write_8(EA_AL_8(), COND_LE() ? 0xff : 0); +} + + +void m68k_op_stop(void) +{ + if(FLAG_S) + { + uint new_sr = OPER_I_16(); + m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */ + CPU_STOPPED |= STOP_LEVEL_STOP; + m68ki_set_sr(new_sr); + if(m68ki_remaining_cycles >= CYC_INSTRUCTION[REG_IR]) + m68ki_remaining_cycles = CYC_INSTRUCTION[REG_IR]; + else + USE_ALL_CYCLES(); + return; + } + m68ki_exception_privilege_violation(); +} + + +void m68k_op_sub_8_er_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pi7(void) +{ + uint* r_dst = &DX; + uint src = OPER_A7_PI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pd7(void) +{ + uint* r_dst = &DX; + uint src = OPER_A7_PD_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_8_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_d(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_a(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(AY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_16_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_sub_32_er_d(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_a(void) +{ + uint* r_dst = &DX; + uint src = AY; + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_ai(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_AI_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_pi(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PI_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_pd(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_PD_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_di(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_DI_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_ix(void) +{ + uint* r_dst = &DX; + uint src = OPER_AY_IX_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_aw(void) +{ + uint* r_dst = &DX; + uint src = OPER_AW_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_al(void) +{ + uint* r_dst = &DX; + uint src = OPER_AL_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_pcdi(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCDI_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_pcix(void) +{ + uint* r_dst = &DX; + uint src = OPER_PCIX_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_32_er_i(void) +{ + uint* r_dst = &DX; + uint src = OPER_I_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_sub_8_re_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_di(void) +{ + uint ea = EA_AY_DI_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_aw(void) +{ + uint ea = EA_AW_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_8_re_al(void) +{ + uint ea = EA_AL_8(); + uint src = MASK_OUT_ABOVE_8(DX); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_ai(void) +{ + uint ea = EA_AY_AI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_pi(void) +{ + uint ea = EA_AY_PI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_pd(void) +{ + uint ea = EA_AY_PD_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_di(void) +{ + uint ea = EA_AY_DI_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_ix(void) +{ + uint ea = EA_AY_IX_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_aw(void) +{ + uint ea = EA_AW_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_16_re_al(void) +{ + uint ea = EA_AL_16(); + uint src = MASK_OUT_ABOVE_16(DX); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_ai(void) +{ + uint ea = EA_AY_AI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_pi(void) +{ + uint ea = EA_AY_PI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_pd(void) +{ + uint ea = EA_AY_PD_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_di(void) +{ + uint ea = EA_AY_DI_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_ix(void) +{ + uint ea = EA_AY_IX_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_aw(void) +{ + uint ea = EA_AW_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_sub_32_re_al(void) +{ + uint ea = EA_AL_32(); + uint src = DX; + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_suba_16_d(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY)); +} + + +void m68k_op_suba_16_a(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY)); +} + + +void m68k_op_suba_16_ai(void) +{ + signed short src = MAKE_INT_16(OPER_AY_AI_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_16_pi(void) +{ + signed short src = MAKE_INT_16(OPER_AY_PI_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_16_pd(void) +{ + signed short src = MAKE_INT_16(OPER_AY_PD_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_16_di(void) +{ + signed short src = MAKE_INT_16(OPER_AY_DI_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_16_ix(void) +{ + signed short src = MAKE_INT_16(OPER_AY_IX_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_16_aw(void) +{ + signed short src = MAKE_INT_16(OPER_AW_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_16_al(void) +{ + signed short src = MAKE_INT_16(OPER_AL_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_16_pcdi(void) +{ + signed short src = MAKE_INT_16(OPER_PCDI_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_16_pcix(void) +{ + signed short src = MAKE_INT_16(OPER_PCIX_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_16_i(void) +{ + signed short src = MAKE_INT_16(OPER_I_16()); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_d(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY); +} + + +void m68k_op_suba_32_a(void) +{ + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY); +} + + +void m68k_op_suba_32_ai(void) +{ + uint src = OPER_AY_AI_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_pi(void) +{ + uint src = OPER_AY_PI_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_pd(void) +{ + uint src = OPER_AY_PD_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_di(void) +{ + uint src = OPER_AY_DI_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_ix(void) +{ + uint src = OPER_AY_IX_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_aw(void) +{ + uint src = OPER_AW_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_al(void) +{ + uint src = OPER_AL_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_pcdi(void) +{ + uint src = OPER_PCDI_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_pcix(void) +{ + uint src = OPER_PCIX_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_suba_32_i(void) +{ + uint src = OPER_I_32(); + uint* r_dst = &AX; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - src); +} + + +void m68k_op_subi_8_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_8(); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_subi_8_ai(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_pi(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_pi7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_pd(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_pd7(void) +{ + uint src = OPER_I_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_di(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_ix(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_aw(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_8_al(void) +{ + uint src = OPER_I_8(); + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subi_16_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_16(); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_subi_16_ai(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_AI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_pi(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_pd(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_di(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_DI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_ix(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AY_IX_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_aw(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AW_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_16_al(void) +{ + uint src = OPER_I_16(); + uint ea = EA_AL_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subi_32_d(void) +{ + uint* r_dst = &DY; + uint src = OPER_I_32(); + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_subi_32_ai(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_AI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_pi(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_pd(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_di(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_DI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_ix(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AY_IX_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_aw(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AW_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subi_32_al(void) +{ + uint src = OPER_I_32(); + uint ea = EA_AL_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_8_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z; +} + + +void m68k_op_subq_8_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_pi7(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_pd7(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_8_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src; + + FLAG_N = NFLAG_8(res); + FLAG_Z = MASK_OUT_ABOVE_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + m68ki_write_8(ea, FLAG_Z); +} + + +void m68k_op_subq_16_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z; +} + + +void m68k_op_subq_16_a(void) +{ + uint* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1)); +} + + +void m68k_op_subq_16_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_16_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src; + + FLAG_N = NFLAG_16(res); + FLAG_Z = MASK_OUT_ABOVE_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + m68ki_write_16(ea, FLAG_Z); +} + + +void m68k_op_subq_32_d(void) +{ + uint* r_dst = &DY; + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint dst = *r_dst; + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + *r_dst = FLAG_Z; +} + + +void m68k_op_subq_32_a(void) +{ + uint* r_dst = &AY; + + *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1)); +} + + +void m68k_op_subq_32_ai(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_AI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_pi(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_pd(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_di(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_DI_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_ix(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AY_IX_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_aw(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AW_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subq_32_al(void) +{ + uint src = (((REG_IR >> 9) - 1) & 7) + 1; + uint ea = EA_AL_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src; + + FLAG_N = NFLAG_32(res); + FLAG_Z = MASK_OUT_ABOVE_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + m68ki_write_32(ea, FLAG_Z); +} + + +void m68k_op_subx_8_rr(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_8(DY); + uint dst = MASK_OUT_ABOVE_8(*r_dst); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_8(*r_dst) | res; +} + + +void m68k_op_subx_16_rr(void) +{ + uint* r_dst = &DX; + uint src = MASK_OUT_ABOVE_16(DY); + uint dst = MASK_OUT_ABOVE_16(*r_dst); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | res; +} + + +void m68k_op_subx_32_rr(void) +{ + uint* r_dst = &DX; + uint src = DY; + uint dst = *r_dst; + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + *r_dst = res; +} + + +void m68k_op_subx_8_mm_ax7(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_subx_8_mm_ay7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_subx_8_mm_axy7(void) +{ + uint src = OPER_A7_PD_8(); + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_subx_8_mm(void) +{ + uint src = OPER_AY_PD_8(); + uint ea = EA_AX_PD_8(); + uint dst = m68ki_read_8(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_8(res); + FLAG_X = FLAG_C = CFLAG_8(res); + FLAG_V = VFLAG_SUB_8(src, dst, res); + + res = MASK_OUT_ABOVE_8(res); + FLAG_Z |= res; + + m68ki_write_8(ea, res); +} + + +void m68k_op_subx_16_mm(void) +{ + uint src = OPER_AY_PD_16(); + uint ea = EA_AX_PD_16(); + uint dst = m68ki_read_16(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_16(res); + FLAG_X = FLAG_C = CFLAG_16(res); + FLAG_V = VFLAG_SUB_16(src, dst, res); + + res = MASK_OUT_ABOVE_16(res); + FLAG_Z |= res; + + m68ki_write_16(ea, res); +} + + +void m68k_op_subx_32_mm(void) +{ + uint src = OPER_AY_PD_32(); + uint ea = EA_AX_PD_32(); + uint dst = m68ki_read_32(ea); + uint res = dst - src - XFLAG_AS_1(); + + FLAG_N = NFLAG_32(res); + FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res); + FLAG_V = VFLAG_SUB_32(src, dst, res); + + res = MASK_OUT_ABOVE_32(res); + FLAG_Z |= res; + + m68ki_write_32(ea, res); +} + + +void m68k_op_swap_32(void) +{ + uint* r_dst = &DY; + + FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16); + *r_dst = (*r_dst>>16) | FLAG_Z; + + FLAG_Z = *r_dst; + FLAG_N = NFLAG_32(*r_dst); + FLAG_C = CFLAG_CLEAR; + FLAG_V = VFLAG_CLEAR; +} + + +void m68k_op_tas_8_d(void) +{ + uint* r_dst = &DY; + + FLAG_Z = MASK_OUT_ABOVE_8(*r_dst); + FLAG_N = NFLAG_8(*r_dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + *r_dst |= 0x80; +} + + +void m68k_op_tas_8_ai(void) +{ + uint ea = EA_AY_AI_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + m68ki_write_8(ea, dst | 0x80); +} + + +void m68k_op_tas_8_pi(void) +{ + uint ea = EA_AY_PI_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + m68ki_write_8(ea, dst | 0x80); +} + + +void m68k_op_tas_8_pi7(void) +{ + uint ea = EA_A7_PI_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + m68ki_write_8(ea, dst | 0x80); +} + + +void m68k_op_tas_8_pd(void) +{ + uint ea = EA_AY_PD_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + m68ki_write_8(ea, dst | 0x80); +} + + +void m68k_op_tas_8_pd7(void) +{ + uint ea = EA_A7_PD_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + m68ki_write_8(ea, dst | 0x80); +} + + +void m68k_op_tas_8_di(void) +{ + uint ea = EA_AY_DI_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + m68ki_write_8(ea, dst | 0x80); +} + + +void m68k_op_tas_8_ix(void) +{ + uint ea = EA_AY_IX_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + m68ki_write_8(ea, dst | 0x80); +} + + +void m68k_op_tas_8_aw(void) +{ + uint ea = EA_AW_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + m68ki_write_8(ea, dst | 0x80); +} + + +void m68k_op_tas_8_al(void) +{ + uint ea = EA_AL_8(); + uint dst = m68ki_read_8(ea); + + FLAG_Z = dst; + FLAG_N = NFLAG_8(dst); + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + m68ki_write_8(ea, dst | 0x80); +} + + +void m68k_op_trap(void) +{ + /* Trap#n stacks exception frame type 0 */ + m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */ +} + + +void m68k_op_trapt(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapt_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapf(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapf_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapf_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traphi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_HI()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapls(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LS()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcc(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CC()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcs(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CS()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapne(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_NE()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapeq(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_EQ()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvc(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VC()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvs(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VS()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trappl(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_PL()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapmi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_MI()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapge(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GE()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traplt(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LT()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapgt(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GT()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traple(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LE()) + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traphi_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_HI()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapls_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcc_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CC()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcs_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapne_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_NE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapeq_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_EQ()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvc_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VC()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvs_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trappl_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_PL()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapmi_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_MI()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapge_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traplt_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LT()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapgt_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GT()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traple_16(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 2; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traphi_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_HI()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapls_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CC()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapcs_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_CS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapne_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_NE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapeq_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_EQ()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvc_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VC()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapvs_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_VS()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trappl_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_PL()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapmi_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_MI()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapge_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traplt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LT()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapgt_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_GT()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_traple_32(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + if(COND_LE()) + { + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ + return; + } + REG_PC += 4; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_trapv(void) +{ + if(COND_VC()) + { + return; + } + m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */ +} + + +void m68k_op_tst_8_d(void) +{ + uint res = MASK_OUT_ABOVE_8(DY); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_ai(void) +{ + uint res = OPER_AY_AI_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pi(void) +{ + uint res = OPER_AY_PI_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pi7(void) +{ + uint res = OPER_A7_PI_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pd(void) +{ + uint res = OPER_AY_PD_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pd7(void) +{ + uint res = OPER_A7_PD_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_di(void) +{ + uint res = OPER_AY_DI_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_ix(void) +{ + uint res = OPER_AY_IX_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_aw(void) +{ + uint res = OPER_AW_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_al(void) +{ + uint res = OPER_AL_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_8_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCDI_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_8_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCIX_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_8_i(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_I_8(); + + FLAG_N = NFLAG_8(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_16_d(void) +{ + uint res = MASK_OUT_ABOVE_16(DY); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_a(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = MAKE_INT_16(AY); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_16_ai(void) +{ + uint res = OPER_AY_AI_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_pi(void) +{ + uint res = OPER_AY_PI_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_pd(void) +{ + uint res = OPER_AY_PD_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_di(void) +{ + uint res = OPER_AY_DI_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_ix(void) +{ + uint res = OPER_AY_IX_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_aw(void) +{ + uint res = OPER_AW_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_al(void) +{ + uint res = OPER_AL_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_16_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCDI_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_16_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCIX_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_16_i(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_I_16(); + + FLAG_N = NFLAG_16(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_32_d(void) +{ + uint res = DY; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_a(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = AY; + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_32_ai(void) +{ + uint res = OPER_AY_AI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_pi(void) +{ + uint res = OPER_AY_PI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_pd(void) +{ + uint res = OPER_AY_PD_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_di(void) +{ + uint res = OPER_AY_DI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_ix(void) +{ + uint res = OPER_AY_IX_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_aw(void) +{ + uint res = OPER_AW_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_al(void) +{ + uint res = OPER_AL_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; +} + + +void m68k_op_tst_32_pcdi(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCDI_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_32_pcix(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_PCIX_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_tst_32_i(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint res = OPER_I_32(); + + FLAG_N = NFLAG_32(res); + FLAG_Z = res; + FLAG_V = VFLAG_CLEAR; + FLAG_C = CFLAG_CLEAR; + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unlk_32_a7(void) +{ + REG_A[7] = m68ki_read_32(REG_A[7]); +} + + +void m68k_op_unlk_32(void) +{ + uint* r_dst = &AY; + + REG_A[7] = *r_dst; + *r_dst = m68ki_pull_32(); +} + + +void m68k_op_unpk_16_rr(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: DX and DY are reversed in Motorola's docs */ + uint src = DY; + uint* r_dst = &DX; + + *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unpk_16_mm_ax7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint src = OPER_AY_PD_8(); + uint ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + ea_dst = EA_A7_PD_8(); + m68ki_write_8(ea_dst, (src >> 8) & 0xff); + ea_dst = EA_A7_PD_8(); + m68ki_write_8(ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unpk_16_mm_ay7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint src = OPER_A7_PD_8(); + uint ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + ea_dst = EA_AX_PD_8(); + m68ki_write_8(ea_dst, (src >> 8) & 0xff); + ea_dst = EA_AX_PD_8(); + m68ki_write_8(ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unpk_16_mm_axy7(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + uint src = OPER_A7_PD_8(); + uint ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + ea_dst = EA_A7_PD_8(); + m68ki_write_8(ea_dst, (src >> 8) & 0xff); + ea_dst = EA_A7_PD_8(); + m68ki_write_8(ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(); +} + + +void m68k_op_unpk_16_mm(void) +{ + if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE)) + { + /* Note: AX and AY are reversed in Motorola's docs */ + uint src = OPER_AY_PD_8(); + uint ea_dst; + + src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16(); + ea_dst = EA_AX_PD_8(); + m68ki_write_8(ea_dst, (src >> 8) & 0xff); + ea_dst = EA_AX_PD_8(); + m68ki_write_8(ea_dst, src & 0xff); + return; + } + m68ki_exception_illegal(); +} + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + + diff --git a/MCUME_teensy/teensygen/musashi34/m68kops.h b/MCUME_teensy/teensygen/musashi34/m68kops.h new file mode 100644 index 0000000..a531e73 --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68kops.h @@ -0,0 +1,1988 @@ +#ifndef M68KOPS__HEADER +#define M68KOPS__HEADER + +/* ======================================================================== */ +/* ============================ OPCODE HANDLERS =========================== */ +/* ======================================================================== */ + + +void m68k_op_1010(void); +void m68k_op_1111(void); +void m68k_op_abcd_8_rr(void); +void m68k_op_abcd_8_mm_ax7(void); +void m68k_op_abcd_8_mm_ay7(void); +void m68k_op_abcd_8_mm_axy7(void); +void m68k_op_abcd_8_mm(void); +void m68k_op_add_8_er_d(void); +void m68k_op_add_8_er_ai(void); +void m68k_op_add_8_er_pi(void); +void m68k_op_add_8_er_pi7(void); +void m68k_op_add_8_er_pd(void); +void m68k_op_add_8_er_pd7(void); +void m68k_op_add_8_er_di(void); +void m68k_op_add_8_er_ix(void); +void m68k_op_add_8_er_aw(void); +void m68k_op_add_8_er_al(void); +void m68k_op_add_8_er_pcdi(void); +void m68k_op_add_8_er_pcix(void); +void m68k_op_add_8_er_i(void); +void m68k_op_add_16_er_d(void); +void m68k_op_add_16_er_a(void); +void m68k_op_add_16_er_ai(void); +void m68k_op_add_16_er_pi(void); +void m68k_op_add_16_er_pd(void); +void m68k_op_add_16_er_di(void); +void m68k_op_add_16_er_ix(void); +void m68k_op_add_16_er_aw(void); +void m68k_op_add_16_er_al(void); +void m68k_op_add_16_er_pcdi(void); +void m68k_op_add_16_er_pcix(void); +void m68k_op_add_16_er_i(void); +void m68k_op_add_32_er_d(void); +void m68k_op_add_32_er_a(void); +void m68k_op_add_32_er_ai(void); +void m68k_op_add_32_er_pi(void); +void m68k_op_add_32_er_pd(void); +void m68k_op_add_32_er_di(void); +void m68k_op_add_32_er_ix(void); +void m68k_op_add_32_er_aw(void); +void m68k_op_add_32_er_al(void); +void m68k_op_add_32_er_pcdi(void); +void m68k_op_add_32_er_pcix(void); +void m68k_op_add_32_er_i(void); +void m68k_op_add_8_re_ai(void); +void m68k_op_add_8_re_pi(void); +void m68k_op_add_8_re_pi7(void); +void m68k_op_add_8_re_pd(void); +void m68k_op_add_8_re_pd7(void); +void m68k_op_add_8_re_di(void); +void m68k_op_add_8_re_ix(void); +void m68k_op_add_8_re_aw(void); +void m68k_op_add_8_re_al(void); +void m68k_op_add_16_re_ai(void); +void m68k_op_add_16_re_pi(void); +void m68k_op_add_16_re_pd(void); +void m68k_op_add_16_re_di(void); +void m68k_op_add_16_re_ix(void); +void m68k_op_add_16_re_aw(void); +void m68k_op_add_16_re_al(void); +void m68k_op_add_32_re_ai(void); +void m68k_op_add_32_re_pi(void); +void m68k_op_add_32_re_pd(void); +void m68k_op_add_32_re_di(void); +void m68k_op_add_32_re_ix(void); +void m68k_op_add_32_re_aw(void); +void m68k_op_add_32_re_al(void); +void m68k_op_adda_16_d(void); +void m68k_op_adda_16_a(void); +void m68k_op_adda_16_ai(void); +void m68k_op_adda_16_pi(void); +void m68k_op_adda_16_pd(void); +void m68k_op_adda_16_di(void); +void m68k_op_adda_16_ix(void); +void m68k_op_adda_16_aw(void); +void m68k_op_adda_16_al(void); +void m68k_op_adda_16_pcdi(void); +void m68k_op_adda_16_pcix(void); +void m68k_op_adda_16_i(void); +void m68k_op_adda_32_d(void); +void m68k_op_adda_32_a(void); +void m68k_op_adda_32_ai(void); +void m68k_op_adda_32_pi(void); +void m68k_op_adda_32_pd(void); +void m68k_op_adda_32_di(void); +void m68k_op_adda_32_ix(void); +void m68k_op_adda_32_aw(void); +void m68k_op_adda_32_al(void); +void m68k_op_adda_32_pcdi(void); +void m68k_op_adda_32_pcix(void); +void m68k_op_adda_32_i(void); +void m68k_op_addi_8_d(void); +void m68k_op_addi_8_ai(void); +void m68k_op_addi_8_pi(void); +void m68k_op_addi_8_pi7(void); +void m68k_op_addi_8_pd(void); +void m68k_op_addi_8_pd7(void); +void m68k_op_addi_8_di(void); +void m68k_op_addi_8_ix(void); +void m68k_op_addi_8_aw(void); +void m68k_op_addi_8_al(void); +void m68k_op_addi_16_d(void); +void m68k_op_addi_16_ai(void); +void m68k_op_addi_16_pi(void); +void m68k_op_addi_16_pd(void); +void m68k_op_addi_16_di(void); +void m68k_op_addi_16_ix(void); +void m68k_op_addi_16_aw(void); +void m68k_op_addi_16_al(void); +void m68k_op_addi_32_d(void); +void m68k_op_addi_32_ai(void); +void m68k_op_addi_32_pi(void); +void m68k_op_addi_32_pd(void); +void m68k_op_addi_32_di(void); +void m68k_op_addi_32_ix(void); +void m68k_op_addi_32_aw(void); +void m68k_op_addi_32_al(void); +void m68k_op_addq_8_d(void); +void m68k_op_addq_8_ai(void); +void m68k_op_addq_8_pi(void); +void m68k_op_addq_8_pi7(void); +void m68k_op_addq_8_pd(void); +void m68k_op_addq_8_pd7(void); +void m68k_op_addq_8_di(void); +void m68k_op_addq_8_ix(void); +void m68k_op_addq_8_aw(void); +void m68k_op_addq_8_al(void); +void m68k_op_addq_16_d(void); +void m68k_op_addq_16_a(void); +void m68k_op_addq_16_ai(void); +void m68k_op_addq_16_pi(void); +void m68k_op_addq_16_pd(void); +void m68k_op_addq_16_di(void); +void m68k_op_addq_16_ix(void); +void m68k_op_addq_16_aw(void); +void m68k_op_addq_16_al(void); +void m68k_op_addq_32_d(void); +void m68k_op_addq_32_a(void); +void m68k_op_addq_32_ai(void); +void m68k_op_addq_32_pi(void); +void m68k_op_addq_32_pd(void); +void m68k_op_addq_32_di(void); +void m68k_op_addq_32_ix(void); +void m68k_op_addq_32_aw(void); +void m68k_op_addq_32_al(void); +void m68k_op_addx_8_rr(void); +void m68k_op_addx_16_rr(void); +void m68k_op_addx_32_rr(void); +void m68k_op_addx_8_mm_ax7(void); +void m68k_op_addx_8_mm_ay7(void); +void m68k_op_addx_8_mm_axy7(void); +void m68k_op_addx_8_mm(void); +void m68k_op_addx_16_mm(void); +void m68k_op_addx_32_mm(void); +void m68k_op_and_8_er_d(void); +void m68k_op_and_8_er_ai(void); +void m68k_op_and_8_er_pi(void); +void m68k_op_and_8_er_pi7(void); +void m68k_op_and_8_er_pd(void); +void m68k_op_and_8_er_pd7(void); +void m68k_op_and_8_er_di(void); +void m68k_op_and_8_er_ix(void); +void m68k_op_and_8_er_aw(void); +void m68k_op_and_8_er_al(void); +void m68k_op_and_8_er_pcdi(void); +void m68k_op_and_8_er_pcix(void); +void m68k_op_and_8_er_i(void); +void m68k_op_and_16_er_d(void); +void m68k_op_and_16_er_ai(void); +void m68k_op_and_16_er_pi(void); +void m68k_op_and_16_er_pd(void); +void m68k_op_and_16_er_di(void); +void m68k_op_and_16_er_ix(void); +void m68k_op_and_16_er_aw(void); +void m68k_op_and_16_er_al(void); +void m68k_op_and_16_er_pcdi(void); +void m68k_op_and_16_er_pcix(void); +void m68k_op_and_16_er_i(void); +void m68k_op_and_32_er_d(void); +void m68k_op_and_32_er_ai(void); +void m68k_op_and_32_er_pi(void); +void m68k_op_and_32_er_pd(void); +void m68k_op_and_32_er_di(void); +void m68k_op_and_32_er_ix(void); +void m68k_op_and_32_er_aw(void); +void m68k_op_and_32_er_al(void); +void m68k_op_and_32_er_pcdi(void); +void m68k_op_and_32_er_pcix(void); +void m68k_op_and_32_er_i(void); +void m68k_op_and_8_re_ai(void); +void m68k_op_and_8_re_pi(void); +void m68k_op_and_8_re_pi7(void); +void m68k_op_and_8_re_pd(void); +void m68k_op_and_8_re_pd7(void); +void m68k_op_and_8_re_di(void); +void m68k_op_and_8_re_ix(void); +void m68k_op_and_8_re_aw(void); +void m68k_op_and_8_re_al(void); +void m68k_op_and_16_re_ai(void); +void m68k_op_and_16_re_pi(void); +void m68k_op_and_16_re_pd(void); +void m68k_op_and_16_re_di(void); +void m68k_op_and_16_re_ix(void); +void m68k_op_and_16_re_aw(void); +void m68k_op_and_16_re_al(void); +void m68k_op_and_32_re_ai(void); +void m68k_op_and_32_re_pi(void); +void m68k_op_and_32_re_pd(void); +void m68k_op_and_32_re_di(void); +void m68k_op_and_32_re_ix(void); +void m68k_op_and_32_re_aw(void); +void m68k_op_and_32_re_al(void); +void m68k_op_andi_8_d(void); +void m68k_op_andi_8_ai(void); +void m68k_op_andi_8_pi(void); +void m68k_op_andi_8_pi7(void); +void m68k_op_andi_8_pd(void); +void m68k_op_andi_8_pd7(void); +void m68k_op_andi_8_di(void); +void m68k_op_andi_8_ix(void); +void m68k_op_andi_8_aw(void); +void m68k_op_andi_8_al(void); +void m68k_op_andi_16_d(void); +void m68k_op_andi_16_ai(void); +void m68k_op_andi_16_pi(void); +void m68k_op_andi_16_pd(void); +void m68k_op_andi_16_di(void); +void m68k_op_andi_16_ix(void); +void m68k_op_andi_16_aw(void); +void m68k_op_andi_16_al(void); +void m68k_op_andi_32_d(void); +void m68k_op_andi_32_ai(void); +void m68k_op_andi_32_pi(void); +void m68k_op_andi_32_pd(void); +void m68k_op_andi_32_di(void); +void m68k_op_andi_32_ix(void); +void m68k_op_andi_32_aw(void); +void m68k_op_andi_32_al(void); +void m68k_op_andi_16_toc(void); +void m68k_op_andi_16_tos(void); +void m68k_op_asr_8_s(void); +void m68k_op_asr_16_s(void); +void m68k_op_asr_32_s(void); +void m68k_op_asr_8_r(void); +void m68k_op_asr_16_r(void); +void m68k_op_asr_32_r(void); +void m68k_op_asr_16_ai(void); +void m68k_op_asr_16_pi(void); +void m68k_op_asr_16_pd(void); +void m68k_op_asr_16_di(void); +void m68k_op_asr_16_ix(void); +void m68k_op_asr_16_aw(void); +void m68k_op_asr_16_al(void); +void m68k_op_asl_8_s(void); +void m68k_op_asl_16_s(void); +void m68k_op_asl_32_s(void); +void m68k_op_asl_8_r(void); +void m68k_op_asl_16_r(void); +void m68k_op_asl_32_r(void); +void m68k_op_asl_16_ai(void); +void m68k_op_asl_16_pi(void); +void m68k_op_asl_16_pd(void); +void m68k_op_asl_16_di(void); +void m68k_op_asl_16_ix(void); +void m68k_op_asl_16_aw(void); +void m68k_op_asl_16_al(void); +void m68k_op_bhi_8(void); +void m68k_op_bls_8(void); +void m68k_op_bcc_8(void); +void m68k_op_bcs_8(void); +void m68k_op_bne_8(void); +void m68k_op_beq_8(void); +void m68k_op_bvc_8(void); +void m68k_op_bvs_8(void); +void m68k_op_bpl_8(void); +void m68k_op_bmi_8(void); +void m68k_op_bge_8(void); +void m68k_op_blt_8(void); +void m68k_op_bgt_8(void); +void m68k_op_ble_8(void); +void m68k_op_bhi_16(void); +void m68k_op_bls_16(void); +void m68k_op_bcc_16(void); +void m68k_op_bcs_16(void); +void m68k_op_bne_16(void); +void m68k_op_beq_16(void); +void m68k_op_bvc_16(void); +void m68k_op_bvs_16(void); +void m68k_op_bpl_16(void); +void m68k_op_bmi_16(void); +void m68k_op_bge_16(void); +void m68k_op_blt_16(void); +void m68k_op_bgt_16(void); +void m68k_op_ble_16(void); +void m68k_op_bhi_32(void); +void m68k_op_bls_32(void); +void m68k_op_bcc_32(void); +void m68k_op_bcs_32(void); +void m68k_op_bne_32(void); +void m68k_op_beq_32(void); +void m68k_op_bvc_32(void); +void m68k_op_bvs_32(void); +void m68k_op_bpl_32(void); +void m68k_op_bmi_32(void); +void m68k_op_bge_32(void); +void m68k_op_blt_32(void); +void m68k_op_bgt_32(void); +void m68k_op_ble_32(void); +void m68k_op_bchg_32_r_d(void); +void m68k_op_bchg_8_r_ai(void); +void m68k_op_bchg_8_r_pi(void); +void m68k_op_bchg_8_r_pi7(void); +void m68k_op_bchg_8_r_pd(void); +void m68k_op_bchg_8_r_pd7(void); +void m68k_op_bchg_8_r_di(void); +void m68k_op_bchg_8_r_ix(void); +void m68k_op_bchg_8_r_aw(void); +void m68k_op_bchg_8_r_al(void); +void m68k_op_bchg_32_s_d(void); +void m68k_op_bchg_8_s_ai(void); +void m68k_op_bchg_8_s_pi(void); +void m68k_op_bchg_8_s_pi7(void); +void m68k_op_bchg_8_s_pd(void); +void m68k_op_bchg_8_s_pd7(void); +void m68k_op_bchg_8_s_di(void); +void m68k_op_bchg_8_s_ix(void); +void m68k_op_bchg_8_s_aw(void); +void m68k_op_bchg_8_s_al(void); +void m68k_op_bclr_32_r_d(void); +void m68k_op_bclr_8_r_ai(void); +void m68k_op_bclr_8_r_pi(void); +void m68k_op_bclr_8_r_pi7(void); +void m68k_op_bclr_8_r_pd(void); +void m68k_op_bclr_8_r_pd7(void); +void m68k_op_bclr_8_r_di(void); +void m68k_op_bclr_8_r_ix(void); +void m68k_op_bclr_8_r_aw(void); +void m68k_op_bclr_8_r_al(void); +void m68k_op_bclr_32_s_d(void); +void m68k_op_bclr_8_s_ai(void); +void m68k_op_bclr_8_s_pi(void); +void m68k_op_bclr_8_s_pi7(void); +void m68k_op_bclr_8_s_pd(void); +void m68k_op_bclr_8_s_pd7(void); +void m68k_op_bclr_8_s_di(void); +void m68k_op_bclr_8_s_ix(void); +void m68k_op_bclr_8_s_aw(void); +void m68k_op_bclr_8_s_al(void); +void m68k_op_bfchg_32_d(void); +void m68k_op_bfchg_32_ai(void); +void m68k_op_bfchg_32_di(void); +void m68k_op_bfchg_32_ix(void); +void m68k_op_bfchg_32_aw(void); +void m68k_op_bfchg_32_al(void); +void m68k_op_bfclr_32_d(void); +void m68k_op_bfclr_32_ai(void); +void m68k_op_bfclr_32_di(void); +void m68k_op_bfclr_32_ix(void); +void m68k_op_bfclr_32_aw(void); +void m68k_op_bfclr_32_al(void); +void m68k_op_bfexts_32_d(void); +void m68k_op_bfexts_32_ai(void); +void m68k_op_bfexts_32_di(void); +void m68k_op_bfexts_32_ix(void); +void m68k_op_bfexts_32_aw(void); +void m68k_op_bfexts_32_al(void); +void m68k_op_bfexts_32_pcdi(void); +void m68k_op_bfexts_32_pcix(void); +void m68k_op_bfextu_32_d(void); +void m68k_op_bfextu_32_ai(void); +void m68k_op_bfextu_32_di(void); +void m68k_op_bfextu_32_ix(void); +void m68k_op_bfextu_32_aw(void); +void m68k_op_bfextu_32_al(void); +void m68k_op_bfextu_32_pcdi(void); +void m68k_op_bfextu_32_pcix(void); +void m68k_op_bfffo_32_d(void); +void m68k_op_bfffo_32_ai(void); +void m68k_op_bfffo_32_di(void); +void m68k_op_bfffo_32_ix(void); +void m68k_op_bfffo_32_aw(void); +void m68k_op_bfffo_32_al(void); +void m68k_op_bfffo_32_pcdi(void); +void m68k_op_bfffo_32_pcix(void); +void m68k_op_bfins_32_d(void); +void m68k_op_bfins_32_ai(void); +void m68k_op_bfins_32_di(void); +void m68k_op_bfins_32_ix(void); +void m68k_op_bfins_32_aw(void); +void m68k_op_bfins_32_al(void); +void m68k_op_bfset_32_d(void); +void m68k_op_bfset_32_ai(void); +void m68k_op_bfset_32_di(void); +void m68k_op_bfset_32_ix(void); +void m68k_op_bfset_32_aw(void); +void m68k_op_bfset_32_al(void); +void m68k_op_bftst_32_d(void); +void m68k_op_bftst_32_ai(void); +void m68k_op_bftst_32_di(void); +void m68k_op_bftst_32_ix(void); +void m68k_op_bftst_32_aw(void); +void m68k_op_bftst_32_al(void); +void m68k_op_bftst_32_pcdi(void); +void m68k_op_bftst_32_pcix(void); +void m68k_op_bkpt(void); +void m68k_op_bra_8(void); +void m68k_op_bra_16(void); +void m68k_op_bra_32(void); +void m68k_op_bset_32_r_d(void); +void m68k_op_bset_8_r_ai(void); +void m68k_op_bset_8_r_pi(void); +void m68k_op_bset_8_r_pi7(void); +void m68k_op_bset_8_r_pd(void); +void m68k_op_bset_8_r_pd7(void); +void m68k_op_bset_8_r_di(void); +void m68k_op_bset_8_r_ix(void); +void m68k_op_bset_8_r_aw(void); +void m68k_op_bset_8_r_al(void); +void m68k_op_bset_32_s_d(void); +void m68k_op_bset_8_s_ai(void); +void m68k_op_bset_8_s_pi(void); +void m68k_op_bset_8_s_pi7(void); +void m68k_op_bset_8_s_pd(void); +void m68k_op_bset_8_s_pd7(void); +void m68k_op_bset_8_s_di(void); +void m68k_op_bset_8_s_ix(void); +void m68k_op_bset_8_s_aw(void); +void m68k_op_bset_8_s_al(void); +void m68k_op_bsr_8(void); +void m68k_op_bsr_16(void); +void m68k_op_bsr_32(void); +void m68k_op_btst_32_r_d(void); +void m68k_op_btst_8_r_ai(void); +void m68k_op_btst_8_r_pi(void); +void m68k_op_btst_8_r_pi7(void); +void m68k_op_btst_8_r_pd(void); +void m68k_op_btst_8_r_pd7(void); +void m68k_op_btst_8_r_di(void); +void m68k_op_btst_8_r_ix(void); +void m68k_op_btst_8_r_aw(void); +void m68k_op_btst_8_r_al(void); +void m68k_op_btst_8_r_pcdi(void); +void m68k_op_btst_8_r_pcix(void); +void m68k_op_btst_8_r_i(void); +void m68k_op_btst_32_s_d(void); +void m68k_op_btst_8_s_ai(void); +void m68k_op_btst_8_s_pi(void); +void m68k_op_btst_8_s_pi7(void); +void m68k_op_btst_8_s_pd(void); +void m68k_op_btst_8_s_pd7(void); +void m68k_op_btst_8_s_di(void); +void m68k_op_btst_8_s_ix(void); +void m68k_op_btst_8_s_aw(void); +void m68k_op_btst_8_s_al(void); +void m68k_op_btst_8_s_pcdi(void); +void m68k_op_btst_8_s_pcix(void); +void m68k_op_callm_32_ai(void); +void m68k_op_callm_32_di(void); +void m68k_op_callm_32_ix(void); +void m68k_op_callm_32_aw(void); +void m68k_op_callm_32_al(void); +void m68k_op_callm_32_pcdi(void); +void m68k_op_callm_32_pcix(void); +void m68k_op_cas_8_ai(void); +void m68k_op_cas_8_pi(void); +void m68k_op_cas_8_pi7(void); +void m68k_op_cas_8_pd(void); +void m68k_op_cas_8_pd7(void); +void m68k_op_cas_8_di(void); +void m68k_op_cas_8_ix(void); +void m68k_op_cas_8_aw(void); +void m68k_op_cas_8_al(void); +void m68k_op_cas_16_ai(void); +void m68k_op_cas_16_pi(void); +void m68k_op_cas_16_pd(void); +void m68k_op_cas_16_di(void); +void m68k_op_cas_16_ix(void); +void m68k_op_cas_16_aw(void); +void m68k_op_cas_16_al(void); +void m68k_op_cas_32_ai(void); +void m68k_op_cas_32_pi(void); +void m68k_op_cas_32_pd(void); +void m68k_op_cas_32_di(void); +void m68k_op_cas_32_ix(void); +void m68k_op_cas_32_aw(void); +void m68k_op_cas_32_al(void); +void m68k_op_cas2_16(void); +void m68k_op_cas2_32(void); +void m68k_op_chk_16_d(void); +void m68k_op_chk_16_ai(void); +void m68k_op_chk_16_pi(void); +void m68k_op_chk_16_pd(void); +void m68k_op_chk_16_di(void); +void m68k_op_chk_16_ix(void); +void m68k_op_chk_16_aw(void); +void m68k_op_chk_16_al(void); +void m68k_op_chk_16_pcdi(void); +void m68k_op_chk_16_pcix(void); +void m68k_op_chk_16_i(void); +void m68k_op_chk_32_d(void); +void m68k_op_chk_32_ai(void); +void m68k_op_chk_32_pi(void); +void m68k_op_chk_32_pd(void); +void m68k_op_chk_32_di(void); +void m68k_op_chk_32_ix(void); +void m68k_op_chk_32_aw(void); +void m68k_op_chk_32_al(void); +void m68k_op_chk_32_pcdi(void); +void m68k_op_chk_32_pcix(void); +void m68k_op_chk_32_i(void); +void m68k_op_chk2cmp2_8_pcdi(void); +void m68k_op_chk2cmp2_8_pcix(void); +void m68k_op_chk2cmp2_8_ai(void); +void m68k_op_chk2cmp2_8_di(void); +void m68k_op_chk2cmp2_8_ix(void); +void m68k_op_chk2cmp2_8_aw(void); +void m68k_op_chk2cmp2_8_al(void); +void m68k_op_chk2cmp2_16_pcdi(void); +void m68k_op_chk2cmp2_16_pcix(void); +void m68k_op_chk2cmp2_16_ai(void); +void m68k_op_chk2cmp2_16_di(void); +void m68k_op_chk2cmp2_16_ix(void); +void m68k_op_chk2cmp2_16_aw(void); +void m68k_op_chk2cmp2_16_al(void); +void m68k_op_chk2cmp2_32_pcdi(void); +void m68k_op_chk2cmp2_32_pcix(void); +void m68k_op_chk2cmp2_32_ai(void); +void m68k_op_chk2cmp2_32_di(void); +void m68k_op_chk2cmp2_32_ix(void); +void m68k_op_chk2cmp2_32_aw(void); +void m68k_op_chk2cmp2_32_al(void); +void m68k_op_clr_8_d(void); +void m68k_op_clr_8_ai(void); +void m68k_op_clr_8_pi(void); +void m68k_op_clr_8_pi7(void); +void m68k_op_clr_8_pd(void); +void m68k_op_clr_8_pd7(void); +void m68k_op_clr_8_di(void); +void m68k_op_clr_8_ix(void); +void m68k_op_clr_8_aw(void); +void m68k_op_clr_8_al(void); +void m68k_op_clr_16_d(void); +void m68k_op_clr_16_ai(void); +void m68k_op_clr_16_pi(void); +void m68k_op_clr_16_pd(void); +void m68k_op_clr_16_di(void); +void m68k_op_clr_16_ix(void); +void m68k_op_clr_16_aw(void); +void m68k_op_clr_16_al(void); +void m68k_op_clr_32_d(void); +void m68k_op_clr_32_ai(void); +void m68k_op_clr_32_pi(void); +void m68k_op_clr_32_pd(void); +void m68k_op_clr_32_di(void); +void m68k_op_clr_32_ix(void); +void m68k_op_clr_32_aw(void); +void m68k_op_clr_32_al(void); +void m68k_op_cmp_8_d(void); +void m68k_op_cmp_8_ai(void); +void m68k_op_cmp_8_pi(void); +void m68k_op_cmp_8_pi7(void); +void m68k_op_cmp_8_pd(void); +void m68k_op_cmp_8_pd7(void); +void m68k_op_cmp_8_di(void); +void m68k_op_cmp_8_ix(void); +void m68k_op_cmp_8_aw(void); +void m68k_op_cmp_8_al(void); +void m68k_op_cmp_8_pcdi(void); +void m68k_op_cmp_8_pcix(void); +void m68k_op_cmp_8_i(void); +void m68k_op_cmp_16_d(void); +void m68k_op_cmp_16_a(void); +void m68k_op_cmp_16_ai(void); +void m68k_op_cmp_16_pi(void); +void m68k_op_cmp_16_pd(void); +void m68k_op_cmp_16_di(void); +void m68k_op_cmp_16_ix(void); +void m68k_op_cmp_16_aw(void); +void m68k_op_cmp_16_al(void); +void m68k_op_cmp_16_pcdi(void); +void m68k_op_cmp_16_pcix(void); +void m68k_op_cmp_16_i(void); +void m68k_op_cmp_32_d(void); +void m68k_op_cmp_32_a(void); +void m68k_op_cmp_32_ai(void); +void m68k_op_cmp_32_pi(void); +void m68k_op_cmp_32_pd(void); +void m68k_op_cmp_32_di(void); +void m68k_op_cmp_32_ix(void); +void m68k_op_cmp_32_aw(void); +void m68k_op_cmp_32_al(void); +void m68k_op_cmp_32_pcdi(void); +void m68k_op_cmp_32_pcix(void); +void m68k_op_cmp_32_i(void); +void m68k_op_cmpa_16_d(void); +void m68k_op_cmpa_16_a(void); +void m68k_op_cmpa_16_ai(void); +void m68k_op_cmpa_16_pi(void); +void m68k_op_cmpa_16_pd(void); +void m68k_op_cmpa_16_di(void); +void m68k_op_cmpa_16_ix(void); +void m68k_op_cmpa_16_aw(void); +void m68k_op_cmpa_16_al(void); +void m68k_op_cmpa_16_pcdi(void); +void m68k_op_cmpa_16_pcix(void); +void m68k_op_cmpa_16_i(void); +void m68k_op_cmpa_32_d(void); +void m68k_op_cmpa_32_a(void); +void m68k_op_cmpa_32_ai(void); +void m68k_op_cmpa_32_pi(void); +void m68k_op_cmpa_32_pd(void); +void m68k_op_cmpa_32_di(void); +void m68k_op_cmpa_32_ix(void); +void m68k_op_cmpa_32_aw(void); +void m68k_op_cmpa_32_al(void); +void m68k_op_cmpa_32_pcdi(void); +void m68k_op_cmpa_32_pcix(void); +void m68k_op_cmpa_32_i(void); +void m68k_op_cmpi_8_d(void); +void m68k_op_cmpi_8_ai(void); +void m68k_op_cmpi_8_pi(void); +void m68k_op_cmpi_8_pi7(void); +void m68k_op_cmpi_8_pd(void); +void m68k_op_cmpi_8_pd7(void); +void m68k_op_cmpi_8_di(void); +void m68k_op_cmpi_8_ix(void); +void m68k_op_cmpi_8_aw(void); +void m68k_op_cmpi_8_al(void); +void m68k_op_cmpi_8_pcdi(void); +void m68k_op_cmpi_8_pcix(void); +void m68k_op_cmpi_16_d(void); +void m68k_op_cmpi_16_ai(void); +void m68k_op_cmpi_16_pi(void); +void m68k_op_cmpi_16_pd(void); +void m68k_op_cmpi_16_di(void); +void m68k_op_cmpi_16_ix(void); +void m68k_op_cmpi_16_aw(void); +void m68k_op_cmpi_16_al(void); +void m68k_op_cmpi_16_pcdi(void); +void m68k_op_cmpi_16_pcix(void); +void m68k_op_cmpi_32_d(void); +void m68k_op_cmpi_32_ai(void); +void m68k_op_cmpi_32_pi(void); +void m68k_op_cmpi_32_pd(void); +void m68k_op_cmpi_32_di(void); +void m68k_op_cmpi_32_ix(void); +void m68k_op_cmpi_32_aw(void); +void m68k_op_cmpi_32_al(void); +void m68k_op_cmpi_32_pcdi(void); +void m68k_op_cmpi_32_pcix(void); +void m68k_op_cmpm_8_ax7(void); +void m68k_op_cmpm_8_ay7(void); +void m68k_op_cmpm_8_axy7(void); +void m68k_op_cmpm_8(void); +void m68k_op_cmpm_16(void); +void m68k_op_cmpm_32(void); +void m68k_op_cpbcc_32(void); +void m68k_op_cpdbcc_32(void); +void m68k_op_cpgen_32(void); +void m68k_op_cpscc_32(void); +void m68k_op_cptrapcc_32(void); +void m68k_op_dbt_16(void); +void m68k_op_dbf_16(void); +void m68k_op_dbhi_16(void); +void m68k_op_dbls_16(void); +void m68k_op_dbcc_16(void); +void m68k_op_dbcs_16(void); +void m68k_op_dbne_16(void); +void m68k_op_dbeq_16(void); +void m68k_op_dbvc_16(void); +void m68k_op_dbvs_16(void); +void m68k_op_dbpl_16(void); +void m68k_op_dbmi_16(void); +void m68k_op_dbge_16(void); +void m68k_op_dblt_16(void); +void m68k_op_dbgt_16(void); +void m68k_op_dble_16(void); +void m68k_op_divs_16_d(void); +void m68k_op_divs_16_ai(void); +void m68k_op_divs_16_pi(void); +void m68k_op_divs_16_pd(void); +void m68k_op_divs_16_di(void); +void m68k_op_divs_16_ix(void); +void m68k_op_divs_16_aw(void); +void m68k_op_divs_16_al(void); +void m68k_op_divs_16_pcdi(void); +void m68k_op_divs_16_pcix(void); +void m68k_op_divs_16_i(void); +void m68k_op_divu_16_d(void); +void m68k_op_divu_16_ai(void); +void m68k_op_divu_16_pi(void); +void m68k_op_divu_16_pd(void); +void m68k_op_divu_16_di(void); +void m68k_op_divu_16_ix(void); +void m68k_op_divu_16_aw(void); +void m68k_op_divu_16_al(void); +void m68k_op_divu_16_pcdi(void); +void m68k_op_divu_16_pcix(void); +void m68k_op_divu_16_i(void); +void m68k_op_divl_32_d(void); +void m68k_op_divl_32_ai(void); +void m68k_op_divl_32_pi(void); +void m68k_op_divl_32_pd(void); +void m68k_op_divl_32_di(void); +void m68k_op_divl_32_ix(void); +void m68k_op_divl_32_aw(void); +void m68k_op_divl_32_al(void); +void m68k_op_divl_32_pcdi(void); +void m68k_op_divl_32_pcix(void); +void m68k_op_divl_32_i(void); +void m68k_op_eor_8_d(void); +void m68k_op_eor_8_ai(void); +void m68k_op_eor_8_pi(void); +void m68k_op_eor_8_pi7(void); +void m68k_op_eor_8_pd(void); +void m68k_op_eor_8_pd7(void); +void m68k_op_eor_8_di(void); +void m68k_op_eor_8_ix(void); +void m68k_op_eor_8_aw(void); +void m68k_op_eor_8_al(void); +void m68k_op_eor_16_d(void); +void m68k_op_eor_16_ai(void); +void m68k_op_eor_16_pi(void); +void m68k_op_eor_16_pd(void); +void m68k_op_eor_16_di(void); +void m68k_op_eor_16_ix(void); +void m68k_op_eor_16_aw(void); +void m68k_op_eor_16_al(void); +void m68k_op_eor_32_d(void); +void m68k_op_eor_32_ai(void); +void m68k_op_eor_32_pi(void); +void m68k_op_eor_32_pd(void); +void m68k_op_eor_32_di(void); +void m68k_op_eor_32_ix(void); +void m68k_op_eor_32_aw(void); +void m68k_op_eor_32_al(void); +void m68k_op_eori_8_d(void); +void m68k_op_eori_8_ai(void); +void m68k_op_eori_8_pi(void); +void m68k_op_eori_8_pi7(void); +void m68k_op_eori_8_pd(void); +void m68k_op_eori_8_pd7(void); +void m68k_op_eori_8_di(void); +void m68k_op_eori_8_ix(void); +void m68k_op_eori_8_aw(void); +void m68k_op_eori_8_al(void); +void m68k_op_eori_16_d(void); +void m68k_op_eori_16_ai(void); +void m68k_op_eori_16_pi(void); +void m68k_op_eori_16_pd(void); +void m68k_op_eori_16_di(void); +void m68k_op_eori_16_ix(void); +void m68k_op_eori_16_aw(void); +void m68k_op_eori_16_al(void); +void m68k_op_eori_32_d(void); +void m68k_op_eori_32_ai(void); +void m68k_op_eori_32_pi(void); +void m68k_op_eori_32_pd(void); +void m68k_op_eori_32_di(void); +void m68k_op_eori_32_ix(void); +void m68k_op_eori_32_aw(void); +void m68k_op_eori_32_al(void); +void m68k_op_eori_16_toc(void); +void m68k_op_eori_16_tos(void); +void m68k_op_exg_32_dd(void); +void m68k_op_exg_32_aa(void); +void m68k_op_exg_32_da(void); +void m68k_op_ext_16(void); +void m68k_op_ext_32(void); +void m68k_op_extb_32(void); +void m68k_op_illegal(void); +void m68k_op_jmp_32_ai(void); +void m68k_op_jmp_32_di(void); +void m68k_op_jmp_32_ix(void); +void m68k_op_jmp_32_aw(void); +void m68k_op_jmp_32_al(void); +void m68k_op_jmp_32_pcdi(void); +void m68k_op_jmp_32_pcix(void); +void m68k_op_jsr_32_ai(void); +void m68k_op_jsr_32_di(void); +void m68k_op_jsr_32_ix(void); +void m68k_op_jsr_32_aw(void); +void m68k_op_jsr_32_al(void); +void m68k_op_jsr_32_pcdi(void); +void m68k_op_jsr_32_pcix(void); +void m68k_op_lea_32_ai(void); +void m68k_op_lea_32_di(void); +void m68k_op_lea_32_ix(void); +void m68k_op_lea_32_aw(void); +void m68k_op_lea_32_al(void); +void m68k_op_lea_32_pcdi(void); +void m68k_op_lea_32_pcix(void); +void m68k_op_link_16_a7(void); +void m68k_op_link_16(void); +void m68k_op_link_32_a7(void); +void m68k_op_link_32(void); +void m68k_op_lsr_8_s(void); +void m68k_op_lsr_16_s(void); +void m68k_op_lsr_32_s(void); +void m68k_op_lsr_8_r(void); +void m68k_op_lsr_16_r(void); +void m68k_op_lsr_32_r(void); +void m68k_op_lsr_16_ai(void); +void m68k_op_lsr_16_pi(void); +void m68k_op_lsr_16_pd(void); +void m68k_op_lsr_16_di(void); +void m68k_op_lsr_16_ix(void); +void m68k_op_lsr_16_aw(void); +void m68k_op_lsr_16_al(void); +void m68k_op_lsl_8_s(void); +void m68k_op_lsl_16_s(void); +void m68k_op_lsl_32_s(void); +void m68k_op_lsl_8_r(void); +void m68k_op_lsl_16_r(void); +void m68k_op_lsl_32_r(void); +void m68k_op_lsl_16_ai(void); +void m68k_op_lsl_16_pi(void); +void m68k_op_lsl_16_pd(void); +void m68k_op_lsl_16_di(void); +void m68k_op_lsl_16_ix(void); +void m68k_op_lsl_16_aw(void); +void m68k_op_lsl_16_al(void); +void m68k_op_move_8_d_d(void); +void m68k_op_move_8_d_ai(void); +void m68k_op_move_8_d_pi(void); +void m68k_op_move_8_d_pi7(void); +void m68k_op_move_8_d_pd(void); +void m68k_op_move_8_d_pd7(void); +void m68k_op_move_8_d_di(void); +void m68k_op_move_8_d_ix(void); +void m68k_op_move_8_d_aw(void); +void m68k_op_move_8_d_al(void); +void m68k_op_move_8_d_pcdi(void); +void m68k_op_move_8_d_pcix(void); +void m68k_op_move_8_d_i(void); +void m68k_op_move_8_ai_d(void); +void m68k_op_move_8_ai_ai(void); +void m68k_op_move_8_ai_pi(void); +void m68k_op_move_8_ai_pi7(void); +void m68k_op_move_8_ai_pd(void); +void m68k_op_move_8_ai_pd7(void); +void m68k_op_move_8_ai_di(void); +void m68k_op_move_8_ai_ix(void); +void m68k_op_move_8_ai_aw(void); +void m68k_op_move_8_ai_al(void); +void m68k_op_move_8_ai_pcdi(void); +void m68k_op_move_8_ai_pcix(void); +void m68k_op_move_8_ai_i(void); +void m68k_op_move_8_pi7_d(void); +void m68k_op_move_8_pi_d(void); +void m68k_op_move_8_pi7_ai(void); +void m68k_op_move_8_pi7_pi(void); +void m68k_op_move_8_pi7_pi7(void); +void m68k_op_move_8_pi7_pd(void); +void m68k_op_move_8_pi7_pd7(void); +void m68k_op_move_8_pi7_di(void); +void m68k_op_move_8_pi7_ix(void); +void m68k_op_move_8_pi7_aw(void); +void m68k_op_move_8_pi7_al(void); +void m68k_op_move_8_pi7_pcdi(void); +void m68k_op_move_8_pi7_pcix(void); +void m68k_op_move_8_pi7_i(void); +void m68k_op_move_8_pi_ai(void); +void m68k_op_move_8_pi_pi(void); +void m68k_op_move_8_pi_pi7(void); +void m68k_op_move_8_pi_pd(void); +void m68k_op_move_8_pi_pd7(void); +void m68k_op_move_8_pi_di(void); +void m68k_op_move_8_pi_ix(void); +void m68k_op_move_8_pi_aw(void); +void m68k_op_move_8_pi_al(void); +void m68k_op_move_8_pi_pcdi(void); +void m68k_op_move_8_pi_pcix(void); +void m68k_op_move_8_pi_i(void); +void m68k_op_move_8_pd7_d(void); +void m68k_op_move_8_pd_d(void); +void m68k_op_move_8_pd7_ai(void); +void m68k_op_move_8_pd7_pi(void); +void m68k_op_move_8_pd7_pi7(void); +void m68k_op_move_8_pd7_pd(void); +void m68k_op_move_8_pd7_pd7(void); +void m68k_op_move_8_pd7_di(void); +void m68k_op_move_8_pd7_ix(void); +void m68k_op_move_8_pd7_aw(void); +void m68k_op_move_8_pd7_al(void); +void m68k_op_move_8_pd7_pcdi(void); +void m68k_op_move_8_pd7_pcix(void); +void m68k_op_move_8_pd7_i(void); +void m68k_op_move_8_pd_ai(void); +void m68k_op_move_8_pd_pi(void); +void m68k_op_move_8_pd_pi7(void); +void m68k_op_move_8_pd_pd(void); +void m68k_op_move_8_pd_pd7(void); +void m68k_op_move_8_pd_di(void); +void m68k_op_move_8_pd_ix(void); +void m68k_op_move_8_pd_aw(void); +void m68k_op_move_8_pd_al(void); +void m68k_op_move_8_pd_pcdi(void); +void m68k_op_move_8_pd_pcix(void); +void m68k_op_move_8_pd_i(void); +void m68k_op_move_8_di_d(void); +void m68k_op_move_8_di_ai(void); +void m68k_op_move_8_di_pi(void); +void m68k_op_move_8_di_pi7(void); +void m68k_op_move_8_di_pd(void); +void m68k_op_move_8_di_pd7(void); +void m68k_op_move_8_di_di(void); +void m68k_op_move_8_di_ix(void); +void m68k_op_move_8_di_aw(void); +void m68k_op_move_8_di_al(void); +void m68k_op_move_8_di_pcdi(void); +void m68k_op_move_8_di_pcix(void); +void m68k_op_move_8_di_i(void); +void m68k_op_move_8_ix_d(void); +void m68k_op_move_8_ix_ai(void); +void m68k_op_move_8_ix_pi(void); +void m68k_op_move_8_ix_pi7(void); +void m68k_op_move_8_ix_pd(void); +void m68k_op_move_8_ix_pd7(void); +void m68k_op_move_8_ix_di(void); +void m68k_op_move_8_ix_ix(void); +void m68k_op_move_8_ix_aw(void); +void m68k_op_move_8_ix_al(void); +void m68k_op_move_8_ix_pcdi(void); +void m68k_op_move_8_ix_pcix(void); +void m68k_op_move_8_ix_i(void); +void m68k_op_move_8_aw_d(void); +void m68k_op_move_8_aw_ai(void); +void m68k_op_move_8_aw_pi(void); +void m68k_op_move_8_aw_pi7(void); +void m68k_op_move_8_aw_pd(void); +void m68k_op_move_8_aw_pd7(void); +void m68k_op_move_8_aw_di(void); +void m68k_op_move_8_aw_ix(void); +void m68k_op_move_8_aw_aw(void); +void m68k_op_move_8_aw_al(void); +void m68k_op_move_8_aw_pcdi(void); +void m68k_op_move_8_aw_pcix(void); +void m68k_op_move_8_aw_i(void); +void m68k_op_move_8_al_d(void); +void m68k_op_move_8_al_ai(void); +void m68k_op_move_8_al_pi(void); +void m68k_op_move_8_al_pi7(void); +void m68k_op_move_8_al_pd(void); +void m68k_op_move_8_al_pd7(void); +void m68k_op_move_8_al_di(void); +void m68k_op_move_8_al_ix(void); +void m68k_op_move_8_al_aw(void); +void m68k_op_move_8_al_al(void); +void m68k_op_move_8_al_pcdi(void); +void m68k_op_move_8_al_pcix(void); +void m68k_op_move_8_al_i(void); +void m68k_op_move_16_d_d(void); +void m68k_op_move_16_d_a(void); +void m68k_op_move_16_d_ai(void); +void m68k_op_move_16_d_pi(void); +void m68k_op_move_16_d_pd(void); +void m68k_op_move_16_d_di(void); +void m68k_op_move_16_d_ix(void); +void m68k_op_move_16_d_aw(void); +void m68k_op_move_16_d_al(void); +void m68k_op_move_16_d_pcdi(void); +void m68k_op_move_16_d_pcix(void); +void m68k_op_move_16_d_i(void); +void m68k_op_move_16_ai_d(void); +void m68k_op_move_16_ai_a(void); +void m68k_op_move_16_ai_ai(void); +void m68k_op_move_16_ai_pi(void); +void m68k_op_move_16_ai_pd(void); +void m68k_op_move_16_ai_di(void); +void m68k_op_move_16_ai_ix(void); +void m68k_op_move_16_ai_aw(void); +void m68k_op_move_16_ai_al(void); +void m68k_op_move_16_ai_pcdi(void); +void m68k_op_move_16_ai_pcix(void); +void m68k_op_move_16_ai_i(void); +void m68k_op_move_16_pi_d(void); +void m68k_op_move_16_pi_a(void); +void m68k_op_move_16_pi_ai(void); +void m68k_op_move_16_pi_pi(void); +void m68k_op_move_16_pi_pd(void); +void m68k_op_move_16_pi_di(void); +void m68k_op_move_16_pi_ix(void); +void m68k_op_move_16_pi_aw(void); +void m68k_op_move_16_pi_al(void); +void m68k_op_move_16_pi_pcdi(void); +void m68k_op_move_16_pi_pcix(void); +void m68k_op_move_16_pi_i(void); +void m68k_op_move_16_pd_d(void); +void m68k_op_move_16_pd_a(void); +void m68k_op_move_16_pd_ai(void); +void m68k_op_move_16_pd_pi(void); +void m68k_op_move_16_pd_pd(void); +void m68k_op_move_16_pd_di(void); +void m68k_op_move_16_pd_ix(void); +void m68k_op_move_16_pd_aw(void); +void m68k_op_move_16_pd_al(void); +void m68k_op_move_16_pd_pcdi(void); +void m68k_op_move_16_pd_pcix(void); +void m68k_op_move_16_pd_i(void); +void m68k_op_move_16_di_d(void); +void m68k_op_move_16_di_a(void); +void m68k_op_move_16_di_ai(void); +void m68k_op_move_16_di_pi(void); +void m68k_op_move_16_di_pd(void); +void m68k_op_move_16_di_di(void); +void m68k_op_move_16_di_ix(void); +void m68k_op_move_16_di_aw(void); +void m68k_op_move_16_di_al(void); +void m68k_op_move_16_di_pcdi(void); +void m68k_op_move_16_di_pcix(void); +void m68k_op_move_16_di_i(void); +void m68k_op_move_16_ix_d(void); +void m68k_op_move_16_ix_a(void); +void m68k_op_move_16_ix_ai(void); +void m68k_op_move_16_ix_pi(void); +void m68k_op_move_16_ix_pd(void); +void m68k_op_move_16_ix_di(void); +void m68k_op_move_16_ix_ix(void); +void m68k_op_move_16_ix_aw(void); +void m68k_op_move_16_ix_al(void); +void m68k_op_move_16_ix_pcdi(void); +void m68k_op_move_16_ix_pcix(void); +void m68k_op_move_16_ix_i(void); +void m68k_op_move_16_aw_d(void); +void m68k_op_move_16_aw_a(void); +void m68k_op_move_16_aw_ai(void); +void m68k_op_move_16_aw_pi(void); +void m68k_op_move_16_aw_pd(void); +void m68k_op_move_16_aw_di(void); +void m68k_op_move_16_aw_ix(void); +void m68k_op_move_16_aw_aw(void); +void m68k_op_move_16_aw_al(void); +void m68k_op_move_16_aw_pcdi(void); +void m68k_op_move_16_aw_pcix(void); +void m68k_op_move_16_aw_i(void); +void m68k_op_move_16_al_d(void); +void m68k_op_move_16_al_a(void); +void m68k_op_move_16_al_ai(void); +void m68k_op_move_16_al_pi(void); +void m68k_op_move_16_al_pd(void); +void m68k_op_move_16_al_di(void); +void m68k_op_move_16_al_ix(void); +void m68k_op_move_16_al_aw(void); +void m68k_op_move_16_al_al(void); +void m68k_op_move_16_al_pcdi(void); +void m68k_op_move_16_al_pcix(void); +void m68k_op_move_16_al_i(void); +void m68k_op_move_32_d_d(void); +void m68k_op_move_32_d_a(void); +void m68k_op_move_32_d_ai(void); +void m68k_op_move_32_d_pi(void); +void m68k_op_move_32_d_pd(void); +void m68k_op_move_32_d_di(void); +void m68k_op_move_32_d_ix(void); +void m68k_op_move_32_d_aw(void); +void m68k_op_move_32_d_al(void); +void m68k_op_move_32_d_pcdi(void); +void m68k_op_move_32_d_pcix(void); +void m68k_op_move_32_d_i(void); +void m68k_op_move_32_ai_d(void); +void m68k_op_move_32_ai_a(void); +void m68k_op_move_32_ai_ai(void); +void m68k_op_move_32_ai_pi(void); +void m68k_op_move_32_ai_pd(void); +void m68k_op_move_32_ai_di(void); +void m68k_op_move_32_ai_ix(void); +void m68k_op_move_32_ai_aw(void); +void m68k_op_move_32_ai_al(void); +void m68k_op_move_32_ai_pcdi(void); +void m68k_op_move_32_ai_pcix(void); +void m68k_op_move_32_ai_i(void); +void m68k_op_move_32_pi_d(void); +void m68k_op_move_32_pi_a(void); +void m68k_op_move_32_pi_ai(void); +void m68k_op_move_32_pi_pi(void); +void m68k_op_move_32_pi_pd(void); +void m68k_op_move_32_pi_di(void); +void m68k_op_move_32_pi_ix(void); +void m68k_op_move_32_pi_aw(void); +void m68k_op_move_32_pi_al(void); +void m68k_op_move_32_pi_pcdi(void); +void m68k_op_move_32_pi_pcix(void); +void m68k_op_move_32_pi_i(void); +void m68k_op_move_32_pd_d(void); +void m68k_op_move_32_pd_a(void); +void m68k_op_move_32_pd_ai(void); +void m68k_op_move_32_pd_pi(void); +void m68k_op_move_32_pd_pd(void); +void m68k_op_move_32_pd_di(void); +void m68k_op_move_32_pd_ix(void); +void m68k_op_move_32_pd_aw(void); +void m68k_op_move_32_pd_al(void); +void m68k_op_move_32_pd_pcdi(void); +void m68k_op_move_32_pd_pcix(void); +void m68k_op_move_32_pd_i(void); +void m68k_op_move_32_di_d(void); +void m68k_op_move_32_di_a(void); +void m68k_op_move_32_di_ai(void); +void m68k_op_move_32_di_pi(void); +void m68k_op_move_32_di_pd(void); +void m68k_op_move_32_di_di(void); +void m68k_op_move_32_di_ix(void); +void m68k_op_move_32_di_aw(void); +void m68k_op_move_32_di_al(void); +void m68k_op_move_32_di_pcdi(void); +void m68k_op_move_32_di_pcix(void); +void m68k_op_move_32_di_i(void); +void m68k_op_move_32_ix_d(void); +void m68k_op_move_32_ix_a(void); +void m68k_op_move_32_ix_ai(void); +void m68k_op_move_32_ix_pi(void); +void m68k_op_move_32_ix_pd(void); +void m68k_op_move_32_ix_di(void); +void m68k_op_move_32_ix_ix(void); +void m68k_op_move_32_ix_aw(void); +void m68k_op_move_32_ix_al(void); +void m68k_op_move_32_ix_pcdi(void); +void m68k_op_move_32_ix_pcix(void); +void m68k_op_move_32_ix_i(void); +void m68k_op_move_32_aw_d(void); +void m68k_op_move_32_aw_a(void); +void m68k_op_move_32_aw_ai(void); +void m68k_op_move_32_aw_pi(void); +void m68k_op_move_32_aw_pd(void); +void m68k_op_move_32_aw_di(void); +void m68k_op_move_32_aw_ix(void); +void m68k_op_move_32_aw_aw(void); +void m68k_op_move_32_aw_al(void); +void m68k_op_move_32_aw_pcdi(void); +void m68k_op_move_32_aw_pcix(void); +void m68k_op_move_32_aw_i(void); +void m68k_op_move_32_al_d(void); +void m68k_op_move_32_al_a(void); +void m68k_op_move_32_al_ai(void); +void m68k_op_move_32_al_pi(void); +void m68k_op_move_32_al_pd(void); +void m68k_op_move_32_al_di(void); +void m68k_op_move_32_al_ix(void); +void m68k_op_move_32_al_aw(void); +void m68k_op_move_32_al_al(void); +void m68k_op_move_32_al_pcdi(void); +void m68k_op_move_32_al_pcix(void); +void m68k_op_move_32_al_i(void); +void m68k_op_movea_16_d(void); +void m68k_op_movea_16_a(void); +void m68k_op_movea_16_ai(void); +void m68k_op_movea_16_pi(void); +void m68k_op_movea_16_pd(void); +void m68k_op_movea_16_di(void); +void m68k_op_movea_16_ix(void); +void m68k_op_movea_16_aw(void); +void m68k_op_movea_16_al(void); +void m68k_op_movea_16_pcdi(void); +void m68k_op_movea_16_pcix(void); +void m68k_op_movea_16_i(void); +void m68k_op_movea_32_d(void); +void m68k_op_movea_32_a(void); +void m68k_op_movea_32_ai(void); +void m68k_op_movea_32_pi(void); +void m68k_op_movea_32_pd(void); +void m68k_op_movea_32_di(void); +void m68k_op_movea_32_ix(void); +void m68k_op_movea_32_aw(void); +void m68k_op_movea_32_al(void); +void m68k_op_movea_32_pcdi(void); +void m68k_op_movea_32_pcix(void); +void m68k_op_movea_32_i(void); +void m68k_op_move_16_frc_d(void); +void m68k_op_move_16_frc_ai(void); +void m68k_op_move_16_frc_pi(void); +void m68k_op_move_16_frc_pd(void); +void m68k_op_move_16_frc_di(void); +void m68k_op_move_16_frc_ix(void); +void m68k_op_move_16_frc_aw(void); +void m68k_op_move_16_frc_al(void); +void m68k_op_move_16_toc_d(void); +void m68k_op_move_16_toc_ai(void); +void m68k_op_move_16_toc_pi(void); +void m68k_op_move_16_toc_pd(void); +void m68k_op_move_16_toc_di(void); +void m68k_op_move_16_toc_ix(void); +void m68k_op_move_16_toc_aw(void); +void m68k_op_move_16_toc_al(void); +void m68k_op_move_16_toc_pcdi(void); +void m68k_op_move_16_toc_pcix(void); +void m68k_op_move_16_toc_i(void); +void m68k_op_move_16_frs_d(void); +void m68k_op_move_16_frs_ai(void); +void m68k_op_move_16_frs_pi(void); +void m68k_op_move_16_frs_pd(void); +void m68k_op_move_16_frs_di(void); +void m68k_op_move_16_frs_ix(void); +void m68k_op_move_16_frs_aw(void); +void m68k_op_move_16_frs_al(void); +void m68k_op_move_16_tos_d(void); +void m68k_op_move_16_tos_ai(void); +void m68k_op_move_16_tos_pi(void); +void m68k_op_move_16_tos_pd(void); +void m68k_op_move_16_tos_di(void); +void m68k_op_move_16_tos_ix(void); +void m68k_op_move_16_tos_aw(void); +void m68k_op_move_16_tos_al(void); +void m68k_op_move_16_tos_pcdi(void); +void m68k_op_move_16_tos_pcix(void); +void m68k_op_move_16_tos_i(void); +void m68k_op_move_32_fru(void); +void m68k_op_move_32_tou(void); +void m68k_op_movec_32_cr(void); +void m68k_op_movec_32_rc(void); +void m68k_op_movem_16_re_pd(void); +void m68k_op_movem_16_re_ai(void); +void m68k_op_movem_16_re_di(void); +void m68k_op_movem_16_re_ix(void); +void m68k_op_movem_16_re_aw(void); +void m68k_op_movem_16_re_al(void); +void m68k_op_movem_32_re_pd(void); +void m68k_op_movem_32_re_ai(void); +void m68k_op_movem_32_re_di(void); +void m68k_op_movem_32_re_ix(void); +void m68k_op_movem_32_re_aw(void); +void m68k_op_movem_32_re_al(void); +void m68k_op_movem_16_er_pi(void); +void m68k_op_movem_16_er_pcdi(void); +void m68k_op_movem_16_er_pcix(void); +void m68k_op_movem_16_er_ai(void); +void m68k_op_movem_16_er_di(void); +void m68k_op_movem_16_er_ix(void); +void m68k_op_movem_16_er_aw(void); +void m68k_op_movem_16_er_al(void); +void m68k_op_movem_32_er_pi(void); +void m68k_op_movem_32_er_pcdi(void); +void m68k_op_movem_32_er_pcix(void); +void m68k_op_movem_32_er_ai(void); +void m68k_op_movem_32_er_di(void); +void m68k_op_movem_32_er_ix(void); +void m68k_op_movem_32_er_aw(void); +void m68k_op_movem_32_er_al(void); +void m68k_op_movep_16_re(void); +void m68k_op_movep_32_re(void); +void m68k_op_movep_16_er(void); +void m68k_op_movep_32_er(void); +void m68k_op_moves_8_ai(void); +void m68k_op_moves_8_pi(void); +void m68k_op_moves_8_pi7(void); +void m68k_op_moves_8_pd(void); +void m68k_op_moves_8_pd7(void); +void m68k_op_moves_8_di(void); +void m68k_op_moves_8_ix(void); +void m68k_op_moves_8_aw(void); +void m68k_op_moves_8_al(void); +void m68k_op_moves_16_ai(void); +void m68k_op_moves_16_pi(void); +void m68k_op_moves_16_pd(void); +void m68k_op_moves_16_di(void); +void m68k_op_moves_16_ix(void); +void m68k_op_moves_16_aw(void); +void m68k_op_moves_16_al(void); +void m68k_op_moves_32_ai(void); +void m68k_op_moves_32_pi(void); +void m68k_op_moves_32_pd(void); +void m68k_op_moves_32_di(void); +void m68k_op_moves_32_ix(void); +void m68k_op_moves_32_aw(void); +void m68k_op_moves_32_al(void); +void m68k_op_moveq_32(void); +void m68k_op_muls_16_d(void); +void m68k_op_muls_16_ai(void); +void m68k_op_muls_16_pi(void); +void m68k_op_muls_16_pd(void); +void m68k_op_muls_16_di(void); +void m68k_op_muls_16_ix(void); +void m68k_op_muls_16_aw(void); +void m68k_op_muls_16_al(void); +void m68k_op_muls_16_pcdi(void); +void m68k_op_muls_16_pcix(void); +void m68k_op_muls_16_i(void); +void m68k_op_mulu_16_d(void); +void m68k_op_mulu_16_ai(void); +void m68k_op_mulu_16_pi(void); +void m68k_op_mulu_16_pd(void); +void m68k_op_mulu_16_di(void); +void m68k_op_mulu_16_ix(void); +void m68k_op_mulu_16_aw(void); +void m68k_op_mulu_16_al(void); +void m68k_op_mulu_16_pcdi(void); +void m68k_op_mulu_16_pcix(void); +void m68k_op_mulu_16_i(void); +void m68k_op_mull_32_d(void); +void m68k_op_mull_32_ai(void); +void m68k_op_mull_32_pi(void); +void m68k_op_mull_32_pd(void); +void m68k_op_mull_32_di(void); +void m68k_op_mull_32_ix(void); +void m68k_op_mull_32_aw(void); +void m68k_op_mull_32_al(void); +void m68k_op_mull_32_pcdi(void); +void m68k_op_mull_32_pcix(void); +void m68k_op_mull_32_i(void); +void m68k_op_nbcd_8_d(void); +void m68k_op_nbcd_8_ai(void); +void m68k_op_nbcd_8_pi(void); +void m68k_op_nbcd_8_pi7(void); +void m68k_op_nbcd_8_pd(void); +void m68k_op_nbcd_8_pd7(void); +void m68k_op_nbcd_8_di(void); +void m68k_op_nbcd_8_ix(void); +void m68k_op_nbcd_8_aw(void); +void m68k_op_nbcd_8_al(void); +void m68k_op_neg_8_d(void); +void m68k_op_neg_8_ai(void); +void m68k_op_neg_8_pi(void); +void m68k_op_neg_8_pi7(void); +void m68k_op_neg_8_pd(void); +void m68k_op_neg_8_pd7(void); +void m68k_op_neg_8_di(void); +void m68k_op_neg_8_ix(void); +void m68k_op_neg_8_aw(void); +void m68k_op_neg_8_al(void); +void m68k_op_neg_16_d(void); +void m68k_op_neg_16_ai(void); +void m68k_op_neg_16_pi(void); +void m68k_op_neg_16_pd(void); +void m68k_op_neg_16_di(void); +void m68k_op_neg_16_ix(void); +void m68k_op_neg_16_aw(void); +void m68k_op_neg_16_al(void); +void m68k_op_neg_32_d(void); +void m68k_op_neg_32_ai(void); +void m68k_op_neg_32_pi(void); +void m68k_op_neg_32_pd(void); +void m68k_op_neg_32_di(void); +void m68k_op_neg_32_ix(void); +void m68k_op_neg_32_aw(void); +void m68k_op_neg_32_al(void); +void m68k_op_negx_8_d(void); +void m68k_op_negx_8_ai(void); +void m68k_op_negx_8_pi(void); +void m68k_op_negx_8_pi7(void); +void m68k_op_negx_8_pd(void); +void m68k_op_negx_8_pd7(void); +void m68k_op_negx_8_di(void); +void m68k_op_negx_8_ix(void); +void m68k_op_negx_8_aw(void); +void m68k_op_negx_8_al(void); +void m68k_op_negx_16_d(void); +void m68k_op_negx_16_ai(void); +void m68k_op_negx_16_pi(void); +void m68k_op_negx_16_pd(void); +void m68k_op_negx_16_di(void); +void m68k_op_negx_16_ix(void); +void m68k_op_negx_16_aw(void); +void m68k_op_negx_16_al(void); +void m68k_op_negx_32_d(void); +void m68k_op_negx_32_ai(void); +void m68k_op_negx_32_pi(void); +void m68k_op_negx_32_pd(void); +void m68k_op_negx_32_di(void); +void m68k_op_negx_32_ix(void); +void m68k_op_negx_32_aw(void); +void m68k_op_negx_32_al(void); +void m68k_op_nop(void); +void m68k_op_not_8_d(void); +void m68k_op_not_8_ai(void); +void m68k_op_not_8_pi(void); +void m68k_op_not_8_pi7(void); +void m68k_op_not_8_pd(void); +void m68k_op_not_8_pd7(void); +void m68k_op_not_8_di(void); +void m68k_op_not_8_ix(void); +void m68k_op_not_8_aw(void); +void m68k_op_not_8_al(void); +void m68k_op_not_16_d(void); +void m68k_op_not_16_ai(void); +void m68k_op_not_16_pi(void); +void m68k_op_not_16_pd(void); +void m68k_op_not_16_di(void); +void m68k_op_not_16_ix(void); +void m68k_op_not_16_aw(void); +void m68k_op_not_16_al(void); +void m68k_op_not_32_d(void); +void m68k_op_not_32_ai(void); +void m68k_op_not_32_pi(void); +void m68k_op_not_32_pd(void); +void m68k_op_not_32_di(void); +void m68k_op_not_32_ix(void); +void m68k_op_not_32_aw(void); +void m68k_op_not_32_al(void); +void m68k_op_or_8_er_d(void); +void m68k_op_or_8_er_ai(void); +void m68k_op_or_8_er_pi(void); +void m68k_op_or_8_er_pi7(void); +void m68k_op_or_8_er_pd(void); +void m68k_op_or_8_er_pd7(void); +void m68k_op_or_8_er_di(void); +void m68k_op_or_8_er_ix(void); +void m68k_op_or_8_er_aw(void); +void m68k_op_or_8_er_al(void); +void m68k_op_or_8_er_pcdi(void); +void m68k_op_or_8_er_pcix(void); +void m68k_op_or_8_er_i(void); +void m68k_op_or_16_er_d(void); +void m68k_op_or_16_er_ai(void); +void m68k_op_or_16_er_pi(void); +void m68k_op_or_16_er_pd(void); +void m68k_op_or_16_er_di(void); +void m68k_op_or_16_er_ix(void); +void m68k_op_or_16_er_aw(void); +void m68k_op_or_16_er_al(void); +void m68k_op_or_16_er_pcdi(void); +void m68k_op_or_16_er_pcix(void); +void m68k_op_or_16_er_i(void); +void m68k_op_or_32_er_d(void); +void m68k_op_or_32_er_ai(void); +void m68k_op_or_32_er_pi(void); +void m68k_op_or_32_er_pd(void); +void m68k_op_or_32_er_di(void); +void m68k_op_or_32_er_ix(void); +void m68k_op_or_32_er_aw(void); +void m68k_op_or_32_er_al(void); +void m68k_op_or_32_er_pcdi(void); +void m68k_op_or_32_er_pcix(void); +void m68k_op_or_32_er_i(void); +void m68k_op_or_8_re_ai(void); +void m68k_op_or_8_re_pi(void); +void m68k_op_or_8_re_pi7(void); +void m68k_op_or_8_re_pd(void); +void m68k_op_or_8_re_pd7(void); +void m68k_op_or_8_re_di(void); +void m68k_op_or_8_re_ix(void); +void m68k_op_or_8_re_aw(void); +void m68k_op_or_8_re_al(void); +void m68k_op_or_16_re_ai(void); +void m68k_op_or_16_re_pi(void); +void m68k_op_or_16_re_pd(void); +void m68k_op_or_16_re_di(void); +void m68k_op_or_16_re_ix(void); +void m68k_op_or_16_re_aw(void); +void m68k_op_or_16_re_al(void); +void m68k_op_or_32_re_ai(void); +void m68k_op_or_32_re_pi(void); +void m68k_op_or_32_re_pd(void); +void m68k_op_or_32_re_di(void); +void m68k_op_or_32_re_ix(void); +void m68k_op_or_32_re_aw(void); +void m68k_op_or_32_re_al(void); +void m68k_op_ori_8_d(void); +void m68k_op_ori_8_ai(void); +void m68k_op_ori_8_pi(void); +void m68k_op_ori_8_pi7(void); +void m68k_op_ori_8_pd(void); +void m68k_op_ori_8_pd7(void); +void m68k_op_ori_8_di(void); +void m68k_op_ori_8_ix(void); +void m68k_op_ori_8_aw(void); +void m68k_op_ori_8_al(void); +void m68k_op_ori_16_d(void); +void m68k_op_ori_16_ai(void); +void m68k_op_ori_16_pi(void); +void m68k_op_ori_16_pd(void); +void m68k_op_ori_16_di(void); +void m68k_op_ori_16_ix(void); +void m68k_op_ori_16_aw(void); +void m68k_op_ori_16_al(void); +void m68k_op_ori_32_d(void); +void m68k_op_ori_32_ai(void); +void m68k_op_ori_32_pi(void); +void m68k_op_ori_32_pd(void); +void m68k_op_ori_32_di(void); +void m68k_op_ori_32_ix(void); +void m68k_op_ori_32_aw(void); +void m68k_op_ori_32_al(void); +void m68k_op_ori_16_toc(void); +void m68k_op_ori_16_tos(void); +void m68k_op_pack_16_rr(void); +void m68k_op_pack_16_mm_ax7(void); +void m68k_op_pack_16_mm_ay7(void); +void m68k_op_pack_16_mm_axy7(void); +void m68k_op_pack_16_mm(void); +void m68k_op_pea_32_ai(void); +void m68k_op_pea_32_di(void); +void m68k_op_pea_32_ix(void); +void m68k_op_pea_32_aw(void); +void m68k_op_pea_32_al(void); +void m68k_op_pea_32_pcdi(void); +void m68k_op_pea_32_pcix(void); +void m68k_op_reset(void); +void m68k_op_ror_8_s(void); +void m68k_op_ror_16_s(void); +void m68k_op_ror_32_s(void); +void m68k_op_ror_8_r(void); +void m68k_op_ror_16_r(void); +void m68k_op_ror_32_r(void); +void m68k_op_ror_16_ai(void); +void m68k_op_ror_16_pi(void); +void m68k_op_ror_16_pd(void); +void m68k_op_ror_16_di(void); +void m68k_op_ror_16_ix(void); +void m68k_op_ror_16_aw(void); +void m68k_op_ror_16_al(void); +void m68k_op_rol_8_s(void); +void m68k_op_rol_16_s(void); +void m68k_op_rol_32_s(void); +void m68k_op_rol_8_r(void); +void m68k_op_rol_16_r(void); +void m68k_op_rol_32_r(void); +void m68k_op_rol_16_ai(void); +void m68k_op_rol_16_pi(void); +void m68k_op_rol_16_pd(void); +void m68k_op_rol_16_di(void); +void m68k_op_rol_16_ix(void); +void m68k_op_rol_16_aw(void); +void m68k_op_rol_16_al(void); +void m68k_op_roxr_8_s(void); +void m68k_op_roxr_16_s(void); +void m68k_op_roxr_32_s(void); +void m68k_op_roxr_8_r(void); +void m68k_op_roxr_16_r(void); +void m68k_op_roxr_32_r(void); +void m68k_op_roxr_16_ai(void); +void m68k_op_roxr_16_pi(void); +void m68k_op_roxr_16_pd(void); +void m68k_op_roxr_16_di(void); +void m68k_op_roxr_16_ix(void); +void m68k_op_roxr_16_aw(void); +void m68k_op_roxr_16_al(void); +void m68k_op_roxl_8_s(void); +void m68k_op_roxl_16_s(void); +void m68k_op_roxl_32_s(void); +void m68k_op_roxl_8_r(void); +void m68k_op_roxl_16_r(void); +void m68k_op_roxl_32_r(void); +void m68k_op_roxl_16_ai(void); +void m68k_op_roxl_16_pi(void); +void m68k_op_roxl_16_pd(void); +void m68k_op_roxl_16_di(void); +void m68k_op_roxl_16_ix(void); +void m68k_op_roxl_16_aw(void); +void m68k_op_roxl_16_al(void); +void m68k_op_rtd_32(void); +void m68k_op_rte_32(void); +void m68k_op_rtm_32(void); +void m68k_op_rtr_32(void); +void m68k_op_rts_32(void); +void m68k_op_sbcd_8_rr(void); +void m68k_op_sbcd_8_mm_ax7(void); +void m68k_op_sbcd_8_mm_ay7(void); +void m68k_op_sbcd_8_mm_axy7(void); +void m68k_op_sbcd_8_mm(void); +void m68k_op_st_8_d(void); +void m68k_op_st_8_ai(void); +void m68k_op_st_8_pi(void); +void m68k_op_st_8_pi7(void); +void m68k_op_st_8_pd(void); +void m68k_op_st_8_pd7(void); +void m68k_op_st_8_di(void); +void m68k_op_st_8_ix(void); +void m68k_op_st_8_aw(void); +void m68k_op_st_8_al(void); +void m68k_op_sf_8_d(void); +void m68k_op_sf_8_ai(void); +void m68k_op_sf_8_pi(void); +void m68k_op_sf_8_pi7(void); +void m68k_op_sf_8_pd(void); +void m68k_op_sf_8_pd7(void); +void m68k_op_sf_8_di(void); +void m68k_op_sf_8_ix(void); +void m68k_op_sf_8_aw(void); +void m68k_op_sf_8_al(void); +void m68k_op_shi_8_d(void); +void m68k_op_sls_8_d(void); +void m68k_op_scc_8_d(void); +void m68k_op_scs_8_d(void); +void m68k_op_sne_8_d(void); +void m68k_op_seq_8_d(void); +void m68k_op_svc_8_d(void); +void m68k_op_svs_8_d(void); +void m68k_op_spl_8_d(void); +void m68k_op_smi_8_d(void); +void m68k_op_sge_8_d(void); +void m68k_op_slt_8_d(void); +void m68k_op_sgt_8_d(void); +void m68k_op_sle_8_d(void); +void m68k_op_shi_8_ai(void); +void m68k_op_shi_8_pi(void); +void m68k_op_shi_8_pi7(void); +void m68k_op_shi_8_pd(void); +void m68k_op_shi_8_pd7(void); +void m68k_op_shi_8_di(void); +void m68k_op_shi_8_ix(void); +void m68k_op_shi_8_aw(void); +void m68k_op_shi_8_al(void); +void m68k_op_sls_8_ai(void); +void m68k_op_sls_8_pi(void); +void m68k_op_sls_8_pi7(void); +void m68k_op_sls_8_pd(void); +void m68k_op_sls_8_pd7(void); +void m68k_op_sls_8_di(void); +void m68k_op_sls_8_ix(void); +void m68k_op_sls_8_aw(void); +void m68k_op_sls_8_al(void); +void m68k_op_scc_8_ai(void); +void m68k_op_scc_8_pi(void); +void m68k_op_scc_8_pi7(void); +void m68k_op_scc_8_pd(void); +void m68k_op_scc_8_pd7(void); +void m68k_op_scc_8_di(void); +void m68k_op_scc_8_ix(void); +void m68k_op_scc_8_aw(void); +void m68k_op_scc_8_al(void); +void m68k_op_scs_8_ai(void); +void m68k_op_scs_8_pi(void); +void m68k_op_scs_8_pi7(void); +void m68k_op_scs_8_pd(void); +void m68k_op_scs_8_pd7(void); +void m68k_op_scs_8_di(void); +void m68k_op_scs_8_ix(void); +void m68k_op_scs_8_aw(void); +void m68k_op_scs_8_al(void); +void m68k_op_sne_8_ai(void); +void m68k_op_sne_8_pi(void); +void m68k_op_sne_8_pi7(void); +void m68k_op_sne_8_pd(void); +void m68k_op_sne_8_pd7(void); +void m68k_op_sne_8_di(void); +void m68k_op_sne_8_ix(void); +void m68k_op_sne_8_aw(void); +void m68k_op_sne_8_al(void); +void m68k_op_seq_8_ai(void); +void m68k_op_seq_8_pi(void); +void m68k_op_seq_8_pi7(void); +void m68k_op_seq_8_pd(void); +void m68k_op_seq_8_pd7(void); +void m68k_op_seq_8_di(void); +void m68k_op_seq_8_ix(void); +void m68k_op_seq_8_aw(void); +void m68k_op_seq_8_al(void); +void m68k_op_svc_8_ai(void); +void m68k_op_svc_8_pi(void); +void m68k_op_svc_8_pi7(void); +void m68k_op_svc_8_pd(void); +void m68k_op_svc_8_pd7(void); +void m68k_op_svc_8_di(void); +void m68k_op_svc_8_ix(void); +void m68k_op_svc_8_aw(void); +void m68k_op_svc_8_al(void); +void m68k_op_svs_8_ai(void); +void m68k_op_svs_8_pi(void); +void m68k_op_svs_8_pi7(void); +void m68k_op_svs_8_pd(void); +void m68k_op_svs_8_pd7(void); +void m68k_op_svs_8_di(void); +void m68k_op_svs_8_ix(void); +void m68k_op_svs_8_aw(void); +void m68k_op_svs_8_al(void); +void m68k_op_spl_8_ai(void); +void m68k_op_spl_8_pi(void); +void m68k_op_spl_8_pi7(void); +void m68k_op_spl_8_pd(void); +void m68k_op_spl_8_pd7(void); +void m68k_op_spl_8_di(void); +void m68k_op_spl_8_ix(void); +void m68k_op_spl_8_aw(void); +void m68k_op_spl_8_al(void); +void m68k_op_smi_8_ai(void); +void m68k_op_smi_8_pi(void); +void m68k_op_smi_8_pi7(void); +void m68k_op_smi_8_pd(void); +void m68k_op_smi_8_pd7(void); +void m68k_op_smi_8_di(void); +void m68k_op_smi_8_ix(void); +void m68k_op_smi_8_aw(void); +void m68k_op_smi_8_al(void); +void m68k_op_sge_8_ai(void); +void m68k_op_sge_8_pi(void); +void m68k_op_sge_8_pi7(void); +void m68k_op_sge_8_pd(void); +void m68k_op_sge_8_pd7(void); +void m68k_op_sge_8_di(void); +void m68k_op_sge_8_ix(void); +void m68k_op_sge_8_aw(void); +void m68k_op_sge_8_al(void); +void m68k_op_slt_8_ai(void); +void m68k_op_slt_8_pi(void); +void m68k_op_slt_8_pi7(void); +void m68k_op_slt_8_pd(void); +void m68k_op_slt_8_pd7(void); +void m68k_op_slt_8_di(void); +void m68k_op_slt_8_ix(void); +void m68k_op_slt_8_aw(void); +void m68k_op_slt_8_al(void); +void m68k_op_sgt_8_ai(void); +void m68k_op_sgt_8_pi(void); +void m68k_op_sgt_8_pi7(void); +void m68k_op_sgt_8_pd(void); +void m68k_op_sgt_8_pd7(void); +void m68k_op_sgt_8_di(void); +void m68k_op_sgt_8_ix(void); +void m68k_op_sgt_8_aw(void); +void m68k_op_sgt_8_al(void); +void m68k_op_sle_8_ai(void); +void m68k_op_sle_8_pi(void); +void m68k_op_sle_8_pi7(void); +void m68k_op_sle_8_pd(void); +void m68k_op_sle_8_pd7(void); +void m68k_op_sle_8_di(void); +void m68k_op_sle_8_ix(void); +void m68k_op_sle_8_aw(void); +void m68k_op_sle_8_al(void); +void m68k_op_stop(void); +void m68k_op_sub_8_er_d(void); +void m68k_op_sub_8_er_ai(void); +void m68k_op_sub_8_er_pi(void); +void m68k_op_sub_8_er_pi7(void); +void m68k_op_sub_8_er_pd(void); +void m68k_op_sub_8_er_pd7(void); +void m68k_op_sub_8_er_di(void); +void m68k_op_sub_8_er_ix(void); +void m68k_op_sub_8_er_aw(void); +void m68k_op_sub_8_er_al(void); +void m68k_op_sub_8_er_pcdi(void); +void m68k_op_sub_8_er_pcix(void); +void m68k_op_sub_8_er_i(void); +void m68k_op_sub_16_er_d(void); +void m68k_op_sub_16_er_a(void); +void m68k_op_sub_16_er_ai(void); +void m68k_op_sub_16_er_pi(void); +void m68k_op_sub_16_er_pd(void); +void m68k_op_sub_16_er_di(void); +void m68k_op_sub_16_er_ix(void); +void m68k_op_sub_16_er_aw(void); +void m68k_op_sub_16_er_al(void); +void m68k_op_sub_16_er_pcdi(void); +void m68k_op_sub_16_er_pcix(void); +void m68k_op_sub_16_er_i(void); +void m68k_op_sub_32_er_d(void); +void m68k_op_sub_32_er_a(void); +void m68k_op_sub_32_er_ai(void); +void m68k_op_sub_32_er_pi(void); +void m68k_op_sub_32_er_pd(void); +void m68k_op_sub_32_er_di(void); +void m68k_op_sub_32_er_ix(void); +void m68k_op_sub_32_er_aw(void); +void m68k_op_sub_32_er_al(void); +void m68k_op_sub_32_er_pcdi(void); +void m68k_op_sub_32_er_pcix(void); +void m68k_op_sub_32_er_i(void); +void m68k_op_sub_8_re_ai(void); +void m68k_op_sub_8_re_pi(void); +void m68k_op_sub_8_re_pi7(void); +void m68k_op_sub_8_re_pd(void); +void m68k_op_sub_8_re_pd7(void); +void m68k_op_sub_8_re_di(void); +void m68k_op_sub_8_re_ix(void); +void m68k_op_sub_8_re_aw(void); +void m68k_op_sub_8_re_al(void); +void m68k_op_sub_16_re_ai(void); +void m68k_op_sub_16_re_pi(void); +void m68k_op_sub_16_re_pd(void); +void m68k_op_sub_16_re_di(void); +void m68k_op_sub_16_re_ix(void); +void m68k_op_sub_16_re_aw(void); +void m68k_op_sub_16_re_al(void); +void m68k_op_sub_32_re_ai(void); +void m68k_op_sub_32_re_pi(void); +void m68k_op_sub_32_re_pd(void); +void m68k_op_sub_32_re_di(void); +void m68k_op_sub_32_re_ix(void); +void m68k_op_sub_32_re_aw(void); +void m68k_op_sub_32_re_al(void); +void m68k_op_suba_16_d(void); +void m68k_op_suba_16_a(void); +void m68k_op_suba_16_ai(void); +void m68k_op_suba_16_pi(void); +void m68k_op_suba_16_pd(void); +void m68k_op_suba_16_di(void); +void m68k_op_suba_16_ix(void); +void m68k_op_suba_16_aw(void); +void m68k_op_suba_16_al(void); +void m68k_op_suba_16_pcdi(void); +void m68k_op_suba_16_pcix(void); +void m68k_op_suba_16_i(void); +void m68k_op_suba_32_d(void); +void m68k_op_suba_32_a(void); +void m68k_op_suba_32_ai(void); +void m68k_op_suba_32_pi(void); +void m68k_op_suba_32_pd(void); +void m68k_op_suba_32_di(void); +void m68k_op_suba_32_ix(void); +void m68k_op_suba_32_aw(void); +void m68k_op_suba_32_al(void); +void m68k_op_suba_32_pcdi(void); +void m68k_op_suba_32_pcix(void); +void m68k_op_suba_32_i(void); +void m68k_op_subi_8_d(void); +void m68k_op_subi_8_ai(void); +void m68k_op_subi_8_pi(void); +void m68k_op_subi_8_pi7(void); +void m68k_op_subi_8_pd(void); +void m68k_op_subi_8_pd7(void); +void m68k_op_subi_8_di(void); +void m68k_op_subi_8_ix(void); +void m68k_op_subi_8_aw(void); +void m68k_op_subi_8_al(void); +void m68k_op_subi_16_d(void); +void m68k_op_subi_16_ai(void); +void m68k_op_subi_16_pi(void); +void m68k_op_subi_16_pd(void); +void m68k_op_subi_16_di(void); +void m68k_op_subi_16_ix(void); +void m68k_op_subi_16_aw(void); +void m68k_op_subi_16_al(void); +void m68k_op_subi_32_d(void); +void m68k_op_subi_32_ai(void); +void m68k_op_subi_32_pi(void); +void m68k_op_subi_32_pd(void); +void m68k_op_subi_32_di(void); +void m68k_op_subi_32_ix(void); +void m68k_op_subi_32_aw(void); +void m68k_op_subi_32_al(void); +void m68k_op_subq_8_d(void); +void m68k_op_subq_8_ai(void); +void m68k_op_subq_8_pi(void); +void m68k_op_subq_8_pi7(void); +void m68k_op_subq_8_pd(void); +void m68k_op_subq_8_pd7(void); +void m68k_op_subq_8_di(void); +void m68k_op_subq_8_ix(void); +void m68k_op_subq_8_aw(void); +void m68k_op_subq_8_al(void); +void m68k_op_subq_16_d(void); +void m68k_op_subq_16_a(void); +void m68k_op_subq_16_ai(void); +void m68k_op_subq_16_pi(void); +void m68k_op_subq_16_pd(void); +void m68k_op_subq_16_di(void); +void m68k_op_subq_16_ix(void); +void m68k_op_subq_16_aw(void); +void m68k_op_subq_16_al(void); +void m68k_op_subq_32_d(void); +void m68k_op_subq_32_a(void); +void m68k_op_subq_32_ai(void); +void m68k_op_subq_32_pi(void); +void m68k_op_subq_32_pd(void); +void m68k_op_subq_32_di(void); +void m68k_op_subq_32_ix(void); +void m68k_op_subq_32_aw(void); +void m68k_op_subq_32_al(void); +void m68k_op_subx_8_rr(void); +void m68k_op_subx_16_rr(void); +void m68k_op_subx_32_rr(void); +void m68k_op_subx_8_mm_ax7(void); +void m68k_op_subx_8_mm_ay7(void); +void m68k_op_subx_8_mm_axy7(void); +void m68k_op_subx_8_mm(void); +void m68k_op_subx_16_mm(void); +void m68k_op_subx_32_mm(void); +void m68k_op_swap_32(void); +void m68k_op_tas_8_d(void); +void m68k_op_tas_8_ai(void); +void m68k_op_tas_8_pi(void); +void m68k_op_tas_8_pi7(void); +void m68k_op_tas_8_pd(void); +void m68k_op_tas_8_pd7(void); +void m68k_op_tas_8_di(void); +void m68k_op_tas_8_ix(void); +void m68k_op_tas_8_aw(void); +void m68k_op_tas_8_al(void); +void m68k_op_trap(void); +void m68k_op_trapt(void); +void m68k_op_trapt_16(void); +void m68k_op_trapt_32(void); +void m68k_op_trapf(void); +void m68k_op_trapf_16(void); +void m68k_op_trapf_32(void); +void m68k_op_traphi(void); +void m68k_op_trapls(void); +void m68k_op_trapcc(void); +void m68k_op_trapcs(void); +void m68k_op_trapne(void); +void m68k_op_trapeq(void); +void m68k_op_trapvc(void); +void m68k_op_trapvs(void); +void m68k_op_trappl(void); +void m68k_op_trapmi(void); +void m68k_op_trapge(void); +void m68k_op_traplt(void); +void m68k_op_trapgt(void); +void m68k_op_traple(void); +void m68k_op_traphi_16(void); +void m68k_op_trapls_16(void); +void m68k_op_trapcc_16(void); +void m68k_op_trapcs_16(void); +void m68k_op_trapne_16(void); +void m68k_op_trapeq_16(void); +void m68k_op_trapvc_16(void); +void m68k_op_trapvs_16(void); +void m68k_op_trappl_16(void); +void m68k_op_trapmi_16(void); +void m68k_op_trapge_16(void); +void m68k_op_traplt_16(void); +void m68k_op_trapgt_16(void); +void m68k_op_traple_16(void); +void m68k_op_traphi_32(void); +void m68k_op_trapls_32(void); +void m68k_op_trapcc_32(void); +void m68k_op_trapcs_32(void); +void m68k_op_trapne_32(void); +void m68k_op_trapeq_32(void); +void m68k_op_trapvc_32(void); +void m68k_op_trapvs_32(void); +void m68k_op_trappl_32(void); +void m68k_op_trapmi_32(void); +void m68k_op_trapge_32(void); +void m68k_op_traplt_32(void); +void m68k_op_trapgt_32(void); +void m68k_op_traple_32(void); +void m68k_op_trapv(void); +void m68k_op_tst_8_d(void); +void m68k_op_tst_8_ai(void); +void m68k_op_tst_8_pi(void); +void m68k_op_tst_8_pi7(void); +void m68k_op_tst_8_pd(void); +void m68k_op_tst_8_pd7(void); +void m68k_op_tst_8_di(void); +void m68k_op_tst_8_ix(void); +void m68k_op_tst_8_aw(void); +void m68k_op_tst_8_al(void); +void m68k_op_tst_8_pcdi(void); +void m68k_op_tst_8_pcix(void); +void m68k_op_tst_8_i(void); +void m68k_op_tst_16_d(void); +void m68k_op_tst_16_a(void); +void m68k_op_tst_16_ai(void); +void m68k_op_tst_16_pi(void); +void m68k_op_tst_16_pd(void); +void m68k_op_tst_16_di(void); +void m68k_op_tst_16_ix(void); +void m68k_op_tst_16_aw(void); +void m68k_op_tst_16_al(void); +void m68k_op_tst_16_pcdi(void); +void m68k_op_tst_16_pcix(void); +void m68k_op_tst_16_i(void); +void m68k_op_tst_32_d(void); +void m68k_op_tst_32_a(void); +void m68k_op_tst_32_ai(void); +void m68k_op_tst_32_pi(void); +void m68k_op_tst_32_pd(void); +void m68k_op_tst_32_di(void); +void m68k_op_tst_32_ix(void); +void m68k_op_tst_32_aw(void); +void m68k_op_tst_32_al(void); +void m68k_op_tst_32_pcdi(void); +void m68k_op_tst_32_pcix(void); +void m68k_op_tst_32_i(void); +void m68k_op_unlk_32_a7(void); +void m68k_op_unlk_32(void); +void m68k_op_unpk_16_rr(void); +void m68k_op_unpk_16_mm_ax7(void); +void m68k_op_unpk_16_mm_ay7(void); +void m68k_op_unpk_16_mm_axy7(void); +void m68k_op_unpk_16_mm(void); +/* Build the opcode handler table */ +void m68ki_build_opcode_table(void); + +typedef void (*m68ki_instruction_jump_call)(void); + +extern const m68ki_instruction_jump_call m68ki_instruction_jump_table[]; +//extern void (*m68ki_instruction_jump_table)(void); /* opcode handler jump table */ +//extern const unsigned char m68ki_cycles[1][0x10000]; +extern const unsigned char m68ki_cycles[1][0x10000]; + + +/* ======================================================================== */ +/* ============================== END OF FILE ============================= */ +/* ======================================================================== */ + +#endif /* M68KOPS__HEADER */ + + diff --git a/MCUME_teensy/teensygen/musashi34/m68kops_pre.c b/MCUME_teensy/teensygen/musashi34/m68kops_pre.c new file mode 100644 index 0000000..40bee10 --- /dev/null +++ b/MCUME_teensy/teensygen/musashi34/m68kops_pre.c @@ -0,0 +1,69644 @@ +#include "m68kops.h" + +//Opcodes are built on the host, this does not need to do anything. +void m68ki_build_opcode_table() {} +//#include + +/*PROGMEM*/ const m68ki_instruction_jump_call m68ki_instruction_jump_table[]={ + m68k_op_ori_8_d , + m68k_op_ori_8_d , + m68k_op_ori_8_d , + m68k_op_ori_8_d , + m68k_op_ori_8_d , + m68k_op_ori_8_d , + m68k_op_ori_8_d , + m68k_op_ori_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ori_8_ai , + m68k_op_ori_8_ai , + m68k_op_ori_8_ai , + m68k_op_ori_8_ai , + m68k_op_ori_8_ai , + m68k_op_ori_8_ai , + m68k_op_ori_8_ai , + m68k_op_ori_8_ai , + m68k_op_ori_8_pi , + m68k_op_ori_8_pi , + m68k_op_ori_8_pi , + m68k_op_ori_8_pi , + m68k_op_ori_8_pi , + m68k_op_ori_8_pi , + m68k_op_ori_8_pi , + m68k_op_ori_8_pi7 , + m68k_op_ori_8_pd , + m68k_op_ori_8_pd , + m68k_op_ori_8_pd , + m68k_op_ori_8_pd , + m68k_op_ori_8_pd , + m68k_op_ori_8_pd , + m68k_op_ori_8_pd , + m68k_op_ori_8_pd7 , + m68k_op_ori_8_di , + m68k_op_ori_8_di , + m68k_op_ori_8_di , + m68k_op_ori_8_di , + m68k_op_ori_8_di , + m68k_op_ori_8_di , + m68k_op_ori_8_di , + m68k_op_ori_8_di , + m68k_op_ori_8_ix , + m68k_op_ori_8_ix , + m68k_op_ori_8_ix , + m68k_op_ori_8_ix , + m68k_op_ori_8_ix , + m68k_op_ori_8_ix , + m68k_op_ori_8_ix , + m68k_op_ori_8_ix , + m68k_op_ori_8_aw , + m68k_op_ori_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ori_16_toc , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ori_16_d , + m68k_op_ori_16_d , + m68k_op_ori_16_d , + m68k_op_ori_16_d , + m68k_op_ori_16_d , + m68k_op_ori_16_d , + m68k_op_ori_16_d , + m68k_op_ori_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ori_16_ai , + m68k_op_ori_16_ai , + m68k_op_ori_16_ai , + m68k_op_ori_16_ai , + m68k_op_ori_16_ai , + m68k_op_ori_16_ai , + m68k_op_ori_16_ai , + m68k_op_ori_16_ai , + m68k_op_ori_16_pi , + m68k_op_ori_16_pi , + m68k_op_ori_16_pi , + m68k_op_ori_16_pi , + m68k_op_ori_16_pi , + m68k_op_ori_16_pi , + m68k_op_ori_16_pi , + m68k_op_ori_16_pi , + m68k_op_ori_16_pd , + m68k_op_ori_16_pd , + m68k_op_ori_16_pd , + m68k_op_ori_16_pd , + m68k_op_ori_16_pd , + m68k_op_ori_16_pd , + m68k_op_ori_16_pd , + m68k_op_ori_16_pd , + m68k_op_ori_16_di , + m68k_op_ori_16_di , + m68k_op_ori_16_di , + m68k_op_ori_16_di , + m68k_op_ori_16_di , + m68k_op_ori_16_di , + m68k_op_ori_16_di , + m68k_op_ori_16_di , + m68k_op_ori_16_ix , + m68k_op_ori_16_ix , + m68k_op_ori_16_ix , + m68k_op_ori_16_ix , + m68k_op_ori_16_ix , + m68k_op_ori_16_ix , + m68k_op_ori_16_ix , + m68k_op_ori_16_ix , + m68k_op_ori_16_aw , + m68k_op_ori_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ori_16_tos , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ori_32_d , + m68k_op_ori_32_d , + m68k_op_ori_32_d , + m68k_op_ori_32_d , + m68k_op_ori_32_d , + m68k_op_ori_32_d , + m68k_op_ori_32_d , + m68k_op_ori_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ori_32_ai , + m68k_op_ori_32_ai , + m68k_op_ori_32_ai , + m68k_op_ori_32_ai , + m68k_op_ori_32_ai , + m68k_op_ori_32_ai , + m68k_op_ori_32_ai , + m68k_op_ori_32_ai , + m68k_op_ori_32_pi , + m68k_op_ori_32_pi , + m68k_op_ori_32_pi , + m68k_op_ori_32_pi , + m68k_op_ori_32_pi , + m68k_op_ori_32_pi , + m68k_op_ori_32_pi , + m68k_op_ori_32_pi , + m68k_op_ori_32_pd , + m68k_op_ori_32_pd , + m68k_op_ori_32_pd , + m68k_op_ori_32_pd , + m68k_op_ori_32_pd , + m68k_op_ori_32_pd , + m68k_op_ori_32_pd , + m68k_op_ori_32_pd , + m68k_op_ori_32_di , + m68k_op_ori_32_di , + m68k_op_ori_32_di , + m68k_op_ori_32_di , + m68k_op_ori_32_di , + m68k_op_ori_32_di , + m68k_op_ori_32_di , + m68k_op_ori_32_di , + m68k_op_ori_32_ix , + m68k_op_ori_32_ix , + m68k_op_ori_32_ix , + m68k_op_ori_32_ix , + m68k_op_ori_32_ix , + m68k_op_ori_32_ix , + m68k_op_ori_32_ix , + m68k_op_ori_32_ix , + m68k_op_ori_32_aw , + m68k_op_ori_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk2cmp2_8_ai , + m68k_op_chk2cmp2_8_ai , + m68k_op_chk2cmp2_8_ai , + m68k_op_chk2cmp2_8_ai , + m68k_op_chk2cmp2_8_ai , + m68k_op_chk2cmp2_8_ai , + m68k_op_chk2cmp2_8_ai , + m68k_op_chk2cmp2_8_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk2cmp2_8_di , + m68k_op_chk2cmp2_8_di , + m68k_op_chk2cmp2_8_di , + m68k_op_chk2cmp2_8_di , + m68k_op_chk2cmp2_8_di , + m68k_op_chk2cmp2_8_di , + m68k_op_chk2cmp2_8_di , + m68k_op_chk2cmp2_8_di , + m68k_op_chk2cmp2_8_ix , + m68k_op_chk2cmp2_8_ix , + m68k_op_chk2cmp2_8_ix , + m68k_op_chk2cmp2_8_ix , + m68k_op_chk2cmp2_8_ix , + m68k_op_chk2cmp2_8_ix , + m68k_op_chk2cmp2_8_ix , + m68k_op_chk2cmp2_8_ix , + m68k_op_chk2cmp2_8_aw , + m68k_op_chk2cmp2_8_al , + m68k_op_chk2cmp2_8_pcdi , + m68k_op_chk2cmp2_8_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi7 , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd7 , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_aw , + m68k_op_btst_8_r_al , + m68k_op_btst_8_r_pcdi , + m68k_op_btst_8_r_pcix , + m68k_op_btst_8_r_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi7 , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd7 , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_aw , + m68k_op_bchg_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi7 , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd7 , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_aw , + m68k_op_bclr_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi7 , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd7 , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_aw , + m68k_op_bset_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_andi_8_d , + m68k_op_andi_8_d , + m68k_op_andi_8_d , + m68k_op_andi_8_d , + m68k_op_andi_8_d , + m68k_op_andi_8_d , + m68k_op_andi_8_d , + m68k_op_andi_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_andi_8_ai , + m68k_op_andi_8_ai , + m68k_op_andi_8_ai , + m68k_op_andi_8_ai , + m68k_op_andi_8_ai , + m68k_op_andi_8_ai , + m68k_op_andi_8_ai , + m68k_op_andi_8_ai , + m68k_op_andi_8_pi , + m68k_op_andi_8_pi , + m68k_op_andi_8_pi , + m68k_op_andi_8_pi , + m68k_op_andi_8_pi , + m68k_op_andi_8_pi , + m68k_op_andi_8_pi , + m68k_op_andi_8_pi7 , + m68k_op_andi_8_pd , + m68k_op_andi_8_pd , + m68k_op_andi_8_pd , + m68k_op_andi_8_pd , + m68k_op_andi_8_pd , + m68k_op_andi_8_pd , + m68k_op_andi_8_pd , + m68k_op_andi_8_pd7 , + m68k_op_andi_8_di , + m68k_op_andi_8_di , + m68k_op_andi_8_di , + m68k_op_andi_8_di , + m68k_op_andi_8_di , + m68k_op_andi_8_di , + m68k_op_andi_8_di , + m68k_op_andi_8_di , + m68k_op_andi_8_ix , + m68k_op_andi_8_ix , + m68k_op_andi_8_ix , + m68k_op_andi_8_ix , + m68k_op_andi_8_ix , + m68k_op_andi_8_ix , + m68k_op_andi_8_ix , + m68k_op_andi_8_ix , + m68k_op_andi_8_aw , + m68k_op_andi_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_andi_16_toc , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_andi_16_d , + m68k_op_andi_16_d , + m68k_op_andi_16_d , + m68k_op_andi_16_d , + m68k_op_andi_16_d , + m68k_op_andi_16_d , + m68k_op_andi_16_d , + m68k_op_andi_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_andi_16_ai , + m68k_op_andi_16_ai , + m68k_op_andi_16_ai , + m68k_op_andi_16_ai , + m68k_op_andi_16_ai , + m68k_op_andi_16_ai , + m68k_op_andi_16_ai , + m68k_op_andi_16_ai , + m68k_op_andi_16_pi , + m68k_op_andi_16_pi , + m68k_op_andi_16_pi , + m68k_op_andi_16_pi , + m68k_op_andi_16_pi , + m68k_op_andi_16_pi , + m68k_op_andi_16_pi , + m68k_op_andi_16_pi , + m68k_op_andi_16_pd , + m68k_op_andi_16_pd , + m68k_op_andi_16_pd , + m68k_op_andi_16_pd , + m68k_op_andi_16_pd , + m68k_op_andi_16_pd , + m68k_op_andi_16_pd , + m68k_op_andi_16_pd , + m68k_op_andi_16_di , + m68k_op_andi_16_di , + m68k_op_andi_16_di , + m68k_op_andi_16_di , + m68k_op_andi_16_di , + m68k_op_andi_16_di , + m68k_op_andi_16_di , + m68k_op_andi_16_di , + m68k_op_andi_16_ix , + m68k_op_andi_16_ix , + m68k_op_andi_16_ix , + m68k_op_andi_16_ix , + m68k_op_andi_16_ix , + m68k_op_andi_16_ix , + m68k_op_andi_16_ix , + m68k_op_andi_16_ix , + m68k_op_andi_16_aw , + m68k_op_andi_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_andi_16_tos , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_andi_32_d , + m68k_op_andi_32_d , + m68k_op_andi_32_d , + m68k_op_andi_32_d , + m68k_op_andi_32_d , + m68k_op_andi_32_d , + m68k_op_andi_32_d , + m68k_op_andi_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_andi_32_ai , + m68k_op_andi_32_ai , + m68k_op_andi_32_ai , + m68k_op_andi_32_ai , + m68k_op_andi_32_ai , + m68k_op_andi_32_ai , + m68k_op_andi_32_ai , + m68k_op_andi_32_ai , + m68k_op_andi_32_pi , + m68k_op_andi_32_pi , + m68k_op_andi_32_pi , + m68k_op_andi_32_pi , + m68k_op_andi_32_pi , + m68k_op_andi_32_pi , + m68k_op_andi_32_pi , + m68k_op_andi_32_pi , + m68k_op_andi_32_pd , + m68k_op_andi_32_pd , + m68k_op_andi_32_pd , + m68k_op_andi_32_pd , + m68k_op_andi_32_pd , + m68k_op_andi_32_pd , + m68k_op_andi_32_pd , + m68k_op_andi_32_pd , + m68k_op_andi_32_di , + m68k_op_andi_32_di , + m68k_op_andi_32_di , + m68k_op_andi_32_di , + m68k_op_andi_32_di , + m68k_op_andi_32_di , + m68k_op_andi_32_di , + m68k_op_andi_32_di , + m68k_op_andi_32_ix , + m68k_op_andi_32_ix , + m68k_op_andi_32_ix , + m68k_op_andi_32_ix , + m68k_op_andi_32_ix , + m68k_op_andi_32_ix , + m68k_op_andi_32_ix , + m68k_op_andi_32_ix , + m68k_op_andi_32_aw , + m68k_op_andi_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk2cmp2_16_ai , + m68k_op_chk2cmp2_16_ai , + m68k_op_chk2cmp2_16_ai , + m68k_op_chk2cmp2_16_ai , + m68k_op_chk2cmp2_16_ai , + m68k_op_chk2cmp2_16_ai , + m68k_op_chk2cmp2_16_ai , + m68k_op_chk2cmp2_16_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk2cmp2_16_di , + m68k_op_chk2cmp2_16_di , + m68k_op_chk2cmp2_16_di , + m68k_op_chk2cmp2_16_di , + m68k_op_chk2cmp2_16_di , + m68k_op_chk2cmp2_16_di , + m68k_op_chk2cmp2_16_di , + m68k_op_chk2cmp2_16_di , + m68k_op_chk2cmp2_16_ix , + m68k_op_chk2cmp2_16_ix , + m68k_op_chk2cmp2_16_ix , + m68k_op_chk2cmp2_16_ix , + m68k_op_chk2cmp2_16_ix , + m68k_op_chk2cmp2_16_ix , + m68k_op_chk2cmp2_16_ix , + m68k_op_chk2cmp2_16_ix , + m68k_op_chk2cmp2_16_aw , + m68k_op_chk2cmp2_16_al , + m68k_op_chk2cmp2_16_pcdi , + m68k_op_chk2cmp2_16_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi7 , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd7 , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_aw , + m68k_op_btst_8_r_al , + m68k_op_btst_8_r_pcdi , + m68k_op_btst_8_r_pcix , + m68k_op_btst_8_r_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi7 , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd7 , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_aw , + m68k_op_bchg_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi7 , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd7 , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_aw , + m68k_op_bclr_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi7 , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd7 , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_aw , + m68k_op_bset_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subi_8_d , + m68k_op_subi_8_d , + m68k_op_subi_8_d , + m68k_op_subi_8_d , + m68k_op_subi_8_d , + m68k_op_subi_8_d , + m68k_op_subi_8_d , + m68k_op_subi_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subi_8_ai , + m68k_op_subi_8_ai , + m68k_op_subi_8_ai , + m68k_op_subi_8_ai , + m68k_op_subi_8_ai , + m68k_op_subi_8_ai , + m68k_op_subi_8_ai , + m68k_op_subi_8_ai , + m68k_op_subi_8_pi , + m68k_op_subi_8_pi , + m68k_op_subi_8_pi , + m68k_op_subi_8_pi , + m68k_op_subi_8_pi , + m68k_op_subi_8_pi , + m68k_op_subi_8_pi , + m68k_op_subi_8_pi7 , + m68k_op_subi_8_pd , + m68k_op_subi_8_pd , + m68k_op_subi_8_pd , + m68k_op_subi_8_pd , + m68k_op_subi_8_pd , + m68k_op_subi_8_pd , + m68k_op_subi_8_pd , + m68k_op_subi_8_pd7 , + m68k_op_subi_8_di , + m68k_op_subi_8_di , + m68k_op_subi_8_di , + m68k_op_subi_8_di , + m68k_op_subi_8_di , + m68k_op_subi_8_di , + m68k_op_subi_8_di , + m68k_op_subi_8_di , + m68k_op_subi_8_ix , + m68k_op_subi_8_ix , + m68k_op_subi_8_ix , + m68k_op_subi_8_ix , + m68k_op_subi_8_ix , + m68k_op_subi_8_ix , + m68k_op_subi_8_ix , + m68k_op_subi_8_ix , + m68k_op_subi_8_aw , + m68k_op_subi_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subi_16_d , + m68k_op_subi_16_d , + m68k_op_subi_16_d , + m68k_op_subi_16_d , + m68k_op_subi_16_d , + m68k_op_subi_16_d , + m68k_op_subi_16_d , + m68k_op_subi_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subi_16_ai , + m68k_op_subi_16_ai , + m68k_op_subi_16_ai , + m68k_op_subi_16_ai , + m68k_op_subi_16_ai , + m68k_op_subi_16_ai , + m68k_op_subi_16_ai , + m68k_op_subi_16_ai , + m68k_op_subi_16_pi , + m68k_op_subi_16_pi , + m68k_op_subi_16_pi , + m68k_op_subi_16_pi , + m68k_op_subi_16_pi , + m68k_op_subi_16_pi , + m68k_op_subi_16_pi , + m68k_op_subi_16_pi , + m68k_op_subi_16_pd , + m68k_op_subi_16_pd , + m68k_op_subi_16_pd , + m68k_op_subi_16_pd , + m68k_op_subi_16_pd , + m68k_op_subi_16_pd , + m68k_op_subi_16_pd , + m68k_op_subi_16_pd , + m68k_op_subi_16_di , + m68k_op_subi_16_di , + m68k_op_subi_16_di , + m68k_op_subi_16_di , + m68k_op_subi_16_di , + m68k_op_subi_16_di , + m68k_op_subi_16_di , + m68k_op_subi_16_di , + m68k_op_subi_16_ix , + m68k_op_subi_16_ix , + m68k_op_subi_16_ix , + m68k_op_subi_16_ix , + m68k_op_subi_16_ix , + m68k_op_subi_16_ix , + m68k_op_subi_16_ix , + m68k_op_subi_16_ix , + m68k_op_subi_16_aw , + m68k_op_subi_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subi_32_d , + m68k_op_subi_32_d , + m68k_op_subi_32_d , + m68k_op_subi_32_d , + m68k_op_subi_32_d , + m68k_op_subi_32_d , + m68k_op_subi_32_d , + m68k_op_subi_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subi_32_ai , + m68k_op_subi_32_ai , + m68k_op_subi_32_ai , + m68k_op_subi_32_ai , + m68k_op_subi_32_ai , + m68k_op_subi_32_ai , + m68k_op_subi_32_ai , + m68k_op_subi_32_ai , + m68k_op_subi_32_pi , + m68k_op_subi_32_pi , + m68k_op_subi_32_pi , + m68k_op_subi_32_pi , + m68k_op_subi_32_pi , + m68k_op_subi_32_pi , + m68k_op_subi_32_pi , + m68k_op_subi_32_pi , + m68k_op_subi_32_pd , + m68k_op_subi_32_pd , + m68k_op_subi_32_pd , + m68k_op_subi_32_pd , + m68k_op_subi_32_pd , + m68k_op_subi_32_pd , + m68k_op_subi_32_pd , + m68k_op_subi_32_pd , + m68k_op_subi_32_di , + m68k_op_subi_32_di , + m68k_op_subi_32_di , + m68k_op_subi_32_di , + m68k_op_subi_32_di , + m68k_op_subi_32_di , + m68k_op_subi_32_di , + m68k_op_subi_32_di , + m68k_op_subi_32_ix , + m68k_op_subi_32_ix , + m68k_op_subi_32_ix , + m68k_op_subi_32_ix , + m68k_op_subi_32_ix , + m68k_op_subi_32_ix , + m68k_op_subi_32_ix , + m68k_op_subi_32_ix , + m68k_op_subi_32_aw , + m68k_op_subi_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk2cmp2_32_ai , + m68k_op_chk2cmp2_32_ai , + m68k_op_chk2cmp2_32_ai , + m68k_op_chk2cmp2_32_ai , + m68k_op_chk2cmp2_32_ai , + m68k_op_chk2cmp2_32_ai , + m68k_op_chk2cmp2_32_ai , + m68k_op_chk2cmp2_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk2cmp2_32_di , + m68k_op_chk2cmp2_32_di , + m68k_op_chk2cmp2_32_di , + m68k_op_chk2cmp2_32_di , + m68k_op_chk2cmp2_32_di , + m68k_op_chk2cmp2_32_di , + m68k_op_chk2cmp2_32_di , + m68k_op_chk2cmp2_32_di , + m68k_op_chk2cmp2_32_ix , + m68k_op_chk2cmp2_32_ix , + m68k_op_chk2cmp2_32_ix , + m68k_op_chk2cmp2_32_ix , + m68k_op_chk2cmp2_32_ix , + m68k_op_chk2cmp2_32_ix , + m68k_op_chk2cmp2_32_ix , + m68k_op_chk2cmp2_32_ix , + m68k_op_chk2cmp2_32_aw , + m68k_op_chk2cmp2_32_al , + m68k_op_chk2cmp2_32_pcdi , + m68k_op_chk2cmp2_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi7 , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd7 , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_aw , + m68k_op_btst_8_r_al , + m68k_op_btst_8_r_pcdi , + m68k_op_btst_8_r_pcix , + m68k_op_btst_8_r_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi7 , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd7 , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_aw , + m68k_op_bchg_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi7 , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd7 , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_aw , + m68k_op_bclr_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi7 , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd7 , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_aw , + m68k_op_bset_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addi_8_d , + m68k_op_addi_8_d , + m68k_op_addi_8_d , + m68k_op_addi_8_d , + m68k_op_addi_8_d , + m68k_op_addi_8_d , + m68k_op_addi_8_d , + m68k_op_addi_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addi_8_ai , + m68k_op_addi_8_ai , + m68k_op_addi_8_ai , + m68k_op_addi_8_ai , + m68k_op_addi_8_ai , + m68k_op_addi_8_ai , + m68k_op_addi_8_ai , + m68k_op_addi_8_ai , + m68k_op_addi_8_pi , + m68k_op_addi_8_pi , + m68k_op_addi_8_pi , + m68k_op_addi_8_pi , + m68k_op_addi_8_pi , + m68k_op_addi_8_pi , + m68k_op_addi_8_pi , + m68k_op_addi_8_pi7 , + m68k_op_addi_8_pd , + m68k_op_addi_8_pd , + m68k_op_addi_8_pd , + m68k_op_addi_8_pd , + m68k_op_addi_8_pd , + m68k_op_addi_8_pd , + m68k_op_addi_8_pd , + m68k_op_addi_8_pd7 , + m68k_op_addi_8_di , + m68k_op_addi_8_di , + m68k_op_addi_8_di , + m68k_op_addi_8_di , + m68k_op_addi_8_di , + m68k_op_addi_8_di , + m68k_op_addi_8_di , + m68k_op_addi_8_di , + m68k_op_addi_8_ix , + m68k_op_addi_8_ix , + m68k_op_addi_8_ix , + m68k_op_addi_8_ix , + m68k_op_addi_8_ix , + m68k_op_addi_8_ix , + m68k_op_addi_8_ix , + m68k_op_addi_8_ix , + m68k_op_addi_8_aw , + m68k_op_addi_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addi_16_d , + m68k_op_addi_16_d , + m68k_op_addi_16_d , + m68k_op_addi_16_d , + m68k_op_addi_16_d , + m68k_op_addi_16_d , + m68k_op_addi_16_d , + m68k_op_addi_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addi_16_ai , + m68k_op_addi_16_ai , + m68k_op_addi_16_ai , + m68k_op_addi_16_ai , + m68k_op_addi_16_ai , + m68k_op_addi_16_ai , + m68k_op_addi_16_ai , + m68k_op_addi_16_ai , + m68k_op_addi_16_pi , + m68k_op_addi_16_pi , + m68k_op_addi_16_pi , + m68k_op_addi_16_pi , + m68k_op_addi_16_pi , + m68k_op_addi_16_pi , + m68k_op_addi_16_pi , + m68k_op_addi_16_pi , + m68k_op_addi_16_pd , + m68k_op_addi_16_pd , + m68k_op_addi_16_pd , + m68k_op_addi_16_pd , + m68k_op_addi_16_pd , + m68k_op_addi_16_pd , + m68k_op_addi_16_pd , + m68k_op_addi_16_pd , + m68k_op_addi_16_di , + m68k_op_addi_16_di , + m68k_op_addi_16_di , + m68k_op_addi_16_di , + m68k_op_addi_16_di , + m68k_op_addi_16_di , + m68k_op_addi_16_di , + m68k_op_addi_16_di , + m68k_op_addi_16_ix , + m68k_op_addi_16_ix , + m68k_op_addi_16_ix , + m68k_op_addi_16_ix , + m68k_op_addi_16_ix , + m68k_op_addi_16_ix , + m68k_op_addi_16_ix , + m68k_op_addi_16_ix , + m68k_op_addi_16_aw , + m68k_op_addi_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addi_32_d , + m68k_op_addi_32_d , + m68k_op_addi_32_d , + m68k_op_addi_32_d , + m68k_op_addi_32_d , + m68k_op_addi_32_d , + m68k_op_addi_32_d , + m68k_op_addi_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addi_32_ai , + m68k_op_addi_32_ai , + m68k_op_addi_32_ai , + m68k_op_addi_32_ai , + m68k_op_addi_32_ai , + m68k_op_addi_32_ai , + m68k_op_addi_32_ai , + m68k_op_addi_32_ai , + m68k_op_addi_32_pi , + m68k_op_addi_32_pi , + m68k_op_addi_32_pi , + m68k_op_addi_32_pi , + m68k_op_addi_32_pi , + m68k_op_addi_32_pi , + m68k_op_addi_32_pi , + m68k_op_addi_32_pi , + m68k_op_addi_32_pd , + m68k_op_addi_32_pd , + m68k_op_addi_32_pd , + m68k_op_addi_32_pd , + m68k_op_addi_32_pd , + m68k_op_addi_32_pd , + m68k_op_addi_32_pd , + m68k_op_addi_32_pd , + m68k_op_addi_32_di , + m68k_op_addi_32_di , + m68k_op_addi_32_di , + m68k_op_addi_32_di , + m68k_op_addi_32_di , + m68k_op_addi_32_di , + m68k_op_addi_32_di , + m68k_op_addi_32_di , + m68k_op_addi_32_ix , + m68k_op_addi_32_ix , + m68k_op_addi_32_ix , + m68k_op_addi_32_ix , + m68k_op_addi_32_ix , + m68k_op_addi_32_ix , + m68k_op_addi_32_ix , + m68k_op_addi_32_ix , + m68k_op_addi_32_aw , + m68k_op_addi_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_rtm_32 , + m68k_op_callm_32_ai , + m68k_op_callm_32_ai , + m68k_op_callm_32_ai , + m68k_op_callm_32_ai , + m68k_op_callm_32_ai , + m68k_op_callm_32_ai , + m68k_op_callm_32_ai , + m68k_op_callm_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_callm_32_di , + m68k_op_callm_32_di , + m68k_op_callm_32_di , + m68k_op_callm_32_di , + m68k_op_callm_32_di , + m68k_op_callm_32_di , + m68k_op_callm_32_di , + m68k_op_callm_32_di , + m68k_op_callm_32_ix , + m68k_op_callm_32_ix , + m68k_op_callm_32_ix , + m68k_op_callm_32_ix , + m68k_op_callm_32_ix , + m68k_op_callm_32_ix , + m68k_op_callm_32_ix , + m68k_op_callm_32_ix , + m68k_op_callm_32_aw , + m68k_op_callm_32_al , + m68k_op_callm_32_pcdi , + m68k_op_callm_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi7 , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd7 , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_aw , + m68k_op_btst_8_r_al , + m68k_op_btst_8_r_pcdi , + m68k_op_btst_8_r_pcix , + m68k_op_btst_8_r_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi7 , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd7 , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_aw , + m68k_op_bchg_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi7 , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd7 , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_aw , + m68k_op_bclr_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi7 , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd7 , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_aw , + m68k_op_bset_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_32_s_d , + m68k_op_btst_32_s_d , + m68k_op_btst_32_s_d , + m68k_op_btst_32_s_d , + m68k_op_btst_32_s_d , + m68k_op_btst_32_s_d , + m68k_op_btst_32_s_d , + m68k_op_btst_32_s_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_8_s_ai , + m68k_op_btst_8_s_ai , + m68k_op_btst_8_s_ai , + m68k_op_btst_8_s_ai , + m68k_op_btst_8_s_ai , + m68k_op_btst_8_s_ai , + m68k_op_btst_8_s_ai , + m68k_op_btst_8_s_ai , + m68k_op_btst_8_s_pi , + m68k_op_btst_8_s_pi , + m68k_op_btst_8_s_pi , + m68k_op_btst_8_s_pi , + m68k_op_btst_8_s_pi , + m68k_op_btst_8_s_pi , + m68k_op_btst_8_s_pi , + m68k_op_btst_8_s_pi7 , + m68k_op_btst_8_s_pd , + m68k_op_btst_8_s_pd , + m68k_op_btst_8_s_pd , + m68k_op_btst_8_s_pd , + m68k_op_btst_8_s_pd , + m68k_op_btst_8_s_pd , + m68k_op_btst_8_s_pd , + m68k_op_btst_8_s_pd7 , + m68k_op_btst_8_s_di , + m68k_op_btst_8_s_di , + m68k_op_btst_8_s_di , + m68k_op_btst_8_s_di , + m68k_op_btst_8_s_di , + m68k_op_btst_8_s_di , + m68k_op_btst_8_s_di , + m68k_op_btst_8_s_di , + m68k_op_btst_8_s_ix , + m68k_op_btst_8_s_ix , + m68k_op_btst_8_s_ix , + m68k_op_btst_8_s_ix , + m68k_op_btst_8_s_ix , + m68k_op_btst_8_s_ix , + m68k_op_btst_8_s_ix , + m68k_op_btst_8_s_ix , + m68k_op_btst_8_s_aw , + m68k_op_btst_8_s_al , + m68k_op_btst_8_s_pcdi , + m68k_op_btst_8_s_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_32_s_d , + m68k_op_bchg_32_s_d , + m68k_op_bchg_32_s_d , + m68k_op_bchg_32_s_d , + m68k_op_bchg_32_s_d , + m68k_op_bchg_32_s_d , + m68k_op_bchg_32_s_d , + m68k_op_bchg_32_s_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_8_s_ai , + m68k_op_bchg_8_s_ai , + m68k_op_bchg_8_s_ai , + m68k_op_bchg_8_s_ai , + m68k_op_bchg_8_s_ai , + m68k_op_bchg_8_s_ai , + m68k_op_bchg_8_s_ai , + m68k_op_bchg_8_s_ai , + m68k_op_bchg_8_s_pi , + m68k_op_bchg_8_s_pi , + m68k_op_bchg_8_s_pi , + m68k_op_bchg_8_s_pi , + m68k_op_bchg_8_s_pi , + m68k_op_bchg_8_s_pi , + m68k_op_bchg_8_s_pi , + m68k_op_bchg_8_s_pi7 , + m68k_op_bchg_8_s_pd , + m68k_op_bchg_8_s_pd , + m68k_op_bchg_8_s_pd , + m68k_op_bchg_8_s_pd , + m68k_op_bchg_8_s_pd , + m68k_op_bchg_8_s_pd , + m68k_op_bchg_8_s_pd , + m68k_op_bchg_8_s_pd7 , + m68k_op_bchg_8_s_di , + m68k_op_bchg_8_s_di , + m68k_op_bchg_8_s_di , + m68k_op_bchg_8_s_di , + m68k_op_bchg_8_s_di , + m68k_op_bchg_8_s_di , + m68k_op_bchg_8_s_di , + m68k_op_bchg_8_s_di , + m68k_op_bchg_8_s_ix , + m68k_op_bchg_8_s_ix , + m68k_op_bchg_8_s_ix , + m68k_op_bchg_8_s_ix , + m68k_op_bchg_8_s_ix , + m68k_op_bchg_8_s_ix , + m68k_op_bchg_8_s_ix , + m68k_op_bchg_8_s_ix , + m68k_op_bchg_8_s_aw , + m68k_op_bchg_8_s_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_32_s_d , + m68k_op_bclr_32_s_d , + m68k_op_bclr_32_s_d , + m68k_op_bclr_32_s_d , + m68k_op_bclr_32_s_d , + m68k_op_bclr_32_s_d , + m68k_op_bclr_32_s_d , + m68k_op_bclr_32_s_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_8_s_ai , + m68k_op_bclr_8_s_ai , + m68k_op_bclr_8_s_ai , + m68k_op_bclr_8_s_ai , + m68k_op_bclr_8_s_ai , + m68k_op_bclr_8_s_ai , + m68k_op_bclr_8_s_ai , + m68k_op_bclr_8_s_ai , + m68k_op_bclr_8_s_pi , + m68k_op_bclr_8_s_pi , + m68k_op_bclr_8_s_pi , + m68k_op_bclr_8_s_pi , + m68k_op_bclr_8_s_pi , + m68k_op_bclr_8_s_pi , + m68k_op_bclr_8_s_pi , + m68k_op_bclr_8_s_pi7 , + m68k_op_bclr_8_s_pd , + m68k_op_bclr_8_s_pd , + m68k_op_bclr_8_s_pd , + m68k_op_bclr_8_s_pd , + m68k_op_bclr_8_s_pd , + m68k_op_bclr_8_s_pd , + m68k_op_bclr_8_s_pd , + m68k_op_bclr_8_s_pd7 , + m68k_op_bclr_8_s_di , + m68k_op_bclr_8_s_di , + m68k_op_bclr_8_s_di , + m68k_op_bclr_8_s_di , + m68k_op_bclr_8_s_di , + m68k_op_bclr_8_s_di , + m68k_op_bclr_8_s_di , + m68k_op_bclr_8_s_di , + m68k_op_bclr_8_s_ix , + m68k_op_bclr_8_s_ix , + m68k_op_bclr_8_s_ix , + m68k_op_bclr_8_s_ix , + m68k_op_bclr_8_s_ix , + m68k_op_bclr_8_s_ix , + m68k_op_bclr_8_s_ix , + m68k_op_bclr_8_s_ix , + m68k_op_bclr_8_s_aw , + m68k_op_bclr_8_s_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_32_s_d , + m68k_op_bset_32_s_d , + m68k_op_bset_32_s_d , + m68k_op_bset_32_s_d , + m68k_op_bset_32_s_d , + m68k_op_bset_32_s_d , + m68k_op_bset_32_s_d , + m68k_op_bset_32_s_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_8_s_ai , + m68k_op_bset_8_s_ai , + m68k_op_bset_8_s_ai , + m68k_op_bset_8_s_ai , + m68k_op_bset_8_s_ai , + m68k_op_bset_8_s_ai , + m68k_op_bset_8_s_ai , + m68k_op_bset_8_s_ai , + m68k_op_bset_8_s_pi , + m68k_op_bset_8_s_pi , + m68k_op_bset_8_s_pi , + m68k_op_bset_8_s_pi , + m68k_op_bset_8_s_pi , + m68k_op_bset_8_s_pi , + m68k_op_bset_8_s_pi , + m68k_op_bset_8_s_pi7 , + m68k_op_bset_8_s_pd , + m68k_op_bset_8_s_pd , + m68k_op_bset_8_s_pd , + m68k_op_bset_8_s_pd , + m68k_op_bset_8_s_pd , + m68k_op_bset_8_s_pd , + m68k_op_bset_8_s_pd , + m68k_op_bset_8_s_pd7 , + m68k_op_bset_8_s_di , + m68k_op_bset_8_s_di , + m68k_op_bset_8_s_di , + m68k_op_bset_8_s_di , + m68k_op_bset_8_s_di , + m68k_op_bset_8_s_di , + m68k_op_bset_8_s_di , + m68k_op_bset_8_s_di , + m68k_op_bset_8_s_ix , + m68k_op_bset_8_s_ix , + m68k_op_bset_8_s_ix , + m68k_op_bset_8_s_ix , + m68k_op_bset_8_s_ix , + m68k_op_bset_8_s_ix , + m68k_op_bset_8_s_ix , + m68k_op_bset_8_s_ix , + m68k_op_bset_8_s_aw , + m68k_op_bset_8_s_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi7 , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd7 , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_aw , + m68k_op_btst_8_r_al , + m68k_op_btst_8_r_pcdi , + m68k_op_btst_8_r_pcix , + m68k_op_btst_8_r_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi7 , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd7 , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_aw , + m68k_op_bchg_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi7 , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd7 , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_aw , + m68k_op_bclr_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi7 , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd7 , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_aw , + m68k_op_bset_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eori_8_d , + m68k_op_eori_8_d , + m68k_op_eori_8_d , + m68k_op_eori_8_d , + m68k_op_eori_8_d , + m68k_op_eori_8_d , + m68k_op_eori_8_d , + m68k_op_eori_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eori_8_ai , + m68k_op_eori_8_ai , + m68k_op_eori_8_ai , + m68k_op_eori_8_ai , + m68k_op_eori_8_ai , + m68k_op_eori_8_ai , + m68k_op_eori_8_ai , + m68k_op_eori_8_ai , + m68k_op_eori_8_pi , + m68k_op_eori_8_pi , + m68k_op_eori_8_pi , + m68k_op_eori_8_pi , + m68k_op_eori_8_pi , + m68k_op_eori_8_pi , + m68k_op_eori_8_pi , + m68k_op_eori_8_pi7 , + m68k_op_eori_8_pd , + m68k_op_eori_8_pd , + m68k_op_eori_8_pd , + m68k_op_eori_8_pd , + m68k_op_eori_8_pd , + m68k_op_eori_8_pd , + m68k_op_eori_8_pd , + m68k_op_eori_8_pd7 , + m68k_op_eori_8_di , + m68k_op_eori_8_di , + m68k_op_eori_8_di , + m68k_op_eori_8_di , + m68k_op_eori_8_di , + m68k_op_eori_8_di , + m68k_op_eori_8_di , + m68k_op_eori_8_di , + m68k_op_eori_8_ix , + m68k_op_eori_8_ix , + m68k_op_eori_8_ix , + m68k_op_eori_8_ix , + m68k_op_eori_8_ix , + m68k_op_eori_8_ix , + m68k_op_eori_8_ix , + m68k_op_eori_8_ix , + m68k_op_eori_8_aw , + m68k_op_eori_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eori_16_toc , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eori_16_d , + m68k_op_eori_16_d , + m68k_op_eori_16_d , + m68k_op_eori_16_d , + m68k_op_eori_16_d , + m68k_op_eori_16_d , + m68k_op_eori_16_d , + m68k_op_eori_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eori_16_ai , + m68k_op_eori_16_ai , + m68k_op_eori_16_ai , + m68k_op_eori_16_ai , + m68k_op_eori_16_ai , + m68k_op_eori_16_ai , + m68k_op_eori_16_ai , + m68k_op_eori_16_ai , + m68k_op_eori_16_pi , + m68k_op_eori_16_pi , + m68k_op_eori_16_pi , + m68k_op_eori_16_pi , + m68k_op_eori_16_pi , + m68k_op_eori_16_pi , + m68k_op_eori_16_pi , + m68k_op_eori_16_pi , + m68k_op_eori_16_pd , + m68k_op_eori_16_pd , + m68k_op_eori_16_pd , + m68k_op_eori_16_pd , + m68k_op_eori_16_pd , + m68k_op_eori_16_pd , + m68k_op_eori_16_pd , + m68k_op_eori_16_pd , + m68k_op_eori_16_di , + m68k_op_eori_16_di , + m68k_op_eori_16_di , + m68k_op_eori_16_di , + m68k_op_eori_16_di , + m68k_op_eori_16_di , + m68k_op_eori_16_di , + m68k_op_eori_16_di , + m68k_op_eori_16_ix , + m68k_op_eori_16_ix , + m68k_op_eori_16_ix , + m68k_op_eori_16_ix , + m68k_op_eori_16_ix , + m68k_op_eori_16_ix , + m68k_op_eori_16_ix , + m68k_op_eori_16_ix , + m68k_op_eori_16_aw , + m68k_op_eori_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eori_16_tos , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eori_32_d , + m68k_op_eori_32_d , + m68k_op_eori_32_d , + m68k_op_eori_32_d , + m68k_op_eori_32_d , + m68k_op_eori_32_d , + m68k_op_eori_32_d , + m68k_op_eori_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eori_32_ai , + m68k_op_eori_32_ai , + m68k_op_eori_32_ai , + m68k_op_eori_32_ai , + m68k_op_eori_32_ai , + m68k_op_eori_32_ai , + m68k_op_eori_32_ai , + m68k_op_eori_32_ai , + m68k_op_eori_32_pi , + m68k_op_eori_32_pi , + m68k_op_eori_32_pi , + m68k_op_eori_32_pi , + m68k_op_eori_32_pi , + m68k_op_eori_32_pi , + m68k_op_eori_32_pi , + m68k_op_eori_32_pi , + m68k_op_eori_32_pd , + m68k_op_eori_32_pd , + m68k_op_eori_32_pd , + m68k_op_eori_32_pd , + m68k_op_eori_32_pd , + m68k_op_eori_32_pd , + m68k_op_eori_32_pd , + m68k_op_eori_32_pd , + m68k_op_eori_32_di , + m68k_op_eori_32_di , + m68k_op_eori_32_di , + m68k_op_eori_32_di , + m68k_op_eori_32_di , + m68k_op_eori_32_di , + m68k_op_eori_32_di , + m68k_op_eori_32_di , + m68k_op_eori_32_ix , + m68k_op_eori_32_ix , + m68k_op_eori_32_ix , + m68k_op_eori_32_ix , + m68k_op_eori_32_ix , + m68k_op_eori_32_ix , + m68k_op_eori_32_ix , + m68k_op_eori_32_ix , + m68k_op_eori_32_aw , + m68k_op_eori_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cas_8_ai , + m68k_op_cas_8_ai , + m68k_op_cas_8_ai , + m68k_op_cas_8_ai , + m68k_op_cas_8_ai , + m68k_op_cas_8_ai , + m68k_op_cas_8_ai , + m68k_op_cas_8_ai , + m68k_op_cas_8_pi , + m68k_op_cas_8_pi , + m68k_op_cas_8_pi , + m68k_op_cas_8_pi , + m68k_op_cas_8_pi , + m68k_op_cas_8_pi , + m68k_op_cas_8_pi , + m68k_op_cas_8_pi7 , + m68k_op_cas_8_pd , + m68k_op_cas_8_pd , + m68k_op_cas_8_pd , + m68k_op_cas_8_pd , + m68k_op_cas_8_pd , + m68k_op_cas_8_pd , + m68k_op_cas_8_pd , + m68k_op_cas_8_pd7 , + m68k_op_cas_8_di , + m68k_op_cas_8_di , + m68k_op_cas_8_di , + m68k_op_cas_8_di , + m68k_op_cas_8_di , + m68k_op_cas_8_di , + m68k_op_cas_8_di , + m68k_op_cas_8_di , + m68k_op_cas_8_ix , + m68k_op_cas_8_ix , + m68k_op_cas_8_ix , + m68k_op_cas_8_ix , + m68k_op_cas_8_ix , + m68k_op_cas_8_ix , + m68k_op_cas_8_ix , + m68k_op_cas_8_ix , + m68k_op_cas_8_aw , + m68k_op_cas_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi7 , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd7 , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_aw , + m68k_op_btst_8_r_al , + m68k_op_btst_8_r_pcdi , + m68k_op_btst_8_r_pcix , + m68k_op_btst_8_r_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi7 , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd7 , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_aw , + m68k_op_bchg_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi7 , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd7 , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_aw , + m68k_op_bclr_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi7 , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd7 , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_aw , + m68k_op_bset_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpi_8_d , + m68k_op_cmpi_8_d , + m68k_op_cmpi_8_d , + m68k_op_cmpi_8_d , + m68k_op_cmpi_8_d , + m68k_op_cmpi_8_d , + m68k_op_cmpi_8_d , + m68k_op_cmpi_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpi_8_ai , + m68k_op_cmpi_8_ai , + m68k_op_cmpi_8_ai , + m68k_op_cmpi_8_ai , + m68k_op_cmpi_8_ai , + m68k_op_cmpi_8_ai , + m68k_op_cmpi_8_ai , + m68k_op_cmpi_8_ai , + m68k_op_cmpi_8_pi , + m68k_op_cmpi_8_pi , + m68k_op_cmpi_8_pi , + m68k_op_cmpi_8_pi , + m68k_op_cmpi_8_pi , + m68k_op_cmpi_8_pi , + m68k_op_cmpi_8_pi , + m68k_op_cmpi_8_pi7 , + m68k_op_cmpi_8_pd , + m68k_op_cmpi_8_pd , + m68k_op_cmpi_8_pd , + m68k_op_cmpi_8_pd , + m68k_op_cmpi_8_pd , + m68k_op_cmpi_8_pd , + m68k_op_cmpi_8_pd , + m68k_op_cmpi_8_pd7 , + m68k_op_cmpi_8_di , + m68k_op_cmpi_8_di , + m68k_op_cmpi_8_di , + m68k_op_cmpi_8_di , + m68k_op_cmpi_8_di , + m68k_op_cmpi_8_di , + m68k_op_cmpi_8_di , + m68k_op_cmpi_8_di , + m68k_op_cmpi_8_ix , + m68k_op_cmpi_8_ix , + m68k_op_cmpi_8_ix , + m68k_op_cmpi_8_ix , + m68k_op_cmpi_8_ix , + m68k_op_cmpi_8_ix , + m68k_op_cmpi_8_ix , + m68k_op_cmpi_8_ix , + m68k_op_cmpi_8_aw , + m68k_op_cmpi_8_al , + m68k_op_cmpi_8_pcdi , + m68k_op_cmpi_8_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpi_16_d , + m68k_op_cmpi_16_d , + m68k_op_cmpi_16_d , + m68k_op_cmpi_16_d , + m68k_op_cmpi_16_d , + m68k_op_cmpi_16_d , + m68k_op_cmpi_16_d , + m68k_op_cmpi_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpi_16_ai , + m68k_op_cmpi_16_ai , + m68k_op_cmpi_16_ai , + m68k_op_cmpi_16_ai , + m68k_op_cmpi_16_ai , + m68k_op_cmpi_16_ai , + m68k_op_cmpi_16_ai , + m68k_op_cmpi_16_ai , + m68k_op_cmpi_16_pi , + m68k_op_cmpi_16_pi , + m68k_op_cmpi_16_pi , + m68k_op_cmpi_16_pi , + m68k_op_cmpi_16_pi , + m68k_op_cmpi_16_pi , + m68k_op_cmpi_16_pi , + m68k_op_cmpi_16_pi , + m68k_op_cmpi_16_pd , + m68k_op_cmpi_16_pd , + m68k_op_cmpi_16_pd , + m68k_op_cmpi_16_pd , + m68k_op_cmpi_16_pd , + m68k_op_cmpi_16_pd , + m68k_op_cmpi_16_pd , + m68k_op_cmpi_16_pd , + m68k_op_cmpi_16_di , + m68k_op_cmpi_16_di , + m68k_op_cmpi_16_di , + m68k_op_cmpi_16_di , + m68k_op_cmpi_16_di , + m68k_op_cmpi_16_di , + m68k_op_cmpi_16_di , + m68k_op_cmpi_16_di , + m68k_op_cmpi_16_ix , + m68k_op_cmpi_16_ix , + m68k_op_cmpi_16_ix , + m68k_op_cmpi_16_ix , + m68k_op_cmpi_16_ix , + m68k_op_cmpi_16_ix , + m68k_op_cmpi_16_ix , + m68k_op_cmpi_16_ix , + m68k_op_cmpi_16_aw , + m68k_op_cmpi_16_al , + m68k_op_cmpi_16_pcdi , + m68k_op_cmpi_16_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpi_32_d , + m68k_op_cmpi_32_d , + m68k_op_cmpi_32_d , + m68k_op_cmpi_32_d , + m68k_op_cmpi_32_d , + m68k_op_cmpi_32_d , + m68k_op_cmpi_32_d , + m68k_op_cmpi_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpi_32_ai , + m68k_op_cmpi_32_ai , + m68k_op_cmpi_32_ai , + m68k_op_cmpi_32_ai , + m68k_op_cmpi_32_ai , + m68k_op_cmpi_32_ai , + m68k_op_cmpi_32_ai , + m68k_op_cmpi_32_ai , + m68k_op_cmpi_32_pi , + m68k_op_cmpi_32_pi , + m68k_op_cmpi_32_pi , + m68k_op_cmpi_32_pi , + m68k_op_cmpi_32_pi , + m68k_op_cmpi_32_pi , + m68k_op_cmpi_32_pi , + m68k_op_cmpi_32_pi , + m68k_op_cmpi_32_pd , + m68k_op_cmpi_32_pd , + m68k_op_cmpi_32_pd , + m68k_op_cmpi_32_pd , + m68k_op_cmpi_32_pd , + m68k_op_cmpi_32_pd , + m68k_op_cmpi_32_pd , + m68k_op_cmpi_32_pd , + m68k_op_cmpi_32_di , + m68k_op_cmpi_32_di , + m68k_op_cmpi_32_di , + m68k_op_cmpi_32_di , + m68k_op_cmpi_32_di , + m68k_op_cmpi_32_di , + m68k_op_cmpi_32_di , + m68k_op_cmpi_32_di , + m68k_op_cmpi_32_ix , + m68k_op_cmpi_32_ix , + m68k_op_cmpi_32_ix , + m68k_op_cmpi_32_ix , + m68k_op_cmpi_32_ix , + m68k_op_cmpi_32_ix , + m68k_op_cmpi_32_ix , + m68k_op_cmpi_32_ix , + m68k_op_cmpi_32_aw , + m68k_op_cmpi_32_al , + m68k_op_cmpi_32_pcdi , + m68k_op_cmpi_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cas_16_ai , + m68k_op_cas_16_ai , + m68k_op_cas_16_ai , + m68k_op_cas_16_ai , + m68k_op_cas_16_ai , + m68k_op_cas_16_ai , + m68k_op_cas_16_ai , + m68k_op_cas_16_ai , + m68k_op_cas_16_pi , + m68k_op_cas_16_pi , + m68k_op_cas_16_pi , + m68k_op_cas_16_pi , + m68k_op_cas_16_pi , + m68k_op_cas_16_pi , + m68k_op_cas_16_pi , + m68k_op_cas_16_pi , + m68k_op_cas_16_pd , + m68k_op_cas_16_pd , + m68k_op_cas_16_pd , + m68k_op_cas_16_pd , + m68k_op_cas_16_pd , + m68k_op_cas_16_pd , + m68k_op_cas_16_pd , + m68k_op_cas_16_pd , + m68k_op_cas_16_di , + m68k_op_cas_16_di , + m68k_op_cas_16_di , + m68k_op_cas_16_di , + m68k_op_cas_16_di , + m68k_op_cas_16_di , + m68k_op_cas_16_di , + m68k_op_cas_16_di , + m68k_op_cas_16_ix , + m68k_op_cas_16_ix , + m68k_op_cas_16_ix , + m68k_op_cas_16_ix , + m68k_op_cas_16_ix , + m68k_op_cas_16_ix , + m68k_op_cas_16_ix , + m68k_op_cas_16_ix , + m68k_op_cas_16_aw , + m68k_op_cas_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cas2_16 , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi7 , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd7 , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_aw , + m68k_op_btst_8_r_al , + m68k_op_btst_8_r_pcdi , + m68k_op_btst_8_r_pcix , + m68k_op_btst_8_r_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi7 , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd7 , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_aw , + m68k_op_bchg_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi7 , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd7 , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_aw , + m68k_op_bclr_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi7 , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd7 , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_aw , + m68k_op_bset_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_moves_8_ai , + m68k_op_moves_8_ai , + m68k_op_moves_8_ai , + m68k_op_moves_8_ai , + m68k_op_moves_8_ai , + m68k_op_moves_8_ai , + m68k_op_moves_8_ai , + m68k_op_moves_8_ai , + m68k_op_moves_8_pi , + m68k_op_moves_8_pi , + m68k_op_moves_8_pi , + m68k_op_moves_8_pi , + m68k_op_moves_8_pi , + m68k_op_moves_8_pi , + m68k_op_moves_8_pi , + m68k_op_moves_8_pi7 , + m68k_op_moves_8_pd , + m68k_op_moves_8_pd , + m68k_op_moves_8_pd , + m68k_op_moves_8_pd , + m68k_op_moves_8_pd , + m68k_op_moves_8_pd , + m68k_op_moves_8_pd , + m68k_op_moves_8_pd7 , + m68k_op_moves_8_di , + m68k_op_moves_8_di , + m68k_op_moves_8_di , + m68k_op_moves_8_di , + m68k_op_moves_8_di , + m68k_op_moves_8_di , + m68k_op_moves_8_di , + m68k_op_moves_8_di , + m68k_op_moves_8_ix , + m68k_op_moves_8_ix , + m68k_op_moves_8_ix , + m68k_op_moves_8_ix , + m68k_op_moves_8_ix , + m68k_op_moves_8_ix , + m68k_op_moves_8_ix , + m68k_op_moves_8_ix , + m68k_op_moves_8_aw , + m68k_op_moves_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_moves_16_ai , + m68k_op_moves_16_ai , + m68k_op_moves_16_ai , + m68k_op_moves_16_ai , + m68k_op_moves_16_ai , + m68k_op_moves_16_ai , + m68k_op_moves_16_ai , + m68k_op_moves_16_ai , + m68k_op_moves_16_pi , + m68k_op_moves_16_pi , + m68k_op_moves_16_pi , + m68k_op_moves_16_pi , + m68k_op_moves_16_pi , + m68k_op_moves_16_pi , + m68k_op_moves_16_pi , + m68k_op_moves_16_pi , + m68k_op_moves_16_pd , + m68k_op_moves_16_pd , + m68k_op_moves_16_pd , + m68k_op_moves_16_pd , + m68k_op_moves_16_pd , + m68k_op_moves_16_pd , + m68k_op_moves_16_pd , + m68k_op_moves_16_pd , + m68k_op_moves_16_di , + m68k_op_moves_16_di , + m68k_op_moves_16_di , + m68k_op_moves_16_di , + m68k_op_moves_16_di , + m68k_op_moves_16_di , + m68k_op_moves_16_di , + m68k_op_moves_16_di , + m68k_op_moves_16_ix , + m68k_op_moves_16_ix , + m68k_op_moves_16_ix , + m68k_op_moves_16_ix , + m68k_op_moves_16_ix , + m68k_op_moves_16_ix , + m68k_op_moves_16_ix , + m68k_op_moves_16_ix , + m68k_op_moves_16_aw , + m68k_op_moves_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_moves_32_ai , + m68k_op_moves_32_ai , + m68k_op_moves_32_ai , + m68k_op_moves_32_ai , + m68k_op_moves_32_ai , + m68k_op_moves_32_ai , + m68k_op_moves_32_ai , + m68k_op_moves_32_ai , + m68k_op_moves_32_pi , + m68k_op_moves_32_pi , + m68k_op_moves_32_pi , + m68k_op_moves_32_pi , + m68k_op_moves_32_pi , + m68k_op_moves_32_pi , + m68k_op_moves_32_pi , + m68k_op_moves_32_pi , + m68k_op_moves_32_pd , + m68k_op_moves_32_pd , + m68k_op_moves_32_pd , + m68k_op_moves_32_pd , + m68k_op_moves_32_pd , + m68k_op_moves_32_pd , + m68k_op_moves_32_pd , + m68k_op_moves_32_pd , + m68k_op_moves_32_di , + m68k_op_moves_32_di , + m68k_op_moves_32_di , + m68k_op_moves_32_di , + m68k_op_moves_32_di , + m68k_op_moves_32_di , + m68k_op_moves_32_di , + m68k_op_moves_32_di , + m68k_op_moves_32_ix , + m68k_op_moves_32_ix , + m68k_op_moves_32_ix , + m68k_op_moves_32_ix , + m68k_op_moves_32_ix , + m68k_op_moves_32_ix , + m68k_op_moves_32_ix , + m68k_op_moves_32_ix , + m68k_op_moves_32_aw , + m68k_op_moves_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cas_32_ai , + m68k_op_cas_32_ai , + m68k_op_cas_32_ai , + m68k_op_cas_32_ai , + m68k_op_cas_32_ai , + m68k_op_cas_32_ai , + m68k_op_cas_32_ai , + m68k_op_cas_32_ai , + m68k_op_cas_32_pi , + m68k_op_cas_32_pi , + m68k_op_cas_32_pi , + m68k_op_cas_32_pi , + m68k_op_cas_32_pi , + m68k_op_cas_32_pi , + m68k_op_cas_32_pi , + m68k_op_cas_32_pi , + m68k_op_cas_32_pd , + m68k_op_cas_32_pd , + m68k_op_cas_32_pd , + m68k_op_cas_32_pd , + m68k_op_cas_32_pd , + m68k_op_cas_32_pd , + m68k_op_cas_32_pd , + m68k_op_cas_32_pd , + m68k_op_cas_32_di , + m68k_op_cas_32_di , + m68k_op_cas_32_di , + m68k_op_cas_32_di , + m68k_op_cas_32_di , + m68k_op_cas_32_di , + m68k_op_cas_32_di , + m68k_op_cas_32_di , + m68k_op_cas_32_ix , + m68k_op_cas_32_ix , + m68k_op_cas_32_ix , + m68k_op_cas_32_ix , + m68k_op_cas_32_ix , + m68k_op_cas_32_ix , + m68k_op_cas_32_ix , + m68k_op_cas_32_ix , + m68k_op_cas_32_aw , + m68k_op_cas_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cas2_32 , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_btst_32_r_d , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_movep_16_er , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_ai , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi , + m68k_op_btst_8_r_pi7 , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd , + m68k_op_btst_8_r_pd7 , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_di , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_ix , + m68k_op_btst_8_r_aw , + m68k_op_btst_8_r_al , + m68k_op_btst_8_r_pcdi , + m68k_op_btst_8_r_pcix , + m68k_op_btst_8_r_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_bchg_32_r_d , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_movep_32_er , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_ai , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi , + m68k_op_bchg_8_r_pi7 , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd , + m68k_op_bchg_8_r_pd7 , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_di , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_ix , + m68k_op_bchg_8_r_aw , + m68k_op_bchg_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_bclr_32_r_d , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_movep_16_re , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_ai , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi , + m68k_op_bclr_8_r_pi7 , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd , + m68k_op_bclr_8_r_pd7 , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_di , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_ix , + m68k_op_bclr_8_r_aw , + m68k_op_bclr_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_bset_32_r_d , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_movep_32_re , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_ai , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi , + m68k_op_bset_8_r_pi7 , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd , + m68k_op_bset_8_r_pd7 , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_di , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_ix , + m68k_op_bset_8_r_aw , + m68k_op_bset_8_r_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi7 , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd7 , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_aw , + m68k_op_move_8_d_al , + m68k_op_move_8_d_pcdi , + m68k_op_move_8_d_pcix , + m68k_op_move_8_d_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi7 , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd7 , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_aw , + m68k_op_move_8_ai_al , + m68k_op_move_8_ai_pcdi , + m68k_op_move_8_ai_pcix , + m68k_op_move_8_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi7 , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd7 , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_aw , + m68k_op_move_8_pi_al , + m68k_op_move_8_pi_pcdi , + m68k_op_move_8_pi_pcix , + m68k_op_move_8_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi7 , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd7 , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_aw , + m68k_op_move_8_pd_al , + m68k_op_move_8_pd_pcdi , + m68k_op_move_8_pd_pcix , + m68k_op_move_8_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_illegal, + 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m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_aw , + m68k_op_move_8_di_al , + m68k_op_move_8_di_pcdi , + m68k_op_move_8_di_pcix , + m68k_op_move_8_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi7 , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd7 , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_aw , + m68k_op_move_8_ix_al , + m68k_op_move_8_ix_pcdi , + m68k_op_move_8_ix_pcix , + m68k_op_move_8_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_aw_d , + m68k_op_move_8_aw_d , + m68k_op_move_8_aw_d , + m68k_op_move_8_aw_d , + m68k_op_move_8_aw_d , + m68k_op_move_8_aw_d , + m68k_op_move_8_aw_d , + m68k_op_move_8_aw_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_aw_ai , + m68k_op_move_8_aw_ai , + m68k_op_move_8_aw_ai , + m68k_op_move_8_aw_ai , + m68k_op_move_8_aw_ai , + m68k_op_move_8_aw_ai , + m68k_op_move_8_aw_ai , + m68k_op_move_8_aw_ai , + m68k_op_move_8_aw_pi , + m68k_op_move_8_aw_pi , + m68k_op_move_8_aw_pi , + m68k_op_move_8_aw_pi , + m68k_op_move_8_aw_pi , + m68k_op_move_8_aw_pi , + m68k_op_move_8_aw_pi , + m68k_op_move_8_aw_pi7 , + m68k_op_move_8_aw_pd , + m68k_op_move_8_aw_pd , + m68k_op_move_8_aw_pd , + m68k_op_move_8_aw_pd , + m68k_op_move_8_aw_pd , + m68k_op_move_8_aw_pd , + m68k_op_move_8_aw_pd , + m68k_op_move_8_aw_pd7 , + m68k_op_move_8_aw_di , + m68k_op_move_8_aw_di , + m68k_op_move_8_aw_di , + m68k_op_move_8_aw_di , + m68k_op_move_8_aw_di , + m68k_op_move_8_aw_di , + m68k_op_move_8_aw_di , + m68k_op_move_8_aw_di , + m68k_op_move_8_aw_ix , + m68k_op_move_8_aw_ix , + m68k_op_move_8_aw_ix , + m68k_op_move_8_aw_ix , + m68k_op_move_8_aw_ix , + m68k_op_move_8_aw_ix , + m68k_op_move_8_aw_ix , + m68k_op_move_8_aw_ix , + m68k_op_move_8_aw_aw , + m68k_op_move_8_aw_al , + m68k_op_move_8_aw_pcdi , + m68k_op_move_8_aw_pcix , + m68k_op_move_8_aw_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + 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+ m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd7 , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_aw , + m68k_op_move_8_ai_al , + m68k_op_move_8_ai_pcdi , + m68k_op_move_8_ai_pcix , + m68k_op_move_8_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi7 , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd7 , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_aw , + m68k_op_move_8_pi_al , + m68k_op_move_8_pi_pcdi , + m68k_op_move_8_pi_pcix , + m68k_op_move_8_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi7 , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd7 , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_aw , + m68k_op_move_8_pd_al , + m68k_op_move_8_pd_pcdi , + m68k_op_move_8_pd_pcix , + m68k_op_move_8_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi7 , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd7 , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_aw , + m68k_op_move_8_di_al , + m68k_op_move_8_di_pcdi , + m68k_op_move_8_di_pcix , + m68k_op_move_8_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi 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m68k_op_move_8_al_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_al_ai , + m68k_op_move_8_al_ai , + m68k_op_move_8_al_ai , + m68k_op_move_8_al_ai , + m68k_op_move_8_al_ai , + m68k_op_move_8_al_ai , + m68k_op_move_8_al_ai , + m68k_op_move_8_al_ai , + m68k_op_move_8_al_pi , + m68k_op_move_8_al_pi , + m68k_op_move_8_al_pi , + m68k_op_move_8_al_pi , + m68k_op_move_8_al_pi , + m68k_op_move_8_al_pi , + m68k_op_move_8_al_pi , + m68k_op_move_8_al_pi7 , + m68k_op_move_8_al_pd , + m68k_op_move_8_al_pd , + m68k_op_move_8_al_pd , + m68k_op_move_8_al_pd , + m68k_op_move_8_al_pd , + m68k_op_move_8_al_pd , + m68k_op_move_8_al_pd , + m68k_op_move_8_al_pd7 , + m68k_op_move_8_al_di , + m68k_op_move_8_al_di , + m68k_op_move_8_al_di , + m68k_op_move_8_al_di , + m68k_op_move_8_al_di , + m68k_op_move_8_al_di , + m68k_op_move_8_al_di , + m68k_op_move_8_al_di , + m68k_op_move_8_al_ix , + m68k_op_move_8_al_ix , + m68k_op_move_8_al_ix , + m68k_op_move_8_al_ix , + m68k_op_move_8_al_ix , + m68k_op_move_8_al_ix , + m68k_op_move_8_al_ix , + m68k_op_move_8_al_ix , + m68k_op_move_8_al_aw , + m68k_op_move_8_al_al , + m68k_op_move_8_al_pcdi , + m68k_op_move_8_al_pcix , + m68k_op_move_8_al_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi7 , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd7 , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_aw , + m68k_op_move_8_d_al , + m68k_op_move_8_d_pcdi , + m68k_op_move_8_d_pcix , + m68k_op_move_8_d_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + 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m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_move_8_ai_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi7 , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd7 , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_aw , + m68k_op_move_8_ai_al , + m68k_op_move_8_ai_pcdi , + m68k_op_move_8_ai_pcix , + m68k_op_move_8_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi7 , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd7 , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_aw , + m68k_op_move_8_pi_al , + m68k_op_move_8_pi_pcdi , + m68k_op_move_8_pi_pcix , + m68k_op_move_8_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi7 , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd7 , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_aw , + m68k_op_move_8_pd_al , + m68k_op_move_8_pd_pcdi , + m68k_op_move_8_pd_pcix , + m68k_op_move_8_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi7 , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd7 , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_aw , + m68k_op_move_8_di_al , + m68k_op_move_8_di_pcdi , + m68k_op_move_8_di_pcix , + m68k_op_move_8_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi7 , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd7 , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_aw , + m68k_op_move_8_ix_al , + m68k_op_move_8_ix_pcdi , + m68k_op_move_8_ix_pcix , + m68k_op_move_8_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi7 , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd7 , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di 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m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_ai , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi , + m68k_op_move_8_ai_pi7 , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd , + m68k_op_move_8_ai_pd7 , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_aw , + m68k_op_move_8_ai_al , + m68k_op_move_8_ai_pcdi , + m68k_op_move_8_ai_pcix , + m68k_op_move_8_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi7 , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd7 , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_aw , + m68k_op_move_8_pi_al , + m68k_op_move_8_pi_pcdi , + m68k_op_move_8_pi_pcix , + m68k_op_move_8_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi7 , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd7 , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_aw , + m68k_op_move_8_pd_al , + m68k_op_move_8_pd_pcdi , + m68k_op_move_8_pd_pcix , + m68k_op_move_8_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi7 , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd7 , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_aw , + m68k_op_move_8_di_al , + m68k_op_move_8_di_pcdi , + m68k_op_move_8_di_pcix , + m68k_op_move_8_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi7 , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd7 , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_aw , + m68k_op_move_8_ix_al , + m68k_op_move_8_ix_pcdi , + m68k_op_move_8_ix_pcix , + m68k_op_move_8_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi7 , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd7 , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_aw , + m68k_op_move_8_d_al , + m68k_op_move_8_d_pcdi , + m68k_op_move_8_d_pcix , + m68k_op_move_8_d_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + 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m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi7 , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd7 , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_aw , + m68k_op_move_8_pi_al , + m68k_op_move_8_pi_pcdi , + m68k_op_move_8_pi_pcix , + m68k_op_move_8_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai 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m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi7 , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd7 , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_aw , + m68k_op_move_8_di_al , + m68k_op_move_8_di_pcdi , + m68k_op_move_8_di_pcix , + m68k_op_move_8_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai 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m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_di , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_aw , + m68k_op_move_8_ai_al , + m68k_op_move_8_ai_pcdi , + m68k_op_move_8_ai_pcix , + m68k_op_move_8_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi7 , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd7 , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_aw , + m68k_op_move_8_pi_al , + m68k_op_move_8_pi_pcdi , + m68k_op_move_8_pi_pcix , + m68k_op_move_8_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi7 , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd7 , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_aw , + m68k_op_move_8_pd_al , + m68k_op_move_8_pd_pcdi , + m68k_op_move_8_pd_pcix , + m68k_op_move_8_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_move_8_di_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_ai , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi , + m68k_op_move_8_di_pi7 , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd7 , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_aw , + m68k_op_move_8_di_al , + m68k_op_move_8_di_pcdi , + m68k_op_move_8_di_pcix , + m68k_op_move_8_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi7 , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd7 , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_aw , + m68k_op_move_8_ix_al , + m68k_op_move_8_ix_pcdi , + m68k_op_move_8_ix_pcix , + m68k_op_move_8_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_move_8_d_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_ai , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi , + m68k_op_move_8_d_pi7 , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd , + m68k_op_move_8_d_pd7 , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_di , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_ix , + m68k_op_move_8_d_aw , + m68k_op_move_8_d_al , + m68k_op_move_8_d_pcdi , + m68k_op_move_8_d_pcix , + m68k_op_move_8_d_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + 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m68k_op_move_8_ai_ix , + m68k_op_move_8_ai_aw , + m68k_op_move_8_ai_al , + m68k_op_move_8_ai_pcdi , + m68k_op_move_8_ai_pcix , + m68k_op_move_8_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_move_8_pi_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_ai , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi , + m68k_op_move_8_pi_pi7 , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd , + m68k_op_move_8_pi_pd7 , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_di , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_ix , + m68k_op_move_8_pi_aw , + m68k_op_move_8_pi_al , + m68k_op_move_8_pi_pcdi , + m68k_op_move_8_pi_pcix , + m68k_op_move_8_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_move_8_pd_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_ai , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi , + m68k_op_move_8_pd_pi7 , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd , + m68k_op_move_8_pd_pd7 , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_di , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + m68k_op_move_8_pd_ix , + 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, + m68k_op_move_8_di_pi7 , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd , + m68k_op_move_8_di_pd7 , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_di , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_ix , + m68k_op_move_8_di_aw , + m68k_op_move_8_di_al , + m68k_op_move_8_di_pcdi , + m68k_op_move_8_di_pcix , + m68k_op_move_8_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_move_8_ix_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_ai , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi , + m68k_op_move_8_ix_pi7 , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd , + m68k_op_move_8_ix_pd7 , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_di , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_ix , + m68k_op_move_8_ix_aw , + m68k_op_move_8_ix_al , + m68k_op_move_8_ix_pcdi , + m68k_op_move_8_ix_pcix , + m68k_op_move_8_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + 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m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_aw , + m68k_op_movea_32_al , + m68k_op_movea_32_pcdi , + m68k_op_movea_32_pcix , + m68k_op_movea_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_aw , + m68k_op_move_32_ai_al , + m68k_op_move_32_ai_pcdi , + m68k_op_move_32_ai_pcix , + m68k_op_move_32_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_aw , + m68k_op_move_32_pi_al , + m68k_op_move_32_pi_pcdi , + m68k_op_move_32_pi_pcix , + m68k_op_move_32_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_aw , + m68k_op_move_32_pd_al , + m68k_op_move_32_pd_pcdi , + m68k_op_move_32_pd_pcix , + m68k_op_move_32_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_aw , + m68k_op_move_32_di_al , + m68k_op_move_32_di_pcdi , + m68k_op_move_32_di_pcix , + m68k_op_move_32_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_aw , + m68k_op_move_32_ix_al , + m68k_op_move_32_ix_pcdi , + m68k_op_move_32_ix_pcix , + m68k_op_move_32_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_aw_d , + m68k_op_move_32_aw_d , + m68k_op_move_32_aw_d , + m68k_op_move_32_aw_d , + m68k_op_move_32_aw_d , + m68k_op_move_32_aw_d , + m68k_op_move_32_aw_d , + m68k_op_move_32_aw_d , + m68k_op_move_32_aw_a , + m68k_op_move_32_aw_a , + m68k_op_move_32_aw_a , + m68k_op_move_32_aw_a , + m68k_op_move_32_aw_a , + m68k_op_move_32_aw_a , + m68k_op_move_32_aw_a , + m68k_op_move_32_aw_a , + m68k_op_move_32_aw_ai , + m68k_op_move_32_aw_ai , + m68k_op_move_32_aw_ai , + m68k_op_move_32_aw_ai , + m68k_op_move_32_aw_ai , + m68k_op_move_32_aw_ai , + m68k_op_move_32_aw_ai , + m68k_op_move_32_aw_ai , + m68k_op_move_32_aw_pi , + m68k_op_move_32_aw_pi , + m68k_op_move_32_aw_pi , + m68k_op_move_32_aw_pi , + m68k_op_move_32_aw_pi , + m68k_op_move_32_aw_pi , + m68k_op_move_32_aw_pi , + m68k_op_move_32_aw_pi , + m68k_op_move_32_aw_pd , + m68k_op_move_32_aw_pd , + m68k_op_move_32_aw_pd , + m68k_op_move_32_aw_pd , + m68k_op_move_32_aw_pd , + m68k_op_move_32_aw_pd , + m68k_op_move_32_aw_pd , + m68k_op_move_32_aw_pd , + m68k_op_move_32_aw_di , + m68k_op_move_32_aw_di , + m68k_op_move_32_aw_di , + m68k_op_move_32_aw_di , + m68k_op_move_32_aw_di , + m68k_op_move_32_aw_di , + m68k_op_move_32_aw_di , + m68k_op_move_32_aw_di , + m68k_op_move_32_aw_ix , + m68k_op_move_32_aw_ix , + m68k_op_move_32_aw_ix , + m68k_op_move_32_aw_ix , + m68k_op_move_32_aw_ix , + m68k_op_move_32_aw_ix , + m68k_op_move_32_aw_ix , + m68k_op_move_32_aw_ix , + m68k_op_move_32_aw_aw , + m68k_op_move_32_aw_al , + m68k_op_move_32_aw_pcdi , + m68k_op_move_32_aw_pcix , + m68k_op_move_32_aw_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_aw , + m68k_op_move_32_d_al , + m68k_op_move_32_d_pcdi , + m68k_op_move_32_d_pcix , + m68k_op_move_32_d_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_aw , + m68k_op_movea_32_al , + m68k_op_movea_32_pcdi , + m68k_op_movea_32_pcix , + m68k_op_movea_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai 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m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_aw , + m68k_op_movea_32_al , + m68k_op_movea_32_pcdi , + m68k_op_movea_32_pcix , + m68k_op_movea_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_aw , + m68k_op_move_32_ai_al , + m68k_op_move_32_ai_pcdi , + m68k_op_move_32_ai_pcix , + m68k_op_move_32_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_aw , + m68k_op_move_32_pi_al , + m68k_op_move_32_pi_pcdi , + m68k_op_move_32_pi_pcix , + m68k_op_move_32_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_aw , + m68k_op_move_32_pd_al , + m68k_op_move_32_pd_pcdi , + m68k_op_move_32_pd_pcix , + m68k_op_move_32_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_aw , + m68k_op_move_32_di_al , + m68k_op_move_32_di_pcdi , + m68k_op_move_32_di_pcix , + m68k_op_move_32_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_aw , + m68k_op_move_32_ix_al , + m68k_op_move_32_ix_pcdi , + m68k_op_move_32_ix_pcix , + m68k_op_move_32_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_aw , + m68k_op_move_32_d_al , + m68k_op_move_32_d_pcdi , + m68k_op_move_32_d_pcix , + m68k_op_move_32_d_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_aw , + m68k_op_movea_32_al , + m68k_op_movea_32_pcdi , + m68k_op_movea_32_pcix , + m68k_op_movea_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_aw , + m68k_op_move_32_ai_al , + m68k_op_move_32_ai_pcdi , + m68k_op_move_32_ai_pcix , + m68k_op_move_32_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_aw , + m68k_op_move_32_pi_al , + m68k_op_move_32_pi_pcdi , + m68k_op_move_32_pi_pcix , + m68k_op_move_32_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_aw , + m68k_op_move_32_pd_al , + m68k_op_move_32_pd_pcdi , + m68k_op_move_32_pd_pcix , + m68k_op_move_32_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_aw , + m68k_op_move_32_di_al , + m68k_op_move_32_di_pcdi , + m68k_op_move_32_di_pcix , + m68k_op_move_32_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_aw , + m68k_op_move_32_ix_al , + m68k_op_move_32_ix_pcdi , + m68k_op_move_32_ix_pcix , + m68k_op_move_32_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + 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m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_aw , + m68k_op_movea_32_al , + m68k_op_movea_32_pcdi , + m68k_op_movea_32_pcix , + m68k_op_movea_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_aw , + m68k_op_move_32_ai_al , + m68k_op_move_32_ai_pcdi , + m68k_op_move_32_ai_pcix , + m68k_op_move_32_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_aw , + m68k_op_move_32_pi_al , + m68k_op_move_32_pi_pcdi , + m68k_op_move_32_pi_pcix , + m68k_op_move_32_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_aw , + m68k_op_move_32_pd_al , + m68k_op_move_32_pd_pcdi , + m68k_op_move_32_pd_pcix , + m68k_op_move_32_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_aw , + m68k_op_move_32_di_al , + m68k_op_move_32_di_pcdi , + m68k_op_move_32_di_pcix , + m68k_op_move_32_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd 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m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_aw , + m68k_op_move_32_d_al , + m68k_op_move_32_d_pcdi , + m68k_op_move_32_d_pcix , + m68k_op_move_32_d_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_aw , + m68k_op_movea_32_al , + m68k_op_movea_32_pcdi , + m68k_op_movea_32_pcix , + m68k_op_movea_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_aw , + m68k_op_move_32_ai_al , + m68k_op_move_32_ai_pcdi , + m68k_op_move_32_ai_pcix , + m68k_op_move_32_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_aw , + m68k_op_move_32_pi_al , + m68k_op_move_32_pi_pcdi , + m68k_op_move_32_pi_pcix , + m68k_op_move_32_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_aw , + m68k_op_move_32_pd_al , + m68k_op_move_32_pd_pcdi , + m68k_op_move_32_pd_pcix , + m68k_op_move_32_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_aw , + m68k_op_move_32_di_al , + m68k_op_move_32_di_pcdi , + m68k_op_move_32_di_pcix , + m68k_op_move_32_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + 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m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_aw , + m68k_op_move_32_d_al , + m68k_op_move_32_d_pcdi , + m68k_op_move_32_d_pcix , + m68k_op_move_32_d_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_aw , + m68k_op_movea_32_al , + m68k_op_movea_32_pcdi , + m68k_op_movea_32_pcix , + m68k_op_movea_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_aw , + m68k_op_move_32_ai_al , + m68k_op_move_32_ai_pcdi , + m68k_op_move_32_ai_pcix , + m68k_op_move_32_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_aw , + m68k_op_move_32_pi_al , + m68k_op_move_32_pi_pcdi , + m68k_op_move_32_pi_pcix , + m68k_op_move_32_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_aw , + m68k_op_move_32_pd_al , + m68k_op_move_32_pd_pcdi , + m68k_op_move_32_pd_pcix , + m68k_op_move_32_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_aw , + m68k_op_move_32_di_al , + m68k_op_move_32_di_pcdi , + m68k_op_move_32_di_pcix , + m68k_op_move_32_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_a , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_ai , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pi , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_pd , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_di , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_ix , + m68k_op_move_32_ix_aw , + m68k_op_move_32_ix_al , + m68k_op_move_32_ix_pcdi , + m68k_op_move_32_ix_pcix , + m68k_op_move_32_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + 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m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_d , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_a , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_ai , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pi , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_pd , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_di , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_ix , + m68k_op_move_32_d_aw , + m68k_op_move_32_d_al , + m68k_op_move_32_d_pcdi , + m68k_op_move_32_d_pcix , + m68k_op_move_32_d_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_d , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_a , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_ai , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pi , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_pd , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_di , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_ix , + m68k_op_movea_32_aw , + m68k_op_movea_32_al , + m68k_op_movea_32_pcdi , + m68k_op_movea_32_pcix , + m68k_op_movea_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_d , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_a , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_ai , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pi , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_pd , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_di , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_ix , + m68k_op_move_32_ai_aw , + m68k_op_move_32_ai_al , + m68k_op_move_32_ai_pcdi , + m68k_op_move_32_ai_pcix , + m68k_op_move_32_ai_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_d , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_a , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_ai , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pi , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_pd , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_di , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_ix , + m68k_op_move_32_pi_aw , + m68k_op_move_32_pi_al , + m68k_op_move_32_pi_pcdi , + m68k_op_move_32_pi_pcix , + m68k_op_move_32_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_d , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_a , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_ai , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pi , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_pd , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_di , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_ix , + m68k_op_move_32_pd_aw , + m68k_op_move_32_pd_al , + m68k_op_move_32_pd_pcdi , + m68k_op_move_32_pd_pcix , + m68k_op_move_32_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_d , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_a , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_ai , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pi , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_pd , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_di , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_ix , + m68k_op_move_32_di_aw , + m68k_op_move_32_di_al , + m68k_op_move_32_di_pcdi , + m68k_op_move_32_di_pcix , + m68k_op_move_32_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + m68k_op_move_32_ix_d , + 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m68k_op_move_16_pi_pi , + m68k_op_move_16_pi_pd , + m68k_op_move_16_pi_pd , + m68k_op_move_16_pi_pd , + m68k_op_move_16_pi_pd , + m68k_op_move_16_pi_pd , + m68k_op_move_16_pi_pd , + m68k_op_move_16_pi_pd , + m68k_op_move_16_pi_pd , + m68k_op_move_16_pi_di , + m68k_op_move_16_pi_di , + m68k_op_move_16_pi_di , + m68k_op_move_16_pi_di , + m68k_op_move_16_pi_di , + m68k_op_move_16_pi_di , + m68k_op_move_16_pi_di , + m68k_op_move_16_pi_di , + m68k_op_move_16_pi_ix , + m68k_op_move_16_pi_ix , + m68k_op_move_16_pi_ix , + m68k_op_move_16_pi_ix , + m68k_op_move_16_pi_ix , + m68k_op_move_16_pi_ix , + m68k_op_move_16_pi_ix , + m68k_op_move_16_pi_ix , + m68k_op_move_16_pi_aw , + m68k_op_move_16_pi_al , + m68k_op_move_16_pi_pcdi , + m68k_op_move_16_pi_pcix , + m68k_op_move_16_pi_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_pd_d , + m68k_op_move_16_pd_d , + m68k_op_move_16_pd_d , + m68k_op_move_16_pd_d , + m68k_op_move_16_pd_d , + m68k_op_move_16_pd_d , + m68k_op_move_16_pd_d , + m68k_op_move_16_pd_d , + m68k_op_move_16_pd_a , + m68k_op_move_16_pd_a , + m68k_op_move_16_pd_a , + m68k_op_move_16_pd_a , + m68k_op_move_16_pd_a , + m68k_op_move_16_pd_a , + m68k_op_move_16_pd_a , + m68k_op_move_16_pd_a , + m68k_op_move_16_pd_ai , + m68k_op_move_16_pd_ai , + m68k_op_move_16_pd_ai , + m68k_op_move_16_pd_ai , + m68k_op_move_16_pd_ai , + m68k_op_move_16_pd_ai , + m68k_op_move_16_pd_ai , + m68k_op_move_16_pd_ai , + m68k_op_move_16_pd_pi , + m68k_op_move_16_pd_pi , + m68k_op_move_16_pd_pi , + m68k_op_move_16_pd_pi , + m68k_op_move_16_pd_pi , + m68k_op_move_16_pd_pi , + m68k_op_move_16_pd_pi , + m68k_op_move_16_pd_pi , + m68k_op_move_16_pd_pd , + m68k_op_move_16_pd_pd , + m68k_op_move_16_pd_pd , + m68k_op_move_16_pd_pd , + m68k_op_move_16_pd_pd , + m68k_op_move_16_pd_pd , + m68k_op_move_16_pd_pd , + m68k_op_move_16_pd_pd , + m68k_op_move_16_pd_di , + m68k_op_move_16_pd_di , + m68k_op_move_16_pd_di , + m68k_op_move_16_pd_di , + m68k_op_move_16_pd_di , + m68k_op_move_16_pd_di , + m68k_op_move_16_pd_di , + m68k_op_move_16_pd_di , + m68k_op_move_16_pd_ix , + m68k_op_move_16_pd_ix , + m68k_op_move_16_pd_ix , + m68k_op_move_16_pd_ix , + m68k_op_move_16_pd_ix , + m68k_op_move_16_pd_ix , + m68k_op_move_16_pd_ix , + m68k_op_move_16_pd_ix , + m68k_op_move_16_pd_aw , + m68k_op_move_16_pd_al , + m68k_op_move_16_pd_pcdi , + m68k_op_move_16_pd_pcix , + m68k_op_move_16_pd_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_di_d , + m68k_op_move_16_di_d , + m68k_op_move_16_di_d , + m68k_op_move_16_di_d , + m68k_op_move_16_di_d , + m68k_op_move_16_di_d , + m68k_op_move_16_di_d , + m68k_op_move_16_di_d , + m68k_op_move_16_di_a , + m68k_op_move_16_di_a , + m68k_op_move_16_di_a , + m68k_op_move_16_di_a , + m68k_op_move_16_di_a , + m68k_op_move_16_di_a , + m68k_op_move_16_di_a , + m68k_op_move_16_di_a , + m68k_op_move_16_di_ai , + m68k_op_move_16_di_ai , + m68k_op_move_16_di_ai , + m68k_op_move_16_di_ai , + m68k_op_move_16_di_ai , + m68k_op_move_16_di_ai , + m68k_op_move_16_di_ai , + m68k_op_move_16_di_ai , + m68k_op_move_16_di_pi , + m68k_op_move_16_di_pi , + m68k_op_move_16_di_pi , + m68k_op_move_16_di_pi , + m68k_op_move_16_di_pi , + m68k_op_move_16_di_pi , + m68k_op_move_16_di_pi , + m68k_op_move_16_di_pi , + m68k_op_move_16_di_pd , + m68k_op_move_16_di_pd , + m68k_op_move_16_di_pd , + m68k_op_move_16_di_pd , + m68k_op_move_16_di_pd , + m68k_op_move_16_di_pd , + m68k_op_move_16_di_pd , + m68k_op_move_16_di_pd , + m68k_op_move_16_di_di , + m68k_op_move_16_di_di , + m68k_op_move_16_di_di , + m68k_op_move_16_di_di , + m68k_op_move_16_di_di , + m68k_op_move_16_di_di , + m68k_op_move_16_di_di , + m68k_op_move_16_di_di , + m68k_op_move_16_di_ix , + m68k_op_move_16_di_ix , + m68k_op_move_16_di_ix , + m68k_op_move_16_di_ix , + m68k_op_move_16_di_ix , + m68k_op_move_16_di_ix , + m68k_op_move_16_di_ix , + m68k_op_move_16_di_ix , + m68k_op_move_16_di_aw , + m68k_op_move_16_di_al , + m68k_op_move_16_di_pcdi , + m68k_op_move_16_di_pcix , + m68k_op_move_16_di_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_ix_d , + m68k_op_move_16_ix_d , + m68k_op_move_16_ix_d , + m68k_op_move_16_ix_d , + m68k_op_move_16_ix_d , + m68k_op_move_16_ix_d , + m68k_op_move_16_ix_d , + m68k_op_move_16_ix_d , + m68k_op_move_16_ix_a , + m68k_op_move_16_ix_a , + m68k_op_move_16_ix_a , + m68k_op_move_16_ix_a , + m68k_op_move_16_ix_a , + m68k_op_move_16_ix_a , + m68k_op_move_16_ix_a , + m68k_op_move_16_ix_a , + m68k_op_move_16_ix_ai , + m68k_op_move_16_ix_ai , + m68k_op_move_16_ix_ai , + m68k_op_move_16_ix_ai , + m68k_op_move_16_ix_ai , + m68k_op_move_16_ix_ai , + m68k_op_move_16_ix_ai , + m68k_op_move_16_ix_ai , + m68k_op_move_16_ix_pi , + m68k_op_move_16_ix_pi , + m68k_op_move_16_ix_pi , + m68k_op_move_16_ix_pi , + m68k_op_move_16_ix_pi , + m68k_op_move_16_ix_pi , + m68k_op_move_16_ix_pi , + m68k_op_move_16_ix_pi , + m68k_op_move_16_ix_pd , + m68k_op_move_16_ix_pd , + m68k_op_move_16_ix_pd , + m68k_op_move_16_ix_pd , + m68k_op_move_16_ix_pd , + m68k_op_move_16_ix_pd , + m68k_op_move_16_ix_pd , + m68k_op_move_16_ix_pd , + m68k_op_move_16_ix_di , + m68k_op_move_16_ix_di , + m68k_op_move_16_ix_di , + m68k_op_move_16_ix_di , + m68k_op_move_16_ix_di , + m68k_op_move_16_ix_di , + m68k_op_move_16_ix_di , + m68k_op_move_16_ix_di , + m68k_op_move_16_ix_ix , + m68k_op_move_16_ix_ix , + m68k_op_move_16_ix_ix , + m68k_op_move_16_ix_ix , + m68k_op_move_16_ix_ix , + m68k_op_move_16_ix_ix , + m68k_op_move_16_ix_ix , + m68k_op_move_16_ix_ix , + m68k_op_move_16_ix_aw , + m68k_op_move_16_ix_al , + m68k_op_move_16_ix_pcdi , + m68k_op_move_16_ix_pcix , + m68k_op_move_16_ix_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_negx_8_d , + m68k_op_negx_8_d , + m68k_op_negx_8_d , + m68k_op_negx_8_d , + m68k_op_negx_8_d , + m68k_op_negx_8_d , + m68k_op_negx_8_d , + m68k_op_negx_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_negx_8_ai , + m68k_op_negx_8_ai , + m68k_op_negx_8_ai , + m68k_op_negx_8_ai , + m68k_op_negx_8_ai , + m68k_op_negx_8_ai , + m68k_op_negx_8_ai , + m68k_op_negx_8_ai , + m68k_op_negx_8_pi , + m68k_op_negx_8_pi , + m68k_op_negx_8_pi , + m68k_op_negx_8_pi , + m68k_op_negx_8_pi , + m68k_op_negx_8_pi , + m68k_op_negx_8_pi , + m68k_op_negx_8_pi7 , + m68k_op_negx_8_pd , + m68k_op_negx_8_pd , + m68k_op_negx_8_pd , + m68k_op_negx_8_pd , + m68k_op_negx_8_pd , + m68k_op_negx_8_pd , + m68k_op_negx_8_pd , + m68k_op_negx_8_pd7 , + m68k_op_negx_8_di , + m68k_op_negx_8_di , + m68k_op_negx_8_di , + m68k_op_negx_8_di , + m68k_op_negx_8_di , + m68k_op_negx_8_di , + m68k_op_negx_8_di , + m68k_op_negx_8_di , + m68k_op_negx_8_ix , + m68k_op_negx_8_ix , + m68k_op_negx_8_ix , + m68k_op_negx_8_ix , + m68k_op_negx_8_ix , + m68k_op_negx_8_ix , + m68k_op_negx_8_ix , + m68k_op_negx_8_ix , + m68k_op_negx_8_aw , + m68k_op_negx_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_negx_16_d , + m68k_op_negx_16_d , + m68k_op_negx_16_d , + m68k_op_negx_16_d , + m68k_op_negx_16_d , + m68k_op_negx_16_d , + m68k_op_negx_16_d , + m68k_op_negx_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_negx_16_ai , + m68k_op_negx_16_ai , + m68k_op_negx_16_ai , + m68k_op_negx_16_ai , + m68k_op_negx_16_ai , + m68k_op_negx_16_ai , + m68k_op_negx_16_ai , + m68k_op_negx_16_ai , + m68k_op_negx_16_pi , + m68k_op_negx_16_pi , + m68k_op_negx_16_pi , + m68k_op_negx_16_pi , + m68k_op_negx_16_pi , + m68k_op_negx_16_pi , + m68k_op_negx_16_pi , + m68k_op_negx_16_pi , + m68k_op_negx_16_pd , + m68k_op_negx_16_pd , + m68k_op_negx_16_pd , + m68k_op_negx_16_pd , + m68k_op_negx_16_pd , + m68k_op_negx_16_pd , + m68k_op_negx_16_pd , + m68k_op_negx_16_pd , + m68k_op_negx_16_di , + m68k_op_negx_16_di , + m68k_op_negx_16_di , + m68k_op_negx_16_di , + m68k_op_negx_16_di , + m68k_op_negx_16_di , + m68k_op_negx_16_di , + m68k_op_negx_16_di , + m68k_op_negx_16_ix , + m68k_op_negx_16_ix , + m68k_op_negx_16_ix , + m68k_op_negx_16_ix , + m68k_op_negx_16_ix , + m68k_op_negx_16_ix , + m68k_op_negx_16_ix , + m68k_op_negx_16_ix , + m68k_op_negx_16_aw , + m68k_op_negx_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_negx_32_d , + m68k_op_negx_32_d , + m68k_op_negx_32_d , + m68k_op_negx_32_d , + m68k_op_negx_32_d , + m68k_op_negx_32_d , + m68k_op_negx_32_d , + m68k_op_negx_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_negx_32_ai , + m68k_op_negx_32_ai , + m68k_op_negx_32_ai , + m68k_op_negx_32_ai , + m68k_op_negx_32_ai , + m68k_op_negx_32_ai , + m68k_op_negx_32_ai , + m68k_op_negx_32_ai , + m68k_op_negx_32_pi , + m68k_op_negx_32_pi , + m68k_op_negx_32_pi , + m68k_op_negx_32_pi , + m68k_op_negx_32_pi , + m68k_op_negx_32_pi , + m68k_op_negx_32_pi , + m68k_op_negx_32_pi , + m68k_op_negx_32_pd , + m68k_op_negx_32_pd , + m68k_op_negx_32_pd , + m68k_op_negx_32_pd , + m68k_op_negx_32_pd , + m68k_op_negx_32_pd , + m68k_op_negx_32_pd , + m68k_op_negx_32_pd , + m68k_op_negx_32_di , + m68k_op_negx_32_di , + m68k_op_negx_32_di , + m68k_op_negx_32_di , + m68k_op_negx_32_di , + m68k_op_negx_32_di , + m68k_op_negx_32_di , + m68k_op_negx_32_di , + m68k_op_negx_32_ix , + m68k_op_negx_32_ix , + m68k_op_negx_32_ix , + m68k_op_negx_32_ix , + m68k_op_negx_32_ix , + m68k_op_negx_32_ix , + m68k_op_negx_32_ix , + m68k_op_negx_32_ix , + m68k_op_negx_32_aw , + m68k_op_negx_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_frs_d , + m68k_op_move_16_frs_d , + m68k_op_move_16_frs_d , + m68k_op_move_16_frs_d , + m68k_op_move_16_frs_d , + m68k_op_move_16_frs_d , + m68k_op_move_16_frs_d , + m68k_op_move_16_frs_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_frs_ai , + m68k_op_move_16_frs_ai , + m68k_op_move_16_frs_ai , + m68k_op_move_16_frs_ai , + m68k_op_move_16_frs_ai , + m68k_op_move_16_frs_ai , + m68k_op_move_16_frs_ai , + m68k_op_move_16_frs_ai , + m68k_op_move_16_frs_pi , + m68k_op_move_16_frs_pi , + m68k_op_move_16_frs_pi , + m68k_op_move_16_frs_pi , + m68k_op_move_16_frs_pi , + m68k_op_move_16_frs_pi , + m68k_op_move_16_frs_pi , + m68k_op_move_16_frs_pi , + m68k_op_move_16_frs_pd , + m68k_op_move_16_frs_pd , + m68k_op_move_16_frs_pd , + m68k_op_move_16_frs_pd , + m68k_op_move_16_frs_pd , + m68k_op_move_16_frs_pd , + m68k_op_move_16_frs_pd , + m68k_op_move_16_frs_pd , + m68k_op_move_16_frs_di , + m68k_op_move_16_frs_di , + m68k_op_move_16_frs_di , + m68k_op_move_16_frs_di , + m68k_op_move_16_frs_di , + m68k_op_move_16_frs_di , + m68k_op_move_16_frs_di , + m68k_op_move_16_frs_di , + m68k_op_move_16_frs_ix , + m68k_op_move_16_frs_ix , + m68k_op_move_16_frs_ix , + m68k_op_move_16_frs_ix , + m68k_op_move_16_frs_ix , + m68k_op_move_16_frs_ix , + m68k_op_move_16_frs_ix , + m68k_op_move_16_frs_ix , + m68k_op_move_16_frs_aw , + m68k_op_move_16_frs_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_aw , + m68k_op_chk_32_al , + m68k_op_chk_32_pcdi , + m68k_op_chk_32_pcix , + m68k_op_chk_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_aw , + m68k_op_chk_16_al , + m68k_op_chk_16_pcdi , + m68k_op_chk_16_pcix , + m68k_op_chk_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_aw , + m68k_op_lea_32_al , + m68k_op_lea_32_pcdi , + m68k_op_lea_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_clr_8_d , + m68k_op_clr_8_d , + m68k_op_clr_8_d , + m68k_op_clr_8_d , + m68k_op_clr_8_d , + m68k_op_clr_8_d , + m68k_op_clr_8_d , + m68k_op_clr_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_clr_8_ai , + m68k_op_clr_8_ai , + m68k_op_clr_8_ai , + m68k_op_clr_8_ai , + m68k_op_clr_8_ai , + m68k_op_clr_8_ai , + m68k_op_clr_8_ai , + m68k_op_clr_8_ai , + m68k_op_clr_8_pi , + m68k_op_clr_8_pi , + m68k_op_clr_8_pi , + m68k_op_clr_8_pi , + m68k_op_clr_8_pi , + m68k_op_clr_8_pi , + m68k_op_clr_8_pi , + m68k_op_clr_8_pi7 , + m68k_op_clr_8_pd , + m68k_op_clr_8_pd , + m68k_op_clr_8_pd , + m68k_op_clr_8_pd , + m68k_op_clr_8_pd , + m68k_op_clr_8_pd , + m68k_op_clr_8_pd , + m68k_op_clr_8_pd7 , + m68k_op_clr_8_di , + m68k_op_clr_8_di , + m68k_op_clr_8_di , + m68k_op_clr_8_di , + m68k_op_clr_8_di , + m68k_op_clr_8_di , + m68k_op_clr_8_di , + m68k_op_clr_8_di , + m68k_op_clr_8_ix , + m68k_op_clr_8_ix , + m68k_op_clr_8_ix , + m68k_op_clr_8_ix , + m68k_op_clr_8_ix , + m68k_op_clr_8_ix , + m68k_op_clr_8_ix , + m68k_op_clr_8_ix , + m68k_op_clr_8_aw , + m68k_op_clr_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_clr_16_d , + m68k_op_clr_16_d , + m68k_op_clr_16_d , + m68k_op_clr_16_d , + m68k_op_clr_16_d , + m68k_op_clr_16_d , + m68k_op_clr_16_d , + m68k_op_clr_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_clr_16_ai , + m68k_op_clr_16_ai , + m68k_op_clr_16_ai , + m68k_op_clr_16_ai , + m68k_op_clr_16_ai , + m68k_op_clr_16_ai , + m68k_op_clr_16_ai , + m68k_op_clr_16_ai , + m68k_op_clr_16_pi , + m68k_op_clr_16_pi , + m68k_op_clr_16_pi , + m68k_op_clr_16_pi , + m68k_op_clr_16_pi , + m68k_op_clr_16_pi , + m68k_op_clr_16_pi , + m68k_op_clr_16_pi , + m68k_op_clr_16_pd , + m68k_op_clr_16_pd , + m68k_op_clr_16_pd , + m68k_op_clr_16_pd , + m68k_op_clr_16_pd , + m68k_op_clr_16_pd , + m68k_op_clr_16_pd , + m68k_op_clr_16_pd , + m68k_op_clr_16_di , + m68k_op_clr_16_di , + m68k_op_clr_16_di , + m68k_op_clr_16_di , + m68k_op_clr_16_di , + m68k_op_clr_16_di , + m68k_op_clr_16_di , + m68k_op_clr_16_di , + m68k_op_clr_16_ix , + m68k_op_clr_16_ix , + m68k_op_clr_16_ix , + m68k_op_clr_16_ix , + m68k_op_clr_16_ix , + m68k_op_clr_16_ix , + m68k_op_clr_16_ix , + m68k_op_clr_16_ix , + m68k_op_clr_16_aw , + m68k_op_clr_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_clr_32_d , + m68k_op_clr_32_d , + m68k_op_clr_32_d , + m68k_op_clr_32_d , + m68k_op_clr_32_d , + m68k_op_clr_32_d , + m68k_op_clr_32_d , + m68k_op_clr_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_clr_32_ai , + m68k_op_clr_32_ai , + m68k_op_clr_32_ai , + m68k_op_clr_32_ai , + m68k_op_clr_32_ai , + m68k_op_clr_32_ai , + m68k_op_clr_32_ai , + m68k_op_clr_32_ai , + m68k_op_clr_32_pi , + m68k_op_clr_32_pi , + m68k_op_clr_32_pi , + m68k_op_clr_32_pi , + m68k_op_clr_32_pi , + m68k_op_clr_32_pi , + m68k_op_clr_32_pi , + m68k_op_clr_32_pi , + m68k_op_clr_32_pd , + m68k_op_clr_32_pd , + m68k_op_clr_32_pd , + m68k_op_clr_32_pd , + m68k_op_clr_32_pd , + m68k_op_clr_32_pd , + m68k_op_clr_32_pd , + m68k_op_clr_32_pd , + m68k_op_clr_32_di , + m68k_op_clr_32_di , + m68k_op_clr_32_di , + m68k_op_clr_32_di , + m68k_op_clr_32_di , + m68k_op_clr_32_di , + m68k_op_clr_32_di , + m68k_op_clr_32_di , + m68k_op_clr_32_ix , + m68k_op_clr_32_ix , + m68k_op_clr_32_ix , + m68k_op_clr_32_ix , + m68k_op_clr_32_ix , + m68k_op_clr_32_ix , + m68k_op_clr_32_ix , + m68k_op_clr_32_ix , + m68k_op_clr_32_aw , + m68k_op_clr_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_frc_d , + m68k_op_move_16_frc_d , + m68k_op_move_16_frc_d , + m68k_op_move_16_frc_d , + m68k_op_move_16_frc_d , + m68k_op_move_16_frc_d , + m68k_op_move_16_frc_d , + m68k_op_move_16_frc_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_frc_ai , + m68k_op_move_16_frc_ai , + m68k_op_move_16_frc_ai , + m68k_op_move_16_frc_ai , + m68k_op_move_16_frc_ai , + m68k_op_move_16_frc_ai , + m68k_op_move_16_frc_ai , + m68k_op_move_16_frc_ai , + m68k_op_move_16_frc_pi , + m68k_op_move_16_frc_pi , + m68k_op_move_16_frc_pi , + m68k_op_move_16_frc_pi , + m68k_op_move_16_frc_pi , + m68k_op_move_16_frc_pi , + m68k_op_move_16_frc_pi , + m68k_op_move_16_frc_pi , + m68k_op_move_16_frc_pd , + m68k_op_move_16_frc_pd , + m68k_op_move_16_frc_pd , + m68k_op_move_16_frc_pd , + m68k_op_move_16_frc_pd , + m68k_op_move_16_frc_pd , + m68k_op_move_16_frc_pd , + m68k_op_move_16_frc_pd , + m68k_op_move_16_frc_di , + m68k_op_move_16_frc_di , + m68k_op_move_16_frc_di , + m68k_op_move_16_frc_di , + m68k_op_move_16_frc_di , + m68k_op_move_16_frc_di , + m68k_op_move_16_frc_di , + m68k_op_move_16_frc_di , + m68k_op_move_16_frc_ix , + m68k_op_move_16_frc_ix , + m68k_op_move_16_frc_ix , + m68k_op_move_16_frc_ix , + m68k_op_move_16_frc_ix , + m68k_op_move_16_frc_ix , + m68k_op_move_16_frc_ix , + m68k_op_move_16_frc_ix , + m68k_op_move_16_frc_aw , + m68k_op_move_16_frc_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_aw , + m68k_op_chk_32_al , + m68k_op_chk_32_pcdi , + m68k_op_chk_32_pcix , + m68k_op_chk_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_aw , + m68k_op_chk_16_al , + m68k_op_chk_16_pcdi , + m68k_op_chk_16_pcix , + m68k_op_chk_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_aw , + m68k_op_lea_32_al , + m68k_op_lea_32_pcdi , + m68k_op_lea_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_neg_8_d , + m68k_op_neg_8_d , + m68k_op_neg_8_d , + m68k_op_neg_8_d , + m68k_op_neg_8_d , + m68k_op_neg_8_d , + m68k_op_neg_8_d , + m68k_op_neg_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_neg_8_ai , + m68k_op_neg_8_ai , + m68k_op_neg_8_ai , + m68k_op_neg_8_ai , + m68k_op_neg_8_ai , + m68k_op_neg_8_ai , + m68k_op_neg_8_ai , + m68k_op_neg_8_ai , + m68k_op_neg_8_pi , + m68k_op_neg_8_pi , + m68k_op_neg_8_pi , + m68k_op_neg_8_pi , + m68k_op_neg_8_pi , + m68k_op_neg_8_pi , + m68k_op_neg_8_pi , + m68k_op_neg_8_pi7 , + m68k_op_neg_8_pd , + m68k_op_neg_8_pd , + m68k_op_neg_8_pd , + m68k_op_neg_8_pd , + m68k_op_neg_8_pd , + m68k_op_neg_8_pd , + m68k_op_neg_8_pd , + m68k_op_neg_8_pd7 , + m68k_op_neg_8_di , + m68k_op_neg_8_di , + m68k_op_neg_8_di , + m68k_op_neg_8_di , + m68k_op_neg_8_di , + m68k_op_neg_8_di , + m68k_op_neg_8_di , + m68k_op_neg_8_di , + m68k_op_neg_8_ix , + m68k_op_neg_8_ix , + m68k_op_neg_8_ix , + m68k_op_neg_8_ix , + m68k_op_neg_8_ix , + m68k_op_neg_8_ix , + m68k_op_neg_8_ix , + m68k_op_neg_8_ix , + m68k_op_neg_8_aw , + m68k_op_neg_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_neg_16_d , + m68k_op_neg_16_d , + m68k_op_neg_16_d , + m68k_op_neg_16_d , + m68k_op_neg_16_d , + m68k_op_neg_16_d , + m68k_op_neg_16_d , + m68k_op_neg_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_neg_16_ai , + m68k_op_neg_16_ai , + m68k_op_neg_16_ai , + m68k_op_neg_16_ai , + m68k_op_neg_16_ai , + m68k_op_neg_16_ai , + m68k_op_neg_16_ai , + m68k_op_neg_16_ai , + m68k_op_neg_16_pi , + m68k_op_neg_16_pi , + m68k_op_neg_16_pi , + m68k_op_neg_16_pi , + m68k_op_neg_16_pi , + m68k_op_neg_16_pi , + m68k_op_neg_16_pi , + m68k_op_neg_16_pi , + m68k_op_neg_16_pd , + m68k_op_neg_16_pd , + m68k_op_neg_16_pd , + m68k_op_neg_16_pd , + m68k_op_neg_16_pd , + m68k_op_neg_16_pd , + m68k_op_neg_16_pd , + m68k_op_neg_16_pd , + m68k_op_neg_16_di , + m68k_op_neg_16_di , + m68k_op_neg_16_di , + m68k_op_neg_16_di , + m68k_op_neg_16_di , + m68k_op_neg_16_di , + m68k_op_neg_16_di , + m68k_op_neg_16_di , + m68k_op_neg_16_ix , + m68k_op_neg_16_ix , + m68k_op_neg_16_ix , + m68k_op_neg_16_ix , + m68k_op_neg_16_ix , + m68k_op_neg_16_ix , + m68k_op_neg_16_ix , + m68k_op_neg_16_ix , + m68k_op_neg_16_aw , + m68k_op_neg_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_neg_32_d , + m68k_op_neg_32_d , + m68k_op_neg_32_d , + m68k_op_neg_32_d , + m68k_op_neg_32_d , + m68k_op_neg_32_d , + m68k_op_neg_32_d , + m68k_op_neg_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_neg_32_ai , + m68k_op_neg_32_ai , + m68k_op_neg_32_ai , + m68k_op_neg_32_ai , + m68k_op_neg_32_ai , + m68k_op_neg_32_ai , + m68k_op_neg_32_ai , + m68k_op_neg_32_ai , + m68k_op_neg_32_pi , + m68k_op_neg_32_pi , + m68k_op_neg_32_pi , + m68k_op_neg_32_pi , + m68k_op_neg_32_pi , + m68k_op_neg_32_pi , + m68k_op_neg_32_pi , + m68k_op_neg_32_pi , + m68k_op_neg_32_pd , + m68k_op_neg_32_pd , + m68k_op_neg_32_pd , + m68k_op_neg_32_pd , + m68k_op_neg_32_pd , + m68k_op_neg_32_pd , + m68k_op_neg_32_pd , + m68k_op_neg_32_pd , + m68k_op_neg_32_di , + m68k_op_neg_32_di , + m68k_op_neg_32_di , + m68k_op_neg_32_di , + m68k_op_neg_32_di , + m68k_op_neg_32_di , + m68k_op_neg_32_di , + m68k_op_neg_32_di , + m68k_op_neg_32_ix , + m68k_op_neg_32_ix , + m68k_op_neg_32_ix , + m68k_op_neg_32_ix , + m68k_op_neg_32_ix , + m68k_op_neg_32_ix , + m68k_op_neg_32_ix , + m68k_op_neg_32_ix , + m68k_op_neg_32_aw , + m68k_op_neg_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_toc_d , + m68k_op_move_16_toc_d , + m68k_op_move_16_toc_d , + m68k_op_move_16_toc_d , + m68k_op_move_16_toc_d , + m68k_op_move_16_toc_d , + m68k_op_move_16_toc_d , + m68k_op_move_16_toc_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_toc_ai , + m68k_op_move_16_toc_ai , + m68k_op_move_16_toc_ai , + m68k_op_move_16_toc_ai , + m68k_op_move_16_toc_ai , + m68k_op_move_16_toc_ai , + m68k_op_move_16_toc_ai , + m68k_op_move_16_toc_ai , + m68k_op_move_16_toc_pi , + m68k_op_move_16_toc_pi , + m68k_op_move_16_toc_pi , + m68k_op_move_16_toc_pi , + m68k_op_move_16_toc_pi , + m68k_op_move_16_toc_pi , + m68k_op_move_16_toc_pi , + m68k_op_move_16_toc_pi , + m68k_op_move_16_toc_pd , + m68k_op_move_16_toc_pd , + m68k_op_move_16_toc_pd , + m68k_op_move_16_toc_pd , + m68k_op_move_16_toc_pd , + m68k_op_move_16_toc_pd , + m68k_op_move_16_toc_pd , + m68k_op_move_16_toc_pd , + m68k_op_move_16_toc_di , + m68k_op_move_16_toc_di , + m68k_op_move_16_toc_di , + m68k_op_move_16_toc_di , + m68k_op_move_16_toc_di , + m68k_op_move_16_toc_di , + m68k_op_move_16_toc_di , + m68k_op_move_16_toc_di , + m68k_op_move_16_toc_ix , + m68k_op_move_16_toc_ix , + m68k_op_move_16_toc_ix , + m68k_op_move_16_toc_ix , + m68k_op_move_16_toc_ix , + m68k_op_move_16_toc_ix , + m68k_op_move_16_toc_ix , + m68k_op_move_16_toc_ix , + m68k_op_move_16_toc_aw , + m68k_op_move_16_toc_al , + m68k_op_move_16_toc_pcdi , + m68k_op_move_16_toc_pcix , + m68k_op_move_16_toc_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_aw , + m68k_op_chk_32_al , + m68k_op_chk_32_pcdi , + m68k_op_chk_32_pcix , + m68k_op_chk_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_aw , + m68k_op_chk_16_al , + m68k_op_chk_16_pcdi , + m68k_op_chk_16_pcix , + m68k_op_chk_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_aw , + m68k_op_lea_32_al , + m68k_op_lea_32_pcdi , + m68k_op_lea_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_not_8_d , + m68k_op_not_8_d , + m68k_op_not_8_d , + m68k_op_not_8_d , + m68k_op_not_8_d , + m68k_op_not_8_d , + m68k_op_not_8_d , + m68k_op_not_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_not_8_ai , + m68k_op_not_8_ai , + m68k_op_not_8_ai , + m68k_op_not_8_ai , + m68k_op_not_8_ai , + m68k_op_not_8_ai , + m68k_op_not_8_ai , + m68k_op_not_8_ai , + m68k_op_not_8_pi , + m68k_op_not_8_pi , + m68k_op_not_8_pi , + m68k_op_not_8_pi , + m68k_op_not_8_pi , + m68k_op_not_8_pi , + m68k_op_not_8_pi , + m68k_op_not_8_pi7 , + m68k_op_not_8_pd , + m68k_op_not_8_pd , + m68k_op_not_8_pd , + m68k_op_not_8_pd , + m68k_op_not_8_pd , + m68k_op_not_8_pd , + m68k_op_not_8_pd , + m68k_op_not_8_pd7 , + m68k_op_not_8_di , + m68k_op_not_8_di , + m68k_op_not_8_di , + m68k_op_not_8_di , + m68k_op_not_8_di , + m68k_op_not_8_di , + m68k_op_not_8_di , + m68k_op_not_8_di , + m68k_op_not_8_ix , + m68k_op_not_8_ix , + m68k_op_not_8_ix , + m68k_op_not_8_ix , + m68k_op_not_8_ix , + m68k_op_not_8_ix , + m68k_op_not_8_ix , + m68k_op_not_8_ix , + m68k_op_not_8_aw , + m68k_op_not_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_not_16_d , + m68k_op_not_16_d , + m68k_op_not_16_d , + m68k_op_not_16_d , + m68k_op_not_16_d , + m68k_op_not_16_d , + m68k_op_not_16_d , + m68k_op_not_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_not_16_ai , + m68k_op_not_16_ai , + m68k_op_not_16_ai , + m68k_op_not_16_ai , + m68k_op_not_16_ai , + m68k_op_not_16_ai , + m68k_op_not_16_ai , + m68k_op_not_16_ai , + m68k_op_not_16_pi , + m68k_op_not_16_pi , + m68k_op_not_16_pi , + m68k_op_not_16_pi , + m68k_op_not_16_pi , + m68k_op_not_16_pi , + m68k_op_not_16_pi , + m68k_op_not_16_pi , + m68k_op_not_16_pd , + m68k_op_not_16_pd , + m68k_op_not_16_pd , + m68k_op_not_16_pd , + m68k_op_not_16_pd , + m68k_op_not_16_pd , + m68k_op_not_16_pd , + m68k_op_not_16_pd , + m68k_op_not_16_di , + m68k_op_not_16_di , + m68k_op_not_16_di , + m68k_op_not_16_di , + m68k_op_not_16_di , + m68k_op_not_16_di , + m68k_op_not_16_di , + m68k_op_not_16_di , + m68k_op_not_16_ix , + m68k_op_not_16_ix , + m68k_op_not_16_ix , + m68k_op_not_16_ix , + m68k_op_not_16_ix , + m68k_op_not_16_ix , + m68k_op_not_16_ix , + m68k_op_not_16_ix , + m68k_op_not_16_aw , + m68k_op_not_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_not_32_d , + m68k_op_not_32_d , + m68k_op_not_32_d , + m68k_op_not_32_d , + m68k_op_not_32_d , + m68k_op_not_32_d , + m68k_op_not_32_d , + m68k_op_not_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_not_32_ai , + m68k_op_not_32_ai , + m68k_op_not_32_ai , + m68k_op_not_32_ai , + m68k_op_not_32_ai , + m68k_op_not_32_ai , + m68k_op_not_32_ai , + m68k_op_not_32_ai , + m68k_op_not_32_pi , + m68k_op_not_32_pi , + m68k_op_not_32_pi , + m68k_op_not_32_pi , + m68k_op_not_32_pi , + m68k_op_not_32_pi , + m68k_op_not_32_pi , + m68k_op_not_32_pi , + m68k_op_not_32_pd , + m68k_op_not_32_pd , + m68k_op_not_32_pd , + m68k_op_not_32_pd , + m68k_op_not_32_pd , + m68k_op_not_32_pd , + m68k_op_not_32_pd , + m68k_op_not_32_pd , + m68k_op_not_32_di , + m68k_op_not_32_di , + m68k_op_not_32_di , + m68k_op_not_32_di , + m68k_op_not_32_di , + m68k_op_not_32_di , + m68k_op_not_32_di , + m68k_op_not_32_di , + m68k_op_not_32_ix , + m68k_op_not_32_ix , + m68k_op_not_32_ix , + m68k_op_not_32_ix , + m68k_op_not_32_ix , + m68k_op_not_32_ix , + m68k_op_not_32_ix , + m68k_op_not_32_ix , + m68k_op_not_32_aw , + m68k_op_not_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_tos_d , + m68k_op_move_16_tos_d , + m68k_op_move_16_tos_d , + m68k_op_move_16_tos_d , + m68k_op_move_16_tos_d , + m68k_op_move_16_tos_d , + m68k_op_move_16_tos_d , + m68k_op_move_16_tos_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_move_16_tos_ai , + m68k_op_move_16_tos_ai , + m68k_op_move_16_tos_ai , + m68k_op_move_16_tos_ai , + m68k_op_move_16_tos_ai , + m68k_op_move_16_tos_ai , + m68k_op_move_16_tos_ai , + m68k_op_move_16_tos_ai , + m68k_op_move_16_tos_pi , + m68k_op_move_16_tos_pi , + m68k_op_move_16_tos_pi , + m68k_op_move_16_tos_pi , + m68k_op_move_16_tos_pi , + m68k_op_move_16_tos_pi , + m68k_op_move_16_tos_pi , + m68k_op_move_16_tos_pi , + m68k_op_move_16_tos_pd , + m68k_op_move_16_tos_pd , + m68k_op_move_16_tos_pd , + m68k_op_move_16_tos_pd , + m68k_op_move_16_tos_pd , + m68k_op_move_16_tos_pd , + m68k_op_move_16_tos_pd , + m68k_op_move_16_tos_pd , + m68k_op_move_16_tos_di , + m68k_op_move_16_tos_di , + m68k_op_move_16_tos_di , + m68k_op_move_16_tos_di , + m68k_op_move_16_tos_di , + m68k_op_move_16_tos_di , + m68k_op_move_16_tos_di , + m68k_op_move_16_tos_di , + m68k_op_move_16_tos_ix , + m68k_op_move_16_tos_ix , + m68k_op_move_16_tos_ix , + m68k_op_move_16_tos_ix , + m68k_op_move_16_tos_ix , + m68k_op_move_16_tos_ix , + m68k_op_move_16_tos_ix , + m68k_op_move_16_tos_ix , + m68k_op_move_16_tos_aw , + m68k_op_move_16_tos_al , + m68k_op_move_16_tos_pcdi , + m68k_op_move_16_tos_pcix , + m68k_op_move_16_tos_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_aw , + m68k_op_chk_32_al , + m68k_op_chk_32_pcdi , + m68k_op_chk_32_pcix , + m68k_op_chk_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_aw , + m68k_op_chk_16_al , + m68k_op_chk_16_pcdi , + m68k_op_chk_16_pcix , + m68k_op_chk_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_aw , + m68k_op_lea_32_al , + m68k_op_lea_32_pcdi , + m68k_op_lea_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_nbcd_8_d , + m68k_op_nbcd_8_d , + m68k_op_nbcd_8_d , + m68k_op_nbcd_8_d , + m68k_op_nbcd_8_d , + m68k_op_nbcd_8_d , + m68k_op_nbcd_8_d , + m68k_op_nbcd_8_d , + m68k_op_link_32 , + m68k_op_link_32 , + m68k_op_link_32 , + m68k_op_link_32 , + m68k_op_link_32 , + m68k_op_link_32 , + m68k_op_link_32 , + m68k_op_link_32_a7 , + m68k_op_nbcd_8_ai , + m68k_op_nbcd_8_ai , + m68k_op_nbcd_8_ai , + m68k_op_nbcd_8_ai , + m68k_op_nbcd_8_ai , + m68k_op_nbcd_8_ai , + m68k_op_nbcd_8_ai , + m68k_op_nbcd_8_ai , + m68k_op_nbcd_8_pi , + m68k_op_nbcd_8_pi , + m68k_op_nbcd_8_pi , + m68k_op_nbcd_8_pi , + m68k_op_nbcd_8_pi , + m68k_op_nbcd_8_pi , + m68k_op_nbcd_8_pi , + m68k_op_nbcd_8_pi7 , + m68k_op_nbcd_8_pd , + m68k_op_nbcd_8_pd , + m68k_op_nbcd_8_pd , + m68k_op_nbcd_8_pd , + m68k_op_nbcd_8_pd , + m68k_op_nbcd_8_pd , + m68k_op_nbcd_8_pd , + m68k_op_nbcd_8_pd7 , + m68k_op_nbcd_8_di , + m68k_op_nbcd_8_di , + m68k_op_nbcd_8_di , + m68k_op_nbcd_8_di , + m68k_op_nbcd_8_di , + m68k_op_nbcd_8_di , + m68k_op_nbcd_8_di , + m68k_op_nbcd_8_di , + m68k_op_nbcd_8_ix , + m68k_op_nbcd_8_ix , + m68k_op_nbcd_8_ix , + m68k_op_nbcd_8_ix , + m68k_op_nbcd_8_ix , + m68k_op_nbcd_8_ix , + m68k_op_nbcd_8_ix , + m68k_op_nbcd_8_ix , + m68k_op_nbcd_8_aw , + m68k_op_nbcd_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_swap_32 , + m68k_op_swap_32 , + m68k_op_swap_32 , + m68k_op_swap_32 , + m68k_op_swap_32 , + m68k_op_swap_32 , + m68k_op_swap_32 , + m68k_op_swap_32 , + m68k_op_bkpt , + m68k_op_bkpt , + m68k_op_bkpt , + m68k_op_bkpt , + m68k_op_bkpt , + m68k_op_bkpt , + m68k_op_bkpt , + m68k_op_bkpt , + m68k_op_pea_32_ai , + m68k_op_pea_32_ai , + m68k_op_pea_32_ai , + m68k_op_pea_32_ai , + m68k_op_pea_32_ai , + m68k_op_pea_32_ai , + m68k_op_pea_32_ai , + m68k_op_pea_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_pea_32_di , + m68k_op_pea_32_di , + m68k_op_pea_32_di , + m68k_op_pea_32_di , + m68k_op_pea_32_di , + m68k_op_pea_32_di , + m68k_op_pea_32_di , + m68k_op_pea_32_di , + m68k_op_pea_32_ix , + m68k_op_pea_32_ix , + m68k_op_pea_32_ix , + m68k_op_pea_32_ix , + m68k_op_pea_32_ix , + m68k_op_pea_32_ix , + m68k_op_pea_32_ix , + m68k_op_pea_32_ix , + m68k_op_pea_32_aw , + m68k_op_pea_32_al , + m68k_op_pea_32_pcdi , + m68k_op_pea_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ext_16 , + m68k_op_ext_16 , + m68k_op_ext_16 , + m68k_op_ext_16 , + m68k_op_ext_16 , + m68k_op_ext_16 , + m68k_op_ext_16 , + m68k_op_ext_16 , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movem_16_re_ai , + m68k_op_movem_16_re_ai , + m68k_op_movem_16_re_ai , + m68k_op_movem_16_re_ai , + m68k_op_movem_16_re_ai , + m68k_op_movem_16_re_ai , + m68k_op_movem_16_re_ai , + m68k_op_movem_16_re_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movem_16_re_pd , + m68k_op_movem_16_re_pd , + m68k_op_movem_16_re_pd , + m68k_op_movem_16_re_pd , + m68k_op_movem_16_re_pd , + m68k_op_movem_16_re_pd , + m68k_op_movem_16_re_pd , + m68k_op_movem_16_re_pd , + m68k_op_movem_16_re_di , + m68k_op_movem_16_re_di , + m68k_op_movem_16_re_di , + m68k_op_movem_16_re_di , + m68k_op_movem_16_re_di , + m68k_op_movem_16_re_di , + m68k_op_movem_16_re_di , + m68k_op_movem_16_re_di , + m68k_op_movem_16_re_ix , + m68k_op_movem_16_re_ix , + m68k_op_movem_16_re_ix , + m68k_op_movem_16_re_ix , + m68k_op_movem_16_re_ix , + m68k_op_movem_16_re_ix , + m68k_op_movem_16_re_ix , + m68k_op_movem_16_re_ix , + m68k_op_movem_16_re_aw , + m68k_op_movem_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ext_32 , + m68k_op_ext_32 , + m68k_op_ext_32 , + m68k_op_ext_32 , + m68k_op_ext_32 , + m68k_op_ext_32 , + m68k_op_ext_32 , + m68k_op_ext_32 , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movem_32_re_ai , + m68k_op_movem_32_re_ai , + m68k_op_movem_32_re_ai , + m68k_op_movem_32_re_ai , + m68k_op_movem_32_re_ai , + m68k_op_movem_32_re_ai , + m68k_op_movem_32_re_ai , + m68k_op_movem_32_re_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movem_32_re_pd , + m68k_op_movem_32_re_pd , + m68k_op_movem_32_re_pd , + m68k_op_movem_32_re_pd , + m68k_op_movem_32_re_pd , + m68k_op_movem_32_re_pd , + m68k_op_movem_32_re_pd , + m68k_op_movem_32_re_pd , + m68k_op_movem_32_re_di , + m68k_op_movem_32_re_di , + m68k_op_movem_32_re_di , + m68k_op_movem_32_re_di , + m68k_op_movem_32_re_di , + m68k_op_movem_32_re_di , + m68k_op_movem_32_re_di , + m68k_op_movem_32_re_di , + m68k_op_movem_32_re_ix , + m68k_op_movem_32_re_ix , + m68k_op_movem_32_re_ix , + m68k_op_movem_32_re_ix , + m68k_op_movem_32_re_ix , + m68k_op_movem_32_re_ix , + m68k_op_movem_32_re_ix , + m68k_op_movem_32_re_ix , + m68k_op_movem_32_re_aw , + m68k_op_movem_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_aw , + m68k_op_chk_32_al , + m68k_op_chk_32_pcdi , + m68k_op_chk_32_pcix , + m68k_op_chk_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_aw , + m68k_op_chk_16_al , + m68k_op_chk_16_pcdi , + m68k_op_chk_16_pcix , + m68k_op_chk_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_extb_32 , + m68k_op_extb_32 , + m68k_op_extb_32 , + m68k_op_extb_32 , + m68k_op_extb_32 , + m68k_op_extb_32 , + m68k_op_extb_32 , + m68k_op_extb_32 , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_aw , + m68k_op_lea_32_al , + m68k_op_lea_32_pcdi , + m68k_op_lea_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_tst_8_d , + m68k_op_tst_8_d , + m68k_op_tst_8_d , + m68k_op_tst_8_d , + m68k_op_tst_8_d , + m68k_op_tst_8_d , + m68k_op_tst_8_d , + m68k_op_tst_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_tst_8_ai , + m68k_op_tst_8_ai , + m68k_op_tst_8_ai , + m68k_op_tst_8_ai , + m68k_op_tst_8_ai , + m68k_op_tst_8_ai , + m68k_op_tst_8_ai , + m68k_op_tst_8_ai , + m68k_op_tst_8_pi , + m68k_op_tst_8_pi , + m68k_op_tst_8_pi , + m68k_op_tst_8_pi , + m68k_op_tst_8_pi , + m68k_op_tst_8_pi , + m68k_op_tst_8_pi , + m68k_op_tst_8_pi7 , + m68k_op_tst_8_pd , + m68k_op_tst_8_pd , + m68k_op_tst_8_pd , + m68k_op_tst_8_pd , + m68k_op_tst_8_pd , + m68k_op_tst_8_pd , + m68k_op_tst_8_pd , + m68k_op_tst_8_pd7 , + m68k_op_tst_8_di , + m68k_op_tst_8_di , + m68k_op_tst_8_di , + m68k_op_tst_8_di , + m68k_op_tst_8_di , + m68k_op_tst_8_di , + m68k_op_tst_8_di , + m68k_op_tst_8_di , + m68k_op_tst_8_ix , + m68k_op_tst_8_ix , + m68k_op_tst_8_ix , + m68k_op_tst_8_ix , + m68k_op_tst_8_ix , + m68k_op_tst_8_ix , + m68k_op_tst_8_ix , + m68k_op_tst_8_ix , + m68k_op_tst_8_aw , + m68k_op_tst_8_al , + m68k_op_tst_8_pcdi , + m68k_op_tst_8_pcix , + m68k_op_tst_8_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_tst_16_d , + m68k_op_tst_16_d , + m68k_op_tst_16_d , + m68k_op_tst_16_d , + m68k_op_tst_16_d , + m68k_op_tst_16_d , + m68k_op_tst_16_d , + m68k_op_tst_16_d , + m68k_op_tst_16_a , + m68k_op_tst_16_a , + m68k_op_tst_16_a , + m68k_op_tst_16_a , + m68k_op_tst_16_a , + m68k_op_tst_16_a , + m68k_op_tst_16_a , + m68k_op_tst_16_a , + m68k_op_tst_16_ai , + m68k_op_tst_16_ai , + m68k_op_tst_16_ai , + m68k_op_tst_16_ai , + m68k_op_tst_16_ai , + m68k_op_tst_16_ai , + m68k_op_tst_16_ai , + m68k_op_tst_16_ai , + m68k_op_tst_16_pi , + m68k_op_tst_16_pi , + m68k_op_tst_16_pi , + m68k_op_tst_16_pi , + m68k_op_tst_16_pi , + m68k_op_tst_16_pi , + m68k_op_tst_16_pi , + m68k_op_tst_16_pi , + m68k_op_tst_16_pd , + m68k_op_tst_16_pd , + m68k_op_tst_16_pd , + m68k_op_tst_16_pd , + m68k_op_tst_16_pd , + m68k_op_tst_16_pd , + m68k_op_tst_16_pd , + m68k_op_tst_16_pd , + m68k_op_tst_16_di , + m68k_op_tst_16_di , + m68k_op_tst_16_di , + m68k_op_tst_16_di , + m68k_op_tst_16_di , + m68k_op_tst_16_di , + m68k_op_tst_16_di , + m68k_op_tst_16_di , + m68k_op_tst_16_ix , + m68k_op_tst_16_ix , + m68k_op_tst_16_ix , + m68k_op_tst_16_ix , + m68k_op_tst_16_ix , + m68k_op_tst_16_ix , + m68k_op_tst_16_ix , + m68k_op_tst_16_ix , + m68k_op_tst_16_aw , + m68k_op_tst_16_al , + m68k_op_tst_16_pcdi , + m68k_op_tst_16_pcix , + m68k_op_tst_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_tst_32_d , + m68k_op_tst_32_d , + m68k_op_tst_32_d , + m68k_op_tst_32_d , + m68k_op_tst_32_d , + m68k_op_tst_32_d , + m68k_op_tst_32_d , + m68k_op_tst_32_d , + m68k_op_tst_32_a , + m68k_op_tst_32_a , + m68k_op_tst_32_a , + m68k_op_tst_32_a , + m68k_op_tst_32_a , + m68k_op_tst_32_a , + m68k_op_tst_32_a , + m68k_op_tst_32_a , + m68k_op_tst_32_ai , + m68k_op_tst_32_ai , + m68k_op_tst_32_ai , + m68k_op_tst_32_ai , + m68k_op_tst_32_ai , + m68k_op_tst_32_ai , + m68k_op_tst_32_ai , + m68k_op_tst_32_ai , + m68k_op_tst_32_pi , + m68k_op_tst_32_pi , + m68k_op_tst_32_pi , + m68k_op_tst_32_pi , + m68k_op_tst_32_pi , + m68k_op_tst_32_pi , + m68k_op_tst_32_pi , + m68k_op_tst_32_pi , + m68k_op_tst_32_pd , + m68k_op_tst_32_pd , + m68k_op_tst_32_pd , + m68k_op_tst_32_pd , + m68k_op_tst_32_pd , + m68k_op_tst_32_pd , + m68k_op_tst_32_pd , + m68k_op_tst_32_pd , + m68k_op_tst_32_di , + m68k_op_tst_32_di , + m68k_op_tst_32_di , + m68k_op_tst_32_di , + m68k_op_tst_32_di , + m68k_op_tst_32_di , + m68k_op_tst_32_di , + m68k_op_tst_32_di , + m68k_op_tst_32_ix , + m68k_op_tst_32_ix , + m68k_op_tst_32_ix , + m68k_op_tst_32_ix , + m68k_op_tst_32_ix , + m68k_op_tst_32_ix , + m68k_op_tst_32_ix , + m68k_op_tst_32_ix , + m68k_op_tst_32_aw , + m68k_op_tst_32_al , + m68k_op_tst_32_pcdi , + m68k_op_tst_32_pcix , + m68k_op_tst_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_tas_8_d , + m68k_op_tas_8_d , + m68k_op_tas_8_d , + m68k_op_tas_8_d , + m68k_op_tas_8_d , + m68k_op_tas_8_d , + m68k_op_tas_8_d , + m68k_op_tas_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_tas_8_ai , + m68k_op_tas_8_ai , + m68k_op_tas_8_ai , + m68k_op_tas_8_ai , + m68k_op_tas_8_ai , + m68k_op_tas_8_ai , + m68k_op_tas_8_ai , + m68k_op_tas_8_ai , + m68k_op_tas_8_pi , + m68k_op_tas_8_pi , + m68k_op_tas_8_pi , + m68k_op_tas_8_pi , + m68k_op_tas_8_pi , + m68k_op_tas_8_pi , + m68k_op_tas_8_pi , + m68k_op_tas_8_pi7 , + m68k_op_tas_8_pd , + m68k_op_tas_8_pd , + m68k_op_tas_8_pd , + m68k_op_tas_8_pd , + m68k_op_tas_8_pd , + m68k_op_tas_8_pd , + m68k_op_tas_8_pd , + m68k_op_tas_8_pd7 , + m68k_op_tas_8_di , + m68k_op_tas_8_di , + m68k_op_tas_8_di , + m68k_op_tas_8_di , + m68k_op_tas_8_di , + m68k_op_tas_8_di , + m68k_op_tas_8_di , + m68k_op_tas_8_di , + m68k_op_tas_8_ix , + m68k_op_tas_8_ix , + m68k_op_tas_8_ix , + m68k_op_tas_8_ix , + m68k_op_tas_8_ix , + m68k_op_tas_8_ix , + m68k_op_tas_8_ix , + m68k_op_tas_8_ix , + m68k_op_tas_8_aw , + m68k_op_tas_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_aw , + m68k_op_chk_32_al , + m68k_op_chk_32_pcdi , + m68k_op_chk_32_pcix , + m68k_op_chk_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_aw , + m68k_op_chk_16_al , + m68k_op_chk_16_pcdi , + m68k_op_chk_16_pcix , + m68k_op_chk_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_aw , + m68k_op_lea_32_al , + m68k_op_lea_32_pcdi , + m68k_op_lea_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mull_32_d , + m68k_op_mull_32_d , + m68k_op_mull_32_d , + m68k_op_mull_32_d , + m68k_op_mull_32_d , + m68k_op_mull_32_d , + m68k_op_mull_32_d , + m68k_op_mull_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mull_32_ai , + m68k_op_mull_32_ai , + m68k_op_mull_32_ai , + m68k_op_mull_32_ai , + m68k_op_mull_32_ai , + m68k_op_mull_32_ai , + m68k_op_mull_32_ai , + m68k_op_mull_32_ai , + m68k_op_mull_32_pi , + m68k_op_mull_32_pi , + m68k_op_mull_32_pi , + m68k_op_mull_32_pi , + m68k_op_mull_32_pi , + m68k_op_mull_32_pi , + m68k_op_mull_32_pi , + m68k_op_mull_32_pi , + m68k_op_mull_32_pd , + m68k_op_mull_32_pd , + m68k_op_mull_32_pd , + m68k_op_mull_32_pd , + m68k_op_mull_32_pd , + m68k_op_mull_32_pd , + m68k_op_mull_32_pd , + m68k_op_mull_32_pd , + m68k_op_mull_32_di , + m68k_op_mull_32_di , + m68k_op_mull_32_di , + m68k_op_mull_32_di , + m68k_op_mull_32_di , + m68k_op_mull_32_di , + m68k_op_mull_32_di , + m68k_op_mull_32_di , + m68k_op_mull_32_ix , + m68k_op_mull_32_ix , + m68k_op_mull_32_ix , + m68k_op_mull_32_ix , + m68k_op_mull_32_ix , + m68k_op_mull_32_ix , + m68k_op_mull_32_ix , + m68k_op_mull_32_ix , + m68k_op_mull_32_aw , + m68k_op_mull_32_al , + m68k_op_mull_32_pcdi , + m68k_op_mull_32_pcix , + m68k_op_mull_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divl_32_d , + m68k_op_divl_32_d , + m68k_op_divl_32_d , + m68k_op_divl_32_d , + m68k_op_divl_32_d , + m68k_op_divl_32_d , + m68k_op_divl_32_d , + m68k_op_divl_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divl_32_ai , + m68k_op_divl_32_ai , + m68k_op_divl_32_ai , + m68k_op_divl_32_ai , + m68k_op_divl_32_ai , + m68k_op_divl_32_ai , + m68k_op_divl_32_ai , + m68k_op_divl_32_ai , + m68k_op_divl_32_pi , + m68k_op_divl_32_pi , + m68k_op_divl_32_pi , + m68k_op_divl_32_pi , + m68k_op_divl_32_pi , + m68k_op_divl_32_pi , + m68k_op_divl_32_pi , + m68k_op_divl_32_pi , + m68k_op_divl_32_pd , + m68k_op_divl_32_pd , + m68k_op_divl_32_pd , + m68k_op_divl_32_pd , + m68k_op_divl_32_pd , + m68k_op_divl_32_pd , + m68k_op_divl_32_pd , + m68k_op_divl_32_pd , + m68k_op_divl_32_di , + m68k_op_divl_32_di , + m68k_op_divl_32_di , + m68k_op_divl_32_di , + m68k_op_divl_32_di , + m68k_op_divl_32_di , + m68k_op_divl_32_di , + m68k_op_divl_32_di , + m68k_op_divl_32_ix , + m68k_op_divl_32_ix , + m68k_op_divl_32_ix , + m68k_op_divl_32_ix , + m68k_op_divl_32_ix , + m68k_op_divl_32_ix , + m68k_op_divl_32_ix , + m68k_op_divl_32_ix , + m68k_op_divl_32_aw , + m68k_op_divl_32_al , + m68k_op_divl_32_pcdi , + m68k_op_divl_32_pcix , + m68k_op_divl_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movem_16_er_ai , + m68k_op_movem_16_er_ai , + m68k_op_movem_16_er_ai , + m68k_op_movem_16_er_ai , + m68k_op_movem_16_er_ai , + m68k_op_movem_16_er_ai , + m68k_op_movem_16_er_ai , + m68k_op_movem_16_er_ai , + m68k_op_movem_16_er_pi , + m68k_op_movem_16_er_pi , + m68k_op_movem_16_er_pi , + m68k_op_movem_16_er_pi , + m68k_op_movem_16_er_pi , + m68k_op_movem_16_er_pi , + m68k_op_movem_16_er_pi , + m68k_op_movem_16_er_pi , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movem_16_er_di , + m68k_op_movem_16_er_di , + m68k_op_movem_16_er_di , + m68k_op_movem_16_er_di , + m68k_op_movem_16_er_di , + m68k_op_movem_16_er_di , + m68k_op_movem_16_er_di , + m68k_op_movem_16_er_di , + m68k_op_movem_16_er_ix , + m68k_op_movem_16_er_ix , + m68k_op_movem_16_er_ix , + m68k_op_movem_16_er_ix , + m68k_op_movem_16_er_ix , + m68k_op_movem_16_er_ix , + m68k_op_movem_16_er_ix , + m68k_op_movem_16_er_ix , + m68k_op_movem_16_er_aw , + m68k_op_movem_16_er_al , + m68k_op_movem_16_er_pcdi , + m68k_op_movem_16_er_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movem_32_er_ai , + m68k_op_movem_32_er_ai , + m68k_op_movem_32_er_ai , + m68k_op_movem_32_er_ai , + m68k_op_movem_32_er_ai , + m68k_op_movem_32_er_ai , + m68k_op_movem_32_er_ai , + m68k_op_movem_32_er_ai , + m68k_op_movem_32_er_pi , + m68k_op_movem_32_er_pi , + m68k_op_movem_32_er_pi , + m68k_op_movem_32_er_pi , + m68k_op_movem_32_er_pi , + m68k_op_movem_32_er_pi , + m68k_op_movem_32_er_pi , + m68k_op_movem_32_er_pi , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movem_32_er_di , + m68k_op_movem_32_er_di , + m68k_op_movem_32_er_di , + m68k_op_movem_32_er_di , + m68k_op_movem_32_er_di , + m68k_op_movem_32_er_di , + m68k_op_movem_32_er_di , + m68k_op_movem_32_er_di , + m68k_op_movem_32_er_ix , + m68k_op_movem_32_er_ix , + m68k_op_movem_32_er_ix , + m68k_op_movem_32_er_ix , + m68k_op_movem_32_er_ix , + m68k_op_movem_32_er_ix , + m68k_op_movem_32_er_ix , + m68k_op_movem_32_er_ix , + m68k_op_movem_32_er_aw , + m68k_op_movem_32_er_al , + m68k_op_movem_32_er_pcdi , + m68k_op_movem_32_er_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_aw , + m68k_op_chk_32_al , + m68k_op_chk_32_pcdi , + m68k_op_chk_32_pcix , + m68k_op_chk_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_aw , + m68k_op_chk_16_al , + m68k_op_chk_16_pcdi , + m68k_op_chk_16_pcix , + m68k_op_chk_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_aw , + m68k_op_lea_32_al , + m68k_op_lea_32_pcdi , + m68k_op_lea_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_trap , + m68k_op_link_16 , + m68k_op_link_16 , + m68k_op_link_16 , + m68k_op_link_16 , + m68k_op_link_16 , + m68k_op_link_16 , + m68k_op_link_16 , + m68k_op_link_16_a7 , + m68k_op_unlk_32 , + m68k_op_unlk_32 , + m68k_op_unlk_32 , + m68k_op_unlk_32 , + m68k_op_unlk_32 , + m68k_op_unlk_32 , + m68k_op_unlk_32 , + m68k_op_unlk_32_a7 , + m68k_op_move_32_tou , + m68k_op_move_32_tou , + m68k_op_move_32_tou , + m68k_op_move_32_tou , + m68k_op_move_32_tou , + m68k_op_move_32_tou , + m68k_op_move_32_tou , + m68k_op_move_32_tou , + m68k_op_move_32_fru , + m68k_op_move_32_fru , + m68k_op_move_32_fru , + m68k_op_move_32_fru , + m68k_op_move_32_fru , + m68k_op_move_32_fru , + m68k_op_move_32_fru , + m68k_op_move_32_fru , + m68k_op_reset , + m68k_op_nop , + m68k_op_stop , + m68k_op_rte_32 , + m68k_op_rtd_32 , + m68k_op_rts_32 , + m68k_op_trapv , + m68k_op_rtr_32 , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_movec_32_cr , + m68k_op_movec_32_rc , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_jsr_32_ai , + m68k_op_jsr_32_ai , + m68k_op_jsr_32_ai , + m68k_op_jsr_32_ai , + m68k_op_jsr_32_ai , + m68k_op_jsr_32_ai , + m68k_op_jsr_32_ai , + m68k_op_jsr_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_jsr_32_di , + m68k_op_jsr_32_di , + m68k_op_jsr_32_di , + m68k_op_jsr_32_di , + m68k_op_jsr_32_di , + m68k_op_jsr_32_di , + m68k_op_jsr_32_di , + m68k_op_jsr_32_di , + m68k_op_jsr_32_ix , + m68k_op_jsr_32_ix , + m68k_op_jsr_32_ix , + m68k_op_jsr_32_ix , + m68k_op_jsr_32_ix , + m68k_op_jsr_32_ix , + m68k_op_jsr_32_ix , + m68k_op_jsr_32_ix , + m68k_op_jsr_32_aw , + m68k_op_jsr_32_al , + m68k_op_jsr_32_pcdi , + m68k_op_jsr_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_jmp_32_ai , + m68k_op_jmp_32_ai , + m68k_op_jmp_32_ai , + m68k_op_jmp_32_ai , + m68k_op_jmp_32_ai , + m68k_op_jmp_32_ai , + m68k_op_jmp_32_ai , + m68k_op_jmp_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_jmp_32_di , + m68k_op_jmp_32_di , + m68k_op_jmp_32_di , + m68k_op_jmp_32_di , + m68k_op_jmp_32_di , + m68k_op_jmp_32_di , + m68k_op_jmp_32_di , + m68k_op_jmp_32_di , + m68k_op_jmp_32_ix , + m68k_op_jmp_32_ix , + m68k_op_jmp_32_ix , + m68k_op_jmp_32_ix , + m68k_op_jmp_32_ix , + m68k_op_jmp_32_ix , + m68k_op_jmp_32_ix , + m68k_op_jmp_32_ix , + m68k_op_jmp_32_aw , + m68k_op_jmp_32_al , + m68k_op_jmp_32_pcdi , + m68k_op_jmp_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_chk_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_ai , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pi , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_pd , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_di , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_ix , + m68k_op_chk_32_aw , + m68k_op_chk_32_al , + m68k_op_chk_32_pcdi , + m68k_op_chk_32_pcix , + m68k_op_chk_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_chk_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_ai , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pi , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_pd , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_di , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_ix , + m68k_op_chk_16_aw , + m68k_op_chk_16_al , + m68k_op_chk_16_pcdi , + m68k_op_chk_16_pcix , + m68k_op_chk_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_lea_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_di , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_ix , + m68k_op_lea_32_aw , + m68k_op_lea_32_al , + m68k_op_lea_32_pcdi , + m68k_op_lea_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi7 , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd7 , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_aw , + m68k_op_addq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_aw , + m68k_op_addq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_aw , + m68k_op_addq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_st_8_d , + m68k_op_st_8_d , + m68k_op_st_8_d , + m68k_op_st_8_d , + m68k_op_st_8_d , + m68k_op_st_8_d , + m68k_op_st_8_d , + m68k_op_st_8_d , + m68k_op_dbt_16 , + m68k_op_dbt_16 , + m68k_op_dbt_16 , + m68k_op_dbt_16 , + m68k_op_dbt_16 , + m68k_op_dbt_16 , + m68k_op_dbt_16 , + m68k_op_dbt_16 , + m68k_op_st_8_ai , + m68k_op_st_8_ai , + m68k_op_st_8_ai , + m68k_op_st_8_ai , + m68k_op_st_8_ai , + m68k_op_st_8_ai , + m68k_op_st_8_ai , + m68k_op_st_8_ai , + m68k_op_st_8_pi , + m68k_op_st_8_pi , + m68k_op_st_8_pi , + m68k_op_st_8_pi , + m68k_op_st_8_pi , + m68k_op_st_8_pi , + m68k_op_st_8_pi , + m68k_op_st_8_pi7 , + m68k_op_st_8_pd , + m68k_op_st_8_pd , + m68k_op_st_8_pd , + m68k_op_st_8_pd , + m68k_op_st_8_pd , + m68k_op_st_8_pd , + m68k_op_st_8_pd , + m68k_op_st_8_pd7 , + m68k_op_st_8_di , + m68k_op_st_8_di , + m68k_op_st_8_di , + m68k_op_st_8_di , + m68k_op_st_8_di , + m68k_op_st_8_di , + m68k_op_st_8_di , + m68k_op_st_8_di , + m68k_op_st_8_ix , + m68k_op_st_8_ix , + m68k_op_st_8_ix , + m68k_op_st_8_ix , + m68k_op_st_8_ix , + m68k_op_st_8_ix , + m68k_op_st_8_ix , + m68k_op_st_8_ix , + m68k_op_st_8_aw , + m68k_op_st_8_al , + m68k_op_trapt_16 , + m68k_op_trapt_32 , + m68k_op_trapt , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi7 , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd7 , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_aw , + m68k_op_subq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_aw , + m68k_op_subq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_aw , + m68k_op_subq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sf_8_d , + m68k_op_sf_8_d , + m68k_op_sf_8_d , + m68k_op_sf_8_d , + m68k_op_sf_8_d , + m68k_op_sf_8_d , + m68k_op_sf_8_d , + m68k_op_sf_8_d , + m68k_op_dbf_16 , + m68k_op_dbf_16 , + m68k_op_dbf_16 , + m68k_op_dbf_16 , + m68k_op_dbf_16 , + m68k_op_dbf_16 , + m68k_op_dbf_16 , + m68k_op_dbf_16 , + m68k_op_sf_8_ai , + m68k_op_sf_8_ai , + m68k_op_sf_8_ai , + m68k_op_sf_8_ai , + m68k_op_sf_8_ai , + m68k_op_sf_8_ai , + m68k_op_sf_8_ai , + m68k_op_sf_8_ai , + m68k_op_sf_8_pi , + m68k_op_sf_8_pi , + m68k_op_sf_8_pi , + m68k_op_sf_8_pi , + m68k_op_sf_8_pi , + m68k_op_sf_8_pi , + m68k_op_sf_8_pi , + m68k_op_sf_8_pi7 , + m68k_op_sf_8_pd , + m68k_op_sf_8_pd , + m68k_op_sf_8_pd , + m68k_op_sf_8_pd , + m68k_op_sf_8_pd , + m68k_op_sf_8_pd , + m68k_op_sf_8_pd , + m68k_op_sf_8_pd7 , + m68k_op_sf_8_di , + m68k_op_sf_8_di , + m68k_op_sf_8_di , + m68k_op_sf_8_di , + m68k_op_sf_8_di , + m68k_op_sf_8_di , + m68k_op_sf_8_di , + m68k_op_sf_8_di , + m68k_op_sf_8_ix , + m68k_op_sf_8_ix , + m68k_op_sf_8_ix , + m68k_op_sf_8_ix , + m68k_op_sf_8_ix , + m68k_op_sf_8_ix , + m68k_op_sf_8_ix , + m68k_op_sf_8_ix , + m68k_op_sf_8_aw , + m68k_op_sf_8_al , + m68k_op_trapf_16 , + m68k_op_trapf_32 , + m68k_op_trapf , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi7 , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd7 , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_aw , + m68k_op_addq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_aw , + m68k_op_addq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_aw , + m68k_op_addq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_shi_8_d , + m68k_op_shi_8_d , + m68k_op_shi_8_d , + m68k_op_shi_8_d , + m68k_op_shi_8_d , + m68k_op_shi_8_d , + m68k_op_shi_8_d , + m68k_op_shi_8_d , + m68k_op_dbhi_16 , + m68k_op_dbhi_16 , + m68k_op_dbhi_16 , + m68k_op_dbhi_16 , + m68k_op_dbhi_16 , + m68k_op_dbhi_16 , + m68k_op_dbhi_16 , + m68k_op_dbhi_16 , + m68k_op_shi_8_ai , + m68k_op_shi_8_ai , + m68k_op_shi_8_ai , + m68k_op_shi_8_ai , + m68k_op_shi_8_ai , + m68k_op_shi_8_ai , + m68k_op_shi_8_ai , + m68k_op_shi_8_ai , + m68k_op_shi_8_pi , + m68k_op_shi_8_pi , + m68k_op_shi_8_pi , + m68k_op_shi_8_pi , + m68k_op_shi_8_pi , + m68k_op_shi_8_pi , + m68k_op_shi_8_pi , + m68k_op_shi_8_pi7 , + m68k_op_shi_8_pd , + m68k_op_shi_8_pd , + m68k_op_shi_8_pd , + m68k_op_shi_8_pd , + m68k_op_shi_8_pd , + m68k_op_shi_8_pd , + m68k_op_shi_8_pd , + m68k_op_shi_8_pd7 , + m68k_op_shi_8_di , + m68k_op_shi_8_di , + m68k_op_shi_8_di , + m68k_op_shi_8_di , + m68k_op_shi_8_di , + m68k_op_shi_8_di , + m68k_op_shi_8_di , + m68k_op_shi_8_di , + m68k_op_shi_8_ix , + m68k_op_shi_8_ix , + m68k_op_shi_8_ix , + m68k_op_shi_8_ix , + m68k_op_shi_8_ix , + m68k_op_shi_8_ix , + m68k_op_shi_8_ix , + m68k_op_shi_8_ix , + m68k_op_shi_8_aw , + m68k_op_shi_8_al , + m68k_op_traphi_16 , + m68k_op_traphi_32 , + m68k_op_traphi , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi7 , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd7 , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_aw , + m68k_op_subq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_aw , + m68k_op_subq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_aw , + m68k_op_subq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sls_8_d , + m68k_op_sls_8_d , + m68k_op_sls_8_d , + m68k_op_sls_8_d , + m68k_op_sls_8_d , + m68k_op_sls_8_d , + m68k_op_sls_8_d , + m68k_op_sls_8_d , + m68k_op_dbls_16 , + m68k_op_dbls_16 , + m68k_op_dbls_16 , + m68k_op_dbls_16 , + m68k_op_dbls_16 , + m68k_op_dbls_16 , + m68k_op_dbls_16 , + m68k_op_dbls_16 , + m68k_op_sls_8_ai , + m68k_op_sls_8_ai , + m68k_op_sls_8_ai , + m68k_op_sls_8_ai , + m68k_op_sls_8_ai , + m68k_op_sls_8_ai , + m68k_op_sls_8_ai , + m68k_op_sls_8_ai , + m68k_op_sls_8_pi , + m68k_op_sls_8_pi , + m68k_op_sls_8_pi , + m68k_op_sls_8_pi , + m68k_op_sls_8_pi , + m68k_op_sls_8_pi , + m68k_op_sls_8_pi , + m68k_op_sls_8_pi7 , + m68k_op_sls_8_pd , + m68k_op_sls_8_pd , + m68k_op_sls_8_pd , + m68k_op_sls_8_pd , + m68k_op_sls_8_pd , + m68k_op_sls_8_pd , + m68k_op_sls_8_pd , + m68k_op_sls_8_pd7 , + m68k_op_sls_8_di , + m68k_op_sls_8_di , + m68k_op_sls_8_di , + m68k_op_sls_8_di , + m68k_op_sls_8_di , + m68k_op_sls_8_di , + m68k_op_sls_8_di , + m68k_op_sls_8_di , + m68k_op_sls_8_ix , + m68k_op_sls_8_ix , + m68k_op_sls_8_ix , + m68k_op_sls_8_ix , + m68k_op_sls_8_ix , + m68k_op_sls_8_ix , + m68k_op_sls_8_ix , + m68k_op_sls_8_ix , + m68k_op_sls_8_aw , + m68k_op_sls_8_al , + m68k_op_trapls_16 , + m68k_op_trapls_32 , + m68k_op_trapls , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi7 , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd7 , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_aw , + m68k_op_addq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_aw , + m68k_op_addq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_aw , + m68k_op_addq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_scc_8_d , + m68k_op_scc_8_d , + m68k_op_scc_8_d , + m68k_op_scc_8_d , + m68k_op_scc_8_d , + m68k_op_scc_8_d , + m68k_op_scc_8_d , + m68k_op_scc_8_d , + m68k_op_dbcc_16 , + m68k_op_dbcc_16 , + m68k_op_dbcc_16 , + m68k_op_dbcc_16 , + m68k_op_dbcc_16 , + m68k_op_dbcc_16 , + m68k_op_dbcc_16 , + m68k_op_dbcc_16 , + m68k_op_scc_8_ai , + m68k_op_scc_8_ai , + m68k_op_scc_8_ai , + m68k_op_scc_8_ai , + m68k_op_scc_8_ai , + m68k_op_scc_8_ai , + m68k_op_scc_8_ai , + m68k_op_scc_8_ai , + m68k_op_scc_8_pi , + m68k_op_scc_8_pi , + m68k_op_scc_8_pi , + m68k_op_scc_8_pi , + m68k_op_scc_8_pi , + m68k_op_scc_8_pi , + m68k_op_scc_8_pi , + m68k_op_scc_8_pi7 , + m68k_op_scc_8_pd , + m68k_op_scc_8_pd , + m68k_op_scc_8_pd , + m68k_op_scc_8_pd , + m68k_op_scc_8_pd , + m68k_op_scc_8_pd , + m68k_op_scc_8_pd , + m68k_op_scc_8_pd7 , + m68k_op_scc_8_di , + m68k_op_scc_8_di , + m68k_op_scc_8_di , + m68k_op_scc_8_di , + m68k_op_scc_8_di , + m68k_op_scc_8_di , + m68k_op_scc_8_di , + m68k_op_scc_8_di , + m68k_op_scc_8_ix , + m68k_op_scc_8_ix , + m68k_op_scc_8_ix , + m68k_op_scc_8_ix , + m68k_op_scc_8_ix , + m68k_op_scc_8_ix , + m68k_op_scc_8_ix , + m68k_op_scc_8_ix , + m68k_op_scc_8_aw , + m68k_op_scc_8_al , + m68k_op_trapcc_16 , + m68k_op_trapcc_32 , + m68k_op_trapcc , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi7 , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd7 , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_aw , + m68k_op_subq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_aw , + m68k_op_subq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_aw , + m68k_op_subq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_scs_8_d , + m68k_op_scs_8_d , + m68k_op_scs_8_d , + m68k_op_scs_8_d , + m68k_op_scs_8_d , + m68k_op_scs_8_d , + m68k_op_scs_8_d , + m68k_op_scs_8_d , + m68k_op_dbcs_16 , + m68k_op_dbcs_16 , + m68k_op_dbcs_16 , + m68k_op_dbcs_16 , + m68k_op_dbcs_16 , + m68k_op_dbcs_16 , + m68k_op_dbcs_16 , + m68k_op_dbcs_16 , + m68k_op_scs_8_ai , + m68k_op_scs_8_ai , + m68k_op_scs_8_ai , + m68k_op_scs_8_ai , + m68k_op_scs_8_ai , + m68k_op_scs_8_ai , + m68k_op_scs_8_ai , + m68k_op_scs_8_ai , + m68k_op_scs_8_pi , + m68k_op_scs_8_pi , + m68k_op_scs_8_pi , + m68k_op_scs_8_pi , + m68k_op_scs_8_pi , + m68k_op_scs_8_pi , + m68k_op_scs_8_pi , + m68k_op_scs_8_pi7 , + m68k_op_scs_8_pd , + m68k_op_scs_8_pd , + m68k_op_scs_8_pd , + m68k_op_scs_8_pd , + m68k_op_scs_8_pd , + m68k_op_scs_8_pd , + m68k_op_scs_8_pd , + m68k_op_scs_8_pd7 , + m68k_op_scs_8_di , + m68k_op_scs_8_di , + m68k_op_scs_8_di , + m68k_op_scs_8_di , + m68k_op_scs_8_di , + m68k_op_scs_8_di , + m68k_op_scs_8_di , + m68k_op_scs_8_di , + m68k_op_scs_8_ix , + m68k_op_scs_8_ix , + m68k_op_scs_8_ix , + m68k_op_scs_8_ix , + m68k_op_scs_8_ix , + m68k_op_scs_8_ix , + m68k_op_scs_8_ix , + m68k_op_scs_8_ix , + m68k_op_scs_8_aw , + m68k_op_scs_8_al , + m68k_op_trapcs_16 , + m68k_op_trapcs_32 , + m68k_op_trapcs , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi7 , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd7 , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_aw , + m68k_op_addq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_aw , + m68k_op_addq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_aw , + m68k_op_addq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sne_8_d , + m68k_op_sne_8_d , + m68k_op_sne_8_d , + m68k_op_sne_8_d , + m68k_op_sne_8_d , + m68k_op_sne_8_d , + m68k_op_sne_8_d , + m68k_op_sne_8_d , + m68k_op_dbne_16 , + m68k_op_dbne_16 , + m68k_op_dbne_16 , + m68k_op_dbne_16 , + m68k_op_dbne_16 , + m68k_op_dbne_16 , + m68k_op_dbne_16 , + m68k_op_dbne_16 , + m68k_op_sne_8_ai , + m68k_op_sne_8_ai , + m68k_op_sne_8_ai , + m68k_op_sne_8_ai , + m68k_op_sne_8_ai , + m68k_op_sne_8_ai , + m68k_op_sne_8_ai , + m68k_op_sne_8_ai , + m68k_op_sne_8_pi , + m68k_op_sne_8_pi , + m68k_op_sne_8_pi , + m68k_op_sne_8_pi , + m68k_op_sne_8_pi , + m68k_op_sne_8_pi , + m68k_op_sne_8_pi , + m68k_op_sne_8_pi7 , + m68k_op_sne_8_pd , + m68k_op_sne_8_pd , + m68k_op_sne_8_pd , + m68k_op_sne_8_pd , + m68k_op_sne_8_pd , + m68k_op_sne_8_pd , + m68k_op_sne_8_pd , + m68k_op_sne_8_pd7 , + m68k_op_sne_8_di , + m68k_op_sne_8_di , + m68k_op_sne_8_di , + m68k_op_sne_8_di , + m68k_op_sne_8_di , + m68k_op_sne_8_di , + m68k_op_sne_8_di , + m68k_op_sne_8_di , + m68k_op_sne_8_ix , + m68k_op_sne_8_ix , + m68k_op_sne_8_ix , + m68k_op_sne_8_ix , + m68k_op_sne_8_ix , + m68k_op_sne_8_ix , + m68k_op_sne_8_ix , + m68k_op_sne_8_ix , + m68k_op_sne_8_aw , + m68k_op_sne_8_al , + m68k_op_trapne_16 , + m68k_op_trapne_32 , + m68k_op_trapne , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi7 , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd7 , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_aw , + m68k_op_subq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_aw , + m68k_op_subq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_aw , + m68k_op_subq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_seq_8_d , + m68k_op_seq_8_d , + m68k_op_seq_8_d , + m68k_op_seq_8_d , + m68k_op_seq_8_d , + m68k_op_seq_8_d , + m68k_op_seq_8_d , + m68k_op_seq_8_d , + m68k_op_dbeq_16 , + m68k_op_dbeq_16 , + m68k_op_dbeq_16 , + m68k_op_dbeq_16 , + m68k_op_dbeq_16 , + m68k_op_dbeq_16 , + m68k_op_dbeq_16 , + m68k_op_dbeq_16 , + m68k_op_seq_8_ai , + m68k_op_seq_8_ai , + m68k_op_seq_8_ai , + m68k_op_seq_8_ai , + m68k_op_seq_8_ai , + m68k_op_seq_8_ai , + m68k_op_seq_8_ai , + m68k_op_seq_8_ai , + m68k_op_seq_8_pi , + m68k_op_seq_8_pi , + m68k_op_seq_8_pi , + m68k_op_seq_8_pi , + m68k_op_seq_8_pi , + m68k_op_seq_8_pi , + m68k_op_seq_8_pi , + m68k_op_seq_8_pi7 , + m68k_op_seq_8_pd , + m68k_op_seq_8_pd , + m68k_op_seq_8_pd , + m68k_op_seq_8_pd , + m68k_op_seq_8_pd , + m68k_op_seq_8_pd , + m68k_op_seq_8_pd , + m68k_op_seq_8_pd7 , + m68k_op_seq_8_di , + m68k_op_seq_8_di , + m68k_op_seq_8_di , + m68k_op_seq_8_di , + m68k_op_seq_8_di , + m68k_op_seq_8_di , + m68k_op_seq_8_di , + m68k_op_seq_8_di , + m68k_op_seq_8_ix , + m68k_op_seq_8_ix , + m68k_op_seq_8_ix , + m68k_op_seq_8_ix , + m68k_op_seq_8_ix , + m68k_op_seq_8_ix , + m68k_op_seq_8_ix , + m68k_op_seq_8_ix , + m68k_op_seq_8_aw , + m68k_op_seq_8_al , + m68k_op_trapeq_16 , + m68k_op_trapeq_32 , + m68k_op_trapeq , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi7 , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd7 , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_aw , + m68k_op_addq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_aw , + m68k_op_addq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_aw , + m68k_op_addq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_svc_8_d , + m68k_op_svc_8_d , + m68k_op_svc_8_d , + m68k_op_svc_8_d , + m68k_op_svc_8_d , + m68k_op_svc_8_d , + m68k_op_svc_8_d , + m68k_op_svc_8_d , + m68k_op_dbvc_16 , + m68k_op_dbvc_16 , + m68k_op_dbvc_16 , + m68k_op_dbvc_16 , + m68k_op_dbvc_16 , + m68k_op_dbvc_16 , + m68k_op_dbvc_16 , + m68k_op_dbvc_16 , + m68k_op_svc_8_ai , + m68k_op_svc_8_ai , + m68k_op_svc_8_ai , + m68k_op_svc_8_ai , + m68k_op_svc_8_ai , + m68k_op_svc_8_ai , + m68k_op_svc_8_ai , + m68k_op_svc_8_ai , + m68k_op_svc_8_pi , + m68k_op_svc_8_pi , + m68k_op_svc_8_pi , + m68k_op_svc_8_pi , + m68k_op_svc_8_pi , + m68k_op_svc_8_pi , + m68k_op_svc_8_pi , + m68k_op_svc_8_pi7 , + m68k_op_svc_8_pd , + m68k_op_svc_8_pd , + m68k_op_svc_8_pd , + m68k_op_svc_8_pd , + m68k_op_svc_8_pd , + m68k_op_svc_8_pd , + m68k_op_svc_8_pd , + m68k_op_svc_8_pd7 , + m68k_op_svc_8_di , + m68k_op_svc_8_di , + m68k_op_svc_8_di , + m68k_op_svc_8_di , + m68k_op_svc_8_di , + m68k_op_svc_8_di , + m68k_op_svc_8_di , + m68k_op_svc_8_di , + m68k_op_svc_8_ix , + m68k_op_svc_8_ix , + m68k_op_svc_8_ix , + m68k_op_svc_8_ix , + m68k_op_svc_8_ix , + m68k_op_svc_8_ix , + m68k_op_svc_8_ix , + m68k_op_svc_8_ix , + m68k_op_svc_8_aw , + m68k_op_svc_8_al , + m68k_op_trapvc_16 , + m68k_op_trapvc_32 , + m68k_op_trapvc , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi7 , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd7 , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_aw , + m68k_op_subq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_aw , + m68k_op_subq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_aw , + m68k_op_subq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_svs_8_d , + m68k_op_svs_8_d , + m68k_op_svs_8_d , + m68k_op_svs_8_d , + m68k_op_svs_8_d , + m68k_op_svs_8_d , + m68k_op_svs_8_d , + m68k_op_svs_8_d , + m68k_op_dbvs_16 , + m68k_op_dbvs_16 , + m68k_op_dbvs_16 , + m68k_op_dbvs_16 , + m68k_op_dbvs_16 , + m68k_op_dbvs_16 , + m68k_op_dbvs_16 , + m68k_op_dbvs_16 , + m68k_op_svs_8_ai , + m68k_op_svs_8_ai , + m68k_op_svs_8_ai , + m68k_op_svs_8_ai , + m68k_op_svs_8_ai , + m68k_op_svs_8_ai , + m68k_op_svs_8_ai , + m68k_op_svs_8_ai , + m68k_op_svs_8_pi , + m68k_op_svs_8_pi , + m68k_op_svs_8_pi , + m68k_op_svs_8_pi , + m68k_op_svs_8_pi , + m68k_op_svs_8_pi , + m68k_op_svs_8_pi , + m68k_op_svs_8_pi7 , + m68k_op_svs_8_pd , + m68k_op_svs_8_pd , + m68k_op_svs_8_pd , + m68k_op_svs_8_pd , + m68k_op_svs_8_pd , + m68k_op_svs_8_pd , + m68k_op_svs_8_pd , + m68k_op_svs_8_pd7 , + m68k_op_svs_8_di , + m68k_op_svs_8_di , + m68k_op_svs_8_di , + m68k_op_svs_8_di , + m68k_op_svs_8_di , + m68k_op_svs_8_di , + m68k_op_svs_8_di , + m68k_op_svs_8_di , + m68k_op_svs_8_ix , + m68k_op_svs_8_ix , + m68k_op_svs_8_ix , + m68k_op_svs_8_ix , + m68k_op_svs_8_ix , + m68k_op_svs_8_ix , + m68k_op_svs_8_ix , + m68k_op_svs_8_ix , + m68k_op_svs_8_aw , + m68k_op_svs_8_al , + m68k_op_trapvs_16 , + m68k_op_trapvs_32 , + m68k_op_trapvs , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi7 , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd7 , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_aw , + m68k_op_addq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_aw , + m68k_op_addq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_aw , + m68k_op_addq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_spl_8_d , + m68k_op_spl_8_d , + m68k_op_spl_8_d , + m68k_op_spl_8_d , + m68k_op_spl_8_d , + m68k_op_spl_8_d , + m68k_op_spl_8_d , + m68k_op_spl_8_d , + m68k_op_dbpl_16 , + m68k_op_dbpl_16 , + m68k_op_dbpl_16 , + m68k_op_dbpl_16 , + m68k_op_dbpl_16 , + m68k_op_dbpl_16 , + m68k_op_dbpl_16 , + m68k_op_dbpl_16 , + m68k_op_spl_8_ai , + m68k_op_spl_8_ai , + m68k_op_spl_8_ai , + m68k_op_spl_8_ai , + m68k_op_spl_8_ai , + m68k_op_spl_8_ai , + m68k_op_spl_8_ai , + m68k_op_spl_8_ai , + m68k_op_spl_8_pi , + m68k_op_spl_8_pi , + m68k_op_spl_8_pi , + m68k_op_spl_8_pi , + m68k_op_spl_8_pi , + m68k_op_spl_8_pi , + m68k_op_spl_8_pi , + m68k_op_spl_8_pi7 , + m68k_op_spl_8_pd , + m68k_op_spl_8_pd , + m68k_op_spl_8_pd , + m68k_op_spl_8_pd , + m68k_op_spl_8_pd , + m68k_op_spl_8_pd , + m68k_op_spl_8_pd , + m68k_op_spl_8_pd7 , + m68k_op_spl_8_di , + m68k_op_spl_8_di , + m68k_op_spl_8_di , + m68k_op_spl_8_di , + m68k_op_spl_8_di , + m68k_op_spl_8_di , + m68k_op_spl_8_di , + m68k_op_spl_8_di , + m68k_op_spl_8_ix , + m68k_op_spl_8_ix , + m68k_op_spl_8_ix , + m68k_op_spl_8_ix , + m68k_op_spl_8_ix , + m68k_op_spl_8_ix , + m68k_op_spl_8_ix , + m68k_op_spl_8_ix , + m68k_op_spl_8_aw , + m68k_op_spl_8_al , + m68k_op_trappl_16 , + m68k_op_trappl_32 , + m68k_op_trappl , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi7 , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd7 , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_aw , + m68k_op_subq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_aw , + m68k_op_subq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_aw , + m68k_op_subq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_smi_8_d , + m68k_op_smi_8_d , + m68k_op_smi_8_d , + m68k_op_smi_8_d , + m68k_op_smi_8_d , + m68k_op_smi_8_d , + m68k_op_smi_8_d , + m68k_op_smi_8_d , + m68k_op_dbmi_16 , + m68k_op_dbmi_16 , + m68k_op_dbmi_16 , + m68k_op_dbmi_16 , + m68k_op_dbmi_16 , + m68k_op_dbmi_16 , + m68k_op_dbmi_16 , + m68k_op_dbmi_16 , + m68k_op_smi_8_ai , + m68k_op_smi_8_ai , + m68k_op_smi_8_ai , + m68k_op_smi_8_ai , + m68k_op_smi_8_ai , + m68k_op_smi_8_ai , + m68k_op_smi_8_ai , + m68k_op_smi_8_ai , + m68k_op_smi_8_pi , + m68k_op_smi_8_pi , + m68k_op_smi_8_pi , + m68k_op_smi_8_pi , + m68k_op_smi_8_pi , + m68k_op_smi_8_pi , + m68k_op_smi_8_pi , + m68k_op_smi_8_pi7 , + m68k_op_smi_8_pd , + m68k_op_smi_8_pd , + m68k_op_smi_8_pd , + m68k_op_smi_8_pd , + m68k_op_smi_8_pd , + m68k_op_smi_8_pd , + m68k_op_smi_8_pd , + m68k_op_smi_8_pd7 , + m68k_op_smi_8_di , + m68k_op_smi_8_di , + m68k_op_smi_8_di , + m68k_op_smi_8_di , + m68k_op_smi_8_di , + m68k_op_smi_8_di , + m68k_op_smi_8_di , + m68k_op_smi_8_di , + m68k_op_smi_8_ix , + m68k_op_smi_8_ix , + m68k_op_smi_8_ix , + m68k_op_smi_8_ix , + m68k_op_smi_8_ix , + m68k_op_smi_8_ix , + m68k_op_smi_8_ix , + m68k_op_smi_8_ix , + m68k_op_smi_8_aw , + m68k_op_smi_8_al , + m68k_op_trapmi_16 , + m68k_op_trapmi_32 , + m68k_op_trapmi , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi7 , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd7 , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_aw , + m68k_op_addq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_aw , + m68k_op_addq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_aw , + m68k_op_addq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sge_8_d , + m68k_op_sge_8_d , + m68k_op_sge_8_d , + m68k_op_sge_8_d , + m68k_op_sge_8_d , + m68k_op_sge_8_d , + m68k_op_sge_8_d , + m68k_op_sge_8_d , + m68k_op_dbge_16 , + m68k_op_dbge_16 , + m68k_op_dbge_16 , + m68k_op_dbge_16 , + m68k_op_dbge_16 , + m68k_op_dbge_16 , + m68k_op_dbge_16 , + m68k_op_dbge_16 , + m68k_op_sge_8_ai , + m68k_op_sge_8_ai , + m68k_op_sge_8_ai , + m68k_op_sge_8_ai , + m68k_op_sge_8_ai , + m68k_op_sge_8_ai , + m68k_op_sge_8_ai , + m68k_op_sge_8_ai , + m68k_op_sge_8_pi , + m68k_op_sge_8_pi , + m68k_op_sge_8_pi , + m68k_op_sge_8_pi , + m68k_op_sge_8_pi , + m68k_op_sge_8_pi , + m68k_op_sge_8_pi , + m68k_op_sge_8_pi7 , + m68k_op_sge_8_pd , + m68k_op_sge_8_pd , + m68k_op_sge_8_pd , + m68k_op_sge_8_pd , + m68k_op_sge_8_pd , + m68k_op_sge_8_pd , + m68k_op_sge_8_pd , + m68k_op_sge_8_pd7 , + m68k_op_sge_8_di , + m68k_op_sge_8_di , + m68k_op_sge_8_di , + m68k_op_sge_8_di , + m68k_op_sge_8_di , + m68k_op_sge_8_di , + m68k_op_sge_8_di , + m68k_op_sge_8_di , + m68k_op_sge_8_ix , + m68k_op_sge_8_ix , + m68k_op_sge_8_ix , + m68k_op_sge_8_ix , + m68k_op_sge_8_ix , + m68k_op_sge_8_ix , + m68k_op_sge_8_ix , + m68k_op_sge_8_ix , + m68k_op_sge_8_aw , + m68k_op_sge_8_al , + m68k_op_trapge_16 , + m68k_op_trapge_32 , + m68k_op_trapge , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi7 , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd7 , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_aw , + m68k_op_subq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_aw , + m68k_op_subq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_aw , + m68k_op_subq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_slt_8_d , + m68k_op_slt_8_d , + m68k_op_slt_8_d , + m68k_op_slt_8_d , + m68k_op_slt_8_d , + m68k_op_slt_8_d , + m68k_op_slt_8_d , + m68k_op_slt_8_d , + m68k_op_dblt_16 , + m68k_op_dblt_16 , + m68k_op_dblt_16 , + m68k_op_dblt_16 , + m68k_op_dblt_16 , + m68k_op_dblt_16 , + m68k_op_dblt_16 , + m68k_op_dblt_16 , + m68k_op_slt_8_ai , + m68k_op_slt_8_ai , + m68k_op_slt_8_ai , + m68k_op_slt_8_ai , + m68k_op_slt_8_ai , + m68k_op_slt_8_ai , + m68k_op_slt_8_ai , + m68k_op_slt_8_ai , + m68k_op_slt_8_pi , + m68k_op_slt_8_pi , + m68k_op_slt_8_pi , + m68k_op_slt_8_pi , + m68k_op_slt_8_pi , + m68k_op_slt_8_pi , + m68k_op_slt_8_pi , + m68k_op_slt_8_pi7 , + m68k_op_slt_8_pd , + m68k_op_slt_8_pd , + m68k_op_slt_8_pd , + m68k_op_slt_8_pd , + m68k_op_slt_8_pd , + m68k_op_slt_8_pd , + m68k_op_slt_8_pd , + m68k_op_slt_8_pd7 , + m68k_op_slt_8_di , + m68k_op_slt_8_di , + m68k_op_slt_8_di , + m68k_op_slt_8_di , + m68k_op_slt_8_di , + m68k_op_slt_8_di , + m68k_op_slt_8_di , + m68k_op_slt_8_di , + m68k_op_slt_8_ix , + m68k_op_slt_8_ix , + m68k_op_slt_8_ix , + m68k_op_slt_8_ix , + m68k_op_slt_8_ix , + m68k_op_slt_8_ix , + m68k_op_slt_8_ix , + m68k_op_slt_8_ix , + m68k_op_slt_8_aw , + m68k_op_slt_8_al , + m68k_op_traplt_16 , + m68k_op_traplt_32 , + m68k_op_traplt , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_addq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_ai , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi , + m68k_op_addq_8_pi7 , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd , + m68k_op_addq_8_pd7 , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_di , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_ix , + m68k_op_addq_8_aw , + m68k_op_addq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_d , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_a , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_ai , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pi , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_pd , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_di , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_ix , + m68k_op_addq_16_aw , + m68k_op_addq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_d , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_a , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_ai , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pi , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_pd , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_di , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_ix , + m68k_op_addq_32_aw , + m68k_op_addq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sgt_8_d , + m68k_op_sgt_8_d , + m68k_op_sgt_8_d , + m68k_op_sgt_8_d , + m68k_op_sgt_8_d , + m68k_op_sgt_8_d , + m68k_op_sgt_8_d , + m68k_op_sgt_8_d , + m68k_op_dbgt_16 , + m68k_op_dbgt_16 , + m68k_op_dbgt_16 , + m68k_op_dbgt_16 , + m68k_op_dbgt_16 , + m68k_op_dbgt_16 , + m68k_op_dbgt_16 , + m68k_op_dbgt_16 , + m68k_op_sgt_8_ai , + m68k_op_sgt_8_ai , + m68k_op_sgt_8_ai , + m68k_op_sgt_8_ai , + m68k_op_sgt_8_ai , + m68k_op_sgt_8_ai , + m68k_op_sgt_8_ai , + m68k_op_sgt_8_ai , + m68k_op_sgt_8_pi , + m68k_op_sgt_8_pi , + m68k_op_sgt_8_pi , + m68k_op_sgt_8_pi , + m68k_op_sgt_8_pi , + m68k_op_sgt_8_pi , + m68k_op_sgt_8_pi , + m68k_op_sgt_8_pi7 , + m68k_op_sgt_8_pd , + m68k_op_sgt_8_pd , + m68k_op_sgt_8_pd , + m68k_op_sgt_8_pd , + m68k_op_sgt_8_pd , + m68k_op_sgt_8_pd , + m68k_op_sgt_8_pd , + m68k_op_sgt_8_pd7 , + m68k_op_sgt_8_di , + m68k_op_sgt_8_di , + m68k_op_sgt_8_di , + m68k_op_sgt_8_di , + m68k_op_sgt_8_di , + m68k_op_sgt_8_di , + m68k_op_sgt_8_di , + m68k_op_sgt_8_di , + m68k_op_sgt_8_ix , + m68k_op_sgt_8_ix , + m68k_op_sgt_8_ix , + m68k_op_sgt_8_ix , + m68k_op_sgt_8_ix , + m68k_op_sgt_8_ix , + m68k_op_sgt_8_ix , + m68k_op_sgt_8_ix , + m68k_op_sgt_8_aw , + m68k_op_sgt_8_al , + m68k_op_trapgt_16 , + m68k_op_trapgt_32 , + m68k_op_trapgt , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_subq_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_ai , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi , + m68k_op_subq_8_pi7 , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd , + m68k_op_subq_8_pd7 , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_di , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_ix , + m68k_op_subq_8_aw , + m68k_op_subq_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_d , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_a , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_ai , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pi , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_pd , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_di , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_ix , + m68k_op_subq_16_aw , + m68k_op_subq_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_d , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_a , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_ai , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pi , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_pd , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_di , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_ix , + m68k_op_subq_32_aw , + m68k_op_subq_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sle_8_d , + m68k_op_sle_8_d , + m68k_op_sle_8_d , + m68k_op_sle_8_d , + m68k_op_sle_8_d , + m68k_op_sle_8_d , + m68k_op_sle_8_d , + m68k_op_sle_8_d , + m68k_op_dble_16 , + m68k_op_dble_16 , + m68k_op_dble_16 , + m68k_op_dble_16 , + m68k_op_dble_16 , + m68k_op_dble_16 , + m68k_op_dble_16 , + m68k_op_dble_16 , + m68k_op_sle_8_ai , + m68k_op_sle_8_ai , + m68k_op_sle_8_ai , + m68k_op_sle_8_ai , + m68k_op_sle_8_ai , + m68k_op_sle_8_ai , + m68k_op_sle_8_ai , + m68k_op_sle_8_ai , + m68k_op_sle_8_pi , + m68k_op_sle_8_pi , + m68k_op_sle_8_pi , + m68k_op_sle_8_pi , + m68k_op_sle_8_pi , + m68k_op_sle_8_pi , + m68k_op_sle_8_pi , + m68k_op_sle_8_pi7 , + m68k_op_sle_8_pd , + m68k_op_sle_8_pd , + m68k_op_sle_8_pd , + m68k_op_sle_8_pd , + m68k_op_sle_8_pd , + m68k_op_sle_8_pd , + m68k_op_sle_8_pd , + m68k_op_sle_8_pd7 , + m68k_op_sle_8_di , + m68k_op_sle_8_di , + m68k_op_sle_8_di , + m68k_op_sle_8_di , + m68k_op_sle_8_di , + m68k_op_sle_8_di , + m68k_op_sle_8_di , + m68k_op_sle_8_di , + m68k_op_sle_8_ix , + m68k_op_sle_8_ix , + m68k_op_sle_8_ix , + m68k_op_sle_8_ix , + m68k_op_sle_8_ix , + m68k_op_sle_8_ix , + m68k_op_sle_8_ix , + m68k_op_sle_8_ix , + m68k_op_sle_8_aw , + m68k_op_sle_8_al , + m68k_op_traple_16 , + m68k_op_traple_32 , + m68k_op_traple , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bra_16 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + m68k_op_bra_8 , + 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+ m68k_op_or_32_er_al , + m68k_op_or_32_er_pcdi , + m68k_op_or_32_er_pcix , + m68k_op_or_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_aw , + m68k_op_divu_16_al , + m68k_op_divu_16_pcdi , + m68k_op_divu_16_pcix , + m68k_op_divu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm_ay7 , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi7 , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd7 , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_aw , + m68k_op_or_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm_ay7 , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_aw , + m68k_op_or_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm_ay7 , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_aw , + m68k_op_or_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_aw , + m68k_op_divs_16_al , + m68k_op_divs_16_pcdi , + m68k_op_divs_16_pcix , + m68k_op_divs_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi7 , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd7 , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_aw , + m68k_op_or_8_er_al , + m68k_op_or_8_er_pcdi , + m68k_op_or_8_er_pcix , + m68k_op_or_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_aw , + m68k_op_or_16_er_al , + m68k_op_or_16_er_pcdi , + m68k_op_or_16_er_pcix , + m68k_op_or_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_aw , + m68k_op_or_32_er_al , + m68k_op_or_32_er_pcdi , + m68k_op_or_32_er_pcix , + m68k_op_or_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_aw , + m68k_op_divu_16_al , + m68k_op_divu_16_pcdi , + m68k_op_divu_16_pcix , + m68k_op_divu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm_ay7 , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi7 , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd7 , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_aw , + m68k_op_or_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm_ay7 , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_aw , + m68k_op_or_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm_ay7 , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_aw , + m68k_op_or_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_aw , + m68k_op_divs_16_al , + m68k_op_divs_16_pcdi , + m68k_op_divs_16_pcix , + m68k_op_divs_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi7 , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd7 , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_aw , + m68k_op_or_8_er_al , + m68k_op_or_8_er_pcdi , + m68k_op_or_8_er_pcix , + m68k_op_or_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_aw , + m68k_op_or_16_er_al , + m68k_op_or_16_er_pcdi , + m68k_op_or_16_er_pcix , + m68k_op_or_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_aw , + m68k_op_or_32_er_al , + m68k_op_or_32_er_pcdi , + m68k_op_or_32_er_pcix , + m68k_op_or_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_aw , + m68k_op_divu_16_al , + m68k_op_divu_16_pcdi , + m68k_op_divu_16_pcix , + m68k_op_divu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm_ay7 , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi7 , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd7 , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_aw , + m68k_op_or_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm_ay7 , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_aw , + m68k_op_or_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm_ay7 , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_aw , + m68k_op_or_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_aw , + m68k_op_divs_16_al , + m68k_op_divs_16_pcdi , + m68k_op_divs_16_pcix , + m68k_op_divs_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi7 , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd7 , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_aw , + m68k_op_or_8_er_al , + m68k_op_or_8_er_pcdi , + m68k_op_or_8_er_pcix , + m68k_op_or_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_aw , + m68k_op_or_16_er_al , + m68k_op_or_16_er_pcdi , + m68k_op_or_16_er_pcix , + m68k_op_or_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_aw , + m68k_op_or_32_er_al , + m68k_op_or_32_er_pcdi , + m68k_op_or_32_er_pcix , + m68k_op_or_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_aw , + m68k_op_divu_16_al , + m68k_op_divu_16_pcdi , + m68k_op_divu_16_pcix , + m68k_op_divu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm_ay7 , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi7 , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd7 , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_aw , + m68k_op_or_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm_ay7 , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_aw , + m68k_op_or_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm_ay7 , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_aw , + m68k_op_or_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_aw , + m68k_op_divs_16_al , + m68k_op_divs_16_pcdi , + m68k_op_divs_16_pcix , + m68k_op_divs_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi7 , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd7 , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_aw , + m68k_op_or_8_er_al , + m68k_op_or_8_er_pcdi , + m68k_op_or_8_er_pcix , + m68k_op_or_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_aw , + m68k_op_or_16_er_al , + m68k_op_or_16_er_pcdi , + m68k_op_or_16_er_pcix , + m68k_op_or_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_aw , + m68k_op_or_32_er_al , + m68k_op_or_32_er_pcdi , + m68k_op_or_32_er_pcix , + m68k_op_or_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_aw , + m68k_op_divu_16_al , + m68k_op_divu_16_pcdi , + m68k_op_divu_16_pcix , + m68k_op_divu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm_ay7 , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi7 , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd7 , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_aw , + m68k_op_or_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm_ay7 , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_aw , + m68k_op_or_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm_ay7 , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_aw , + m68k_op_or_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_aw , + m68k_op_divs_16_al , + m68k_op_divs_16_pcdi , + m68k_op_divs_16_pcix , + m68k_op_divs_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi7 , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd7 , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_aw , + m68k_op_or_8_er_al , + m68k_op_or_8_er_pcdi , + m68k_op_or_8_er_pcix , + m68k_op_or_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_aw , + m68k_op_or_16_er_al , + m68k_op_or_16_er_pcdi , + m68k_op_or_16_er_pcix , + m68k_op_or_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_aw , + m68k_op_or_32_er_al , + m68k_op_or_32_er_pcdi , + m68k_op_or_32_er_pcix , + m68k_op_or_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_aw , + m68k_op_divu_16_al , + m68k_op_divu_16_pcdi , + m68k_op_divu_16_pcix , + m68k_op_divu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm_ay7 , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi7 , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd7 , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_aw , + m68k_op_or_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm_ay7 , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_aw , + m68k_op_or_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm_ay7 , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_aw , + m68k_op_or_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_aw , + m68k_op_divs_16_al , + m68k_op_divs_16_pcdi , + m68k_op_divs_16_pcix , + m68k_op_divs_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi7 , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd7 , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_aw , + m68k_op_or_8_er_al , + m68k_op_or_8_er_pcdi , + m68k_op_or_8_er_pcix , + m68k_op_or_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_aw , + m68k_op_or_16_er_al , + m68k_op_or_16_er_pcdi , + m68k_op_or_16_er_pcix , + m68k_op_or_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_aw , + m68k_op_or_32_er_al , + m68k_op_or_32_er_pcdi , + m68k_op_or_32_er_pcix , + m68k_op_or_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_aw , + m68k_op_divu_16_al , + m68k_op_divu_16_pcdi , + m68k_op_divu_16_pcix , + m68k_op_divu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm , + m68k_op_sbcd_8_mm_ay7 , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi7 , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd7 , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_aw , + m68k_op_or_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm , + m68k_op_pack_16_mm_ay7 , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_aw , + m68k_op_or_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm , + m68k_op_unpk_16_mm_ay7 , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_aw , + m68k_op_or_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_aw , + m68k_op_divs_16_al , + m68k_op_divs_16_pcdi , + m68k_op_divs_16_pcix , + m68k_op_divs_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_or_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_ai , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi , + m68k_op_or_8_er_pi7 , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd , + m68k_op_or_8_er_pd7 , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_di , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_ix , + m68k_op_or_8_er_aw , + m68k_op_or_8_er_al , + m68k_op_or_8_er_pcdi , + m68k_op_or_8_er_pcix , + m68k_op_or_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_or_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_ai , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pi , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_pd , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_di , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_ix , + m68k_op_or_16_er_aw , + m68k_op_or_16_er_al , + m68k_op_or_16_er_pcdi , + m68k_op_or_16_er_pcix , + m68k_op_or_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_or_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_ai , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pi , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_pd , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_di , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_ix , + m68k_op_or_32_er_aw , + m68k_op_or_32_er_al , + m68k_op_or_32_er_pcdi , + m68k_op_or_32_er_pcix , + m68k_op_or_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_divu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_ai , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pi , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_pd , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_di , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_ix , + m68k_op_divu_16_aw , + m68k_op_divu_16_al , + m68k_op_divu_16_pcdi , + m68k_op_divu_16_pcix , + m68k_op_divu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_rr , + m68k_op_sbcd_8_mm_ax7 , + m68k_op_sbcd_8_mm_ax7 , + m68k_op_sbcd_8_mm_ax7 , + m68k_op_sbcd_8_mm_ax7 , + m68k_op_sbcd_8_mm_ax7 , + m68k_op_sbcd_8_mm_ax7 , + m68k_op_sbcd_8_mm_ax7 , + m68k_op_sbcd_8_mm_axy7 , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_ai , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi , + m68k_op_or_8_re_pi7 , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd , + m68k_op_or_8_re_pd7 , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_di , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_ix , + m68k_op_or_8_re_aw , + m68k_op_or_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_rr , + m68k_op_pack_16_mm_ax7 , + m68k_op_pack_16_mm_ax7 , + m68k_op_pack_16_mm_ax7 , + m68k_op_pack_16_mm_ax7 , + m68k_op_pack_16_mm_ax7 , + m68k_op_pack_16_mm_ax7 , + m68k_op_pack_16_mm_ax7 , + m68k_op_pack_16_mm_axy7 , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_ai , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pi , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_pd , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_di , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_ix , + m68k_op_or_16_re_aw , + m68k_op_or_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_rr , + m68k_op_unpk_16_mm_ax7 , + m68k_op_unpk_16_mm_ax7 , + m68k_op_unpk_16_mm_ax7 , + m68k_op_unpk_16_mm_ax7 , + m68k_op_unpk_16_mm_ax7 , + m68k_op_unpk_16_mm_ax7 , + m68k_op_unpk_16_mm_ax7 , + m68k_op_unpk_16_mm_axy7 , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_ai , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pi , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_pd , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_di , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_ix , + m68k_op_or_32_re_aw , + m68k_op_or_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_divs_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_ai , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pi , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_pd , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_di , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_ix , + m68k_op_divs_16_aw , + m68k_op_divs_16_al , + m68k_op_divs_16_pcdi , + m68k_op_divs_16_pcix , + m68k_op_divs_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi7 , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd7 , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_aw , + m68k_op_sub_8_er_al , + m68k_op_sub_8_er_pcdi , + m68k_op_sub_8_er_pcix , + m68k_op_sub_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_aw , + m68k_op_sub_16_er_al , + m68k_op_sub_16_er_pcdi , + m68k_op_sub_16_er_pcix , + m68k_op_sub_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_aw , + m68k_op_sub_32_er_al , + m68k_op_sub_32_er_pcdi , + m68k_op_sub_32_er_pcix , + m68k_op_sub_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_aw , + m68k_op_suba_16_al , + m68k_op_suba_16_pcdi , + m68k_op_suba_16_pcix , + m68k_op_suba_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm_ay7 , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi7 , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd7 , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_aw , + m68k_op_sub_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_aw , + m68k_op_sub_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_aw , + m68k_op_sub_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_aw , + m68k_op_suba_32_al , + m68k_op_suba_32_pcdi , + m68k_op_suba_32_pcix , + m68k_op_suba_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi7 , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd7 , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_aw , + m68k_op_sub_8_er_al , + m68k_op_sub_8_er_pcdi , + m68k_op_sub_8_er_pcix , + m68k_op_sub_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_aw , + m68k_op_sub_16_er_al , + m68k_op_sub_16_er_pcdi , + m68k_op_sub_16_er_pcix , + m68k_op_sub_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_aw , + m68k_op_sub_32_er_al , + m68k_op_sub_32_er_pcdi , + m68k_op_sub_32_er_pcix , + m68k_op_sub_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_aw , + m68k_op_suba_16_al , + m68k_op_suba_16_pcdi , + m68k_op_suba_16_pcix , + m68k_op_suba_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm_ay7 , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi7 , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd7 , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_aw , + m68k_op_sub_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_aw , + m68k_op_sub_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_aw , + m68k_op_sub_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_aw , + m68k_op_suba_32_al , + m68k_op_suba_32_pcdi , + m68k_op_suba_32_pcix , + m68k_op_suba_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi7 , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd7 , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_aw , + m68k_op_sub_8_er_al , + m68k_op_sub_8_er_pcdi , + m68k_op_sub_8_er_pcix , + m68k_op_sub_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_aw , + m68k_op_sub_16_er_al , + m68k_op_sub_16_er_pcdi , + m68k_op_sub_16_er_pcix , + m68k_op_sub_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_aw , + m68k_op_sub_32_er_al , + m68k_op_sub_32_er_pcdi , + m68k_op_sub_32_er_pcix , + m68k_op_sub_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_aw , + m68k_op_suba_16_al , + m68k_op_suba_16_pcdi , + m68k_op_suba_16_pcix , + m68k_op_suba_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm_ay7 , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi7 , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd7 , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_aw , + m68k_op_sub_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_aw , + m68k_op_sub_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_aw , + m68k_op_sub_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_aw , + m68k_op_suba_32_al , + m68k_op_suba_32_pcdi , + m68k_op_suba_32_pcix , + m68k_op_suba_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi7 , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd7 , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_aw , + m68k_op_sub_8_er_al , + m68k_op_sub_8_er_pcdi , + m68k_op_sub_8_er_pcix , + m68k_op_sub_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_aw , + m68k_op_sub_16_er_al , + m68k_op_sub_16_er_pcdi , + m68k_op_sub_16_er_pcix , + m68k_op_sub_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_aw , + m68k_op_sub_32_er_al , + m68k_op_sub_32_er_pcdi , + m68k_op_sub_32_er_pcix , + m68k_op_sub_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_aw , + m68k_op_suba_16_al , + m68k_op_suba_16_pcdi , + m68k_op_suba_16_pcix , + m68k_op_suba_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm_ay7 , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi7 , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd7 , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_aw , + m68k_op_sub_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_aw , + m68k_op_sub_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_aw , + m68k_op_sub_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_aw , + m68k_op_suba_32_al , + m68k_op_suba_32_pcdi , + m68k_op_suba_32_pcix , + m68k_op_suba_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi7 , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd7 , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_aw , + m68k_op_sub_8_er_al , + m68k_op_sub_8_er_pcdi , + m68k_op_sub_8_er_pcix , + m68k_op_sub_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_aw , + m68k_op_sub_16_er_al , + m68k_op_sub_16_er_pcdi , + m68k_op_sub_16_er_pcix , + m68k_op_sub_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_aw , + m68k_op_sub_32_er_al , + m68k_op_sub_32_er_pcdi , + m68k_op_sub_32_er_pcix , + m68k_op_sub_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_aw , + m68k_op_suba_16_al , + m68k_op_suba_16_pcdi , + m68k_op_suba_16_pcix , + m68k_op_suba_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm_ay7 , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi7 , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd7 , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_aw , + m68k_op_sub_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_aw , + m68k_op_sub_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_aw , + m68k_op_sub_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_aw , + m68k_op_suba_32_al , + m68k_op_suba_32_pcdi , + m68k_op_suba_32_pcix , + m68k_op_suba_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi7 , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd7 , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_aw , + m68k_op_sub_8_er_al , + m68k_op_sub_8_er_pcdi , + m68k_op_sub_8_er_pcix , + m68k_op_sub_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_aw , + m68k_op_sub_16_er_al , + m68k_op_sub_16_er_pcdi , + m68k_op_sub_16_er_pcix , + m68k_op_sub_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_aw , + m68k_op_sub_32_er_al , + m68k_op_sub_32_er_pcdi , + m68k_op_sub_32_er_pcix , + m68k_op_sub_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_aw , + m68k_op_suba_16_al , + m68k_op_suba_16_pcdi , + m68k_op_suba_16_pcix , + m68k_op_suba_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm_ay7 , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi7 , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd7 , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_aw , + m68k_op_sub_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_aw , + m68k_op_sub_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_aw , + m68k_op_sub_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_aw , + m68k_op_suba_32_al , + m68k_op_suba_32_pcdi , + m68k_op_suba_32_pcix , + m68k_op_suba_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi7 , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd7 , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_aw , + m68k_op_sub_8_er_al , + m68k_op_sub_8_er_pcdi , + m68k_op_sub_8_er_pcix , + m68k_op_sub_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_aw , + m68k_op_sub_16_er_al , + m68k_op_sub_16_er_pcdi , + m68k_op_sub_16_er_pcix , + m68k_op_sub_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_aw , + m68k_op_sub_32_er_al , + m68k_op_sub_32_er_pcdi , + m68k_op_sub_32_er_pcix , + m68k_op_sub_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_aw , + m68k_op_suba_16_al , + m68k_op_suba_16_pcdi , + m68k_op_suba_16_pcix , + m68k_op_suba_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm , + m68k_op_subx_8_mm_ay7 , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi7 , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd7 , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_aw , + m68k_op_sub_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_aw , + m68k_op_sub_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_aw , + m68k_op_sub_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_aw , + m68k_op_suba_32_al , + m68k_op_suba_32_pcdi , + m68k_op_suba_32_pcix , + m68k_op_suba_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_sub_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_ai , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi , + m68k_op_sub_8_er_pi7 , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd , + m68k_op_sub_8_er_pd7 , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_di , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_ix , + m68k_op_sub_8_er_aw , + m68k_op_sub_8_er_al , + m68k_op_sub_8_er_pcdi , + m68k_op_sub_8_er_pcix , + m68k_op_sub_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_d , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_a , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_ai , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pi , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_pd , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_di , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_ix , + m68k_op_sub_16_er_aw , + m68k_op_sub_16_er_al , + m68k_op_sub_16_er_pcdi , + m68k_op_sub_16_er_pcix , + m68k_op_sub_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_d , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_a , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_ai , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pi , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_pd , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_di , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_ix , + m68k_op_sub_32_er_aw , + m68k_op_sub_32_er_al , + m68k_op_sub_32_er_pcdi , + m68k_op_sub_32_er_pcix , + m68k_op_sub_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_d , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_a , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_ai , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pi , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_pd , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_di , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_ix , + m68k_op_suba_16_aw , + m68k_op_suba_16_al , + m68k_op_suba_16_pcdi , + m68k_op_suba_16_pcix , + m68k_op_suba_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_rr , + m68k_op_subx_8_mm_ax7 , + m68k_op_subx_8_mm_ax7 , + m68k_op_subx_8_mm_ax7 , + m68k_op_subx_8_mm_ax7 , + m68k_op_subx_8_mm_ax7 , + m68k_op_subx_8_mm_ax7 , + m68k_op_subx_8_mm_ax7 , + m68k_op_subx_8_mm_axy7 , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_ai , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi , + m68k_op_sub_8_re_pi7 , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd , + m68k_op_sub_8_re_pd7 , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_di , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_ix , + m68k_op_sub_8_re_aw , + m68k_op_sub_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_rr , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_subx_16_mm , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_ai , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pi , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_pd , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_di , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_ix , + m68k_op_sub_16_re_aw , + m68k_op_sub_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_rr , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_subx_32_mm , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_ai , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pi , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_pd , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_di , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_ix , + m68k_op_sub_32_re_aw , + m68k_op_sub_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_d , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_a , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_ai , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pi , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_pd , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_di , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_ix , + m68k_op_suba_32_aw , + m68k_op_suba_32_al , + m68k_op_suba_32_pcdi , + m68k_op_suba_32_pcix , + m68k_op_suba_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + 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, + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_1010 , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi7 , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd7 , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_aw , + m68k_op_cmp_8_al , + m68k_op_cmp_8_pcdi , + m68k_op_cmp_8_pcix , + m68k_op_cmp_8_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_aw , + m68k_op_cmp_16_al , + m68k_op_cmp_16_pcdi , + m68k_op_cmp_16_pcix , + m68k_op_cmp_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_aw , + m68k_op_cmp_32_al , + m68k_op_cmp_32_pcdi , + m68k_op_cmp_32_pcix , + m68k_op_cmp_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_aw , + m68k_op_cmpa_16_al , + m68k_op_cmpa_16_pcdi , + m68k_op_cmpa_16_pcix , + m68k_op_cmpa_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8_ay7 , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi7 , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd7 , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_aw , + m68k_op_eor_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_aw , + m68k_op_eor_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_aw , + m68k_op_eor_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_aw , + m68k_op_cmpa_32_al , + m68k_op_cmpa_32_pcdi , + m68k_op_cmpa_32_pcix , + m68k_op_cmpa_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi7 , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd7 , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_aw , + m68k_op_cmp_8_al , + m68k_op_cmp_8_pcdi , + m68k_op_cmp_8_pcix , + m68k_op_cmp_8_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_aw , + m68k_op_cmp_16_al , + m68k_op_cmp_16_pcdi , + m68k_op_cmp_16_pcix , + m68k_op_cmp_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_aw , + m68k_op_cmp_32_al , + m68k_op_cmp_32_pcdi , + m68k_op_cmp_32_pcix , + m68k_op_cmp_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_aw , + m68k_op_cmpa_16_al , + m68k_op_cmpa_16_pcdi , + m68k_op_cmpa_16_pcix , + m68k_op_cmpa_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8_ay7 , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi7 , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd7 , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_aw , + m68k_op_eor_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_aw , + m68k_op_eor_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_aw , + m68k_op_eor_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_aw , + m68k_op_cmpa_32_al , + m68k_op_cmpa_32_pcdi , + m68k_op_cmpa_32_pcix , + m68k_op_cmpa_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi7 , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd7 , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_aw , + m68k_op_cmp_8_al , + m68k_op_cmp_8_pcdi , + m68k_op_cmp_8_pcix , + m68k_op_cmp_8_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_aw , + m68k_op_cmp_16_al , + m68k_op_cmp_16_pcdi , + m68k_op_cmp_16_pcix , + m68k_op_cmp_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_aw , + m68k_op_cmp_32_al , + m68k_op_cmp_32_pcdi , + m68k_op_cmp_32_pcix , + m68k_op_cmp_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_aw , + m68k_op_cmpa_16_al , + m68k_op_cmpa_16_pcdi , + m68k_op_cmpa_16_pcix , + m68k_op_cmpa_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8_ay7 , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi7 , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd7 , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_aw , + m68k_op_eor_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_aw , + m68k_op_eor_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_aw , + m68k_op_eor_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_aw , + m68k_op_cmpa_32_al , + m68k_op_cmpa_32_pcdi , + m68k_op_cmpa_32_pcix , + m68k_op_cmpa_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi7 , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd7 , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_aw , + m68k_op_cmp_8_al , + m68k_op_cmp_8_pcdi , + m68k_op_cmp_8_pcix , + m68k_op_cmp_8_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_aw , + m68k_op_cmp_16_al , + m68k_op_cmp_16_pcdi , + m68k_op_cmp_16_pcix , + m68k_op_cmp_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_aw , + m68k_op_cmp_32_al , + m68k_op_cmp_32_pcdi , + m68k_op_cmp_32_pcix , + m68k_op_cmp_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_aw , + m68k_op_cmpa_16_al , + m68k_op_cmpa_16_pcdi , + m68k_op_cmpa_16_pcix , + m68k_op_cmpa_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8_ay7 , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi7 , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd7 , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_aw , + m68k_op_eor_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_aw , + m68k_op_eor_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_aw , + m68k_op_eor_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_aw , + m68k_op_cmpa_32_al , + m68k_op_cmpa_32_pcdi , + m68k_op_cmpa_32_pcix , + m68k_op_cmpa_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi7 , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd7 , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_aw , + m68k_op_cmp_8_al , + m68k_op_cmp_8_pcdi , + m68k_op_cmp_8_pcix , + m68k_op_cmp_8_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_aw , + m68k_op_cmp_16_al , + m68k_op_cmp_16_pcdi , + m68k_op_cmp_16_pcix , + m68k_op_cmp_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_aw , + m68k_op_cmp_32_al , + m68k_op_cmp_32_pcdi , + m68k_op_cmp_32_pcix , + m68k_op_cmp_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_aw , + m68k_op_cmpa_16_al , + m68k_op_cmpa_16_pcdi , + m68k_op_cmpa_16_pcix , + m68k_op_cmpa_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8_ay7 , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi7 , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd7 , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_aw , + m68k_op_eor_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_aw , + m68k_op_eor_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_aw , + m68k_op_eor_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_aw , + m68k_op_cmpa_32_al , + m68k_op_cmpa_32_pcdi , + m68k_op_cmpa_32_pcix , + m68k_op_cmpa_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi7 , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd7 , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_aw , + m68k_op_cmp_8_al , + m68k_op_cmp_8_pcdi , + m68k_op_cmp_8_pcix , + m68k_op_cmp_8_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_aw , + m68k_op_cmp_16_al , + m68k_op_cmp_16_pcdi , + m68k_op_cmp_16_pcix , + m68k_op_cmp_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_aw , + m68k_op_cmp_32_al , + m68k_op_cmp_32_pcdi , + m68k_op_cmp_32_pcix , + m68k_op_cmp_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_aw , + m68k_op_cmpa_16_al , + m68k_op_cmpa_16_pcdi , + m68k_op_cmpa_16_pcix , + m68k_op_cmpa_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8_ay7 , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi7 , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd7 , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_aw , + m68k_op_eor_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_aw , + m68k_op_eor_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_aw , + m68k_op_eor_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_aw , + m68k_op_cmpa_32_al , + m68k_op_cmpa_32_pcdi , + m68k_op_cmpa_32_pcix , + m68k_op_cmpa_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi7 , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd7 , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_aw , + m68k_op_cmp_8_al , + m68k_op_cmp_8_pcdi , + m68k_op_cmp_8_pcix , + m68k_op_cmp_8_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_aw , + m68k_op_cmp_16_al , + m68k_op_cmp_16_pcdi , + m68k_op_cmp_16_pcix , + m68k_op_cmp_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_aw , + m68k_op_cmp_32_al , + m68k_op_cmp_32_pcdi , + m68k_op_cmp_32_pcix , + m68k_op_cmp_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_aw , + m68k_op_cmpa_16_al , + m68k_op_cmpa_16_pcdi , + m68k_op_cmpa_16_pcix , + m68k_op_cmpa_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8 , + m68k_op_cmpm_8_ay7 , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi7 , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd7 , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_aw , + m68k_op_eor_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_aw , + m68k_op_eor_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_aw , + m68k_op_eor_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_aw , + m68k_op_cmpa_32_al , + m68k_op_cmpa_32_pcdi , + m68k_op_cmpa_32_pcix , + m68k_op_cmpa_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_cmp_8_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_ai , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi , + m68k_op_cmp_8_pi7 , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd , + m68k_op_cmp_8_pd7 , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_di , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_ix , + m68k_op_cmp_8_aw , + m68k_op_cmp_8_al , + m68k_op_cmp_8_pcdi , + m68k_op_cmp_8_pcix , + m68k_op_cmp_8_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_d , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_a , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_ai , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pi , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_pd , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_di , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_ix , + m68k_op_cmp_16_aw , + m68k_op_cmp_16_al , + m68k_op_cmp_16_pcdi , + m68k_op_cmp_16_pcix , + m68k_op_cmp_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_d , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_a , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_ai , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pi , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_pd , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_di , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_ix , + m68k_op_cmp_32_aw , + m68k_op_cmp_32_al , + m68k_op_cmp_32_pcdi , + m68k_op_cmp_32_pcix , + m68k_op_cmp_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_d , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_a , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_ai , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pi , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_pd , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_di , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_ix , + m68k_op_cmpa_16_aw , + m68k_op_cmpa_16_al , + m68k_op_cmpa_16_pcdi , + m68k_op_cmpa_16_pcix , + m68k_op_cmpa_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_eor_8_d , + m68k_op_cmpm_8_ax7 , + m68k_op_cmpm_8_ax7 , + m68k_op_cmpm_8_ax7 , + m68k_op_cmpm_8_ax7 , + m68k_op_cmpm_8_ax7 , + m68k_op_cmpm_8_ax7 , + m68k_op_cmpm_8_ax7 , + m68k_op_cmpm_8_axy7 , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_ai , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi , + m68k_op_eor_8_pi7 , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd , + m68k_op_eor_8_pd7 , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_di , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_ix , + m68k_op_eor_8_aw , + m68k_op_eor_8_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_eor_16_d , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_cmpm_16 , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_ai , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pi , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_pd , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_di , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_ix , + m68k_op_eor_16_aw , + m68k_op_eor_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_eor_32_d , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_cmpm_32 , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_ai , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pi , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_pd , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_di , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_ix , + m68k_op_eor_32_aw , + m68k_op_eor_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_d , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_a , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_ai , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pi , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_pd , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_di , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_ix , + m68k_op_cmpa_32_aw , + m68k_op_cmpa_32_al , + m68k_op_cmpa_32_pcdi , + m68k_op_cmpa_32_pcix , + m68k_op_cmpa_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi7 , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd7 , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_aw , + m68k_op_and_8_er_al , + m68k_op_and_8_er_pcdi , + m68k_op_and_8_er_pcix , + m68k_op_and_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_aw , + m68k_op_and_16_er_al , + m68k_op_and_16_er_pcdi , + m68k_op_and_16_er_pcix , + m68k_op_and_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_aw , + m68k_op_and_32_er_al , + m68k_op_and_32_er_pcdi , + m68k_op_and_32_er_pcix , + m68k_op_and_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_aw , + m68k_op_mulu_16_al , + m68k_op_mulu_16_pcdi , + m68k_op_mulu_16_pcix , + m68k_op_mulu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm_ay7 , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi7 , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd7 , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_aw , + m68k_op_and_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_aw , + m68k_op_and_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_aw , + m68k_op_and_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_aw , + m68k_op_muls_16_al , + m68k_op_muls_16_pcdi , + m68k_op_muls_16_pcix , + m68k_op_muls_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi7 , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd7 , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_aw , + m68k_op_and_8_er_al , + m68k_op_and_8_er_pcdi , + m68k_op_and_8_er_pcix , + m68k_op_and_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_aw , + m68k_op_and_16_er_al , + m68k_op_and_16_er_pcdi , + m68k_op_and_16_er_pcix , + m68k_op_and_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_aw , + m68k_op_and_32_er_al , + m68k_op_and_32_er_pcdi , + m68k_op_and_32_er_pcix , + m68k_op_and_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_aw , + m68k_op_mulu_16_al , + m68k_op_mulu_16_pcdi , + m68k_op_mulu_16_pcix , + m68k_op_mulu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm_ay7 , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi7 , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd7 , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_aw , + m68k_op_and_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_aw , + m68k_op_and_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_aw , + m68k_op_and_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_aw , + m68k_op_muls_16_al , + m68k_op_muls_16_pcdi , + m68k_op_muls_16_pcix , + m68k_op_muls_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi7 , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd7 , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_aw , + m68k_op_and_8_er_al , + m68k_op_and_8_er_pcdi , + m68k_op_and_8_er_pcix , + m68k_op_and_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_aw , + m68k_op_and_16_er_al , + m68k_op_and_16_er_pcdi , + m68k_op_and_16_er_pcix , + m68k_op_and_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_aw , + m68k_op_and_32_er_al , + m68k_op_and_32_er_pcdi , + m68k_op_and_32_er_pcix , + m68k_op_and_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_aw , + m68k_op_mulu_16_al , + m68k_op_mulu_16_pcdi , + m68k_op_mulu_16_pcix , + m68k_op_mulu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm_ay7 , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi7 , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd7 , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_aw , + m68k_op_and_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_aw , + m68k_op_and_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_aw , + m68k_op_and_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_aw , + m68k_op_muls_16_al , + m68k_op_muls_16_pcdi , + m68k_op_muls_16_pcix , + m68k_op_muls_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi7 , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd7 , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_aw , + m68k_op_and_8_er_al , + m68k_op_and_8_er_pcdi , + m68k_op_and_8_er_pcix , + m68k_op_and_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_aw , + m68k_op_and_16_er_al , + m68k_op_and_16_er_pcdi , + m68k_op_and_16_er_pcix , + m68k_op_and_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_aw , + m68k_op_and_32_er_al , + m68k_op_and_32_er_pcdi , + m68k_op_and_32_er_pcix , + m68k_op_and_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_aw , + m68k_op_mulu_16_al , + m68k_op_mulu_16_pcdi , + m68k_op_mulu_16_pcix , + m68k_op_mulu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm_ay7 , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi7 , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd7 , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_aw , + m68k_op_and_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_aw , + m68k_op_and_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_aw , + m68k_op_and_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_aw , + m68k_op_muls_16_al , + m68k_op_muls_16_pcdi , + m68k_op_muls_16_pcix , + m68k_op_muls_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi7 , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd7 , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_aw , + m68k_op_and_8_er_al , + m68k_op_and_8_er_pcdi , + m68k_op_and_8_er_pcix , + m68k_op_and_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_aw , + m68k_op_and_16_er_al , + m68k_op_and_16_er_pcdi , + m68k_op_and_16_er_pcix , + m68k_op_and_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_aw , + m68k_op_and_32_er_al , + m68k_op_and_32_er_pcdi , + m68k_op_and_32_er_pcix , + m68k_op_and_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_aw , + m68k_op_mulu_16_al , + m68k_op_mulu_16_pcdi , + m68k_op_mulu_16_pcix , + m68k_op_mulu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm_ay7 , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi7 , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd7 , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_aw , + m68k_op_and_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_aw , + m68k_op_and_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_aw , + m68k_op_and_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_aw , + m68k_op_muls_16_al , + m68k_op_muls_16_pcdi , + m68k_op_muls_16_pcix , + m68k_op_muls_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi7 , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd7 , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_aw , + m68k_op_and_8_er_al , + m68k_op_and_8_er_pcdi , + m68k_op_and_8_er_pcix , + m68k_op_and_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_aw , + m68k_op_and_16_er_al , + m68k_op_and_16_er_pcdi , + m68k_op_and_16_er_pcix , + m68k_op_and_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_aw , + m68k_op_and_32_er_al , + m68k_op_and_32_er_pcdi , + m68k_op_and_32_er_pcix , + m68k_op_and_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_aw , + m68k_op_mulu_16_al , + m68k_op_mulu_16_pcdi , + m68k_op_mulu_16_pcix , + m68k_op_mulu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm_ay7 , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi7 , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd7 , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_aw , + m68k_op_and_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_aw , + m68k_op_and_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_aw , + m68k_op_and_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_aw , + m68k_op_muls_16_al , + m68k_op_muls_16_pcdi , + m68k_op_muls_16_pcix , + m68k_op_muls_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi7 , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd7 , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_aw , + m68k_op_and_8_er_al , + m68k_op_and_8_er_pcdi , + m68k_op_and_8_er_pcix , + m68k_op_and_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_aw , + m68k_op_and_16_er_al , + m68k_op_and_16_er_pcdi , + m68k_op_and_16_er_pcix , + m68k_op_and_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_aw , + m68k_op_and_32_er_al , + m68k_op_and_32_er_pcdi , + m68k_op_and_32_er_pcix , + m68k_op_and_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_aw , + m68k_op_mulu_16_al , + m68k_op_mulu_16_pcdi , + m68k_op_mulu_16_pcix , + m68k_op_mulu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm , + m68k_op_abcd_8_mm_ay7 , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi7 , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd7 , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_aw , + m68k_op_and_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_aw , + m68k_op_and_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_aw , + m68k_op_and_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_aw , + m68k_op_muls_16_al , + m68k_op_muls_16_pcdi , + m68k_op_muls_16_pcix , + m68k_op_muls_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_and_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_ai , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi , + m68k_op_and_8_er_pi7 , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd , + m68k_op_and_8_er_pd7 , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_di , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_ix , + m68k_op_and_8_er_aw , + m68k_op_and_8_er_al , + m68k_op_and_8_er_pcdi , + m68k_op_and_8_er_pcix , + m68k_op_and_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_and_16_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_ai , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pi , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_pd , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_di , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_ix , + m68k_op_and_16_er_aw , + m68k_op_and_16_er_al , + m68k_op_and_16_er_pcdi , + m68k_op_and_16_er_pcix , + m68k_op_and_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_and_32_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_ai , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pi , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_pd , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_di , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_ix , + m68k_op_and_32_er_aw , + m68k_op_and_32_er_al , + m68k_op_and_32_er_pcdi , + m68k_op_and_32_er_pcix , + m68k_op_and_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_mulu_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_ai , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pi , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_pd , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_di , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_ix , + m68k_op_mulu_16_aw , + m68k_op_mulu_16_al , + m68k_op_mulu_16_pcdi , + m68k_op_mulu_16_pcix , + m68k_op_mulu_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_rr , + m68k_op_abcd_8_mm_ax7 , + m68k_op_abcd_8_mm_ax7 , + m68k_op_abcd_8_mm_ax7 , + m68k_op_abcd_8_mm_ax7 , + m68k_op_abcd_8_mm_ax7 , + m68k_op_abcd_8_mm_ax7 , + m68k_op_abcd_8_mm_ax7 , + m68k_op_abcd_8_mm_axy7 , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_ai , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi , + m68k_op_and_8_re_pi7 , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd , + m68k_op_and_8_re_pd7 , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_di , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_ix , + m68k_op_and_8_re_aw , + m68k_op_and_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_dd , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_exg_32_aa , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_ai , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pi , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_pd , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_di , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_ix , + m68k_op_and_16_re_aw , + m68k_op_and_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_exg_32_da , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_ai , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pi , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_pd , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_di , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_ix , + m68k_op_and_32_re_aw , + m68k_op_and_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_muls_16_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_ai , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pi , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_pd , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_di , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_ix , + m68k_op_muls_16_aw , + m68k_op_muls_16_al , + m68k_op_muls_16_pcdi , + m68k_op_muls_16_pcix , + m68k_op_muls_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi7 , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd7 , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_aw , + m68k_op_add_8_er_al , + m68k_op_add_8_er_pcdi , + m68k_op_add_8_er_pcix , + m68k_op_add_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_aw , + m68k_op_add_16_er_al , + m68k_op_add_16_er_pcdi , + m68k_op_add_16_er_pcix , + m68k_op_add_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_aw , + m68k_op_add_32_er_al , + m68k_op_add_32_er_pcdi , + m68k_op_add_32_er_pcix , + m68k_op_add_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_aw , + m68k_op_adda_16_al , + m68k_op_adda_16_pcdi , + m68k_op_adda_16_pcix , + m68k_op_adda_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm_ay7 , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi7 , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd7 , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_aw , + m68k_op_add_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_aw , + m68k_op_add_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_aw , + m68k_op_add_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_aw , + m68k_op_adda_32_al , + m68k_op_adda_32_pcdi , + m68k_op_adda_32_pcix , + m68k_op_adda_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi7 , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd7 , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_aw , + m68k_op_add_8_er_al , + m68k_op_add_8_er_pcdi , + m68k_op_add_8_er_pcix , + m68k_op_add_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_aw , + m68k_op_add_16_er_al , + m68k_op_add_16_er_pcdi , + m68k_op_add_16_er_pcix , + m68k_op_add_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_aw , + m68k_op_add_32_er_al , + m68k_op_add_32_er_pcdi , + m68k_op_add_32_er_pcix , + m68k_op_add_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_aw , + m68k_op_adda_16_al , + m68k_op_adda_16_pcdi , + m68k_op_adda_16_pcix , + m68k_op_adda_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm_ay7 , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi7 , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd7 , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_aw , + m68k_op_add_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_aw , + m68k_op_add_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_aw , + m68k_op_add_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_aw , + m68k_op_adda_32_al , + m68k_op_adda_32_pcdi , + m68k_op_adda_32_pcix , + m68k_op_adda_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi7 , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd7 , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_aw , + m68k_op_add_8_er_al , + m68k_op_add_8_er_pcdi , + m68k_op_add_8_er_pcix , + m68k_op_add_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_aw , + m68k_op_add_16_er_al , + m68k_op_add_16_er_pcdi , + m68k_op_add_16_er_pcix , + m68k_op_add_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_aw , + m68k_op_add_32_er_al , + m68k_op_add_32_er_pcdi , + m68k_op_add_32_er_pcix , + m68k_op_add_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_aw , + m68k_op_adda_16_al , + m68k_op_adda_16_pcdi , + m68k_op_adda_16_pcix , + m68k_op_adda_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm_ay7 , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi7 , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd7 , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_aw , + m68k_op_add_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_aw , + m68k_op_add_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_aw , + m68k_op_add_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_aw , + m68k_op_adda_32_al , + m68k_op_adda_32_pcdi , + m68k_op_adda_32_pcix , + m68k_op_adda_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi7 , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd7 , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_aw , + m68k_op_add_8_er_al , + m68k_op_add_8_er_pcdi , + m68k_op_add_8_er_pcix , + m68k_op_add_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_aw , + m68k_op_add_16_er_al , + m68k_op_add_16_er_pcdi , + m68k_op_add_16_er_pcix , + m68k_op_add_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_aw , + m68k_op_add_32_er_al , + m68k_op_add_32_er_pcdi , + m68k_op_add_32_er_pcix , + m68k_op_add_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_aw , + m68k_op_adda_16_al , + m68k_op_adda_16_pcdi , + m68k_op_adda_16_pcix , + m68k_op_adda_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm_ay7 , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi7 , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd7 , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_aw , + m68k_op_add_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_aw , + m68k_op_add_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_aw , + m68k_op_add_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_aw , + m68k_op_adda_32_al , + m68k_op_adda_32_pcdi , + m68k_op_adda_32_pcix , + m68k_op_adda_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi7 , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd7 , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_aw , + m68k_op_add_8_er_al , + m68k_op_add_8_er_pcdi , + m68k_op_add_8_er_pcix , + m68k_op_add_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_aw , + m68k_op_add_16_er_al , + m68k_op_add_16_er_pcdi , + m68k_op_add_16_er_pcix , + m68k_op_add_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_aw , + m68k_op_add_32_er_al , + m68k_op_add_32_er_pcdi , + m68k_op_add_32_er_pcix , + m68k_op_add_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_aw , + m68k_op_adda_16_al , + m68k_op_adda_16_pcdi , + m68k_op_adda_16_pcix , + m68k_op_adda_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm_ay7 , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi7 , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd7 , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_aw , + m68k_op_add_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_aw , + m68k_op_add_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_aw , + m68k_op_add_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_aw , + m68k_op_adda_32_al , + m68k_op_adda_32_pcdi , + m68k_op_adda_32_pcix , + m68k_op_adda_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi7 , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd7 , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_aw , + m68k_op_add_8_er_al , + m68k_op_add_8_er_pcdi , + m68k_op_add_8_er_pcix , + m68k_op_add_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_aw , + m68k_op_add_16_er_al , + m68k_op_add_16_er_pcdi , + m68k_op_add_16_er_pcix , + m68k_op_add_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_aw , + m68k_op_add_32_er_al , + m68k_op_add_32_er_pcdi , + m68k_op_add_32_er_pcix , + m68k_op_add_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_aw , + m68k_op_adda_16_al , + m68k_op_adda_16_pcdi , + m68k_op_adda_16_pcix , + m68k_op_adda_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm_ay7 , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi7 , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd7 , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_aw , + m68k_op_add_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_aw , + m68k_op_add_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_aw , + m68k_op_add_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_aw , + m68k_op_adda_32_al , + m68k_op_adda_32_pcdi , + m68k_op_adda_32_pcix , + m68k_op_adda_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi7 , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd7 , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_aw , + m68k_op_add_8_er_al , + m68k_op_add_8_er_pcdi , + m68k_op_add_8_er_pcix , + m68k_op_add_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_aw , + m68k_op_add_16_er_al , + m68k_op_add_16_er_pcdi , + m68k_op_add_16_er_pcix , + m68k_op_add_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_aw , + m68k_op_add_32_er_al , + m68k_op_add_32_er_pcdi , + m68k_op_add_32_er_pcix , + m68k_op_add_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_aw , + m68k_op_adda_16_al , + m68k_op_adda_16_pcdi , + m68k_op_adda_16_pcix , + m68k_op_adda_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm , + m68k_op_addx_8_mm_ay7 , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi7 , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd7 , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_aw , + m68k_op_add_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_aw , + m68k_op_add_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_aw , + m68k_op_add_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_aw , + m68k_op_adda_32_al , + m68k_op_adda_32_pcdi , + m68k_op_adda_32_pcix , + m68k_op_adda_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_add_8_er_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_ai , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi , + m68k_op_add_8_er_pi7 , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd , + m68k_op_add_8_er_pd7 , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_di , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_ix , + m68k_op_add_8_er_aw , + m68k_op_add_8_er_al , + m68k_op_add_8_er_pcdi , + m68k_op_add_8_er_pcix , + m68k_op_add_8_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_d , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_a , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_ai , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pi , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_pd , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_di , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_ix , + m68k_op_add_16_er_aw , + m68k_op_add_16_er_al , + m68k_op_add_16_er_pcdi , + m68k_op_add_16_er_pcix , + m68k_op_add_16_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_d , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_a , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_ai , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pi , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_pd , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_di , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_ix , + m68k_op_add_32_er_aw , + m68k_op_add_32_er_al , + m68k_op_add_32_er_pcdi , + m68k_op_add_32_er_pcix , + m68k_op_add_32_er_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_d , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_a , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_ai , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pi , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_pd , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_di , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_ix , + m68k_op_adda_16_aw , + m68k_op_adda_16_al , + m68k_op_adda_16_pcdi , + m68k_op_adda_16_pcix , + m68k_op_adda_16_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_rr , + m68k_op_addx_8_mm_ax7 , + m68k_op_addx_8_mm_ax7 , + m68k_op_addx_8_mm_ax7 , + m68k_op_addx_8_mm_ax7 , + m68k_op_addx_8_mm_ax7 , + m68k_op_addx_8_mm_ax7 , + m68k_op_addx_8_mm_ax7 , + m68k_op_addx_8_mm_axy7 , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_ai , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi , + m68k_op_add_8_re_pi7 , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd , + m68k_op_add_8_re_pd7 , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_di , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_ix , + m68k_op_add_8_re_aw , + m68k_op_add_8_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_rr , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_addx_16_mm , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_ai , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pi , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_pd , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_di , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_ix , + m68k_op_add_16_re_aw , + m68k_op_add_16_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_rr , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_addx_32_mm , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_ai , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pi , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_pd , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_di , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_ix , + m68k_op_add_32_re_aw , + m68k_op_add_32_re_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_d , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_a , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_ai , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pi , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_pd , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_di , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_ix , + m68k_op_adda_32_aw , + m68k_op_adda_32_al , + m68k_op_adda_32_pcdi , + m68k_op_adda_32_pcix , + m68k_op_adda_32_i , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asr_16_ai , + m68k_op_asr_16_ai , + m68k_op_asr_16_ai , + m68k_op_asr_16_ai , + m68k_op_asr_16_ai , + m68k_op_asr_16_ai , + m68k_op_asr_16_ai , + m68k_op_asr_16_ai , + m68k_op_asr_16_pi , + m68k_op_asr_16_pi , + m68k_op_asr_16_pi , + m68k_op_asr_16_pi , + m68k_op_asr_16_pi , + m68k_op_asr_16_pi , + m68k_op_asr_16_pi , + m68k_op_asr_16_pi , + m68k_op_asr_16_pd , + m68k_op_asr_16_pd , + m68k_op_asr_16_pd , + m68k_op_asr_16_pd , + m68k_op_asr_16_pd , + m68k_op_asr_16_pd , + m68k_op_asr_16_pd , + m68k_op_asr_16_pd , + m68k_op_asr_16_di , + m68k_op_asr_16_di , + m68k_op_asr_16_di , + m68k_op_asr_16_di , + m68k_op_asr_16_di , + m68k_op_asr_16_di , + m68k_op_asr_16_di , + m68k_op_asr_16_di , + m68k_op_asr_16_ix , + m68k_op_asr_16_ix , + m68k_op_asr_16_ix , + m68k_op_asr_16_ix , + m68k_op_asr_16_ix , + m68k_op_asr_16_ix , + m68k_op_asr_16_ix , + m68k_op_asr_16_ix , + m68k_op_asr_16_aw , + m68k_op_asr_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asl_16_ai , + m68k_op_asl_16_ai , + m68k_op_asl_16_ai , + m68k_op_asl_16_ai , + m68k_op_asl_16_ai , + m68k_op_asl_16_ai , + m68k_op_asl_16_ai , + m68k_op_asl_16_ai , + m68k_op_asl_16_pi , + m68k_op_asl_16_pi , + m68k_op_asl_16_pi , + m68k_op_asl_16_pi , + m68k_op_asl_16_pi , + m68k_op_asl_16_pi , + m68k_op_asl_16_pi , + m68k_op_asl_16_pi , + m68k_op_asl_16_pd , + m68k_op_asl_16_pd , + m68k_op_asl_16_pd , + m68k_op_asl_16_pd , + m68k_op_asl_16_pd , + m68k_op_asl_16_pd , + m68k_op_asl_16_pd , + m68k_op_asl_16_pd , + m68k_op_asl_16_di , + m68k_op_asl_16_di , + m68k_op_asl_16_di , + m68k_op_asl_16_di , + m68k_op_asl_16_di , + m68k_op_asl_16_di , + m68k_op_asl_16_di , + m68k_op_asl_16_di , + m68k_op_asl_16_ix , + m68k_op_asl_16_ix , + m68k_op_asl_16_ix , + m68k_op_asl_16_ix , + m68k_op_asl_16_ix , + m68k_op_asl_16_ix , + m68k_op_asl_16_ix , + m68k_op_asl_16_ix , + m68k_op_asl_16_aw , + m68k_op_asl_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lsr_16_ai , + m68k_op_lsr_16_ai , + m68k_op_lsr_16_ai , + m68k_op_lsr_16_ai , + m68k_op_lsr_16_ai , + m68k_op_lsr_16_ai , + m68k_op_lsr_16_ai , + m68k_op_lsr_16_ai , + m68k_op_lsr_16_pi , + m68k_op_lsr_16_pi , + m68k_op_lsr_16_pi , + m68k_op_lsr_16_pi , + m68k_op_lsr_16_pi , + m68k_op_lsr_16_pi , + m68k_op_lsr_16_pi , + m68k_op_lsr_16_pi , + m68k_op_lsr_16_pd , + m68k_op_lsr_16_pd , + m68k_op_lsr_16_pd , + m68k_op_lsr_16_pd , + m68k_op_lsr_16_pd , + m68k_op_lsr_16_pd , + m68k_op_lsr_16_pd , + m68k_op_lsr_16_pd , + m68k_op_lsr_16_di , + m68k_op_lsr_16_di , + m68k_op_lsr_16_di , + m68k_op_lsr_16_di , + m68k_op_lsr_16_di , + m68k_op_lsr_16_di , + m68k_op_lsr_16_di , + m68k_op_lsr_16_di , + m68k_op_lsr_16_ix , + m68k_op_lsr_16_ix , + m68k_op_lsr_16_ix , + m68k_op_lsr_16_ix , + m68k_op_lsr_16_ix , + m68k_op_lsr_16_ix , + m68k_op_lsr_16_ix , + m68k_op_lsr_16_ix , + m68k_op_lsr_16_aw , + m68k_op_lsr_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_lsl_16_ai , + m68k_op_lsl_16_ai , + m68k_op_lsl_16_ai , + m68k_op_lsl_16_ai , + m68k_op_lsl_16_ai , + m68k_op_lsl_16_ai , + m68k_op_lsl_16_ai , + m68k_op_lsl_16_ai , + m68k_op_lsl_16_pi , + m68k_op_lsl_16_pi , + m68k_op_lsl_16_pi , + m68k_op_lsl_16_pi , + m68k_op_lsl_16_pi , + m68k_op_lsl_16_pi , + m68k_op_lsl_16_pi , + m68k_op_lsl_16_pi , + m68k_op_lsl_16_pd , + m68k_op_lsl_16_pd , + m68k_op_lsl_16_pd , + m68k_op_lsl_16_pd , + m68k_op_lsl_16_pd , + m68k_op_lsl_16_pd , + m68k_op_lsl_16_pd , + m68k_op_lsl_16_pd , + m68k_op_lsl_16_di , + m68k_op_lsl_16_di , + m68k_op_lsl_16_di , + m68k_op_lsl_16_di , + m68k_op_lsl_16_di , + m68k_op_lsl_16_di , + m68k_op_lsl_16_di , + m68k_op_lsl_16_di , + m68k_op_lsl_16_ix , + m68k_op_lsl_16_ix , + m68k_op_lsl_16_ix , + m68k_op_lsl_16_ix , + m68k_op_lsl_16_ix , + m68k_op_lsl_16_ix , + m68k_op_lsl_16_ix , + m68k_op_lsl_16_ix , + m68k_op_lsl_16_aw , + m68k_op_lsl_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_roxr_16_ai , + m68k_op_roxr_16_ai , + m68k_op_roxr_16_ai , + m68k_op_roxr_16_ai , + m68k_op_roxr_16_ai , + m68k_op_roxr_16_ai , + m68k_op_roxr_16_ai , + m68k_op_roxr_16_ai , + m68k_op_roxr_16_pi , + m68k_op_roxr_16_pi , + m68k_op_roxr_16_pi , + m68k_op_roxr_16_pi , + m68k_op_roxr_16_pi , + m68k_op_roxr_16_pi , + m68k_op_roxr_16_pi , + m68k_op_roxr_16_pi , + m68k_op_roxr_16_pd , + m68k_op_roxr_16_pd , + m68k_op_roxr_16_pd , + m68k_op_roxr_16_pd , + m68k_op_roxr_16_pd , + m68k_op_roxr_16_pd , + m68k_op_roxr_16_pd , + m68k_op_roxr_16_pd , + m68k_op_roxr_16_di , + m68k_op_roxr_16_di , + m68k_op_roxr_16_di , + m68k_op_roxr_16_di , + m68k_op_roxr_16_di , + m68k_op_roxr_16_di , + m68k_op_roxr_16_di , + m68k_op_roxr_16_di , + m68k_op_roxr_16_ix , + m68k_op_roxr_16_ix , + m68k_op_roxr_16_ix , + m68k_op_roxr_16_ix , + m68k_op_roxr_16_ix , + m68k_op_roxr_16_ix , + m68k_op_roxr_16_ix , + m68k_op_roxr_16_ix , + m68k_op_roxr_16_aw , + m68k_op_roxr_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_roxl_16_ai , + m68k_op_roxl_16_ai , + m68k_op_roxl_16_ai , + m68k_op_roxl_16_ai , + m68k_op_roxl_16_ai , + m68k_op_roxl_16_ai , + m68k_op_roxl_16_ai , + m68k_op_roxl_16_ai , + m68k_op_roxl_16_pi , + m68k_op_roxl_16_pi , + m68k_op_roxl_16_pi , + m68k_op_roxl_16_pi , + m68k_op_roxl_16_pi , + m68k_op_roxl_16_pi , + m68k_op_roxl_16_pi , + m68k_op_roxl_16_pi , + m68k_op_roxl_16_pd , + m68k_op_roxl_16_pd , + m68k_op_roxl_16_pd , + m68k_op_roxl_16_pd , + m68k_op_roxl_16_pd , + m68k_op_roxl_16_pd , + m68k_op_roxl_16_pd , + m68k_op_roxl_16_pd , + m68k_op_roxl_16_di , + m68k_op_roxl_16_di , + m68k_op_roxl_16_di , + m68k_op_roxl_16_di , + m68k_op_roxl_16_di , + m68k_op_roxl_16_di , + m68k_op_roxl_16_di , + m68k_op_roxl_16_di , + m68k_op_roxl_16_ix , + m68k_op_roxl_16_ix , + m68k_op_roxl_16_ix , + m68k_op_roxl_16_ix , + m68k_op_roxl_16_ix , + m68k_op_roxl_16_ix , + m68k_op_roxl_16_ix , + m68k_op_roxl_16_ix , + m68k_op_roxl_16_aw , + m68k_op_roxl_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_ror_16_ai , + m68k_op_ror_16_ai , + m68k_op_ror_16_ai , + m68k_op_ror_16_ai , + m68k_op_ror_16_ai , + m68k_op_ror_16_ai , + m68k_op_ror_16_ai , + m68k_op_ror_16_ai , + m68k_op_ror_16_pi , + m68k_op_ror_16_pi , + m68k_op_ror_16_pi , + m68k_op_ror_16_pi , + m68k_op_ror_16_pi , + m68k_op_ror_16_pi , + m68k_op_ror_16_pi , + m68k_op_ror_16_pi , + m68k_op_ror_16_pd , + m68k_op_ror_16_pd , + m68k_op_ror_16_pd , + m68k_op_ror_16_pd , + m68k_op_ror_16_pd , + m68k_op_ror_16_pd , + m68k_op_ror_16_pd , + m68k_op_ror_16_pd , + m68k_op_ror_16_di , + m68k_op_ror_16_di , + m68k_op_ror_16_di , + m68k_op_ror_16_di , + m68k_op_ror_16_di , + m68k_op_ror_16_di , + m68k_op_ror_16_di , + m68k_op_ror_16_di , + m68k_op_ror_16_ix , + m68k_op_ror_16_ix , + m68k_op_ror_16_ix , + m68k_op_ror_16_ix , + m68k_op_ror_16_ix , + m68k_op_ror_16_ix , + m68k_op_ror_16_ix , + m68k_op_ror_16_ix , + m68k_op_ror_16_aw , + m68k_op_ror_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_rol_16_ai , + m68k_op_rol_16_ai , + m68k_op_rol_16_ai , + m68k_op_rol_16_ai , + m68k_op_rol_16_ai , + m68k_op_rol_16_ai , + m68k_op_rol_16_ai , + m68k_op_rol_16_ai , + m68k_op_rol_16_pi , + m68k_op_rol_16_pi , + m68k_op_rol_16_pi , + m68k_op_rol_16_pi , + m68k_op_rol_16_pi , + m68k_op_rol_16_pi , + m68k_op_rol_16_pi , + m68k_op_rol_16_pi , + m68k_op_rol_16_pd , + m68k_op_rol_16_pd , + m68k_op_rol_16_pd , + m68k_op_rol_16_pd , + m68k_op_rol_16_pd , + m68k_op_rol_16_pd , + m68k_op_rol_16_pd , + m68k_op_rol_16_pd , + m68k_op_rol_16_di , + m68k_op_rol_16_di , + m68k_op_rol_16_di , + m68k_op_rol_16_di , + m68k_op_rol_16_di , + m68k_op_rol_16_di , + m68k_op_rol_16_di , + m68k_op_rol_16_di , + m68k_op_rol_16_ix , + m68k_op_rol_16_ix , + m68k_op_rol_16_ix , + m68k_op_rol_16_ix , + m68k_op_rol_16_ix , + m68k_op_rol_16_ix , + m68k_op_rol_16_ix , + m68k_op_rol_16_ix , + m68k_op_rol_16_aw , + m68k_op_rol_16_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_bftst_32_d , + m68k_op_bftst_32_d , + m68k_op_bftst_32_d , + m68k_op_bftst_32_d , + m68k_op_bftst_32_d , + m68k_op_bftst_32_d , + m68k_op_bftst_32_d , + m68k_op_bftst_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bftst_32_ai , + m68k_op_bftst_32_ai , + m68k_op_bftst_32_ai , + m68k_op_bftst_32_ai , + m68k_op_bftst_32_ai , + m68k_op_bftst_32_ai , + m68k_op_bftst_32_ai , + m68k_op_bftst_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bftst_32_di , + m68k_op_bftst_32_di , + m68k_op_bftst_32_di , + m68k_op_bftst_32_di , + m68k_op_bftst_32_di , + m68k_op_bftst_32_di , + m68k_op_bftst_32_di , + m68k_op_bftst_32_di , + m68k_op_bftst_32_ix , + m68k_op_bftst_32_ix , + m68k_op_bftst_32_ix , + m68k_op_bftst_32_ix , + m68k_op_bftst_32_ix , + m68k_op_bftst_32_ix , + m68k_op_bftst_32_ix , + m68k_op_bftst_32_ix , + m68k_op_bftst_32_aw , + m68k_op_bftst_32_al , + m68k_op_bftst_32_pcdi , + m68k_op_bftst_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_bfextu_32_d , + m68k_op_bfextu_32_d , + m68k_op_bfextu_32_d , + m68k_op_bfextu_32_d , + m68k_op_bfextu_32_d , + m68k_op_bfextu_32_d , + m68k_op_bfextu_32_d , + m68k_op_bfextu_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfextu_32_ai , + m68k_op_bfextu_32_ai , + m68k_op_bfextu_32_ai , + m68k_op_bfextu_32_ai , + m68k_op_bfextu_32_ai , + m68k_op_bfextu_32_ai , + m68k_op_bfextu_32_ai , + m68k_op_bfextu_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfextu_32_di , + m68k_op_bfextu_32_di , + m68k_op_bfextu_32_di , + m68k_op_bfextu_32_di , + m68k_op_bfextu_32_di , + m68k_op_bfextu_32_di , + m68k_op_bfextu_32_di , + m68k_op_bfextu_32_di , + m68k_op_bfextu_32_ix , + m68k_op_bfextu_32_ix , + m68k_op_bfextu_32_ix , + m68k_op_bfextu_32_ix , + m68k_op_bfextu_32_ix , + m68k_op_bfextu_32_ix , + m68k_op_bfextu_32_ix , + m68k_op_bfextu_32_ix , + m68k_op_bfextu_32_aw , + m68k_op_bfextu_32_al , + m68k_op_bfextu_32_pcdi , + m68k_op_bfextu_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_bfchg_32_d , + m68k_op_bfchg_32_d , + m68k_op_bfchg_32_d , + m68k_op_bfchg_32_d , + m68k_op_bfchg_32_d , + m68k_op_bfchg_32_d , + m68k_op_bfchg_32_d , + m68k_op_bfchg_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfchg_32_ai , + m68k_op_bfchg_32_ai , + m68k_op_bfchg_32_ai , + m68k_op_bfchg_32_ai , + m68k_op_bfchg_32_ai , + m68k_op_bfchg_32_ai , + m68k_op_bfchg_32_ai , + m68k_op_bfchg_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfchg_32_di , + m68k_op_bfchg_32_di , + m68k_op_bfchg_32_di , + m68k_op_bfchg_32_di , + m68k_op_bfchg_32_di , + m68k_op_bfchg_32_di , + m68k_op_bfchg_32_di , + m68k_op_bfchg_32_di , + m68k_op_bfchg_32_ix , + m68k_op_bfchg_32_ix , + m68k_op_bfchg_32_ix , + m68k_op_bfchg_32_ix , + m68k_op_bfchg_32_ix , + m68k_op_bfchg_32_ix , + m68k_op_bfchg_32_ix , + m68k_op_bfchg_32_ix , + m68k_op_bfchg_32_aw , + m68k_op_bfchg_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_bfexts_32_d , + m68k_op_bfexts_32_d , + m68k_op_bfexts_32_d , + m68k_op_bfexts_32_d , + m68k_op_bfexts_32_d , + m68k_op_bfexts_32_d , + m68k_op_bfexts_32_d , + m68k_op_bfexts_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfexts_32_ai , + m68k_op_bfexts_32_ai , + m68k_op_bfexts_32_ai , + m68k_op_bfexts_32_ai , + m68k_op_bfexts_32_ai , + m68k_op_bfexts_32_ai , + m68k_op_bfexts_32_ai , + m68k_op_bfexts_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfexts_32_di , + m68k_op_bfexts_32_di , + m68k_op_bfexts_32_di , + m68k_op_bfexts_32_di , + m68k_op_bfexts_32_di , + m68k_op_bfexts_32_di , + m68k_op_bfexts_32_di , + m68k_op_bfexts_32_di , + m68k_op_bfexts_32_ix , + m68k_op_bfexts_32_ix , + m68k_op_bfexts_32_ix , + m68k_op_bfexts_32_ix , + m68k_op_bfexts_32_ix , + m68k_op_bfexts_32_ix , + m68k_op_bfexts_32_ix , + m68k_op_bfexts_32_ix , + m68k_op_bfexts_32_aw , + m68k_op_bfexts_32_al , + m68k_op_bfexts_32_pcdi , + m68k_op_bfexts_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_bfclr_32_d , + m68k_op_bfclr_32_d , + m68k_op_bfclr_32_d , + m68k_op_bfclr_32_d , + m68k_op_bfclr_32_d , + m68k_op_bfclr_32_d , + m68k_op_bfclr_32_d , + m68k_op_bfclr_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfclr_32_ai , + m68k_op_bfclr_32_ai , + m68k_op_bfclr_32_ai , + m68k_op_bfclr_32_ai , + m68k_op_bfclr_32_ai , + m68k_op_bfclr_32_ai , + m68k_op_bfclr_32_ai , + m68k_op_bfclr_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfclr_32_di , + m68k_op_bfclr_32_di , + m68k_op_bfclr_32_di , + m68k_op_bfclr_32_di , + m68k_op_bfclr_32_di , + m68k_op_bfclr_32_di , + m68k_op_bfclr_32_di , + m68k_op_bfclr_32_di , + m68k_op_bfclr_32_ix , + m68k_op_bfclr_32_ix , + m68k_op_bfclr_32_ix , + m68k_op_bfclr_32_ix , + m68k_op_bfclr_32_ix , + m68k_op_bfclr_32_ix , + m68k_op_bfclr_32_ix , + m68k_op_bfclr_32_ix , + m68k_op_bfclr_32_aw , + m68k_op_bfclr_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_bfffo_32_d , + m68k_op_bfffo_32_d , + m68k_op_bfffo_32_d , + m68k_op_bfffo_32_d , + m68k_op_bfffo_32_d , + m68k_op_bfffo_32_d , + m68k_op_bfffo_32_d , + m68k_op_bfffo_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfffo_32_ai , + m68k_op_bfffo_32_ai , + m68k_op_bfffo_32_ai , + m68k_op_bfffo_32_ai , + m68k_op_bfffo_32_ai , + m68k_op_bfffo_32_ai , + m68k_op_bfffo_32_ai , + m68k_op_bfffo_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfffo_32_di , + m68k_op_bfffo_32_di , + m68k_op_bfffo_32_di , + m68k_op_bfffo_32_di , + m68k_op_bfffo_32_di , + m68k_op_bfffo_32_di , + m68k_op_bfffo_32_di , + m68k_op_bfffo_32_di , + m68k_op_bfffo_32_ix , + m68k_op_bfffo_32_ix , + m68k_op_bfffo_32_ix , + m68k_op_bfffo_32_ix , + m68k_op_bfffo_32_ix , + m68k_op_bfffo_32_ix , + m68k_op_bfffo_32_ix , + m68k_op_bfffo_32_ix , + m68k_op_bfffo_32_aw , + m68k_op_bfffo_32_al , + m68k_op_bfffo_32_pcdi , + m68k_op_bfffo_32_pcix , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_asr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_lsr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_roxr_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_ror_8_s , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_asr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_lsr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_roxr_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_ror_8_r , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_asr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_lsr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_roxr_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_ror_16_s , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_asr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_lsr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_roxr_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_ror_16_r , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_asr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_lsr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_roxr_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_ror_32_s , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_asr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_lsr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_roxr_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_ror_32_r , + m68k_op_bfset_32_d , + m68k_op_bfset_32_d , + m68k_op_bfset_32_d , + m68k_op_bfset_32_d , + m68k_op_bfset_32_d , + m68k_op_bfset_32_d , + m68k_op_bfset_32_d , + m68k_op_bfset_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfset_32_ai , + m68k_op_bfset_32_ai , + m68k_op_bfset_32_ai , + m68k_op_bfset_32_ai , + m68k_op_bfset_32_ai , + m68k_op_bfset_32_ai , + m68k_op_bfset_32_ai , + m68k_op_bfset_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfset_32_di , + m68k_op_bfset_32_di , + m68k_op_bfset_32_di , + m68k_op_bfset_32_di , + m68k_op_bfset_32_di , + m68k_op_bfset_32_di , + m68k_op_bfset_32_di , + m68k_op_bfset_32_di , + m68k_op_bfset_32_ix , + m68k_op_bfset_32_ix , + m68k_op_bfset_32_ix , + m68k_op_bfset_32_ix , + m68k_op_bfset_32_ix , + m68k_op_bfset_32_ix , + m68k_op_bfset_32_ix , + m68k_op_bfset_32_ix , + m68k_op_bfset_32_aw , + m68k_op_bfset_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_asl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_lsl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_roxl_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_rol_8_s , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_asl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_lsl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_roxl_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_rol_8_r , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_asl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_lsl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_roxl_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_rol_16_s , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_asl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_lsl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_roxl_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_rol_16_r , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_asl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_lsl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_roxl_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_rol_32_s , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_asl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_lsl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_roxl_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_rol_32_r , + m68k_op_bfins_32_d , + m68k_op_bfins_32_d , + m68k_op_bfins_32_d , + m68k_op_bfins_32_d , + m68k_op_bfins_32_d , + m68k_op_bfins_32_d , + m68k_op_bfins_32_d , + m68k_op_bfins_32_d , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfins_32_ai , + m68k_op_bfins_32_ai , + m68k_op_bfins_32_ai , + m68k_op_bfins_32_ai , + m68k_op_bfins_32_ai , + m68k_op_bfins_32_ai , + m68k_op_bfins_32_ai , + m68k_op_bfins_32_ai , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_bfins_32_di , + m68k_op_bfins_32_di , + m68k_op_bfins_32_di , + m68k_op_bfins_32_di , + m68k_op_bfins_32_di , + m68k_op_bfins_32_di , + m68k_op_bfins_32_di , + m68k_op_bfins_32_di , + m68k_op_bfins_32_ix , + m68k_op_bfins_32_ix , + m68k_op_bfins_32_ix , + m68k_op_bfins_32_ix , + m68k_op_bfins_32_ix , + m68k_op_bfins_32_ix , + m68k_op_bfins_32_ix , + m68k_op_bfins_32_ix , + m68k_op_bfins_32_aw , + m68k_op_bfins_32_al , + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_illegal, + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 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m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + 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m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + 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, + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpgen_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpdbcc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cpscc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cptrapcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_cpbcc_32 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , + m68k_op_1111 , +}; + +const unsigned char m68ki_cycles[1][0x10000]={ + { + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0, + 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, + 30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, + 34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 20, 0, 0, 0, + 14, 14, 14, 14, 14, 14, 14, 14, 0, 0, 0, 0, 0, 0, 0, 0, + 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, + 30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, + 34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0, + 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, + 30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, + 34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0, + 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, 28, + 30, 30, 30, 30, 30, 30, 30, 30, 32, 32, 32, 32, 32, 32, 32, 32, + 34, 34, 34, 34, 34, 34, 34, 34, 32, 36, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 10, 10, 10, 10, 10, 10, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 16, 18, 0, 0, 0, 0, + 12, 12, 12, 12, 12, 12, 12, 12, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, + 14, 14, 14, 14, 14, 14, 14, 14, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, + 12, 12, 12, 12, 12, 12, 12, 12, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 20, 20, 20, 20, 20, 20, 20, 20, + 22, 22, 22, 22, 22, 22, 22, 22, 20, 24, 0, 0, 0, 0, 0, 0, + 6, 6, 6, 6, 6, 6, 6, 6, 16, 16, 16, 16, 16, 16, 16, 16, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 12, 16, 12, 14, 8, 0, 0, 0, + 8, 8, 8, 8, 8, 8, 8, 8, 24, 24, 24, 24, 24, 24, 24, 24, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, + 10, 10, 10, 10, 10, 10, 10, 10, 16, 16, 16, 16, 16, 16, 16, 16, + 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, + 14, 14, 14, 14, 14, 14, 14, 14, 16, 16, 16, 16, 16, 16, 16, 16, + 18, 18, 18, 18, 18, 18, 18, 18, 16, 20, 0, 0, 0, 0, 0, 0, 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0000000..cf4a553 --- /dev/null +++ b/MCUME_teensy/teensygen/osd_cpu.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* * +* Define size independent data types and operations. * +* * +* The following types must be supported by all platforms: * +* * +* UINT8 - Unsigned 8-bit Integer INT8 - Signed 8-bit integer * +* UINT16 - Unsigned 16-bit Integer INT16 - Signed 16-bit integer * +* UINT32 - Unsigned 32-bit Integer INT32 - Signed 32-bit integer * +* UINT64 - Unsigned 64-bit Integer INT64 - Signed 64-bit integer * +* * +* * +* The macro names for the artithmatic operations are composed as follows: * +* * +* XXX_R_A_B, where XXX - 3 letter operation code (ADD, SUB, etc.) * +* R - The type of the result * +* A - The type of operand 1 * +* B - The type of operand 2 (if binary operation) * +* * +* Each type is one of: U8,8,U16,16,U32,32,U64,64 * +* * +*******************************************************************************/ + + +#ifndef OSD_CPU_H +#define OSD_CPU_H + +#include "shared.h" + +/* Combine two 32-bit integers into a 64-bit integer */ +#define COMBINE_64_32_32(A,B) ((((UINT64)(A))<<32) | (UINT32)(B)) +#define COMBINE_U64_U32_U32(A,B) COMBINE_64_32_32(A,B) + +/* Return upper 32 bits of a 64-bit integer */ +#define HI32_32_64(A) (((UINT64)(A)) >> 32) +#define HI32_U32_U64(A) HI32_32_64(A) + +/* Return lower 32 bits of a 64-bit integer */ +#define LO32_32_64(A) ((A) & 0xffffffff) +#define LO32_U32_U64(A) LO32_32_64(A) + +#define DIV_64_64_32(A,B) ((A)/(B)) +#define DIV_U64_U64_U32(A,B) ((A)/(UINT32)(B)) + +#define MOD_32_64_32(A,B) ((A)%(B)) +#define MOD_U32_U64_U32(A,B) ((A)%(UINT32)(B)) + +#define MUL_64_32_32(A,B) ((A)*(INT64)(B)) +#define MUL_U64_U32_U32(A,B) ((A)*(UINT64)(UINT32)(B)) + + +/****************************************************************************** + * Union of UINT8, UINT16 and UINT32 in native endianess of the target + * This is used to access bytes and words in a machine independent manner. + * The upper bytes h2 and h3 normally contain zero (16 bit CPU cores) + * thus PAIR.d can be used to pass arguments to the memory system + * which expects 'int' really. + ******************************************************************************/ +typedef union { +#ifdef LSB_FIRST + struct { UINT8 l,h,h2,h3; } b; + struct { UINT16 l,h; } w; +#else + struct { UINT8 h3,h2,h,l; } b; + struct { UINT16 h,l; } w; +#endif + UINT32 d; +} PAIR; + +#endif /* defined OSD_CPU_H */ diff --git a/MCUME_teensy/teensygen/psram_t.cpp b/MCUME_teensy/teensygen/psram_t.cpp new file mode 100644 index 0000000..3a47eb8 --- /dev/null +++ b/MCUME_teensy/teensygen/psram_t.cpp @@ -0,0 +1,356 @@ +/* + PSRAM driver for IPS6404 +*/ + +#include "psram_t.h" + +#include +#include + +#define SPI SPI2 + +//#define SPICLOCK 104000000 +#define SPICLOCK 70000000 +//#define SPICLOCK 144e6 //Just a number..max speed +#define SPI_MODE SPI_MODE0 + +#define RAM_READ 0xB +//#define RAM_READ 0x3 +#define RAM_WRITE 0x2 + + +uint8_t PSRAM_T::_cs, PSRAM_T::_miso, PSRAM_T::_mosi, PSRAM_T::_sclk; +Page PSRAM_T::pages[MAX_PAGES]; +uint8_t PSRAM_T::nbPages=0; +int8_t PSRAM_T::top=0; +int8_t PSRAM_T::last=0; + + +PSRAM_T::PSRAM_T(uint8_t cs, uint8_t mosi, uint8_t sclk, uint8_t miso) +{ + _cs = cs; + _mosi = mosi; + _sclk = sclk; + _miso = miso; + pinMode(_cs, OUTPUT); + digitalWrite(_cs, 1); +} + + +void PSRAM_T::begin(void) +{ + SPI.setMOSI(_mosi); + SPI.setMISO(_miso); + SPI.setSCK(_sclk); + SPI.begin(); + + delay(1); + + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(0x66); + digitalWrite(_cs, 1); + SPI.endTransaction(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + SPI.transfer(0x99); + SPI.endTransaction(); + digitalWrite(_cs, 1); + delayMicroseconds(20); +} + + + +uint8_t PSRAM_T::psram_read(uint32_t addr) +{ + uint8_t val=0; + + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_READ); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); +#if RAM_READ == 0xB + SPI.transfer(0xFF); +#endif + val = SPI.transfer(0xFF); + SPI.endTransaction(); + digitalWrite(_cs, 1); + return val; +} + + +void PSRAM_T::psram_read_n(uint32_t addr, uint8_t * val, int n) +{ + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_READ); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); +#if RAM_READ == 0xB + SPI.transfer(0xFF); +#endif + /* + while (n > 0) { + *val++ = SPI.transfer(0xFF); + n--; + } + */ + SPI.transfer(val,n); + SPI.endTransaction(); + digitalWrite(_cs, 1); +} + + +void PSRAM_T::psram_write(uint32_t addr, uint8_t val) +{ + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + SPI.transfer(val); + SPI.endTransaction(); + digitalWrite(_cs, 1); +} + +static uint8_t resp[PAGE_SIZE]; + + +void PSRAM_T::psram_write_n(uint32_t addr, uint8_t * val, int n) +{ + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + /* + while (n > 0) { + SPI.transfer(*val++); + n--; + } + */ + SPI.transfer(val,&resp[0],n); + SPI.endTransaction(); + digitalWrite(_cs, 1); +} + + +#ifdef DMATRY +#include + +DMAMEM static uint8_t src[PAGE_SIZE+4]; +DMAMEM static uint8_t dst[PAGE_SIZE+4]; +static DMASetting dmasettings[8]; +static DMAChannel dmatx; +static volatile uint8_t rstop = 0; + +#define DMASPI_PRINT(x) do {Serial.printf(x) ; Serial.flush();} while (0); + +static void dmaInterrupt() +{ + dmatx.clearInterrupt(); + rstop = 1; + //DMASPI_PRINT("irq"); +} + +void PSRAM_T::psram_write_n_dma(uint32_t addr, uint8_t * val, int n) { + uint8_t * dstPt = &dst[0]; + //*dstPt++ = RAM_WRITE; + //*dstPt++ = (addr>>16)&0xff; + //*dstPt++ = (addr>>8)&0xff; + //*dstPt++ = addr&0xff; + int cnt = n; + while (cnt > 0) { + *dstPt++ = *val++; + cnt--; + } + arm_dcache_flush(&dst[0], n); + rstop = 0; + dmatx.disable(); + dmatx.attachInterrupt(dmaInterrupt); + + dmasettings[0].sourceBuffer(&dst[0], n); + //dmasettings[0].destination((uint8_t &) LPSPI4_TDR); + dmasettings[0].destination((uint8_t &) IMXRT_LPSPI1_S.TDR); + dmasettings[0].TCD->ATTR_DST = 1; + dmasettings[0].interruptAtCompletion(); + +Serial.printf("A") ; Serial.flush(); + + digitalWrite(_cs, HIGH); + // SPI.begin(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + + digitalWrite(_cs, 0); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + //SPI.transfer(0); + //SPI.transfer(1); +Serial.printf("B") ; Serial.flush(); + +#ifdef XXX + LPSPI4_CR &= ~LPSPI_CR_MEN;//disable LPSPI: + LPSPI4_CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + //LPSPI4_TCR = 15; // Framesize 16 Bits + IMXRT_LPSPI4_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + LPSPI4_DER = LPSPI_DER_TDDE; //TX DMA Request Enable + // IMXRT_LPSPI4_S.DER = LPSPI_DER_TDDE; // | LPSPI_DER_RDDE; //enable DMA on both TX and RX + LPSPI4_CR |= LPSPI_CR_MEN; //enable LPSPI: + //IMXRT_LPSPI4_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + // IMXRT_LPSPI4_S.FCR = 0; + // Lets try to output the first byte to make sure that we are in 8 bit mode... + // IMXRT_LPSPI4_S.SR = 0x3f00; // clear out all of the other status... + + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI4_TX ); +#endif + IMXRT_LPSPI1_S.CR &= ~LPSPI_CR_MEN;//disable LPSPI: + IMXRT_LPSPI1_S.CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + IMXRT_LPSPI1_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + IMXRT_LPSPI1_S.DER = LPSPI_DER_TDDE; //TX DMA Request Enable + IMXRT_LPSPI1_S.CR |= LPSPI_CR_MEN; //enable LPSPI: + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI1_TX ); +Serial.printf("C") ; Serial.flush(); +// SPI.initDMAChannels(); + dmatx = dmasettings[0]; + + dmatx.enable(); +Serial.printf("D") ; Serial.flush(); + while (rstop == 0) {}; + + Serial.printf("E") ; Serial.flush(); + digitalWrite(_cs, 1); +} +#endif + + + + +void PSRAM_T::pswrite(uint32_t addr, uint8_t val) +{ + psram_write(addr, val); + //return; + uint32_t curPage=addr&(~(PAGE_SIZE-1)); + for (int i=0; i + +#define PAGE_SIZE 16 //16 //32 //2048 //1024 +#define MAX_PAGES 8 + +struct Page { + uint8_t page[PAGE_SIZE]; + uint32_t pageid; + int8_t next; + int8_t prev; +}; + +class PSRAM_T +{ + public: + PSRAM_T(uint8_t _CS, uint8_t _MOSI=11, uint8_t _SCLK=13, uint8_t _MISO=12); + void begin(void); + void pswrite(uint32_t addr, uint8_t val); + uint8_t psread(uint32_t addr); + uint16_t psread_w(uint32_t addr); + + private: + static uint8_t psram_read(uint32_t addr); + static void psram_read_n(uint32_t addr, uint8_t * val, int n); + static void psram_write(uint32_t addr, uint8_t val); + static void psram_write_n(uint32_t addr, uint8_t * val, int n); + + protected: + static uint8_t _cs, _miso, _mosi, _sclk; + static Page pages[MAX_PAGES]; + static uint8_t nbPages; + static int8_t top; + static int8_t last; +}; +#endif + +#endif + diff --git a/MCUME_teensy/teensygen/render.c b/MCUME_teensy/teensygen/render.c new file mode 100644 index 0000000..09b7dd8 --- /dev/null +++ b/MCUME_teensy/teensygen/render.c @@ -0,0 +1,1047 @@ +/* + only update window clip on window change (?) + fix leftmost window/nta render and window bug + sprite masking isn't right in sonic/micromachines 2, but + seems ok in galaxy force 2 +*/ + + +#include "shared.h" + +#ifdef ALIGN_LONG + +/* Or change the names if you depend on these from elsewhere.. */ +#undef READ_LONG +#undef WRITE_LONG + +static __inline__ uint32 READ_LONG(void *address) +{ + if ((uint32)address & 3) + { +#ifdef LSB_FIRST /* little endian version */ + return ( *((uint8 *)address) + + (*((uint8 *)address+1) << 8) + + (*((uint8 *)address+2) << 16) + + (*((uint8 *)address+3) << 24) ); +#else /* big endian version */ + return ( *((uint8 *)address+3) + + (*((uint8 *)address+2) << 8) + + (*((uint8 *)address+1) << 16) + + (*((uint8 *)address) << 24) ); +#endif /* LSB_FIRST */ + } + else + return *(uint32 *)address; +} + +static __inline__ void WRITE_LONG(void *address, uint32 data) +{ + if ((uint32)address & 3) + { +#ifdef LSB_FIRST + *((uint8 *)address) = data; + *((uint8 *)address+1) = (data >> 8); + *((uint8 *)address+2) = (data >> 16); + *((uint8 *)address+3) = (data >> 24); +#else + *((uint8 *)address+3) = data; + *((uint8 *)address+2) = (data >> 8); + *((uint8 *)address+1) = (data >> 16); + *((uint8 *)address) = (data >> 24); +#endif /* LSB_FIRST */ + return; + } + else + *(uint32 *)address = data; +} + +#endif /* ALIGN_LONG */ + +#ifdef ALIGN_LONG +/* Draw a single 8-pixel column */ +#define DRAW_COLUMN(ATTR, LINE) \ + atex = atex_table[(ATTR >> 13) & 7]; \ + src = (uint32 *)&bg_pattern_cache[(ATTR & 0x0FFF) << 6 | (LINE)]; \ + WRITE_LONG(dst, READ_LONG(src) | atex); \ + dst++; \ + src++; \ + WRITE_LONG(dst, READ_LONG(src) | atex); \ + dst++; \ + src++; \ + ATTR >>= 16; \ + atex = atex_table[(ATTR >> 13) & 7]; \ + src = (uint32 *)&bg_pattern_cache[(ATTR & 0x0FFF) << 6 | (LINE)]; \ + WRITE_LONG(dst, READ_LONG(src) | atex); \ + dst++; \ + src++; \ + WRITE_LONG(dst, READ_LONG(src) | atex); \ + dst++; \ + src++; + + +/* Draw a single 16-pixel column */ +#define DRAW_COLUMN_IM2(ATTR, LINE) \ + atex = atex_table[(ATTR >> 13) & 7]; \ + offs = (ATTR & 0x03FF) << 7 | (ATTR & 0x0800) << 6 | (LINE); \ + if(ATTR & 0x1000) offs ^= 0x40; \ + src = (uint32 *)&bg_pattern_cache[offs]; \ + WRITE_LONG(dst, READ_LONG(src) | atex); \ + dst++; \ + src++; \ + WRITE_LONG(dst, READ_LONG(src) | atex); \ + dst++; \ + src++; \ + ATTR >>= 16; \ + atex = atex_table[(ATTR >> 13) & 7]; \ + offs = (ATTR & 0x03FF) << 7 | (ATTR & 0x0800) << 6 | (LINE); \ + if(ATTR & 0x1000) offs ^= 0x40; \ + src = (uint32 *)&bg_pattern_cache[offs]; \ + WRITE_LONG(dst, READ_LONG(src) | atex); \ + dst++; \ + src++; \ + WRITE_LONG(dst, READ_LONG(src) | atex); \ + dst++; \ + src++; + +#else + +#define DRAW_COLUMN(ATTR, LINE) \ + atex = atex_table[(ATTR >> 13) & 7]; \ + src = (uint32 *)&bg_pattern_cache[(ATTR & 0x0FFF) << 6 | (LINE)]; \ + *dst++ = (*src++ | atex); \ + *dst++ = (*src++ | atex); \ + ATTR >>= 16; \ + atex = atex_table[(ATTR >> 13) & 7]; \ + src = (uint32 *)&bg_pattern_cache[(ATTR & 0x0FFF) << 6 | (LINE)]; \ + *dst++ = (*src++ | atex); \ + *dst++ = (*src++ | atex); + +#define DRAW_COLUMN_IM2(ATTR, LINE) \ + atex = atex_table[(ATTR >> 13) & 7]; \ + offs = (ATTR & 0x03FF) << 7 | (ATTR & 0x0800) << 6 | (LINE); \ + if(ATTR & 0x1000) offs ^= 0x40; \ + src = (uint32 *)&bg_pattern_cache[offs]; \ + *dst++ = (*src++ | atex); \ + *dst++ = (*src++ | atex); \ + ATTR >>= 16; \ + atex = atex_table[(ATTR >> 13) & 7]; \ + offs = (ATTR & 0x03FF) << 7 | (ATTR & 0x0800) << 6 | (LINE); \ + if(ATTR & 0x1000) offs ^= 0x40; \ + src = (uint32 *)&bg_pattern_cache[offs]; \ + *dst++ = (*src++ | atex); \ + *dst++ = (*src++ | atex); + + + +#endif /* ALIGN_LONG */ + + + +/* + gcc complains about this: + *lb++ = table[(*lb << 8) |(*src++ | palette)]; + .. claiming the result on lb is undefined. + So we manually advance lb and use constant offsets into the line buffer. +*/ +#define DRAW_SPRITE_TILE \ + lb[0] = table[(lb[0] << 8) |(*src++ | palette)]; \ + lb[1] = table[(lb[1] << 8) |(*src++ | palette)]; \ + lb[2] = table[(lb[2] << 8) |(*src++ | palette)]; \ + lb[3] = table[(lb[3] << 8) |(*src++ | palette)]; \ + lb[4] = table[(lb[4] << 8) |(*src++ | palette)]; \ + lb[5] = table[(lb[5] << 8) |(*src++ | palette)]; \ + lb[6] = table[(lb[6] << 8) |(*src++ | palette)]; \ + lb[7] = table[(lb[7] << 8) |(*src++ | palette)] + +/* Pixel creation macros, input is four bits each */ + +/* 5:6:5 RGB */ +#define MAKE_PIXEL_16(r,g,b) ((r) << 12 | (g) << 7 | (b) << 1) + +/* Clip data */ +static clip_t clip[2]; + +/* Attribute expansion table */ +static const uint32 atex_table[] = { + 0x00000000, 0x10101010, 0x20202020, 0x30303030, + 0x40404040, 0x50505050, 0x60606060, 0x70707070 +}; + +/* Sprite name look-up table */ +static uint8 name_lut[0x400]; + +/* Sprite line buffer data */ +static uint8 object_index_count; + +struct { + uint16 ypos; + uint16 xpos; + uint16 attr; + uint8 size; + uint8 index; +}object_info[20]; + +/* Pixel look-up tables and table base address */ +static uint8 *lut[5]; +#include "genlut.h" + +/* 16-bit pixel remapping data */ +static uint16 pixel_16[0x100]; +static uint16 pixel_16_lut[3][0x200]; + +/* Line buffers */ +static uint8 tmp_buf[0x400]; /* Temporary buffer */ +static uint8 bg_buf[0x400]; /* Merged background buffer */ +static uint8 nta_buf[0x400]; /* Plane A / Window line buffer */ +static uint8 ntb_buf[0x400]; /* Plane B line buffer */ +static uint8 obj_buf[0x400]; /* Object layer line buffer */ + +//static uint16 line_buf[0x400]; + + + +/*--------------------------------------------------------------------------*/ +/* Init, reset, shutdown routines */ +/*--------------------------------------------------------------------------*/ + +int render_init(void) +{ + int i; + + /* Pixel look-up tables */ + lut[0] = (uint8 *)(lut_base); + for(i = 1; i < LUT_MAX; i += 1) + { + lut[i] = lut[0] + (i * LUT_SIZE); + } + + /* Make pixel data tables */ + for(i = 0; i < 0x200; i += 1) + { + int r, g, b; + + r = (i >> 6) & 7; + g = (i >> 3) & 7; + b = (i >> 0) & 7; + + pixel_16_lut[0][i] = MAKE_PIXEL_16(r,g,b); + pixel_16_lut[1][i] = MAKE_PIXEL_16(r<<1,g<<1,b<<1); + pixel_16_lut[2][i] = MAKE_PIXEL_16(r|8,g|8,b|8); + } + + /* Set up color update function */ + color_update = color_update_16; + + /* Make sprite name look-up table */ + make_name_lut(); + + return (1); +} + +void make_name_lut(void) +{ + int col, row; + int vcol, vrow; + int width, height; + int flipx, flipy; + int i, name; + + memset(name_lut, 0, sizeof(name_lut)); + + for(i = 0; i < 0x400; i += 1) + { + vcol = col = i & 3; + vrow = row = (i >> 2) & 3; + height = (i >> 4) & 3; + width = (i >> 6) & 3; + flipx = (i >> 8) & 1; + flipy = (i >> 9) & 1; + + if(flipx) + vcol = (width - col); + if(flipy) + vrow = (height - row); + + name = vrow + (vcol * (height + 1)); + + if((row > height) || col > width) + name = -1; + + name_lut[i] = name; + } +} + + + +void render_reset(void) +{ + memset(&clip, 0, sizeof(clip)); + + memset(bg_buf, 0, sizeof(bg_buf)); + memset(tmp_buf, 0, sizeof(tmp_buf)); + memset(nta_buf, 0, sizeof(nta_buf)); + memset(ntb_buf, 0, sizeof(ntb_buf)); + memset(obj_buf, 0, sizeof(obj_buf)); + + memset(&pixel_16, 0, sizeof(pixel_16)); +} + + +void render_shutdown(void) +{ +} + +/*--------------------------------------------------------------------------*/ +/* Line render function */ +/*--------------------------------------------------------------------------*/ + +void render_line(int line) +{ +// uint8 *lb = (gbitmap.remap == 1) ? tmp_buf : &gbitmap.data[(line * gbitmap.pitch)]; + uint8 *lb = tmp_buf; + + if((reg[1] & 0x40) == 0x00) + { + /* Use the overscan color to clear the screen */ + memset(&lb[gbitmap.viewport.x], 0x40 | border, gbitmap.viewport.w); + } + else + { + update_bg_pattern_cache(); + window_clip(line); + + if(im2_flag) + { + render_ntx_im2(0, line, nta_buf); + render_ntx_im2(1, line, ntb_buf); + } + else + { + if(reg[0x0B] & 4) + { + render_ntx_vs(0, line, nta_buf); + render_ntx_vs(1, line, ntb_buf); + } + else + { + render_ntx(0, line, nta_buf); + render_ntx(1, line, ntb_buf); + } + } + + if(im2_flag) + render_ntw_im2(line, nta_buf); + else + render_ntw(line, nta_buf); + + if(reg[12] & 8) + { + merge(&nta_buf[0x20], &ntb_buf[0x20], &bg_buf[0x20], lut[2], (reg[12] & 1) ? 320 : 256); + memset(&obj_buf[0x20], 0, (reg[12] & 1) ? 320 : 256); + + if(im2_flag) + render_obj_im2(line, obj_buf, lut[3]); + else + render_obj(line, obj_buf, lut[3]); + + merge(&obj_buf[0x20], &bg_buf[0x20], &lb[0x20], lut[4], (reg[12] & 1) ? 320 : 256); + } + else + { + merge(&nta_buf[0x20], &ntb_buf[0x20], &lb[0x20], lut[0], (reg[12] & 1) ? 320 : 256); + if(im2_flag) + render_obj_im2(line, lb, lut[1]); + else + render_obj(line, lb, lut[1]); + } + } + + if(reg[0] & 0x20) + { + memset(&lb[gbitmap.viewport.x], 0x40 | border, 0x08); + } + + + int width = (reg[12] & 1) ? 320 : 256; + + + + //remap_16(lb+0x20, line_buf, pixel_16, width); + //emu_DrawLine16(line_buf, width ,256, line); + remap_16(lb+0x20, emu_LineBuffer(line), pixel_16, width); +} +/*--------------------------------------------------------------------------*/ +/* Window rendering */ +/*--------------------------------------------------------------------------*/ + +void render_ntw(int line, uint8 *buf) +{ + int column, v_line, width; + uint32 *nt, *src, *dst, atex, atbuf; + + v_line = (line & 7) << 3; + width = (reg[12] & 1) ? 7 : 6; + + nt = (uint32 *)&vram[ntwb | ((line >> 3) << width)]; + dst = (uint32 *)&buf[0x20 + (clip[1].left << 4)]; + + for(column = clip[1].left; column < clip[1].right; column += 1) + { + atbuf = nt[column]; + DRAW_COLUMN(atbuf, v_line) + } +} + +void render_ntw_im2(int line, uint8 *buf) +{ + int column, v_line, width; + uint32 *nt, *src, *dst, atex, atbuf, offs; + + v_line = ((line & 7) << 1 | ((status >> 4) & 1)) << 3; + width = (reg[12] & 1) ? 7 : 6; + + nt = (uint32 *)&vram[ntwb | ((line >> 3) << width)]; + dst = (uint32 *)&buf[0x20 + (clip[1].left << 4)]; + + for(column = clip[1].left; column < clip[1].right; column += 1) + { + atbuf = nt[column]; + DRAW_COLUMN_IM2(atbuf, v_line) + } +} + +/*--------------------------------------------------------------------------*/ +/* Background plane rendering */ +/*--------------------------------------------------------------------------*/ + +void render_ntx(int which, int line, uint8 *buf) +{ + int column; + int start, end; + int index; + int shift; + int nametable_row_mask = (playfield_col_mask >> 1); + int v_line; + uint32 atex, atbuf, *src, *dst; + uint16 xascroll, xbscroll, xscroll; + int y_scroll; + uint32 *nt; + int vsr_shift; + uint32 *vs; + uint16 table; + + + + + table = (which) ? ntbb : ntab; + + get_hscroll(line, &xascroll, &xbscroll); + xscroll = (which) ? xbscroll : xascroll; + + shift = (xscroll & 0x0F); + index = ((playfield_col_mask + 1) >> 1) - ((xscroll >> 4) & nametable_row_mask); + + if(which) + { + start = 0; + end = (reg[0x0C] & 1) ? 20 : 16; + } + else + { +// Looks correct if clip[0].left has 1 subtracted +// Otherwise window has gap between endpoint and where the first normal +// nta column starts + + if(clip[0].enable == 0) return; + start = clip[0].left; + end = clip[0].right; + index = (index + clip[0].left) & nametable_row_mask; + } + + vsr_shift = (which) ? 16 : 0; + vs = (uint32 *)&vsram[0]; + + y_scroll = (vs[0] >> vsr_shift) & 0xFFFF; + +// int dy = line & 0x7; +// int rev_line = (line & 0x1f8) + (dy^7); + + y_scroll = (line + (y_scroll & 0x3FF)) & playfield_row_mask; + + int dy = y_scroll & 0x7; + int y_scroll2 = (y_scroll & 0x1f8) + (dy^7); + + + + + v_line = (y_scroll & 7) << 3; + int v_line2 = (y_scroll2 & 7) << 3; + + nt = (uint32 *)&vram[table + (((y_scroll >> 3) << playfield_shift) & y_mask)]; + + if(shift) + { + dst = (uint32 *)&buf[0x20-(0x10-shift)]; + atbuf = nt[(index-1) & nametable_row_mask]; + //DRAW_COLUMN(atbuf, v_line) + // JMH + if (atbuf & 0x1000) { + DRAW_COLUMN(atbuf, v_line2); + } + else { + DRAW_COLUMN(atbuf, v_line); + } + } + buf = (buf + 0x20 + shift); + dst = (uint32 *)&buf[start<<4]; + + + + for(column = start; column < end; column += 1, index += 1) + { + atbuf = nt[index & nametable_row_mask]; + // JMH + if (atbuf & 0x1000) { + DRAW_COLUMN(atbuf, v_line2); + } + else + { + DRAW_COLUMN(atbuf, v_line); + } + } + +} + + +void render_ntx_im2(int which, int line, uint8 *buf) +{ + int column; + int start, end; + int index; + int shift; + int nametable_row_mask = (playfield_col_mask >> 1); + int v_line; + uint32 atex, atbuf, *src, *dst; + uint16 xascroll, xbscroll, xscroll; + int y_scroll; + uint32 *nt; + int vsr_shift; + uint32 *vs; + uint16 table; + uint32 offs; + + table = (which) ? ntbb : ntab; + + get_hscroll(line, &xascroll, &xbscroll); + xscroll = (which) ? xbscroll : xascroll; + + shift = (xscroll & 0x0F); + index = ((playfield_col_mask + 1) >> 1) - ((xscroll >> 4) & nametable_row_mask); + + if(which) + { + start = 0; + end = (reg[0x0C] & 1) ? 20 : 16; + } + else + { + if(clip[0].enable == 0) return; + start = clip[0].left; + end = clip[0].right; + index = (index + clip[0].left) & nametable_row_mask; + } + + vsr_shift = (which) ? 16 : 0; + vs = (uint32 *)&vsram[0]; + + y_scroll = (vs[0] >> vsr_shift) & 0xFFFF; + y_scroll = (line + ((y_scroll >> 1) & 0x3FF)) & playfield_row_mask; + v_line = (((y_scroll & 7) << 1) | ((status >> 4) & 1)) << 3; + nt = (uint32 *)&vram[table + (((y_scroll >> 3) << playfield_shift) & y_mask)]; + + if(shift) + { + dst = (uint32 *)&buf[0x20-(0x10-shift)]; + atbuf = nt[(index-1) & nametable_row_mask]; + DRAW_COLUMN_IM2(atbuf, v_line) + } + buf = (buf + 0x20 + shift); + dst = (uint32 *)&buf[start<<4]; + + for(column = start; column < end; column += 1, index += 1) + { + atbuf = nt[index & nametable_row_mask]; + DRAW_COLUMN_IM2(atbuf, v_line) + } +} + + +void render_ntx_vs(int which, int line, uint8 *buf) +{ + int column; + int start, end; + int index; + int shift; + int nametable_row_mask = (playfield_col_mask >> 1); + int v_line; + uint32 atex, atbuf, *src, *dst; + uint16 xascroll, xbscroll, xscroll; + int y_scroll; + uint32 *nt; + int vsr_shift; + uint32 *vs; + uint16 table; + + table = (which) ? ntbb : ntab; + + get_hscroll(line, &xascroll, &xbscroll); + xscroll = (which) ? xbscroll : xascroll; + shift = (xscroll & 0x0F); + index = ((playfield_col_mask + 1) >> 1) - ((xscroll >> 4) & nametable_row_mask); + + if(which) + { + start = 0; + end = (reg[0x0C] & 1) ? 20 : 16; + } + else + { + if(clip[0].enable == 0) return; + start = clip[0].left; + end = clip[0].right; + index = (index + clip[0].left) & nametable_row_mask; + } + + vsr_shift = (which) ? 16 : 0; + vs = (uint32 *)&vsram[0]; + end = (reg[0x0C] & 1) ? 20 : 16; + + if(shift) + { + dst = (uint32 *)&buf[0x20-(0x10-shift)]; + y_scroll = (line & playfield_row_mask); + v_line = (y_scroll & 7) << 3; + nt = (uint32 *)&vram[table + (((y_scroll >> 3) << playfield_shift) & y_mask)]; + atbuf = nt[(index-1) & nametable_row_mask]; + DRAW_COLUMN(atbuf, v_line) + } + + buf = (buf + 0x20 + shift); + dst = (uint32 *)&buf[start << 4]; + + for(column = start; column < end; column += 1, index += 1) + { + y_scroll = (vs[column] >> vsr_shift) & 0xFFFF; + y_scroll = (line + (y_scroll & 0x3FF)) & playfield_row_mask; + v_line = (y_scroll & 7) << 3; + nt = (uint32 *)&vram[table + (((y_scroll >> 3) << playfield_shift) & y_mask)]; + atbuf = nt[index & nametable_row_mask]; + DRAW_COLUMN(atbuf, v_line) + } +} +/*--------------------------------------------------------------------------*/ +/* Helper functions (cache update, hscroll, window clip) */ +/*--------------------------------------------------------------------------*/ + +void update_bg_pattern_cache(void) +{ + int i; + uint8 x, y, c; + uint16 name; + + if(!bg_list_index) return; + + for(i = 0; i < bg_list_index; i += 1) + { + name = bg_name_list[i]; + bg_name_list[i] = 0; + + for(y = 0; y < 8; y += 1) + { + if(bg_name_dirty[name] & (1 << y)) + { + uint8 *dst = &bg_pattern_cache[name << 6]; + uint32 bp = *(uint32 *)&vram[(name << 5) | (y << 2)]; + + for(x = 0; x < 8; x += 1) + { + c = (bp >> ((x ^ 3) << 2)) & 0x0F; + dst[0x00000 | (y << 3) | (x)] = (c); + dst[0x20000 | (y << 3) | (x ^ 7)] = (c); + //dst[0x40000 | ((y ^ 7) << 3) | (x)] = (c); + //dst[0x60000 | ((y ^ 7) << 3) | (x ^ 7)] = (c); + } + } + } + bg_name_dirty[name] = 0; + } + bg_list_index = 0; +} + +void get_hscroll(int line, uint16 *scrolla, uint16 *scrollb) +{ + switch(reg[11] & 3) + { + case 0: /* Full-screen */ + *scrolla = *(uint16 *)&vram[hscb + 0]; + *scrollb = *(uint16 *)&vram[hscb + 2]; + break; + + case 1: /* First 8 lines */ + *scrolla = *(uint16 *)&vram[hscb + ((line & 7) << 2) + 0]; + *scrollb = *(uint16 *)&vram[hscb + ((line & 7) << 2) + 2]; + break; + + case 2: /* Every 8 lines */ + *scrolla = *(uint16 *)&vram[hscb + ((line & ~7) << 2) + 0]; + *scrollb = *(uint16 *)&vram[hscb + ((line & ~7) << 2) + 2]; + break; + + case 3: /* Every line */ + *scrolla = *(uint16 *)&vram[hscb + (line << 2) + 0]; + *scrollb = *(uint16 *)&vram[hscb + (line << 2) + 2]; + break; + } + + *scrolla &= 0x03FF; + *scrollb &= 0x03FF; +} + +void window_clip(int line) +{ + /* Window size and invert flags */ + int hp = (reg[17] & 0x1F); + int hf = (reg[17] >> 7) & 1; + int vp = (reg[18] & 0x1F) << 3; + int vf = (reg[18] >> 7) & 1; + + /* Display size */ + int sw = (reg[12] & 1) ? 20 : 16; + + /* Clear clipping data */ + memset(&clip, 0, sizeof(clip)); + + /* Check if line falls within window range */ + if(vf == (line >= vp)) + { + /* Window takes up entire line */ + clip[1].right = sw; + clip[1].enable = 1; + } + else + { + /* Perform horizontal clipping; the results are applied in reverse + if the horizontal inversion flag is set */ + int a = hf; + int w = hf ^ 1; + + if(hp) + { + if(hp > sw) + { + /* Plane W takes up entire line */ + clip[w].right = sw; + clip[w].enable = 1; + } + else + { + /* Window takes left side, Plane A takes right side */ + clip[w].right = hp; + clip[a].left = hp; + clip[a].right = sw; + clip[0].enable = clip[1].enable = 1; + } + } + else + { + /* Plane A takes up entire line */ + clip[a].right = sw; + clip[a].enable = 1; + } + } +} + + + + + + + +/*--------------------------------------------------------------------------*/ +/* Remap functions */ +/*--------------------------------------------------------------------------*/ + +/* +void remap_8(uint8 *src, uint8 *dst, uint8 *table, int length) +{ + int count; + for(count = 0; count < length; count += 1) + { + *dst++ = table[*src++]; + } +} +*/ + +void remap_16(uint8 *src, uint16 *dst, uint16 *table, int length) +{ + int count; + for(count = 0; count < length; count += 1) + { + *dst++ = table[*src++]; + } +} + + +/*--------------------------------------------------------------------------*/ +/* Merge functions */ +/*--------------------------------------------------------------------------*/ + +void merge(uint8 *srca, uint8 *srcb, uint8 *dst, uint8 *table, int width) +{ + int i; + for(i = 0; i < width; i += 1) + { + uint8 a = srca[i]; + uint8 b = srcb[i]; + uint8 c = table[(b << 8) | (a)]; + dst[i] = c; + } +} + +void color_update_16(int index, uint16 data) +{ + if(reg[12] & 8) + { + pixel_16[0x00 | index] = pixel_16_lut[0][data]; + pixel_16[0x40 | index] = pixel_16_lut[1][data]; + pixel_16[0x80 | index] = pixel_16_lut[2][data]; + } + else + { + uint16 temp = pixel_16_lut[1][data]; + pixel_16[0x00 | index] = temp; + pixel_16[0x40 | index] = temp; + pixel_16[0x80 | index] = temp; + } +} + + +/*--------------------------------------------------------------------------*/ +/* Object render functions */ +/*--------------------------------------------------------------------------*/ + +void parse_satb(int line) +{ + static uint8 sizetab[] = {8, 16, 24, 32}; + uint8 *p, *q, link = 0; + uint16 ypos; + + int count; + int height; + + int limit = (reg[12] & 1) ? 20 : 16; + int total = (reg[12] & 1) ? 80 : 64; + + object_index_count = 0; + + for(count = 0; count < total; count += 1) + { + q = &sat[link << 3]; + p = &vram[satb + (link << 3)]; + + ypos = *(uint16 *)&q[0]; + + if(im2_flag) + ypos = (ypos >> 1) & 0x1FF; + else + ypos &= 0x1FF; + + height = sizetab[q[3] & 3]; + + if((line >= ypos) && (line < (ypos + height))) + { + object_info[object_index_count].ypos = *(uint16 *)&q[0]; + object_info[object_index_count].xpos = *(uint16 *)&p[6]; + + // using xpos from internal satb stops sprite x + // scrolling in bloodlin.bin, + // but this seems to go against the test prog +// object_info[object_index_count].xpos = *(uint16 *)&q[6]; + object_info[object_index_count].attr = *(uint16 *)&p[4]; + object_info[object_index_count].size = q[3]; + object_info[object_index_count].index = count; + + object_index_count += 1; + + if(object_index_count == limit) + { + if(vint_pending == 0) + status |= 0x40; + return; + } + } + + link = q[2] & 0x7F; + if(link == 0) break; + } +} + +void render_obj(int line, uint8 *buf, uint8 *table) +{ + uint16 ypos; + uint16 attr; + uint16 xpos; + uint8 sizetab[] = {8, 16, 24, 32}; + uint8 size; + uint8 *src; + + int count; + int pixellimit = (reg[12] & 1) ? 320 : 256; + int pixelcount = 0; + int width; + int height; + int v_line; + int column; + int sol_flag = 0; + int left = 0x80; + int right = 0x80 + ((reg[12] & 1) ? 320 : 256); + + uint8 *s, *lb; + uint16 name, index; + uint8 palette; + + int attr_mask, nt_row; + + if(object_index_count == 0) return; + + for(count = 0; count < object_index_count; count += 1) + { + size = object_info[count].size & 0x0f; + xpos = object_info[count].xpos; + xpos &= 0x1ff; + + width = sizetab[(size >> 2) & 3]; + + if(xpos != 0) sol_flag = 1; + else + if(xpos == 0 && sol_flag) return; + + if(pixelcount > pixellimit) return; + pixelcount += width; + + if(((xpos + width) >= left) && (xpos < right)) + { + ypos = object_info[count].ypos; + ypos &= 0x1ff; + + attr = object_info[count].attr; +// attr_mask = (attr & 0x1800); + attr_mask = (attr & 0x800); + + height = sizetab[size & 3]; + palette = (attr >> 9) & 0x70; + + v_line = (line - ypos); + nt_row = (v_line >> 3) & 3; + + if (attr & 0x1000) { + v_line = ((v_line & 7)^0x07) << 3; + } + else { + v_line = ((v_line & 7)) << 3; + } + + name = (attr & 0x07FF); + s = &name_lut[((attr >> 3) & 0x300) | (size << 4) | (nt_row << 2)]; + + lb = (uint8 *)&buf[0x20 + (xpos - 0x80)]; + + width >>= 3; + for(column = 0; column < width; column += 1, lb+=8) + { + index = attr_mask | ((name + s[column]) & 0x07FF); + src = &bg_pattern_cache[(index << 6) | (v_line)]; + DRAW_SPRITE_TILE; + } + } + } +} + +void render_obj_im2(int line, uint8 *buf, uint8 *table) +{ + uint16 ypos; + uint16 attr; + uint16 xpos; + uint8 sizetab[] = {8, 16, 24, 32}; + uint8 size; + uint8 *src; + + int count; + int pixellimit = (reg[12] & 1) ? 320 : 256; + int pixelcount = 0; + int width; + int height; + int v_line; + int column; + int sol_flag = 0; + int left = 0x80; + int right = 0x80 + ((reg[12] & 1) ? 320 : 256); + + uint8 *s, *lb; + uint16 name, index; + uint8 palette; + uint32 offs; + + int attr_mask, nt_row; + + if(object_index_count == 0) return; + + for(count = 0; count < object_index_count; count += 1) + { + size = object_info[count].size & 0x0f; + xpos = object_info[count].xpos; + xpos &= 0x1ff; + + width = sizetab[(size >> 2) & 3]; + + if(xpos != 0) sol_flag = 1; + else + if(xpos == 0 && sol_flag) return; + + if(pixelcount > pixellimit) return; + pixelcount += width; + + if(((xpos + width) >= left) && (xpos < right)) + { + ypos = object_info[count].ypos; + ypos = (ypos >> 1) & 0x1ff; + + attr = object_info[count].attr; +// attr_mask = (attr & 0x1800); + attr_mask = (attr & 0x800); + + height = sizetab[size & 3]; + palette = (attr >> 9) & 0x70; + + v_line = (line - ypos); + nt_row = (v_line >> 3) & 3; + v_line = ((((v_line & 7)/*^0x07*/) << 1) | ((status >> 4) & 1)) << 3; + + name = (attr & 0x03FF); + s = &name_lut[((attr >> 3) & 0x300) | (size << 4) | (nt_row << 2)]; + + lb = (uint8 *)&buf[0x20 + (xpos - 0x80)]; + + width >>= 3; + for(column = 0; column < width; column += 1, lb+=8) + { + index = (name + s[column]) & 0x3ff; + offs = index << 7 | attr_mask << 6 | v_line; + if(attr & 0x1000) offs ^= 0x40; + src = &bg_pattern_cache[offs]; + DRAW_SPRITE_TILE; + } + } + } +} + diff --git a/MCUME_teensy/teensygen/render.h b/MCUME_teensy/teensygen/render.h new file mode 100644 index 0000000..b2cd395 --- /dev/null +++ b/MCUME_teensy/teensygen/render.h @@ -0,0 +1,40 @@ + +#ifndef _RENDER_H_ +#define _RENDER_H_ + + +/* Look-up pixel table information */ +#define LUT_MAX (5) +#define LUT_SIZE (0x10000) + +/* Clip structure */ +typedef struct +{ + uint8 left; + uint8 right; + uint8 enable; +}clip_t; + +/* Function prototypes */ +int render_init(void); +void render_reset(void); +void render_shutdown(void); +void render_line(int line); +void render_obj(int line, uint8 *buf, uint8 *table); +void render_obj_im2(int line, uint8 *buf, uint8 *table); +void render_ntw(int line, uint8 *buf); +void render_ntw_im2(int line, uint8 *buf); +void render_ntx(int which, int line, uint8 *buf); +void render_ntx_im2(int which, int line, uint8 *buf); +void render_ntx_vs(int which, int line, uint8 *buf); +void update_bg_pattern_cache(void); +void get_hscroll(int line, uint16 *scrolla, uint16 *scrollb); +void window_clip(int line); +void remap_16(uint8 *src, uint16 *dst, uint16 *table, int length); +void merge(uint8 *srca, uint8 *srcb, uint8 *dst, uint8 *table, int width); +void color_update_16(int index, uint16 data); +void make_name_lut(void); +void parse_satb(int line); + +#endif /* _RENDER_H_ */ + diff --git a/MCUME_teensy/teensygen/shared.h b/MCUME_teensy/teensygen/shared.h new file mode 100644 index 0000000..5120897 --- /dev/null +++ b/MCUME_teensy/teensygen/shared.h @@ -0,0 +1,53 @@ + +#ifndef _SHARED_H_ +#define _SHARED_H_ + + +#define LSB_FIRST 1 +#define SOUND_PRESENT 1 +//#define ALIGN_LONG 1 +#define GENESIS_HACKS 1 + + +typedef unsigned char uint8; +typedef unsigned short int uint16; +typedef unsigned long int uint32; + +typedef signed char int8; +typedef signed short int int16; +typedef signed long int int32; + +typedef unsigned char UINT8; +typedef unsigned short int UINT16; +typedef unsigned long int UINT32; + +typedef signed char INT8; +typedef signed short int INT16; +typedef signed long int INT32; + + + +#include +#include "macros.h" +#include "m68k.h" +#include "z80.h" +#include "genesis.h" +#include "vdp.h" +#include "render.h" +#include "mem68k.h" +#include "memz80.h" +#include "membnk.h" +#include "memvdp.h" +#include "system.h" +#include "io.h" +#include "sound.h" +#include "fm.h" +#include "sn76496.h" +#include "memory.h" + +#define __inline__ +#define error(...) + + + +#endif /* _SHARED_H_ */ diff --git a/MCUME_teensy/teensygen/sn76496.c b/MCUME_teensy/teensygen/sn76496.c new file mode 100644 index 0000000..575101f --- /dev/null +++ b/MCUME_teensy/teensygen/sn76496.c @@ -0,0 +1,273 @@ + +#include "shared.h" + +#define MAX_OUTPUT 0x7fff +#define STEP 0x10000 +#define FB_WNOISE 0x12000 +#define FB_PNOISE 0x08000 +#define NG_PRESET 0x0F35 + +struct SN76496 +{ + int SampleRate; + unsigned int UpdateStep; + int VolTable[16]; + int Register[8]; + int LastRegister; + int Volume[4]; + unsigned int RNG; + int NoiseFB; + int Period[4]; + int Count[4]; + int Output[4]; +}; + + +struct SN76496 sn[MAX_76496]; + + + +void SN76496Write(int chip,int data) +{ + struct SN76496 *R = &sn[chip]; + + if (data & 0x80) + { + int r = (data & 0x70) >> 4; + int c = r/2; + + R->LastRegister = r; + R->Register[r] = (R->Register[r] & 0x3f0) | (data & 0x0f); + switch (r) + { + case 0: /* tone 0 : frequency */ + case 2: /* tone 1 : frequency */ + case 4: /* tone 2 : frequency */ + R->Period[c] = R->UpdateStep * R->Register[r]; + if (R->Period[c] == 0) R->Period[c] = R->UpdateStep; + if (r == 4) + { + /* update noise shift frequency */ + if ((R->Register[6] & 0x03) == 0x03) + R->Period[3] = 2 * R->Period[2]; + } + break; + case 1: /* tone 0 : volume */ + case 3: /* tone 1 : volume */ + case 5: /* tone 2 : volume */ + case 7: /* noise : volume */ + R->Volume[c] = R->VolTable[data & 0x0f]; + break; + case 6: /* noise : frequency, mode */ + { + int n = R->Register[6]; + R->NoiseFB = (n & 4) ? FB_WNOISE : FB_PNOISE; + n &= 3; + /* N/512,N/1024,N/2048,Tone #3 output */ + R->Period[3] = (n == 3) ? 2 * R->Period[2] : (R->UpdateStep << (5+n)); + + /* reset noise shifter */ + R->RNG = NG_PRESET; + R->Output[3] = R->RNG & 1; + } + break; + } + } + else + { + int r = R->LastRegister; + int c = r/2; + + switch (r) + { + case 0: /* tone 0 : frequency */ + case 2: /* tone 1 : frequency */ + case 4: /* tone 2 : frequency */ + R->Register[r] = (R->Register[r] & 0x0f) | ((data & 0x3f) << 4); + R->Period[c] = R->UpdateStep * R->Register[r]; + if (R->Period[c] == 0) R->Period[c] = R->UpdateStep; + if (r == 4) + { + /* update noise shift frequency */ + if ((R->Register[6] & 0x03) == 0x03) + R->Period[3] = 2 * R->Period[2]; + } + break; + } + } +} + + +void SN76496Update(int chip,signed short int *buffer,int length) +{ + int i; + struct SN76496 *R = &sn[chip]; + + + /* If the volume is 0, increase the counter */ + for (i = 0;i < 4;i++) + { + if (R->Volume[i] == 0) + { + /* note that I do count += length, NOT count = length + 1. You might think */ + /* it's the same since the volume is 0, but doing the latter could cause */ + /* interferencies when the program is rapidly modulating the volume. */ + if (R->Count[i] <= length*STEP) R->Count[i] += length*STEP; + } + } + + while (length > 0) + { + int vol[4]; + unsigned int out; + int left; + + + /* vol[] keeps track of how long each square wave stays */ + /* in the 1 position during the sample period. */ + vol[0] = vol[1] = vol[2] = vol[3] = 0; + + for (i = 0;i < 3;i++) + { + if (R->Output[i]) vol[i] += R->Count[i]; + R->Count[i] -= STEP; + /* Period[i] is the half period of the square wave. Here, in each */ + /* loop I add Period[i] twice, so that at the end of the loop the */ + /* square wave is in the same status (0 or 1) it was at the start. */ + /* vol[i] is also incremented by Period[i], since the wave has been 1 */ + /* exactly half of the time, regardless of the initial position. */ + /* If we exit the loop in the middle, Output[i] has to be inverted */ + /* and vol[i] incremented only if the exit status of the square */ + /* wave is 1. */ + while (R->Count[i] <= 0) + { + R->Count[i] += R->Period[i]; + if (R->Count[i] > 0) + { + R->Output[i] ^= 1; + if (R->Output[i]) vol[i] += R->Period[i]; + break; + } + R->Count[i] += R->Period[i]; + vol[i] += R->Period[i]; + } + if (R->Output[i]) vol[i] -= R->Count[i]; + } + + left = STEP; + do + { + int nextevent; + + + if (R->Count[3] < left) nextevent = R->Count[3]; + else nextevent = left; + + if (R->Output[3]) vol[3] += R->Count[3]; + R->Count[3] -= nextevent; + if (R->Count[3] <= 0) + { + if (R->RNG & 1) R->RNG ^= R->NoiseFB; + R->RNG >>= 1; + R->Output[3] = R->RNG & 1; + R->Count[3] += R->Period[3]; + if (R->Output[3]) vol[3] += R->Period[3]; + } + if (R->Output[3]) vol[3] -= R->Count[3]; + + left -= nextevent; + } while (left > 0); + + out = vol[0] * R->Volume[0] + vol[1] * R->Volume[1] + + vol[2] * R->Volume[2] + vol[3] * R->Volume[3]; + + if (out > MAX_OUTPUT * STEP) out = MAX_OUTPUT * STEP; + + *(buffer++) = out / STEP; + + length--; + } +} + + + +void SN76496_set_clock(int chip,int clock) +{ + struct SN76496 *R = &sn[chip]; + + + /* the base clock for the tone generators is the chip clock divided by 16; */ + /* for the noise generator, it is clock / 256. */ + /* Here we calculate the number of steps which happen during one sample */ + /* at the given sample rate. No. of events = sample rate / (clock/16). */ + /* STEP is a multiplier used to turn the fraction into a fixed point */ + /* number. */ + R->UpdateStep = ((double)STEP * R->SampleRate * 16) / clock; +} + + + +void SN76496_set_gain(int chip,int gain) +{ + struct SN76496 *R = &sn[chip]; + int i; + double out; + + + gain &= 0xff; + + /* increase max output basing on gain (0.2 dB per step) */ + out = MAX_OUTPUT / 3; + while (gain-- > 0) + out *= 1.023292992; /* = (10 ^ (0.2/20)) */ + + /* build volume table (2dB per step) */ + for (i = 0;i < 15;i++) + { + /* limit volume to avoid clipping */ + if (out > MAX_OUTPUT / 3) R->VolTable[i] = MAX_OUTPUT / 3; + else R->VolTable[i] = out; + + out /= 1.258925412; /* = 10 ^ (2/20) = 2dB */ + } + R->VolTable[15] = 0; +} + + + +int SN76496_init(int chip,int clock,int volume,int sample_rate) +{ + int i; + struct SN76496 *R = &sn[chip]; + + R->SampleRate = sample_rate; + SN76496_set_clock(chip,clock); + + for (i = 0;i < 4;i++) R->Volume[i] = 0; + + R->LastRegister = 0; + for (i = 0;i < 8;i+=2) + { + R->Register[i] = 0; + R->Register[i + 1] = 0x0f; /* volume = 0 */ + } + + for (i = 0;i < 4;i++) + { + R->Output[i] = 0; + R->Period[i] = R->Count[i] = R->UpdateStep; + } + R->RNG = NG_PRESET; + R->Output[3] = R->RNG & 1; + + return 0; +} + + + +int SN76496_sh_start(int clock, int volume, int rate) +{ + SN76496_init(0, clock, volume & 0xff, rate); + SN76496_set_gain(0, (volume >> 8) & 0xff); + return 0; +} diff --git a/MCUME_teensy/teensygen/sn76496.h b/MCUME_teensy/teensygen/sn76496.h new file mode 100644 index 0000000..58fd388 --- /dev/null +++ b/MCUME_teensy/teensygen/sn76496.h @@ -0,0 +1,21 @@ +#ifndef SN76496_H +#define SN76496_H + +#define MAX_76496 1 + +struct SN76496interface +{ + int num; + int baseclock[MAX_76496]; + int volume[MAX_76496]; +}; + +/* Function prototypes */ +void SN76496Write(int chip,int data); +void SN76496Update(int chip,signed short int *buffer,int length); +void SN76496_set_clock(int chip,int clock); +void SN76496_set_gain(int chip,int gain); +int SN76496_init(int chip,int clock,int volume,int sample_rate); +int SN76496_sh_start(int clock, int volume, int rate); + +#endif diff --git a/MCUME_teensy/teensygen/sound.c b/MCUME_teensy/teensygen/sound.c new file mode 100644 index 0000000..85f20e7 --- /dev/null +++ b/MCUME_teensy/teensygen/sound.c @@ -0,0 +1,170 @@ +/* + sound.c + YM2612 and SN76489 emulation +*/ + +#include "shared.h" + +/* YM2612 data */ +int fm_timera_tab[0x400]; /* Precalculated timer A values */ +int fm_timerb_tab[0x100]; /* Precalculated timer B values */ +uint8 fm_reg[2][0x100]; /* Register arrays (2x256) */ +uint8 fm_latch[2]; /* Register latches */ +uint8 fm_status; /* Read-only status flags */ +t_timer timer[2]; /* Timers A and B */ + +/* Initialize the YM2612 and SN76489 emulation */ +void sound_init(void) +{ + /* Timers run at half the YM2612 input clock */ + float clock = ((53.693175 / 7) / 2); + int i; + + /* Make Timer A table */ + for(i = 0; i < 1024; i += 1) + { + /* Formula is "time(us) = 72 * (1024 - A) / clock" */ + fm_timera_tab[i] = ((int)(float)(72 * (1024 - i)) / (clock)); + } + + /* Make Timer B table */ + for(i = 0; i < 256; i += 1) + { + /* Formula is "time(us) = 1152 * (256 - B) / clock" */ + fm_timerb_tab[i] = (int)(float)(1152 * (256 - i)) / clock; + } +} + +void sound_reset(void) +{ + if(snd.enabled) + { + YM2612ResetChip(0); + } +} + +void fm_write(int address, int data) +{ + int a0 = (address & 1); + int a1 = (address >> 1) & 1; + + if(a0) + { + /* Register data */ + fm_reg[a1][fm_latch[a1]] = data; + + /* Timer control only in set A */ + if(a1 == 0) + switch(fm_latch[a1]) + { + case 0x24: /* Timer A (LSB) */ + timer[0].index = (timer[0].index & 0x0003) | (data << 2); + timer[0].index &= 0x03FF; + timer[0].base = fm_timera_tab[timer[0].index]; + break; + + case 0x25: /* Timer A (MSB) */ + timer[0].index = (timer[0].index & 0x03FC) | (data & 3); + timer[0].index &= 0x03FF; + timer[0].base = fm_timera_tab[timer[0].index]; + break; + + case 0x26: /* Timer B */ + timer[1].index = data; + timer[1].base = timer[1].count = fm_timerb_tab[timer[1].index]; + break; + + case 0x27: /* Timer Control */ + + /* LOAD */ + timer[0].running = (data >> 0) & 1; + if(timer[0].running) timer[0].count = 0; + timer[1].running = (data >> 1) & 1; + if(timer[1].running) timer[1].count = 0; + + /* ENABLE */ + timer[0].enable = (data >> 2) & 1; + timer[1].enable = (data >> 3) & 1; + + /* RESET */ + if(data & 0x10) fm_status &= ~1; + if(data & 0x20) fm_status &= ~2; + break; + } + } + else + { + /* Register latch */ + fm_latch[a1] = data; + } + + if(snd.enabled) + { + if(snd.fm.curStage - snd.fm.lastStage > 1) + { + int16 *tempBuffer[2]; + tempBuffer[0] = snd.fm.buffer[0] + snd.fm.lastStage; + tempBuffer[1] = snd.fm.buffer[1] + snd.fm.lastStage; + YM2612UpdateOne(0, (int16 **)tempBuffer, snd.fm.curStage - snd.fm.lastStage); + snd.fm.lastStage = snd.fm.curStage; + } + + YM2612Write(0, address & 3, data); + } +} + + +int fm_read(int address) +{ + return (fm_status); +} + + +void fm_update_timers(void) +{ + int i; + + /* Process YM2612 timers */ + for(i = 0; i < 2; i += 1) + { + /* Is the timer running? */ + if(timer[i].running) + { + /* Each scanline takes up roughly 64 microseconds */ + timer[i].count += 64; + + /* Check if the counter overflowed */ + if(timer[i].count > timer[i].base) + { + /* Reload counter */ + timer[i].count = 0; + + /* Disable timer */ + timer[i].running = 0; + + /* Set overflow flag (if flag setting is enabled) */ + if(timer[i].enable) + { + fm_status |= (1 << i); + } + } + } + } +} + +void psg_write(int data) +{ + if(snd.enabled) + { + if(snd.psg.curStage - snd.psg.lastStage > 1) + { + int16 *tempBuffer; + tempBuffer = snd.psg.buffer + snd.psg.lastStage; + SN76496Update(0, tempBuffer, snd.psg.curStage - snd.psg.lastStage); + snd.psg.lastStage = snd.psg.curStage; + } + + SN76496Write(0, data); + } +} + diff --git a/MCUME_teensy/teensygen/sound.h b/MCUME_teensy/teensygen/sound.h new file mode 100644 index 0000000..0a5a998 --- /dev/null +++ b/MCUME_teensy/teensygen/sound.h @@ -0,0 +1,30 @@ + +#ifndef _SOUND_H_ +#define _SOUND_H_ + +typedef struct +{ + int running; + int enable; + int count; + int base; + int index; +} t_timer; + +/* Global variables */ +extern int fm_timera_tab[1024]; +extern int fm_timerb_tab[256]; +extern uint8 fm_reg[2][0x100]; +extern uint8 fm_latch[2]; +extern int timer_status; +extern t_timer timer[2]; + +/* Function prototypes */ +void sound_init(void); +void sound_reset(void); +void fm_write(int address, int data); +int fm_read(int address); +void fm_update_timers(void); +void psg_write(int data); + +#endif /* _SOUND_H_ */ diff --git a/MCUME_teensy/teensygen/system.c b/MCUME_teensy/teensygen/system.c new file mode 100644 index 0000000..e6f18a2 --- /dev/null +++ b/MCUME_teensy/teensygen/system.c @@ -0,0 +1,256 @@ +/* + Copyright (C) 1999, 2000, 2001, 2002, 2003 Charles MacDonald + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include "shared.h" + +t_bitmap gbitmap; +t_input input; +t_snd snd; +static int sound_tbl[262]; + +#define SND_SIZE (snd.buffer_size * sizeof(int16)) + + +int audio_init(int rate) +{ + int i; + + /* 68000 and YM2612 clock */ + float vclk = 53693175.0 / 7; + + /* Z80 and SN76489 clock */ + float zclk = 3579545.0; + + /* Clear the sound data context */ + memset(&snd, 0, sizeof(snd)); + + /* Make sure the requested sample rate is valid */ + if(!rate || ((rate < 8000) | (rate > 44100))) + { + return (0); + } + + /* Calculate the sound buffer size */ + snd.buffer_size = (rate / 60); + snd.sample_rate = rate; + + /* Allocate sound buffers */ + snd.fm.buffer[0] = emu_Malloc(SND_SIZE); + snd.fm.buffer[1] = emu_Malloc(SND_SIZE); + snd.psg.buffer = emu_Malloc(SND_SIZE); + + /* Make sure we could allocate everything */ + if(!snd.fm.buffer[0] || !snd.fm.buffer[1] || !snd.psg.buffer) + { + return (0); + } + + /* Initialize sound chip emulation */ + SN76496_sh_start(zclk, 100, rate); + YM2612Init(1, vclk, rate, NULL, NULL); + + /* Set audio enable flag */ + snd.enabled = 1; + + /* Make sound table */ + for (i = 0; i < 262; i++) + { + float p = snd.buffer_size * i; + p = p / 262; + sound_tbl[i] = p; + } + + return (0); +} + +void system_init(void) +{ + gen_init(); + vdp_init(); + render_init(); +} + +void system_reset(void) +{ + gen_reset(); + vdp_reset(); + render_reset(); + + if(snd.enabled) + { + YM2612ResetChip(0); + //memset(snd.buffer[0], 0, SND_SIZE); + //memset(snd.buffer[1], 0, SND_SIZE); + memset(snd.fm.buffer[0], 0, SND_SIZE); + memset(snd.fm.buffer[1], 0, SND_SIZE); + memset(snd.psg.buffer, 0, SND_SIZE); + } +} + +void system_shutdown(void) +{ + gen_shutdown(); + vdp_shutdown(); + render_shutdown(); +} + + +int system_frame(int do_skip) +{ + int line; + + if(gen_running == 0) + return 0; + + /* Clear V-Blank flag */ + status &= ~0x0008; + + /* Toggle even/odd flag (IM2 only) */ + if(im2_flag) + status ^= 0x0010; + + /* Point to start of sound buffer */ + snd.fm.lastStage = snd.fm.curStage = 0; + snd.psg.lastStage = snd.psg.curStage = 0; + + /* Parse sprites for line 0 (done on line 261) */ + parse_satb(0x80); + + for(line = 0; line < 262; line += 1) + { + /* Used by HV counter */ + v_counter = line; + + /* Run 68000 emulation */ + m68k_execute(487); + if(!gen_running) break; + + /* Run Z80 emulation (if enabled) */ + if(zreset == 1 && zbusreq == 0) + { +// z80_execute(228); + if(!gen_running) break; + } + + /* If a Z80 interrupt is still pending after a scanline, cancel it */ + if(zirq == 1) + { + zirq = 0; + z80_set_irq_line(0, CLEAR_LINE); + } + + /* Render a line of the display */ + if(do_skip == 0) + { + if(line < frame_end ) render_line(line); + if(line < frame_end-1 ) parse_satb(0x81 + line); + } + + /* Do H interrupt processing */ + if(line <= frame_end) + { + counter -= 1; + if(counter == -1) + { + counter = reg[10]; + hint_pending = 1; + if(reg[0] & 0x10) + { + m68k_set_irq(4); + } + } + } + else + { + counter = reg[10]; + } + + /* Do end of frame processing */ + if(line == frame_end) + { + status |= 0x0088; + vint_pending = 1; + + /* Give enough time to read the interrupt pending flag before + the interrupt actually occurs. */ + m68k_execute(16); + if(!gen_running) break; + + if(reg[1] & 0x20) + { + m68k_set_irq(6); + } + + if(zreset == 1 && zbusreq == 0) + { + z80_set_irq_line(0, ASSERT_LINE); + zirq = 1; + } + } + + fm_update_timers(); + + snd.fm.curStage = sound_tbl[line]; + snd.psg.curStage = sound_tbl[line]; + } + + if(snd.enabled) + { + audio_update(); + } + + return gen_running; +} + +void audio_update(void) +{ +} + +void audio_play_sample(int16 *bufl, int16 *bufr, int length) +{ + int i; + int16 acc; + + length = length/2; + + + int16 *tempBuffer[2]; + tempBuffer[0] = snd.fm.buffer[0]; + tempBuffer[1] = snd.fm.buffer[1]; + YM2612UpdateOne(0, (int16 **)tempBuffer, length); + + tempBuffer[0] = snd.psg.buffer; + SN76496Update(0, tempBuffer[0], length); + + for(i = 0; i < length /*snd.buffer_size*/; i += 1) + { + int16 psg = snd.psg.buffer[i] / 2; + + acc = 0; + acc += snd.fm.buffer[0][i]; + acc += psg; + //snd.buffer[0][i] = acc; + *bufl++ = acc; + + acc = 0; + acc += snd.fm.buffer[1][i]; + acc += psg; + //snd.buffer[1][i] = acc; + *bufl++ = acc; + } +} diff --git a/MCUME_teensy/teensygen/system.h b/MCUME_teensy/teensygen/system.h new file mode 100644 index 0000000..9ad1a7e --- /dev/null +++ b/MCUME_teensy/teensygen/system.h @@ -0,0 +1,85 @@ + +#ifndef _SYSTEM_H_ +#define _SYSTEM_H_ + +/* Input devices */ +#define MAX_DEVICES (8) /* Unsure of maximum */ +#define DEVICE_2BUTTON (0) /* 2-button gamepad */ +#define DEVICE_3BUTTON (1) /* 3-button gamepad */ +#define DEVICE_6BUTTON (2) /* 6-button gamepad */ + +/* Input bitmasks */ +#define INPUT_MODE (0x00000800) +#define INPUT_Z (0x00000400) +#define INPUT_Y (0x00000200) +#define INPUT_X (0x00000100) +#define INPUT_START (0x00000080) +#define INPUT_C (0x00000040) +#define INPUT_B (0x00000020) +#define INPUT_A (0x00000010) +#define INPUT_LEFT (0x00000008) +#define INPUT_RIGHT (0x00000004) +#define INPUT_DOWN (0x00000002) +#define INPUT_UP (0x00000001) + +typedef struct +{ +// uint8 *data; /* Bitmap data */ + int width; /* Bitmap width (32+512+32) */ + int height; /* Bitmap height (256) */ +// int depth; /* Color depth (8 bits) */ + int pitch; /* Width of bitmap in bytes */ +// int granularity; /* Size of each pixel in bytes */ +// int remap; /* 1= Translate pixel data */ + struct { + int x; /* X offset of viewport within bitmap */ + int y; /* Y offset of viewport within bitmap */ + int w; /* Width of viewport */ + int h; /* Height of viewport */ + int ow; /* Previous width of viewport */ + int oh; /* Previous height of viewport */ + int changed; /* 1= Viewport width or height have changed */ + }viewport; +}t_bitmap; + +typedef struct +{ + uint8 dev[MAX_DEVICES]; /* Can be any of the DEVICE_* values */ + uint32 pad[MAX_DEVICES]; /* Can be any of the INPUT_* bitmasks */ + uint32 system; /* Can be any of the SYSTEM_* bitmasks */ +}t_input; + +typedef struct +{ + int sample_rate; /* Sample rate (8000-44100) */ + int enabled; /* 1= sound emulation is enabled */ + int buffer_size; /* Size of sound buffer (in bytes) */ + int16 *buffer[2]; /* Signed 16-bit stereo sound data */ + struct { + int curStage; + int lastStage; + int16 *buffer[2]; + } fm; + struct { + int curStage; + int lastStage; + int16 *buffer; + } psg; +}t_snd; + +/* Global variables */ +extern t_bitmap gbitmap; +extern t_input input; +extern t_snd snd; + +/* Function prototypes */ +void system_init(void); +int system_frame(int skip); +void system_reset(void); +void system_shutdown(void); +int audio_init(int rate); +void audio_update(void); +void audio_play_sample(int16 *bufl, int16 *bufr, int length); + +#endif /* _SYSTEM_H_ */ + diff --git a/MCUME_teensy/teensygen/teensygen.ino b/MCUME_teensy/teensygen/teensygen.ino new file mode 100644 index 0000000..b23fdd6 --- /dev/null +++ b/MCUME_teensy/teensygen/teensygen.ino @@ -0,0 +1,279 @@ +#include "iopins.h" +#include "emuapi.h" + +#include "keyboard_osd.h" +#include "tft_t_dma.h" + +#include "emu.h" + +#ifdef HAS_VGA +#include +uVGA uvga; +#if F_CPU == 144000000 +#define UVGA_144M_326X240 +#define UVGA_XRES 326 +#define UVGA_YRES 240 +#define UVGA_XRES_EXTRA 10 +#elif F_CPU == 180000000 +#define UVGA_180M_360X300 +#define UVGA_XRES 360 +#define UVGA_YRES 300 +#define UVGA_XRES_EXTRA 8 +#elif F_CPU == 240000000 +#define UVGA_240M_452X240 +#define UVGA_XRES 452 +#define UVGA_YRES 240 +#define UVGA_XRES_EXTRA 12 +#else +#error Please select F_CPU=240MHz or F_CPU=180MHz or F_CPU=144MHz +#endif + +#include + +uint8_t * VGA_frame_buffer; +#endif + +TFT_T_DMA tft = TFT_T_DMA(TFT_CS, TFT_DC, TFT_RST, TFT_MOSI, TFT_SCLK, TFT_MISO, TFT_TOUCH_CS, TFT_TOUCH_INT); + +bool vgaMode = false; + +static unsigned char palette8[PALETTE_SIZE]; +static unsigned short palette16[PALETTE_SIZE]; +static IntervalTimer myTimer; +volatile boolean vbl=true; +static int skip=0; +static elapsedMicros tius; + +static void vblCount() { + if (vbl) { + vbl = false; + } else { + vbl = true; + } +} + +void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index) +{ + if (index +#include "AudioPlaySystem.h" + +AudioPlaySystem mymixer; +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) +AudioOutputMQS mqs; +AudioConnection patchCord9(mymixer, 0, mqs, 1); +#else +AudioOutputAnalog dac1; +AudioConnection patchCord1(mymixer, dac1); +#endif + +void emu_sndInit() { + Serial.println("sound init"); + AudioMemory(16); + mymixer.start(); +} + +void emu_sndPlaySound(int chan, int volume, int freq) +{ + if (chan < 6) { + mymixer.sound(chan, freq, volume); + } + /* + Serial.print(chan); + Serial.print(":" ); + Serial.print(volume); + Serial.print(":" ); + Serial.println(freq); + */ +} + +void emu_sndPlayBuzz(int size, int val) { + mymixer.buzz(size,val); + //Serial.print((val==1)?1:0); + //Serial.print(":"); + //Serial.println(size); +} +#endif diff --git a/MCUME_teensy/teensygen/tft_t_dma.cpp b/MCUME_teensy/teensygen/tft_t_dma.cpp new file mode 100644 index 0000000..33c4d32 --- /dev/null +++ b/MCUME_teensy/teensygen/tft_t_dma.cpp @@ -0,0 +1,1182 @@ +/* + Based on C64 ILI9341 dma driver from Frank Bösing, 2017 +*/ + +#include "TFT_T_DMA.h" +#include "font8x8.h" + +//#define SPICLOCK 144e6 //Just a number..max speed +#define SPICLOCK 60000000 +#ifdef ILI9341 +#define SPI_MODE SPI_MODE0 +#endif +#ifdef ST7789 +#define SPI_MODE SPI_MODE2 +#endif + +// touch +#define SPI_SETTING SPISettings(2500000, MSBFIRST, SPI_MODE) +#define XPT2046_CFG_START _BV(7) +#define XPT2046_CFG_MUX(v) ((v&0b111) << (4)) +#define XPT2046_CFG_8BIT _BV(3) +#define XPT2046_CFG_12BIT (0) +#define XPT2046_CFG_SER _BV(2) +#define XPT2046_CFG_DFR (0) +#define XPT2046_CFG_PWR(v) ((v&0b11)) +#define XPT2046_MUX_Y 0b101 +#define XPT2046_MUX_X 0b001 +#define XPT2046_MUX_Z1 0b011 +#define XPT2046_MUX_Z2 0b100 + + +#ifdef TFT_STATICFB +static uint16_t fb0[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t fb1[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t fb2[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t fb3[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t * blocks[NR_OF_BLOCK]={fb0,fb1,fb2,fb3}; +#else +static uint16_t * blocks[NR_OF_BLOCK]; +#endif + + +static DMASetting dmasettings[SCREEN_DMA_NUM_SETTINGS]; +static DMAChannel dmatx;//(false); +static volatile uint8_t rstop = 0; +static volatile bool cancelled = false; +static volatile uint8_t curTransfer = 0; +static uint8_t nbTransfer = 0; + + +PROGMEM static const uint8_t init_commands[] = { +#ifdef ILI9341 + 4, 0xEF, 0x03, 0x80, 0x02, + 4, 0xCF, 0x00, 0XC1, 0X30, + 5, 0xED, 0x64, 0x03, 0X12, 0X81, + 4, 0xE8, 0x85, 0x00, 0x78, + 6, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02, + 2, 0xF7, 0x20, + 3, 0xEA, 0x00, 0x00, + 2, ILI9341_PWCTR1, 0x23, // Power control + 2, ILI9341_PWCTR2, 0x10, // Power control + 3, ILI9341_VMCTR1, 0x3e, 0x28, // VCM control + 2, ILI9341_VMCTR2, 0x86, // VCM control2 + 2, ILI9341_MADCTL, 0x48, // Memory Access Control + 2, ILI9341_PIXFMT, 0x55, + 3, ILI9341_FRMCTR1, 0x00, 0x18, + 4, ILI9341_DFUNCTR, 0x08, 0x82, 0x27, // Display Function Control + 2, 0xF2, 0x00, // Gamma Function Disable + 2, ILI9341_GAMMASET, 0x01, // Gamma curve selected + 16, ILI9341_GMCTRP1, 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, + 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00, // Set Gamma + 16, ILI9341_GMCTRN1, 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, + 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F, // Set Gamma +// 3, 0xb1, 0x00, 0x1f, // FrameRate Control 61Hz + 3, 0xb1, 0x00, 0x10, // FrameRate Control 119Hz + 2, ILI9341_MADCTL, ILI9341_MADCTL_MX | ILI9341_MADCTL_MY | ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR, + 0 +#endif +#ifdef ST7789 +#define DELAY 0x80 + 9, // 9 commands in list: + ST7735_SWRESET, DELAY, // 1: Software reset, no args, w/delay + 150, // 150 ms delay + ST7735_SLPOUT , DELAY, // 2: Out of sleep mode, no args, w/delay + 255, // 255 = 500 ms delay + ST7735_COLMOD , 1+DELAY, // 3: Set color mode, 1 arg + delay: + 0x55, // 16-bit color + 10, // 10 ms delay + ST7735_MADCTL , 1 , // 4: Memory access ctrl (directions), 1 arg: + 0x08, // Row addr/col addr, bottom to top refresh + ST7735_CASET , 4 , // 5: Column addr set, 4 args, no delay: + 0x00, + 0x00, // XSTART = 0 + 0x00, + 240, // XEND = 240 + ST7735_RASET , 4 , // 6: Row addr set, 4 args, no delay: + 0x00, + 0x00, // YSTART = 0 + 320>>8, + 320 & 0xFF, // YEND = 320 + ST7735_INVON , DELAY, // 7: hack + 10, + ST7735_NORON , DELAY, // 8: Normal display on, no args, w/delay + 10, // 10 ms delay + ST7735_DISPON , DELAY, // 9: Main screen turn on, no args, w/delay + 255 +#endif +}; + + +static void dmaInterrupt() { + dmatx.clearInterrupt(); + curTransfer++; + if (curTransfer >= nbTransfer) { + curTransfer = 0; + if (cancelled) { + dmatx.disable(); + rstop = 1; + } + } +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) + arm_dcache_flush(blocks[curTransfer], LINES_PER_BLOCK*TFT_WIDTH*2); +#endif +} + +static void setDmaStruct() { + uint32_t remaining = TFT_HEIGHT*TFT_WIDTH*2; + int i=0; + uint16_t col=RGBVAL16(0x00,0x00,0x00);; + while (remaining > 0) { + uint16_t * fb = blocks[i]; + int32_t len = (remaining >= (LINES_PER_BLOCK*TFT_WIDTH*2)?LINES_PER_BLOCK*TFT_WIDTH*2:remaining); +#ifdef TFT_DEBUG + Serial.println((unsigned long)blocks[i]); + Serial.println(remaining); +#endif + switch (i) { + case 0: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb0[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0x00,0xff,0x00); +#endif + break; + case 1: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb1[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0x00,0xff,0xff); +#endif + break; + case 2: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb2[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0x00,0x00,0xff); +#endif + break; + case 3: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb3[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0xff,0x00,0xff); +#endif + break; + } + blocks[i] = fb; + if (blocks[i] == 0) { + Serial.print("ILI9341 allocaltion failed for block "); + Serial.println(i); + delay(10000); + } + + for (int j=0;jATTR_DST = 1; +#else + dmasettings[i].sourceBuffer(fb, len); + dmasettings[i].destination((uint8_t &) SPI0_PUSHR); + dmasettings[i].TCD->ATTR_DST = 1; +#endif + dmasettings[i].replaceSettingsOnCompletion(dmasettings[i+1]); + dmasettings[i].interruptAtCompletion(); + remaining -= len; + i++; + } + dmasettings[i-1].replaceSettingsOnCompletion(dmasettings[0]); + nbTransfer = i; +#ifdef TFT_DEBUG + Serial.println(nbTransfer); +#endif +} + + +TFT_T_DMA::TFT_T_DMA(uint8_t cs, uint8_t dc, uint8_t rst, uint8_t mosi, uint8_t sclk, uint8_t miso, uint8_t touch_cs, uint8_t touch_irq) +{ + _cs = cs; + _dc = dc; + _rst = rst; + _mosi = mosi; + _sclk = sclk; + _miso = miso; + pinMode(_dc, OUTPUT); + pinMode(_cs, OUTPUT); + digitalWrite(_cs, 1); + digitalWrite(_dc, 1); + if ( (touch_cs != 255) && (touch_irq != 255) ) { + _touch_irq = touch_irq; + _touch_cs = touch_cs; + pinMode(_touch_cs, OUTPUT); + pinMode(touch_irq, INPUT_PULLUP); + digitalWrite(_touch_cs, 1); + } +} + + +void TFT_T_DMA::setArea(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2) { + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + + digitalWrite(_dc, 0); + SPI.transfer(TFT_CASET); + digitalWrite(_dc, 1); + SPI.transfer16(x1); + SPI.transfer16(x2); + + digitalWrite(_dc, 0); + SPI.transfer(TFT_PASET); + digitalWrite(_dc, 1); + SPI.transfer16(y1); + SPI.transfer16(y2); + + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + digitalWrite(_dc, 1); + + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + + +void TFT_T_DMA::begin(void) { + SPI.setMOSI(_mosi); + SPI.setMISO(_miso); + SPI.setSCK(_sclk); + SPI.begin(); + + // Initialize display + if (_rst < 255) { // toggle RST low to reset + pinMode(_rst, OUTPUT); + digitalWrite(_rst, HIGH); + delay(5); + digitalWrite(_rst, LOW); + delay(20); + digitalWrite(_rst, HIGH); + delay(120); + } + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + const uint8_t *addr = init_commands; + digitalWrite(_cs, 0); +#ifdef ILI9341 + while (1) { + uint8_t count = *addr++; + if (count-- == 0) break; + + digitalWrite(_dc, 0); + SPI.transfer(*addr++); + + while (count-- > 0) { + digitalWrite(_dc, 1); + SPI.transfer(*addr++); + } + } + + digitalWrite(_dc, 0); + SPI.transfer(ILI9341_SLPOUT); + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + SPI.endTransaction(); + + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + SPI.endTransaction(); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_dc, 0); + digitalWrite(_cs, 0); + SPI.transfer(ILI9341_DISPON); + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + SPI.endTransaction(); +#endif +#ifdef ST7789 + uint8_t numCommands, numArgs; + uint16_t ms; + numCommands = *addr++; // Number of commands to follow + while(numCommands--) { // For each command... + digitalWrite(_dc, 0); + SPI.transfer(*addr++); + numArgs = *addr++; // Number of args to follow + ms = numArgs & DELAY; // If hibit set, delay follows args + numArgs &= ~DELAY; // Mask out delay bit + while(numArgs > 1) { // For each argument... + digitalWrite(_dc, 1); + SPI.transfer(*addr++); + numArgs--; + } + + if (numArgs) { + digitalWrite(_dc, 1); + SPI.transfer(*addr++); + } + if(ms) { + ms = *addr++; // Read post-command delay time (ms) + if(ms == 255) ms = 500; // If 255, delay for 500 ms + SPI.endTransaction(); + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + delay(ms); + //beginSPITransaction(); + } + } +#endif + + setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1); + + cancelled = false; +#ifdef FLIP_SCREEN + flipscreen(true); +#else + flipscreen(false); +#endif +}; + + + +void TFT_T_DMA::flipscreen(bool flip) +{ + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_dc, 0); + digitalWrite(_cs, 0); + SPI.transfer(TFT_MADCTL); + digitalWrite(_dc, 1); + if (flip) { + flipped=true; +#ifdef ILI9341 + SPI.transfer(ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR); +#endif +#ifdef ST7789 + //SPI.transfer(ST77XX_MADCTL_RGB); + SPI.transfer(ST77XX_MADCTL_MV | ST77XX_MADCTL_RGB); +#endif + } + else { + flipped=false; +#ifdef ILI9341 + SPI.transfer(ILI9341_MADCTL_MX | ILI9341_MADCTL_MY | ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR); +#endif +#ifdef ST7789 + SPI.transfer(ST77XX_MADCTL_MX | ST77XX_MADCTL_MV | ST77XX_MADCTL_RGB); +#endif + } + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + +boolean TFT_T_DMA::isflipped(void) +{ + return(flipped); +} + + +#define PRREG(x) Serial.print(#x" 0x"); Serial.println(x,HEX) + + +void TFT_T_DMA::startDMA(void) { + curTransfer = 0; + rstop = 0; + //dmatx.begin(true); + dmatx.attachInterrupt(dmaInterrupt); + setDmaStruct(); + setArea((TFT_REALWIDTH-TFT_WIDTH)/2, (TFT_REALHEIGHT-TFT_HEIGHT)/2, (TFT_REALWIDTH-TFT_WIDTH)/2 + TFT_WIDTH-1, (TFT_REALHEIGHT-TFT_HEIGHT)/2+TFT_HEIGHT-1); + fillScreen(RGBVAL16(0x00,0x00,0x00)); + + digitalWrite(_cs, HIGH); + SPI.begin(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE0)); +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) + +#ifdef TFT_DEBUG + PRREG(LPSPI4_CCR); + PRREG(LPSPI4_TCR); + PRREG(LPSPI4_FCR); + Serial.printf("SPI CLOCK %d CCR freq %.1f MHz\n", SPICLOCK, 528. / 7 / ((0xff & LPSPI4_CCR) + 2)); +#endif + LPSPI4_CR &= ~LPSPI_CR_MEN;//disable LPSPI: + LPSPI4_CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + LPSPI4_TCR = 15; // Framesize 16 Bits + //LPSPI4_FCR = 0; // Fifo Watermark + LPSPI4_DER = LPSPI_DER_TDDE; //TX DMA Request Enable + LPSPI4_CR |= LPSPI_CR_MEN; //enable LPSPI: + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI4_TX ); +#else + SPI0_RSER |= SPI_RSER_TFFF_DIRS | SPI_RSER_TFFF_RE; // Set ILI_DMA Interrupt Request Select and Enable register + SPI0_MCR &= ~SPI_MCR_HALT; //Start transfers. + SPI0_CTAR0 = SPI0_CTAR1; + (*(volatile uint16_t *)((int)&SPI0_PUSHR + 2)) = (SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT) >> 16; //Enable 16 Bit Transfers + Continue-Bit + dmatx.triggerAtHardwareEvent(DMAMUX_SOURCE_SPI0_TX ); +#endif + dmatx = dmasettings[0]; + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + digitalWrite(_dc, 1); + dmatx.enable(); +} + + +void TFT_T_DMA::stopDMA(void) { + rstop = 0; + wait(); + delay(50); + cancelled = false; + dmatx.detachInterrupt(); + fillScreen(RGBVAL16(0x00,0x00,0x00)); + SPI.end(); +#ifdef ST7789 + begin(); +#endif +#ifdef ILI9341 + SPI.begin(); + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.endTransaction(); + digitalWrite(_cs, 1); + digitalWrite(_dc, 1); +#endif + setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1); +} + +void TFT_T_DMA::wait(void) { + rstop = 1; + unsigned long m = millis(); + cancelled = true; + while (!rstop) { + if ((millis() - m) > 100) break; + delay(10); + asm volatile("wfi"); + }; + rstop = 0; +} + + +/*********************************************************************************************** + Touch functions + ***********************************************************************************************/ +/* Code based on ... + * + * @file XPT2046.cpp + * @date 19.02.2016 + * @author Markus Sattler + * + * Copyright (c) 2015 Markus Sattler. All rights reserved. + * This file is part of the XPT2046 driver for Arduino. + */ + +#define ADC_MAX 0x0fff + +void TFT_T_DMA::enableTouchIrq() +{ + SPI.beginTransaction(SPI_SETTING); + digitalWrite(_touch_cs, LOW); + const uint8_t buf[4] = { (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y)), 0x00, 0x00, 0x00 }; + SPI.transfer((void*)&buf[0],3); + digitalWrite(_touch_cs, HIGH); + SPI.endTransaction(); +} + +//Default callibration for non flipped +#define TX_MIN 30 +#define TY_MIN 20 +#define TX_MAX 300 +#define TY_MAX 220 + +//Default callibration for flipped +#define TFX_MIN 20 +#define TFY_MIN 25 +#define TFX_MAX 288 +#define TFY_MAX 221 + +static uint16_t txMin; +static uint16_t tyMin; +static uint16_t txMax; +static uint16_t tyMax; + + +void TFT_T_DMA::callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax) { + if ( (xMin >= 0) && (yMin >= 0) && (xMax < 320) && (yMax < 200) ) { + txMin = xMin; + tyMin = yMin; + txMax = xMax; + tyMax = yMax; + } + else { + if (flipped) { + txMin = TFX_MIN; + tyMin = TFY_MIN; + txMax = TFX_MAX; + tyMax = TFY_MAX; + } + else { + txMin = TX_MIN; + tyMin = TY_MIN; + txMax = TX_MAX; + tyMax = TY_MAX; + } + } +} + + +void TFT_T_DMA::readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + if ( TOUCH_ENABLED() ) { + uint16_t x = 0; + uint16_t y = 0; + uint16_t z1 = 0; + uint16_t z2 = 0; + uint8_t i = 0; + int16_t xraw=0, yraw=0; + + SPI.beginTransaction(SPI_SETTING); + digitalWrite(_touch_cs, LOW); + + for(; i < 15; i++) { + // SPI requirer 32bit aliment + uint8_t buf[12] = { + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3)), 0x00, 0x00 + }; + SPI.transfer(&buf[0], &buf[0], 12); + y += (buf[1] << 8 | buf[2])>>3; + x += (buf[4] << 8 | buf[5])>>3; + z1 += (buf[7] << 8 | buf[8])>>3; + z2 += (buf[10] << 8 | buf[11])>>3; + } + enableTouchIrq(); + + if(i == 0) { + *oX = 0; + *oY = 0; + *oZ = 0; + } + else { + x /= i; + y /= i; + z1 /= i; + z2 /= i; + } + + digitalWrite(_touch_cs, HIGH); + SPI.endTransaction(); + int z = z1 + ADC_MAX - z2; + if (flipped) { + xraw = x; + yraw = y; + } else { + xraw = ADC_MAX - x; + yraw = ADC_MAX - y; + } + xraw=(xraw*TFT_REALWIDTH)/(ADC_MAX+1); + yraw=(yraw*TFT_REALHEIGHT)/(ADC_MAX+1); + + *oX = xraw; + *oY = yraw; + *oZ = z; + } + else + { + *oX = 0; + *oY = 0; + *oZ = 0; + } +} + +void TFT_T_DMA::readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + readRaw(oX,oY,oZ); + // callibrate ... + if(*oX >= txMin) *oX = ((*oX - txMin)*TFT_REALWIDTH)/(txMax-txMin); + if(*oY >= tyMin) *oY = ((*oY - tyMin)*TFT_REALHEIGHT)/(tyMax-tyMin); + //Serial.print(*oX); + //Serial.print(" "); + //Serial.println(*oY); +} + + +/*********************************************************************************************** + No DMA functions + ***********************************************************************************************/ +void TFT_T_DMA::fillScreenNoDma(uint16_t color) { + setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + int i,j; + for (j=0; j(arx+arw)) || ((x+w)(ary+arh)) || ((y+h) arx) && (x<(arx+arw)) ) { + arw = arw - (x-arx); + arx = arx + (x-arx); + } else { + bmp_offx = arx; + } + if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) { + arw -= (arx+arw-x-w); + } + if ( (y > ary) && (y<(ary+arh)) ) { + arh = arh - (y-ary); + ary = ary + (y-ary); + } else { + bmp_offy = ary; + } + if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) { + arh -= (ary+arh-y-h); + } + } + + setArea(arx, ary, arx+arw-1, ary+arh-1); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + + bitmap = bitmap + bmp_offy*w + bmp_offx; + for (int row=0;row> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + } + bits = *charpt++; + digitalWrite(_dc, 1); + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + } + x +=8; +#ifdef ILI9341 + digitalWrite(_dc, 0); + SPI.transfer(ILI9341_SLPOUT); + digitalWrite(_dc, 1); +#endif + digitalWrite(_cs, 1); + SPI.endTransaction(); + } + + setArea(0, 0, (TFT_REALWIDTH-1), (TFT_REALHEIGHT-1)); +} + + +void TFT_T_DMA::drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color) { + setArea(x,y,x+w-1,y+h-1); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + int i; + for (i=0; i<(w*h); i++) + { + digitalWrite(_dc, 1); + SPI.transfer16(color); + } +#ifdef ILI9341 + digitalWrite(_dc, 0); + SPI.transfer(ILI9341_SLPOUT); + digitalWrite(_dc, 1); +#endif + digitalWrite(_cs, 1); + SPI.endTransaction(); + + setArea(0, 0, (TFT_REALWIDTH-1), (TFT_REALHEIGHT-1)); +} + + + +/*********************************************************************************************** + DMA functions + ***********************************************************************************************/ +uint16_t * TFT_T_DMA::getLineBuffer(int j) +{ + uint16_t * block=blocks[j>>6]; + return(&block[(j&0x3F)*TFT_REALWIDTH]); +} + +void TFT_T_DMA::writeScreen(int width, int height, int stride, uint8_t *buf, uint16_t *palette16) { + uint8_t *buffer=buf; + uint8_t *src; + + int i,j,y=0; + if (width*2 <= TFT_REALWIDTH) { + for (j=0; j>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*TFT_WIDTH]; + src=buffer; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH+(TFT_WIDTH-width)/2]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*TFT_WIDTH+(TFT_WIDTH-width)/2]; + src=buffer; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH]; + if (width > TFT_WIDTH) { +#ifdef TFT_LINEARINT + int delta = (width/(width-TFT_WIDTH))-1; + int pos = delta; + for (int i=0; i> 8]&PAL_COLOR_MASK]; + pos +=step; + } +#endif + } + else if ((width*2) == TFT_WIDTH) { + for (int i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH]; + if (width > TFT_WIDTH) { +#ifdef TFT_LINEARINT + int delta = (width/(width-TFT_WIDTH))-1; + int pos = delta; + for (int i=0; i> 8]; + pos +=step; + } +#endif + } + else if ((width*2) == TFT_WIDTH) { + for (int i=0; i>6]; + uint16_t * dst=&block[(j&0x3F)*TFT_WIDTH]; + for (i=0; i>6]; + uint16_t * dst=&block[(l&0x3F)*TFT_WIDTH+x]; + for (i=0; i>6]; + dst=&block[(l&0x3F)*TFT_WIDTH+x]; + bits = *charpt; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + block=blocks[l>>6]; + dst=&block[(l&0x3F)*TFT_WIDTH+x]; + bits = *charpt++; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + x +=8; + } +} + +void TFT_T_DMA::drawSprite(int16_t x, int16_t y, const uint16_t *bitmap) { + drawSprite(x,y,bitmap, 0,0,0,0); +} + +void TFT_T_DMA::drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t arx, uint16_t ary, uint16_t arw, uint16_t arh) +{ + int bmp_offx = 0; + int bmp_offy = 0; + uint16_t *bmp_ptr; + + int w =*bitmap++; + int h = *bitmap++; + + + if ( (arw == 0) || (arh == 0) ) { + // no crop window + arx = x; + ary = y; + arw = w; + arh = h; + } + else { + if ( (x>(arx+arw)) || ((x+w)(ary+arh)) || ((y+h) arx) && (x<(arx+arw)) ) { + arw = arw - (x-arx); + arx = arx + (x-arx); + } else { + bmp_offx = arx; + } + if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) { + arw -= (arx+arw-x-w); + } + if ( (y > ary) && (y<(ary+arh)) ) { + arh = arh - (y-ary); + ary = ary + (y-ary); + } else { + bmp_offy = ary; + } + if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) { + arh -= (ary+arh-y-h); + } + } + + + int l=ary; + bitmap = bitmap + bmp_offy*w + bmp_offx; + for (int row=0;row>6]; + uint16_t * dst=&block[(l&0x3F)*TFT_WIDTH+arx]; + bmp_ptr = (uint16_t*)bitmap; + for (int col=0;col +#include +#include +#endif + +#include "tft_t_dma_config.h" + +#define RGBVAL32(r,g,b) ( (r<<16) | (g<<8) | b ) +#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) ) +#define RGBVAL8(r,g,b) ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) ) +#define R16(rgb) ((rgb>>8)&0xf8) +#define G16(rgb) ((rgb>>3)&0xfc) +#define B16(rgb) ((rgb<<3)&0xf8) + +#define PAL_COLOR_MASK 0xff + +#define TFT_HEIGHT 240 + +#ifdef ILI9341 +#define TFT_WIDTH 320 +#define TFT_REALWIDTH 320 +#define TFT_REALHEIGHT 240 +#endif +#ifdef ST7789 +#define TFT_WIDTH 240 +#define TFT_REALWIDTH 240 +#define TFT_REALHEIGHT 240 +#endif + +#define LINES_PER_BLOCK 64 +#define NR_OF_BLOCK 4 +#define SCREEN_DMA_NUM_SETTINGS NR_OF_BLOCK + + +#ifdef ILI9341 + +#define ILI9341_NOP 0x00 +#define ILI9341_SWRESET 0x01 +#define ILI9341_RDDID 0x04 +#define ILI9341_RDDST 0x09 + +#define ILI9341_SLPIN 0x10 +#define ILI9341_SLPOUT 0x11 +#define ILI9341_PTLON 0x12 +#define ILI9341_NORON 0x13 + +#define ILI9341_RDMODE 0x0A +#define ILI9341_RDMADCTL 0x0B +#define ILI9341_RDPIXFMT 0x0C +#define ILI9341_RDIMGFMT 0x0D +#define ILI9341_RDSELFDIAG 0x0F + +#define ILI9341_INVOFF 0x20 +#define ILI9341_INVON 0x21 +#define ILI9341_GAMMASET 0x26 +#define ILI9341_DISPOFF 0x28 +#define ILI9341_DISPON 0x29 + +#define ILI9341_CASET 0x2A +#define ILI9341_PASET 0x2B +#define ILI9341_RAMWR 0x2C +#define ILI9341_RAMRD 0x2E + +#define ILI9341_PTLAR 0x30 +#define ILI9341_MADCTL 0x36 +#define ILI9341_VSCRSADD 0x37 +#define ILI9341_PIXFMT 0x3A + +#define ILI9341_FRMCTR1 0xB1 +#define ILI9341_FRMCTR2 0xB2 +#define ILI9341_FRMCTR3 0xB3 +#define ILI9341_INVCTR 0xB4 +#define ILI9341_DFUNCTR 0xB6 + +#define ILI9341_PWCTR1 0xC0 +#define ILI9341_PWCTR2 0xC1 +#define ILI9341_PWCTR3 0xC2 +#define ILI9341_PWCTR4 0xC3 +#define ILI9341_PWCTR5 0xC4 +#define ILI9341_VMCTR1 0xC5 +#define ILI9341_VMCTR2 0xC7 + +#define ILI9341_RDID1 0xDA +#define ILI9341_RDID2 0xDB +#define ILI9341_RDID3 0xDC +#define ILI9341_RDID4 0xDD + +#define ILI9341_GMCTRP1 0xE0 +#define ILI9341_GMCTRN1 0xE1 + +#define ILI9341_MADCTL_MY 0x80 +#define ILI9341_MADCTL_MX 0x40 +#define ILI9341_MADCTL_MV 0x20 +#define ILI9341_MADCTL_ML 0x10 +#define ILI9341_MADCTL_RGB 0x00 +#define ILI9341_MADCTL_BGR 0x08 +#define ILI9341_MADCTL_MH 0x04 + +#define TFT_CASET ILI9341_CASET +#define TFT_PASET ILI9341_PASET +#define TFT_RAMWR ILI9341_RAMWR +#define TFT_MADCTL ILI9341_MADCTL + +#endif + + +#ifdef ST7789 + +#define ST7735_NOP 0x00 +#define ST7735_SWRESET 0x01 +#define ST7735_RDDID 0x04 +#define ST7735_RDDST 0x09 + +#define ST7735_SLPIN 0x10 +#define ST7735_SLPOUT 0x11 +#define ST7735_PTLON 0x12 +#define ST7735_NORON 0x13 + +#define ST7735_INVOFF 0x20 +#define ST7735_INVON 0x21 +#define ST7735_DISPOFF 0x28 +#define ST7735_DISPON 0x29 +#define ST7735_CASET 0x2A +#define ST7735_RASET 0x2B +#define ST7735_RAMWR 0x2C +#define ST7735_RAMRD 0x2E + +#define ST7735_PTLAR 0x30 +#define ST7735_COLMOD 0x3A +#define ST7735_MADCTL 0x36 + +#define ST7735_FRMCTR1 0xB1 +#define ST7735_FRMCTR2 0xB2 +#define ST7735_FRMCTR3 0xB3 +#define ST7735_INVCTR 0xB4 +#define ST7735_DISSET5 0xB6 + +#define ST7735_PWCTR1 0xC0 +#define ST7735_PWCTR2 0xC1 +#define ST7735_PWCTR3 0xC2 +#define ST7735_PWCTR4 0xC3 +#define ST7735_PWCTR5 0xC4 +#define ST7735_VMCTR1 0xC5 + +#define ST7735_RDID1 0xDA +#define ST7735_RDID2 0xDB +#define ST7735_RDID3 0xDC +#define ST7735_RDID4 0xDD + +#define ST7735_PWCTR6 0xFC + +#define ST7735_GMCTRP1 0xE0 +#define ST7735_GMCTRN1 0xE1 + +#define ST77XX_MADCTL_MY 0x80 +#define ST77XX_MADCTL_MX 0x40 +#define ST77XX_MADCTL_MV 0x20 +#define ST77XX_MADCTL_ML 0x10 +#define ST77XX_MADCTL_RGB 0x00 +#define ST77XX_MADCTL_BGR 0x08 +#define ST77XX_MADCTL_MH 0x04 + +#define TFT_CASET ST7735_CASET +#define TFT_PASET ST7735_RASET +#define TFT_RAMWR ST7735_RAMWR +#define TFT_MADCTL ST7735_MADCTL + +#endif + + + +#ifdef __cplusplus + +class TFT_T_DMA +{ + public: + TFT_T_DMA(uint8_t _CS, uint8_t _DC, uint8_t _RST = 255, uint8_t _MOSI=11, uint8_t _SCLK=13, uint8_t _MISO=12, uint8_t touch_cs=38, uint8_t touch_irq=37); + + void setArea(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2); + void begin(void); + void flipscreen(bool flip); + boolean isflipped(void); + void startDMA(void); + void stopDMA(); + + // Touch screen functions + #define TOUCH_ENABLED() ((_touch_cs != 255) && (_touch_irq != 255)) + bool isTouching(void) { return ((!TOUCH_ENABLED())?false:(digitalRead(_touch_irq) == LOW)); } + void readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax); + + // NoDMA functions + void writeScreenNoDma(const uint16_t *pcolors); + void fillScreenNoDma(uint16_t color); + void drawTextNoDma(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize); + void drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color); + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap); + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh); + + // DMA functions + uint16_t * getLineBuffer(int j); + void writeScreen(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int y, uint16_t *buf); + void fillScreen(uint16_t color); + void drawText(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize); + void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh); + + + protected: + uint8_t _rst, _cs, _dc; + uint8_t _miso, _mosi, _sclk; + uint8_t _touch_irq=255, _touch_cs=255; + bool flipped=false; + + void wait(void); + void enableTouchIrq(); +}; + +#endif +#endif + diff --git a/MCUME_teensy/teensygen/tft_t_dma_config.h b/MCUME_teensy/teensygen/tft_t_dma_config.h new file mode 100644 index 0000000..3006874 --- /dev/null +++ b/MCUME_teensy/teensygen/tft_t_dma_config.h @@ -0,0 +1,10 @@ +//#define ST7789 1 +#define ILI9341 1 +#define TFT_LINEARINT 1 +#define LINEARINT_HACK 1 + +//#define FLIP_SCREEN 1 +//#define TFT_DEBUG 1 +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) +#define TFT_STATICFB 1 +#endif diff --git a/MCUME_teensy/teensygen/vcnt.h b/MCUME_teensy/teensygen/vcnt.h new file mode 100644 index 0000000..dd21411 --- /dev/null +++ b/MCUME_teensy/teensygen/vcnt.h @@ -0,0 +1,28 @@ + +#ifndef _VCNT_H_ +#define _VCNT_H_ + +#include "arduinoproto.h" + +PROGMEM static const char vc28[262] = +{ + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, + 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, + 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF +}; + +#endif /* _VCNT_H_ */ diff --git a/MCUME_teensy/teensygen/vdp.c b/MCUME_teensy/teensygen/vdp.c new file mode 100644 index 0000000..85a57ad --- /dev/null +++ b/MCUME_teensy/teensygen/vdp.c @@ -0,0 +1,557 @@ + +#include "shared.h" +#include "vcnt.h" +#include "hcnt.h" +#include "hvc.h" + +/* Pack and unpack CRAM data */ +#define PACK_CRAM(d) ((((d)&0xE00)>>9)|(((d)&0x0E0)>>2)|(((d)&0x00E)<<5)) +#define UNPACK_CRAM(d) ((((d)&0x1C0)>>5)|((d)&0x038)<<2|(((d)&0x007)<<9)) + +/* Mark a pattern as dirty */ +#define MARK_BG_DIRTY(addr) \ +{ \ + int name = (addr >> 5) & 0x7FF; \ + if(bg_name_dirty[name] == 0) \ + { \ + bg_name_list[bg_list_index] = name; \ + bg_list_index += 1; \ + } \ + bg_name_dirty[name] |= (1 << ((addr >> 2) & 0x07)); \ +} + +/* Tables that define the playfield layout */ +uint8 shift_table[] = {6, 7, 0, 8}; +uint8 col_mask_table[] = {0x1F, 0x3F, 0x1F, 0x7F}; +uint16 row_mask_table[] = {0x0FF, 0x1FF, 0x2FF, 0x3FF}; +uint32 y_mask_table[] = {0x1FC0, 0x1FC0, 0x1F80, 0x1F00}; + +uint8 sat[0x400]; /* Internal copy of sprite attribute table */ +//uint8 vram[0x10000]; /* Video RAM (64Kx8) */ +uint8 cram[0x80]; /* On-chip color RAM (64x9) */ +uint8 vsram[0x80]; /* On-chip vertical scroll RAM (40x11) */ +uint8 reg[0x20]; /* Internal VDP registers (23x8) */ +uint16 addr; /* Address register */ +uint16 addr_latch; /* Latched A15, A14 of address */ +uint8 code; /* Code register */ +uint8 pending; /* Pending write flag */ +uint16 buffer; /* Read buffer */ +uint16 status; /* VDP status flags */ +uint16 ntab; /* Name table A base address */ +uint16 ntbb; /* Name table B base address */ +uint16 ntwb; /* Name table W base address */ +uint16 satb; /* Sprite attribute table base address */ +uint16 hscb; /* Horizontal scroll table base address */ +uint16 sat_base_mask; /* Base bits of SAT */ +uint16 sat_addr_mask; /* Index bits of SAT */ +uint8 is_color_dirty; /* 1= One or more colors have changed */ +uint8 color_dirty[0x40]; /* 1= This color is dirty */ +uint8 border; /* Border color index */ +uint8 is_border_dirty; /* 1= The border color has changed */ +//uint8 bg_name_dirty[0x800]; /* 1= This pattern is dirty */ +//uint16 bg_name_list[0x800]; /* List of modified pattern indices */ +uint16 bg_list_index; /* # of modified patterns in list */ +//uint8 bg_pattern_cache[0x80000];/* Cached and flipped patterns */ +uint8 playfield_shift; /* Width of planes A, B (in bits) */ +uint8 playfield_col_mask; /* Vertical scroll mask */ +uint16 playfield_row_mask; /* Horizontal scroll mask */ +uint32 y_mask; /* Name table Y-index bits mask */ +int hint_pending; /* 0= Line interrupt is pending */ +int vint_pending; /* 1= Frame interrupt is pending */ +int counter; /* Raster counter */ +int dma_fill; /* 1= DMA fill has been requested */ +int im2_flag; /* 1= Interlace mode 2 is being used */ +int frame_end; /* End-of-frame (IRQ line) */ +int v_counter; /* VDP scan line counter */ +int v_update; /* 1= VC was updated by a ctrl or HV read */ +void (*color_update)(int index, uint16 data); + +/*--------------------------------------------------------------------------*/ +/* Init, reset, shutdown functions */ +/*--------------------------------------------------------------------------*/ + +void vdp_init(void) +{ +} + +void vdp_reset(void) +{ + memset(sat, 0, sizeof(sat)); + memset(vram, 0, VRAM_SIZE); + memset(cram, 0, sizeof(cram)); + memset(vsram, 0, sizeof(vsram)); + memset(reg, 0, sizeof(reg)); + + addr = addr_latch = code = pending = buffer = status = 0; + ntab = ntbb = ntwb = satb = hscb = 0; + sat_base_mask = 0xFE00; + sat_addr_mask = 0x01FF; + + /* Mark all colors as dirty to force a palette update */ + is_color_dirty = 1; + memset(color_dirty, 1, 0x40); + border = 0x00; + is_border_dirty = 1; + + memset(bg_name_dirty, 0, BGNAMEDIRTY_SIZE); + memset(bg_name_list, 0, BGNAME_SIZE); + bg_list_index = 0; + memset(bg_pattern_cache, 0, BGPATTERN_CACH_SIZE); + + playfield_shift = 6; + playfield_col_mask = 0x1F; + playfield_row_mask = 0x0FF; + y_mask = 0x1FC0; + + hint_pending = vint_pending = 0; + counter = 0; + frame_end = 0xE0; + v_counter = v_update = 0; + + /* Initialize viewport */ + gbitmap.viewport.x = 0x20; + gbitmap.viewport.y = 0x20; + gbitmap.viewport.w = 256; + gbitmap.viewport.h = 224; + gbitmap.viewport.oh = 256; + gbitmap.viewport.ow = 224; + gbitmap.viewport.changed = 1; +} + +void vdp_shutdown(void) +{ +} + + +/*--------------------------------------------------------------------------*/ +/* Memory access functions */ +/*--------------------------------------------------------------------------*/ + +void vdp_ctrl_w(uint16 data) +{ + if(pending == 0) + { + if((data & 0xC000) == 0x8000) + { + uint8 r = (data >> 8) & 0x1F; + uint8 d = (data >> 0) & 0xFF; + vdp_reg_w(r, d); + } + else + { + pending = 1; + } + + addr = ((addr_latch & 0xC000) | (data & 0x3FFF)) & 0xFFFF; + code = ((code & 0x3C) | ((data >> 14) & 0x03)) & 0x3F; + } + else + { + /* Clear pending flag */ + pending = 0; + + /* Update address and code registers */ + addr = ((addr & 0x3FFF) | ((data & 3) << 14)) & 0xFFFF; + code = ((code & 0x03) | ((data >> 2) & 0x3C)) & 0x3F; + + /* Save address bits A15 and A14 */ + addr_latch = (addr & 0xC000); + + if((code & 0x20) && (reg[1] & 0x10)) + { + switch(reg[23] & 0xC0) + { + case 0x00: /* V bus to VDP DMA */ + case 0x40: /* V bus to VDP DMA */ + dma_vbus(); + break; + + case 0x80: /* VRAM fill */ + dma_fill = 1; + break; + + case 0xC0: /* VRAM copy */ + dma_copy(); + break; + } + } + } +} + +uint16 vdp_ctrl_r(void) +{ +#if 0 + int cycles = m68k_cycles_run(); + uint16 temp = status; + + /* Clear pending flag */ + pending = 0; + + /* VBlank flag is set when the screen is disabled */ + if((reg[1] & 0x40) == 0x00) + { + temp |= 0x0008; + } + + /* Clear collision flag on reads */ + status &= ~0x0020; + + /* Set HBlank flag based on H counter */ + if(reg[12] & 1) + { + int hc = cycle2hc40[(cycles % 487)]; + if((hc >= 0xB6) && (hc <= 0xFF)) temp |= 0x0004; + } + else + { + int hc = cycle2hc32[(cycles % 487)]; + if((hc >= 0x93) && (hc <= 0xFF)) temp |= 0x0004; + } + + /* Flag FIFO as empty */ + temp |= 0x0200; + + /* Clear unused bits */ + temp &= 0x03FF; + + return (temp); +#else + uint16 temp = (0x4e71 & 0xFC00); + pending = 0; + status &= ~0x0020; // clear sprite hit flag on reads + status |= 0x0200; // fifo empty + status ^= 0x0004; /* hack (red zone) */ + temp |= (status & 0x03BF); // clear spr over + return (temp); +#endif +} + + +void vdp_data_w(uint16 data) +{ + /* Clear pending flag */ + pending = 0; + + switch(code & 0x0F) + { + case 0x01: /* VRAM */ + /* Byte-swap data if A0 is set */ + if(addr & 1) data = (data >> 8) | (data << 8); + + /* Copy SAT data to the internal SAT */ + if((addr & sat_base_mask) == satb) + { + *(uint16 *)&sat[addr & sat_addr_mask] = data; + } + + /* Only write unique data to VRAM */ + if(data != *(uint16 *)&vram[addr & 0xFFFE]) + { + /* Write data to VRAM */ + *(uint16 *)&vram[addr & 0xFFFE] = data; + + /* Update the pattern cache */ + MARK_BG_DIRTY(addr); + } + break; + + case 0x03: /* CRAM */ + { + uint16 *p = (uint16 *)&cram[(addr & 0x7E)]; + data &= 0x0EEE; + if(data != *p) + { + int index = (addr >> 1) & 0x3F; + *p = PACK_CRAM(data); + + if((index & 0x0F) != 0x00) + { + color_dirty[index] = is_color_dirty = 1; + } + + if(index == border) + { + is_border_dirty = 1; + if(color_update) + { + color_update(0x00, *p); + color_update(0x40, *p); + color_update(0x80, *p); + } + } + + if(color_update) color_update(index, *p); + } + } + break; + + case 0x05: /* VSRAM */ + *(uint16 *)&vsram[(addr & 0x7E)] = data; + break; + } + + /* Bump address register */ + addr += reg[15]; + + if(dma_fill) + { + int length = (reg[20] << 8 | reg[19]) & 0xFFFF; + if(!length) length = 0x10000; + + do { + vram[(addr & 0xFFFF)] = (data >> 8) & 0xFF; + MARK_BG_DIRTY(addr); + addr += reg[15]; + } while(--length); + dma_fill = 0; + } +} + + +uint16 vdp_data_r(void) +{ + uint16 temp = 0; + + /* Clear pending flag */ + pending = 0; + + switch(code & 0x0F) + { + case 0x00: /* VRAM */ + temp = *(uint16 *)&vram[(addr & 0xFFFE)]; + break; + + case 0x08: /* CRAM */ + temp = *(uint16 *)&cram[(addr & 0x7E)]; + temp = UNPACK_CRAM(temp); + break; + + case 0x04: /* VSRAM */ + temp = *(uint16 *)&vsram[(addr & 0x7E)]; + break; + } + + /* Bump address register */ + addr += reg[15]; + + /* return data */ + return (temp); +} + + +/* + The reg[] array is updated at the *end* of this function, so the new + register data can be compared with the previous data. +*/ +void vdp_reg_w(uint8 r, uint8 d) +{ + switch(r) + { + case 0x00: /* CTRL #1 */ + + if(hint_pending) + { + if(d & 0x10) + { + m68k_set_irq(4); + } + else + { + /* Cancel pending level 4 interrupt */ + m68k_set_irq(0); + } + } + break; + + case 0x01: /* CTRL #2 */ + + if(vint_pending) + { + if(d & 0x20) + { + m68k_set_irq(6); + } + else + { + /* Cancel pending level 6 interrupt */ + m68k_set_irq(0); + } + } + + /* Change the frame timing */ + frame_end = (d & 8) ? 0xF0 : 0xE0; + + /* Check if the viewport height has actually been changed */ + if((reg[1] & 8) != (d & 8)) + { + /* Update the height of the viewport */ + gbitmap.viewport.oh = gbitmap.viewport.h; + gbitmap.viewport.h = (d & 8) ? 240 : 224; + gbitmap.viewport.changed = 1; + } + break; + + case 0x02: /* NTAB */ + ntab = (d << 10) & 0xE000; + break; + + case 0x03: /* NTWB */ + ntwb = (d << 10) & 0xF800; + if(reg[12] & 1) ntwb &= 0xF000; + break; + + case 0x04: /* NTBB */ + ntbb = (d << 13) & 0xE000; + break; + + case 0x05: /* SATB */ + sat_base_mask = (reg[12] & 1) ? 0xFC00 : 0xFE00; + sat_addr_mask = (reg[12] & 1) ? 0x03FF : 0x01FF; + satb = (d << 9) & sat_base_mask; + break; + + case 0x07: + d &= 0x3F; + + /* Check if the border color has actually changed */ + if(border != d) + { + /* Mark the border color as modified */ + border = d; + is_border_dirty = 1; + if(color_update) + { + color_update(0x00, *(uint16 *)&cram[(border << 1)]); + color_update(0x40, *(uint16 *)&cram[(border << 1)]); + color_update(0x80, *(uint16 *)&cram[(border << 1)]); + } + } + break; + + case 0x0C: + + /* Check if the viewport width has actually been changed */ + if((reg[0x0C] & 1) != (d & 1)) + { + /* Update the width of the viewport */ + gbitmap.viewport.ow = gbitmap.viewport.w; + gbitmap.viewport.w = (d & 1) ? 320 : 256; + gbitmap.viewport.changed = 1; + } + + /* See if the S/TE mode bit has changed */ + if((reg[0x0C] & 8) != (d & 8)) + { + int i; + reg[0x0C] = d; + + /* Update colors */ + if(color_update) + { + for(i = 0; i < 0x40; i += 1) + { + color_update(i, *(uint16 *)&cram[i << 1]); + } + color_update(0x00, *(uint16 *)&cram[border << 1]); + color_update(0x40, *(uint16 *)&cram[border << 1]); + color_update(0x80, *(uint16 *)&cram[border << 1]); + } + /* Flush palette */ + is_color_dirty = is_border_dirty = 1; + memset(color_dirty, 1, 0x40); + } + + /* Check interlace mode 2 setting */ + im2_flag = ((d & 0x06) == 0x06) ? 1 : 0; + + /* The following register updates check this value */ + reg[0x0C] = d; + + /* Update display-dependant registers */ + vdp_reg_w(0x03, reg[0x03]); + vdp_reg_w(0x05, reg[0x05]); + + break; + + case 0x0D: /* HSCB */ + hscb = (d << 10) & 0xFC00; + break; + + case 0x10: /* Playfield size */ + playfield_shift = shift_table[(d & 3)]; + playfield_col_mask = col_mask_table[(d & 3)]; + playfield_row_mask = row_mask_table[(d >> 4) & 3]; + y_mask = y_mask_table[(d & 3)]; + break; + } + + /* Write new register value */ + reg[r] = d; +} + + +uint16 vdp_hvc_r(void) +{ + int cycles = m68k_cycles_run(); + uint8 *hctab = (reg[12] & 1) ? cycle2hc40 : cycle2hc32; + int vc = vc28[v_counter]; + int hc = hctab[(cycles % 487)]; + return (vc << 8 | hc); +} + +/* + VRAM to VRAM copy + Read byte from VRAM (source), write to VRAM (addr), + bump source and add r15 to addr. + + - see how source addr is affected + (can it make high source byte inc?) +*/ +void dma_copy(void) +{ + int length = (reg[20] << 8 | reg[19]) & 0xFFFF; + int source = (reg[22] << 8 | reg[21]) & 0xFFFF; + if(!length) length = 0x10000; + + do { + uint8 temp = vram[source]; + vram[addr] = temp; + MARK_BG_DIRTY(addr); + source = (source + 1) & 0xFFFF; + addr = (addr + reg[15]) & 0xFFFF; + } while (--length); + + reg[19] = (length >> 0) & 0xFF; + reg[20] = (length >> 8) & 0xFF; +} + + +void dma_vbus(void) +{ + uint32 base, source = ((reg[23] & 0x7F) << 17 | reg[22] << 9 | reg[21] << 1) & 0xFFFFFE; + uint32 length = (reg[20] << 8 | reg[19]) & 0xFFFF; + + if(!length) length = 0x10000; + base = source; + + do { + uint16 temp = vdp_dma_r(source); + source += 2; + source = ((base & 0xFE0000) | (source & 0x1FFFF)); + vdp_data_w(temp); + } while (--length); + + reg[19] = (length >> 0) & 0xFF; + reg[20] = (length >> 8) & 0xFF; + + reg[21] = (source >> 1) & 0xFF; + reg[22] = (source >> 9) & 0xFF; + reg[23] = (reg[23] & 0x80) | ((source >> 17) & 0x7F); +} + + +void vdp_test_w(uint16 value) +{ +} + + diff --git a/MCUME_teensy/teensygen/vdp.h b/MCUME_teensy/teensygen/vdp.h new file mode 100644 index 0000000..042ab60 --- /dev/null +++ b/MCUME_teensy/teensygen/vdp.h @@ -0,0 +1,53 @@ + +#ifndef _VDP_H_ +#define _VDP_H_ + +/* Global variables */ +extern uint8 sat[0x400]; +//extern uint8 vram[0x10000]; +extern uint8 cram[0x80]; +extern uint8 vsram[0x80]; +extern uint8 reg[0x20]; +extern uint16 status; +extern uint16 ntab; +extern uint16 ntbb; +extern uint16 ntwb; +extern uint16 satb; +extern uint16 hscb; +extern uint8 is_color_dirty; +extern uint8 color_dirty[0x40]; +extern uint8 border; +extern uint8 is_border_dirty; +//extern uint8 bg_name_dirty[0x800]; +//extern uint16 bg_name_list[0x800]; +extern uint16 bg_list_index; +//extern uint8 bg_pattern_cache[0x80000]; +extern uint8 playfield_shift; +extern uint8 playfield_col_mask; +extern uint16 playfield_row_mask; +extern uint32 y_mask; +extern int vint_pending; +extern int hint_pending; +extern int scanline; +extern int counter; +extern int im2_flag; +extern int frame_end; +extern int v_counter, v_update; + +extern void (*color_update)(int index, uint16 data); + +/* Function prototypes */ +void vdp_init(void); +void vdp_reset(void); +void vdp_shutdown(void); +void vdp_ctrl_w(uint16 data); +uint16 vdp_ctrl_r(void); +void vdp_data_w(uint16 data); +uint16 vdp_data_r(void); +void vdp_reg_w(uint8 r, uint8 d); +uint16 vdp_hvc_r(void); +void dma_copy(void); +void dma_vbus(void); +void vdp_test_w(uint16 value); + +#endif /* _VDP_H_ */ diff --git a/MCUME_teensy/teensygen/z80.c b/MCUME_teensy/teensygen/z80.c new file mode 100644 index 0000000..01d5f26 --- /dev/null +++ b/MCUME_teensy/teensygen/z80.c @@ -0,0 +1,4514 @@ +/***************************************************************************** + * + * z80.c + * Portable Z80 emulator V2.8 + * + * Copyright (C) 1998,1999,2000 Juergen Buchmueller, all rights reserved. + * + * - This source code is released as freeware for non-commercial purposes. + * - You are free to use and redistribute this code in modified or + * unmodified form, provided you list me in the credits. + * - If you modify this source code, you must add a notice to each modified + * source file that it has been changed. If you're a nice person, you + * will clearly mark each change too. :) + * - If you wish to use this for commercial purposes, please contact me at + * pullmoll@t-online.de + * - The author of this copywritten work reserves the right to change the + * terms of its usage and license at any time, including retroactively + * - This entire notice must remain in the source code. + * + * Changes in 3.2 + * - Fixed undocumented flags XF & YF of RRCA, and CF and HF of + * INI/IND/OUTI/OUTD/INIR/INDR/OTIR/OTDR [Sean Young] + * Changes in 3.1 + * - removed the REPEAT_AT_ONCE execution of LDIR/CPIR etc. opcodes + * for readabilities sake and because the implementation was buggy + * (and I was not able to find the difference) + * Changes in 3.0 + * - 'finished' switch to dynamically overrideable cycle count tables + * Changes in 2.9: + * - added methods to access and override the cycle count tables + * - fixed handling and timing of multiple DD/FD prefixed opcodes + * Changes in 2.8: + * - OUTI/OUTD/OTIR/OTDR also pre-decrement the B register now. + * This was wrong because of a bug fix on the wrong side + * (astrocade sound driver). + * Changes in 2.7: + * - removed z80_vm specific code, it's not needed (and never was). + * Changes in 2.6: + * - BUSY_LOOP_HACKS needed to call change_pc16() earlier, before + * checking the opcodes at the new address, because otherwise they + * might access the old (wrong or even NULL) banked memory region. + * Thanks to Sean Young for finding this nasty bug. + * Changes in 2.5: + * - Burning cycles always adjusts the ICount by a multiple of 4. + * - In REPEAT_AT_ONCE cases the R register wasn't incremented twice + * per repetition as it should have been. Those repeated opcodes + * could also underflow the ICount. + * - Simplified TIME_LOOP_HACKS for BC and added two more for DE + HL + * timing loops. I think those hacks weren't endian safe before too. + * Changes in 2.4: + * - z80_reset zaps the entire context, sets IX and IY to 0xffff(!) and + * sets the Z flag. With these changes the Tehkan World Cup driver + * _seems_ to work again. + * Changes in 2.3: + * - External termination of the execution loop calls z80_burn() and + * z80_vm_burn() to burn an amount of cycles (R adjustment) + * - Shortcuts which burn CPU cycles (BUSY_LOOP_HACKS and TIME_LOOP_HACKS) + * now also adjust the R register depending on the skipped opcodes. + * Changes in 2.2: + * - Fixed bugs in CPL, SCF and CCF instructions flag handling. + * - Changed variable EA and ARG16() function to UINT32; this + * produces slightly more efficient code. + * - The DD/FD XY CB opcodes where XY is 40-7F and Y is not 6/E + * are changed to calls to the X6/XE opcodes to reduce object size. + * They're hardly ever used so this should not yield a speed penalty. + * New in 2.0: + * - Optional more exact Z80 emulation (#define Z80_EXACT 1) according + * to a detailed description by Sean Young which can be found at: + * http://www.msxnet.org/tech/Z80/z80undoc.txt + *****************************************************************************/ + + +#include "shared.h" +#include "cpuintrf.h" +#include "z80.h" + +#include "arduinoproto.h" + +#define cpu_readop cpu_readmem16 +#define cpu_readop_arg cpu_readmem16 + +#define VERBOSE 0 + +#if VERBOSE +#define LOG(x) logerror x +#else +#define LOG(x) +#endif + +/* execute main opcodes inside a big switch statement */ +#ifndef BIG_SWITCH +#define BIG_SWITCH 1 +#endif + +/* big flags array for ADD/ADC/SUB/SBC/CP results */ +//#define BIG_FLAGS_ARRAY 1 + +/* Set to 1 for a more exact (but somewhat slower) Z80 emulation */ +//#define Z80_EXACT 1 + +/* on JP and JR opcodes check for tight loops */ +#define BUSY_LOOP_HACKS 1 + +/* check for delay loops counting down BC */ +#define TIME_LOOP_HACKS 1 + +#ifdef X86_ASM +#undef BIG_FLAGS_ARRAY +#define BIG_FLAGS_ARRAY 0 +#endif + +#if 0 +static UINT8 z80_reg_layout[] = { + Z80_PC, Z80_SP, Z80_AF, Z80_BC, Z80_DE, Z80_HL, -1, + Z80_IX, Z80_IY, Z80_AF2,Z80_BC2,Z80_DE2,Z80_HL2,-1, + Z80_R, Z80_I, Z80_IM, Z80_IFF1,Z80_IFF2, -1, + Z80_NMI_STATE,Z80_IRQ_STATE,Z80_DC0,Z80_DC1,Z80_DC2,Z80_DC3, 0 +}; + +static UINT8 z80_win_layout[] = { + 27, 0,53, 4, /* register window (top rows) */ + 0, 0,26,22, /* disassembler window (left colums) */ + 27, 5,53, 8, /* memory #1 window (right, upper middle) */ + 27,14,53, 8, /* memory #2 window (right, lower middle) */ + 0,23,80, 1, /* command line window (bottom rows) */ +}; +#endif + +/****************************************************************************/ +/* The Z80 registers. HALT is set to 1 when the CPU is halted, the refresh */ +/* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128) */ +/****************************************************************************/ +typedef struct { +/* 00 */ PAIR PREPC,PC,SP,AF,BC,DE,HL,IX,IY; +/* 24 */ PAIR AF2,BC2,DE2,HL2; +/* 34 */ UINT8 R,R2,IFF1,IFF2,HALT,IM,I; +/* 3B */ UINT8 irq_max; /* number of daisy chain devices */ +/* 3C */ INT8 request_irq; /* daisy chain next request device */ +/* 3D */ INT8 service_irq; /* daisy chain next reti handling device */ +/* 3E */ UINT8 nmi_state; /* nmi line state */ +/* 3F */ UINT8 irq_state; /* irq line state */ +/* 40 */ UINT8 int_state[Z80_MAXDAISY]; +/* 44 */ Z80_DaisyChain irq[Z80_MAXDAISY]; +/* 84 */ int (*irq_callback)(int irqline); +/* 88 */ int extra_cycles; /* extra cycles for interrupts */ +} Z80_Regs; + +#define CF 0x01 +#define NF 0x02 +#define PF 0x04 +#define VF PF +#define XF 0x08 +#define HF 0x10 +#define YF 0x20 +#define ZF 0x40 +#define SF 0x80 + +#define INT_IRQ 0x01 +#define NMI_IRQ 0x02 + +#define _PPC Z80.PREPC.d /* previous program counter */ + +#define _PCD Z80.PC.d +#define _PC Z80.PC.w.l + +#define _SPD Z80.SP.d +#define _SP Z80.SP.w.l + +#define _AFD Z80.AF.d +#define _AF Z80.AF.w.l +#define _A Z80.AF.b.h +#define _F Z80.AF.b.l + +#define _BCD Z80.BC.d +#define _BC Z80.BC.w.l +#define _B Z80.BC.b.h +#define _C Z80.BC.b.l + +#define _DED Z80.DE.d +#define _DE Z80.DE.w.l +#define _D Z80.DE.b.h +#define _E Z80.DE.b.l + +#define _HLD Z80.HL.d +#define _HL Z80.HL.w.l +#define _H Z80.HL.b.h +#define _L Z80.HL.b.l + +#define _IXD Z80.IX.d +#define _IX Z80.IX.w.l +#define _HX Z80.IX.b.h +#define _LX Z80.IX.b.l + +#define _IYD Z80.IY.d +#define _IY Z80.IY.w.l +#define _HY Z80.IY.b.h +#define _LY Z80.IY.b.l + +#define _I Z80.I +#define _R Z80.R +#define _R2 Z80.R2 +#define _IM Z80.IM +#define _IFF1 Z80.IFF1 +#define _IFF2 Z80.IFF2 +#define _HALT Z80.HALT + +int z80_ICount; +static Z80_Regs Z80; +static UINT32 EA; +static int after_EI = 0; + +static UINT8 SZ[256]; /* zero and sign flags */ +static UINT8 SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */ +static UINT8 SZP[256]; /* zero, sign and parity flags */ +static UINT8 SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */ +static UINT8 SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */ + +#include "z80daa.h" + +#if BIG_FLAGS_ARRAY +//#include +static UINT8 *SZHVC_add = 0; +static UINT8 *SZHVC_sub = 0; +#endif + +#if Z80_EXACT +/* tmp1 value for ini/inir/outi/otir for [C.1-0][io.1-0] */ +static UINT8 irep_tmp1[4][4] = { + {0,0,1,0},{0,1,0,1},{1,0,1,1},{0,1,1,0} +}; + +/* tmp1 value for ind/indr/outd/otdr for [C.1-0][io.1-0] */ +static UINT8 drep_tmp1[4][4] = { + {0,1,0,0},{1,0,0,1},{0,0,1,0},{0,1,0,1} +}; + +/* tmp2 value for all in/out repeated opcodes for B.7-0 */ +static UINT8 breg_tmp2[256] = { + 0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1 +}; +#endif + + +PROGMEM static UINT8 cc_op[0x100] = { + 4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4, + 8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4, + 7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4, + 7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11, + 5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11, + 5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11, + 5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11}; + +PROGMEM static UINT8 cc_cb[0x100] = { + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8}; + +PROGMEM static UINT8 cc_ed[0x100] = { + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, +12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9, +12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9, +12,12,15,20, 8, 8, 8,18,12,12,15,20, 8, 8, 8,18, +12,12,15,20, 8, 8, 8, 8,12,12,15,20, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, +16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, +16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; + +PROGMEM static UINT8 cc_xy[0x100] = { + 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4, + 4,14,20,10, 9, 9, 9, 4, 4,15,20,10, 9, 9, 9, 4, + 4, 4, 4, 4,23,23,19, 4, 4,15, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9, +19,19,19,19,19,19, 4,19, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, + 4,14, 4,23, 4,15, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4,10, 4, 4, 4, 4, 4, 4}; + +PROGMEM static UINT8 cc_xycb[0x100] = { +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23}; + +/* extra cycles if jr/jp/call taken and 'interrupt latency' on rst 0-7 */ +PROGMEM static UINT8 cc_ex[0x100] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* DJNZ */ + 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, /* JR NZ/JR Z */ + 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, /* JR NC/JR C */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 5, 5, 5, 5, 0, 0, 0, 0, 5, 5, 5, 5, 0, 0, 0, 0, /* LDIR/CPIR/INIR/OTIR LDDR/CPDR/INDR/OTDR */ + 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, + 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, + 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2, + 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2}; + +static UINT8 *cc[6] = { cc_op, cc_cb, cc_ed, cc_xy, cc_xycb, cc_ex }; +#define Z80_TABLE_dd Z80_TABLE_xy +#define Z80_TABLE_fd Z80_TABLE_xy + +static void take_interrupt(void); + +#define PROTOTYPES(tablename,prefix) \ + static __inline__ void prefix##_00(void); static __inline__ void prefix##_01(void); static __inline__ void prefix##_02(void); static __inline__ void prefix##_03(void); \ + static __inline__ void prefix##_04(void); static __inline__ void prefix##_05(void); static __inline__ void prefix##_06(void); static __inline__ void prefix##_07(void); \ + static __inline__ void prefix##_08(void); static __inline__ void prefix##_09(void); static __inline__ void prefix##_0a(void); static __inline__ void prefix##_0b(void); \ + static __inline__ void prefix##_0c(void); static __inline__ void prefix##_0d(void); static __inline__ void prefix##_0e(void); static __inline__ void prefix##_0f(void); \ + static __inline__ void prefix##_10(void); static __inline__ void prefix##_11(void); static __inline__ void prefix##_12(void); static __inline__ void prefix##_13(void); \ + static __inline__ void prefix##_14(void); static __inline__ void prefix##_15(void); static __inline__ void prefix##_16(void); static __inline__ void prefix##_17(void); \ + static __inline__ void prefix##_18(void); static __inline__ void prefix##_19(void); static __inline__ void prefix##_1a(void); static __inline__ void prefix##_1b(void); \ + static __inline__ void prefix##_1c(void); static __inline__ void prefix##_1d(void); static __inline__ void prefix##_1e(void); static __inline__ void prefix##_1f(void); \ + static __inline__ void prefix##_20(void); static __inline__ void prefix##_21(void); static __inline__ void prefix##_22(void); static __inline__ void prefix##_23(void); \ + static __inline__ void prefix##_24(void); static __inline__ void prefix##_25(void); static __inline__ void prefix##_26(void); static __inline__ void prefix##_27(void); \ + static __inline__ void prefix##_28(void); static __inline__ void prefix##_29(void); static __inline__ void prefix##_2a(void); static __inline__ void prefix##_2b(void); \ + static __inline__ void prefix##_2c(void); static __inline__ void prefix##_2d(void); static __inline__ void prefix##_2e(void); static __inline__ void prefix##_2f(void); \ + static __inline__ void prefix##_30(void); static __inline__ void prefix##_31(void); static __inline__ void prefix##_32(void); static __inline__ void prefix##_33(void); \ + static __inline__ void prefix##_34(void); static __inline__ void prefix##_35(void); static __inline__ void prefix##_36(void); static __inline__ void prefix##_37(void); \ + static __inline__ void prefix##_38(void); static __inline__ void prefix##_39(void); static __inline__ void prefix##_3a(void); static __inline__ void prefix##_3b(void); \ + static __inline__ void prefix##_3c(void); static __inline__ void prefix##_3d(void); static __inline__ void prefix##_3e(void); static __inline__ void prefix##_3f(void); \ + static __inline__ void prefix##_40(void); static __inline__ void prefix##_41(void); static __inline__ void prefix##_42(void); static __inline__ void prefix##_43(void); \ + static __inline__ void prefix##_44(void); static __inline__ void prefix##_45(void); static __inline__ void prefix##_46(void); static __inline__ void prefix##_47(void); \ + static __inline__ void prefix##_48(void); static __inline__ void prefix##_49(void); static __inline__ void prefix##_4a(void); static __inline__ void prefix##_4b(void); \ + static __inline__ void prefix##_4c(void); static __inline__ void prefix##_4d(void); static __inline__ void prefix##_4e(void); static __inline__ void prefix##_4f(void); \ + static __inline__ void prefix##_50(void); static __inline__ void prefix##_51(void); static __inline__ void prefix##_52(void); static __inline__ void prefix##_53(void); \ + static __inline__ void prefix##_54(void); static __inline__ void prefix##_55(void); static __inline__ void prefix##_56(void); static __inline__ void prefix##_57(void); \ + static __inline__ void prefix##_58(void); static __inline__ void prefix##_59(void); static __inline__ void prefix##_5a(void); static __inline__ void prefix##_5b(void); \ + static __inline__ void prefix##_5c(void); static __inline__ void prefix##_5d(void); static __inline__ void prefix##_5e(void); static __inline__ void prefix##_5f(void); \ + static __inline__ void prefix##_60(void); static __inline__ void prefix##_61(void); static __inline__ void prefix##_62(void); static __inline__ void prefix##_63(void); \ + static __inline__ void prefix##_64(void); static __inline__ void prefix##_65(void); static __inline__ void prefix##_66(void); static __inline__ void prefix##_67(void); \ + static __inline__ void prefix##_68(void); static __inline__ void prefix##_69(void); static __inline__ void prefix##_6a(void); static __inline__ void prefix##_6b(void); \ + static __inline__ void prefix##_6c(void); static __inline__ void prefix##_6d(void); static __inline__ void prefix##_6e(void); static __inline__ void prefix##_6f(void); \ + static __inline__ void prefix##_70(void); static __inline__ void prefix##_71(void); static __inline__ void prefix##_72(void); static __inline__ void prefix##_73(void); \ + static __inline__ void prefix##_74(void); static __inline__ void prefix##_75(void); static __inline__ void prefix##_76(void); static __inline__ void prefix##_77(void); \ + static __inline__ void prefix##_78(void); static __inline__ void prefix##_79(void); static __inline__ void prefix##_7a(void); static __inline__ void prefix##_7b(void); \ + static __inline__ void prefix##_7c(void); static __inline__ void prefix##_7d(void); static __inline__ void prefix##_7e(void); static __inline__ void prefix##_7f(void); \ + static __inline__ void prefix##_80(void); static __inline__ void prefix##_81(void); static __inline__ void prefix##_82(void); static __inline__ void prefix##_83(void); \ + static __inline__ void prefix##_84(void); static __inline__ void prefix##_85(void); static __inline__ void prefix##_86(void); static __inline__ void prefix##_87(void); \ + static __inline__ void prefix##_88(void); static __inline__ void prefix##_89(void); static __inline__ void prefix##_8a(void); static __inline__ void prefix##_8b(void); \ + static __inline__ void prefix##_8c(void); static __inline__ void prefix##_8d(void); static __inline__ void prefix##_8e(void); static __inline__ void prefix##_8f(void); \ + static __inline__ void prefix##_90(void); static __inline__ void prefix##_91(void); static __inline__ void prefix##_92(void); static __inline__ void prefix##_93(void); \ + static __inline__ void prefix##_94(void); static __inline__ void prefix##_95(void); static __inline__ void prefix##_96(void); static __inline__ void prefix##_97(void); \ + static __inline__ void prefix##_98(void); static __inline__ void prefix##_99(void); static __inline__ void prefix##_9a(void); static __inline__ void prefix##_9b(void); \ + static __inline__ void prefix##_9c(void); static __inline__ void prefix##_9d(void); static __inline__ void prefix##_9e(void); static __inline__ void prefix##_9f(void); \ + static __inline__ void prefix##_a0(void); static __inline__ void prefix##_a1(void); static __inline__ void prefix##_a2(void); static __inline__ void prefix##_a3(void); \ + static __inline__ void prefix##_a4(void); static __inline__ void prefix##_a5(void); static __inline__ void prefix##_a6(void); static __inline__ void prefix##_a7(void); \ + static __inline__ void prefix##_a8(void); static __inline__ void prefix##_a9(void); static __inline__ void prefix##_aa(void); static __inline__ void prefix##_ab(void); \ + static __inline__ void prefix##_ac(void); static __inline__ void prefix##_ad(void); static __inline__ void prefix##_ae(void); static __inline__ void prefix##_af(void); \ + static __inline__ void prefix##_b0(void); static __inline__ void prefix##_b1(void); static __inline__ void prefix##_b2(void); static __inline__ void prefix##_b3(void); \ + static __inline__ void prefix##_b4(void); static __inline__ void prefix##_b5(void); static __inline__ void prefix##_b6(void); static __inline__ void prefix##_b7(void); \ + static __inline__ void prefix##_b8(void); static __inline__ void prefix##_b9(void); static __inline__ void prefix##_ba(void); static __inline__ void prefix##_bb(void); \ + static __inline__ void prefix##_bc(void); static __inline__ void prefix##_bd(void); static __inline__ void prefix##_be(void); static __inline__ void prefix##_bf(void); \ + static __inline__ void prefix##_c0(void); static __inline__ void prefix##_c1(void); static __inline__ void prefix##_c2(void); static __inline__ void prefix##_c3(void); \ + static __inline__ void prefix##_c4(void); static __inline__ void prefix##_c5(void); static __inline__ void prefix##_c6(void); static __inline__ void prefix##_c7(void); \ + static __inline__ void prefix##_c8(void); static __inline__ void prefix##_c9(void); static __inline__ void prefix##_ca(void); static __inline__ void prefix##_cb(void); \ + static __inline__ void prefix##_cc(void); static __inline__ void prefix##_cd(void); static __inline__ void prefix##_ce(void); static __inline__ void prefix##_cf(void); \ + static __inline__ void prefix##_d0(void); static __inline__ void prefix##_d1(void); static __inline__ void prefix##_d2(void); static __inline__ void prefix##_d3(void); \ + static __inline__ void prefix##_d4(void); static __inline__ void prefix##_d5(void); static __inline__ void prefix##_d6(void); static __inline__ void prefix##_d7(void); \ + static __inline__ void prefix##_d8(void); static __inline__ void prefix##_d9(void); static __inline__ void prefix##_da(void); static __inline__ void prefix##_db(void); \ + static __inline__ void prefix##_dc(void); static __inline__ void prefix##_dd(void); static __inline__ void prefix##_de(void); static __inline__ void prefix##_df(void); \ + static __inline__ void prefix##_e0(void); static __inline__ void prefix##_e1(void); static __inline__ void prefix##_e2(void); static __inline__ void prefix##_e3(void); \ + static __inline__ void prefix##_e4(void); static __inline__ void prefix##_e5(void); static __inline__ void prefix##_e6(void); static __inline__ void prefix##_e7(void); \ + static __inline__ void prefix##_e8(void); static __inline__ void prefix##_e9(void); static __inline__ void prefix##_ea(void); static __inline__ void prefix##_eb(void); \ + static __inline__ void prefix##_ec(void); static __inline__ void prefix##_ed(void); static __inline__ void prefix##_ee(void); static __inline__ void prefix##_ef(void); \ + static __inline__ void prefix##_f0(void); static __inline__ void prefix##_f1(void); static __inline__ void prefix##_f2(void); static __inline__ void prefix##_f3(void); \ + static __inline__ void prefix##_f4(void); static __inline__ void prefix##_f5(void); static __inline__ void prefix##_f6(void); static __inline__ void prefix##_f7(void); \ + static __inline__ void prefix##_f8(void); static __inline__ void prefix##_f9(void); static __inline__ void prefix##_fa(void); static __inline__ void prefix##_fb(void); \ + static __inline__ void prefix##_fc(void); static __inline__ void prefix##_fd(void); static __inline__ void prefix##_fe(void); static __inline__ void prefix##_ff(void); \ +PROGMEM static void (*tablename[0x100])(void) = { \ + prefix##_00,prefix##_01,prefix##_02,prefix##_03,prefix##_04,prefix##_05,prefix##_06,prefix##_07, \ + prefix##_08,prefix##_09,prefix##_0a,prefix##_0b,prefix##_0c,prefix##_0d,prefix##_0e,prefix##_0f, \ + prefix##_10,prefix##_11,prefix##_12,prefix##_13,prefix##_14,prefix##_15,prefix##_16,prefix##_17, \ + prefix##_18,prefix##_19,prefix##_1a,prefix##_1b,prefix##_1c,prefix##_1d,prefix##_1e,prefix##_1f, \ + prefix##_20,prefix##_21,prefix##_22,prefix##_23,prefix##_24,prefix##_25,prefix##_26,prefix##_27, \ + prefix##_28,prefix##_29,prefix##_2a,prefix##_2b,prefix##_2c,prefix##_2d,prefix##_2e,prefix##_2f, \ + prefix##_30,prefix##_31,prefix##_32,prefix##_33,prefix##_34,prefix##_35,prefix##_36,prefix##_37, \ + prefix##_38,prefix##_39,prefix##_3a,prefix##_3b,prefix##_3c,prefix##_3d,prefix##_3e,prefix##_3f, \ + prefix##_40,prefix##_41,prefix##_42,prefix##_43,prefix##_44,prefix##_45,prefix##_46,prefix##_47, \ + prefix##_48,prefix##_49,prefix##_4a,prefix##_4b,prefix##_4c,prefix##_4d,prefix##_4e,prefix##_4f, \ + prefix##_50,prefix##_51,prefix##_52,prefix##_53,prefix##_54,prefix##_55,prefix##_56,prefix##_57, \ + prefix##_58,prefix##_59,prefix##_5a,prefix##_5b,prefix##_5c,prefix##_5d,prefix##_5e,prefix##_5f, \ + prefix##_60,prefix##_61,prefix##_62,prefix##_63,prefix##_64,prefix##_65,prefix##_66,prefix##_67, \ + prefix##_68,prefix##_69,prefix##_6a,prefix##_6b,prefix##_6c,prefix##_6d,prefix##_6e,prefix##_6f, \ + prefix##_70,prefix##_71,prefix##_72,prefix##_73,prefix##_74,prefix##_75,prefix##_76,prefix##_77, \ + prefix##_78,prefix##_79,prefix##_7a,prefix##_7b,prefix##_7c,prefix##_7d,prefix##_7e,prefix##_7f, \ + prefix##_80,prefix##_81,prefix##_82,prefix##_83,prefix##_84,prefix##_85,prefix##_86,prefix##_87, \ + prefix##_88,prefix##_89,prefix##_8a,prefix##_8b,prefix##_8c,prefix##_8d,prefix##_8e,prefix##_8f, \ + prefix##_90,prefix##_91,prefix##_92,prefix##_93,prefix##_94,prefix##_95,prefix##_96,prefix##_97, \ + prefix##_98,prefix##_99,prefix##_9a,prefix##_9b,prefix##_9c,prefix##_9d,prefix##_9e,prefix##_9f, \ + prefix##_a0,prefix##_a1,prefix##_a2,prefix##_a3,prefix##_a4,prefix##_a5,prefix##_a6,prefix##_a7, \ + prefix##_a8,prefix##_a9,prefix##_aa,prefix##_ab,prefix##_ac,prefix##_ad,prefix##_ae,prefix##_af, \ + prefix##_b0,prefix##_b1,prefix##_b2,prefix##_b3,prefix##_b4,prefix##_b5,prefix##_b6,prefix##_b7, \ + prefix##_b8,prefix##_b9,prefix##_ba,prefix##_bb,prefix##_bc,prefix##_bd,prefix##_be,prefix##_bf, \ + prefix##_c0,prefix##_c1,prefix##_c2,prefix##_c3,prefix##_c4,prefix##_c5,prefix##_c6,prefix##_c7, \ + prefix##_c8,prefix##_c9,prefix##_ca,prefix##_cb,prefix##_cc,prefix##_cd,prefix##_ce,prefix##_cf, \ + prefix##_d0,prefix##_d1,prefix##_d2,prefix##_d3,prefix##_d4,prefix##_d5,prefix##_d6,prefix##_d7, \ + prefix##_d8,prefix##_d9,prefix##_da,prefix##_db,prefix##_dc,prefix##_dd,prefix##_de,prefix##_df, \ + prefix##_e0,prefix##_e1,prefix##_e2,prefix##_e3,prefix##_e4,prefix##_e5,prefix##_e6,prefix##_e7, \ + prefix##_e8,prefix##_e9,prefix##_ea,prefix##_eb,prefix##_ec,prefix##_ed,prefix##_ee,prefix##_ef, \ + prefix##_f0,prefix##_f1,prefix##_f2,prefix##_f3,prefix##_f4,prefix##_f5,prefix##_f6,prefix##_f7, \ + prefix##_f8,prefix##_f9,prefix##_fa,prefix##_fb,prefix##_fc,prefix##_fd,prefix##_fe,prefix##_ff \ +} + +PROTOTYPES(Z80op,op); +PROTOTYPES(Z80cb,cb); +PROTOTYPES(Z80dd,dd); +PROTOTYPES(Z80ed,ed); +PROTOTYPES(Z80fd,fd); +PROTOTYPES(Z80xycb,xycb); + +/****************************************************************************/ +/* Burn an odd amount of cycles, that is instructions taking something */ +/* different from 4 T-states per opcode (and R increment) */ +/****************************************************************************/ +static __inline__ void BURNODD(int cycles, int opcodes, int cyclesum) +{ + if( cycles > 0 ) + { + _R += (cycles / cyclesum) * opcodes; + z80_ICount -= (cycles / cyclesum) * cyclesum; + } +} + +/*************************************************************** + * define an opcode function + ***************************************************************/ +#define OP(prefix,opcode) static __inline__ void prefix##_##opcode(void) + +/*************************************************************** + * adjust cycle count by n T-states + ***************************************************************/ +#define CC(prefix,opcode) z80_ICount -= cc[Z80_TABLE_##prefix][opcode] + +/*************************************************************** + * execute an opcode + ***************************************************************/ +#define EXEC(prefix,opcode) \ +{ \ + unsigned op = opcode; \ + CC(prefix,op); \ + (*Z80##prefix[op])(); \ +} + +#if BIG_SWITCH +#define EXEC_INLINE(prefix,opcode) \ +{ \ + unsigned op = opcode; \ + CC(prefix,op); \ + switch(op) \ + { \ + case 0x00:prefix##_##00();break; case 0x01:prefix##_##01();break; case 0x02:prefix##_##02();break; case 0x03:prefix##_##03();break; \ + case 0x04:prefix##_##04();break; case 0x05:prefix##_##05();break; case 0x06:prefix##_##06();break; case 0x07:prefix##_##07();break; \ + case 0x08:prefix##_##08();break; case 0x09:prefix##_##09();break; case 0x0a:prefix##_##0a();break; case 0x0b:prefix##_##0b();break; \ + case 0x0c:prefix##_##0c();break; case 0x0d:prefix##_##0d();break; case 0x0e:prefix##_##0e();break; case 0x0f:prefix##_##0f();break; \ + case 0x10:prefix##_##10();break; case 0x11:prefix##_##11();break; case 0x12:prefix##_##12();break; case 0x13:prefix##_##13();break; \ + case 0x14:prefix##_##14();break; case 0x15:prefix##_##15();break; case 0x16:prefix##_##16();break; case 0x17:prefix##_##17();break; \ + case 0x18:prefix##_##18();break; case 0x19:prefix##_##19();break; case 0x1a:prefix##_##1a();break; case 0x1b:prefix##_##1b();break; \ + case 0x1c:prefix##_##1c();break; case 0x1d:prefix##_##1d();break; case 0x1e:prefix##_##1e();break; case 0x1f:prefix##_##1f();break; \ + case 0x20:prefix##_##20();break; case 0x21:prefix##_##21();break; case 0x22:prefix##_##22();break; case 0x23:prefix##_##23();break; \ + case 0x24:prefix##_##24();break; case 0x25:prefix##_##25();break; case 0x26:prefix##_##26();break; case 0x27:prefix##_##27();break; \ + case 0x28:prefix##_##28();break; case 0x29:prefix##_##29();break; case 0x2a:prefix##_##2a();break; case 0x2b:prefix##_##2b();break; \ + case 0x2c:prefix##_##2c();break; case 0x2d:prefix##_##2d();break; case 0x2e:prefix##_##2e();break; case 0x2f:prefix##_##2f();break; \ + case 0x30:prefix##_##30();break; case 0x31:prefix##_##31();break; case 0x32:prefix##_##32();break; case 0x33:prefix##_##33();break; \ + case 0x34:prefix##_##34();break; case 0x35:prefix##_##35();break; case 0x36:prefix##_##36();break; case 0x37:prefix##_##37();break; \ + case 0x38:prefix##_##38();break; case 0x39:prefix##_##39();break; case 0x3a:prefix##_##3a();break; case 0x3b:prefix##_##3b();break; \ + case 0x3c:prefix##_##3c();break; case 0x3d:prefix##_##3d();break; case 0x3e:prefix##_##3e();break; case 0x3f:prefix##_##3f();break; \ + case 0x40:prefix##_##40();break; case 0x41:prefix##_##41();break; case 0x42:prefix##_##42();break; case 0x43:prefix##_##43();break; \ + case 0x44:prefix##_##44();break; case 0x45:prefix##_##45();break; case 0x46:prefix##_##46();break; case 0x47:prefix##_##47();break; \ + case 0x48:prefix##_##48();break; case 0x49:prefix##_##49();break; case 0x4a:prefix##_##4a();break; case 0x4b:prefix##_##4b();break; \ + case 0x4c:prefix##_##4c();break; case 0x4d:prefix##_##4d();break; case 0x4e:prefix##_##4e();break; case 0x4f:prefix##_##4f();break; \ + case 0x50:prefix##_##50();break; case 0x51:prefix##_##51();break; case 0x52:prefix##_##52();break; case 0x53:prefix##_##53();break; \ + case 0x54:prefix##_##54();break; case 0x55:prefix##_##55();break; case 0x56:prefix##_##56();break; case 0x57:prefix##_##57();break; \ + case 0x58:prefix##_##58();break; case 0x59:prefix##_##59();break; case 0x5a:prefix##_##5a();break; case 0x5b:prefix##_##5b();break; \ + case 0x5c:prefix##_##5c();break; case 0x5d:prefix##_##5d();break; case 0x5e:prefix##_##5e();break; case 0x5f:prefix##_##5f();break; \ + case 0x60:prefix##_##60();break; case 0x61:prefix##_##61();break; case 0x62:prefix##_##62();break; case 0x63:prefix##_##63();break; \ + case 0x64:prefix##_##64();break; case 0x65:prefix##_##65();break; case 0x66:prefix##_##66();break; case 0x67:prefix##_##67();break; \ + case 0x68:prefix##_##68();break; case 0x69:prefix##_##69();break; case 0x6a:prefix##_##6a();break; case 0x6b:prefix##_##6b();break; \ + case 0x6c:prefix##_##6c();break; case 0x6d:prefix##_##6d();break; case 0x6e:prefix##_##6e();break; case 0x6f:prefix##_##6f();break; \ + case 0x70:prefix##_##70();break; case 0x71:prefix##_##71();break; case 0x72:prefix##_##72();break; case 0x73:prefix##_##73();break; \ + case 0x74:prefix##_##74();break; case 0x75:prefix##_##75();break; case 0x76:prefix##_##76();break; case 0x77:prefix##_##77();break; \ + case 0x78:prefix##_##78();break; case 0x79:prefix##_##79();break; case 0x7a:prefix##_##7a();break; case 0x7b:prefix##_##7b();break; \ + case 0x7c:prefix##_##7c();break; case 0x7d:prefix##_##7d();break; case 0x7e:prefix##_##7e();break; case 0x7f:prefix##_##7f();break; \ + case 0x80:prefix##_##80();break; case 0x81:prefix##_##81();break; case 0x82:prefix##_##82();break; case 0x83:prefix##_##83();break; \ + case 0x84:prefix##_##84();break; case 0x85:prefix##_##85();break; case 0x86:prefix##_##86();break; case 0x87:prefix##_##87();break; \ + case 0x88:prefix##_##88();break; case 0x89:prefix##_##89();break; case 0x8a:prefix##_##8a();break; case 0x8b:prefix##_##8b();break; \ + case 0x8c:prefix##_##8c();break; case 0x8d:prefix##_##8d();break; case 0x8e:prefix##_##8e();break; case 0x8f:prefix##_##8f();break; \ + case 0x90:prefix##_##90();break; case 0x91:prefix##_##91();break; case 0x92:prefix##_##92();break; case 0x93:prefix##_##93();break; \ + case 0x94:prefix##_##94();break; case 0x95:prefix##_##95();break; case 0x96:prefix##_##96();break; case 0x97:prefix##_##97();break; \ + case 0x98:prefix##_##98();break; case 0x99:prefix##_##99();break; case 0x9a:prefix##_##9a();break; case 0x9b:prefix##_##9b();break; \ + case 0x9c:prefix##_##9c();break; case 0x9d:prefix##_##9d();break; case 0x9e:prefix##_##9e();break; case 0x9f:prefix##_##9f();break; \ + case 0xa0:prefix##_##a0();break; case 0xa1:prefix##_##a1();break; case 0xa2:prefix##_##a2();break; case 0xa3:prefix##_##a3();break; \ + case 0xa4:prefix##_##a4();break; case 0xa5:prefix##_##a5();break; case 0xa6:prefix##_##a6();break; case 0xa7:prefix##_##a7();break; \ + case 0xa8:prefix##_##a8();break; case 0xa9:prefix##_##a9();break; case 0xaa:prefix##_##aa();break; case 0xab:prefix##_##ab();break; \ + case 0xac:prefix##_##ac();break; case 0xad:prefix##_##ad();break; case 0xae:prefix##_##ae();break; case 0xaf:prefix##_##af();break; \ + case 0xb0:prefix##_##b0();break; case 0xb1:prefix##_##b1();break; case 0xb2:prefix##_##b2();break; case 0xb3:prefix##_##b3();break; \ + case 0xb4:prefix##_##b4();break; case 0xb5:prefix##_##b5();break; case 0xb6:prefix##_##b6();break; case 0xb7:prefix##_##b7();break; \ + case 0xb8:prefix##_##b8();break; case 0xb9:prefix##_##b9();break; case 0xba:prefix##_##ba();break; case 0xbb:prefix##_##bb();break; \ + case 0xbc:prefix##_##bc();break; case 0xbd:prefix##_##bd();break; case 0xbe:prefix##_##be();break; case 0xbf:prefix##_##bf();break; \ + case 0xc0:prefix##_##c0();break; case 0xc1:prefix##_##c1();break; case 0xc2:prefix##_##c2();break; case 0xc3:prefix##_##c3();break; \ + case 0xc4:prefix##_##c4();break; case 0xc5:prefix##_##c5();break; case 0xc6:prefix##_##c6();break; case 0xc7:prefix##_##c7();break; \ + case 0xc8:prefix##_##c8();break; case 0xc9:prefix##_##c9();break; case 0xca:prefix##_##ca();break; case 0xcb:prefix##_##cb();break; \ + case 0xcc:prefix##_##cc();break; case 0xcd:prefix##_##cd();break; case 0xce:prefix##_##ce();break; case 0xcf:prefix##_##cf();break; \ + case 0xd0:prefix##_##d0();break; case 0xd1:prefix##_##d1();break; case 0xd2:prefix##_##d2();break; case 0xd3:prefix##_##d3();break; \ + case 0xd4:prefix##_##d4();break; case 0xd5:prefix##_##d5();break; case 0xd6:prefix##_##d6();break; case 0xd7:prefix##_##d7();break; \ + case 0xd8:prefix##_##d8();break; case 0xd9:prefix##_##d9();break; case 0xda:prefix##_##da();break; case 0xdb:prefix##_##db();break; \ + case 0xdc:prefix##_##dc();break; case 0xdd:prefix##_##dd();break; case 0xde:prefix##_##de();break; case 0xdf:prefix##_##df();break; \ + case 0xe0:prefix##_##e0();break; case 0xe1:prefix##_##e1();break; case 0xe2:prefix##_##e2();break; case 0xe3:prefix##_##e3();break; \ + case 0xe4:prefix##_##e4();break; case 0xe5:prefix##_##e5();break; case 0xe6:prefix##_##e6();break; case 0xe7:prefix##_##e7();break; \ + case 0xe8:prefix##_##e8();break; case 0xe9:prefix##_##e9();break; case 0xea:prefix##_##ea();break; case 0xeb:prefix##_##eb();break; \ + case 0xec:prefix##_##ec();break; case 0xed:prefix##_##ed();break; case 0xee:prefix##_##ee();break; case 0xef:prefix##_##ef();break; \ + case 0xf0:prefix##_##f0();break; case 0xf1:prefix##_##f1();break; case 0xf2:prefix##_##f2();break; case 0xf3:prefix##_##f3();break; \ + case 0xf4:prefix##_##f4();break; case 0xf5:prefix##_##f5();break; case 0xf6:prefix##_##f6();break; case 0xf7:prefix##_##f7();break; \ + case 0xf8:prefix##_##f8();break; case 0xf9:prefix##_##f9();break; case 0xfa:prefix##_##fa();break; case 0xfb:prefix##_##fb();break; \ + case 0xfc:prefix##_##fc();break; case 0xfd:prefix##_##fd();break; case 0xfe:prefix##_##fe();break; case 0xff:prefix##_##ff();break; \ + } \ +} +#else +#define EXEC_INLINE EXEC +#endif + + +/*************************************************************** + * Enter HALT state; write 1 to fake port on first execution + ***************************************************************/ +#define ENTER_HALT { \ + _PC--; \ + _HALT = 1; \ + if( !after_EI ) \ + z80_burn( z80_ICount ); \ +} + +/*************************************************************** + * Leave HALT state; write 0 to fake port + ***************************************************************/ +#define LEAVE_HALT { \ + if( _HALT ) \ + { \ + _HALT = 0; \ + _PC++; \ + } \ +} + +/*************************************************************** + * Input a byte from given I/O port + ***************************************************************/ +#define IN(port) ((UINT8)cpu_readport16(port)) + +/*************************************************************** + * Output a byte to given I/O port + ***************************************************************/ +#define OUT(port,value) cpu_writeport16(port,value) + +/*************************************************************** + * Read a byte from given memory location + ***************************************************************/ +#define RM(addr) (UINT8)cpu_readmem16(addr) + +/*************************************************************** + * Read a word from given memory location + ***************************************************************/ +static __inline__ void RM16( UINT32 addr, PAIR *r ) +{ + r->b.l = RM(addr); + r->b.h = RM((addr+1)&0xffff); +} + +/*************************************************************** + * Write a byte to given memory location + ***************************************************************/ +#define WM(addr,value) cpu_writemem16(addr,value) + +/*************************************************************** + * Write a word to given memory location + ***************************************************************/ +static __inline__ void WM16( UINT32 addr, PAIR *r ) +{ + WM(addr,r->b.l); + WM((addr+1)&0xffff,r->b.h); +} + +/*************************************************************** + * ROP() is identical to RM() except it is used for + * reading opcodes. In case of system with memory mapped I/O, + * this function can be used to greatly speed up emulation + ***************************************************************/ +static __inline__ UINT8 ROP(void) +{ + unsigned pc = _PCD; + _PC++; + return cpu_readop(pc); +} + +/**************************************************************** + * ARG() is identical to ROP() except it is used + * for reading opcode arguments. This difference can be used to + * support systems that use different encoding mechanisms for + * opcodes and opcode arguments + ***************************************************************/ +static __inline__ UINT8 ARG(void) +{ + unsigned pc = _PCD; + _PC++; + return cpu_readop_arg(pc); +} + +static __inline__ UINT32 ARG16(void) +{ + unsigned pc = _PCD; + _PC += 2; + return cpu_readop_arg(pc) | (cpu_readop_arg((pc+1)&0xffff) << 8); +} + +/*************************************************************** + * Calculate the effective address EA of an opcode using + * IX+offset resp. IY+offset addressing. + ***************************************************************/ +#define EAX EA = (UINT32)(UINT16)(_IX+(INT8)ARG()) +#define EAY EA = (UINT32)(UINT16)(_IY+(INT8)ARG()) + +/*************************************************************** + * POP + ***************************************************************/ +#define POP(DR) { RM16( _SPD, &Z80.DR ); _SP += 2; } + +/*************************************************************** + * PUSH + ***************************************************************/ +#define PUSH(SR) { _SP -= 2; WM16( _SPD, &Z80.SR ); } + +/*************************************************************** + * JP + ***************************************************************/ +#if BUSY_LOOP_HACKS +#define JP { \ + unsigned oldpc = _PCD-1; \ + _PCD = ARG16(); \ + /* speed up busy loop */ \ + if( _PCD == oldpc ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount, 1, cc[Z80_TABLE_op][0xc3] ); \ + } \ + else \ + { \ + UINT8 op = cpu_readop(_PCD); \ + if( _PCD == oldpc-1 ) \ + { \ + /* NOP - JP $-1 or EI - JP $-1 */ \ + if ( op == 0x00 || op == 0xfb ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount-cc[Z80_TABLE_op][0x00], \ + 2, cc[Z80_TABLE_op][0x00]+cc[Z80_TABLE_op][0xc3]); \ + } \ + } \ + else \ + /* LD SP,#xxxx - JP $-3 (Galaga) */ \ + if( _PCD == oldpc-3 && op == 0x31 ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount-cc[Z80_TABLE_op][0x31], \ + 2, cc[Z80_TABLE_op][0x31]+cc[Z80_TABLE_op][0xc3]); \ + } \ + } \ +} +#else +#define JP { \ + _PCD = ARG16(); \ +} +#endif + +/*************************************************************** + * JP_COND + ***************************************************************/ + +#define JP_COND(cond) \ + if( cond ) \ + { \ + _PCD = ARG16(); \ + } \ + else \ + { \ + _PC += 2; \ + } + +/*************************************************************** + * JR + ***************************************************************/ +#define JR() \ +{ \ + unsigned oldpc = _PCD-1; \ + INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \ + _PC += arg; /* so don't do _PC += ARG() */ \ + /* speed up busy loop */ \ + if( _PCD == oldpc ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount, 1, cc[Z80_TABLE_op][0x18] ); \ + } \ + else \ + { \ + UINT8 op = cpu_readop(_PCD); \ + if( _PCD == oldpc-1 ) \ + { \ + /* NOP - JR $-1 or EI - JR $-1 */ \ + if ( op == 0x00 || op == 0xfb ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount-cc[Z80_TABLE_op][0x00], \ + 2, cc[Z80_TABLE_op][0x00]+cc[Z80_TABLE_op][0x18]); \ + } \ + } \ + else \ + /* LD SP,#xxxx - JR $-3 */ \ + if( _PCD == oldpc-3 && op == 0x31 ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount-cc[Z80_TABLE_op][0x31], \ + 2, cc[Z80_TABLE_op][0x31]+cc[Z80_TABLE_op][0x18]); \ + } \ + } \ +} + +/*************************************************************** + * JR_COND + ***************************************************************/ +#define JR_COND(cond,opcode) \ + if( cond ) \ + { \ + INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \ + _PC += arg; /* so don't do _PC += ARG() */ \ + CC(ex,opcode); \ + } \ + else _PC++; \ + +/*************************************************************** + * CALL + ***************************************************************/ +#define CALL() \ + EA = ARG16(); \ + PUSH( PC ); \ + _PCD = EA; + +/*************************************************************** + * CALL_COND + ***************************************************************/ +#define CALL_COND(cond,opcode) \ + if( cond ) \ + { \ + EA = ARG16(); \ + PUSH( PC ); \ + _PCD = EA; \ + CC(ex,opcode); \ + } \ + else \ + { \ + _PC+=2; \ + } + +/*************************************************************** + * RET_COND + ***************************************************************/ +#define RET_COND(cond,opcode) \ + if( cond ) \ + { \ + POP(PC); \ + CC(ex,opcode); \ + } + +/*************************************************************** + * RETN + ***************************************************************/ +#define RETN { \ + POP(PC); \ + if( _IFF1 == 0 && _IFF2 == 1 ) \ + { \ + _IFF1 = 1; \ + if( Z80.irq_state != CLEAR_LINE || \ + Z80.request_irq >= 0 ) \ + { \ + take_interrupt(); \ + } \ + } \ + else _IFF1 = _IFF2; \ +} + +/*************************************************************** + * RETI + ***************************************************************/ +#define RETI { \ + int device = Z80.service_irq; \ + POP(PC); \ +/* according to http://www.msxnet.org/tech/Z80/z80undoc.txt */ \ +/* _IFF1 = _IFF2; */ \ + if( device >= 0 ) \ + { \ + Z80.irq[device].interrupt_reti(Z80.irq[device].irq_param); \ + } \ +} + +/*************************************************************** + * LD R,A + ***************************************************************/ +#define LD_R_A { \ + _R = _A; \ + _R2 = _A & 0x80; /* keep bit 7 of R */ \ +} + +/*************************************************************** + * LD A,R + ***************************************************************/ +#define LD_A_R { \ + _A = (_R & 0x7f) | _R2; \ + _F = (_F & CF) | SZ[_A] | ( _IFF2 << 2 ); \ +} + +/*************************************************************** + * LD I,A + ***************************************************************/ +#define LD_I_A { \ + _I = _A; \ +} + +/*************************************************************** + * LD A,I + ***************************************************************/ +#define LD_A_I { \ + _A = _I; \ + _F = (_F & CF) | SZ[_A] | ( _IFF2 << 2 ); \ +} + +/*************************************************************** + * RST + ***************************************************************/ +#define RST(addr) \ + PUSH( PC ); \ + _PCD = addr; + +/*************************************************************** + * INC r8 + ***************************************************************/ +static __inline__ UINT8 INC(UINT8 value) +{ + UINT8 res = value + 1; + _F = (_F & CF) | SZHV_inc[res]; + return (UINT8)res; +} + +/*************************************************************** + * DEC r8 + ***************************************************************/ +static __inline__ UINT8 DEC(UINT8 value) +{ + UINT8 res = value - 1; + _F = (_F & CF) | SZHV_dec[res]; + return res; +} + +/*************************************************************** + * RLCA + ***************************************************************/ +#if Z80_EXACT +#define RLCA \ + _A = (_A << 1) | (_A >> 7); \ + _F = (_F & (SF | ZF | PF)) | (_A & (YF | XF | CF)) +#else +#define RLCA \ + _A = (_A << 1) | (_A >> 7); \ + _F = (_F & (SF | ZF | YF | XF | PF)) | (_A & CF) +#endif + +/*************************************************************** + * RRCA + ***************************************************************/ +#if Z80_EXACT +#define RRCA \ + _F = (_F & (SF | ZF | PF)) | (_A & CF); \ + _A = (_A >> 1) | (_A << 7); \ + _F |= (_A & (YF | XF) ) +#else +#define RRCA \ + _F = (_F & (SF | ZF | YF | XF | PF)) | (_A & CF); \ + _A = (_A >> 1) | (_A << 7) +#endif + +/*************************************************************** + * RLA + ***************************************************************/ +#if Z80_EXACT +#define RLA { \ + UINT8 res = (_A << 1) | (_F & CF); \ + UINT8 c = (_A & 0x80) ? CF : 0; \ + _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \ + _A = res; \ +} +#else +#define RLA { \ + UINT8 res = (_A << 1) | (_F & CF); \ + UINT8 c = (_A & 0x80) ? CF : 0; \ + _F = (_F & (SF | ZF | YF | XF | PF)) | c; \ + _A = res; \ +} +#endif + +/*************************************************************** + * RRA + ***************************************************************/ +#if Z80_EXACT +#define RRA { \ + UINT8 res = (_A >> 1) | (_F << 7); \ + UINT8 c = (_A & 0x01) ? CF : 0; \ + _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \ + _A = res; \ +} +#else +#define RRA { \ + UINT8 res = (_A >> 1) | (_F << 7); \ + UINT8 c = (_A & 0x01) ? CF : 0; \ + _F = (_F & (SF | ZF | YF | XF | PF)) | c; \ + _A = res; \ +} +#endif + +/*************************************************************** + * RRD + ***************************************************************/ +#define RRD { \ + UINT8 n = RM(_HL); \ + WM( _HL, (n >> 4) | (_A << 4) ); \ + _A = (_A & 0xf0) | (n & 0x0f); \ + _F = (_F & CF) | SZP[_A]; \ +} + +/*************************************************************** + * RLD + ***************************************************************/ +#define RLD { \ + UINT8 n = RM(_HL); \ + WM( _HL, (n << 4) | (_A & 0x0f) ); \ + _A = (_A & 0xf0) | (n >> 4); \ + _F = (_F & CF) | SZP[_A]; \ +} + +/*************************************************************** + * ADD A,n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define ADD(value) \ + asm ( \ + " addb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " addb %1,%1 \n" \ + " addb %1,%1 \n" /* shift to P/V bit position */ \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" \ + " movb %0,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define ADD(value) \ + asm ( \ + " addb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " addb %1,%1 \n" \ + " addb %1,%1 \n" /* shift to P/V bit position */ \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define ADD(value) \ +{ \ + UINT32 ah = _AFD & 0xff00; \ + UINT32 res = (UINT8)((ah >> 8) + value); \ + _F = SZHVC_add[ah | res]; \ + _A = res; \ +} +#else +#define ADD(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A + val; \ + _F = SZ[(UINT8)res] | ((res >> 8) & CF) | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \ + _A = (UINT8)res; \ +} +#endif +#endif + +/*************************************************************** + * ADC A,n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define ADC(value) \ + asm ( \ + " shrb $1,%1 \n" \ + " adcb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " addb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + " movb %0,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define ADC(value) \ + asm ( \ + " shrb $1,%1 \n" \ + " adcb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " addb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define ADC(value) \ +{ \ + UINT32 ah = _AFD & 0xff00, c = _AFD & 1; \ + UINT32 res = (UINT8)((ah >> 8) + value + c); \ + _F = SZHVC_add[(c << 16) | ah | res]; \ + _A = res; \ +} +#else +#define ADC(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A + val + (_F & CF); \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \ + _A = res; \ +} +#endif +#endif + +/*************************************************************** + * SUB n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define SUB(value) \ + asm ( \ + " subb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + " movb %0,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define SUB(value) \ + asm ( \ + " subb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define SUB(value) \ +{ \ + UINT32 ah = _AFD & 0xff00; \ + UINT32 res = (UINT8)((ah >> 8) - value); \ + _F = SZHVC_sub[ah | res]; \ + _A = res; \ +} +#else +#define SUB(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A - val; \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A) & (_A ^ res) & 0x80) >> 5); \ + _A = res; \ +} +#endif +#endif + +/*************************************************************** + * SBC A,n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define SBC(value) \ + asm ( \ + " shrb $1,%1 \n" \ + " sbbb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + " movb %0,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define SBC(value) \ + asm ( \ + " shrb $1,%1 \n" \ + " sbbb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define SBC(value) \ +{ \ + UINT32 ah = _AFD & 0xff00, c = _AFD & 1; \ + UINT32 res = (UINT8)((ah >> 8) - value - c); \ + _F = SZHVC_sub[(c<<16) | ah | res]; \ + _A = res; \ +} +#else +#define SBC(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A - val - (_F & CF); \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A) & (_A ^ res) & 0x80) >> 5); \ + _A = res; \ +} +#endif +#endif + +/*************************************************************** + * NEG + ***************************************************************/ +#define NEG { \ + UINT8 value = _A; \ + _A = 0; \ + SUB(value); \ +} + +/*************************************************************** + * DAA + ***************************************************************/ +#define DAA { \ + int idx = _A; \ + if( _F & CF ) idx |= 0x100; \ + if( _F & HF ) idx |= 0x200; \ + if( _F & NF ) idx |= 0x400; \ + _AF = DAATable[idx]; \ +} + +/*************************************************************** + * AND n + ***************************************************************/ +#define AND(value) \ + _A &= value; \ + _F = SZP[_A] | HF + +/*************************************************************** + * OR n + ***************************************************************/ +#define OR(value) \ + _A |= value; \ + _F = SZP[_A] + +/*************************************************************** + * XOR n + ***************************************************************/ +#define XOR(value) \ + _A ^= value; \ + _F = SZP[_A] + +/*************************************************************** + * CP n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define CP(value) \ + asm ( \ + " cmpb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + " movb %2,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define CP(value) \ + asm ( \ + " cmpb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define CP(value) \ +{ \ + UINT32 ah = _AFD & 0xff00; \ + UINT32 res = (UINT8)((ah >> 8) - value); \ + _F = SZHVC_sub[ah | res]; \ +} +#else +#define CP(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A - val; \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ + ((_A ^ res ^ val) & HF) | \ + ((((val ^ _A) & (_A ^ res)) >> 5) & VF); \ +} +#endif +#endif + +/*************************************************************** + * EX AF,AF' + ***************************************************************/ +#define EX_AF { \ + PAIR tmp; \ + tmp = Z80.AF; Z80.AF = Z80.AF2; Z80.AF2 = tmp; \ +} + +/*************************************************************** + * EX DE,HL + ***************************************************************/ +#define EX_DE_HL { \ + PAIR tmp; \ + tmp = Z80.DE; Z80.DE = Z80.HL; Z80.HL = tmp; \ +} + +/*************************************************************** + * EXX + ***************************************************************/ +#define EXX { \ + PAIR tmp; \ + tmp = Z80.BC; Z80.BC = Z80.BC2; Z80.BC2 = tmp; \ + tmp = Z80.DE; Z80.DE = Z80.DE2; Z80.DE2 = tmp; \ + tmp = Z80.HL; Z80.HL = Z80.HL2; Z80.HL2 = tmp; \ +} + +/*************************************************************** + * EX (SP),r16 + ***************************************************************/ +#define EXSP(DR) \ +{ \ + PAIR tmp = { { 0, 0, 0, 0 } }; \ + RM16( _SPD, &tmp ); \ + WM16( _SPD, &Z80.DR ); \ + Z80.DR = tmp; \ +} + + +/*************************************************************** + * ADD16 + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define ADD16(DR,SR) \ + asm ( \ + " andb $0xc4,%1 \n" \ + " addb %%dl,%%cl \n" \ + " adcb %%dh,%%ch \n" \ + " lahf \n" \ + " andb $0x11,%%ah \n" \ + " orb %%ah,%1 \n" \ + " movb %%ch,%%ah \n" /* get result MSB */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=c" (Z80.DR.d), "=r" (_F) \ + :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d) \ + ) +#else +#define ADD16(DR,SR) \ + asm ( \ + " andb $0xc4,%1 \n" \ + " addb %%dl,%%cl \n" \ + " adcb %%dh,%%ch \n" \ + " lahf \n" \ + " andb $0x11,%%ah \n" \ + " orb %%ah,%1 \n" \ + :"=c" (Z80.DR.d), "=r" (_F) \ + :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d) \ + ) +#endif +#else +#define ADD16(DR,SR) \ +{ \ + UINT32 res = Z80.DR.d + Z80.SR.d; \ + _F = (_F & (SF | ZF | VF)) | \ + (((Z80.DR.d ^ res ^ Z80.SR.d) >> 8) & HF) | \ + ((res >> 16) & CF); \ + Z80.DR.w.l = (UINT16)res; \ +} +#endif + +/*************************************************************** + * ADC r16,r16 + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define ADC16(Reg) \ + asm ( \ + " shrb $1,%1 \n" \ + " adcb %%dl,%%cl \n" \ + " lahf \n" \ + " movb %%ah,%%dl \n" \ + " adcb %%dh,%%ch \n" \ + " lahf \n" \ + " setob %1 \n" \ + " orb $0xbf,%%dl \n" /* set all but zero */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ + " addb %1,%1 \n" \ + " orb %%ah,%1 \n" /* overflow into P/V */ \ + " andb %%dl,%1 \n" /* mask zero */ \ + " movb %%ch,%%ah \n" /* get result MSB */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=c" (_HLD), "=r" (_F) \ + :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ + ) +#else +#define ADC16(Reg) \ + asm ( \ + " shrb $1,%1 \n" \ + " adcb %%dl,%%cl \n" \ + " lahf \n" \ + " movb %%ah,%%dl \n" \ + " adcb %%dh,%%ch \n" \ + " lahf \n" \ + " setob %1 \n" \ + " orb $0xbf,%%dl \n" /* set all but zero */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ + " addb %1,%1 \n" \ + " orb %%ah,%1 \n" /* overflow into P/V */ \ + " andb %%dl,%1 \n" /* mask zero */ \ + :"=c" (_HLD), "=r" (_F) \ + :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ + ) +#endif +#else +#define ADC16(Reg) \ +{ \ + UINT32 res = _HLD + Z80.Reg.d + (_F & CF); \ + _F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) | \ + ((res >> 16) & CF) | \ + ((res >> 8) & SF) | \ + ((res & 0xffff) ? 0 : ZF) | \ + (((Z80.Reg.d ^ _HLD ^ 0x8000) & (Z80.Reg.d ^ res) & 0x8000) >> 13); \ + _HL = (UINT16)res; \ +} +#endif + +/*************************************************************** + * SBC r16,r16 + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define SBC16(Reg) \ +asm ( \ + " shrb $1,%1 \n" \ + " sbbb %%dl,%%cl \n" \ + " lahf \n" \ + " movb %%ah,%%dl \n" \ + " sbbb %%dh,%%ch \n" \ + " lahf \n" \ + " setob %1 \n" \ + " orb $0xbf,%%dl \n" /* set all but zero */ \ + " stc \n" \ + " adcb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ + " addb %1,%1 \n" \ + " orb %%ah,%1 \n" /* overflow into P/V */ \ + " andb %%dl,%1 \n" /* mask zero */ \ + " movb %%ch,%%ah \n" /* get result MSB */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=c" (_HLD), "=r" (_F) \ + :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ + ) +#else +#define SBC16(Reg) \ +asm ( \ + " shrb $1,%1 \n" \ + " sbbb %%dl,%%cl \n" \ + " lahf \n" \ + " movb %%ah,%%dl \n" \ + " sbbb %%dh,%%ch \n" \ + " lahf \n" \ + " setob %1 \n" \ + " orb $0xbf,%%dl \n" /* set all but zero */ \ + " stc \n" \ + " adcb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ + " addb %1,%1 \n" \ + " orb %%ah,%1 \n" /* overflow into P/V */ \ + " andb %%dl,%1 \n" /* mask zero */ \ + :"=c" (_HLD), "=r" (_F) \ + :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ + ) +#endif +#else +#define SBC16(Reg) \ +{ \ + UINT32 res = _HLD - Z80.Reg.d - (_F & CF); \ + _F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) | NF | \ + ((res >> 16) & CF) | \ + ((res >> 8) & SF) | \ + ((res & 0xffff) ? 0 : ZF) | \ + (((Z80.Reg.d ^ _HLD) & (_HLD ^ res) &0x8000) >> 13); \ + _HL = (UINT16)res; \ +} +#endif + +/*************************************************************** + * RLC r8 + ***************************************************************/ +static __inline__ UINT8 RLC(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x80) ? CF : 0; + res = ((res << 1) | (res >> 7)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * RRC r8 + ***************************************************************/ +static __inline__ UINT8 RRC(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x01) ? CF : 0; + res = ((res >> 1) | (res << 7)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * RL r8 + ***************************************************************/ +static __inline__ UINT8 RL(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x80) ? CF : 0; + res = ((res << 1) | (_F & CF)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * RR r8 + ***************************************************************/ +static __inline__ UINT8 RR(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x01) ? CF : 0; + res = ((res >> 1) | (_F << 7)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * SLA r8 + ***************************************************************/ +static __inline__ UINT8 SLA(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x80) ? CF : 0; + res = (res << 1) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * SRA r8 + ***************************************************************/ +static __inline__ UINT8 SRA(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x01) ? CF : 0; + res = ((res >> 1) | (res & 0x80)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * SLL r8 + ***************************************************************/ +static __inline__ UINT8 SLL(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x80) ? CF : 0; + res = ((res << 1) | 0x01) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * SRL r8 + ***************************************************************/ +static __inline__ UINT8 SRL(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x01) ? CF : 0; + res = (res >> 1) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * BIT bit,r8 + ***************************************************************/ +#define BIT(bit,reg) \ + _F = (_F & CF) | HF | SZ_BIT[reg & (1<>8) & (YF|XF)) +#else +#define BIT_XY BIT +#endif + +/*************************************************************** + * RES bit,r8 + ***************************************************************/ +static __inline__ UINT8 RES(UINT8 bit, UINT8 value) +{ + return value & ~(1< flag 5 */ \ + if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + _HL++; _DE++; _BC--; \ + if( _BC ) _F |= VF; \ +} +#else +#define LDI { \ + WM( _DE, RM(_HL) ); \ + _F &= SF | ZF | YF | XF | CF; \ + _HL++; _DE++; _BC--; \ + if( _BC ) _F |= VF; \ +} +#endif + +/*************************************************************** + * CPI + ***************************************************************/ +#if Z80_EXACT +#define CPI { \ + UINT8 val = RM(_HL); \ + UINT8 res = _A - val; \ + _HL++; _BC--; \ + _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF; \ + if( _F & HF ) res -= 1; \ + if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ + if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + if( _BC ) _F |= VF; \ +} +#else +#define CPI { \ + UINT8 val = RM(_HL); \ + UINT8 res = _A - val; \ + _HL++; _BC--; \ + _F = (_F & CF) | SZ[res] | ((_A ^ val ^ res) & HF) | NF; \ + if( _BC ) _F |= VF; \ +} +#endif + +/*************************************************************** + * INI + ***************************************************************/ +#if Z80_EXACT +#define INI { \ + UINT8 io = IN(_BC); \ + _B--; \ + WM( _HL, io ); \ + _HL++; \ + _F = SZ[_B]; \ + if( io & SF ) _F |= NF; \ + if( ( ( (_C + 1) & 0xff) + io) & 0x100 ) _F |= HF | CF; \ + if( (irep_tmp1[_C & 3][io & 3] ^ \ + breg_tmp2[_B] ^ \ + (_C >> 2) ^ \ + (io >> 2)) & 1 ) \ + _F |= PF; \ +} +#else +#define INI { \ + _B--; \ + WM( _HL, IN(_BC) ); \ + _HL++; \ + _F = (_B) ? NF : NF | ZF; \ +} +#endif + +/*************************************************************** + * OUTI + ***************************************************************/ +#if Z80_EXACT +#define OUTI { \ + UINT8 io = RM(_HL); \ + _B--; \ + OUT( _BC, io ); \ + _HL++; \ + _F = SZ[_B]; \ + if( io & SF ) _F |= NF; \ + if( ( ( (_C + 1) & 0xff) + io) & 0x100 ) _F |= HF | CF; \ + if( (irep_tmp1[_C & 3][io & 3] ^ \ + breg_tmp2[_B] ^ \ + (_C >> 2) ^ \ + (io >> 2)) & 1 ) \ + _F |= PF; \ +} +#else +#define OUTI { \ + _B--; \ + OUT( _BC, RM(_HL) ); \ + _HL++; \ + _F = (_B) ? NF : NF | ZF; \ +} +#endif + +/*************************************************************** + * LDD + ***************************************************************/ +#if Z80_EXACT +#define LDD { \ + UINT8 io = RM(_HL); \ + WM( _DE, io ); \ + _F &= SF | ZF | CF; \ + if( (_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ + if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + _HL--; _DE--; _BC--; \ + if( _BC ) _F |= VF; \ +} +#else +#define LDD { \ + WM( _DE, RM(_HL) ); \ + _F &= SF | ZF | YF | XF | CF; \ + _HL--; _DE--; _BC--; \ + if( _BC ) _F |= VF; \ +} +#endif + +/*************************************************************** + * CPD + ***************************************************************/ +#if Z80_EXACT +#define CPD { \ + UINT8 val = RM(_HL); \ + UINT8 res = _A - val; \ + _HL--; _BC--; \ + _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF; \ + if( _F & HF ) res -= 1; \ + if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ + if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + if( _BC ) _F |= VF; \ +} +#else +#define CPD { \ + UINT8 val = RM(_HL); \ + UINT8 res = _A - val; \ + _HL--; _BC--; \ + _F = (_F & CF) | SZ[res] | ((_A ^ val ^ res) & HF) | NF; \ + if( _BC ) _F |= VF; \ +} +#endif + +/*************************************************************** + * IND + ***************************************************************/ +#if Z80_EXACT +#define IND { \ + UINT8 io = IN(_BC); \ + _B--; \ + WM( _HL, io ); \ + _HL--; \ + _F = SZ[_B]; \ + if( io & SF ) _F |= NF; \ + if( ( ( (_C - 1) & 0xff) + io) & 0x100 ) _F |= HF | CF; \ + if( (drep_tmp1[_C & 3][io & 3] ^ \ + breg_tmp2[_B] ^ \ + (_C >> 2) ^ \ + (io >> 2)) & 1 ) \ + _F |= PF; \ +} +#else +#define IND { \ + _B--; \ + WM( _HL, IN(_BC) ); \ + _HL--; \ + _F = (_B) ? NF : NF | ZF; \ +} +#endif + +/*************************************************************** + * OUTD + ***************************************************************/ +#if Z80_EXACT +#define OUTD { \ + UINT8 io = RM(_HL); \ + _B--; \ + OUT( _BC, io ); \ + _HL--; \ + _F = SZ[_B]; \ + if( io & SF ) _F |= NF; \ + if( ( ( (_C - 1) & 0xff) + io) & 0x100 ) _F |= HF | CF; \ + if( (drep_tmp1[_C & 3][io & 3] ^ \ + breg_tmp2[_B] ^ \ + (_C >> 2) ^ \ + (io >> 2)) & 1 ) \ + _F |= PF; \ +} +#else +#define OUTD { \ + _B--; \ + OUT( _BC, RM(_HL) ); \ + _HL--; \ + _F = (_B) ? NF : NF | ZF; \ +} +#endif + +/*************************************************************** + * LDIR + ***************************************************************/ +#define LDIR \ + LDI; \ + if( _BC ) \ + { \ + _PC -= 2; \ + CC(ex,0xb0); \ + } + +/*************************************************************** + * CPIR + ***************************************************************/ +#define CPIR \ + CPI; \ + if( _BC && !(_F & ZF) ) \ + { \ + _PC -= 2; \ + CC(ex,0xb1); \ + } + +/*************************************************************** + * INIR + ***************************************************************/ +#define INIR \ + INI; \ + if( _B ) \ + { \ + _PC -= 2; \ + CC(ex,0xb2); \ + } + +/*************************************************************** + * OTIR + ***************************************************************/ +#define OTIR \ + OUTI; \ + if( _B ) \ + { \ + _PC -= 2; \ + CC(ex,0xb3); \ + } + +/*************************************************************** + * LDDR + ***************************************************************/ +#define LDDR \ + LDD; \ + if( _BC ) \ + { \ + _PC -= 2; \ + CC(ex,0xb8); \ + } + +/*************************************************************** + * CPDR + ***************************************************************/ +#define CPDR \ + CPD; \ + if( _BC && !(_F & ZF) ) \ + { \ + _PC -= 2; \ + CC(ex,0xb9); \ + } + +/*************************************************************** + * INDR + ***************************************************************/ +#define INDR \ + IND; \ + if( _B ) \ + { \ + _PC -= 2; \ + CC(ex,0xba); \ + } + +/*************************************************************** + * OTDR + ***************************************************************/ +#define OTDR \ + OUTD; \ + if( _B ) \ + { \ + _PC -= 2; \ + CC(ex,0xbb); \ + } + +/*************************************************************** + * EI + ***************************************************************/ +#define EI { \ + /* If interrupts were disabled, execute one more \ + * instruction and check the IRQ line. \ + * If not, simply set interrupt flip-flop 2 \ + */ \ + if( _IFF1 == 0 ) \ + { \ + _IFF1 = _IFF2 = 1; \ + _PPC = _PCD; \ + _R++; \ + while( cpu_readop(_PCD) == 0xfb ) /* more EIs? */ \ + { \ + CC(op,0xfb); \ + _PPC =_PCD; \ + _PC++; \ + _R++; \ + } \ + if( Z80.irq_state != CLEAR_LINE || \ + Z80.request_irq >= 0 ) \ + { \ + after_EI = 1; /* avoid cycle skip hacks */ \ + EXEC(op,ROP()); \ + after_EI = 0; \ + take_interrupt(); \ + } else EXEC(op,ROP()); \ + } else _IFF2 = 1; \ +} + +/********************************************************** + * opcodes with CB prefix + * rotate, shift and bit operations + **********************************************************/ +OP(cb,00) { _B = RLC(_B); } /* RLC B */ +OP(cb,01) { _C = RLC(_C); } /* RLC C */ +OP(cb,02) { _D = RLC(_D); } /* RLC D */ +OP(cb,03) { _E = RLC(_E); } /* RLC E */ +OP(cb,04) { _H = RLC(_H); } /* RLC H */ +OP(cb,05) { _L = RLC(_L); } /* RLC L */ +OP(cb,06) { WM( _HL, RLC(RM(_HL)) ); } /* RLC (HL) */ +OP(cb,07) { _A = RLC(_A); } /* RLC A */ + +OP(cb,08) { _B = RRC(_B); } /* RRC B */ +OP(cb,09) { _C = RRC(_C); } /* RRC C */ +OP(cb,0a) { _D = RRC(_D); } /* RRC D */ +OP(cb,0b) { _E = RRC(_E); } /* RRC E */ +OP(cb,0c) { _H = RRC(_H); } /* RRC H */ +OP(cb,0d) { _L = RRC(_L); } /* RRC L */ +OP(cb,0e) { WM( _HL, RRC(RM(_HL)) ); } /* RRC (HL) */ +OP(cb,0f) { _A = RRC(_A); } /* RRC A */ + +OP(cb,10) { _B = RL(_B); } /* RL B */ +OP(cb,11) { _C = RL(_C); } /* RL C */ +OP(cb,12) { _D = RL(_D); } /* RL D */ +OP(cb,13) { _E = RL(_E); } /* RL E */ +OP(cb,14) { _H = RL(_H); } /* RL H */ +OP(cb,15) { _L = RL(_L); } /* RL L */ +OP(cb,16) { WM( _HL, RL(RM(_HL)) ); } /* RL (HL) */ +OP(cb,17) { _A = RL(_A); } /* RL A */ + +OP(cb,18) { _B = RR(_B); } /* RR B */ +OP(cb,19) { _C = RR(_C); } /* RR C */ +OP(cb,1a) { _D = RR(_D); } /* RR D */ +OP(cb,1b) { _E = RR(_E); } /* RR E */ +OP(cb,1c) { _H = RR(_H); } /* RR H */ +OP(cb,1d) { _L = RR(_L); } /* RR L */ +OP(cb,1e) { WM( _HL, RR(RM(_HL)) ); } /* RR (HL) */ +OP(cb,1f) { _A = RR(_A); } /* RR A */ + +OP(cb,20) { _B = SLA(_B); } /* SLA B */ +OP(cb,21) { _C = SLA(_C); } /* SLA C */ +OP(cb,22) { _D = SLA(_D); } /* SLA D */ +OP(cb,23) { _E = SLA(_E); } /* SLA E */ +OP(cb,24) { _H = SLA(_H); } /* SLA H */ +OP(cb,25) { _L = SLA(_L); } /* SLA L */ +OP(cb,26) { WM( _HL, SLA(RM(_HL)) ); } /* SLA (HL) */ +OP(cb,27) { _A = SLA(_A); } /* SLA A */ + +OP(cb,28) { _B = SRA(_B); } /* SRA B */ +OP(cb,29) { _C = SRA(_C); } /* SRA C */ +OP(cb,2a) { _D = SRA(_D); } /* SRA D */ +OP(cb,2b) { _E = SRA(_E); } /* SRA E */ +OP(cb,2c) { _H = SRA(_H); } /* SRA H */ +OP(cb,2d) { _L = SRA(_L); } /* SRA L */ +OP(cb,2e) { WM( _HL, SRA(RM(_HL)) ); } /* SRA (HL) */ +OP(cb,2f) { _A = SRA(_A); } /* SRA A */ + +OP(cb,30) { _B = SLL(_B); } /* SLL B */ +OP(cb,31) { _C = SLL(_C); } /* SLL C */ +OP(cb,32) { _D = SLL(_D); } /* SLL D */ +OP(cb,33) { _E = SLL(_E); } /* SLL E */ +OP(cb,34) { _H = SLL(_H); } /* SLL H */ +OP(cb,35) { _L = SLL(_L); } /* SLL L */ +OP(cb,36) { WM( _HL, SLL(RM(_HL)) ); } /* SLL (HL) */ +OP(cb,37) { _A = SLL(_A); } /* SLL A */ + +OP(cb,38) { _B = SRL(_B); } /* SRL B */ +OP(cb,39) { _C = SRL(_C); } /* SRL C */ +OP(cb,3a) { _D = SRL(_D); } /* SRL D */ +OP(cb,3b) { _E = SRL(_E); } /* SRL E */ +OP(cb,3c) { _H = SRL(_H); } /* SRL H */ +OP(cb,3d) { _L = SRL(_L); } /* SRL L */ +OP(cb,3e) { WM( _HL, SRL(RM(_HL)) ); } /* SRL (HL) */ +OP(cb,3f) { _A = SRL(_A); } /* SRL A */ + +OP(cb,40) { BIT(0,_B); } /* BIT 0,B */ +OP(cb,41) { BIT(0,_C); } /* BIT 0,C */ +OP(cb,42) { BIT(0,_D); } /* BIT 0,D */ +OP(cb,43) { BIT(0,_E); } /* BIT 0,E */ +OP(cb,44) { BIT(0,_H); } /* BIT 0,H */ +OP(cb,45) { BIT(0,_L); } /* BIT 0,L */ +OP(cb,46) { BIT(0,RM(_HL)); } /* BIT 0,(HL) */ +OP(cb,47) { BIT(0,_A); } /* BIT 0,A */ + +OP(cb,48) { BIT(1,_B); } /* BIT 1,B */ +OP(cb,49) { BIT(1,_C); } /* BIT 1,C */ +OP(cb,4a) { BIT(1,_D); } /* BIT 1,D */ +OP(cb,4b) { BIT(1,_E); } /* BIT 1,E */ +OP(cb,4c) { BIT(1,_H); } /* BIT 1,H */ +OP(cb,4d) { BIT(1,_L); } /* BIT 1,L */ +OP(cb,4e) { BIT(1,RM(_HL)); } /* BIT 1,(HL) */ +OP(cb,4f) { BIT(1,_A); } /* BIT 1,A */ + +OP(cb,50) { BIT(2,_B); } /* BIT 2,B */ +OP(cb,51) { BIT(2,_C); } /* BIT 2,C */ +OP(cb,52) { BIT(2,_D); } /* BIT 2,D */ +OP(cb,53) { BIT(2,_E); } /* BIT 2,E */ +OP(cb,54) { BIT(2,_H); } /* BIT 2,H */ +OP(cb,55) { BIT(2,_L); } /* BIT 2,L */ +OP(cb,56) { BIT(2,RM(_HL)); } /* BIT 2,(HL) */ +OP(cb,57) { BIT(2,_A); } /* BIT 2,A */ + +OP(cb,58) { BIT(3,_B); } /* BIT 3,B */ +OP(cb,59) { BIT(3,_C); } /* BIT 3,C */ +OP(cb,5a) { BIT(3,_D); } /* BIT 3,D */ +OP(cb,5b) { BIT(3,_E); } /* BIT 3,E */ +OP(cb,5c) { BIT(3,_H); } /* BIT 3,H */ +OP(cb,5d) { BIT(3,_L); } /* BIT 3,L */ +OP(cb,5e) { BIT(3,RM(_HL)); } /* BIT 3,(HL) */ +OP(cb,5f) { BIT(3,_A); } /* BIT 3,A */ + +OP(cb,60) { BIT(4,_B); } /* BIT 4,B */ +OP(cb,61) { BIT(4,_C); } /* BIT 4,C */ +OP(cb,62) { BIT(4,_D); } /* BIT 4,D */ +OP(cb,63) { BIT(4,_E); } /* BIT 4,E */ +OP(cb,64) { BIT(4,_H); } /* BIT 4,H */ +OP(cb,65) { BIT(4,_L); } /* BIT 4,L */ +OP(cb,66) { BIT(4,RM(_HL)); } /* BIT 4,(HL) */ +OP(cb,67) { BIT(4,_A); } /* BIT 4,A */ + +OP(cb,68) { BIT(5,_B); } /* BIT 5,B */ +OP(cb,69) { BIT(5,_C); } /* BIT 5,C */ +OP(cb,6a) { BIT(5,_D); } /* BIT 5,D */ +OP(cb,6b) { BIT(5,_E); } /* BIT 5,E */ +OP(cb,6c) { BIT(5,_H); } /* BIT 5,H */ +OP(cb,6d) { BIT(5,_L); } /* BIT 5,L */ +OP(cb,6e) { BIT(5,RM(_HL)); } /* BIT 5,(HL) */ +OP(cb,6f) { BIT(5,_A); } /* BIT 5,A */ + +OP(cb,70) { BIT(6,_B); } /* BIT 6,B */ +OP(cb,71) { BIT(6,_C); } /* BIT 6,C */ +OP(cb,72) { BIT(6,_D); } /* BIT 6,D */ +OP(cb,73) { BIT(6,_E); } /* BIT 6,E */ +OP(cb,74) { BIT(6,_H); } /* BIT 6,H */ +OP(cb,75) { BIT(6,_L); } /* BIT 6,L */ +OP(cb,76) { BIT(6,RM(_HL)); } /* BIT 6,(HL) */ +OP(cb,77) { BIT(6,_A); } /* BIT 6,A */ + +OP(cb,78) { BIT(7,_B); } /* BIT 7,B */ +OP(cb,79) { BIT(7,_C); } /* BIT 7,C */ +OP(cb,7a) { BIT(7,_D); } /* BIT 7,D */ +OP(cb,7b) { BIT(7,_E); } /* BIT 7,E */ +OP(cb,7c) { BIT(7,_H); } /* BIT 7,H */ +OP(cb,7d) { BIT(7,_L); } /* BIT 7,L */ +OP(cb,7e) { BIT(7,RM(_HL)); } /* BIT 7,(HL) */ +OP(cb,7f) { BIT(7,_A); } /* BIT 7,A */ + +OP(cb,80) { _B = RES(0,_B); } /* RES 0,B */ +OP(cb,81) { _C = RES(0,_C); } /* RES 0,C */ +OP(cb,82) { _D = RES(0,_D); } /* RES 0,D */ +OP(cb,83) { _E = RES(0,_E); } /* RES 0,E */ +OP(cb,84) { _H = RES(0,_H); } /* RES 0,H */ +OP(cb,85) { _L = RES(0,_L); } /* RES 0,L */ +OP(cb,86) { WM( _HL, RES(0,RM(_HL)) ); } /* RES 0,(HL) */ +OP(cb,87) { _A = RES(0,_A); } /* RES 0,A */ + +OP(cb,88) { _B = RES(1,_B); } /* RES 1,B */ +OP(cb,89) { _C = RES(1,_C); } /* RES 1,C */ +OP(cb,8a) { _D = RES(1,_D); } /* RES 1,D */ +OP(cb,8b) { _E = RES(1,_E); } /* RES 1,E */ +OP(cb,8c) { _H = RES(1,_H); } /* RES 1,H */ +OP(cb,8d) { _L = RES(1,_L); } /* RES 1,L */ +OP(cb,8e) { WM( _HL, RES(1,RM(_HL)) ); } /* RES 1,(HL) */ +OP(cb,8f) { _A = RES(1,_A); } /* RES 1,A */ + +OP(cb,90) { _B = RES(2,_B); } /* RES 2,B */ +OP(cb,91) { _C = RES(2,_C); } /* RES 2,C */ +OP(cb,92) { _D = RES(2,_D); } /* RES 2,D */ +OP(cb,93) { _E = RES(2,_E); } /* RES 2,E */ +OP(cb,94) { _H = RES(2,_H); } /* RES 2,H */ +OP(cb,95) { _L = RES(2,_L); } /* RES 2,L */ +OP(cb,96) { WM( _HL, RES(2,RM(_HL)) ); } /* RES 2,(HL) */ +OP(cb,97) { _A = RES(2,_A); } /* RES 2,A */ + +OP(cb,98) { _B = RES(3,_B); } /* RES 3,B */ +OP(cb,99) { _C = RES(3,_C); } /* RES 3,C */ +OP(cb,9a) { _D = RES(3,_D); } /* RES 3,D */ +OP(cb,9b) { _E = RES(3,_E); } /* RES 3,E */ +OP(cb,9c) { _H = RES(3,_H); } /* RES 3,H */ +OP(cb,9d) { _L = RES(3,_L); } /* RES 3,L */ +OP(cb,9e) { WM( _HL, RES(3,RM(_HL)) ); } /* RES 3,(HL) */ +OP(cb,9f) { _A = RES(3,_A); } /* RES 3,A */ + +OP(cb,a0) { _B = RES(4,_B); } /* RES 4,B */ +OP(cb,a1) { _C = RES(4,_C); } /* RES 4,C */ +OP(cb,a2) { _D = RES(4,_D); } /* RES 4,D */ +OP(cb,a3) { _E = RES(4,_E); } /* RES 4,E */ +OP(cb,a4) { _H = RES(4,_H); } /* RES 4,H */ +OP(cb,a5) { _L = RES(4,_L); } /* RES 4,L */ +OP(cb,a6) { WM( _HL, RES(4,RM(_HL)) ); } /* RES 4,(HL) */ +OP(cb,a7) { _A = RES(4,_A); } /* RES 4,A */ + +OP(cb,a8) { _B = RES(5,_B); } /* RES 5,B */ +OP(cb,a9) { _C = RES(5,_C); } /* RES 5,C */ +OP(cb,aa) { _D = RES(5,_D); } /* RES 5,D */ +OP(cb,ab) { _E = RES(5,_E); } /* RES 5,E */ +OP(cb,ac) { _H = RES(5,_H); } /* RES 5,H */ +OP(cb,ad) { _L = RES(5,_L); } /* RES 5,L */ +OP(cb,ae) { WM( _HL, RES(5,RM(_HL)) ); } /* RES 5,(HL) */ +OP(cb,af) { _A = RES(5,_A); } /* RES 5,A */ + +OP(cb,b0) { _B = RES(6,_B); } /* RES 6,B */ +OP(cb,b1) { _C = RES(6,_C); } /* RES 6,C */ +OP(cb,b2) { _D = RES(6,_D); } /* RES 6,D */ +OP(cb,b3) { _E = RES(6,_E); } /* RES 6,E */ +OP(cb,b4) { _H = RES(6,_H); } /* RES 6,H */ +OP(cb,b5) { _L = RES(6,_L); } /* RES 6,L */ +OP(cb,b6) { WM( _HL, RES(6,RM(_HL)) ); } /* RES 6,(HL) */ +OP(cb,b7) { _A = RES(6,_A); } /* RES 6,A */ + +OP(cb,b8) { _B = RES(7,_B); } /* RES 7,B */ +OP(cb,b9) { _C = RES(7,_C); } /* RES 7,C */ +OP(cb,ba) { _D = RES(7,_D); } /* RES 7,D */ +OP(cb,bb) { _E = RES(7,_E); } /* RES 7,E */ +OP(cb,bc) { _H = RES(7,_H); } /* RES 7,H */ +OP(cb,bd) { _L = RES(7,_L); } /* RES 7,L */ +OP(cb,be) { WM( _HL, RES(7,RM(_HL)) ); } /* RES 7,(HL) */ +OP(cb,bf) { _A = RES(7,_A); } /* RES 7,A */ + +OP(cb,c0) { _B = SET(0,_B); } /* SET 0,B */ +OP(cb,c1) { _C = SET(0,_C); } /* SET 0,C */ +OP(cb,c2) { _D = SET(0,_D); } /* SET 0,D */ +OP(cb,c3) { _E = SET(0,_E); } /* SET 0,E */ +OP(cb,c4) { _H = SET(0,_H); } /* SET 0,H */ +OP(cb,c5) { _L = SET(0,_L); } /* SET 0,L */ +OP(cb,c6) { WM( _HL, SET(0,RM(_HL)) ); } /* SET 0,(HL) */ +OP(cb,c7) { _A = SET(0,_A); } /* SET 0,A */ + +OP(cb,c8) { _B = SET(1,_B); } /* SET 1,B */ +OP(cb,c9) { _C = SET(1,_C); } /* SET 1,C */ +OP(cb,ca) { _D = SET(1,_D); } /* SET 1,D */ +OP(cb,cb) { _E = SET(1,_E); } /* SET 1,E */ +OP(cb,cc) { _H = SET(1,_H); } /* SET 1,H */ +OP(cb,cd) { _L = SET(1,_L); } /* SET 1,L */ +OP(cb,ce) { WM( _HL, SET(1,RM(_HL)) ); } /* SET 1,(HL) */ +OP(cb,cf) { _A = SET(1,_A); } /* SET 1,A */ + +OP(cb,d0) { _B = SET(2,_B); } /* SET 2,B */ +OP(cb,d1) { _C = SET(2,_C); } /* SET 2,C */ +OP(cb,d2) { _D = SET(2,_D); } /* SET 2,D */ +OP(cb,d3) { _E = SET(2,_E); } /* SET 2,E */ +OP(cb,d4) { _H = SET(2,_H); } /* SET 2,H */ +OP(cb,d5) { _L = SET(2,_L); } /* SET 2,L */ +OP(cb,d6) { WM( _HL, SET(2,RM(_HL)) ); }/* SET 2,(HL) */ +OP(cb,d7) { _A = SET(2,_A); } /* SET 2,A */ + +OP(cb,d8) { _B = SET(3,_B); } /* SET 3,B */ +OP(cb,d9) { _C = SET(3,_C); } /* SET 3,C */ +OP(cb,da) { _D = SET(3,_D); } /* SET 3,D */ +OP(cb,db) { _E = SET(3,_E); } /* SET 3,E */ +OP(cb,dc) { _H = SET(3,_H); } /* SET 3,H */ +OP(cb,dd) { _L = SET(3,_L); } /* SET 3,L */ +OP(cb,de) { WM( _HL, SET(3,RM(_HL)) ); } /* SET 3,(HL) */ +OP(cb,df) { _A = SET(3,_A); } /* SET 3,A */ + +OP(cb,e0) { _B = SET(4,_B); } /* SET 4,B */ +OP(cb,e1) { _C = SET(4,_C); } /* SET 4,C */ +OP(cb,e2) { _D = SET(4,_D); } /* SET 4,D */ +OP(cb,e3) { _E = SET(4,_E); } /* SET 4,E */ +OP(cb,e4) { _H = SET(4,_H); } /* SET 4,H */ +OP(cb,e5) { _L = SET(4,_L); } /* SET 4,L */ +OP(cb,e6) { WM( _HL, SET(4,RM(_HL)) ); } /* SET 4,(HL) */ +OP(cb,e7) { _A = SET(4,_A); } /* SET 4,A */ + +OP(cb,e8) { _B = SET(5,_B); } /* SET 5,B */ +OP(cb,e9) { _C = SET(5,_C); } /* SET 5,C */ +OP(cb,ea) { _D = SET(5,_D); } /* SET 5,D */ +OP(cb,eb) { _E = SET(5,_E); } /* SET 5,E */ +OP(cb,ec) { _H = SET(5,_H); } /* SET 5,H */ +OP(cb,ed) { _L = SET(5,_L); } /* SET 5,L */ +OP(cb,ee) { WM( _HL, SET(5,RM(_HL)) ); } /* SET 5,(HL) */ +OP(cb,ef) { _A = SET(5,_A); } /* SET 5,A */ + +OP(cb,f0) { _B = SET(6,_B); } /* SET 6,B */ +OP(cb,f1) { _C = SET(6,_C); } /* SET 6,C */ +OP(cb,f2) { _D = SET(6,_D); } /* SET 6,D */ +OP(cb,f3) { _E = SET(6,_E); } /* SET 6,E */ +OP(cb,f4) { _H = SET(6,_H); } /* SET 6,H */ +OP(cb,f5) { _L = SET(6,_L); } /* SET 6,L */ +OP(cb,f6) { WM( _HL, SET(6,RM(_HL)) ); } /* SET 6,(HL) */ +OP(cb,f7) { _A = SET(6,_A); } /* SET 6,A */ + +OP(cb,f8) { _B = SET(7,_B); } /* SET 7,B */ +OP(cb,f9) { _C = SET(7,_C); } /* SET 7,C */ +OP(cb,fa) { _D = SET(7,_D); } /* SET 7,D */ +OP(cb,fb) { _E = SET(7,_E); } /* SET 7,E */ +OP(cb,fc) { _H = SET(7,_H); } /* SET 7,H */ +OP(cb,fd) { _L = SET(7,_L); } /* SET 7,L */ +OP(cb,fe) { WM( _HL, SET(7,RM(_HL)) ); } /* SET 7,(HL) */ +OP(cb,ff) { _A = SET(7,_A); } /* SET 7,A */ + + +/********************************************************** +* opcodes with DD/FD CB prefix +* rotate, shift and bit operations with (IX+o) +**********************************************************/ +OP(xycb,00) { _B = RLC( RM(EA) ); WM( EA,_B ); } /* RLC B=(XY+o) */ +OP(xycb,01) { _C = RLC( RM(EA) ); WM( EA,_C ); } /* RLC C=(XY+o) */ +OP(xycb,02) { _D = RLC( RM(EA) ); WM( EA,_D ); } /* RLC D=(XY+o) */ +OP(xycb,03) { _E = RLC( RM(EA) ); WM( EA,_E ); } /* RLC E=(XY+o) */ +OP(xycb,04) { _H = RLC( RM(EA) ); WM( EA,_H ); } /* RLC H=(XY+o) */ +OP(xycb,05) { _L = RLC( RM(EA) ); WM( EA,_L ); } /* RLC L=(XY+o) */ +OP(xycb,06) { WM( EA, RLC( RM(EA) ) ); } /* RLC (XY+o) */ +OP(xycb,07) { _A = RLC( RM(EA) ); WM( EA,_A ); } /* RLC A=(XY+o) */ + +OP(xycb,08) { _B = RRC( RM(EA) ); WM( EA,_B ); } /* RRC B=(XY+o) */ +OP(xycb,09) { _C = RRC( RM(EA) ); WM( EA,_C ); } /* RRC C=(XY+o) */ +OP(xycb,0a) { _D = RRC( RM(EA) ); WM( EA,_D ); } /* RRC D=(XY+o) */ +OP(xycb,0b) { _E = RRC( RM(EA) ); WM( EA,_E ); } /* RRC E=(XY+o) */ +OP(xycb,0c) { _H = RRC( RM(EA) ); WM( EA,_H ); } /* RRC H=(XY+o) */ +OP(xycb,0d) { _L = RRC( RM(EA) ); WM( EA,_L ); } /* RRC L=(XY+o) */ +OP(xycb,0e) { WM( EA,RRC( RM(EA) ) ); } /* RRC (XY+o) */ +OP(xycb,0f) { _A = RRC( RM(EA) ); WM( EA,_A ); } /* RRC A=(XY+o) */ + +OP(xycb,10) { _B = RL( RM(EA) ); WM( EA,_B ); } /* RL B=(XY+o) */ +OP(xycb,11) { _C = RL( RM(EA) ); WM( EA,_C ); } /* RL C=(XY+o) */ +OP(xycb,12) { _D = RL( RM(EA) ); WM( EA,_D ); } /* RL D=(XY+o) */ +OP(xycb,13) { _E = RL( RM(EA) ); WM( EA,_E ); } /* RL E=(XY+o) */ +OP(xycb,14) { _H = RL( RM(EA) ); WM( EA,_H ); } /* RL H=(XY+o) */ +OP(xycb,15) { _L = RL( RM(EA) ); WM( EA,_L ); } /* RL L=(XY+o) */ +OP(xycb,16) { WM( EA,RL( RM(EA) ) ); } /* RL (XY+o) */ +OP(xycb,17) { _A = RL( RM(EA) ); WM( EA,_A ); } /* RL A=(XY+o) */ + +OP(xycb,18) { _B = RR( RM(EA) ); WM( EA,_B ); } /* RR B=(XY+o) */ +OP(xycb,19) { _C = RR( RM(EA) ); WM( EA,_C ); } /* RR C=(XY+o) */ +OP(xycb,1a) { _D = RR( RM(EA) ); WM( EA,_D ); } /* RR D=(XY+o) */ +OP(xycb,1b) { _E = RR( RM(EA) ); WM( EA,_E ); } /* RR E=(XY+o) */ +OP(xycb,1c) { _H = RR( RM(EA) ); WM( EA,_H ); } /* RR H=(XY+o) */ +OP(xycb,1d) { _L = RR( RM(EA) ); WM( EA,_L ); } /* RR L=(XY+o) */ +OP(xycb,1e) { WM( EA,RR( RM(EA) ) ); } /* RR (XY+o) */ +OP(xycb,1f) { _A = RR( RM(EA) ); WM( EA,_A ); } /* RR A=(XY+o) */ + +OP(xycb,20) { _B = SLA( RM(EA) ); WM( EA,_B ); } /* SLA B=(XY+o) */ +OP(xycb,21) { _C = SLA( RM(EA) ); WM( EA,_C ); } /* SLA C=(XY+o) */ +OP(xycb,22) { _D = SLA( RM(EA) ); WM( EA,_D ); } /* SLA D=(XY+o) */ +OP(xycb,23) { _E = SLA( RM(EA) ); WM( EA,_E ); } /* SLA E=(XY+o) */ +OP(xycb,24) { _H = SLA( RM(EA) ); WM( EA,_H ); } /* SLA H=(XY+o) */ +OP(xycb,25) { _L = SLA( RM(EA) ); WM( EA,_L ); } /* SLA L=(XY+o) */ +OP(xycb,26) { WM( EA,SLA( RM(EA) ) ); } /* SLA (XY+o) */ +OP(xycb,27) { _A = SLA( RM(EA) ); WM( EA,_A ); } /* SLA A=(XY+o) */ + +OP(xycb,28) { _B = SRA( RM(EA) ); WM( EA,_B ); } /* SRA B=(XY+o) */ +OP(xycb,29) { _C = SRA( RM(EA) ); WM( EA,_C ); } /* SRA C=(XY+o) */ +OP(xycb,2a) { _D = SRA( RM(EA) ); WM( EA,_D ); } /* SRA D=(XY+o) */ +OP(xycb,2b) { _E = SRA( RM(EA) ); WM( EA,_E ); } /* SRA E=(XY+o) */ +OP(xycb,2c) { _H = SRA( RM(EA) ); WM( EA,_H ); } /* SRA H=(XY+o) */ +OP(xycb,2d) { _L = SRA( RM(EA) ); WM( EA,_L ); } /* SRA L=(XY+o) */ +OP(xycb,2e) { WM( EA,SRA( RM(EA) ) ); } /* SRA (XY+o) */ +OP(xycb,2f) { _A = SRA( RM(EA) ); WM( EA,_A ); } /* SRA A=(XY+o) */ + +OP(xycb,30) { _B = SLL( RM(EA) ); WM( EA,_B ); } /* SLL B=(XY+o) */ +OP(xycb,31) { _C = SLL( RM(EA) ); WM( EA,_C ); } /* SLL C=(XY+o) */ +OP(xycb,32) { _D = SLL( RM(EA) ); WM( EA,_D ); } /* SLL D=(XY+o) */ +OP(xycb,33) { _E = SLL( RM(EA) ); WM( EA,_E ); } /* SLL E=(XY+o) */ +OP(xycb,34) { _H = SLL( RM(EA) ); WM( EA,_H ); } /* SLL H=(XY+o) */ +OP(xycb,35) { _L = SLL( RM(EA) ); WM( EA,_L ); } /* SLL L=(XY+o) */ +OP(xycb,36) { WM( EA,SLL( RM(EA) ) ); } /* SLL (XY+o) */ +OP(xycb,37) { _A = SLL( RM(EA) ); WM( EA,_A ); } /* SLL A=(XY+o) */ + +OP(xycb,38) { _B = SRL( RM(EA) ); WM( EA,_B ); } /* SRL B=(XY+o) */ +OP(xycb,39) { _C = SRL( RM(EA) ); WM( EA,_C ); } /* SRL C=(XY+o) */ +OP(xycb,3a) { _D = SRL( RM(EA) ); WM( EA,_D ); } /* SRL D=(XY+o) */ +OP(xycb,3b) { _E = SRL( RM(EA) ); WM( EA,_E ); } /* SRL E=(XY+o) */ +OP(xycb,3c) { _H = SRL( RM(EA) ); WM( EA,_H ); } /* SRL H=(XY+o) */ +OP(xycb,3d) { _L = SRL( RM(EA) ); WM( EA,_L ); } /* SRL L=(XY+o) */ +OP(xycb,3e) { WM( EA,SRL( RM(EA) ) ); } /* SRL (XY+o) */ +OP(xycb,3f) { _A = SRL( RM(EA) ); WM( EA,_A ); } /* SRL A=(XY+o) */ + +OP(xycb,40) { xycb_46(); } /* BIT 0,B=(XY+o) */ +OP(xycb,41) { xycb_46(); } /* BIT 0,C=(XY+o) */ +OP(xycb,42) { xycb_46(); } /* BIT 0,D=(XY+o) */ +OP(xycb,43) { xycb_46(); } /* BIT 0,E=(XY+o) */ +OP(xycb,44) { xycb_46(); } /* BIT 0,H=(XY+o) */ +OP(xycb,45) { xycb_46(); } /* BIT 0,L=(XY+o) */ +OP(xycb,46) { BIT_XY(0,RM(EA)); } /* BIT 0,(XY+o) */ +OP(xycb,47) { xycb_46(); } /* BIT 0,A=(XY+o) */ + +OP(xycb,48) { xycb_4e(); } /* BIT 1,B=(XY+o) */ +OP(xycb,49) { xycb_4e(); } /* BIT 1,C=(XY+o) */ +OP(xycb,4a) { xycb_4e(); } /* BIT 1,D=(XY+o) */ +OP(xycb,4b) { xycb_4e(); } /* BIT 1,E=(XY+o) */ +OP(xycb,4c) { xycb_4e(); } /* BIT 1,H=(XY+o) */ +OP(xycb,4d) { xycb_4e(); } /* BIT 1,L=(XY+o) */ +OP(xycb,4e) { BIT_XY(1,RM(EA)); } /* BIT 1,(XY+o) */ +OP(xycb,4f) { xycb_4e(); } /* BIT 1,A=(XY+o) */ + +OP(xycb,50) { xycb_56(); } /* BIT 2,B=(XY+o) */ +OP(xycb,51) { xycb_56(); } /* BIT 2,C=(XY+o) */ +OP(xycb,52) { xycb_56(); } /* BIT 2,D=(XY+o) */ +OP(xycb,53) { xycb_56(); } /* BIT 2,E=(XY+o) */ +OP(xycb,54) { xycb_56(); } /* BIT 2,H=(XY+o) */ +OP(xycb,55) { xycb_56(); } /* BIT 2,L=(XY+o) */ +OP(xycb,56) { BIT_XY(2,RM(EA)); } /* BIT 2,(XY+o) */ +OP(xycb,57) { xycb_56(); } /* BIT 2,A=(XY+o) */ + +OP(xycb,58) { xycb_5e(); } /* BIT 3,B=(XY+o) */ +OP(xycb,59) { xycb_5e(); } /* BIT 3,C=(XY+o) */ +OP(xycb,5a) { xycb_5e(); } /* BIT 3,D=(XY+o) */ +OP(xycb,5b) { xycb_5e(); } /* BIT 3,E=(XY+o) */ +OP(xycb,5c) { xycb_5e(); } /* BIT 3,H=(XY+o) */ +OP(xycb,5d) { xycb_5e(); } /* BIT 3,L=(XY+o) */ +OP(xycb,5e) { BIT_XY(3,RM(EA)); } /* BIT 3,(XY+o) */ +OP(xycb,5f) { xycb_5e(); } /* BIT 3,A=(XY+o) */ + +OP(xycb,60) { xycb_66(); } /* BIT 4,B=(XY+o) */ +OP(xycb,61) { xycb_66(); } /* BIT 4,C=(XY+o) */ +OP(xycb,62) { xycb_66(); } /* BIT 4,D=(XY+o) */ +OP(xycb,63) { xycb_66(); } /* BIT 4,E=(XY+o) */ +OP(xycb,64) { xycb_66(); } /* BIT 4,H=(XY+o) */ +OP(xycb,65) { xycb_66(); } /* BIT 4,L=(XY+o) */ +OP(xycb,66) { BIT_XY(4,RM(EA)); } /* BIT 4,(XY+o) */ +OP(xycb,67) { xycb_66(); } /* BIT 4,A=(XY+o) */ + +OP(xycb,68) { xycb_6e(); } /* BIT 5,B=(XY+o) */ +OP(xycb,69) { xycb_6e(); } /* BIT 5,C=(XY+o) */ +OP(xycb,6a) { xycb_6e(); } /* BIT 5,D=(XY+o) */ +OP(xycb,6b) { xycb_6e(); } /* BIT 5,E=(XY+o) */ +OP(xycb,6c) { xycb_6e(); } /* BIT 5,H=(XY+o) */ +OP(xycb,6d) { xycb_6e(); } /* BIT 5,L=(XY+o) */ +OP(xycb,6e) { BIT_XY(5,RM(EA)); } /* BIT 5,(XY+o) */ +OP(xycb,6f) { xycb_6e(); } /* BIT 5,A=(XY+o) */ + +OP(xycb,70) { xycb_76(); } /* BIT 6,B=(XY+o) */ +OP(xycb,71) { xycb_76(); } /* BIT 6,C=(XY+o) */ +OP(xycb,72) { xycb_76(); } /* BIT 6,D=(XY+o) */ +OP(xycb,73) { xycb_76(); } /* BIT 6,E=(XY+o) */ +OP(xycb,74) { xycb_76(); } /* BIT 6,H=(XY+o) */ +OP(xycb,75) { xycb_76(); } /* BIT 6,L=(XY+o) */ +OP(xycb,76) { BIT_XY(6,RM(EA)); } /* BIT 6,(XY+o) */ +OP(xycb,77) { xycb_76(); } /* BIT 6,A=(XY+o) */ + +OP(xycb,78) { xycb_7e(); } /* BIT 7,B=(XY+o) */ +OP(xycb,79) { xycb_7e(); } /* BIT 7,C=(XY+o) */ +OP(xycb,7a) { xycb_7e(); } /* BIT 7,D=(XY+o) */ +OP(xycb,7b) { xycb_7e(); } /* BIT 7,E=(XY+o) */ +OP(xycb,7c) { xycb_7e(); } /* BIT 7,H=(XY+o) */ +OP(xycb,7d) { xycb_7e(); } /* BIT 7,L=(XY+o) */ +OP(xycb,7e) { BIT_XY(7,RM(EA)); } /* BIT 7,(XY+o) */ +OP(xycb,7f) { xycb_7e(); } /* BIT 7,A=(XY+o) */ + +OP(xycb,80) { _B = RES(0, RM(EA) ); WM( EA,_B ); } /* RES 0,B=(XY+o) */ +OP(xycb,81) { _C = RES(0, RM(EA) ); WM( EA,_C ); } /* RES 0,C=(XY+o) */ +OP(xycb,82) { _D = RES(0, RM(EA) ); WM( EA,_D ); } /* RES 0,D=(XY+o) */ +OP(xycb,83) { _E = RES(0, RM(EA) ); WM( EA,_E ); } /* RES 0,E=(XY+o) */ +OP(xycb,84) { _H = RES(0, RM(EA) ); WM( EA,_H ); } /* RES 0,H=(XY+o) */ +OP(xycb,85) { _L = RES(0, RM(EA) ); WM( EA,_L ); } /* RES 0,L=(XY+o) */ +OP(xycb,86) { WM( EA, RES(0,RM(EA)) ); } /* RES 0,(XY+o) */ +OP(xycb,87) { _A = RES(0, RM(EA) ); WM( EA,_A ); } /* RES 0,A=(XY+o) */ + +OP(xycb,88) { _B = RES(1, RM(EA) ); WM( EA,_B ); } /* RES 1,B=(XY+o) */ +OP(xycb,89) { _C = RES(1, RM(EA) ); WM( EA,_C ); } /* RES 1,C=(XY+o) */ +OP(xycb,8a) { _D = RES(1, RM(EA) ); WM( EA,_D ); } /* RES 1,D=(XY+o) */ +OP(xycb,8b) { _E = RES(1, RM(EA) ); WM( EA,_E ); } /* RES 1,E=(XY+o) */ +OP(xycb,8c) { _H = RES(1, RM(EA) ); WM( EA,_H ); } /* RES 1,H=(XY+o) */ +OP(xycb,8d) { _L = RES(1, RM(EA) ); WM( EA,_L ); } /* RES 1,L=(XY+o) */ +OP(xycb,8e) { WM( EA, RES(1,RM(EA)) ); } /* RES 1,(XY+o) */ +OP(xycb,8f) { _A = RES(1, RM(EA) ); WM( EA,_A ); } /* RES 1,A=(XY+o) */ + +OP(xycb,90) { _B = RES(2, RM(EA) ); WM( EA,_B ); } /* RES 2,B=(XY+o) */ +OP(xycb,91) { _C = RES(2, RM(EA) ); WM( EA,_C ); } /* RES 2,C=(XY+o) */ +OP(xycb,92) { _D = RES(2, RM(EA) ); WM( EA,_D ); } /* RES 2,D=(XY+o) */ +OP(xycb,93) { _E = RES(2, RM(EA) ); WM( EA,_E ); } /* RES 2,E=(XY+o) */ +OP(xycb,94) { _H = RES(2, RM(EA) ); WM( EA,_H ); } /* RES 2,H=(XY+o) */ +OP(xycb,95) { _L = RES(2, RM(EA) ); WM( EA,_L ); } /* RES 2,L=(XY+o) */ +OP(xycb,96) { WM( EA, RES(2,RM(EA)) ); } /* RES 2,(XY+o) */ +OP(xycb,97) { _A = RES(2, RM(EA) ); WM( EA,_A ); } /* RES 2,A=(XY+o) */ + +OP(xycb,98) { _B = RES(3, RM(EA) ); WM( EA,_B ); } /* RES 3,B=(XY+o) */ +OP(xycb,99) { _C = RES(3, RM(EA) ); WM( EA,_C ); } /* RES 3,C=(XY+o) */ +OP(xycb,9a) { _D = RES(3, RM(EA) ); WM( EA,_D ); } /* RES 3,D=(XY+o) */ +OP(xycb,9b) { _E = RES(3, RM(EA) ); WM( EA,_E ); } /* RES 3,E=(XY+o) */ +OP(xycb,9c) { _H = RES(3, RM(EA) ); WM( EA,_H ); } /* RES 3,H=(XY+o) */ +OP(xycb,9d) { _L = RES(3, RM(EA) ); WM( EA,_L ); } /* RES 3,L=(XY+o) */ +OP(xycb,9e) { WM( EA, RES(3,RM(EA)) ); } /* RES 3,(XY+o) */ +OP(xycb,9f) { _A = RES(3, RM(EA) ); WM( EA,_A ); } /* RES 3,A=(XY+o) */ + +OP(xycb,a0) { _B = RES(4, RM(EA) ); WM( EA,_B ); } /* RES 4,B=(XY+o) */ +OP(xycb,a1) { _C = RES(4, RM(EA) ); WM( EA,_C ); } /* RES 4,C=(XY+o) */ +OP(xycb,a2) { _D = RES(4, RM(EA) ); WM( EA,_D ); } /* RES 4,D=(XY+o) */ +OP(xycb,a3) { _E = RES(4, RM(EA) ); WM( EA,_E ); } /* RES 4,E=(XY+o) */ +OP(xycb,a4) { _H = RES(4, RM(EA) ); WM( EA,_H ); } /* RES 4,H=(XY+o) */ +OP(xycb,a5) { _L = RES(4, RM(EA) ); WM( EA,_L ); } /* RES 4,L=(XY+o) */ +OP(xycb,a6) { WM( EA, RES(4,RM(EA)) ); } /* RES 4,(XY+o) */ +OP(xycb,a7) { _A = RES(4, RM(EA) ); WM( EA,_A ); } /* RES 4,A=(XY+o) */ + +OP(xycb,a8) { _B = RES(5, RM(EA) ); WM( EA,_B ); } /* RES 5,B=(XY+o) */ +OP(xycb,a9) { _C = RES(5, RM(EA) ); WM( EA,_C ); } /* RES 5,C=(XY+o) */ +OP(xycb,aa) { _D = RES(5, RM(EA) ); WM( EA,_D ); } /* RES 5,D=(XY+o) */ +OP(xycb,ab) { _E = RES(5, RM(EA) ); WM( EA,_E ); } /* RES 5,E=(XY+o) */ +OP(xycb,ac) { _H = RES(5, RM(EA) ); WM( EA,_H ); } /* RES 5,H=(XY+o) */ +OP(xycb,ad) { _L = RES(5, RM(EA) ); WM( EA,_L ); } /* RES 5,L=(XY+o) */ +OP(xycb,ae) { WM( EA, RES(5,RM(EA)) ); } /* RES 5,(XY+o) */ +OP(xycb,af) { _A = RES(5, RM(EA) ); WM( EA,_A ); } /* RES 5,A=(XY+o) */ + +OP(xycb,b0) { _B = RES(6, RM(EA) ); WM( EA,_B ); } /* RES 6,B=(XY+o) */ +OP(xycb,b1) { _C = RES(6, RM(EA) ); WM( EA,_C ); } /* RES 6,C=(XY+o) */ +OP(xycb,b2) { _D = RES(6, RM(EA) ); WM( EA,_D ); } /* RES 6,D=(XY+o) */ +OP(xycb,b3) { _E = RES(6, RM(EA) ); WM( EA,_E ); } /* RES 6,E=(XY+o) */ +OP(xycb,b4) { _H = RES(6, RM(EA) ); WM( EA,_H ); } /* RES 6,H=(XY+o) */ +OP(xycb,b5) { _L = RES(6, RM(EA) ); WM( EA,_L ); } /* RES 6,L=(XY+o) */ +OP(xycb,b6) { WM( EA, RES(6,RM(EA)) ); } /* RES 6,(XY+o) */ +OP(xycb,b7) { _A = RES(6, RM(EA) ); WM( EA,_A ); } /* RES 6,A=(XY+o) */ + +OP(xycb,b8) { _B = RES(7, RM(EA) ); WM( EA,_B ); } /* RES 7,B=(XY+o) */ +OP(xycb,b9) { _C = RES(7, RM(EA) ); WM( EA,_C ); } /* RES 7,C=(XY+o) */ +OP(xycb,ba) { _D = RES(7, RM(EA) ); WM( EA,_D ); } /* RES 7,D=(XY+o) */ +OP(xycb,bb) { _E = RES(7, RM(EA) ); WM( EA,_E ); } /* RES 7,E=(XY+o) */ +OP(xycb,bc) { _H = RES(7, RM(EA) ); WM( EA,_H ); } /* RES 7,H=(XY+o) */ +OP(xycb,bd) { _L = RES(7, RM(EA) ); WM( EA,_L ); } /* RES 7,L=(XY+o) */ +OP(xycb,be) { WM( EA, RES(7,RM(EA)) ); } /* RES 7,(XY+o) */ +OP(xycb,bf) { _A = RES(7, RM(EA) ); WM( EA,_A ); } /* RES 7,A=(XY+o) */ + +OP(xycb,c0) { _B = SET(0, RM(EA) ); WM( EA,_B ); } /* SET 0,B=(XY+o) */ +OP(xycb,c1) { _C = SET(0, RM(EA) ); WM( EA,_C ); } /* SET 0,C=(XY+o) */ +OP(xycb,c2) { _D = SET(0, RM(EA) ); WM( EA,_D ); } /* SET 0,D=(XY+o) */ +OP(xycb,c3) { _E = SET(0, RM(EA) ); WM( EA,_E ); } /* SET 0,E=(XY+o) */ +OP(xycb,c4) { _H = SET(0, RM(EA) ); WM( EA,_H ); } /* SET 0,H=(XY+o) */ +OP(xycb,c5) { _L = SET(0, RM(EA) ); WM( EA,_L ); } /* SET 0,L=(XY+o) */ +OP(xycb,c6) { WM( EA, SET(0,RM(EA)) ); } /* SET 0,(XY+o) */ +OP(xycb,c7) { _A = SET(0, RM(EA) ); WM( EA,_A ); } /* SET 0,A=(XY+o) */ + +OP(xycb,c8) { _B = SET(1, RM(EA) ); WM( EA,_B ); } /* SET 1,B=(XY+o) */ +OP(xycb,c9) { _C = SET(1, RM(EA) ); WM( EA,_C ); } /* SET 1,C=(XY+o) */ +OP(xycb,ca) { _D = SET(1, RM(EA) ); WM( EA,_D ); } /* SET 1,D=(XY+o) */ +OP(xycb,cb) { _E = SET(1, RM(EA) ); WM( EA,_E ); } /* SET 1,E=(XY+o) */ +OP(xycb,cc) { _H = SET(1, RM(EA) ); WM( EA,_H ); } /* SET 1,H=(XY+o) */ +OP(xycb,cd) { _L = SET(1, RM(EA) ); WM( EA,_L ); } /* SET 1,L=(XY+o) */ +OP(xycb,ce) { WM( EA, SET(1,RM(EA)) ); } /* SET 1,(XY+o) */ +OP(xycb,cf) { _A = SET(1, RM(EA) ); WM( EA,_A ); } /* SET 1,A=(XY+o) */ + +OP(xycb,d0) { _B = SET(2, RM(EA) ); WM( EA,_B ); } /* SET 2,B=(XY+o) */ +OP(xycb,d1) { _C = SET(2, RM(EA) ); WM( EA,_C ); } /* SET 2,C=(XY+o) */ +OP(xycb,d2) { _D = SET(2, RM(EA) ); WM( EA,_D ); } /* SET 2,D=(XY+o) */ +OP(xycb,d3) { _E = SET(2, RM(EA) ); WM( EA,_E ); } /* SET 2,E=(XY+o) */ +OP(xycb,d4) { _H = SET(2, RM(EA) ); WM( EA,_H ); } /* SET 2,H=(XY+o) */ +OP(xycb,d5) { _L = SET(2, RM(EA) ); WM( EA,_L ); } /* SET 2,L=(XY+o) */ +OP(xycb,d6) { WM( EA, SET(2,RM(EA)) ); } /* SET 2,(XY+o) */ +OP(xycb,d7) { _A = SET(2, RM(EA) ); WM( EA,_A ); } /* SET 2,A=(XY+o) */ + +OP(xycb,d8) { _B = SET(3, RM(EA) ); WM( EA,_B ); } /* SET 3,B=(XY+o) */ +OP(xycb,d9) { _C = SET(3, RM(EA) ); WM( EA,_C ); } /* SET 3,C=(XY+o) */ +OP(xycb,da) { _D = SET(3, RM(EA) ); WM( EA,_D ); } /* SET 3,D=(XY+o) */ +OP(xycb,db) { _E = SET(3, RM(EA) ); WM( EA,_E ); } /* SET 3,E=(XY+o) */ +OP(xycb,dc) { _H = SET(3, RM(EA) ); WM( EA,_H ); } /* SET 3,H=(XY+o) */ +OP(xycb,dd) { _L = SET(3, RM(EA) ); WM( EA,_L ); } /* SET 3,L=(XY+o) */ +OP(xycb,de) { WM( EA, SET(3,RM(EA)) ); } /* SET 3,(XY+o) */ +OP(xycb,df) { _A = SET(3, RM(EA) ); WM( EA,_A ); } /* SET 3,A=(XY+o) */ + +OP(xycb,e0) { _B = SET(4, RM(EA) ); WM( EA,_B ); } /* SET 4,B=(XY+o) */ +OP(xycb,e1) { _C = SET(4, RM(EA) ); WM( EA,_C ); } /* SET 4,C=(XY+o) */ +OP(xycb,e2) { _D = SET(4, RM(EA) ); WM( EA,_D ); } /* SET 4,D=(XY+o) */ +OP(xycb,e3) { _E = SET(4, RM(EA) ); WM( EA,_E ); } /* SET 4,E=(XY+o) */ +OP(xycb,e4) { _H = SET(4, RM(EA) ); WM( EA,_H ); } /* SET 4,H=(XY+o) */ +OP(xycb,e5) { _L = SET(4, RM(EA) ); WM( EA,_L ); } /* SET 4,L=(XY+o) */ +OP(xycb,e6) { WM( EA, SET(4,RM(EA)) ); } /* SET 4,(XY+o) */ +OP(xycb,e7) { _A = SET(4, RM(EA) ); WM( EA,_A ); } /* SET 4,A=(XY+o) */ + +OP(xycb,e8) { _B = SET(5, RM(EA) ); WM( EA,_B ); } /* SET 5,B=(XY+o) */ +OP(xycb,e9) { _C = SET(5, RM(EA) ); WM( EA,_C ); } /* SET 5,C=(XY+o) */ +OP(xycb,ea) { _D = SET(5, RM(EA) ); WM( EA,_D ); } /* SET 5,D=(XY+o) */ +OP(xycb,eb) { _E = SET(5, RM(EA) ); WM( EA,_E ); } /* SET 5,E=(XY+o) */ +OP(xycb,ec) { _H = SET(5, RM(EA) ); WM( EA,_H ); } /* SET 5,H=(XY+o) */ +OP(xycb,ed) { _L = SET(5, RM(EA) ); WM( EA,_L ); } /* SET 5,L=(XY+o) */ +OP(xycb,ee) { WM( EA, SET(5,RM(EA)) ); } /* SET 5,(XY+o) */ +OP(xycb,ef) { _A = SET(5, RM(EA) ); WM( EA,_A ); } /* SET 5,A=(XY+o) */ + +OP(xycb,f0) { _B = SET(6, RM(EA) ); WM( EA,_B ); } /* SET 6,B=(XY+o) */ +OP(xycb,f1) { _C = SET(6, RM(EA) ); WM( EA,_C ); } /* SET 6,C=(XY+o) */ +OP(xycb,f2) { _D = SET(6, RM(EA) ); WM( EA,_D ); } /* SET 6,D=(XY+o) */ +OP(xycb,f3) { _E = SET(6, RM(EA) ); WM( EA,_E ); } /* SET 6,E=(XY+o) */ +OP(xycb,f4) { _H = SET(6, RM(EA) ); WM( EA,_H ); } /* SET 6,H=(XY+o) */ +OP(xycb,f5) { _L = SET(6, RM(EA) ); WM( EA,_L ); } /* SET 6,L=(XY+o) */ +OP(xycb,f6) { WM( EA, SET(6,RM(EA)) ); } /* SET 6,(XY+o) */ +OP(xycb,f7) { _A = SET(6, RM(EA) ); WM( EA,_A ); } /* SET 6,A=(XY+o) */ + +OP(xycb,f8) { _B = SET(7, RM(EA) ); WM( EA,_B ); } /* SET 7,B=(XY+o) */ +OP(xycb,f9) { _C = SET(7, RM(EA) ); WM( EA,_C ); } /* SET 7,C=(XY+o) */ +OP(xycb,fa) { _D = SET(7, RM(EA) ); WM( EA,_D ); } /* SET 7,D=(XY+o) */ +OP(xycb,fb) { _E = SET(7, RM(EA) ); WM( EA,_E ); } /* SET 7,E=(XY+o) */ +OP(xycb,fc) { _H = SET(7, RM(EA) ); WM( EA,_H ); } /* SET 7,H=(XY+o) */ +OP(xycb,fd) { _L = SET(7, RM(EA) ); WM( EA,_L ); } /* SET 7,L=(XY+o) */ +OP(xycb,fe) { WM( EA, SET(7,RM(EA)) ); } /* SET 7,(XY+o) */ +OP(xycb,ff) { _A = SET(7, RM(EA) ); WM( EA,_A ); } /* SET 7,A=(XY+o) */ + +OP(illegal,1) { +} + +/********************************************************** + * IX register related opcodes (DD prefix) + **********************************************************/ +OP(dd,00) { illegal_1(); op_00(); } /* DB DD */ +OP(dd,01) { illegal_1(); op_01(); } /* DB DD */ +OP(dd,02) { illegal_1(); op_02(); } /* DB DD */ +OP(dd,03) { illegal_1(); op_03(); } /* DB DD */ +OP(dd,04) { illegal_1(); op_04(); } /* DB DD */ +OP(dd,05) { illegal_1(); op_05(); } /* DB DD */ +OP(dd,06) { illegal_1(); op_06(); } /* DB DD */ +OP(dd,07) { illegal_1(); op_07(); } /* DB DD */ + +OP(dd,08) { illegal_1(); op_08(); } /* DB DD */ +OP(dd,09) { _R++; ADD16(IX,BC); } /* ADD IX,BC */ +OP(dd,0a) { illegal_1(); op_0a(); } /* DB DD */ +OP(dd,0b) { illegal_1(); op_0b(); } /* DB DD */ +OP(dd,0c) { illegal_1(); op_0c(); } /* DB DD */ +OP(dd,0d) { illegal_1(); op_0d(); } /* DB DD */ +OP(dd,0e) { illegal_1(); op_0e(); } /* DB DD */ +OP(dd,0f) { illegal_1(); op_0f(); } /* DB DD */ + +OP(dd,10) { illegal_1(); op_10(); } /* DB DD */ +OP(dd,11) { illegal_1(); op_11(); } /* DB DD */ +OP(dd,12) { illegal_1(); op_12(); } /* DB DD */ +OP(dd,13) { illegal_1(); op_13(); } /* DB DD */ +OP(dd,14) { illegal_1(); op_14(); } /* DB DD */ +OP(dd,15) { illegal_1(); op_15(); } /* DB DD */ +OP(dd,16) { illegal_1(); op_16(); } /* DB DD */ +OP(dd,17) { illegal_1(); op_17(); } /* DB DD */ + +OP(dd,18) { illegal_1(); op_18(); } /* DB DD */ +OP(dd,19) { _R++; ADD16(IX,DE); } /* ADD IX,DE */ +OP(dd,1a) { illegal_1(); op_1a(); } /* DB DD */ +OP(dd,1b) { illegal_1(); op_1b(); } /* DB DD */ +OP(dd,1c) { illegal_1(); op_1c(); } /* DB DD */ +OP(dd,1d) { illegal_1(); op_1d(); } /* DB DD */ +OP(dd,1e) { illegal_1(); op_1e(); } /* DB DD */ +OP(dd,1f) { illegal_1(); op_1f(); } /* DB DD */ + +OP(dd,20) { illegal_1(); op_20(); } /* DB DD */ +OP(dd,21) { _R++; _IX = ARG16(); } /* LD IX,w */ +OP(dd,22) { _R++; EA = ARG16(); WM16( EA, &Z80.IX ); } /* LD (w),IX */ +OP(dd,23) { _R++; _IX++; } /* INC IX */ +OP(dd,24) { _R++; _HX = INC(_HX); } /* INC HX */ +OP(dd,25) { _R++; _HX = DEC(_HX); } /* DEC HX */ +OP(dd,26) { _R++; _HX = ARG(); } /* LD HX,n */ +OP(dd,27) { illegal_1(); op_27(); } /* DB DD */ + +OP(dd,28) { illegal_1(); op_28(); } /* DB DD */ +OP(dd,29) { _R++; ADD16(IX,IX); } /* ADD IX,IX */ +OP(dd,2a) { _R++; EA = ARG16(); RM16( EA, &Z80.IX ); } /* LD IX,(w) */ +OP(dd,2b) { _R++; _IX--; } /* DEC IX */ +OP(dd,2c) { _R++; _LX = INC(_LX); } /* INC LX */ +OP(dd,2d) { _R++; _LX = DEC(_LX); } /* DEC LX */ +OP(dd,2e) { _R++; _LX = ARG(); } /* LD LX,n */ +OP(dd,2f) { illegal_1(); op_2f(); } /* DB DD */ + +OP(dd,30) { illegal_1(); op_30(); } /* DB DD */ +OP(dd,31) { illegal_1(); op_31(); } /* DB DD */ +OP(dd,32) { illegal_1(); op_32(); } /* DB DD */ +OP(dd,33) { illegal_1(); op_33(); } /* DB DD */ +OP(dd,34) { _R++; EAX; WM( EA, INC(RM(EA)) ); } /* INC (IX+o) */ +OP(dd,35) { _R++; EAX; WM( EA, DEC(RM(EA)) ); } /* DEC (IX+o) */ +OP(dd,36) { _R++; EAX; WM( EA, ARG() ); } /* LD (IX+o),n */ +OP(dd,37) { illegal_1(); op_37(); } /* DB DD */ + +OP(dd,38) { illegal_1(); op_38(); } /* DB DD */ +OP(dd,39) { _R++; ADD16(IX,SP); } /* ADD IX,SP */ +OP(dd,3a) { illegal_1(); op_3a(); } /* DB DD */ +OP(dd,3b) { illegal_1(); op_3b(); } /* DB DD */ +OP(dd,3c) { illegal_1(); op_3c(); } /* DB DD */ +OP(dd,3d) { illegal_1(); op_3d(); } /* DB DD */ +OP(dd,3e) { illegal_1(); op_3e(); } /* DB DD */ +OP(dd,3f) { illegal_1(); op_3f(); } /* DB DD */ + +OP(dd,40) { illegal_1(); op_40(); } /* DB DD */ +OP(dd,41) { illegal_1(); op_41(); } /* DB DD */ +OP(dd,42) { illegal_1(); op_42(); } /* DB DD */ +OP(dd,43) { illegal_1(); op_43(); } /* DB DD */ +OP(dd,44) { _R++; _B = _HX; } /* LD B,HX */ +OP(dd,45) { _R++; _B = _LX; } /* LD B,LX */ +OP(dd,46) { _R++; EAX; _B = RM(EA); } /* LD B,(IX+o) */ +OP(dd,47) { illegal_1(); op_47(); } /* DB DD */ + +OP(dd,48) { illegal_1(); op_48(); } /* DB DD */ +OP(dd,49) { illegal_1(); op_49(); } /* DB DD */ +OP(dd,4a) { illegal_1(); op_4a(); } /* DB DD */ +OP(dd,4b) { illegal_1(); op_4b(); } /* DB DD */ +OP(dd,4c) { _R++; _C = _HX; } /* LD C,HX */ +OP(dd,4d) { _R++; _C = _LX; } /* LD C,LX */ +OP(dd,4e) { _R++; EAX; _C = RM(EA); } /* LD C,(IX+o) */ +OP(dd,4f) { illegal_1(); op_4f(); } /* DB DD */ + +OP(dd,50) { illegal_1(); op_50(); } /* DB DD */ +OP(dd,51) { illegal_1(); op_51(); } /* DB DD */ +OP(dd,52) { illegal_1(); op_52(); } /* DB DD */ +OP(dd,53) { illegal_1(); op_53(); } /* DB DD */ +OP(dd,54) { _R++; _D = _HX; } /* LD D,HX */ +OP(dd,55) { _R++; _D = _LX; } /* LD D,LX */ +OP(dd,56) { _R++; EAX; _D = RM(EA); } /* LD D,(IX+o) */ +OP(dd,57) { illegal_1(); op_57(); } /* DB DD */ + +OP(dd,58) { illegal_1(); op_58(); } /* DB DD */ +OP(dd,59) { illegal_1(); op_59(); } /* DB DD */ +OP(dd,5a) { illegal_1(); op_5a(); } /* DB DD */ +OP(dd,5b) { illegal_1(); op_5b(); } /* DB DD */ +OP(dd,5c) { _R++; _E = _HX; } /* LD E,HX */ +OP(dd,5d) { _R++; _E = _LX; } /* LD E,LX */ +OP(dd,5e) { _R++; EAX; _E = RM(EA); } /* LD E,(IX+o) */ +OP(dd,5f) { illegal_1(); op_5f(); } /* DB DD */ + +OP(dd,60) { _R++; _HX = _B; } /* LD HX,B */ +OP(dd,61) { _R++; _HX = _C; } /* LD HX,C */ +OP(dd,62) { _R++; _HX = _D; } /* LD HX,D */ +OP(dd,63) { _R++; _HX = _E; } /* LD HX,E */ +OP(dd,64) { } /* LD HX,HX */ +OP(dd,65) { _R++; _HX = _LX; } /* LD HX,LX */ +OP(dd,66) { _R++; EAX; _H = RM(EA); } /* LD H,(IX+o) */ +OP(dd,67) { _R++; _HX = _A; } /* LD HX,A */ + +OP(dd,68) { _R++; _LX = _B; } /* LD LX,B */ +OP(dd,69) { _R++; _LX = _C; } /* LD LX,C */ +OP(dd,6a) { _R++; _LX = _D; } /* LD LX,D */ +OP(dd,6b) { _R++; _LX = _E; } /* LD LX,E */ +OP(dd,6c) { _R++; _LX = _HX; } /* LD LX,HX */ +OP(dd,6d) { } /* LD LX,LX */ +OP(dd,6e) { _R++; EAX; _L = RM(EA); } /* LD L,(IX+o) */ +OP(dd,6f) { _R++; _LX = _A; } /* LD LX,A */ + +OP(dd,70) { _R++; EAX; WM( EA, _B ); } /* LD (IX+o),B */ +OP(dd,71) { _R++; EAX; WM( EA, _C ); } /* LD (IX+o),C */ +OP(dd,72) { _R++; EAX; WM( EA, _D ); } /* LD (IX+o),D */ +OP(dd,73) { _R++; EAX; WM( EA, _E ); } /* LD (IX+o),E */ +OP(dd,74) { _R++; EAX; WM( EA, _H ); } /* LD (IX+o),H */ +OP(dd,75) { _R++; EAX; WM( EA, _L ); } /* LD (IX+o),L */ +OP(dd,76) { illegal_1(); op_76(); } /* DB DD */ +OP(dd,77) { _R++; EAX; WM( EA, _A ); } /* LD (IX+o),A */ + +OP(dd,78) { illegal_1(); op_78(); } /* DB DD */ +OP(dd,79) { illegal_1(); op_79(); } /* DB DD */ +OP(dd,7a) { illegal_1(); op_7a(); } /* DB DD */ +OP(dd,7b) { illegal_1(); op_7b(); } /* DB DD */ +OP(dd,7c) { _R++; _A = _HX; } /* LD A,HX */ +OP(dd,7d) { _R++; _A = _LX; } /* LD A,LX */ +OP(dd,7e) { _R++; EAX; _A = RM(EA); } /* LD A,(IX+o) */ +OP(dd,7f) { illegal_1(); op_7f(); } /* DB DD */ + +OP(dd,80) { illegal_1(); op_80(); } /* DB DD */ +OP(dd,81) { illegal_1(); op_81(); } /* DB DD */ +OP(dd,82) { illegal_1(); op_82(); } /* DB DD */ +OP(dd,83) { illegal_1(); op_83(); } /* DB DD */ +OP(dd,84) { _R++; ADD(_HX); } /* ADD A,HX */ +OP(dd,85) { _R++; ADD(_LX); } /* ADD A,LX */ +OP(dd,86) { _R++; EAX; ADD(RM(EA)); } /* ADD A,(IX+o) */ +OP(dd,87) { illegal_1(); op_87(); } /* DB DD */ + +OP(dd,88) { illegal_1(); op_88(); } /* DB DD */ +OP(dd,89) { illegal_1(); op_89(); } /* DB DD */ +OP(dd,8a) { illegal_1(); op_8a(); } /* DB DD */ +OP(dd,8b) { illegal_1(); op_8b(); } /* DB DD */ +OP(dd,8c) { _R++; ADC(_HX); } /* ADC A,HX */ +OP(dd,8d) { _R++; ADC(_LX); } /* ADC A,LX */ +OP(dd,8e) { _R++; EAX; ADC(RM(EA)); } /* ADC A,(IX+o) */ +OP(dd,8f) { illegal_1(); op_8f(); } /* DB DD */ + +OP(dd,90) { illegal_1(); op_90(); } /* DB DD */ +OP(dd,91) { illegal_1(); op_91(); } /* DB DD */ +OP(dd,92) { illegal_1(); op_92(); } /* DB DD */ +OP(dd,93) { illegal_1(); op_93(); } /* DB DD */ +OP(dd,94) { _R++; SUB(_HX); } /* SUB HX */ +OP(dd,95) { _R++; SUB(_LX); } /* SUB LX */ +OP(dd,96) { _R++; EAX; SUB(RM(EA)); } /* SUB (IX+o) */ +OP(dd,97) { illegal_1(); op_97(); } /* DB DD */ + +OP(dd,98) { illegal_1(); op_98(); } /* DB DD */ +OP(dd,99) { illegal_1(); op_99(); } /* DB DD */ +OP(dd,9a) { illegal_1(); op_9a(); } /* DB DD */ +OP(dd,9b) { illegal_1(); op_9b(); } /* DB DD */ +OP(dd,9c) { _R++; SBC(_HX); } /* SBC A,HX */ +OP(dd,9d) { _R++; SBC(_LX); } /* SBC A,LX */ +OP(dd,9e) { _R++; EAX; SBC(RM(EA)); } /* SBC A,(IX+o) */ +OP(dd,9f) { illegal_1(); op_9f(); } /* DB DD */ + +OP(dd,a0) { illegal_1(); op_a0(); } /* DB DD */ +OP(dd,a1) { illegal_1(); op_a1(); } /* DB DD */ +OP(dd,a2) { illegal_1(); op_a2(); } /* DB DD */ +OP(dd,a3) { illegal_1(); op_a3(); } /* DB DD */ +OP(dd,a4) { _R++; AND(_HX); } /* AND HX */ +OP(dd,a5) { _R++; AND(_LX); } /* AND LX */ +OP(dd,a6) { _R++; EAX; AND(RM(EA)); } /* AND (IX+o) */ +OP(dd,a7) { illegal_1(); op_a7(); } /* DB DD */ + +OP(dd,a8) { illegal_1(); op_a8(); } /* DB DD */ +OP(dd,a9) { illegal_1(); op_a9(); } /* DB DD */ +OP(dd,aa) { illegal_1(); op_aa(); } /* DB DD */ +OP(dd,ab) { illegal_1(); op_ab(); } /* DB DD */ +OP(dd,ac) { _R++; XOR(_HX); } /* XOR HX */ +OP(dd,ad) { _R++; XOR(_LX); } /* XOR LX */ +OP(dd,ae) { _R++; EAX; XOR(RM(EA)); } /* XOR (IX+o) */ +OP(dd,af) { illegal_1(); op_af(); } /* DB DD */ + +OP(dd,b0) { illegal_1(); op_b0(); } /* DB DD */ +OP(dd,b1) { illegal_1(); op_b1(); } /* DB DD */ +OP(dd,b2) { illegal_1(); op_b2(); } /* DB DD */ +OP(dd,b3) { illegal_1(); op_b3(); } /* DB DD */ +OP(dd,b4) { _R++; OR(_HX); } /* OR HX */ +OP(dd,b5) { _R++; OR(_LX); } /* OR LX */ +OP(dd,b6) { _R++; EAX; OR(RM(EA)); } /* OR (IX+o) */ +OP(dd,b7) { illegal_1(); op_b7(); } /* DB DD */ + +OP(dd,b8) { illegal_1(); op_b8(); } /* DB DD */ +OP(dd,b9) { illegal_1(); op_b9(); } /* DB DD */ +OP(dd,ba) { illegal_1(); op_ba(); } /* DB DD */ +OP(dd,bb) { illegal_1(); op_bb(); } /* DB DD */ +OP(dd,bc) { _R++; CP(_HX); } /* CP HX */ +OP(dd,bd) { _R++; CP(_LX); } /* CP LX */ +OP(dd,be) { _R++; EAX; CP(RM(EA)); } /* CP (IX+o) */ +OP(dd,bf) { illegal_1(); op_bf(); } /* DB DD */ + +OP(dd,c0) { illegal_1(); op_c0(); } /* DB DD */ +OP(dd,c1) { illegal_1(); op_c1(); } /* DB DD */ +OP(dd,c2) { illegal_1(); op_c2(); } /* DB DD */ +OP(dd,c3) { illegal_1(); op_c3(); } /* DB DD */ +OP(dd,c4) { illegal_1(); op_c4(); } /* DB DD */ +OP(dd,c5) { illegal_1(); op_c5(); } /* DB DD */ +OP(dd,c6) { illegal_1(); op_c6(); } /* DB DD */ +OP(dd,c7) { illegal_1(); op_c7(); } /* DB DD */ + +OP(dd,c8) { illegal_1(); op_c8(); } /* DB DD */ +OP(dd,c9) { illegal_1(); op_c9(); } /* DB DD */ +OP(dd,ca) { illegal_1(); op_ca(); } /* DB DD */ +OP(dd,cb) { _R++; EAX; EXEC(xycb,ARG()); } /* ** DD CB xx */ +OP(dd,cc) { illegal_1(); op_cc(); } /* DB DD */ +OP(dd,cd) { illegal_1(); op_cd(); } /* DB DD */ +OP(dd,ce) { illegal_1(); op_ce(); } /* DB DD */ +OP(dd,cf) { illegal_1(); op_cf(); } /* DB DD */ + +OP(dd,d0) { illegal_1(); op_d0(); } /* DB DD */ +OP(dd,d1) { illegal_1(); op_d1(); } /* DB DD */ +OP(dd,d2) { illegal_1(); op_d2(); } /* DB DD */ +OP(dd,d3) { illegal_1(); op_d3(); } /* DB DD */ +OP(dd,d4) { illegal_1(); op_d4(); } /* DB DD */ +OP(dd,d5) { illegal_1(); op_d5(); } /* DB DD */ +OP(dd,d6) { illegal_1(); op_d6(); } /* DB DD */ +OP(dd,d7) { illegal_1(); op_d7(); } /* DB DD */ + +OP(dd,d8) { illegal_1(); op_d8(); } /* DB DD */ +OP(dd,d9) { illegal_1(); op_d9(); } /* DB DD */ +OP(dd,da) { illegal_1(); op_da(); } /* DB DD */ +OP(dd,db) { illegal_1(); op_db(); } /* DB DD */ +OP(dd,dc) { illegal_1(); op_dc(); } /* DB DD */ +OP(dd,dd) { illegal_1(); op_dd(); } /* DB DD */ +OP(dd,de) { illegal_1(); op_de(); } /* DB DD */ +OP(dd,df) { illegal_1(); op_df(); } /* DB DD */ + +OP(dd,e0) { illegal_1(); op_e0(); } /* DB DD */ +OP(dd,e1) { _R++; POP(IX); } /* POP IX */ +OP(dd,e2) { illegal_1(); op_e2(); } /* DB DD */ +OP(dd,e3) { _R++; EXSP(IX); } /* EX (SP),IX */ +OP(dd,e4) { illegal_1(); op_e4(); } /* DB DD */ +OP(dd,e5) { _R++; PUSH( IX ); } /* PUSH IX */ +OP(dd,e6) { illegal_1(); op_e6(); } /* DB DD */ +OP(dd,e7) { illegal_1(); op_e7(); } /* DB DD */ + +OP(dd,e8) { illegal_1(); op_e8(); } /* DB DD */ +OP(dd,e9) { _R++; _PC = _IX; } /* JP (IX) */ +OP(dd,ea) { illegal_1(); op_ea(); } /* DB DD */ +OP(dd,eb) { illegal_1(); op_eb(); } /* DB DD */ +OP(dd,ec) { illegal_1(); op_ec(); } /* DB DD */ +OP(dd,ed) { illegal_1(); op_ed(); } /* DB DD */ +OP(dd,ee) { illegal_1(); op_ee(); } /* DB DD */ +OP(dd,ef) { illegal_1(); op_ef(); } /* DB DD */ + +OP(dd,f0) { illegal_1(); op_f0(); } /* DB DD */ +OP(dd,f1) { illegal_1(); op_f1(); } /* DB DD */ +OP(dd,f2) { illegal_1(); op_f2(); } /* DB DD */ +OP(dd,f3) { illegal_1(); op_f3(); } /* DB DD */ +OP(dd,f4) { illegal_1(); op_f4(); } /* DB DD */ +OP(dd,f5) { illegal_1(); op_f5(); } /* DB DD */ +OP(dd,f6) { illegal_1(); op_f6(); } /* DB DD */ +OP(dd,f7) { illegal_1(); op_f7(); } /* DB DD */ + +OP(dd,f8) { illegal_1(); op_f8(); } /* DB DD */ +OP(dd,f9) { _R++; _SP = _IX; } /* LD SP,IX */ +OP(dd,fa) { illegal_1(); op_fa(); } /* DB DD */ +OP(dd,fb) { illegal_1(); op_fb(); } /* DB DD */ +OP(dd,fc) { illegal_1(); op_fc(); } /* DB DD */ +OP(dd,fd) { illegal_1(); op_fd(); } /* DB DD */ +OP(dd,fe) { illegal_1(); op_fe(); } /* DB DD */ +OP(dd,ff) { illegal_1(); op_ff(); } /* DB DD */ + +/********************************************************** + * IY register related opcodes (FD prefix) + **********************************************************/ +OP(fd,00) { illegal_1(); op_00(); } /* DB FD */ +OP(fd,01) { illegal_1(); op_01(); } /* DB FD */ +OP(fd,02) { illegal_1(); op_02(); } /* DB FD */ +OP(fd,03) { illegal_1(); op_03(); } /* DB FD */ +OP(fd,04) { illegal_1(); op_04(); } /* DB FD */ +OP(fd,05) { illegal_1(); op_05(); } /* DB FD */ +OP(fd,06) { illegal_1(); op_06(); } /* DB FD */ +OP(fd,07) { illegal_1(); op_07(); } /* DB FD */ + +OP(fd,08) { illegal_1(); op_08(); } /* DB FD */ +OP(fd,09) { _R++; ADD16(IY,BC); } /* ADD IY,BC */ +OP(fd,0a) { illegal_1(); op_0a(); } /* DB FD */ +OP(fd,0b) { illegal_1(); op_0b(); } /* DB FD */ +OP(fd,0c) { illegal_1(); op_0c(); } /* DB FD */ +OP(fd,0d) { illegal_1(); op_0d(); } /* DB FD */ +OP(fd,0e) { illegal_1(); op_0e(); } /* DB FD */ +OP(fd,0f) { illegal_1(); op_0f(); } /* DB FD */ + +OP(fd,10) { illegal_1(); op_10(); } /* DB FD */ +OP(fd,11) { illegal_1(); op_11(); } /* DB FD */ +OP(fd,12) { illegal_1(); op_12(); } /* DB FD */ +OP(fd,13) { illegal_1(); op_13(); } /* DB FD */ +OP(fd,14) { illegal_1(); op_14(); } /* DB FD */ +OP(fd,15) { illegal_1(); op_15(); } /* DB FD */ +OP(fd,16) { illegal_1(); op_16(); } /* DB FD */ +OP(fd,17) { illegal_1(); op_17(); } /* DB FD */ + +OP(fd,18) { illegal_1(); op_18(); } /* DB FD */ +OP(fd,19) { _R++; ADD16(IY,DE); } /* ADD IY,DE */ +OP(fd,1a) { illegal_1(); op_1a(); } /* DB FD */ +OP(fd,1b) { illegal_1(); op_1b(); } /* DB FD */ +OP(fd,1c) { illegal_1(); op_1c(); } /* DB FD */ +OP(fd,1d) { illegal_1(); op_1d(); } /* DB FD */ +OP(fd,1e) { illegal_1(); op_1e(); } /* DB FD */ +OP(fd,1f) { illegal_1(); op_1f(); } /* DB FD */ + +OP(fd,20) { illegal_1(); op_20(); } /* DB FD */ +OP(fd,21) { _R++; _IY = ARG16(); } /* LD IY,w */ +OP(fd,22) { _R++; EA = ARG16(); WM16( EA, &Z80.IY ); } /* LD (w),IY */ +OP(fd,23) { _R++; _IY++; } /* INC IY */ +OP(fd,24) { _R++; _HY = INC(_HY); } /* INC HY */ +OP(fd,25) { _R++; _HY = DEC(_HY); } /* DEC HY */ +OP(fd,26) { _R++; _HY = ARG(); } /* LD HY,n */ +OP(fd,27) { illegal_1(); op_27(); } /* DB FD */ + +OP(fd,28) { illegal_1(); op_28(); } /* DB FD */ +OP(fd,29) { _R++; ADD16(IY,IY); } /* ADD IY,IY */ +OP(fd,2a) { _R++; EA = ARG16(); RM16( EA, &Z80.IY ); } /* LD IY,(w) */ +OP(fd,2b) { _R++; _IY--; } /* DEC IY */ +OP(fd,2c) { _R++; _LY = INC(_LY); } /* INC LY */ +OP(fd,2d) { _R++; _LY = DEC(_LY); } /* DEC LY */ +OP(fd,2e) { _R++; _LY = ARG(); } /* LD LY,n */ +OP(fd,2f) { illegal_1(); op_2f(); } /* DB FD */ + +OP(fd,30) { illegal_1(); op_30(); } /* DB FD */ +OP(fd,31) { illegal_1(); op_31(); } /* DB FD */ +OP(fd,32) { illegal_1(); op_32(); } /* DB FD */ +OP(fd,33) { illegal_1(); op_33(); } /* DB FD */ +OP(fd,34) { _R++; EAY; WM( EA, INC(RM(EA)) ); } /* INC (IY+o) */ +OP(fd,35) { _R++; EAY; WM( EA, DEC(RM(EA)) ); } /* DEC (IY+o) */ +OP(fd,36) { _R++; EAY; WM( EA, ARG() ); } /* LD (IY+o),n */ +OP(fd,37) { illegal_1(); op_37(); } /* DB FD */ + +OP(fd,38) { illegal_1(); op_38(); } /* DB FD */ +OP(fd,39) { _R++; ADD16(IY,SP); } /* ADD IY,SP */ +OP(fd,3a) { illegal_1(); op_3a(); } /* DB FD */ +OP(fd,3b) { illegal_1(); op_3b(); } /* DB FD */ +OP(fd,3c) { illegal_1(); op_3c(); } /* DB FD */ +OP(fd,3d) { illegal_1(); op_3d(); } /* DB FD */ +OP(fd,3e) { illegal_1(); op_3e(); } /* DB FD */ +OP(fd,3f) { illegal_1(); op_3f(); } /* DB FD */ + +OP(fd,40) { illegal_1(); op_40(); } /* DB FD */ +OP(fd,41) { illegal_1(); op_41(); } /* DB FD */ +OP(fd,42) { illegal_1(); op_42(); } /* DB FD */ +OP(fd,43) { illegal_1(); op_43(); } /* DB FD */ +OP(fd,44) { _R++; _B = _HY; } /* LD B,HY */ +OP(fd,45) { _R++; _B = _LY; } /* LD B,LY */ +OP(fd,46) { _R++; EAY; _B = RM(EA); } /* LD B,(IY+o) */ +OP(fd,47) { illegal_1(); op_47(); } /* DB FD */ + +OP(fd,48) { illegal_1(); op_48(); } /* DB FD */ +OP(fd,49) { illegal_1(); op_49(); } /* DB FD */ +OP(fd,4a) { illegal_1(); op_4a(); } /* DB FD */ +OP(fd,4b) { illegal_1(); op_4b(); } /* DB FD */ +OP(fd,4c) { _R++; _C = _HY; } /* LD C,HY */ +OP(fd,4d) { _R++; _C = _LY; } /* LD C,LY */ +OP(fd,4e) { _R++; EAY; _C = RM(EA); } /* LD C,(IY+o) */ +OP(fd,4f) { illegal_1(); op_4f(); } /* DB FD */ + +OP(fd,50) { illegal_1(); op_50(); } /* DB FD */ +OP(fd,51) { illegal_1(); op_51(); } /* DB FD */ +OP(fd,52) { illegal_1(); op_52(); } /* DB FD */ +OP(fd,53) { illegal_1(); op_53(); } /* DB FD */ +OP(fd,54) { _R++; _D = _HY; } /* LD D,HY */ +OP(fd,55) { _R++; _D = _LY; } /* LD D,LY */ +OP(fd,56) { _R++; EAY; _D = RM(EA); } /* LD D,(IY+o) */ +OP(fd,57) { illegal_1(); op_57(); } /* DB FD */ + +OP(fd,58) { illegal_1(); op_58(); } /* DB FD */ +OP(fd,59) { illegal_1(); op_59(); } /* DB FD */ +OP(fd,5a) { illegal_1(); op_5a(); } /* DB FD */ +OP(fd,5b) { illegal_1(); op_5b(); } /* DB FD */ +OP(fd,5c) { _R++; _E = _HY; } /* LD E,HY */ +OP(fd,5d) { _R++; _E = _LY; } /* LD E,LY */ +OP(fd,5e) { _R++; EAY; _E = RM(EA); } /* LD E,(IY+o) */ +OP(fd,5f) { illegal_1(); op_5f(); } /* DB FD */ + +OP(fd,60) { _R++; _HY = _B; } /* LD HY,B */ +OP(fd,61) { _R++; _HY = _C; } /* LD HY,C */ +OP(fd,62) { _R++; _HY = _D; } /* LD HY,D */ +OP(fd,63) { _R++; _HY = _E; } /* LD HY,E */ +OP(fd,64) { _R++; } /* LD HY,HY */ +OP(fd,65) { _R++; _HY = _LY; } /* LD HY,LY */ +OP(fd,66) { _R++; EAY; _H = RM(EA); } /* LD H,(IY+o) */ +OP(fd,67) { _R++; _HY = _A; } /* LD HY,A */ + +OP(fd,68) { _R++; _LY = _B; } /* LD LY,B */ +OP(fd,69) { _R++; _LY = _C; } /* LD LY,C */ +OP(fd,6a) { _R++; _LY = _D; } /* LD LY,D */ +OP(fd,6b) { _R++; _LY = _E; } /* LD LY,E */ +OP(fd,6c) { _R++; _LY = _HY; } /* LD LY,HY */ +OP(fd,6d) { _R++; } /* LD LY,LY */ +OP(fd,6e) { _R++; EAY; _L = RM(EA); } /* LD L,(IY+o) */ +OP(fd,6f) { _R++; _LY = _A; } /* LD LY,A */ + +OP(fd,70) { _R++; EAY; WM( EA, _B ); } /* LD (IY+o),B */ +OP(fd,71) { _R++; EAY; WM( EA, _C ); } /* LD (IY+o),C */ +OP(fd,72) { _R++; EAY; WM( EA, _D ); } /* LD (IY+o),D */ +OP(fd,73) { _R++; EAY; WM( EA, _E ); } /* LD (IY+o),E */ +OP(fd,74) { _R++; EAY; WM( EA, _H ); } /* LD (IY+o),H */ +OP(fd,75) { _R++; EAY; WM( EA, _L ); } /* LD (IY+o),L */ +OP(fd,76) { illegal_1(); op_76(); } /* DB FD */ +OP(fd,77) { _R++; EAY; WM( EA, _A ); } /* LD (IY+o),A */ + +OP(fd,78) { illegal_1(); op_78(); } /* DB FD */ +OP(fd,79) { illegal_1(); op_79(); } /* DB FD */ +OP(fd,7a) { illegal_1(); op_7a(); } /* DB FD */ +OP(fd,7b) { illegal_1(); op_7b(); } /* DB FD */ +OP(fd,7c) { _R++; _A = _HY; } /* LD A,HY */ +OP(fd,7d) { _R++; _A = _LY; } /* LD A,LY */ +OP(fd,7e) { _R++; EAY; _A = RM(EA); } /* LD A,(IY+o) */ +OP(fd,7f) { illegal_1(); op_7f(); } /* DB FD */ + +OP(fd,80) { illegal_1(); op_80(); } /* DB FD */ +OP(fd,81) { illegal_1(); op_81(); } /* DB FD */ +OP(fd,82) { illegal_1(); op_82(); } /* DB FD */ +OP(fd,83) { illegal_1(); op_83(); } /* DB FD */ +OP(fd,84) { _R++; ADD(_HY); } /* ADD A,HY */ +OP(fd,85) { _R++; ADD(_LY); } /* ADD A,LY */ +OP(fd,86) { _R++; EAY; ADD(RM(EA)); } /* ADD A,(IY+o) */ +OP(fd,87) { illegal_1(); op_87(); } /* DB FD */ + +OP(fd,88) { illegal_1(); op_88(); } /* DB FD */ +OP(fd,89) { illegal_1(); op_89(); } /* DB FD */ +OP(fd,8a) { illegal_1(); op_8a(); } /* DB FD */ +OP(fd,8b) { illegal_1(); op_8b(); } /* DB FD */ +OP(fd,8c) { _R++; ADC(_HY); } /* ADC A,HY */ +OP(fd,8d) { _R++; ADC(_LY); } /* ADC A,LY */ +OP(fd,8e) { _R++; EAY; ADC(RM(EA)); } /* ADC A,(IY+o) */ +OP(fd,8f) { illegal_1(); op_8f(); } /* DB FD */ + +OP(fd,90) { illegal_1(); op_90(); } /* DB FD */ +OP(fd,91) { illegal_1(); op_91(); } /* DB FD */ +OP(fd,92) { illegal_1(); op_92(); } /* DB FD */ +OP(fd,93) { illegal_1(); op_93(); } /* DB FD */ +OP(fd,94) { _R++; SUB(_HY); } /* SUB HY */ +OP(fd,95) { _R++; SUB(_LY); } /* SUB LY */ +OP(fd,96) { _R++; EAY; SUB(RM(EA)); } /* SUB (IY+o) */ +OP(fd,97) { illegal_1(); op_97(); } /* DB FD */ + +OP(fd,98) { illegal_1(); op_98(); } /* DB FD */ +OP(fd,99) { illegal_1(); op_99(); } /* DB FD */ +OP(fd,9a) { illegal_1(); op_9a(); } /* DB FD */ +OP(fd,9b) { illegal_1(); op_9b(); } /* DB FD */ +OP(fd,9c) { _R++; SBC(_HY); } /* SBC A,HY */ +OP(fd,9d) { _R++; SBC(_LY); } /* SBC A,LY */ +OP(fd,9e) { _R++; EAY; SBC(RM(EA)); } /* SBC A,(IY+o) */ +OP(fd,9f) { illegal_1(); op_9f(); } /* DB FD */ + +OP(fd,a0) { illegal_1(); op_a0(); } /* DB FD */ +OP(fd,a1) { illegal_1(); op_a1(); } /* DB FD */ +OP(fd,a2) { illegal_1(); op_a2(); } /* DB FD */ +OP(fd,a3) { illegal_1(); op_a3(); } /* DB FD */ +OP(fd,a4) { _R++; AND(_HY); } /* AND HY */ +OP(fd,a5) { _R++; AND(_LY); } /* AND LY */ +OP(fd,a6) { _R++; EAY; AND(RM(EA)); } /* AND (IY+o) */ +OP(fd,a7) { illegal_1(); op_a7(); } /* DB FD */ + +OP(fd,a8) { illegal_1(); op_a8(); } /* DB FD */ +OP(fd,a9) { illegal_1(); op_a9(); } /* DB FD */ +OP(fd,aa) { illegal_1(); op_aa(); } /* DB FD */ +OP(fd,ab) { illegal_1(); op_ab(); } /* DB FD */ +OP(fd,ac) { _R++; XOR(_HY); } /* XOR HY */ +OP(fd,ad) { _R++; XOR(_LY); } /* XOR LY */ +OP(fd,ae) { _R++; EAY; XOR(RM(EA)); } /* XOR (IY+o) */ +OP(fd,af) { illegal_1(); op_af(); } /* DB FD */ + +OP(fd,b0) { illegal_1(); op_b0(); } /* DB FD */ +OP(fd,b1) { illegal_1(); op_b1(); } /* DB FD */ +OP(fd,b2) { illegal_1(); op_b2(); } /* DB FD */ +OP(fd,b3) { illegal_1(); op_b3(); } /* DB FD */ +OP(fd,b4) { _R++; OR(_HY); } /* OR HY */ +OP(fd,b5) { _R++; OR(_LY); } /* OR LY */ +OP(fd,b6) { _R++; EAY; OR(RM(EA)); } /* OR (IY+o) */ +OP(fd,b7) { illegal_1(); op_b7(); } /* DB FD */ + +OP(fd,b8) { illegal_1(); op_b8(); } /* DB FD */ +OP(fd,b9) { illegal_1(); op_b9(); } /* DB FD */ +OP(fd,ba) { illegal_1(); op_ba(); } /* DB FD */ +OP(fd,bb) { illegal_1(); op_bb(); } /* DB FD */ +OP(fd,bc) { _R++; CP(_HY); } /* CP HY */ +OP(fd,bd) { _R++; CP(_LY); } /* CP LY */ +OP(fd,be) { _R++; EAY; CP(RM(EA)); } /* CP (IY+o) */ +OP(fd,bf) { illegal_1(); op_bf(); } /* DB FD */ + +OP(fd,c0) { illegal_1(); op_c0(); } /* DB FD */ +OP(fd,c1) { illegal_1(); op_c1(); } /* DB FD */ +OP(fd,c2) { illegal_1(); op_c2(); } /* DB FD */ +OP(fd,c3) { illegal_1(); op_c3(); } /* DB FD */ +OP(fd,c4) { illegal_1(); op_c4(); } /* DB FD */ +OP(fd,c5) { illegal_1(); op_c5(); } /* DB FD */ +OP(fd,c6) { illegal_1(); op_c6(); } /* DB FD */ +OP(fd,c7) { illegal_1(); op_c7(); } /* DB FD */ + +OP(fd,c8) { illegal_1(); op_c8(); } /* DB FD */ +OP(fd,c9) { illegal_1(); op_c9(); } /* DB FD */ +OP(fd,ca) { illegal_1(); op_ca(); } /* DB FD */ +OP(fd,cb) { _R++; EAY; EXEC(xycb,ARG()); } /* ** FD CB xx */ +OP(fd,cc) { illegal_1(); op_cc(); } /* DB FD */ +OP(fd,cd) { illegal_1(); op_cd(); } /* DB FD */ +OP(fd,ce) { illegal_1(); op_ce(); } /* DB FD */ +OP(fd,cf) { illegal_1(); op_cf(); } /* DB FD */ + +OP(fd,d0) { illegal_1(); op_d0(); } /* DB FD */ +OP(fd,d1) { illegal_1(); op_d1(); } /* DB FD */ +OP(fd,d2) { illegal_1(); op_d2(); } /* DB FD */ +OP(fd,d3) { illegal_1(); op_d3(); } /* DB FD */ +OP(fd,d4) { illegal_1(); op_d4(); } /* DB FD */ +OP(fd,d5) { illegal_1(); op_d5(); } /* DB FD */ +OP(fd,d6) { illegal_1(); op_d6(); } /* DB FD */ +OP(fd,d7) { illegal_1(); op_d7(); } /* DB FD */ + +OP(fd,d8) { illegal_1(); op_d8(); } /* DB FD */ +OP(fd,d9) { illegal_1(); op_d9(); } /* DB FD */ +OP(fd,da) { illegal_1(); op_da(); } /* DB FD */ +OP(fd,db) { illegal_1(); op_db(); } /* DB FD */ +OP(fd,dc) { illegal_1(); op_dc(); } /* DB FD */ +OP(fd,dd) { illegal_1(); op_dd(); } /* DB FD */ +OP(fd,de) { illegal_1(); op_de(); } /* DB FD */ +OP(fd,df) { illegal_1(); op_df(); } /* DB FD */ + +OP(fd,e0) { illegal_1(); op_e0(); } /* DB FD */ +OP(fd,e1) { _R++; POP(IY); } /* POP IY */ +OP(fd,e2) { illegal_1(); op_e2(); } /* DB FD */ +OP(fd,e3) { _R++; EXSP(IY); } /* EX (SP),IY */ +OP(fd,e4) { illegal_1(); op_e4(); } /* DB FD */ +OP(fd,e5) { _R++; PUSH( IY ); } /* PUSH IY */ +OP(fd,e6) { illegal_1(); op_e6(); } /* DB FD */ +OP(fd,e7) { illegal_1(); op_e7(); } /* DB FD */ + +OP(fd,e8) { illegal_1(); op_e8(); } /* DB FD */ +OP(fd,e9) { _R++; _PC = _IY; } /* JP (IY) */ +OP(fd,ea) { illegal_1(); op_ea(); } /* DB FD */ +OP(fd,eb) { illegal_1(); op_eb(); } /* DB FD */ +OP(fd,ec) { illegal_1(); op_ec(); } /* DB FD */ +OP(fd,ed) { illegal_1(); op_ed(); } /* DB FD */ +OP(fd,ee) { illegal_1(); op_ee(); } /* DB FD */ +OP(fd,ef) { illegal_1(); op_ef(); } /* DB FD */ + +OP(fd,f0) { illegal_1(); op_f0(); } /* DB FD */ +OP(fd,f1) { illegal_1(); op_f1(); } /* DB FD */ +OP(fd,f2) { illegal_1(); op_f2(); } /* DB FD */ +OP(fd,f3) { illegal_1(); op_f3(); } /* DB FD */ +OP(fd,f4) { illegal_1(); op_f4(); } /* DB FD */ +OP(fd,f5) { illegal_1(); op_f5(); } /* DB FD */ +OP(fd,f6) { illegal_1(); op_f6(); } /* DB FD */ +OP(fd,f7) { illegal_1(); op_f7(); } /* DB FD */ + +OP(fd,f8) { illegal_1(); op_f8(); } /* DB FD */ +OP(fd,f9) { _R++; _SP = _IY; } /* LD SP,IY */ +OP(fd,fa) { illegal_1(); op_fa(); } /* DB FD */ +OP(fd,fb) { illegal_1(); op_fb(); } /* DB FD */ +OP(fd,fc) { illegal_1(); op_fc(); } /* DB FD */ +OP(fd,fd) { illegal_1(); op_fd(); } /* DB FD */ +OP(fd,fe) { illegal_1(); op_fe(); } /* DB FD */ +OP(fd,ff) { illegal_1(); op_ff(); } /* DB FD */ + +OP(illegal,2) +{ +} + +/********************************************************** + * special opcodes (ED prefix) + **********************************************************/ +OP(ed,00) { illegal_2(); } /* DB ED */ +OP(ed,01) { illegal_2(); } /* DB ED */ +OP(ed,02) { illegal_2(); } /* DB ED */ +OP(ed,03) { illegal_2(); } /* DB ED */ +OP(ed,04) { illegal_2(); } /* DB ED */ +OP(ed,05) { illegal_2(); } /* DB ED */ +OP(ed,06) { illegal_2(); } /* DB ED */ +OP(ed,07) { illegal_2(); } /* DB ED */ + +OP(ed,08) { illegal_2(); } /* DB ED */ +OP(ed,09) { illegal_2(); } /* DB ED */ +OP(ed,0a) { illegal_2(); } /* DB ED */ +OP(ed,0b) { illegal_2(); } /* DB ED */ +OP(ed,0c) { illegal_2(); } /* DB ED */ +OP(ed,0d) { illegal_2(); } /* DB ED */ +OP(ed,0e) { illegal_2(); } /* DB ED */ +OP(ed,0f) { illegal_2(); } /* DB ED */ + +OP(ed,10) { illegal_2(); } /* DB ED */ +OP(ed,11) { illegal_2(); } /* DB ED */ +OP(ed,12) { illegal_2(); } /* DB ED */ +OP(ed,13) { illegal_2(); } /* DB ED */ +OP(ed,14) { illegal_2(); } /* DB ED */ +OP(ed,15) { illegal_2(); } /* DB ED */ +OP(ed,16) { illegal_2(); } /* DB ED */ +OP(ed,17) { illegal_2(); } /* DB ED */ + +OP(ed,18) { illegal_2(); } /* DB ED */ +OP(ed,19) { illegal_2(); } /* DB ED */ +OP(ed,1a) { illegal_2(); } /* DB ED */ +OP(ed,1b) { illegal_2(); } /* DB ED */ +OP(ed,1c) { illegal_2(); } /* DB ED */ +OP(ed,1d) { illegal_2(); } /* DB ED */ +OP(ed,1e) { illegal_2(); } /* DB ED */ +OP(ed,1f) { illegal_2(); } /* DB ED */ + +OP(ed,20) { illegal_2(); } /* DB ED */ +OP(ed,21) { illegal_2(); } /* DB ED */ +OP(ed,22) { illegal_2(); } /* DB ED */ +OP(ed,23) { illegal_2(); } /* DB ED */ +OP(ed,24) { illegal_2(); } /* DB ED */ +OP(ed,25) { illegal_2(); } /* DB ED */ +OP(ed,26) { illegal_2(); } /* DB ED */ +OP(ed,27) { illegal_2(); } /* DB ED */ + +OP(ed,28) { illegal_2(); } /* DB ED */ +OP(ed,29) { illegal_2(); } /* DB ED */ +OP(ed,2a) { illegal_2(); } /* DB ED */ +OP(ed,2b) { illegal_2(); } /* DB ED */ +OP(ed,2c) { illegal_2(); } /* DB ED */ +OP(ed,2d) { illegal_2(); } /* DB ED */ +OP(ed,2e) { illegal_2(); } /* DB ED */ +OP(ed,2f) { illegal_2(); } /* DB ED */ + +OP(ed,30) { illegal_2(); } /* DB ED */ +OP(ed,31) { illegal_2(); } /* DB ED */ +OP(ed,32) { illegal_2(); } /* DB ED */ +OP(ed,33) { illegal_2(); } /* DB ED */ +OP(ed,34) { illegal_2(); } /* DB ED */ +OP(ed,35) { illegal_2(); } /* DB ED */ +OP(ed,36) { illegal_2(); } /* DB ED */ +OP(ed,37) { illegal_2(); } /* DB ED */ + +OP(ed,38) { illegal_2(); } /* DB ED */ +OP(ed,39) { illegal_2(); } /* DB ED */ +OP(ed,3a) { illegal_2(); } /* DB ED */ +OP(ed,3b) { illegal_2(); } /* DB ED */ +OP(ed,3c) { illegal_2(); } /* DB ED */ +OP(ed,3d) { illegal_2(); } /* DB ED */ +OP(ed,3e) { illegal_2(); } /* DB ED */ +OP(ed,3f) { illegal_2(); } /* DB ED */ + +OP(ed,40) { _B = IN(_BC); _F = (_F & CF) | SZP[_B]; } /* IN B,(C) */ +OP(ed,41) { OUT(_BC,_B); } /* OUT (C),B */ +OP(ed,42) { SBC16( BC ); } /* SBC HL,BC */ +OP(ed,43) { EA = ARG16(); WM16( EA, &Z80.BC ); } /* LD (w),BC */ +OP(ed,44) { NEG; } /* NEG */ +OP(ed,45) { RETN; } /* RETN; */ +OP(ed,46) { _IM = 0; } /* IM 0 */ +OP(ed,47) { LD_I_A; } /* LD I,A */ + +OP(ed,48) { _C = IN(_BC); _F = (_F & CF) | SZP[_C]; } /* IN C,(C) */ +OP(ed,49) { OUT(_BC,_C); } /* OUT (C),C */ +OP(ed,4a) { ADC16( BC ); } /* ADC HL,BC */ +OP(ed,4b) { EA = ARG16(); RM16( EA, &Z80.BC ); } /* LD BC,(w) */ +OP(ed,4c) { NEG; } /* NEG */ +OP(ed,4d) { RETI; } /* RETI */ +OP(ed,4e) { _IM = 0; } /* IM 0 */ +OP(ed,4f) { LD_R_A; } /* LD R,A */ + +OP(ed,50) { _D = IN(_BC); _F = (_F & CF) | SZP[_D]; } /* IN D,(C) */ +OP(ed,51) { OUT(_BC,_D); } /* OUT (C),D */ +OP(ed,52) { SBC16( DE ); } /* SBC HL,DE */ +OP(ed,53) { EA = ARG16(); WM16( EA, &Z80.DE ); } /* LD (w),DE */ +OP(ed,54) { NEG; } /* NEG */ +OP(ed,55) { RETN; } /* RETN; */ +OP(ed,56) { _IM = 1; } /* IM 1 */ +OP(ed,57) { LD_A_I; } /* LD A,I */ + +OP(ed,58) { _E = IN(_BC); _F = (_F & CF) | SZP[_E]; } /* IN E,(C) */ +OP(ed,59) { OUT(_BC,_E); } /* OUT (C),E */ +OP(ed,5a) { ADC16( DE ); } /* ADC HL,DE */ +OP(ed,5b) { EA = ARG16(); RM16( EA, &Z80.DE ); } /* LD DE,(w) */ +OP(ed,5c) { NEG; } /* NEG */ +OP(ed,5d) { RETI; } /* RETI */ +OP(ed,5e) { _IM = 2; } /* IM 2 */ +OP(ed,5f) { LD_A_R; } /* LD A,R */ + +OP(ed,60) { _H = IN(_BC); _F = (_F & CF) | SZP[_H]; } /* IN H,(C) */ +OP(ed,61) { OUT(_BC,_H); } /* OUT (C),H */ +OP(ed,62) { SBC16( HL ); } /* SBC HL,HL */ +OP(ed,63) { EA = ARG16(); WM16( EA, &Z80.HL ); } /* LD (w),HL */ +OP(ed,64) { NEG; } /* NEG */ +OP(ed,65) { RETN; } /* RETN; */ +OP(ed,66) { _IM = 0; } /* IM 0 */ +OP(ed,67) { RRD; } /* RRD (HL) */ + +OP(ed,68) { _L = IN(_BC); _F = (_F & CF) | SZP[_L]; } /* IN L,(C) */ +OP(ed,69) { OUT(_BC,_L); } /* OUT (C),L */ +OP(ed,6a) { ADC16( HL ); } /* ADC HL,HL */ +OP(ed,6b) { EA = ARG16(); RM16( EA, &Z80.HL ); } /* LD HL,(w) */ +OP(ed,6c) { NEG; } /* NEG */ +OP(ed,6d) { RETI; } /* RETI */ +OP(ed,6e) { _IM = 0; } /* IM 0 */ +OP(ed,6f) { RLD; } /* RLD (HL) */ + +OP(ed,70) { UINT8 res = IN(_BC); _F = (_F & CF) | SZP[res]; } /* IN 0,(C) */ +OP(ed,71) { OUT(_BC,0); } /* OUT (C),0 */ +OP(ed,72) { SBC16( SP ); } /* SBC HL,SP */ +OP(ed,73) { EA = ARG16(); WM16( EA, &Z80.SP ); } /* LD (w),SP */ +OP(ed,74) { NEG; } /* NEG */ +OP(ed,75) { RETN; } /* RETN; */ +OP(ed,76) { _IM = 1; } /* IM 1 */ +OP(ed,77) { illegal_2(); } /* DB ED,77 */ + +OP(ed,78) { _A = IN(_BC); _F = (_F & CF) | SZP[_A]; } /* IN E,(C) */ +OP(ed,79) { OUT(_BC,_A); } /* OUT (C),E */ +OP(ed,7a) { ADC16( SP ); } /* ADC HL,SP */ +OP(ed,7b) { EA = ARG16(); RM16( EA, &Z80.SP ); } /* LD SP,(w) */ +OP(ed,7c) { NEG; } /* NEG */ +OP(ed,7d) { RETI; } /* RETI */ +OP(ed,7e) { _IM = 2; } /* IM 2 */ +OP(ed,7f) { illegal_2(); } /* DB ED,7F */ + +OP(ed,80) { illegal_2(); } /* DB ED */ +OP(ed,81) { illegal_2(); } /* DB ED */ +OP(ed,82) { illegal_2(); } /* DB ED */ +OP(ed,83) { illegal_2(); } /* DB ED */ +OP(ed,84) { illegal_2(); } /* DB ED */ +OP(ed,85) { illegal_2(); } /* DB ED */ +OP(ed,86) { illegal_2(); } /* DB ED */ +OP(ed,87) { illegal_2(); } /* DB ED */ + +OP(ed,88) { illegal_2(); } /* DB ED */ +OP(ed,89) { illegal_2(); } /* DB ED */ +OP(ed,8a) { illegal_2(); } /* DB ED */ +OP(ed,8b) { illegal_2(); } /* DB ED */ +OP(ed,8c) { illegal_2(); } /* DB ED */ +OP(ed,8d) { illegal_2(); } /* DB ED */ +OP(ed,8e) { illegal_2(); } /* DB ED */ +OP(ed,8f) { illegal_2(); } /* DB ED */ + +OP(ed,90) { illegal_2(); } /* DB ED */ +OP(ed,91) { illegal_2(); } /* DB ED */ +OP(ed,92) { illegal_2(); } /* DB ED */ +OP(ed,93) { illegal_2(); } /* DB ED */ +OP(ed,94) { illegal_2(); } /* DB ED */ +OP(ed,95) { illegal_2(); } /* DB ED */ +OP(ed,96) { illegal_2(); } /* DB ED */ +OP(ed,97) { illegal_2(); } /* DB ED */ + +OP(ed,98) { illegal_2(); } /* DB ED */ +OP(ed,99) { illegal_2(); } /* DB ED */ +OP(ed,9a) { illegal_2(); } /* DB ED */ +OP(ed,9b) { illegal_2(); } /* DB ED */ +OP(ed,9c) { illegal_2(); } /* DB ED */ +OP(ed,9d) { illegal_2(); } /* DB ED */ +OP(ed,9e) { illegal_2(); } /* DB ED */ +OP(ed,9f) { illegal_2(); } /* DB ED */ + +OP(ed,a0) { LDI; } /* LDI */ +OP(ed,a1) { CPI; } /* CPI */ +OP(ed,a2) { INI; } /* INI */ +OP(ed,a3) { OUTI; } /* OUTI */ +OP(ed,a4) { illegal_2(); } /* DB ED */ +OP(ed,a5) { illegal_2(); } /* DB ED */ +OP(ed,a6) { illegal_2(); } /* DB ED */ +OP(ed,a7) { illegal_2(); } /* DB ED */ + +OP(ed,a8) { LDD; } /* LDD */ +OP(ed,a9) { CPD; } /* CPD */ +OP(ed,aa) { IND; } /* IND */ +OP(ed,ab) { OUTD; } /* OUTD */ +OP(ed,ac) { illegal_2(); } /* DB ED */ +OP(ed,ad) { illegal_2(); } /* DB ED */ +OP(ed,ae) { illegal_2(); } /* DB ED */ +OP(ed,af) { illegal_2(); } /* DB ED */ + +OP(ed,b0) { LDIR; } /* LDIR */ +OP(ed,b1) { CPIR; } /* CPIR */ +OP(ed,b2) { INIR; } /* INIR */ +OP(ed,b3) { OTIR; } /* OTIR */ +OP(ed,b4) { illegal_2(); } /* DB ED */ +OP(ed,b5) { illegal_2(); } /* DB ED */ +OP(ed,b6) { illegal_2(); } /* DB ED */ +OP(ed,b7) { illegal_2(); } /* DB ED */ + +OP(ed,b8) { LDDR; } /* LDDR */ +OP(ed,b9) { CPDR; } /* CPDR */ +OP(ed,ba) { INDR; } /* INDR */ +OP(ed,bb) { OTDR; } /* OTDR */ +OP(ed,bc) { illegal_2(); } /* DB ED */ +OP(ed,bd) { illegal_2(); } /* DB ED */ +OP(ed,be) { illegal_2(); } /* DB ED */ +OP(ed,bf) { illegal_2(); } /* DB ED */ + +OP(ed,c0) { illegal_2(); } /* DB ED */ +OP(ed,c1) { illegal_2(); } /* DB ED */ +OP(ed,c2) { illegal_2(); } /* DB ED */ +OP(ed,c3) { illegal_2(); } /* DB ED */ +OP(ed,c4) { illegal_2(); } /* DB ED */ +OP(ed,c5) { illegal_2(); } /* DB ED */ +OP(ed,c6) { illegal_2(); } /* DB ED */ +OP(ed,c7) { illegal_2(); } /* DB ED */ + +OP(ed,c8) { illegal_2(); } /* DB ED */ +OP(ed,c9) { illegal_2(); } /* DB ED */ +OP(ed,ca) { illegal_2(); } /* DB ED */ +OP(ed,cb) { illegal_2(); } /* DB ED */ +OP(ed,cc) { illegal_2(); } /* DB ED */ +OP(ed,cd) { illegal_2(); } /* DB ED */ +OP(ed,ce) { illegal_2(); } /* DB ED */ +OP(ed,cf) { illegal_2(); } /* DB ED */ + +OP(ed,d0) { illegal_2(); } /* DB ED */ +OP(ed,d1) { illegal_2(); } /* DB ED */ +OP(ed,d2) { illegal_2(); } /* DB ED */ +OP(ed,d3) { illegal_2(); } /* DB ED */ +OP(ed,d4) { illegal_2(); } /* DB ED */ +OP(ed,d5) { illegal_2(); } /* DB ED */ +OP(ed,d6) { illegal_2(); } /* DB ED */ +OP(ed,d7) { illegal_2(); } /* DB ED */ + +OP(ed,d8) { illegal_2(); } /* DB ED */ +OP(ed,d9) { illegal_2(); } /* DB ED */ +OP(ed,da) { illegal_2(); } /* DB ED */ +OP(ed,db) { illegal_2(); } /* DB ED */ +OP(ed,dc) { illegal_2(); } /* DB ED */ +OP(ed,dd) { illegal_2(); } /* DB ED */ +OP(ed,de) { illegal_2(); } /* DB ED */ +OP(ed,df) { illegal_2(); } /* DB ED */ + +OP(ed,e0) { illegal_2(); } /* DB ED */ +OP(ed,e1) { illegal_2(); } /* DB ED */ +OP(ed,e2) { illegal_2(); } /* DB ED */ +OP(ed,e3) { illegal_2(); } /* DB ED */ +OP(ed,e4) { illegal_2(); } /* DB ED */ +OP(ed,e5) { illegal_2(); } /* DB ED */ +OP(ed,e6) { illegal_2(); } /* DB ED */ +OP(ed,e7) { illegal_2(); } /* DB ED */ + +OP(ed,e8) { illegal_2(); } /* DB ED */ +OP(ed,e9) { illegal_2(); } /* DB ED */ +OP(ed,ea) { illegal_2(); } /* DB ED */ +OP(ed,eb) { illegal_2(); } /* DB ED */ +OP(ed,ec) { illegal_2(); } /* DB ED */ +OP(ed,ed) { illegal_2(); } /* DB ED */ +OP(ed,ee) { illegal_2(); } /* DB ED */ +OP(ed,ef) { illegal_2(); } /* DB ED */ + +OP(ed,f0) { illegal_2(); } /* DB ED */ +OP(ed,f1) { illegal_2(); } /* DB ED */ +OP(ed,f2) { illegal_2(); } /* DB ED */ +OP(ed,f3) { illegal_2(); } /* DB ED */ +OP(ed,f4) { illegal_2(); } /* DB ED */ +OP(ed,f5) { illegal_2(); } /* DB ED */ +OP(ed,f6) { illegal_2(); } /* DB ED */ +OP(ed,f7) { illegal_2(); } /* DB ED */ + +OP(ed,f8) { illegal_2(); } /* DB ED */ +OP(ed,f9) { illegal_2(); } /* DB ED */ +OP(ed,fa) { illegal_2(); } /* DB ED */ +OP(ed,fb) { illegal_2(); } /* DB ED */ +OP(ed,fc) { illegal_2(); } /* DB ED */ +OP(ed,fd) { illegal_2(); } /* DB ED */ +OP(ed,fe) { illegal_2(); } /* DB ED */ +OP(ed,ff) { illegal_2(); } /* DB ED */ + +#if TIME_LOOP_HACKS + +#define CHECK_BC_LOOP \ +if( _BC > 1 && _PCD < 0xfffc ) { \ + UINT8 op1 = cpu_readop(_PCD); \ + UINT8 op2 = cpu_readop(_PCD+1); \ + if( (op1==0x78 && op2==0xb1) || (op1==0x79 && op2==0xb0) ) \ + { \ + UINT8 op3 = cpu_readop(_PCD+2); \ + UINT8 op4 = cpu_readop(_PCD+3); \ + if( op3==0x20 && op4==0xfb ) \ + { \ + int cnt = \ + cc[Z80_TABLE_op][0x78] + \ + cc[Z80_TABLE_op][0xb1] + \ + cc[Z80_TABLE_op][0x20] + \ + cc[Z80_TABLE_ex][0x20]; \ + while( _BC > 0 && z80_ICount > cnt ) \ + { \ + BURNODD( cnt, 4, cnt ); \ + _BC--; \ + } \ + } \ + else \ + if( op3 == 0xc2 ) \ + { \ + UINT8 ad1 = cpu_readop_arg(_PCD+3); \ + UINT8 ad2 = cpu_readop_arg(_PCD+4); \ + if( (ad1 + 256 * ad2) == (_PCD - 1) ) \ + { \ + int cnt = \ + cc[Z80_TABLE_op][0x78] + \ + cc[Z80_TABLE_op][0xb1] + \ + cc[Z80_TABLE_op][0xc2] + \ + cc[Z80_TABLE_ex][0xc2]; \ + while( _BC > 0 && z80_ICount > cnt ) \ + { \ + BURNODD( cnt, 4, cnt ); \ + _BC--; \ + } \ + } \ + } \ + } \ +} + +#define CHECK_DE_LOOP \ +if( _DE > 1 && _PCD < 0xfffc ) { \ + UINT8 op1 = cpu_readop(_PCD); \ + UINT8 op2 = cpu_readop(_PCD+1); \ + if( (op1==0x7a && op2==0xb3) || (op1==0x7b && op2==0xb2) ) \ + { \ + UINT8 op3 = cpu_readop(_PCD+2); \ + UINT8 op4 = cpu_readop(_PCD+3); \ + if( op3==0x20 && op4==0xfb ) \ + { \ + int cnt = \ + cc[Z80_TABLE_op][0x7a] + \ + cc[Z80_TABLE_op][0xb3] + \ + cc[Z80_TABLE_op][0x20] + \ + cc[Z80_TABLE_ex][0x20]; \ + while( _DE > 0 && z80_ICount > cnt ) \ + { \ + BURNODD( cnt, 4, cnt ); \ + _DE--; \ + } \ + } \ + else \ + if( op3==0xc2 ) \ + { \ + UINT8 ad1 = cpu_readop_arg(_PCD+3); \ + UINT8 ad2 = cpu_readop_arg(_PCD+4); \ + if( (ad1 + 256 * ad2) == (_PCD - 1) ) \ + { \ + int cnt = \ + cc[Z80_TABLE_op][0x7a] + \ + cc[Z80_TABLE_op][0xb3] + \ + cc[Z80_TABLE_op][0xc2] + \ + cc[Z80_TABLE_ex][0xc2]; \ + while( _DE > 0 && z80_ICount > cnt ) \ + { \ + BURNODD( cnt, 4, cnt ); \ + _DE--; \ + } \ + } \ + } \ + } \ +} + +#define CHECK_HL_LOOP \ +if( _HL > 1 && _PCD < 0xfffc ) { \ + UINT8 op1 = cpu_readop(_PCD); \ + UINT8 op2 = cpu_readop(_PCD+1); \ + if( (op1==0x7c && op2==0xb5) || (op1==0x7d && op2==0xb4) ) \ + { \ + UINT8 op3 = cpu_readop(_PCD+2); \ + UINT8 op4 = cpu_readop(_PCD+3); \ + if( op3==0x20 && op4==0xfb ) \ + { \ + int cnt = \ + cc[Z80_TABLE_op][0x7c] + \ + cc[Z80_TABLE_op][0xb5] + \ + cc[Z80_TABLE_op][0x20] + \ + cc[Z80_TABLE_ex][0x20]; \ + while( _HL > 0 && z80_ICount > cnt ) \ + { \ + BURNODD( cnt, 4, cnt ); \ + _HL--; \ + } \ + } \ + else \ + if( op3==0xc2 ) \ + { \ + UINT8 ad1 = cpu_readop_arg(_PCD+3); \ + UINT8 ad2 = cpu_readop_arg(_PCD+4); \ + if( (ad1 + 256 * ad2) == (_PCD - 1) ) \ + { \ + int cnt = \ + cc[Z80_TABLE_op][0x7c] + \ + cc[Z80_TABLE_op][0xb5] + \ + cc[Z80_TABLE_op][0xc2] + \ + cc[Z80_TABLE_ex][0xc2]; \ + while( _HL > 0 && z80_ICount > cnt ) \ + { \ + BURNODD( cnt, 4, cnt ); \ + _HL--; \ + } \ + } \ + } \ + } \ +} + +#else + +#define CHECK_BC_LOOP +#define CHECK_DE_LOOP +#define CHECK_HL_LOOP + +#endif + +/********************************************************** + * main opcodes + **********************************************************/ +OP(op,00) { } /* NOP */ +OP(op,01) { _BC = ARG16(); } /* LD BC,w */ +OP(op,02) { WM( _BC, _A ); } /* LD (BC),A */ +OP(op,03) { _BC++; } /* INC BC */ +OP(op,04) { _B = INC(_B); } /* INC B */ +OP(op,05) { _B = DEC(_B); } /* DEC B */ +OP(op,06) { _B = ARG(); } /* LD B,n */ +OP(op,07) { RLCA; } /* RLCA */ + +OP(op,08) { EX_AF; } /* EX AF,AF' */ +OP(op,09) { ADD16(HL,BC); } /* ADD HL,BC */ +OP(op,0a) { _A = RM(_BC); } /* LD A,(BC) */ +OP(op,0b) { _BC--; CHECK_BC_LOOP; } /* DEC BC */ +OP(op,0c) { _C = INC(_C); } /* INC C */ +OP(op,0d) { _C = DEC(_C); } /* DEC C */ +OP(op,0e) { _C = ARG(); } /* LD C,n */ +OP(op,0f) { RRCA; } /* RRCA */ + +OP(op,10) { _B--; JR_COND( _B, 0x10 ); } /* DJNZ o */ +OP(op,11) { _DE = ARG16(); } /* LD DE,w */ +OP(op,12) { WM( _DE, _A ); } /* LD (DE),A */ +OP(op,13) { _DE++; } /* INC DE */ +OP(op,14) { _D = INC(_D); } /* INC D */ +OP(op,15) { _D = DEC(_D); } /* DEC D */ +OP(op,16) { _D = ARG(); } /* LD D,n */ +OP(op,17) { RLA; } /* RLA */ + +OP(op,18) { JR(); } /* JR o */ +OP(op,19) { ADD16(HL,DE); } /* ADD HL,DE */ +OP(op,1a) { _A = RM(_DE); } /* LD A,(DE) */ +OP(op,1b) { _DE--; CHECK_DE_LOOP; } /* DEC DE */ +OP(op,1c) { _E = INC(_E); } /* INC E */ +OP(op,1d) { _E = DEC(_E); } /* DEC E */ +OP(op,1e) { _E = ARG(); } /* LD E,n */ +OP(op,1f) { RRA; } /* RRA */ + +OP(op,20) { JR_COND( !(_F & ZF), 0x20 ); } /* JR NZ,o */ +OP(op,21) { _HL = ARG16(); } /* LD HL,w */ +OP(op,22) { EA = ARG16(); WM16( EA, &Z80.HL ); } /* LD (w),HL */ +OP(op,23) { _HL++; } /* INC HL */ +OP(op,24) { _H = INC(_H); } /* INC H */ +OP(op,25) { _H = DEC(_H); } /* DEC H */ +OP(op,26) { _H = ARG(); } /* LD H,n */ +OP(op,27) { DAA; } /* DAA */ + +OP(op,28) { JR_COND( _F & ZF, 0x28 ); } /* JR Z,o */ +OP(op,29) { ADD16(HL,HL); } /* ADD HL,HL */ +OP(op,2a) { EA = ARG16(); RM16( EA, &Z80.HL ); } /* LD HL,(w) */ +OP(op,2b) { _HL--; CHECK_HL_LOOP; } /* DEC HL */ +OP(op,2c) { _L = INC(_L); } /* INC L */ +OP(op,2d) { _L = DEC(_L); } /* DEC L */ +OP(op,2e) { _L = ARG(); } /* LD L,n */ +OP(op,2f) { _A ^= 0xff; _F = (_F&(SF|ZF|PF|CF))|HF|NF|(_A&(YF|XF)); } /* CPL */ + +OP(op,30) { JR_COND( !(_F & CF), 0x30 ); } /* JR NC,o */ +OP(op,31) { _SP = ARG16(); } /* LD SP,w */ +OP(op,32) { EA = ARG16(); WM( EA, _A ); } /* LD (w),A */ +OP(op,33) { _SP++; } /* INC SP */ +OP(op,34) { WM( _HL, INC(RM(_HL)) ); } /* INC (HL) */ +OP(op,35) { WM( _HL, DEC(RM(_HL)) ); } /* DEC (HL) */ +OP(op,36) { WM( _HL, ARG() ); } /* LD (HL),n */ +OP(op,37) { _F = (_F & (SF|ZF|PF)) | CF | (_A & (YF|XF)); } /* SCF */ + +OP(op,38) { JR_COND( _F & CF, 0x38 ); } /* JR C,o */ +OP(op,39) { ADD16(HL,SP); } /* ADD HL,SP */ +OP(op,3a) { EA = ARG16(); _A = RM( EA ); } /* LD A,(w) */ +OP(op,3b) { _SP--; } /* DEC SP */ +OP(op,3c) { _A = INC(_A); } /* INC A */ +OP(op,3d) { _A = DEC(_A); } /* DEC A */ +OP(op,3e) { _A = ARG(); } /* LD A,n */ +OP(op,3f) { _F = ((_F&(SF|ZF|PF|CF))|((_F&CF)<<4)|(_A&(YF|XF)))^CF; } /* CCF */ +//OP(op,3f) { _F = ((_F & ~(HF|NF)) | ((_F & CF)<<4)) ^ CF; } /* CCF */ + +OP(op,40) { } /* LD B,B */ +OP(op,41) { _B = _C; } /* LD B,C */ +OP(op,42) { _B = _D; } /* LD B,D */ +OP(op,43) { _B = _E; } /* LD B,E */ +OP(op,44) { _B = _H; } /* LD B,H */ +OP(op,45) { _B = _L; } /* LD B,L */ +OP(op,46) { _B = RM(_HL); } /* LD B,(HL) */ +OP(op,47) { _B = _A; } /* LD B,A */ + +OP(op,48) { _C = _B; } /* LD C,B */ +OP(op,49) { } /* LD C,C */ +OP(op,4a) { _C = _D; } /* LD C,D */ +OP(op,4b) { _C = _E; } /* LD C,E */ +OP(op,4c) { _C = _H; } /* LD C,H */ +OP(op,4d) { _C = _L; } /* LD C,L */ +OP(op,4e) { _C = RM(_HL); } /* LD C,(HL) */ +OP(op,4f) { _C = _A; } /* LD C,A */ + +OP(op,50) { _D = _B; } /* LD D,B */ +OP(op,51) { _D = _C; } /* LD D,C */ +OP(op,52) { } /* LD D,D */ +OP(op,53) { _D = _E; } /* LD D,E */ +OP(op,54) { _D = _H; } /* LD D,H */ +OP(op,55) { _D = _L; } /* LD D,L */ +OP(op,56) { _D = RM(_HL); } /* LD D,(HL) */ +OP(op,57) { _D = _A; } /* LD D,A */ + +OP(op,58) { _E = _B; } /* LD E,B */ +OP(op,59) { _E = _C; } /* LD E,C */ +OP(op,5a) { _E = _D; } /* LD E,D */ +OP(op,5b) { } /* LD E,E */ +OP(op,5c) { _E = _H; } /* LD E,H */ +OP(op,5d) { _E = _L; } /* LD E,L */ +OP(op,5e) { _E = RM(_HL); } /* LD E,(HL) */ +OP(op,5f) { _E = _A; } /* LD E,A */ + +OP(op,60) { _H = _B; } /* LD H,B */ +OP(op,61) { _H = _C; } /* LD H,C */ +OP(op,62) { _H = _D; } /* LD H,D */ +OP(op,63) { _H = _E; } /* LD H,E */ +OP(op,64) { } /* LD H,H */ +OP(op,65) { _H = _L; } /* LD H,L */ +OP(op,66) { _H = RM(_HL); } /* LD H,(HL) */ +OP(op,67) { _H = _A; } /* LD H,A */ + +OP(op,68) { _L = _B; } /* LD L,B */ +OP(op,69) { _L = _C; } /* LD L,C */ +OP(op,6a) { _L = _D; } /* LD L,D */ +OP(op,6b) { _L = _E; } /* LD L,E */ +OP(op,6c) { _L = _H; } /* LD L,H */ +OP(op,6d) { } /* LD L,L */ +OP(op,6e) { _L = RM(_HL); } /* LD L,(HL) */ +OP(op,6f) { _L = _A; } /* LD L,A */ + +OP(op,70) { WM( _HL, _B ); } /* LD (HL),B */ +OP(op,71) { WM( _HL, _C ); } /* LD (HL),C */ +OP(op,72) { WM( _HL, _D ); } /* LD (HL),D */ +OP(op,73) { WM( _HL, _E ); } /* LD (HL),E */ +OP(op,74) { WM( _HL, _H ); } /* LD (HL),H */ +OP(op,75) { WM( _HL, _L ); } /* LD (HL),L */ +OP(op,76) { ENTER_HALT; } /* HALT */ +OP(op,77) { WM( _HL, _A ); } /* LD (HL),A */ + +OP(op,78) { _A = _B; } /* LD A,B */ +OP(op,79) { _A = _C; } /* LD A,C */ +OP(op,7a) { _A = _D; } /* LD A,D */ +OP(op,7b) { _A = _E; } /* LD A,E */ +OP(op,7c) { _A = _H; } /* LD A,H */ +OP(op,7d) { _A = _L; } /* LD A,L */ +OP(op,7e) { _A = RM(_HL); } /* LD A,(HL) */ +OP(op,7f) { } /* LD A,A */ + +OP(op,80) { ADD(_B); } /* ADD A,B */ +OP(op,81) { ADD(_C); } /* ADD A,C */ +OP(op,82) { ADD(_D); } /* ADD A,D */ +OP(op,83) { ADD(_E); } /* ADD A,E */ +OP(op,84) { ADD(_H); } /* ADD A,H */ +OP(op,85) { ADD(_L); } /* ADD A,L */ +OP(op,86) { ADD(RM(_HL)); } /* ADD A,(HL) */ +OP(op,87) { ADD(_A); } /* ADD A,A */ + +OP(op,88) { ADC(_B); } /* ADC A,B */ +OP(op,89) { ADC(_C); } /* ADC A,C */ +OP(op,8a) { ADC(_D); } /* ADC A,D */ +OP(op,8b) { ADC(_E); } /* ADC A,E */ +OP(op,8c) { ADC(_H); } /* ADC A,H */ +OP(op,8d) { ADC(_L); } /* ADC A,L */ +OP(op,8e) { ADC(RM(_HL)); } /* ADC A,(HL) */ +OP(op,8f) { ADC(_A); } /* ADC A,A */ + +OP(op,90) { SUB(_B); } /* SUB B */ +OP(op,91) { SUB(_C); } /* SUB C */ +OP(op,92) { SUB(_D); } /* SUB D */ +OP(op,93) { SUB(_E); } /* SUB E */ +OP(op,94) { SUB(_H); } /* SUB H */ +OP(op,95) { SUB(_L); } /* SUB L */ +OP(op,96) { SUB(RM(_HL)); } /* SUB (HL) */ +OP(op,97) { SUB(_A); } /* SUB A */ + +OP(op,98) { SBC(_B); } /* SBC A,B */ +OP(op,99) { SBC(_C); } /* SBC A,C */ +OP(op,9a) { SBC(_D); } /* SBC A,D */ +OP(op,9b) { SBC(_E); } /* SBC A,E */ +OP(op,9c) { SBC(_H); } /* SBC A,H */ +OP(op,9d) { SBC(_L); } /* SBC A,L */ +OP(op,9e) { SBC(RM(_HL)); } /* SBC A,(HL) */ +OP(op,9f) { SBC(_A); } /* SBC A,A */ + +OP(op,a0) { AND(_B); } /* AND B */ +OP(op,a1) { AND(_C); } /* AND C */ +OP(op,a2) { AND(_D); } /* AND D */ +OP(op,a3) { AND(_E); } /* AND E */ +OP(op,a4) { AND(_H); } /* AND H */ +OP(op,a5) { AND(_L); } /* AND L */ +OP(op,a6) { AND(RM(_HL)); } /* AND (HL) */ +OP(op,a7) { AND(_A); } /* AND A */ + +OP(op,a8) { XOR(_B); } /* XOR B */ +OP(op,a9) { XOR(_C); } /* XOR C */ +OP(op,aa) { XOR(_D); } /* XOR D */ +OP(op,ab) { XOR(_E); } /* XOR E */ +OP(op,ac) { XOR(_H); } /* XOR H */ +OP(op,ad) { XOR(_L); } /* XOR L */ +OP(op,ae) { XOR(RM(_HL)); } /* XOR (HL) */ +OP(op,af) { XOR(_A); } /* XOR A */ + +OP(op,b0) { OR(_B); } /* OR B */ +OP(op,b1) { OR(_C); } /* OR C */ +OP(op,b2) { OR(_D); } /* OR D */ +OP(op,b3) { OR(_E); } /* OR E */ +OP(op,b4) { OR(_H); } /* OR H */ +OP(op,b5) { OR(_L); } /* OR L */ +OP(op,b6) { OR(RM(_HL)); } /* OR (HL) */ +OP(op,b7) { OR(_A); } /* OR A */ + +OP(op,b8) { CP(_B); } /* CP B */ +OP(op,b9) { CP(_C); } /* CP C */ +OP(op,ba) { CP(_D); } /* CP D */ +OP(op,bb) { CP(_E); } /* CP E */ +OP(op,bc) { CP(_H); } /* CP H */ +OP(op,bd) { CP(_L); } /* CP L */ +OP(op,be) { CP(RM(_HL)); } /* CP (HL) */ +OP(op,bf) { CP(_A); } /* CP A */ + +OP(op,c0) { RET_COND( !(_F & ZF), 0xc0 ); } /* RET NZ */ +OP(op,c1) { POP(BC); } /* POP BC */ +OP(op,c2) { JP_COND( !(_F & ZF) ); } /* JP NZ,a */ +OP(op,c3) { JP; } /* JP a */ +OP(op,c4) { CALL_COND( !(_F & ZF), 0xc4 ); } /* CALL NZ,a */ +OP(op,c5) { PUSH( BC ); } /* PUSH BC */ +OP(op,c6) { ADD(ARG()); } /* ADD A,n */ +OP(op,c7) { RST(0x00); } /* RST 0 */ + +OP(op,c8) { RET_COND( _F & ZF, 0xc8 ); } /* RET Z */ +OP(op,c9) { POP(PC); } /* RET */ +OP(op,ca) { JP_COND( _F & ZF ); } /* JP Z,a */ +OP(op,cb) { _R++; EXEC(cb,ROP()); } /* **** CB xx */ +OP(op,cc) { CALL_COND( _F & ZF, 0xcc ); } /* CALL Z,a */ +OP(op,cd) { CALL(); } /* CALL a */ +OP(op,ce) { ADC(ARG()); } /* ADC A,n */ +OP(op,cf) { RST(0x08); } /* RST 1 */ + +OP(op,d0) { RET_COND( !(_F & CF), 0xd0 ); } /* RET NC */ +OP(op,d1) { POP(DE); } /* POP DE */ +OP(op,d2) { JP_COND( !(_F & CF) ); } /* JP NC,a */ +OP(op,d3) { unsigned n = ARG() | (_A << 8); OUT( n, _A ); } /* OUT (n),A */ +OP(op,d4) { CALL_COND( !(_F & CF), 0xd4 ); } /* CALL NC,a */ +OP(op,d5) { PUSH( DE ); } /* PUSH DE */ +OP(op,d6) { SUB(ARG()); } /* SUB n */ +OP(op,d7) { RST(0x10); } /* RST 2 */ + +OP(op,d8) { RET_COND( _F & CF, 0xd8 ); } /* RET C */ +OP(op,d9) { EXX; } /* EXX */ +OP(op,da) { JP_COND( _F & CF ); } /* JP C,a */ +OP(op,db) { unsigned n = ARG() | (_A << 8); _A = IN( n ); } /* IN A,(n) */ +OP(op,dc) { CALL_COND( _F & CF, 0xdc ); } /* CALL C,a */ +OP(op,dd) { _R++; EXEC(dd,ROP()); } /* **** DD xx */ +OP(op,de) { SBC(ARG()); } /* SBC A,n */ +OP(op,df) { RST(0x18); } /* RST 3 */ + +OP(op,e0) { RET_COND( !(_F & PF), 0xe0 ); } /* RET PO */ +OP(op,e1) { POP(HL); } /* POP HL */ +OP(op,e2) { JP_COND( !(_F & PF) ); } /* JP PO,a */ +OP(op,e3) { EXSP(HL); } /* EX HL,(SP) */ +OP(op,e4) { CALL_COND( !(_F & PF), 0xe4 ); } /* CALL PO,a */ +OP(op,e5) { PUSH( HL ); } /* PUSH HL */ +OP(op,e6) { AND(ARG()); } /* AND n */ +OP(op,e7) { RST(0x20); } /* RST 4 */ + +OP(op,e8) { RET_COND( _F & PF, 0xe8 ); } /* RET PE */ +OP(op,e9) { _PC = _HL; } /* JP (HL) */ +OP(op,ea) { JP_COND( _F & PF ); } /* JP PE,a */ +OP(op,eb) { EX_DE_HL; } /* EX DE,HL */ +OP(op,ec) { CALL_COND( _F & PF, 0xec ); } /* CALL PE,a */ +OP(op,ed) { _R++; EXEC(ed,ROP()); } /* **** ED xx */ +OP(op,ee) { XOR(ARG()); } /* XOR n */ +OP(op,ef) { RST(0x28); } /* RST 5 */ + +OP(op,f0) { RET_COND( !(_F & SF), 0xf0 ); } /* RET P */ +OP(op,f1) { POP(AF); } /* POP AF */ +OP(op,f2) { JP_COND( !(_F & SF) ); } /* JP P,a */ +OP(op,f3) { _IFF1 = _IFF2 = 0; } /* DI */ +OP(op,f4) { CALL_COND( !(_F & SF), 0xf4 ); } /* CALL P,a */ +OP(op,f5) { PUSH( AF ); } /* PUSH AF */ +OP(op,f6) { OR(ARG()); } /* OR n */ +OP(op,f7) { RST(0x30); } /* RST 6 */ + +OP(op,f8) { RET_COND( _F & SF, 0xf8 ); } /* RET M */ +OP(op,f9) { _SP = _HL; } /* LD SP,HL */ +OP(op,fa) { JP_COND(_F & SF); } /* JP M,a */ +OP(op,fb) { EI; } /* EI */ +OP(op,fc) { CALL_COND( _F & SF, 0xfc ); } /* CALL M,a */ +OP(op,fd) { _R++; EXEC(fd,ROP()); } /* **** FD xx */ +OP(op,fe) { CP(ARG()); } /* CP n */ +OP(op,ff) { RST(0x38); } /* RST 7 */ + + +static void take_interrupt(void) +{ + if( _IFF1 ) + { + int irq_vector; + + /* there isn't a valid previous program counter */ + _PPC = -1; + + /* Check if processor was halted */ + LEAVE_HALT; + + if( Z80.irq_max ) /* daisy chain mode */ + { + if( Z80.request_irq >= 0 ) + { + /* Clear both interrupt flip flops */ + _IFF1 = _IFF2 = 0; + irq_vector = Z80.irq[Z80.request_irq].interrupt_entry(Z80.irq[Z80.request_irq].irq_param); + Z80.request_irq = -1; + } else return; + } + else + { + /* Clear both interrupt flip flops */ + _IFF1 = _IFF2 = 0; + /* call back the cpu interface to retrieve the vector */ + irq_vector = (*Z80.irq_callback)(0); + } + + /* Interrupt mode 2. Call [Z80.I:databyte] */ + if( _IM == 2 ) + { + irq_vector = (irq_vector & 0xff) | (_I << 8); + PUSH( PC ); + RM16( irq_vector, &Z80.PC ); + /* CALL opcode timing */ + Z80.extra_cycles += cc[Z80_TABLE_op][0xcd]; + } + else + /* Interrupt mode 1. RST 38h */ + if( _IM == 1 ) + { + PUSH( PC ); + _PCD = 0x0038; + /* RST $38 + 'interrupt latency' cycles */ + Z80.extra_cycles += cc[Z80_TABLE_op][0xff] + cc[Z80_TABLE_ex][0xff]; + } + else + { + /* Interrupt mode 0. We check for CALL and JP instructions, */ + /* if neither of these were found we assume a 1 byte opcode */ + /* was placed on the databus */ + switch (irq_vector & 0xff0000) + { + case 0xcd0000: /* call */ + PUSH( PC ); + _PCD = irq_vector & 0xffff; + /* CALL $xxxx + 'interrupt latency' cycles */ + Z80.extra_cycles += cc[Z80_TABLE_op][0xcd] + cc[Z80_TABLE_ex][0xff]; + break; + case 0xc30000: /* jump */ + _PCD = irq_vector & 0xffff; + /* JP $xxxx + 2 cycles */ + Z80.extra_cycles += cc[Z80_TABLE_op][0xc3] + cc[Z80_TABLE_ex][0xff]; + break; + default: /* rst (or other opcodes?) */ + PUSH( PC ); + _PCD = irq_vector & 0x0038; + /* RST $xx + 2 cycles */ + Z80.extra_cycles += cc[Z80_TABLE_op][_PCD] + cc[Z80_TABLE_ex][_PCD]; + break; + } + } + } +} + +/**************************************************************************** + * Reset registers to their initial values + ****************************************************************************/ +void z80_reset(void *param) +{ + Z80_DaisyChain *daisy_chain = (Z80_DaisyChain *)param; + int i, p; +#if BIG_FLAGS_ARRAY + if( !SZHVC_add || !SZHVC_sub ) + { + int oldval, newval, val; + UINT8 *padd, *padc, *psub, *psbc; + /* allocate big flag arrays once */ + SZHVC_add = (UINT8 *)genmalloc(2*256*256); + SZHVC_sub = (UINT8 *)genmalloc(2*256*256); + if( !SZHVC_add || !SZHVC_sub ) + { + LOG(("Z80: failed to allocate 2 * 128K flags arrays!!!\n")); +// raise(SIGABRT); + } + padd = &SZHVC_add[ 0*256]; + padc = &SZHVC_add[256*256]; + psub = &SZHVC_sub[ 0*256]; + psbc = &SZHVC_sub[256*256]; + for (oldval = 0; oldval < 256; oldval++) + { + for (newval = 0; newval < 256; newval++) + { + /* add or adc w/o carry set */ + val = newval - oldval; + *padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF; +#if Z80_EXACT + *padd |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF; + if( newval < oldval ) *padd |= CF; + if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF; + padd++; + + /* adc with carry set */ + val = newval - oldval - 1; + *padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF; +#if Z80_EXACT + *padc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF; + if( newval <= oldval ) *padc |= CF; + if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF; + padc++; + + /* cp, sub or sbc w/o carry set */ + val = oldval - newval; + *psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF); +#if Z80_EXACT + *psub |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF; + if( newval > oldval ) *psub |= CF; + if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF; + psub++; + + /* sbc with carry set */ + val = oldval - newval - 1; + *psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF); +#if Z80_EXACT + *psbc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF; + if( newval >= oldval ) *psbc |= CF; + if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF; + psbc++; + } + } + } +#endif + for (i = 0; i < 256; i++) + { + p = 0; + if( i&0x01 ) ++p; + if( i&0x02 ) ++p; + if( i&0x04 ) ++p; + if( i&0x08 ) ++p; + if( i&0x10 ) ++p; + if( i&0x20 ) ++p; + if( i&0x40 ) ++p; + if( i&0x80 ) ++p; + SZ[i] = i ? i & SF : ZF; +#if Z80_EXACT + SZ[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + SZ_BIT[i] = i ? i & SF : ZF | PF; +#if Z80_EXACT + SZ_BIT[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + SZP[i] = SZ[i] | ((p & 1) ? 0 : PF); + SZHV_inc[i] = SZ[i]; + if( i == 0x80 ) SZHV_inc[i] |= VF; + if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF; + SZHV_dec[i] = SZ[i] | NF; + if( i == 0x7f ) SZHV_dec[i] |= VF; + if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF; + } + + memset(&Z80, 0, sizeof(Z80)); + _IX = _IY = 0xffff; /* IX and IY are FFFF after a reset! */ + _F = ZF; /* Zero flag is set */ + Z80.request_irq = -1; + Z80.service_irq = -1; + Z80.nmi_state = CLEAR_LINE; + Z80.irq_state = CLEAR_LINE; + + if( daisy_chain ) + { + while( daisy_chain->irq_param != -1 && Z80.irq_max < Z80_MAXDAISY ) + { + /* set callbackhandler after reti */ + Z80.irq[Z80.irq_max] = *daisy_chain; + /* device reset */ + if( Z80.irq[Z80.irq_max].reset ) + Z80.irq[Z80.irq_max].reset(Z80.irq[Z80.irq_max].irq_param); + Z80.irq_max++; + daisy_chain++; + } + } + +} + +void z80_exit(void) +{ +#if BIG_FLAGS_ARRAY + if (SZHVC_add) genfree(SZHVC_add); + SZHVC_add = NULL; + if (SZHVC_sub) genfree(SZHVC_sub); + SZHVC_sub = NULL; +#endif +} + +void z80_end_timeslice(void) +{ + z80_ICount = 0; +} + +/**************************************************************************** + * Execute 'cycles' T-states. Return number of T-states really executed + ****************************************************************************/ +int z80_execute(int cycles) +{ + z80_ICount = cycles - Z80.extra_cycles; + Z80.extra_cycles = 0; + + do + { + _PPC = _PCD; + _R++; + EXEC_INLINE(op,ROP()); + } while( z80_ICount > 0 ); + + z80_ICount -= Z80.extra_cycles; + Z80.extra_cycles = 0; + + return cycles - z80_ICount; +} + +/**************************************************************************** + * Burn 'cycles' T-states. Adjust R register for the lost time + ****************************************************************************/ +void z80_burn(int cycles) +{ + if( cycles > 0 ) + { + /* NOP takes 4 cycles per instruction */ + int n = (cycles + 3) / 4; + _R += n; + z80_ICount -= 4 * n; + } +} + +/**************************************************************************** + * Get all registers in given buffer + ****************************************************************************/ +unsigned z80_get_context (void *dst) +{ + if( dst ) + *(Z80_Regs*)dst = Z80; + return sizeof(Z80_Regs); +} + +/**************************************************************************** + * Set all registers to given values + ****************************************************************************/ +void z80_set_context (void *src) +{ + if( src ) + Z80 = *(Z80_Regs*)src; +} + +/**************************************************************************** + * Get a pointer to a cycle count table + ****************************************************************************/ +void *z80_get_cycle_table (int which) +{ + if (which >= 0 && which <= Z80_TABLE_xycb) + return cc[which]; + return NULL; +} + +/**************************************************************************** + * Set a new cycle count table + ****************************************************************************/ +void z80_set_cycle_table (int which, void *new_table) +{ + if (which >= 0 && which <= Z80_TABLE_ex) + cc[which] = new_table; +} + +/**************************************************************************** + * Return program counter + ****************************************************************************/ +unsigned z80_get_pc (void) +{ + return _PCD; +} + +/**************************************************************************** + * Set program counter + ****************************************************************************/ +void z80_set_pc (unsigned val) +{ + _PC = val; +} + +/**************************************************************************** + * Return stack pointer + ****************************************************************************/ +unsigned z80_get_sp (void) +{ + return _SPD; +} + +/**************************************************************************** + * Set stack pointer + ****************************************************************************/ +void z80_set_sp (unsigned val) +{ + _SP = val; +} + +/**************************************************************************** + * Return a specific register + ****************************************************************************/ +unsigned z80_get_reg (int regnum) +{ + switch( regnum ) + { + case Z80_PC: return Z80.PC.w.l; + case Z80_SP: return Z80.SP.w.l; + case Z80_AF: return Z80.AF.w.l; + case Z80_BC: return Z80.BC.w.l; + case Z80_DE: return Z80.DE.w.l; + case Z80_HL: return Z80.HL.w.l; + case Z80_IX: return Z80.IX.w.l; + case Z80_IY: return Z80.IY.w.l; + case Z80_R: return (Z80.R & 0x7f) | (Z80.R2 & 0x80); + case Z80_I: return Z80.I; + case Z80_AF2: return Z80.AF2.w.l; + case Z80_BC2: return Z80.BC2.w.l; + case Z80_DE2: return Z80.DE2.w.l; + case Z80_HL2: return Z80.HL2.w.l; + case Z80_IM: return Z80.IM; + case Z80_IFF1: return Z80.IFF1; + case Z80_IFF2: return Z80.IFF2; + case Z80_HALT: return Z80.HALT; + case Z80_NMI_STATE: return Z80.nmi_state; + case Z80_IRQ_STATE: return Z80.irq_state; + case Z80_DC0: return Z80.int_state[0]; + case Z80_DC1: return Z80.int_state[1]; + case Z80_DC2: return Z80.int_state[2]; + case Z80_DC3: return Z80.int_state[3]; + case REG_PREVIOUSPC: return Z80.PREPC.w.l; + default: + if( regnum <= REG_SP_CONTENTS ) + { + unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum); + if( offset < 0xffff ) + return RM( offset ) | ( RM( offset + 1) << 8 ); + } + } + return 0; +} + +/**************************************************************************** + * Set a specific register + ****************************************************************************/ +void z80_set_reg (int regnum, unsigned val) +{ + switch( regnum ) + { + case Z80_PC: Z80.PC.w.l = val; break; + case Z80_SP: Z80.SP.w.l = val; break; + case Z80_AF: Z80.AF.w.l = val; break; + case Z80_BC: Z80.BC.w.l = val; break; + case Z80_DE: Z80.DE.w.l = val; break; + case Z80_HL: Z80.HL.w.l = val; break; + case Z80_IX: Z80.IX.w.l = val; break; + case Z80_IY: Z80.IY.w.l = val; break; + case Z80_R: Z80.R = val; Z80.R2 = val & 0x80; break; + case Z80_I: Z80.I = val; break; + case Z80_AF2: Z80.AF2.w.l = val; break; + case Z80_BC2: Z80.BC2.w.l = val; break; + case Z80_DE2: Z80.DE2.w.l = val; break; + case Z80_HL2: Z80.HL2.w.l = val; break; + case Z80_IM: Z80.IM = val; break; + case Z80_IFF1: Z80.IFF1 = val; break; + case Z80_IFF2: Z80.IFF2 = val; break; + case Z80_HALT: Z80.HALT = val; break; + case Z80_NMI_STATE: z80_set_nmi_line(val); break; + case Z80_IRQ_STATE: z80_set_irq_line(0,val); break; + case Z80_DC0: Z80.int_state[0] = val; break; + case Z80_DC1: Z80.int_state[1] = val; break; + case Z80_DC2: Z80.int_state[2] = val; break; + case Z80_DC3: Z80.int_state[3] = val; break; + default: + if( regnum <= REG_SP_CONTENTS ) + { + unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum); + if( offset < 0xffff ) + { + WM( offset, val & 0xff ); + WM( offset+1, (val >> 8) & 0xff ); + } + } + } +} + +/**************************************************************************** + * Set NMI line state + ****************************************************************************/ +void z80_set_nmi_line(int state) +{ + if( Z80.nmi_state == state ) return; + + Z80.nmi_state = state; + if( state == CLEAR_LINE ) return; + + _PPC = -1; /* there isn't a valid previous program counter */ + LEAVE_HALT; /* Check if processor was halted */ + + _IFF1 = 0; + PUSH( PC ); + _PCD = 0x0066; + Z80.extra_cycles += 11; +} + +/**************************************************************************** + * Set IRQ line state + ****************************************************************************/ +void z80_set_irq_line(int irqline, int state) +{ + Z80.irq_state = state; + if( state == CLEAR_LINE ) return; + + if( Z80.irq_max ) + { + int daisychain, device, int_state; + daisychain = (*Z80.irq_callback)(irqline); + daisychain = 0xFF; + device = daisychain >> 8; + int_state = daisychain & 0xff; + + if( Z80.int_state[device] != int_state ) + { + LOG((" change\n")); + /* set new interrupt status */ + Z80.int_state[device] = int_state; + /* check interrupt status */ + Z80.request_irq = Z80.service_irq = -1; + + /* search higher IRQ or IEO */ + for( device = 0 ; device < Z80.irq_max ; device ++ ) + { + /* IEO = disable ? */ + if( Z80.int_state[device] & Z80_INT_IEO ) + { + Z80.request_irq = -1; /* if IEO is disable , masking lower IRQ */ + Z80.service_irq = device; /* set highest interrupt service device */ + } + /* IRQ = request ? */ + if( Z80.int_state[device] & Z80_INT_REQ ) + Z80.request_irq = device; + } + if( Z80.request_irq < 0 ) return; + } + else + { + LOG((" no change\n")); + return; + } + } + take_interrupt(); +} + +/**************************************************************************** + * Set IRQ vector callback + ****************************************************************************/ +void z80_set_irq_callback(int (*callback)(int)) +{ + Z80.irq_callback = callback; +} + +#if 0 +/**************************************************************************** + * Save CPU state + ****************************************************************************/ +void z80_state_save(void *file) +{ + int cpu = cpu_getactivecpu(); + state_save_UINT16(file, "z80", cpu, "AF", &Z80.AF.w.l, 1); + state_save_UINT16(file, "z80", cpu, "BC", &Z80.BC.w.l, 1); + state_save_UINT16(file, "z80", cpu, "DE", &Z80.DE.w.l, 1); + state_save_UINT16(file, "z80", cpu, "HL", &Z80.HL.w.l, 1); + state_save_UINT16(file, "z80", cpu, "IX", &Z80.IX.w.l, 1); + state_save_UINT16(file, "z80", cpu, "IY", &Z80.IY.w.l, 1); + state_save_UINT16(file, "z80", cpu, "PC", &Z80.PC.w.l, 1); + state_save_UINT16(file, "z80", cpu, "SP", &Z80.SP.w.l, 1); + state_save_UINT16(file, "z80", cpu, "AF2", &Z80.AF2.w.l, 1); + state_save_UINT16(file, "z80", cpu, "BC2", &Z80.BC2.w.l, 1); + state_save_UINT16(file, "z80", cpu, "DE2", &Z80.DE2.w.l, 1); + state_save_UINT16(file, "z80", cpu, "HL2", &Z80.HL2.w.l, 1); + state_save_UINT8(file, "z80", cpu, "R", &Z80.R, 1); + state_save_UINT8(file, "z80", cpu, "R2", &Z80.R2, 1); + state_save_UINT8(file, "z80", cpu, "IFF1", &Z80.IFF1, 1); + state_save_UINT8(file, "z80", cpu, "IFF2", &Z80.IFF2, 1); + state_save_UINT8(file, "z80", cpu, "HALT", &Z80.HALT, 1); + state_save_UINT8(file, "z80", cpu, "IM", &Z80.IM, 1); + state_save_UINT8(file, "z80", cpu, "I", &Z80.I, 1); + state_save_UINT8(file, "z80", cpu, "irq_max", &Z80.irq_max, 1); + state_save_INT8(file, "z80", cpu, "request_irq", &Z80.request_irq, 1); + state_save_INT8(file, "z80", cpu, "service_irq", &Z80.service_irq, 1); + state_save_UINT8(file, "z80", cpu, "int_state", Z80.int_state, 4); + state_save_UINT8(file, "z80", cpu, "nmi_state", &Z80.nmi_state, 1); + state_save_UINT8(file, "z80", cpu, "irq_state", &Z80.irq_state, 1); + /* daisy chain needs to be saved by z80ctc.c somehow */ +} + +/**************************************************************************** + * Load CPU state + ****************************************************************************/ +void z80_state_load(void *file) +{ + int cpu = cpu_getactivecpu(); + state_load_UINT16(file, "z80", cpu, "AF", &Z80.AF.w.l, 1); + state_load_UINT16(file, "z80", cpu, "BC", &Z80.BC.w.l, 1); + state_load_UINT16(file, "z80", cpu, "DE", &Z80.DE.w.l, 1); + state_load_UINT16(file, "z80", cpu, "HL", &Z80.HL.w.l, 1); + state_load_UINT16(file, "z80", cpu, "IX", &Z80.IX.w.l, 1); + state_load_UINT16(file, "z80", cpu, "IY", &Z80.IY.w.l, 1); + state_load_UINT16(file, "z80", cpu, "PC", &Z80.PC.w.l, 1); + state_load_UINT16(file, "z80", cpu, "SP", &Z80.SP.w.l, 1); + state_load_UINT16(file, "z80", cpu, "AF2", &Z80.AF2.w.l, 1); + state_load_UINT16(file, "z80", cpu, "BC2", &Z80.BC2.w.l, 1); + state_load_UINT16(file, "z80", cpu, "DE2", &Z80.DE2.w.l, 1); + state_load_UINT16(file, "z80", cpu, "HL2", &Z80.HL2.w.l, 1); + state_load_UINT8(file, "z80", cpu, "R", &Z80.R, 1); + state_load_UINT8(file, "z80", cpu, "R2", &Z80.R2, 1); + state_load_UINT8(file, "z80", cpu, "IFF1", &Z80.IFF1, 1); + state_load_UINT8(file, "z80", cpu, "IFF2", &Z80.IFF2, 1); + state_load_UINT8(file, "z80", cpu, "HALT", &Z80.HALT, 1); + state_load_UINT8(file, "z80", cpu, "IM", &Z80.IM, 1); + state_load_UINT8(file, "z80", cpu, "I", &Z80.I, 1); + state_load_UINT8(file, "z80", cpu, "irq_max", &Z80.irq_max, 1); + state_load_INT8(file, "z80", cpu, "request_irq", &Z80.request_irq, 1); + state_load_INT8(file, "z80", cpu, "service_irq", &Z80.service_irq, 1); + state_load_UINT8(file, "z80", cpu, "int_state", Z80.int_state, 4); + state_load_UINT8(file, "z80", cpu, "nmi_state", &Z80.nmi_state, 1); + state_load_UINT8(file, "z80", cpu, "irq_state", &Z80.irq_state, 1); + /* daisy chain needs to be restored by z80ctc.c somehow */ +} + +/**************************************************************************** + * Return a formatted string for a register + ****************************************************************************/ +const char *z80_info(void *context, int regnum) +{ + static char buffer[32][47+1]; + static int which = 0; + Z80_Regs *r = context; + + which = ++which % 32; + buffer[which][0] = '\0'; + if( !context ) + r = &Z80; + + switch( regnum ) + { + case CPU_INFO_REG+Z80_PC: sprintf(buffer[which], "PC:%04X", r->PC.w.l); break; + case CPU_INFO_REG+Z80_SP: sprintf(buffer[which], "SP:%04X", r->SP.w.l); break; + case CPU_INFO_REG+Z80_AF: sprintf(buffer[which], "AF:%04X", r->AF.w.l); break; + case CPU_INFO_REG+Z80_BC: sprintf(buffer[which], "BC:%04X", r->BC.w.l); break; + case CPU_INFO_REG+Z80_DE: sprintf(buffer[which], "DE:%04X", r->DE.w.l); break; + case CPU_INFO_REG+Z80_HL: sprintf(buffer[which], "HL:%04X", r->HL.w.l); break; + case CPU_INFO_REG+Z80_IX: sprintf(buffer[which], "IX:%04X", r->IX.w.l); break; + case CPU_INFO_REG+Z80_IY: sprintf(buffer[which], "IY:%04X", r->IY.w.l); break; + case CPU_INFO_REG+Z80_R: sprintf(buffer[which], "R:%02X", (r->R & 0x7f) | (r->R2 & 0x80)); break; + case CPU_INFO_REG+Z80_I: sprintf(buffer[which], "I:%02X", r->I); break; + case CPU_INFO_REG+Z80_AF2: sprintf(buffer[which], "AF'%04X", r->AF2.w.l); break; + case CPU_INFO_REG+Z80_BC2: sprintf(buffer[which], "BC'%04X", r->BC2.w.l); break; + case CPU_INFO_REG+Z80_DE2: sprintf(buffer[which], "DE'%04X", r->DE2.w.l); break; + case CPU_INFO_REG+Z80_HL2: sprintf(buffer[which], "HL'%04X", r->HL2.w.l); break; + case CPU_INFO_REG+Z80_IM: sprintf(buffer[which], "IM:%X", r->IM); break; + case CPU_INFO_REG+Z80_IFF1: sprintf(buffer[which], "IFF1:%X", r->IFF1); break; + case CPU_INFO_REG+Z80_IFF2: sprintf(buffer[which], "IFF2:%X", r->IFF2); break; + case CPU_INFO_REG+Z80_HALT: sprintf(buffer[which], "HALT:%X", r->HALT); break; + case CPU_INFO_REG+Z80_NMI_STATE: sprintf(buffer[which], "NMI:%X", r->nmi_state); break; + case CPU_INFO_REG+Z80_IRQ_STATE: sprintf(buffer[which], "IRQ:%X", r->irq_state); break; + case CPU_INFO_REG+Z80_DC0: if(Z80.irq_max >= 1) sprintf(buffer[which], "DC0:%X", r->int_state[0]); break; + case CPU_INFO_REG+Z80_DC1: if(Z80.irq_max >= 2) sprintf(buffer[which], "DC1:%X", r->int_state[1]); break; + case CPU_INFO_REG+Z80_DC2: if(Z80.irq_max >= 3) sprintf(buffer[which], "DC2:%X", r->int_state[2]); break; + case CPU_INFO_REG+Z80_DC3: if(Z80.irq_max >= 4) sprintf(buffer[which], "DC3:%X", r->int_state[3]); break; + case CPU_INFO_FLAGS: + sprintf(buffer[which], "%c%c%c%c%c%c%c%c", + r->AF.b.l & 0x80 ? 'S':'.', + r->AF.b.l & 0x40 ? 'Z':'.', + r->AF.b.l & 0x20 ? '5':'.', + r->AF.b.l & 0x10 ? 'H':'.', + r->AF.b.l & 0x08 ? '3':'.', + r->AF.b.l & 0x04 ? 'P':'.', + r->AF.b.l & 0x02 ? 'N':'.', + r->AF.b.l & 0x01 ? 'C':'.'); + break; + case CPU_INFO_NAME: return "Z80"; + case CPU_INFO_FAMILY: return "Zilog Z80"; + case CPU_INFO_VERSION: return "3.2"; + case CPU_INFO_FILE: return __FILE__; + case CPU_INFO_CREDITS: return "Copyright (C) 1998,1999 Juergen Buchmueller, all rights reserved."; + case CPU_INFO_REG_LAYOUT: return (const char *)z80_reg_layout; + case CPU_INFO_WIN_LAYOUT: return (const char *)z80_win_layout; + } + return buffer[which]; +} + +unsigned z80_dasm( char *buffer, unsigned pc ) +{ +#ifdef MAME_DEBUG + return DasmZ80( buffer, pc ); +#else + sprintf( buffer, "$%02X", cpu_readop(pc) ); + return 1; +#endif +} +#endif diff --git a/MCUME_teensy/teensygen/z80.h b/MCUME_teensy/teensygen/z80.h new file mode 100644 index 0000000..a29c1b9 --- /dev/null +++ b/MCUME_teensy/teensygen/z80.h @@ -0,0 +1,62 @@ +#ifndef Z80_H +#define Z80_H + +#include "cpuintrf.h" +#include "osd_cpu.h" + +enum { + Z80_PC=1, Z80_SP, Z80_AF, Z80_BC, Z80_DE, Z80_HL, + Z80_IX, Z80_IY, Z80_AF2, Z80_BC2, Z80_DE2, Z80_HL2, + Z80_R, Z80_I, Z80_IM, Z80_IFF1, Z80_IFF2, Z80_HALT, + Z80_NMI_STATE, Z80_IRQ_STATE, Z80_DC0, Z80_DC1, Z80_DC2, Z80_DC3 +}; + +enum { + Z80_TABLE_op, + Z80_TABLE_cb, + Z80_TABLE_ed, + Z80_TABLE_xy, + Z80_TABLE_xycb, + Z80_TABLE_ex /* cycles counts for taken jr/jp/call and interrupt latency (rst opcodes) */ +}; + +extern int z80_ICount; /* T-state count */ + +#define Z80_IGNORE_INT -1 /* Ignore interrupt */ +#define Z80_NMI_INT -2 /* Execute NMI */ +#define Z80_IRQ_INT -1000 /* Execute IRQ */ + +extern void z80_reset (void *param); +extern void z80_exit (void); +extern void z80_end_timeslice(void); +extern int z80_execute(int cycles); +extern void z80_burn(int cycles); +extern unsigned z80_get_context (void *dst); +extern void z80_set_context (void *src); +extern void *z80_get_cycle_table (int which); +extern void z80_set_cycle_table (int which, void *new_tbl); +extern unsigned z80_get_pc (void); +extern void z80_set_pc (unsigned val); +extern unsigned z80_get_sp (void); +extern void z80_set_sp (unsigned val); +extern unsigned z80_get_reg (int regnum); +extern void z80_set_reg (int regnum, unsigned val); +extern void z80_set_nmi_line(int state); +extern void z80_set_irq_line(int irqline, int state); +extern void z80_set_irq_callback(int (*irq_callback)(int)); +extern void z80_state_save(void *file); +extern void z80_state_load(void *file); +extern const char *z80_info(void *context, int regnum); +extern unsigned z80_dasm(char *buffer, unsigned pc); + +#ifdef MAME_DEBUG +extern unsigned DasmZ80(char *buffer, unsigned pc); +#endif + +unsigned int cpu_readport16(unsigned int port); +void cpu_writeport16(unsigned int port, unsigned int data); +unsigned int cpu_readmem16(unsigned int address); +void cpu_writemem16(unsigned int address, unsigned int data); + +#endif + diff --git a/MCUME_teensy/teensygen/z80daa.h b/MCUME_teensy/teensygen/z80daa.h new file mode 100644 index 0000000..2dd7225 --- /dev/null +++ b/MCUME_teensy/teensygen/z80daa.h @@ -0,0 +1,2053 @@ +#include "arduinoproto.h" + +PROGMEM static UINT16 DAATable[0x800] = { + (0x00<<8) +ZF +VF , + (0x01<<8) , + (0x02<<8) , + (0x03<<8) +VF , + (0x04<<8) , + (0x05<<8) +VF , + (0x06<<8) +VF , + (0x07<<8) , + (0x08<<8) +XF , + (0x09<<8) +XF+VF , + (0x10<<8) +HF , + (0x11<<8) +HF +VF , + (0x12<<8) +HF +VF , + (0x13<<8) +HF , + (0x14<<8) +HF +VF , + (0x15<<8) +HF , + (0x10<<8) , + (0x11<<8) +VF , + (0x12<<8) +VF , + (0x13<<8) , + (0x14<<8) +VF , + (0x15<<8) , + (0x16<<8) , + (0x17<<8) +VF , + (0x18<<8) +XF+VF , + (0x19<<8) +XF , + (0x20<<8) +YF+HF , + (0x21<<8) +YF+HF +VF , + (0x22<<8) +YF+HF +VF , + (0x23<<8) +YF+HF , + (0x24<<8) +YF+HF +VF , + (0x25<<8) +YF+HF , + (0x20<<8) +YF , + (0x21<<8) +YF +VF , + (0x22<<8) +YF +VF , + (0x23<<8) +YF , + (0x24<<8) +YF +VF , + (0x25<<8) +YF , + (0x26<<8) +YF , + (0x27<<8) +YF +VF , + (0x28<<8) +YF +XF+VF , + (0x29<<8) +YF +XF , + (0x30<<8) +YF+HF +VF , + (0x31<<8) +YF+HF , + (0x32<<8) +YF+HF , + (0x33<<8) +YF+HF +VF , + (0x34<<8) +YF+HF , + (0x35<<8) +YF+HF +VF , + (0x30<<8) +YF +VF , + (0x31<<8) +YF , + (0x32<<8) +YF , + (0x33<<8) +YF +VF , + (0x34<<8) +YF , + (0x35<<8) +YF +VF , + (0x36<<8) +YF +VF , + (0x37<<8) +YF , + (0x38<<8) +YF +XF , + (0x39<<8) +YF +XF+VF , + (0x40<<8) +HF , + (0x41<<8) +HF +VF , + (0x42<<8) +HF +VF , + (0x43<<8) +HF , + (0x44<<8) +HF +VF , + (0x45<<8) +HF , + (0x40<<8) , + (0x41<<8) +VF , + (0x42<<8) +VF , + (0x43<<8) , + (0x44<<8) +VF , + (0x45<<8) , + (0x46<<8) , + (0x47<<8) +VF , + (0x48<<8) +XF+VF , + (0x49<<8) +XF , + (0x50<<8) +HF +VF , + (0x51<<8) +HF , + (0x52<<8) +HF , + (0x53<<8) +HF +VF , + (0x54<<8) +HF , + (0x55<<8) +HF +VF , + (0x50<<8) +VF , + (0x51<<8) , + (0x52<<8) , + (0x53<<8) +VF , + (0x54<<8) , + (0x55<<8) +VF , + (0x56<<8) +VF , + (0x57<<8) , + (0x58<<8) +XF , + (0x59<<8) +XF+VF , + (0x60<<8) +YF+HF +VF , + (0x61<<8) +YF+HF , + (0x62<<8) +YF+HF , + (0x63<<8) +YF+HF +VF , + (0x64<<8) +YF+HF , + (0x65<<8) +YF+HF +VF , + (0x60<<8) +YF +VF , + (0x61<<8) +YF , + (0x62<<8) +YF , + (0x63<<8) +YF +VF , + (0x64<<8) +YF , + (0x65<<8) +YF +VF , + (0x66<<8) +YF +VF , + (0x67<<8) +YF , + (0x68<<8) +YF +XF , + (0x69<<8) +YF +XF+VF , + (0x70<<8) +YF+HF , + (0x71<<8) +YF+HF +VF , + (0x72<<8) +YF+HF +VF , + (0x73<<8) +YF+HF , + (0x74<<8) +YF+HF +VF , + (0x75<<8) +YF+HF , + (0x70<<8) +YF , + (0x71<<8) +YF +VF , + (0x72<<8) +YF +VF , + (0x73<<8) +YF , + (0x74<<8) +YF +VF , + (0x75<<8) +YF , + (0x76<<8) +YF , + (0x77<<8) +YF +VF , + (0x78<<8) +YF +XF+VF , + (0x79<<8) +YF +XF , + (0x80<<8)+SF +HF , + (0x81<<8)+SF +HF +VF , + (0x82<<8)+SF +HF +VF , + (0x83<<8)+SF +HF , + (0x84<<8)+SF +HF +VF , + (0x85<<8)+SF +HF , + (0x80<<8)+SF , + (0x81<<8)+SF +VF , + (0x82<<8)+SF +VF , + (0x83<<8)+SF , + (0x84<<8)+SF +VF , + (0x85<<8)+SF , + (0x86<<8)+SF , + (0x87<<8)+SF +VF , + (0x88<<8)+SF +XF+VF , + (0x89<<8)+SF +XF , + (0x90<<8)+SF +HF +VF , + (0x91<<8)+SF +HF , + (0x92<<8)+SF +HF , + (0x93<<8)+SF +HF +VF , + (0x94<<8)+SF +HF , + (0x95<<8)+SF +HF +VF , + (0x90<<8)+SF +VF , + (0x91<<8)+SF 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(0x4B<<8) +HF+XF+VF+NF+CF, + (0x4C<<8) +HF+XF +NF+CF, + (0x4D<<8) +HF+XF+VF+NF+CF, + (0x4E<<8) +HF+XF+VF+NF+CF, + (0x4F<<8) +HF+XF +NF+CF, + (0x50<<8) +VF+NF+CF, + (0x51<<8) +NF+CF, + (0x52<<8) +NF+CF, + (0x53<<8) +VF+NF+CF, + (0x54<<8) +NF+CF, + (0x55<<8) +VF+NF+CF, + (0x56<<8) +VF+NF+CF, + (0x57<<8) +NF+CF, + (0x58<<8) +XF +NF+CF, + (0x59<<8) +XF+VF+NF+CF, + (0x5A<<8) +HF+XF+VF+NF+CF, + (0x5B<<8) +HF+XF +NF+CF, + (0x5C<<8) +HF+XF+VF+NF+CF, + (0x5D<<8) +HF+XF +NF+CF, + (0x5E<<8) +HF+XF +NF+CF, + (0x5F<<8) +HF+XF+VF+NF+CF, + (0x60<<8) +YF +VF+NF+CF, + (0x61<<8) +YF +NF+CF, + (0x62<<8) +YF +NF+CF, + (0x63<<8) +YF +VF+NF+CF, + (0x64<<8) +YF +NF+CF, + (0x65<<8) +YF +VF+NF+CF, + (0x66<<8) +YF +VF+NF+CF, + (0x67<<8) +YF +NF+CF, + (0x68<<8) +YF +XF +NF+CF, + (0x69<<8) +YF +XF+VF+NF+CF, + (0x6A<<8) +YF+HF+XF+VF+NF+CF, + (0x6B<<8) +YF+HF+XF +NF+CF, + (0x6C<<8) +YF+HF+XF+VF+NF+CF, + (0x6D<<8) +YF+HF+XF +NF+CF, + (0x6E<<8) +YF+HF+XF +NF+CF, + (0x6F<<8) +YF+HF+XF+VF+NF+CF, + (0x70<<8) +YF +NF+CF, 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+VF+NF+CF, + (0x96<<8)+SF +VF+NF+CF, + (0x97<<8)+SF +NF+CF, + (0x98<<8)+SF +XF +NF+CF, + (0x99<<8)+SF +XF+VF+NF+CF, + (0x9A<<8)+SF +HF+XF+VF+NF+CF, + (0x9B<<8)+SF +HF+XF +NF+CF, + (0x9C<<8)+SF +HF+XF+VF+NF+CF, + (0x9D<<8)+SF +HF+XF +NF+CF, + (0x9E<<8)+SF +HF+XF +NF+CF, + (0x9F<<8)+SF +HF+XF+VF+NF+CF, + (0xA0<<8)+SF +YF +VF+NF+CF, + (0xA1<<8)+SF +YF +NF+CF, + (0xA2<<8)+SF +YF +NF+CF, + (0xA3<<8)+SF +YF +VF+NF+CF, + (0xA4<<8)+SF +YF +NF+CF, + (0xA5<<8)+SF +YF +VF+NF+CF, + (0xA6<<8)+SF +YF +VF+NF+CF, + (0xA7<<8)+SF +YF +NF+CF, + (0xA8<<8)+SF +YF +XF +NF+CF, + (0xA9<<8)+SF +YF +XF+VF+NF+CF, + (0xAA<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xAB<<8)+SF +YF+HF+XF +NF+CF, + (0xAC<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xAD<<8)+SF +YF+HF+XF +NF+CF, + (0xAE<<8)+SF +YF+HF+XF +NF+CF, + (0xAF<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xB0<<8)+SF +YF +NF+CF, + (0xB1<<8)+SF +YF +VF+NF+CF, + (0xB2<<8)+SF +YF +VF+NF+CF, + (0xB3<<8)+SF +YF +NF+CF, + (0xB4<<8)+SF +YF +VF+NF+CF, + (0xB5<<8)+SF +YF +NF+CF, + (0xB6<<8)+SF +YF +NF+CF, + (0xB7<<8)+SF +YF +VF+NF+CF, + (0xB8<<8)+SF +YF +XF+VF+NF+CF, + (0xB9<<8)+SF +YF +XF +NF+CF, + (0xBA<<8)+SF +YF+HF+XF +NF+CF, + (0xBB<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xBC<<8)+SF +YF+HF+XF +NF+CF, + (0xBD<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xBE<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xBF<<8)+SF +YF+HF+XF +NF+CF, + (0xC0<<8)+SF +VF+NF+CF, + (0xC1<<8)+SF +NF+CF, + (0xC2<<8)+SF +NF+CF, + (0xC3<<8)+SF +VF+NF+CF, + (0xC4<<8)+SF +NF+CF, + (0xC5<<8)+SF +VF+NF+CF, + (0xC6<<8)+SF +VF+NF+CF, + (0xC7<<8)+SF +NF+CF, + (0xC8<<8)+SF +XF +NF+CF, + (0xC9<<8)+SF +XF+VF+NF+CF, + (0xCA<<8)+SF +HF+XF+VF+NF+CF, + (0xCB<<8)+SF +HF+XF +NF+CF, + (0xCC<<8)+SF +HF+XF+VF+NF+CF, + (0xCD<<8)+SF +HF+XF +NF+CF, + (0xCE<<8)+SF +HF+XF +NF+CF, + (0xCF<<8)+SF +HF+XF+VF+NF+CF, + (0xD0<<8)+SF +NF+CF, + (0xD1<<8)+SF +VF+NF+CF, + (0xD2<<8)+SF +VF+NF+CF, + (0xD3<<8)+SF +NF+CF, + (0xD4<<8)+SF +VF+NF+CF, + (0xD5<<8)+SF +NF+CF, + (0xD6<<8)+SF +NF+CF, + (0xD7<<8)+SF +VF+NF+CF, + (0xD8<<8)+SF +XF+VF+NF+CF, + (0xD9<<8)+SF +XF +NF+CF, + (0xDA<<8)+SF +HF+XF +NF+CF, + (0xDB<<8)+SF +HF+XF+VF+NF+CF, + (0xDC<<8)+SF +HF+XF +NF+CF, + (0xDD<<8)+SF +HF+XF+VF+NF+CF, + (0xDE<<8)+SF +HF+XF+VF+NF+CF, + (0xDF<<8)+SF +HF+XF +NF+CF, + (0xE0<<8)+SF +YF +NF+CF, + (0xE1<<8)+SF +YF +VF+NF+CF, + (0xE2<<8)+SF +YF +VF+NF+CF, + (0xE3<<8)+SF +YF +NF+CF, + (0xE4<<8)+SF +YF +VF+NF+CF, + (0xE5<<8)+SF +YF +NF+CF, + (0xE6<<8)+SF +YF +NF+CF, + (0xE7<<8)+SF +YF +VF+NF+CF, + (0xE8<<8)+SF +YF +XF+VF+NF+CF, + (0xE9<<8)+SF +YF +XF +NF+CF, + (0xEA<<8)+SF +YF+HF+XF +NF+CF, + (0xEB<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xEC<<8)+SF +YF+HF+XF +NF+CF, + (0xED<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xEE<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xEF<<8)+SF +YF+HF+XF +NF+CF, + (0xF0<<8)+SF +YF +VF+NF+CF, + (0xF1<<8)+SF +YF +NF+CF, + (0xF2<<8)+SF +YF +NF+CF, + (0xF3<<8)+SF +YF +VF+NF+CF, + (0xF4<<8)+SF +YF +NF+CF, + (0xF5<<8)+SF +YF +VF+NF+CF, + (0xF6<<8)+SF +YF +VF+NF+CF, + (0xF7<<8)+SF +YF +NF+CF, + (0xF8<<8)+SF +YF +XF +NF+CF, + (0xF9<<8)+SF +YF +XF+VF+NF+CF, + (0xFA<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xFB<<8)+SF +YF+HF+XF +NF+CF, + (0xFC<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xFD<<8)+SF +YF+HF+XF +NF+CF, + (0xFE<<8)+SF +YF+HF+XF +NF+CF, + (0xFF<<8)+SF +YF+HF+XF+VF+NF+CF, + (0x00<<8) +ZF +VF+NF+CF, + (0x01<<8) +NF+CF, + (0x02<<8) +NF+CF, + (0x03<<8) +VF+NF+CF, + (0x04<<8) +NF+CF, + (0x05<<8) +VF+NF+CF, + (0x06<<8) +VF+NF+CF, + (0x07<<8) +NF+CF, + (0x08<<8) +XF +NF+CF, + (0x09<<8) +XF+VF+NF+CF, + (0x0A<<8) +HF+XF+VF+NF+CF, + (0x0B<<8) +HF+XF +NF+CF, + (0x0C<<8) +HF+XF+VF+NF+CF, + (0x0D<<8) +HF+XF +NF+CF, + (0x0E<<8) +HF+XF +NF+CF, + (0x0F<<8) +HF+XF+VF+NF+CF, + (0x10<<8) +NF+CF, + (0x11<<8) +VF+NF+CF, + (0x12<<8) +VF+NF+CF, + (0x13<<8) +NF+CF, + (0x14<<8) +VF+NF+CF, + (0x15<<8) +NF+CF, + (0x16<<8) +NF+CF, + (0x17<<8) +VF+NF+CF, + (0x18<<8) +XF+VF+NF+CF, + (0x19<<8) +XF +NF+CF, + (0x1A<<8) +HF+XF +NF+CF, + (0x1B<<8) +HF+XF+VF+NF+CF, + (0x1C<<8) +HF+XF +NF+CF, + (0x1D<<8) +HF+XF+VF+NF+CF, + (0x1E<<8) +HF+XF+VF+NF+CF, + (0x1F<<8) +HF+XF +NF+CF, + (0x20<<8) +YF +NF+CF, + (0x21<<8) +YF +VF+NF+CF, + (0x22<<8) +YF +VF+NF+CF, + (0x23<<8) +YF +NF+CF, + (0x24<<8) +YF +VF+NF+CF, + (0x25<<8) +YF +NF+CF, + (0x26<<8) +YF +NF+CF, + (0x27<<8) +YF +VF+NF+CF, + (0x28<<8) +YF +XF+VF+NF+CF, + (0x29<<8) +YF +XF +NF+CF, + (0x2A<<8) +YF+HF+XF +NF+CF, + (0x2B<<8) +YF+HF+XF+VF+NF+CF, + (0x2C<<8) +YF+HF+XF +NF+CF, + (0x2D<<8) +YF+HF+XF+VF+NF+CF, + (0x2E<<8) +YF+HF+XF+VF+NF+CF, + (0x2F<<8) +YF+HF+XF +NF+CF, + (0x30<<8) +YF +VF+NF+CF, + (0x31<<8) +YF +NF+CF, + (0x32<<8) +YF +NF+CF, + (0x33<<8) +YF +VF+NF+CF, + (0x34<<8) +YF +NF+CF, + (0x35<<8) +YF +VF+NF+CF, + (0x36<<8) +YF +VF+NF+CF, + (0x37<<8) +YF +NF+CF, + (0x38<<8) +YF +XF +NF+CF, + (0x39<<8) +YF +XF+VF+NF+CF, + (0x3A<<8) +YF+HF+XF+VF+NF+CF, + (0x3B<<8) +YF+HF+XF +NF+CF, + (0x3C<<8) +YF+HF+XF+VF+NF+CF, + (0x3D<<8) +YF+HF+XF +NF+CF, + (0x3E<<8) +YF+HF+XF +NF+CF, + (0x3F<<8) +YF+HF+XF+VF+NF+CF, + (0x40<<8) +NF+CF, + (0x41<<8) +VF+NF+CF, + (0x42<<8) +VF+NF+CF, + (0x43<<8) +NF+CF, + (0x44<<8) +VF+NF+CF, + (0x45<<8) +NF+CF, + (0x46<<8) +NF+CF, + (0x47<<8) +VF+NF+CF, + (0x48<<8) +XF+VF+NF+CF, + (0x49<<8) +XF +NF+CF, + (0x4A<<8) +HF+XF +NF+CF, + (0x4B<<8) +HF+XF+VF+NF+CF, + (0x4C<<8) +HF+XF +NF+CF, + (0x4D<<8) +HF+XF+VF+NF+CF, + (0x4E<<8) +HF+XF+VF+NF+CF, + (0x4F<<8) +HF+XF +NF+CF, + (0x50<<8) +VF+NF+CF, + (0x51<<8) +NF+CF, + (0x52<<8) +NF+CF, + (0x53<<8) +VF+NF+CF, + (0x54<<8) +NF+CF, + (0x55<<8) +VF+NF+CF, + (0x56<<8) +VF+NF+CF, + (0x57<<8) +NF+CF, + (0x58<<8) +XF +NF+CF, + (0x59<<8) +XF+VF+NF+CF, + (0x5A<<8) +HF+XF+VF+NF+CF, + (0x5B<<8) +HF+XF +NF+CF, + (0x5C<<8) +HF+XF+VF+NF+CF, + (0x5D<<8) +HF+XF +NF+CF, + (0x5E<<8) +HF+XF +NF+CF, + (0x5F<<8) +HF+XF+VF+NF+CF, + (0x60<<8) +YF +VF+NF+CF, + (0x61<<8) +YF +NF+CF, + (0x62<<8) +YF +NF+CF, + (0x63<<8) +YF +VF+NF+CF, + (0x64<<8) +YF +NF+CF, + (0x65<<8) +YF +VF+NF+CF, + (0x66<<8) +YF +VF+NF+CF, + (0x67<<8) +YF +NF+CF, + (0x68<<8) +YF +XF +NF+CF, + (0x69<<8) +YF +XF+VF+NF+CF, + (0x6A<<8) +YF+HF+XF+VF+NF+CF, + (0x6B<<8) +YF+HF+XF +NF+CF, + (0x6C<<8) +YF+HF+XF+VF+NF+CF, + (0x6D<<8) +YF+HF+XF +NF+CF, + (0x6E<<8) +YF+HF+XF +NF+CF, + (0x6F<<8) +YF+HF+XF+VF+NF+CF, + (0x70<<8) +YF +NF+CF, + (0x71<<8) +YF +VF+NF+CF, + (0x72<<8) +YF +VF+NF+CF, + (0x73<<8) +YF +NF+CF, + (0x74<<8) +YF +VF+NF+CF, + (0x75<<8) +YF +NF+CF, + (0x76<<8) +YF +NF+CF, + (0x77<<8) +YF +VF+NF+CF, + (0x78<<8) +YF +XF+VF+NF+CF, + (0x79<<8) +YF +XF +NF+CF, + (0x7A<<8) +YF+HF+XF +NF+CF, + (0x7B<<8) +YF+HF+XF+VF+NF+CF, + (0x7C<<8) +YF+HF+XF +NF+CF, + (0x7D<<8) +YF+HF+XF+VF+NF+CF, + (0x7E<<8) +YF+HF+XF+VF+NF+CF, + (0x7F<<8) +YF+HF+XF +NF+CF, + (0x80<<8)+SF +NF+CF, + (0x81<<8)+SF +VF+NF+CF, + (0x82<<8)+SF +VF+NF+CF, + (0x83<<8)+SF +NF+CF, + (0x84<<8)+SF +VF+NF+CF, + (0x85<<8)+SF +NF+CF, + (0x86<<8)+SF +NF+CF, + (0x87<<8)+SF +VF+NF+CF, + (0x88<<8)+SF +XF+VF+NF+CF, + (0x89<<8)+SF +XF +NF+CF, + (0x8A<<8)+SF +HF+XF +NF+CF, + (0x8B<<8)+SF +HF+XF+VF+NF+CF, + (0x8C<<8)+SF +HF+XF +NF+CF, + (0x8D<<8)+SF +HF+XF+VF+NF+CF, + (0x8E<<8)+SF +HF+XF+VF+NF+CF, + (0x8F<<8)+SF +HF+XF +NF+CF, + (0x90<<8)+SF +VF+NF+CF, + (0x91<<8)+SF +NF+CF, + (0x92<<8)+SF +NF+CF, + (0x93<<8)+SF +VF+NF+CF, + (0x94<<8)+SF +NF+CF, + (0x95<<8)+SF +VF+NF+CF, + (0x96<<8)+SF +VF+NF+CF, + (0x97<<8)+SF +NF+CF, + (0x98<<8)+SF +XF +NF+CF, + (0x99<<8)+SF +XF+VF+NF+CF +}; + diff --git a/MCUME_teensy/teensygnuboy/AudioPlaySystem.cpp b/MCUME_teensy/teensygnuboy/AudioPlaySystem.cpp new file mode 100644 index 0000000..cdcd71b --- /dev/null +++ b/MCUME_teensy/teensygnuboy/AudioPlaySystem.cpp @@ -0,0 +1,196 @@ +#include "emuapi.h" + +#ifdef HAS_SND + +#include "AudioPlaySystem.h" +#include +#define SAMPLERATE AUDIO_SAMPLE_RATE_EXACT +#define CLOCKFREQ 985248 + +#ifndef CUSTOM_SND +PROGMEM static const short square[]={ +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +}; + +PROGMEM const short noise[] { +-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,-32767,-32767, +32767,-32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,-32767, +32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767, +32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767, +}; + +#define NOISEBSIZE 0x100 + +typedef struct +{ + unsigned int spos; + unsigned int sinc; + unsigned int vol; +} Channel; + +static Channel chan[6] = { + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} }; + +#endif + +volatile bool playing = false; + + + + +PROGMEM static void snd_Reset(void) +{ +#ifndef CUSTOM_SND + chan[0].vol = 0; + chan[1].vol = 0; + chan[2].vol = 0; + chan[3].vol = 0; + chan[4].vol = 0; + chan[5].vol = 0; + chan[0].sinc = 0; + chan[1].sinc = 0; + chan[2].sinc = 0; + chan[3].sinc = 0; + chan[4].sinc = 0; + chan[5].sinc = 0; +#endif +} + + +#ifdef CUSTOM_SND +void SND_Process(void *sndbuffer, int sndn); +#endif + +PROGMEM static void snd_Mixer(short * stream, int len ) +{ + if (playing) + { +#ifdef CUSTOM_SND + SND_Process((void*)stream, len); +#else + int i; + long s; + len = len >> 1; + + short v0=chan[0].vol; + short v1=chan[1].vol; + short v2=chan[2].vol; + short v3=chan[3].vol; + short v4=chan[4].vol; + short v5=chan[5].vol; + for (i=0;i>8)&0x3f])>>11); + s+=((v1*square[(chan[1].spos>>8)&0x3f])>>11); + s+=((v2*square[(chan[2].spos>>8)&0x3f])>>11); + s+=((v3*noise[(chan[3].spos>>8)&(NOISEBSIZE-1)])>>11); + s+=((v4*noise[(chan[4].spos>>8)&(NOISEBSIZE-1)])>>11); + s+=((v5*noise[(chan[5].spos>>8)&(NOISEBSIZE-1)])>>11); + *stream++ = (short)(s); + *stream++ = (short)(s); + chan[0].spos += chan[0].sinc; + chan[1].spos += chan[1].sinc; + chan[2].spos += chan[2].sinc; + chan[3].spos += chan[3].sinc; + chan[4].spos += chan[4].sinc; + chan[5].spos += chan[5].sinc; + } +#endif + } +} + +PROGMEM void AudioPlaySystem::begin(void) +{ + //emu_printf("AudioPlaySystem constructor"); + this->reset(); + setSampleParameters(CLOCKFREQ, SAMPLERATE); +} + +PROGMEM void AudioPlaySystem::start(void) +{ + //emu_printf("allocating sound buf"); + playing = true; +} + +PROGMEM void AudioPlaySystem::setSampleParameters(float clockfreq, float samplerate) { +} + +PROGMEM void AudioPlaySystem::reset(void) +{ + snd_Reset(); +} + +PROGMEM void AudioPlaySystem::stop(void) +{ + //__disable_irq(); + playing = false; + //__enable_irq(); +} + +PROGMEM bool AudioPlaySystem::isPlaying(void) +{ + return playing; +} + +PROGMEM void AudioPlaySystem::update(void) { + audio_block_t *block; + + // only update if we're playing + if (!playing) return; + + // allocate the audio blocks to transmit + block = allocate(); + if (block == NULL) return; + + snd_Mixer((short*)block->data,AUDIO_BLOCK_SAMPLES); + //memset( (void*)block->data, 0, AUDIO_BLOCK_SAMPLES*2); + + transmit(block); + release(block); +} + +PROGMEM void AudioPlaySystem::sound(int C, int F, int V) { +#ifndef CUSTOM_SND + if (C < 6) { + chan[C].vol = V; + chan[C].sinc = F>>1; + } +#endif +} + +PROGMEM void AudioPlaySystem::step(void) { +} +#endif + diff --git a/MCUME_teensy/teensygnuboy/AudioPlaySystem.h b/MCUME_teensy/teensygnuboy/AudioPlaySystem.h new file mode 100644 index 0000000..0333adb --- /dev/null +++ b/MCUME_teensy/teensygnuboy/AudioPlaySystem.h @@ -0,0 +1,28 @@ +#ifndef audioplaysystem_h_ +#define audioplaysystem_h_ + +#ifdef HAS_SND + +#include + +class AudioPlaySystem : public AudioStream +{ +public: + AudioPlaySystem(void) : AudioStream(0, NULL) { begin(); } + void begin(void); + void setSampleParameters(float clockfreq, float samplerate); + void reset(void); + void start(void); + void stop(void); + bool isPlaying(void); + void sound(int C, int F, int V); + void buzz(int size, int val); + void step(void); + +private: + virtual void update(void); +}; +#endif + +#endif + diff --git a/MCUME_teensy/teensygnuboy/arduinoproto.h b/MCUME_teensy/teensygnuboy/arduinoproto.h new file mode 100644 index 0000000..289030c --- /dev/null +++ b/MCUME_teensy/teensygnuboy/arduinoproto.h @@ -0,0 +1,7 @@ +#ifndef _ARDUINOPROTO_H_ +#define _ARDUINOPROTO_H_ + +#include +//#define PROGMEM + +#endif diff --git a/MCUME_teensy/teensygnuboy/cpu.c b/MCUME_teensy/teensygnuboy/cpu.c new file mode 100644 index 0000000..6f2a362 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/cpu.c @@ -0,0 +1,877 @@ +#include "defs.h" +#include "regs.h" +#include "hw.h" +#include "cpu.h" +#include "mem.h" +#include "cpuregs.h" +#include "cpucore.h" + +#ifdef USE_ASM +#include "asm.h" +#endif + + +struct cpu cpu; + + + + +#define ZFLAG(n) ( (n) ? 0 : FZ ) + + +#define PUSH(w) ( (SP -= 2), (writew(xSP, (w))) ) +#define POP(w) ( ((w) = readw(xSP)), (SP += 2) ) + + +//#define FETCH_OLD ( mbc.rmap[PC>>12] \ +//? mbc.rmap[PC>>12][PC++] \ +//: mem_read(PC++) ) + +#define FETCH (readb(PC++)) + + +#define INC(r) { ((r)++); \ +F = (F & (FL|FC)) | incflag_table[(r)]; } + +#define DEC(r) { ((r)--); \ +F = (F & (FL|FC)) | decflag_table[(r)]; } + +#define INCW(r) ( (r)++ ) + +#define DECW(r) ( (r)-- ) + +#define ADD(n) { \ +W(acc) = (un16)A + (un16)(n); \ +F = (ZFLAG(LB(acc))) \ +| (FH & ((A ^ (n) ^ LB(acc)) << 1)) \ +| (HB(acc) << 4); \ +A = LB(acc); } + +#define ADC(n) { \ +W(acc) = (un16)A + (un16)(n) + (un16)((F&FC)>>4); \ +F = (ZFLAG(LB(acc))) \ +| (FH & ((A ^ (n) ^ LB(acc)) << 1)) \ +| (HB(acc) << 4); \ +A = LB(acc); } + +#define ADDW(n) { \ +DW(acc) = (un32)HL + (un32)(n); \ +F = (F & (FZ)) \ +| (FH & ((H ^ ((n)>>8) ^ HB(acc)) << 1)) \ +| (acc.b[HI][LO] << 4); \ +HL = W(acc); } + +#define ADDSP(n) { \ +DW(acc) = (un32)SP + (un32)(n8)(n); \ +F = (FH & (((SP>>8) ^ ((n)>>8) ^ HB(acc)) << 1)) \ +| (acc.b[HI][LO] << 4); \ +SP = W(acc); } + +#define LDHLSP(n) { \ +DW(acc) = (un32)SP + (un32)(n8)(n); \ +F = (FH & (((SP>>8) ^ ((n)>>8) ^ HB(acc)) << 1)) \ +| (acc.b[HI][LO] << 4); \ +HL = W(acc); } + +#define CP(n) { \ +W(acc) = (un16)A - (un16)(n); \ +F = FN \ +| (ZFLAG(LB(acc))) \ +| (FH & ((A ^ (n) ^ LB(acc)) << 1)) \ +| ((un8)(-(n8)HB(acc)) << 4); } + +#define SUB(n) { CP((n)); A = LB(acc); } + +#define SBC(n) { \ +W(acc) = (un16)A - (un16)(n) - (un16)((F&FC)>>4); \ +F = FN \ +| (ZFLAG((n8)LB(acc))) \ +| (FH & ((A ^ (n) ^ LB(acc)) << 1)) \ +| ((un8)(-(n8)HB(acc)) << 4); \ +A = LB(acc); } + +#define AND(n) { A &= (n); \ +F = ZFLAG(A) | FH; } + +#define XOR(n) { A ^= (n); \ +F = ZFLAG(A); } + +#define OR(n) { A |= (n); \ +F = ZFLAG(A); } + +#define RLCA(r) { (r) = ((r)>>7) | ((r)<<1); \ +F = (((r)&0x01)<<4); } + +#define RRCA(r) { (r) = ((r)<<7) | ((r)>>1); \ +F = (((r)&0x80)>>3); } + +#define RLA(r) { \ +LB(acc) = (((r)&0x80)>>3); \ +(r) = ((r)<<1) | ((F&FC)>>4); \ +F = LB(acc); } + +#define RRA(r) { \ +LB(acc) = (((r)&0x01)<<4); \ +(r) = ((r)>>1) | ((F&FC)<<3); \ +F = LB(acc); } + +#define RLC(r) { RLCA(r); F |= ZFLAG(r); } +#define RRC(r) { RRCA(r); F |= ZFLAG(r); } +#define RL(r) { RLA(r); F |= ZFLAG(r); } +#define RR(r) { RRA(r); F |= ZFLAG(r); } + +#define SLA(r) { \ +LB(acc) = (((r)&0x80)>>3); \ +(r) <<= 1; \ +F = ZFLAG((r)) | LB(acc); } + +#define SRA(r) { \ +LB(acc) = (((r)&0x01)<<4); \ +(r) = (un8)(((n8)(r))>>1); \ +F = ZFLAG((r)) | LB(acc); } + +#define SRL(r) { \ +LB(acc) = (((r)&0x01)<<4); \ +(r) >>= 1; \ +F = ZFLAG((r)) | LB(acc); } + +#define CPL(r) { \ +(r) = ~(r); \ +F |= (FH|FN); } + +#define SCF { F = (F & (FZ)) | FC; } + +#define CCF { F = (F & (FZ|FC)) ^ FC; } + +#define DAA { \ +A += (LB(acc) = daa_table[((((int)F)&0x70)<<4) | A]); \ +F = (F & (FN)) | ZFLAG(A) | daa_carry_table[LB(acc)>>2]; } + +#define SWAP(r) { \ +(r) = swap_table[(r)]; \ +F = ZFLAG((r)); } + +#define BIT(n,r) { F = (F & FC) | ZFLAG(((r) & (1 << (n)))) | FH; } +#define RES(n,r) { (r) &= ~(1 << (n)); } +#define SET(n,r) { (r) |= (1 << (n)); } + +#define CB_REG_CASES(r, n) \ +case 0x00|(n): RLC(r); break; \ +case 0x08|(n): RRC(r); break; \ +case 0x10|(n): RL(r); break; \ +case 0x18|(n): RR(r); break; \ +case 0x20|(n): SLA(r); break; \ +case 0x28|(n): SRA(r); break; \ +case 0x30|(n): SWAP(r); break; \ +case 0x38|(n): SRL(r); break; \ +case 0x40|(n): BIT(0, r); break; \ +case 0x48|(n): BIT(1, r); break; \ +case 0x50|(n): BIT(2, r); break; \ +case 0x58|(n): BIT(3, r); break; \ +case 0x60|(n): BIT(4, r); break; \ +case 0x68|(n): BIT(5, r); break; \ +case 0x70|(n): BIT(6, r); break; \ +case 0x78|(n): BIT(7, r); break; \ +case 0x80|(n): RES(0, r); break; \ +case 0x88|(n): RES(1, r); break; \ +case 0x90|(n): RES(2, r); break; \ +case 0x98|(n): RES(3, r); break; \ +case 0xA0|(n): RES(4, r); break; \ +case 0xA8|(n): RES(5, r); break; \ +case 0xB0|(n): RES(6, r); break; \ +case 0xB8|(n): RES(7, r); break; \ +case 0xC0|(n): SET(0, r); break; \ +case 0xC8|(n): SET(1, r); break; \ +case 0xD0|(n): SET(2, r); break; \ +case 0xD8|(n): SET(3, r); break; \ +case 0xE0|(n): SET(4, r); break; \ +case 0xE8|(n): SET(5, r); break; \ +case 0xF0|(n): SET(6, r); break; \ +case 0xF8|(n): SET(7, r); break; + + +#define ALU_CASES(base, imm, op, label) \ +case (imm): b = FETCH; goto label; \ +case (base): b = B; goto label; \ +case (base)+1: b = C; goto label; \ +case (base)+2: b = D; goto label; \ +case (base)+3: b = E; goto label; \ +case (base)+4: b = H; goto label; \ +case (base)+5: b = L; goto label; \ +case (base)+6: b = readb(HL); goto label; \ +case (base)+7: b = A; \ +label: op(b); break; + + + + + + + + +#define JR ( PC += 1+(n8)readb(PC) ) +#define JP ( PC = readw(PC) ) + +#define CALL ( PUSH(PC+2), JP ) + +#define NOJR ( clen--, PC++ ) +#define NOJP ( clen--, PC+=2 ) +#define NOCALL ( clen-=3, PC+=2 ) +#define NORET ( clen-=3 ) + +#define RST(n) { PUSH(PC); PC = (n); } + +#define RET ( POP(PC) ) + +#define EI ( IMA = 1 ) +#define DI ( cpu.halt = IMA = IME = 0 ) + + + +#define PRE_INT ( DI, PUSH(PC) ) +#define THROW_INT(n) ( (IF &= ~(1<<(n))), (PC = 0x40+((n)<<3)) ) + + + + +void cpu_reset() +{ + cpu.speed = 0; + cpu.halt = 0; + cpu.div = 0; + cpu.tim = 0; + cpu.lcdc = 40; + + IME = 0; + IMA = 0; + + PC = 0x0100; + SP = 0xFFFE; + AF = 0x01B0; + BC = 0x0013; + DE = 0x00D8; + HL = 0x014D; + + if (hw.cgb) A = 0x11; + if (hw.gba) B = 0x01; +} + + +void div_advance(int cnt) +{ + cpu.div += (cnt<<1); + if (cpu.div >= 256) + { + R_DIV += (cpu.div >> 8); + cpu.div &= 0xff; + } +} + +void timer_advance(int cnt) +{ + int unit, tima; + + if (!(R_TAC & 0x04)) return; + + unit = ((-R_TAC) & 3) << 1; + cpu.tim += (cnt<= 512) + { + tima = R_TIMA + (cpu.tim >> 9); + cpu.tim &= 0x1ff; + if (tima >= 256) + { + hw_interrupt(IF_TIMER, IF_TIMER); + hw_interrupt(0, IF_TIMER); + } + while (tima >= 256) + tima = tima - 256 + R_TMA; + R_TIMA = tima; + } +} + +void lcdc_advance(int cnt) +{ + cpu.lcdc -= cnt; + if (cpu.lcdc <= 0) lcdc_trans(); +} + +void sound_advance(int cnt) +{ + cpu.snd += cnt; +} + +void cpu_timers(int cnt) +{ + div_advance(cnt << cpu.speed); + timer_advance(cnt << cpu.speed); + lcdc_advance(cnt); + sound_advance(cnt); +} + +int cpu_idle(int max) +{ + int cnt, unit; + + if (!(cpu.halt && IME)) return 0; + if (R_IF & R_IE) + { + cpu.halt = 0; + return 0; + } + + /* Make sure we don't miss lcdc status events! */ + if ((R_IE & (IF_VBLANK | IF_STAT)) && (max > cpu.lcdc)) + max = cpu.lcdc; + + /* If timer interrupt cannot happen, this is very simple! */ + if (!((R_IE & IF_TIMER) && (R_TAC & 0x04))) + { + cpu_timers(max); + return max; + } + + /* Figure out when the next timer interrupt will happen */ + unit = ((-R_TAC) & 3) << 1; + cnt = (511 - cpu.tim + (1<> unit; + cnt += (255 - R_TIMA) << (9 - unit); + + if (max < cnt) + cnt = max; + + cpu_timers(cnt); + return cnt; +} + +#ifndef ASM_CPU_EMULATE + +#ifdef DEBUG +extern int debug_trace; +#endif + +int cpu_emulate(int cycles) +{ + int i; + byte op, cbop; + int clen; + static union reg acc; + static byte b; + static word w; + + + i = cycles; +next: + if ((clen = cpu_idle(i))) + { + i -= clen; + if (i > 0) goto next; + return cycles-i; + } + + if (IME && (IF & IE)) + { + PRE_INT; + switch ((byte)(IF & IE)) + { + case 0x01: case 0x03: case 0x05: case 0x07: + case 0x09: case 0x0B: case 0x0D: case 0x0F: + case 0x11: case 0x13: case 0x15: case 0x17: + case 0x19: case 0x1B: case 0x1D: case 0x1F: + THROW_INT(0); break; + case 0x02: case 0x06: case 0x0A: case 0x0E: + case 0x12: case 0x16: case 0x1A: case 0x1E: + THROW_INT(1); break; + case 0x04: case 0x0C: case 0x14: case 0x1C: + THROW_INT(2); break; + case 0x08: case 0x18: + THROW_INT(3); break; + case 0x10: + THROW_INT(4); break; + } + } + IME = IMA; +#ifdef DEBUG + if (debug_trace) debug_disassemble(PC, 1); +#endif + op = FETCH; + clen = cycles_table[op]; + + switch(op) + { + case 0x00: /* NOP */ + case 0x40: /* LD B,B */ + case 0x49: /* LD C,C */ + case 0x52: /* LD D,D */ + case 0x5B: /* LD E,E */ + case 0x64: /* LD H,H */ + case 0x6D: /* LD L,L */ + case 0x7F: /* LD A,A */ + break; + + case 0x41: /* LD B,C */ + B = C; break; + case 0x42: /* LD B,D */ + B = D; break; + case 0x43: /* LD B,E */ + B = E; break; + case 0x44: /* LD B,H */ + B = H; break; + case 0x45: /* LD B,L */ + B = L; break; + case 0x46: /* LD B,(HL) */ + B = readb(xHL); break; + case 0x47: /* LD B,A */ + B = A; break; + + case 0x48: /* LD C,B */ + C = B; break; + case 0x4A: /* LD C,D */ + C = D; break; + case 0x4B: /* LD C,E */ + C = E; break; + case 0x4C: /* LD C,H */ + C = H; break; + case 0x4D: /* LD C,L */ + C = L; break; + case 0x4E: /* LD C,(HL) */ + C = readb(xHL); break; + case 0x4F: /* LD C,A */ + C = A; break; + + case 0x50: /* LD D,B */ + D = B; break; + case 0x51: /* LD D,C */ + D = C; break; + case 0x53: /* LD D,E */ + D = E; break; + case 0x54: /* LD D,H */ + D = H; break; + case 0x55: /* LD D,L */ + D = L; break; + case 0x56: /* LD D,(HL) */ + D = readb(xHL); break; + case 0x57: /* LD D,A */ + D = A; break; + + case 0x58: /* LD E,B */ + E = B; break; + case 0x59: /* LD E,C */ + E = C; break; + case 0x5A: /* LD E,D */ + E = D; break; + case 0x5C: /* LD E,H */ + E = H; break; + case 0x5D: /* LD E,L */ + E = L; break; + case 0x5E: /* LD E,(HL) */ + E = readb(xHL); break; + case 0x5F: /* LD E,A */ + E = A; break; + + case 0x60: /* LD H,B */ + H = B; break; + case 0x61: /* LD H,C */ + H = C; break; + case 0x62: /* LD H,D */ + H = D; break; + case 0x63: /* LD H,E */ + H = E; break; + case 0x65: /* LD H,L */ + H = L; break; + case 0x66: /* LD H,(HL) */ + H = readb(xHL); break; + case 0x67: /* LD H,A */ + H = A; break; + + case 0x68: /* LD L,B */ + L = B; break; + case 0x69: /* LD L,C */ + L = C; break; + case 0x6A: /* LD L,D */ + L = D; break; + case 0x6B: /* LD L,E */ + L = E; break; + case 0x6C: /* LD L,H */ + L = H; break; + case 0x6E: /* LD L,(HL) */ + L = readb(xHL); break; + case 0x6F: /* LD L,A */ + L = A; break; + + case 0x70: /* LD (HL),B */ + b = B; goto __LD_HL; + case 0x71: /* LD (HL),C */ + b = C; goto __LD_HL; + case 0x72: /* LD (HL),D */ + b = D; goto __LD_HL; + case 0x73: /* LD (HL),E */ + b = E; goto __LD_HL; + case 0x74: /* LD (HL),H */ + b = H; goto __LD_HL; + case 0x75: /* LD (HL),L */ + b = L; goto __LD_HL; + case 0x77: /* LD (HL),A */ + b = A; + __LD_HL: + writeb(xHL,b); + break; + + case 0x78: /* LD A,B */ + A = B; break; + case 0x79: /* LD A,C */ + A = C; break; + case 0x7A: /* LD A,D */ + A = D; break; + case 0x7B: /* LD A,E */ + A = E; break; + case 0x7C: /* LD A,H */ + A = H; break; + case 0x7D: /* LD A,L */ + A = L; break; + case 0x7E: /* LD A,(HL) */ + A = readb(xHL); break; + + case 0x01: /* LD BC,imm */ + BC = readw(xPC); PC += 2; break; + case 0x11: /* LD DE,imm */ + DE = readw(xPC); PC += 2; break; + case 0x21: /* LD HL,imm */ + HL = readw(xPC); PC += 2; break; + case 0x31: /* LD SP,imm */ + SP = readw(xPC); PC += 2; break; + + case 0x02: /* LD (BC),A */ + writeb(xBC, A); break; + case 0x0A: /* LD A,(BC) */ + A = readb(xBC); break; + case 0x12: /* LD (DE),A */ + writeb(xDE, A); break; + case 0x1A: /* LD A,(DE) */ + A = readb(xDE); break; + + case 0x22: /* LDI (HL),A */ + writeb(xHL, A); HL++; break; + case 0x2A: /* LDI A,(HL) */ + A = readb(xHL); HL++; break; + case 0x32: /* LDD (HL),A */ + writeb(xHL, A); HL--; break; + case 0x3A: /* LDD A,(HL) */ + A = readb(xHL); HL--; break; + + case 0x06: /* LD B,imm */ + B = FETCH; break; + case 0x0E: /* LD C,imm */ + C = FETCH; break; + case 0x16: /* LD D,imm */ + D = FETCH; break; + case 0x1E: /* LD E,imm */ + E = FETCH; break; + case 0x26: /* LD H,imm */ + H = FETCH; break; + case 0x2E: /* LD L,imm */ + L = FETCH; break; + case 0x36: /* LD (HL),imm */ + b = FETCH; writeb(xHL, b); break; + case 0x3E: /* LD A,imm */ + A = FETCH; break; + + case 0x08: /* LD (imm),SP */ + writew(readw(xPC), SP); PC += 2; break; + case 0xEA: /* LD (imm),A */ + writeb(readw(xPC), A); PC += 2; break; + + case 0xE0: /* LDH (imm),A */ + writehi(FETCH, A); break; + case 0xE2: /* LDH (C),A */ + writehi(C, A); break; + case 0xF0: /* LDH A,(imm) */ + A = readhi(FETCH); break; + case 0xF2: /* LDH A,(C) (undocumented) */ + A = readhi(C); break; + + + case 0xF8: /* LD HL,SP+imm */ + b = FETCH; LDHLSP(b); break; + case 0xF9: /* LD SP,HL */ + SP = HL; break; + case 0xFA: /* LD A,(imm) */ + A = readb(readw(xPC)); PC += 2; break; + + ALU_CASES(0x80, 0xC6, ADD, __ADD) + ALU_CASES(0x88, 0xCE, ADC, __ADC) + ALU_CASES(0x90, 0xD6, SUB, __SUB) + ALU_CASES(0x98, 0xDE, SBC, __SBC) + ALU_CASES(0xA0, 0xE6, AND, __AND) + ALU_CASES(0xA8, 0xEE, XOR, __XOR) + ALU_CASES(0xB0, 0xF6, OR, __OR) + ALU_CASES(0xB8, 0xFE, CP, __CP) + + case 0x09: /* ADD HL,BC */ + w = BC; goto __ADDW; + case 0x19: /* ADD HL,DE */ + w = DE; goto __ADDW; + case 0x39: /* ADD HL,SP */ + w = SP; goto __ADDW; + case 0x29: /* ADD HL,HL */ + w = HL; + __ADDW: + ADDW(w); + break; + + case 0x04: /* INC B */ + INC(B); break; + case 0x0C: /* INC C */ + INC(C); break; + case 0x14: /* INC D */ + INC(D); break; + case 0x1C: /* INC E */ + INC(E); break; + case 0x24: /* INC H */ + INC(H); break; + case 0x2C: /* INC L */ + INC(L); break; + case 0x34: /* INC (HL) */ + b = readb(xHL); + INC(b); + writeb(xHL, b); + break; + case 0x3C: /* INC A */ + INC(A); break; + + case 0x03: /* INC BC */ + INCW(BC); break; + case 0x13: /* INC DE */ + INCW(DE); break; + case 0x23: /* INC HL */ + INCW(HL); break; + case 0x33: /* INC SP */ + INCW(SP); break; + + case 0x05: /* DEC B */ + DEC(B); break; + case 0x0D: /* DEC C */ + DEC(C); break; + case 0x15: /* DEC D */ + DEC(D); break; + case 0x1D: /* DEC E */ + DEC(E); break; + case 0x25: /* DEC H */ + DEC(H); break; + case 0x2D: /* DEC L */ + DEC(L); break; + case 0x35: /* DEC (HL) */ + b = readb(xHL); + DEC(b); + writeb(xHL, b); + break; + case 0x3D: /* DEC A */ + DEC(A); break; + + case 0x0B: /* DEC BC */ + DECW(BC); break; + case 0x1B: /* DEC DE */ + DECW(DE); break; + case 0x2B: /* DEC HL */ + DECW(HL); break; + case 0x3B: /* DEC SP */ + DECW(SP); break; + + case 0x07: /* RLCA */ + RLCA(A); break; + case 0x0F: /* RRCA */ + RRCA(A); break; + case 0x17: /* RLA */ + RLA(A); break; + case 0x1F: /* RRA */ + RRA(A); break; + + case 0x27: /* DAA */ + DAA; break; + case 0x2F: /* CPL */ + CPL(A); break; + + case 0x18: /* JR */ + __JR: + JR; break; + case 0x20: /* JR NZ */ + if (!(F&FZ)) goto __JR; NOJR; break; + case 0x28: /* JR Z */ + if (F&FZ) goto __JR; NOJR; break; + case 0x30: /* JR NC */ + if (!(F&FC)) goto __JR; NOJR; break; + case 0x38: /* JR C */ + if (F&FC) goto __JR; NOJR; break; + + case 0xC3: /* JP */ + __JP: + JP; break; + case 0xC2: /* JP NZ */ + if (!(F&FZ)) goto __JP; NOJP; break; + case 0xCA: /* JP Z */ + if (F&FZ) goto __JP; NOJP; break; + case 0xD2: /* JP NC */ + if (!(F&FC)) goto __JP; NOJP; break; + case 0xDA: /* JP C */ + if (F&FC) goto __JP; NOJP; break; + case 0xE9: /* JP HL */ + PC = HL; break; + + case 0xC9: /* RET */ + __RET: + RET; break; + case 0xC0: /* RET NZ */ + if (!(F&FZ)) goto __RET; NORET; break; + case 0xC8: /* RET Z */ + if (F&FZ) goto __RET; NORET; break; + case 0xD0: /* RET NC */ + if (!(F&FC)) goto __RET; NORET; break; + case 0xD8: /* RET C */ + if (F&FC) goto __RET; NORET; break; + case 0xD9: /* RETI */ + IME = IMA = 1; goto __RET; + + case 0xCD: /* CALL */ + __CALL: + CALL; break; + case 0xC4: /* CALL NZ */ + if (!(F&FZ)) goto __CALL; NOCALL; break; + case 0xCC: /* CALL Z */ + if (F&FZ) goto __CALL; NOCALL; break; + case 0xD4: /* CALL NC */ + if (!(F&FC)) goto __CALL; NOCALL; break; + case 0xDC: /* CALL C */ + if (F&FC) goto __CALL; NOCALL; break; + + case 0xC7: /* RST 0 */ + b = 0x00; goto __RST; + case 0xCF: /* RST 8 */ + b = 0x08; goto __RST; + case 0xD7: /* RST 10 */ + b = 0x10; goto __RST; + case 0xDF: /* RST 18 */ + b = 0x18; goto __RST; + case 0xE7: /* RST 20 */ + b = 0x20; goto __RST; + case 0xEF: /* RST 28 */ + b = 0x28; goto __RST; + case 0xF7: /* RST 30 */ + b = 0x30; goto __RST; + case 0xFF: /* RST 38 */ + b = 0x38; + __RST: + RST(b); break; + + case 0xC1: /* POP BC */ + POP(BC); break; + case 0xC5: /* PUSH BC */ + PUSH(BC); break; + case 0xD1: /* POP DE */ + POP(DE); break; + case 0xD5: /* PUSH DE */ + PUSH(DE); break; + case 0xE1: /* POP HL */ + POP(HL); break; + case 0xE5: /* PUSH HL */ + PUSH(HL); break; + case 0xF1: /* POP AF */ + POP(AF); break; + case 0xF5: /* PUSH AF */ + PUSH(AF); break; + + case 0xE8: /* ADD SP,imm */ + b = FETCH; ADDSP(b); break; + + case 0xF3: /* DI */ + DI; break; + case 0xFB: /* EI */ + EI; break; + + case 0x37: /* SCF */ + SCF; break; + case 0x3F: /* CCF */ + CCF; break; + + case 0x10: /* STOP */ + PC++; + if (R_KEY1 & 1) + { + cpu.speed = cpu.speed ^ 1; + R_KEY1 = (R_KEY1 & 0x7E) | (cpu.speed << 7); + break; + } + /* NOTE - we do not implement dmg STOP whatsoever */ + break; + + case 0x76: /* HALT */ + cpu.halt = 1; + break; + + case 0xCB: /* CB prefix */ + cbop = FETCH; + clen = cb_cycles_table[cbop]; + switch (cbop) + { + CB_REG_CASES(B, 0); + CB_REG_CASES(C, 1); + CB_REG_CASES(D, 2); + CB_REG_CASES(E, 3); + CB_REG_CASES(H, 4); + CB_REG_CASES(L, 5); + CB_REG_CASES(A, 7); + default: + b = readb(xHL); + switch(cbop) + { + CB_REG_CASES(b, 6); + } + if ((cbop & 0xC0) != 0x40) /* exclude BIT */ + writeb(xHL, b); + break; + } + break; + + default: + die( + "invalid opcode 0x%02X at address 0x%04X, rombank = %d\n", + op, (PC-1) & 0xffff, mbc.rombank); + break; + } + + clen <<= 1; + div_advance(clen); + timer_advance(clen); + clen >>= cpu.speed; + lcdc_advance(clen); + sound_advance(clen); + + i -= clen; + if (i > 0) goto next; + return cycles-i; +} + +#endif /* ASM_CPU_EMULATE */ + + +#ifndef ASM_CPU_STEP + +int cpu_step(int max) +{ + int cnt; + if ((cnt = cpu_idle(max))) return cnt; + return cpu_emulate(1); +} + +#endif /* ASM_CPU_STEP */ + + + + + + + + + + + + diff --git a/MCUME_teensy/teensygnuboy/cpu.h b/MCUME_teensy/teensygnuboy/cpu.h new file mode 100644 index 0000000..182b368 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/cpu.h @@ -0,0 +1,37 @@ + + +#ifndef __CPU_H__ +#define __CPU_H__ + + + +#include "defs.h" + + +union reg +{ + byte b[2][2]; + uint16 w[2]; + un32 d; /* padding for alignment, carry */ +}; + +struct cpu +{ + union reg pc, sp, bc, de, hl, af; + int ime, ima; + int speed; + int halt; + int div, tim; + int lcdc; + int snd; +}; + +extern struct cpu cpu; + +extern void cpu_reset(); +extern int cpu_emulate(int cycles); + + +#endif + + diff --git a/MCUME_teensy/teensygnuboy/cpucore.h b/MCUME_teensy/teensygnuboy/cpucore.h new file mode 100644 index 0000000..d4f998e --- /dev/null +++ b/MCUME_teensy/teensygnuboy/cpucore.h @@ -0,0 +1,291 @@ + +#include "defs.h" +#include "arduinoproto.h" + + +PROGMEM const static byte cycles_table[256] = +{ + 1, 3, 2, 2, 1, 1, 2, 1, 5, 2, 2, 2, 1, 1, 2, 1, + 1, 3, 2, 2, 1, 1, 2, 1, 3, 2, 2, 2, 1, 1, 2, 1, + 3, 3, 2, 2, 1, 1, 2, 1, 3, 2, 2, 2, 1, 1, 2, 1, + 3, 3, 2, 2, 1, 3, 3, 3, 3, 2, 2, 2, 1, 1, 2, 1, + + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1, + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1, + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1, + 2, 2, 2, 2, 2, 2, 1, 2, 1, 1, 1, 1, 1, 1, 2, 1, + + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1, + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1, + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1, + 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1, + + 5, 3, 4, 4, 6, 4, 2, 4, 5, 4, 4, 1, 6, 6, 2, 4, + 5, 3, 4, 0, 6, 4, 2, 4, 5, 4, 4, 0, 6, 0, 2, 4, + 3, 3, 2, 0, 0, 4, 2, 4, 4, 1, 4, 0, 0, 0, 2, 4, + 3, 3, 2, 1, 0, 4, 2, 4, 3, 2, 4, 1, 0, 0, 2, 4, +}; + +PROGMEM const static byte cb_cycles_table[256] = +{ + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + + 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2, + 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2, + 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2, + 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2, + + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, + 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2, +}; + + + +PROGMEM const static byte zflag_table[256] = +{ + FZ, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +PROGMEM const static byte incflag_table[256] = +{ + FZ|FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + FH, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +PROGMEM const static byte decflag_table[256] = +{ + FZ|FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH, + FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN, FN|FH +}; + +PROGMEM const static byte swap_table[256] = +{ + 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80, 0x90, 0xA0, 0xB0, 0xC0, 0xD0, 0xE0, 0xF0, + 0x01, 0x11, 0x21, 0x31, 0x41, 0x51, 0x61, 0x71, 0x81, 0x91, 0xA1, 0xB1, 0xC1, 0xD1, 0xE1, 0xF1, + 0x02, 0x12, 0x22, 0x32, 0x42, 0x52, 0x62, 0x72, 0x82, 0x92, 0xA2, 0xB2, 0xC2, 0xD2, 0xE2, 0xF2, + 0x03, 0x13, 0x23, 0x33, 0x43, 0x53, 0x63, 0x73, 0x83, 0x93, 0xA3, 0xB3, 0xC3, 0xD3, 0xE3, 0xF3, + 0x04, 0x14, 0x24, 0x34, 0x44, 0x54, 0x64, 0x74, 0x84, 0x94, 0xA4, 0xB4, 0xC4, 0xD4, 0xE4, 0xF4, + 0x05, 0x15, 0x25, 0x35, 0x45, 0x55, 0x65, 0x75, 0x85, 0x95, 0xA5, 0xB5, 0xC5, 0xD5, 0xE5, 0xF5, + 0x06, 0x16, 0x26, 0x36, 0x46, 0x56, 0x66, 0x76, 0x86, 0x96, 0xA6, 0xB6, 0xC6, 0xD6, 0xE6, 0xF6, + 0x07, 0x17, 0x27, 0x37, 0x47, 0x57, 0x67, 0x77, 0x87, 0x97, 0xA7, 0xB7, 0xC7, 0xD7, 0xE7, 0xF7, + 0x08, 0x18, 0x28, 0x38, 0x48, 0x58, 0x68, 0x78, 0x88, 0x98, 0xA8, 0xB8, 0xC8, 0xD8, 0xE8, 0xF8, + 0x09, 0x19, 0x29, 0x39, 0x49, 0x59, 0x69, 0x79, 0x89, 0x99, 0xA9, 0xB9, 0xC9, 0xD9, 0xE9, 0xF9, + 0x0A, 0x1A, 0x2A, 0x3A, 0x4A, 0x5A, 0x6A, 0x7A, 0x8A, 0x9A, 0xAA, 0xBA, 0xCA, 0xDA, 0xEA, 0xFA, + 0x0B, 0x1B, 0x2B, 0x3B, 0x4B, 0x5B, 0x6B, 0x7B, 0x8B, 0x9B, 0xAB, 0xBB, 0xCB, 0xDB, 0xEB, 0xFB, + 0x0C, 0x1C, 0x2C, 0x3C, 0x4C, 0x5C, 0x6C, 0x7C, 0x8C, 0x9C, 0xAC, 0xBC, 0xCC, 0xDC, 0xEC, 0xFC, + 0x0D, 0x1D, 0x2D, 0x3D, 0x4D, 0x5D, 0x6D, 0x7D, 0x8D, 0x9D, 0xAD, 0xBD, 0xCD, 0xDD, 0xED, 0xFD, + 0x0E, 0x1E, 0x2E, 0x3E, 0x4E, 0x5E, 0x6E, 0x7E, 0x8E, 0x9E, 0xAE, 0xBE, 0xCE, 0xDE, 0xEE, 0xFE, + 0x0F, 0x1F, 0x2F, 0x3F, 0x4F, 0x5F, 0x6F, 0x7F, 0x8F, 0x9F, 0xAF, 0xBF, 0xCF, 0xDF, 0xEF, 0xFF, +}; + +PROGMEM const static byte daa_table[4096] = +{ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, + + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, + + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, + 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, 0x9A, +}; + +PROGMEM const static byte daa_carry_table[64] = +{ + 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, + 00, 00, 00, 00, 00, 00, 00, 00, FC, FC, 00, 00, 00, 00, 00, 00, + FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, + FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, FC, 00, FC, +}; + + + + + + + + + + + + diff --git a/MCUME_teensy/teensygnuboy/cpuregs.h b/MCUME_teensy/teensygnuboy/cpuregs.h new file mode 100644 index 0000000..0d09908 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/cpuregs.h @@ -0,0 +1,56 @@ + + +#ifndef __CPUREGS_H__ + +#define __CPUREGS_H__ + + + +#include "defs.h" +#include "cpu.h" + +#define LB(r) ((r).b[LO][LO]) +#define HB(r) ((r).b[LO][HI]) +#define W(r) ((r).w[LO]) +#define DW(r) ((r).d) + +#define A HB(cpu.af) +#define F LB(cpu.af) +#define B HB(cpu.bc) +#define C LB(cpu.bc) +#define D HB(cpu.de) +#define E LB(cpu.de) +#define H HB(cpu.hl) +#define L LB(cpu.hl) + +#define AF W(cpu.af) +#define BC W(cpu.bc) +#define DE W(cpu.de) +#define HL W(cpu.hl) + +#define PC W(cpu.pc) +#define SP W(cpu.sp) + +#define xAF DW(cpu.af) +#define xBC DW(cpu.bc) +#define xDE DW(cpu.de) +#define xHL DW(cpu.hl) + +#define xPC DW(cpu.pc) +#define xSP DW(cpu.sp) + +#define IMA cpu.ima +#define IME cpu.ime +#define IF R_IF +#define IE R_IE + +#define FZ 0x80 +#define FN 0x40 +#define FH 0x20 +#define FC 0x10 +#define FL 0x0F /* low unused portion of flags */ + + +#endif /* __CPUREGS_H__ */ + + diff --git a/MCUME_teensy/teensygnuboy/defs.h b/MCUME_teensy/teensygnuboy/defs.h new file mode 100644 index 0000000..7a42eb2 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/defs.h @@ -0,0 +1,47 @@ +#ifndef __DEFS_H__ +#define __DEFS_H__ + + +#define IS_LITTLE_ENDIAN +//#define LSB_FIRST 1 +#define SOUND_PRESENT 1 + + +#define XRES 160 +#define YRES 144 + +#define die +#define time(x) 1 + + +#ifdef IS_LITTLE_ENDIAN +#define LO 0 +#define HI 1 +#else +#define LO 1 +#define HI 0 +#endif + + +typedef unsigned char uint8; +typedef unsigned short int uint16; +typedef unsigned long int uint32; +typedef signed char int8; +typedef signed short int int16; +typedef signed long int int32; + +//#define NULL 0 + +typedef unsigned char un8; +typedef unsigned short un16; +typedef unsigned int un32; +typedef signed char n8; +typedef signed short n16; +typedef signed int n32; + +typedef unsigned char byte; +//typedef unsigned short word; +typedef unsigned short addr; + +#endif + diff --git a/MCUME_teensy/teensygnuboy/emu.cpp b/MCUME_teensy/teensygnuboy/emu.cpp new file mode 100644 index 0000000..17f7e4a --- /dev/null +++ b/MCUME_teensy/teensygnuboy/emu.cpp @@ -0,0 +1,157 @@ +#include + +#include "emuapi.h" +#include "tft_t_dma.h" +#include "psram_t.h" +#include "iopins.h" + +extern "C" { +#include "shared.h" + +#include "defs.h" +#include "regs.h" +#include "lcd.h" +#include "rc.h" +#include "cpu.h" +#include "mem.h" +#include "hw.h" +#include "rtc.h" +#include "sound.h" + +#include "loader.h" +} + + +static int rom_offset = 0; + +PSRAM_T psram = PSRAM_T(PSRAM_CS, PSRAM_MOSI, PSRAM_SCLK, PSRAM_MISO); + + +extern "C" uint8 read_rom(int address) { + return (psram.psread(address+rom_offset)); +} + +//extern "C" uint8 readb_swap_rom(int address) { +// return(psram.psread(address^1)); +//} + +//extern "C" uint16 readw_swap_rom(int address) { +// return psram.psread_w(address); +//} + +extern "C" void write_rom(int address, uint8 val) { + psram.pswrite(address,val); +} + + + + +void gbe_Init(void) +{ + emu_printf("Allocating MEM"); + psram.begin(); + mem_init(); + emu_printf("Allocating MEM done"); +} + + +static int hk = 0; +static int k = 0; + + +void gbe_Input(int click) { + hk = emu_ReadI2CKeyboard(); + k = emu_ReadKeys(); +} + +static char buf[0x1000]; +extern "C" int loadfile(char * filename); +int loadfile(char * filename) +{ + int romsize = emu_FileSize(filename); + int pos = 0; + int n; + int i; + if (emu_FileOpen(filename)) { + while ( (n = emu_FileRead(buf,sizeof(buf))) ) + { + for (int i=0; i 0 && R_LY < YRES) + cpu_emulate(cpu.lcdc); + + rtc_tick(); + //emu_printi(emu_FrameSkip()); + + emu_DrawVsync(); +} + +void SND_Process(void *stream, int len) { +#ifdef SOUND_PRESENT +#ifdef HAS_SND + audio_play_sample(stream, 0, len); +#endif +#endif +} + + + + diff --git a/MCUME_teensy/teensygnuboy/emu.h b/MCUME_teensy/teensygnuboy/emu.h new file mode 100644 index 0000000..5ff4205 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/emu.h @@ -0,0 +1,5 @@ +extern void gbe_Init(void); +extern void gbe_Step(void); +extern void gbe_Start(char * filename); +extern void gbe_Input(int click); + diff --git a/MCUME_teensy/teensygnuboy/emuapi.cpp b/MCUME_teensy/teensygnuboy/emuapi.cpp new file mode 100644 index 0000000..d317c8d --- /dev/null +++ b/MCUME_teensy/teensygnuboy/emuapi.cpp @@ -0,0 +1,1196 @@ +#define KEYMAP_PRESENT 1 + +extern "C" { + #include "emuapi.h" + #include "iopins.h" +} + +#include "tft_t_dma.h" +//#include "logo.h" +//#include "bmpjoy.h" +//#include "bmpvbar.h" +//#include "bmpvga.h" +//#include "bmptft.h" + +#ifndef SD_CS +#define USE_SDFS 1 +#endif + +#ifdef HAS_I2CKBD +#include +#endif + +#ifdef USE_SDFS +#define SDFSDEV "2:" + +#include "uSDFS.h" +static FATFS fatfs; +static FIL file; +#else +#include +static File file; +#endif + +extern TFT_T_DMA tft; +static char romspath[64]; +static int16_t calMinX=-1,calMinY=-1,calMaxX=-1,calMaxY=-1; +static bool i2cKeyboardPresent = false; +const uint16_t deflogo[] = { + 0x0000,0x0000 +}; +static const uint16_t * logo = deflogo; + +#ifdef USE_SDFS +#define CALIBRATION_FILE SDFSDEV "/cal.cfg" +#else +#define CALIBRATION_FILE "/cal.cfg" +#endif +#define MAX_FILES 128 +#define MAX_FILENAME_SIZE 28 +#define MAX_MENULINES (MKEY_L9) +#define TEXT_HEIGHT 16 +#define TEXT_WIDTH 8 +#define MENU_FILE_XOFFSET (6*TEXT_WIDTH) +#define MENU_FILE_YOFFSET (2*TEXT_HEIGHT) +#define MENU_FILE_W (MAX_FILENAME_SIZE*TEXT_WIDTH) +#define MENU_FILE_H (MAX_MENULINES*TEXT_HEIGHT) +#define MENU_FILE_BGCOLOR RGBVAL16(0x00,0x00,0x20) +#define MENU_JOYS_YOFFSET (12*TEXT_HEIGHT) +#define MENU_VBAR_XOFFSET (0*TEXT_WIDTH) +#define MENU_VBAR_YOFFSET (MENU_FILE_YOFFSET) + +#define MENU_TFT_XOFFSET (MENU_FILE_XOFFSET+MENU_FILE_W+8) +#define MENU_TFT_YOFFSET (MENU_VBAR_YOFFSET+32) +//#define MENU_VGA_XOFFSET (MENU_FILE_XOFFSET+MENU_FILE_W+8) +//#define MENU_VGA_YOFFSET (MENU_VBAR_YOFFSET+MENU_FILE_H-32-37) + + +#define MKEY_L1 1 +#define MKEY_L2 2 +#define MKEY_L3 3 +#define MKEY_L4 4 +#define MKEY_L5 5 +#define MKEY_L6 6 +#define MKEY_L7 7 +#define MKEY_L8 8 +#define MKEY_L9 9 +#define MKEY_UP 20 +#define MKEY_DOWN 21 +#define MKEY_JOY 22 +#define MKEY_TFT 23 +#define MKEY_VGA 24 + +const unsigned short menutouchareas[] = { + TAREA_XY,MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, + TAREA_WH,MENU_FILE_W, TEXT_HEIGHT, + TAREA_NEW_COL,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT, + + TAREA_XY,MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET, + TAREA_WH,32,48, + TAREA_NEW_COL, 72,72,8,40, + + TAREA_XY,MENU_TFT_XOFFSET,MENU_TFT_YOFFSET, + TAREA_WH,32,37, + TAREA_NEW_COL, 38,38, + + TAREA_END}; + +const unsigned short menutouchactions[] = { + MKEY_L1,MKEY_L2,MKEY_L3,MKEY_L4,MKEY_L5,MKEY_L6,MKEY_L7,MKEY_L8,MKEY_L9, + MKEY_UP,MKEY_DOWN,ACTION_NONE,MKEY_JOY, + MKEY_TFT,MKEY_VGA}; + + +static bool menuOn=true; +static bool callibrationOn=false; +static int callibrationStep=0; +static bool menuRedraw=true; +static int nbFiles=0; +static int curFile=0; +static int topFile=0; +static char selection[MAX_FILENAME_SIZE+1]=""; +static uint8_t prev_zt=0; + +static char files[MAX_FILES][MAX_FILENAME_SIZE]; + +static int readNbFiles(void) { + int totalFiles = 0; + +#ifdef USE_SDFS + DIR dir; + FILINFO entry; + f_opendir(&dir, romspath); + while ( (true) && (totalFiles= y1) && (yt < y2) && (xt >= x1) && (xt < x2) ) { + *rx = x1; + *ry = y1; + *rw = x2-x1; + *rh = y2-y1; + return (actions[k]); + } + k++; + } + } + } + prev_zt =1; + } else { + prev_zt=0; + } + + return ACTION_NONE; +} + +void toggleMenu(bool on) { + if (on) { + callibrationOn=false; + menuOn=true; + menuRedraw=true; + tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00)); + tft.drawTextNoDma(0,0, TITLE, RGBVAL16(0x00,0xff,0xff), RGBVAL16(0x00,0x00,0xff), true); + //tft.drawSpriteNoDma(MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET,(uint16_t*)bmpvbar); + //tft.drawSpriteNoDma(MENU_TFT_XOFFSET,MENU_TFT_YOFFSET,(uint16_t*)bmptft); + //tft.drawSpriteNoDma(MENU_VGA_XOFFSET,MENU_VGA_YOFFSET,(uint16_t*)bmpvga); + } else { + menuOn = false; + } +} + + +static void callibrationInit(void) +{ + callibrationOn=true; + menuOn=false; + callibrationStep = 0; + calMinX=0,calMinY=0,calMaxX=0,calMaxY=0; + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration process:", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " Hit the red cross at each corner", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + prev_zt = 1; +} + + +static void readCallibration(void) +{ + char fileBuffer[64]; + +#ifdef USE_SDFS + FIL file; + int retval; + if( !(f_open(&file, CALIBRATION_FILE, FA_READ)) ) { + if( !(f_read (&file, fileBuffer, 64, &retval)) ) { + if (retval == 64) { + sscanf(fileBuffer,"%d %d %d %d", &calMinX,&calMinY,&calMaxX,&calMaxY); + } + } + f_close(&file); + } +#else + File file = SD.open(CALIBRATION_FILE, O_READ); + if (file) { + if ( file.read(fileBuffer, 64) ) { + sscanf(fileBuffer,"%d %d %d %d", &calMinX,&calMinY,&calMaxX,&calMaxY); + } + file.close(); + Serial.println("Current callibration params:"); + Serial.println(calMinX); + Serial.println(calMinY); + Serial.println(calMaxX); + Serial.println(calMaxY); + } + else { + Serial.println("Callibration read error"); + } +#endif + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); +} + +static void writeCallibration(void) +{ + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); +#ifdef USE_SDFS + FIL file; + int retval; + if( !(f_open(&file, CALIBRATION_FILE, FA_WRITE)) ) { + //if( !(f_read (&file, fileBuffer, 64, &retval)) ) { + // if (retval == 64) { + // sscanf(fileBuffer,"%d %d %d %d", &calMinX,&calMinY,&calMaxX,&calMaxY); + // } + //} + f_close(&file); + } + +#else + File file = SD.open(CALIBRATION_FILE, O_WRITE | O_CREAT | O_TRUNC); + if (file) { + file.print(calMinX); + file.print(" "); + file.print(calMinY); + file.print(" "); + file.print(calMaxX); + file.print(" "); + file.println(calMaxY); + file.close(); + } + else { + Serial.println("Callibration write error"); + } +#endif +} + + +bool callibrationActive(void) +{ + return (callibrationOn); +} + + + +int handleCallibration(uint16_t bClick) { + uint16_t xt=0; + uint16_t yt=0; + uint16_t zt=0; + if (tft.isTouching()) { + if (prev_zt == 0) { + prev_zt = 1; + tft.readRaw(&xt,&yt,&zt); + if (zt < 1000) { + return 0; + } + switch (callibrationStep) + { + case 0: + callibrationStep++; + tft.drawTextNoDma(0,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(TFT_REALWIDTH-8,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMinX += xt; + calMinY += yt; + break; + case 1: + callibrationStep++; + tft.drawTextNoDma(TFT_REALWIDTH-8,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(TFT_REALWIDTH-8,TFT_REALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMinY += yt; + break; + case 2: + callibrationStep++; + tft.drawTextNoDma(TFT_REALWIDTH-8,TFT_REALHEIGHT-16, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,TFT_REALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMaxY += yt; + break; + case 3: + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration done!", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " (Click center to exit)", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + callibrationStep++; + calMinX += xt; + calMaxY += yt; + break; + case 4: + //Serial.println(xt); + //Serial.println(yt); + if ( (xt > (TFT_REALWIDTH/4)) && (xt < (TFT_REALWIDTH*3)/4) + && (yt > (TFT_REALHEIGHT/4)) && (yt < (TFT_REALHEIGHT*3)/4) ) { + calMinX /= 2; + calMinY /= 2; + calMaxX /= 2; + calMaxY /= 2; + writeCallibration(); + toggleMenu(true); + } + else { + callibrationInit(); + } + break; + + } + delay(100); + } + } + else { + prev_zt = 0; + } +} + + + +bool menuActive(void) +{ + return (menuOn); +} + +int handleMenu(uint16_t bClick) +{ + int action = ACTION_NONE; + + char newpath[80]; + strcpy(newpath, romspath); + strcat(newpath, "/"); + strcat(newpath, selection); + + int rx=0,ry=0,rw=0,rh=0; + char c = captureTouchZone(menutouchareas, menutouchactions, &rx,&ry,&rw,&rh); + + if ( (bClick & MASK_JOY2_BTN) || (c == MKEY_TFT) ) { + emu_printf(newpath); +#ifdef USE_SDFS + FILINFO entry; + f_stat(newpath, &entry); + if ( (entry.fattrib & AM_DIR) ) { +#else + File file = SD.open(newpath); + if (file.isDirectory()) { +#endif + strcpy(romspath,newpath); + curFile = 0; + nbFiles = readNbFiles(); + } + else { + action = ACTION_RUNTFT; + } + menuRedraw=true; + } + else if ( (bClick & MASK_KEY_USER1) || (c == MKEY_VGA) ) { + menuRedraw=true; + action = ACTION_RUNVGA; + } + else if ( (c >= MKEY_L1) && (c <= MKEY_L9) ) { + if ( (topFile+(int)c-1) <= (nbFiles-1) ) + { + curFile = topFile + (int)c -1; + menuRedraw=true; + //tft.drawRectNoDma( rx,ry,rw,rh, KEYBOARD_HIT_COLOR ); + } + } + else if (bClick & MASK_JOY2_UP) { + if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if ( (bClick & MASK_JOY2_RIGHT) || (bClick & MASK_JOY1_RIGHT) || (c == MKEY_UP) ) { + if ((curFile-9)>=0) { + menuRedraw=true; + curFile -= 9; + } else if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if (bClick & MASK_JOY2_DOWN) { + if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_JOY2_LEFT) || (bClick & MASK_JOY1_LEFT) || (c == MKEY_DOWN) ) { + if ((curFile<(nbFiles-9)) && (nbFiles)) { + curFile += 9; + menuRedraw=true; + } + else if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_KEY_USER2) || (c == MKEY_JOY) ) { + emu_SwapJoysticks(0); + menuRedraw=true; + } + + if (menuRedraw && nbFiles) { + int fileIndex = 0; + tft.drawRectNoDma(MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, MENU_FILE_W, MENU_FILE_H, MENU_FILE_BGCOLOR); +// if (curFile <= (MAX_MENULINES/2-1)) topFile=0; +// else topFile=curFile-(MAX_MENULINES/2); + if (curFile <= (MAX_MENULINES-1)) topFile=0; + else topFile=curFile-(MAX_MENULINES/2); + + //Serial.print("curfile: "); + //Serial.println(curFile); + //Serial.print("topFile: "); + //Serial.println(topFile); + + int i=0; + while (i=nbFiles) { + // no more files + break; + } + char * filename = &files[fileIndex][0]; + if (fileIndex >= topFile) { + if ((i+topFile) < nbFiles ) { + if ((i+topFile)==curFile) { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, filename, RGBVAL16(0xff,0xff,0x00), RGBVAL16(0xff,0x00,0x00), true); + strcpy(selection,filename); + } + else { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, filename, 0xFFFF, 0x0000, true); + } + } + i++; + } + fileIndex++; + } + + //tft.drawSpriteNoDma(0,MENU_JOYS_YOFFSET,(uint16_t*)bmpjoy); + tft.drawTextNoDma(48,MENU_JOYS_YOFFSET+8, (emu_SwapJoysticks(1)?(char*)"SWAP=1":(char*)"SWAP=0"), RGBVAL16(0x00,0xff,0xff), RGBVAL16(0xff,0x00,0x00), false); + menuRedraw=false; + } + + return (action); +} + +char * menuSelection(void) +{ + return (selection); +} + + + + +void emu_init(void) +{ + Serial.begin(115200); + //while (!Serial) {} +#ifdef USE_SDFS + strcpy(romspath,SDFSDEV); + strcat(romspath,ROMSDIR); + FRESULT rc; + if((rc = f_mount (&fatfs, romspath, 1))) { + emu_printf("Fail mounting SDFS"); + } + else { + rc = f_chdrive(ROMSDIR); + } +#else + while (!SD.begin(SD_CS)) { + emu_printf("SdFat.begin() failed"); + delay(1000); + } + strcpy(romspath,ROMSDIR); +#endif + nbFiles = readNbFiles(); + + Serial.print("SD initialized, files found: "); + Serial.println(nbFiles); + + emu_InitJoysticks(); + readCallibration(); + + if ((tft.isTouching()) || (emu_ReadKeys() & MASK_JOY2_BTN) ) { + callibrationInit(); + } + else + { + toggleMenu(true); + } + +#ifdef HAS_I2CKBD + byte msg[7]={0,0,0,0,0,0,0}; + Wire.begin(); // join i2c bus SDA2/SCL2 + Wire.requestFrom(8, 7); // request 7 bytes from slave device #8 + int i = 0; + while (Wire.available() && (i<7) ) { // slave may send less than requested + byte b = Wire.read(); // receive a byte + msg[i++] = b; + } + /* + Serial.println(msg[0], BIN); + Serial.println(msg[1], BIN); + Serial.println(msg[2], BIN); + Serial.println(msg[3], BIN); + Serial.println(msg[4], BIN); + Serial.println(msg[5], BIN); + Serial.println(msg[6], BIN); + */ + if ( (msg[0] == 0xff) && (msg[1] == 0xff) && + (msg[2] == 0xff) && (msg[3] == 0xff) && + (msg[4] == 0xff) && (msg[5] == 0xff) && (msg[6] == 0xff)) { + i2cKeyboardPresent = true; + Serial.println("i2C keyboard found"); + } +#endif +} + + +void emu_printf(char * text) +{ + Serial.println(text); +} + +void emu_printf(int val) +{ + Serial.println(val); +} + +void emu_printi(int val) +{ + Serial.println(val); +} + +void emu_printh(int val) +{ + Serial.println(val,HEX); +} + +static int malbufpt = 0; +static char malbuf[EXTRA_HEAP]; + +void * emu_Malloc(int size) +{ + void * retval = malloc(size); + if (!retval) { + emu_printf("failled to allocate"); + emu_printf(size); + emu_printf("fallback"); + if ( (malbufpt+size) < sizeof(malbuf) ) { + retval = (void *)&malbuf[malbufpt]; + malbufpt += size; + } + else { + emu_printf("failure to allocate"); + } + } + else { + emu_printf("could allocate "); + emu_printf(size); + } + + return retval; +} + +void emu_Free(void * pt) +{ + free(pt); +} + + + +int emu_FileOpen(char * filename) +{ + int retval = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("FileOpen..."); + emu_printf(filepath); +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { +#else + if ((file = SD.open(filepath, O_READ))) { +#endif + retval = 1; + } + else { + emu_printf("FileOpen failed"); + } + return (retval); +} + +int emu_FileRead(char * buf, int size) +{ + unsigned char buffer[256]; + + int remaining = size; + int byteread = 0; + int retval=0; + while (remaining>0) { +#ifdef USE_SDFS + if( !(f_read (&file, buffer, 256, &retval)) ) + //f_read (&file, buffer, 256, &retval); +#else + retval = file.read(buffer, 256); +#endif + if (retval>0) { + //emu_printi(retval); + memcpy(buf,buffer,retval); + buf += retval; + byteread += retval; + remaining -= retval; + } + else { + break; + } + } + + return byteread; +} + +unsigned char emu_FileGetc(void) { + unsigned char c; +#ifdef USE_SDFS + int retval=0; + if( !(f_read (&file, &c, 1, &retval)) ) +#else + int retval = file.read(&c, 1); +#endif + if (retval != 1) { + emu_printf("emu_FileGetc failed"); + } + return c; +} + + +void emu_FileClose(void) +{ +#ifdef USE_SDFS + f_close(&file); +#else + file.close(); +#endif +} + +int emu_FileSize(char * filename) +{ + int filesize=0; + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("FileSize..."); + emu_printf(filepath); +#ifdef USE_SDFS + FILINFO entry; + f_stat(filepath, &entry); + filesize = entry.fsize; +#else + if ((file = SD.open(filepath, O_READ))) + { + emu_printf("filesize is..."); + filesize = file.size(); + emu_printf(filesize); + file.close(); + } +#endif + + return(filesize); +} + +int emu_FileSeek(int seek) +{ +#ifdef USE_SDFS + f_lseek(&file, seek); +#else + file.seek(seek); +#endif + return (seek); +} + +int emu_FileTell(void) +{ +#ifdef USE_SDFS + return (f_tell(&file)); +#else + return (50); +#endif +} + + +int emu_LoadFile(char * filename, char * buf, int size) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("LoadFile..."); + emu_printf(filepath); +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { + filesize = f_size(&file); + emu_printf(filesize); + if (size >= filesize) + { + int retval=0; + if( (f_read (&file, buf, filesize, &retval)) ) { + emu_printf("File read failed"); + } + } + f_close(&file); + } +#else + if ((file = SD.open(filepath, O_READ))) + { + filesize = file.size(); + emu_printf(filesize); + + if (size >= filesize) + { + if (emu_FileRead(buf, filesize) != filesize) + { + emu_printf("File read failed"); + } + } + file.close(); + } +#endif + + return(filesize); +} + +int emu_LoadFileSeek(char * filename, char * buf, int size, int seek) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("LoadFileSeek..."); + emu_printf(filepath); +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { + f_lseek(&file, seek); + emu_printf(size); + if (size >= filesize) + { + int retval=0; + if( (!f_read (&file, buf, size, &retval)) ) + if (retval != size) + { + emu_printf("File read failed"); + } + } + f_close(&file); + } +#else + if ((file = SD.open(filepath, O_READ))) + { + file.seek(seek); + emu_printf(size); + if (file.read(buf, size) != size) { + emu_printf("File read failed"); + } + file.close(); + } +#endif + + return(filesize); +} + +static int keypadval=0; +static boolean joySwapped = false; +static uint16_t bLastState; +static int xRef; +static int yRef; + + +int emu_ReadAnalogJoyX(int min, int max) +{ + int val = analogRead(PIN_JOY2_A1X); +#if INVX + val = 4095 - val; +#endif + val = val-xRef; + val = ((val*140)/100); + if ( (val > -512) && (val < 512) ) val = 0; + val = val+2048; + return (val*(max-min))/4096; +} + +int emu_ReadAnalogJoyY(int min, int max) +{ + int val = analogRead(PIN_JOY2_A2Y); +#if INVY + val = 4095 - val; +#endif + val = val-yRef; + val = ((val*120)/100); + if ( (val > -512) && (val < 512) ) val = 0; + //val = (val*(max-min))/4096; + val = val+2048; + //return val+(max-min)/2; + return (val*(max-min))/4096; +} + + +static uint16_t readAnalogJoystick(void) +{ + uint16_t joysval = 0; + + int xReading = emu_ReadAnalogJoyX(0,256); + if (xReading > 128) joysval |= MASK_JOY2_LEFT; + else if (xReading < 128) joysval |= MASK_JOY2_RIGHT; + + int yReading = emu_ReadAnalogJoyY(0,256); + if (yReading < 128) joysval |= MASK_JOY2_UP; + else if (yReading > 128) joysval |= MASK_JOY2_DOWN; + +#ifdef PIN_JOY2_BTN + joysval |= (digitalRead(PIN_JOY2_BTN) == HIGH ? 0 : MASK_JOY2_BTN); +#endif + return (joysval); +} + + +int emu_SwapJoysticks(int statusOnly) { + if (!statusOnly) { + if (joySwapped) { + joySwapped = false; + } + else { + joySwapped = true; + } + } + return(joySwapped?1:0); +} + +int emu_GetPad(void) +{ + return(keypadval|((joySwapped?1:0)<<7)); +} + +int emu_ReadKeys(void) +{ + uint16_t retval; + uint16_t j1 = readAnalogJoystick(); + uint16_t j2 = 0; + + // Second joystick +#ifdef PIN_JOY1_1 + if ( digitalRead(PIN_JOY1_1) == LOW ) j2 |= MASK_JOY2_UP; +#endif +#ifdef PIN_JOY1_2 + if ( digitalRead(PIN_JOY1_2) == LOW ) j2 |= MASK_JOY2_DOWN; +#endif +#ifdef PIN_JOY1_3 + if ( digitalRead(PIN_JOY1_3) == LOW ) j2 |= MASK_JOY2_RIGHT; +#endif +#ifdef PIN_JOY1_4 + if ( digitalRead(PIN_JOY1_4) == LOW ) j2 |= MASK_JOY2_LEFT; +#endif +#ifdef PIN_JOY1_BTN + if ( digitalRead(PIN_JOY1_BTN) == LOW ) j2 |= MASK_JOY2_BTN; +#endif + if (joySwapped) { + retval = ((j1 << 8) | j2); + } + else { + retval = ((j2 << 8) | j1); + } + +#ifdef PIN_KEY_USER1 + if ( digitalRead(PIN_KEY_USER1) == LOW ) retval |= MASK_KEY_USER1; +#endif +#ifdef PIN_KEY_USER2 + if ( digitalRead(PIN_KEY_USER2) == LOW ) retval |= MASK_KEY_USER2; +#endif +#ifdef PIN_KEY_USER3 + if ( digitalRead(PIN_KEY_USER3) == LOW ) retval |= MASK_KEY_USER3; +#endif +#ifdef PIN_KEY_USER4 + if ( digitalRead(PIN_KEY_USER4) == LOW ) retval |= MASK_KEY_USER4; +#endif + + //Serial.println(j1,HEX); + + return (retval); +} + +unsigned short emu_DebounceLocalKeys(void) +{ + uint16_t bCurState = emu_ReadKeys(); + uint16_t bClick = bCurState & ~bLastState; + bLastState = bCurState; + + return (bClick); +} + +int emu_ReadI2CKeyboard(void) { + int retval=0; +#ifdef HAS_I2CKBD + if (i2cKeyboardPresent) { + byte msg[7]={0,0,0,0,0,0,0}; + Wire.requestFrom(8, 7); // request 7 bytes from slave device #8 + int i = 0; + int hitindex=-1; + while (Wire.available() && (i<7) ) { // slave may send less than requested + byte b = Wire.read(); // receive a byte + if (b != 0xff) hitindex=i; + msg[i++] = b; + } + + if (hitindex >=0 ) { + /* + Serial.println(msg[0], BIN); + Serial.println(msg[1], BIN); + Serial.println(msg[2], BIN); + Serial.println(msg[3], BIN); + Serial.println(msg[4], BIN); + Serial.println(msg[5], BIN); + Serial.println(msg[6], BIN); + */ + unsigned short match = (~msg[hitindex])&0x00FF | (hitindex<<8); + //Serial.println(match,HEX); + for (i=0; i=1) && (c <= ACTION_MAXKBDVAL) ) { + + keypadval = c; + keyPressCount = 10; + delay(50); + vkeyRefresh = true; + exitVkbd = true; + } + else if (c == ACTION_EXITKBD) { + vkeyRefresh = true; + exitVkbd = true; + } + } + } + + if (vkeyRefresh) { + vkeyRefresh = false; + tft.drawSpriteNoDma(0,0,(uint16_t*)logo, rx, ry, rw, rh); + } + + if ( (exitVkbd) && (vkbActive) ) { + if (!vkbKeepOn) { + toggleVirtualkeyboard(false); + } + else { + toggleVirtualkeyboard(true); + } + } +} + +int emu_setKeymap(int index) { + if (index) { + } + else { + } +} + + + diff --git a/MCUME_teensy/teensygnuboy/emuapi.h b/MCUME_teensy/teensygnuboy/emuapi.h new file mode 100644 index 0000000..4fe725f --- /dev/null +++ b/MCUME_teensy/teensygnuboy/emuapi.h @@ -0,0 +1,152 @@ +#ifndef EMUAPI_H +#define EMUAPI_H + +//#define INVX 1 +//#define INVY 1 +#define HAS_SND 1 +#define CUSTOM_SND 1 +//#define HAS_I2CKBD 1 +//#define TIMER_REND 1 + +#define EXTRA_HEAP 0x10 //0x9000 + +// Title: < > +#define TITLE " Gameboy Emulator " +#define ROMSDIR "/gameboy" + +#define emu_Init(ROM) {gbe_Init(); gbe_Start(ROM);} +#define emu_Step(x) {gbe_Step();} +#define emu_Input(x) {gbe_Input(x);} + +#define PALETTE_SIZE 256 +#define VID_FRAME_SKIP 0x0 +#define TFT_VBUFFER_YCROP 0 +#define SINGLELINE_RENDERING 1 + +#define R32(rgb) ((rgb>>16)&0xff) +#define G32(rgb) ((rgb>>8)&0xff) +#define B32(rgb) (rgb & 0xff) + +#define ACTION_NONE 0 +#define ACTION_MAXKBDVAL 16 +#define ACTION_EXITKBD 128 +#define ACTION_RUNTFT 129 +#define ACTION_RUNVGA 130 + +#ifdef KEYMAP_PRESENT + +#define TAREA_W_DEF 32 +#define TAREA_H_DEF 32 +#define TAREA_END 255 +#define TAREA_NEW_ROW 254 +#define TAREA_NEW_COL 253 +#define TAREA_XY 252 +#define TAREA_WH 251 + +#define KEYBOARD_X 16 +#define KEYBOARD_Y 32 +#define KEYBOARD_KEY_H 30 +#define KEYBOARD_KEY_W 28 +#define KEYBOARD_HIT_COLOR RGBVAL16(0xff,0x00,0x00) + +const unsigned short keysw[]= +{ TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + //TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_END}; + +const unsigned short keys[]={ + +59, 60, 61, 62, 63, 64, 65, 66, 67, 68, +109,110,111,112,106,107,108,17,18,19, +20,21,22,23,24,25,26,27,28,29, +30,31,32,33,34,35,36,37,38,57 }; + + + + +#ifdef HAS_I2CKBD +const unsigned short i2ckeys[] = { + 0X0080,0X0008,0X0180,0X0108,0X0280,0X0208,0X0380,0X0308,0X0480,0X0408, + 0X0040,0X0004,0X0140,0X0104,0X0240,0X0204,0X0340,0X0304,0X0440,0X0404, + 0X0020,0X0002,0X0120,0X0102,0X0220,0X0202,0X0320,0X0302,0X0420,0X0402, + 0X0010,0X0001,0X0110,0X0101,0X0210,0X0201,0X0310,0X0301,0X0410,0X0401 }; + //0X0580,0X0540,0X0520,0X0510,0X0508,0X0504,0X0502,0X0501,0X0680,0X0640 }; +#endif + +#endif + + + +#define MASK_JOY2_RIGHT 0x0001 +#define MASK_JOY2_LEFT 0x0002 +#define MASK_JOY2_UP 0x0004 +#define MASK_JOY2_DOWN 0x0008 +#define MASK_JOY2_BTN 0x0010 +#define MASK_KEY_USER1 0x0020 +#define MASK_KEY_USER2 0x0040 +#define MASK_KEY_USER3 0x0080 +#define MASK_JOY1_RIGHT 0x0100 +#define MASK_JOY1_LEFT 0x0200 +#define MASK_JOY1_UP 0x0400 +#define MASK_JOY1_DOWN 0x0800 +#define MASK_JOY1_BTN 0x1000 +#define MASK_KEY_USER4 0x2000 + + + +#ifdef __cplusplus +extern "C" { +#endif +extern void emu_init(void); +extern void emu_printf(char * text); +extern void emu_printi(int val); +extern void emu_printh(int val); +extern void * emu_Malloc(int size); +extern void emu_Free(void * pt); + + +extern int emu_FileOpen(char * filename); +extern int emu_FileRead(char * buf, int size); +extern unsigned char emu_FileGetc(void); +extern int emu_FileTell(void); +extern int emu_FileSeek(int seek); +extern void emu_FileClose(void); +extern int emu_FileSize(char * filename); +extern int emu_LoadFile(char * filename, char * buf, int size); +extern int emu_LoadFileSeek(char * filename, char * buf, int size, int seek); +extern void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index); +extern void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride); +extern void emu_DrawLine(unsigned char * VBuf, int width, int height, int line); +extern void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line); +extern void emu_DrawVsync(void); +extern int emu_FrameSkip(void); +extern void * emu_LineBuffer(int line); + +extern void emu_InitJoysticks(void); +extern int emu_SwapJoysticks(int statusOnly); +extern unsigned short emu_DebounceLocalKeys(void); +extern int emu_ReadKeys(void); +extern int emu_GetPad(void); +extern int emu_ReadAnalogJoyX(int min, int max); +extern int emu_ReadAnalogJoyY(int min, int max); +extern int emu_ReadI2CKeyboard(void); +extern void emu_sndPlaySound(int chan, int volume, int freq); +extern void emu_sndPlayBuzz(int size, int val); +extern void emu_sndInit(); +extern void emu_resetus(void); +extern int emu_us(void); + +extern int emu_setKeymap(int index); + +#ifdef __cplusplus +} +#endif + +#endif + + + + diff --git a/MCUME_teensy/teensygnuboy/font8x8.h b/MCUME_teensy/teensygnuboy/font8x8.h new file mode 100644 index 0000000..2b2ab25 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/font8x8.h @@ -0,0 +1,135 @@ + +// Font: c64_lower.64c + +PROGMEM const unsigned char font8x8[128][8] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0000 (nul) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0001 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0002 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0003 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0004 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0005 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0006 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0007 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0008 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0009 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0010 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0011 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0012 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0013 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0014 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0015 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0016 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0017 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0018 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0019 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0020 (space) + { 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00}, // U+0021 (!) + { 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0022 (") + { 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00}, // U+0023 (#) + { 0x0C, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x0C, 0x00}, // U+0024 ($) + { 0x00, 0x63, 0x33, 0x18, 0x0C, 0x66, 0x63, 0x00}, // U+0025 (%) + { 0x1C, 0x36, 0x1C, 0x6E, 0x3B, 0x33, 0x6E, 0x00}, // U+0026 (&) + { 0x06, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0027 (') + { 0x18, 0x0C, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x00}, // U+0028 (() + { 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06, 0x00}, // U+0029 ()) + { 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00}, // U+002A (*) + { 0x00, 0x0C, 0x0C, 0x3F, 0x0C, 0x0C, 0x00, 0x00}, // U+002B (+) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+002C (,) + { 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00}, // U+002D (-) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+002E (.) + { 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x00}, // U+002F (/) + { 0x3E, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x3E, 0x00}, // U+0030 (0) + { 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x3F, 0x00}, // U+0031 (1) + { 0x1E, 0x33, 0x30, 0x1C, 0x06, 0x33, 0x3F, 0x00}, // U+0032 (2) + { 0x1E, 0x33, 0x30, 0x1C, 0x30, 0x33, 0x1E, 0x00}, // U+0033 (3) + { 0x38, 0x3C, 0x36, 0x33, 0x7F, 0x30, 0x78, 0x00}, // U+0034 (4) + { 0x3F, 0x03, 0x1F, 0x30, 0x30, 0x33, 0x1E, 0x00}, // U+0035 (5) + { 0x1C, 0x06, 0x03, 0x1F, 0x33, 0x33, 0x1E, 0x00}, // U+0036 (6) + { 0x3F, 0x33, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00}, // U+0037 (7) + { 0x1E, 0x33, 0x33, 0x1E, 0x33, 0x33, 0x1E, 0x00}, // U+0038 (8) + { 0x1E, 0x33, 0x33, 0x3E, 0x30, 0x18, 0x0E, 0x00}, // U+0039 (9) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+003A (:) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+003B (//) + { 0x18, 0x0C, 0x06, 0x03, 0x06, 0x0C, 0x18, 0x00}, // U+003C (<) + { 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00}, // U+003D (=) + { 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06, 0x00}, // U+003E (>) + { 0x1E, 0x33, 0x30, 0x18, 0x0C, 0x00, 0x0C, 0x00}, // U+003F (?) + { 0x3E, 0x63, 0x7B, 0x7B, 0x7B, 0x03, 0x1E, 0x00}, // U+0040 (@) + { 0x0C, 0x1E, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x00}, // U+0041 (A) + { 0x3F, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3F, 0x00}, // U+0042 (B) + { 0x3C, 0x66, 0x03, 0x03, 0x03, 0x66, 0x3C, 0x00}, // U+0043 (C) + { 0x1F, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1F, 0x00}, // U+0044 (D) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x46, 0x7F, 0x00}, // U+0045 (E) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x06, 0x0F, 0x00}, // U+0046 (F) + { 0x3C, 0x66, 0x03, 0x03, 0x73, 0x66, 0x7C, 0x00}, // U+0047 (G) + { 0x33, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x33, 0x00}, // U+0048 (H) + { 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0049 (I) + { 0x78, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, 0x00}, // U+004A (J) + { 0x67, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x67, 0x00}, // U+004B (K) + { 0x0F, 0x06, 0x06, 0x06, 0x46, 0x66, 0x7F, 0x00}, // U+004C (L) + { 0x63, 0x77, 0x7F, 0x7F, 0x6B, 0x63, 0x63, 0x00}, // U+004D (M) + { 0x63, 0x67, 0x6F, 0x7B, 0x73, 0x63, 0x63, 0x00}, // U+004E (N) + { 0x1C, 0x36, 0x63, 0x63, 0x63, 0x36, 0x1C, 0x00}, // U+004F (O) + { 0x3F, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x0F, 0x00}, // U+0050 (P) + { 0x1E, 0x33, 0x33, 0x33, 0x3B, 0x1E, 0x38, 0x00}, // U+0051 (Q) + { 0x3F, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x67, 0x00}, // U+0052 (R) + { 0x1E, 0x33, 0x07, 0x0E, 0x38, 0x33, 0x1E, 0x00}, // U+0053 (S) + { 0x3F, 0x2D, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0054 (T) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F, 0x00}, // U+0055 (U) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0056 (V) + { 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00}, // U+0057 (W) + { 0x63, 0x63, 0x36, 0x1C, 0x1C, 0x36, 0x63, 0x00}, // U+0058 (X) + { 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x0C, 0x1E, 0x00}, // U+0059 (Y) + { 0x7F, 0x63, 0x31, 0x18, 0x4C, 0x66, 0x7F, 0x00}, // U+005A (Z) + { 0x1E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1E, 0x00}, // U+005B ([) + { 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00}, // U+005C (\) + { 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00}, // U+005D (]) + { 0x08, 0x1C, 0x36, 0x63, 0x00, 0x00, 0x00, 0x00}, // U+005E (^) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF}, // U+005F (_) + { 0x0C, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0060 (`) + { 0x00, 0x00, 0x1E, 0x30, 0x3E, 0x33, 0x6E, 0x00}, // U+0061 (a) + { 0x07, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3B, 0x00}, // U+0062 (b) + { 0x00, 0x00, 0x1E, 0x33, 0x03, 0x33, 0x1E, 0x00}, // U+0063 (c) + { 0x38, 0x30, 0x30, 0x3e, 0x33, 0x33, 0x6E, 0x00}, // U+0064 (d) + { 0x00, 0x00, 0x1E, 0x33, 0x3f, 0x03, 0x1E, 0x00}, // U+0065 (e) + { 0x1C, 0x36, 0x06, 0x0f, 0x06, 0x06, 0x0F, 0x00}, // U+0066 (f) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0067 (g) + { 0x07, 0x06, 0x36, 0x6E, 0x66, 0x66, 0x67, 0x00}, // U+0068 (h) + { 0x0C, 0x00, 0x0E, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0069 (i) + { 0x30, 0x00, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E}, // U+006A (j) + { 0x07, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x67, 0x00}, // U+006B (k) + { 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+006C (l) + { 0x00, 0x00, 0x33, 0x7F, 0x7F, 0x6B, 0x63, 0x00}, // U+006D (m) + { 0x00, 0x00, 0x1F, 0x33, 0x33, 0x33, 0x33, 0x00}, // U+006E (n) + { 0x00, 0x00, 0x1E, 0x33, 0x33, 0x33, 0x1E, 0x00}, // U+006F (o) + { 0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x0F}, // U+0070 (p) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x78}, // U+0071 (q) + { 0x00, 0x00, 0x3B, 0x6E, 0x66, 0x06, 0x0F, 0x00}, // U+0072 (r) + { 0x00, 0x00, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x00}, // U+0073 (s) + { 0x08, 0x0C, 0x3E, 0x0C, 0x0C, 0x2C, 0x18, 0x00}, // U+0074 (t) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x6E, 0x00}, // U+0075 (u) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0076 (v) + { 0x00, 0x00, 0x63, 0x6B, 0x7F, 0x7F, 0x36, 0x00}, // U+0077 (w) + { 0x00, 0x00, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x00}, // U+0078 (x) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0079 (y) + { 0x00, 0x00, 0x3F, 0x19, 0x0C, 0x26, 0x3F, 0x00}, // U+007A (z) + { 0x38, 0x0C, 0x0C, 0x07, 0x0C, 0x0C, 0x38, 0x00}, // U+007B ({) + { 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00}, // U+007C (|) + { 0x07, 0x0C, 0x0C, 0x38, 0x0C, 0x0C, 0x07, 0x00}, // U+007D (}) + { 0x6E, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+007E (~) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} // U+007F +}; + diff --git a/MCUME_teensy/teensygnuboy/hw.c b/MCUME_teensy/teensygnuboy/hw.c new file mode 100644 index 0000000..5d7c6ca --- /dev/null +++ b/MCUME_teensy/teensygnuboy/hw.c @@ -0,0 +1,181 @@ + + + +#include "defs.h" +#include "cpu.h" +#include "hw.h" +#include "regs.h" +#include "lcd.h" +#include "mem.h" + + +struct hw hw; + + + +/* + * hw_interrupt changes the virtual interrupt lines included in the + * specified mask to the values the corresponding bits in i take, and + * in doing so, raises the appropriate bit of R_IF for any interrupt + * lines that transition from low to high. + */ + +void hw_interrupt(byte i, byte mask) +{ + byte oldif = R_IF; + i &= 0x1F & mask; + R_IF |= i & (hw.ilines ^ i); + + /* FIXME - is this correct? not sure the docs understand... */ + if ((R_IF & (R_IF ^ oldif) & R_IE) && cpu.ime) cpu.halt = 0; + /* if ((i & (hw.ilines ^ i) & R_IE) && cpu.ime) cpu.halt = 0; */ + /* if ((i & R_IE) && cpu.ime) cpu.halt = 0; */ + + hw.ilines &= ~mask; + hw.ilines |= i; +} + + +/* + * hw_dma performs plain old memory-to-oam dma, the original dmg + * dma. Although on the hardware it takes a good deal of time, the cpu + * continues running during this mode of dma, so no special tricks to + * stall the cpu are necessary. + */ + +void hw_dma(byte b) +{ + int i; + addr a; + + a = ((addr)b) << 8; + for (i = 0; i < XRES; i++, a++) + lcd.oam.mem[i] = readb(a); +} + + + +void hw_hdma_cmd(byte c) +{ + int cnt; + addr sa; + int da; + + /* Begin or cancel HDMA */ + if ((hw.hdma|c) & 0x80) + { + hw.hdma = c; + R_HDMA5 = c & 0x7f; + return; + } + + /* Perform GDMA */ + sa = ((addr)R_HDMA1 << 8) | (R_HDMA2&0xf0); + da = 0x8000 | ((int)(R_HDMA3&0x1f) << 8) | (R_HDMA4&0xf0); + cnt = ((int)c)+1; + /* FIXME - this should use cpu time! */ + /*cpu_timers(102 * cnt);*/ + cnt <<= 4; + while (cnt--) + writeb(da++, readb(sa++)); + R_HDMA1 = sa >> 8; + R_HDMA2 = sa & 0xF0; + R_HDMA3 = 0x1F & (da >> 8); + R_HDMA4 = da & 0xF0; + R_HDMA5 = 0xFF; +} + + +void hw_hdma() +{ + int cnt; + addr sa; + int da; + + sa = ((addr)R_HDMA1 << 8) | (R_HDMA2&0xf0); + da = 0x8000 | ((int)(R_HDMA3&0x1f) << 8) | (R_HDMA4&0xf0); + cnt = 16; + while (cnt--) + writeb(da++, readb(sa++)); + R_HDMA1 = sa >> 8; + R_HDMA2 = sa & 0xF0; + R_HDMA3 = 0x1F & (da >> 8); + R_HDMA4 = da & 0xF0; + R_HDMA5--; + hw.hdma--; +} + + +/* + * pad_refresh updates the P1 register from the pad states, generating + * the appropriate interrupts (by quickly raising and lowering the + * interrupt line) if a transition has been made. + */ + +void pad_refresh() +{ + byte oldp1; + oldp1 = R_P1; + R_P1 &= 0x30; + R_P1 |= 0xc0; + if (!(R_P1 & 0x10)) + R_P1 |= (hw.pad & 0x0F); + if (!(R_P1 & 0x20)) + R_P1 |= (hw.pad >> 4); + R_P1 ^= 0x0F; + if (oldp1 & ~R_P1 & 0x0F) + { + hw_interrupt(IF_PAD, IF_PAD); + hw_interrupt(0, IF_PAD); + } +} + + +/* + * These simple functions just update the state of a button on the + * pad. + */ + +void pad_press(byte k) +{ + if (hw.pad & k) + return; + hw.pad |= k; + pad_refresh(); +} + +void pad_release(byte k) +{ + if (!(hw.pad & k)) + return; + hw.pad &= ~k; + pad_refresh(); +} + +void pad_set(byte k, int st) +{ + st ? pad_press(k) : pad_release(k); +} + +void hw_reset() +{ + hw.ilines = hw.pad = 0; + + memset(ram.hi, 0, sizeof ram.hi); + + R_P1 = 0xFF; + R_LCDC = 0x91; + R_BGP = 0xFC; + R_OBP0 = 0xFF; + R_OBP1 = 0xFF; + R_SVBK = 0x01; + R_HDMA5 = 0xFF; + R_VBK = 0xFE; +} + + + + + + + diff --git a/MCUME_teensy/teensygnuboy/hw.h b/MCUME_teensy/teensygnuboy/hw.h new file mode 100644 index 0000000..65e61f3 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/hw.h @@ -0,0 +1,41 @@ + + + +#ifndef __HW_H__ +#define __HW_H__ + + +#include "defs.h" + + +#define PAD_RIGHT 0x01 +#define PAD_LEFT 0x02 +#define PAD_UP 0x04 +#define PAD_DOWN 0x08 +#define PAD_A 0x10 +#define PAD_B 0x20 +#define PAD_SELECT 0x40 +#define PAD_START 0x80 + +#define IF_VBLANK 0x01 +#define IF_STAT 0x02 +#define IF_TIMER 0x04 +#define IF_SERIAL 0x08 +#define IF_PAD 0x10 + +struct hw +{ + byte ilines; + byte pad; + int cgb, gba; + int hdma; +}; + + +extern struct hw hw; + +extern void hw_reset(); + +#endif + + diff --git a/MCUME_teensy/teensygnuboy/iopins.h b/MCUME_teensy/teensygnuboy/iopins.h new file mode 100644 index 0000000..f57086c --- /dev/null +++ b/MCUME_teensy/teensygnuboy/iopins.h @@ -0,0 +1,98 @@ +#ifndef IOPINS_H +#define IOPINS_H + +//#define OLD_LAYOUT 1 + +#include "tft_t_dma_config.h" + +#ifndef OLD_LAYOUT + +#ifdef ST7789 +// ST7789 +#define TFT_SCLK 13 +#define TFT_MOSI 11 +#define TFT_MISO 12 +#define TFT_TOUCH_CS 255 +#define TFT_TOUCH_INT 255 +#define TFT_DC 9 +#define TFT_CS 255 +#define TFT_RST 23 +#else +// ILI9341 +#define TFT_SCLK 13 +#define TFT_MOSI 11 +#define TFT_MISO 12 +#define TFT_TOUCH_CS 255 //38 +#define TFT_TOUCH_INT 255 //37 +#define TFT_DC 9 +#define TFT_CS 23 +#define TFT_RST 255 +#endif + +// PSRAM +#define PSRAM_CS 36 +#define PSRAM_MOSI 35 +#define PSRAM_MISO 34 +#define PSRAM_SCLK 37 + +// SD +#define SD_SCLK 13 +#define SD_MOSI 11 +#define SD_MISO 12 +//#define SD_CS BUILTIN_SDCARD +#define SD_CS 5 + +// I2C keyboard +#define I2C_SCL_IO 19 +#define I2C_SDA_IO 18 + +// Analog joystick (primary) for JOY2 and 5 extra buttons +#define PIN_JOY2_A1X A1 +#define PIN_JOY2_A2Y A2 +#define PIN_JOY2_BTN 17 +#define PIN_KEY_USER1 3 //34 +#define PIN_KEY_USER2 4 //35 +//#define PIN_KEY_USER3 255 +//#define PIN_KEY_USER4 255 + + +#else // OLD LAYOUT!!!! + +#define HAS_VGA 1 + +// ILI9341 +#define TFT_SCLK 13 +#define TFT_MOSI 11 +#define TFT_MISO 12 +#define TFT_TOUCH_CS 38 +#define TFT_TOUCH_INT 37 +#define TFT_DC 9 +#define TFT_CS 10 +#define TFT_RST 255 //connected to 3.3V + +// I2C keyboard +#define I2C_SCL_IO 3 +#define I2C_SDA_IO 4 + +// Analog joystick (primary) for JOY2 and 5 extra buttons +#define PIN_JOY2_A1X A12 +#define PIN_JOY2_A2Y A13 +#define PIN_JOY2_BTN 36 +#define PIN_KEY_USER1 35 +#define PIN_KEY_USER2 34 +#define PIN_KEY_USER3 33 +#define PIN_KEY_USER4 39 + +// Second joystick +#define PIN_JOY1_BTN 30 +#define PIN_JOY1_1 16 +#define PIN_JOY1_2 17 +#define PIN_JOY1_3 18 +#define PIN_JOY1_4 19 +#endif + +#endif + + + + diff --git a/MCUME_teensy/teensygnuboy/keyboard_osd.h b/MCUME_teensy/teensygnuboy/keyboard_osd.h new file mode 100644 index 0000000..062eb4e --- /dev/null +++ b/MCUME_teensy/teensygnuboy/keyboard_osd.h @@ -0,0 +1,20 @@ + +#ifndef keyboard_osd_h_ +#define keyboard_osd_h_ + +extern bool virtualkeyboardIsActive(void); +extern void drawVirtualkeyboard(void); +extern void toggleVirtualkeyboard(bool keepOn); +extern void handleVirtualkeyboard(void); + +extern bool callibrationActive(void); +extern int handleCallibration(uint16_t bClick); + +extern bool menuActive(void); +extern char * menuSelection(void); +extern void toggleMenu(bool on); +extern int handleMenu(uint16_t bClick); + + +#endif + diff --git a/MCUME_teensy/teensygnuboy/lcd.c b/MCUME_teensy/teensygnuboy/lcd.c new file mode 100644 index 0000000..8e79ff4 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/lcd.c @@ -0,0 +1,683 @@ +#include "defs.h" +#include "regs.h" +#include "hw.h" +#include "mem.h" +#include "lcd.h" +#include "rc.h" +#ifdef USE_ASM +#include "asm.h" +#endif +#include "memory.h" + +struct lcd lcd; + +struct scan scan; + +#define BG (scan.bg) +#define WND (scan.wnd) +#define BUF (scan.buf) +#define PRI (scan.pri) + +#define PAL2 (scan.pal2) + +#define VS (scan.vs) /* vissprites */ +#define NS (scan.ns) + +#define L (scan.l) /* line */ +#define X (scan.x) /* screen position */ +#define Y (scan.y) +#define S (scan.s) /* tilemap position */ +#define T (scan.t) +#define U (scan.u) /* position within tile */ +#define V (scan.v) +#define WX (scan.wx) +#define WY (scan.wy) +#define WT (scan.wt) +#define WV (scan.wv) + + + +byte patpix[4096][8][8]; +byte patdirty[1024]; +byte anydirty; + + +static int sprsort = 1; +static int sprdebug; + +#define DEF_PAL { 0x98d0e0, 0x68a0b0, 0x60707C, 0x2C3C3C } + +static int dmg_pal[4][4] = { DEF_PAL, DEF_PAL, DEF_PAL, DEF_PAL }; + + +static uint16 line_buf[200]; +static raster_line = 0; + + +#ifdef ALLOW_UNALIGNED_IO /* long long is ok since this is i386-only anyway? */ +#define MEMCPY8(d, s) ((*(long long *)(d)) = (*(long long *)(s))) +#else +#define MEMCPY8(d, s) memcpy((d), (s), 8) +#endif + + + + +#ifndef ASM_UPDATEPATPIX +void updatepatpix() +{ + int i, j, k; + int a, c; + byte *vram = lcd.vbank[0]; + + if (!anydirty) return; + for (i = 0; i < 1024; i++) + { + if (i == 384) i = 512; + if (i == 896) break; + if (!patdirty[i]) continue; + patdirty[i] = 0; + for (j = 0; j < 8; j++) + { + a = ((i<<4) | (j<<1)); + for (k = 0; k < 8; k++) + { + c = vram[a] & (1<> 3) + 1; + + if (hw.cgb) + { + if (R_LCDC & 0x10) + for (i = cnt; i > 0; i--) + { + *(tilebuf++) = *tilemap + | (((int)*attrmap & 0x08) << 6) + | (((int)*attrmap & 0x60) << 5); + *(tilebuf++) = (((int)*attrmap & 0x07) << 2); + attrmap += *wrap + 1; + tilemap += *(wrap++) + 1; + } + else + for (i = cnt; i > 0; i--) + { + *(tilebuf++) = (256 + ((n8)*tilemap)) + | (((int)*attrmap & 0x08) << 6) + | (((int)*attrmap & 0x60) << 5); + *(tilebuf++) = (((int)*attrmap & 0x07) << 2); + attrmap += *wrap + 1; + tilemap += *(wrap++) + 1; + } + } + else + { + if (R_LCDC & 0x10) + for (i = cnt; i > 0; i--) + { + *(tilebuf++) = *(tilemap++); + tilemap += *(wrap++); + } + else + for (i = cnt; i > 0; i--) + { + *(tilebuf++) = (256 + ((n8)*(tilemap++))); + tilemap += *(wrap++); + } + } + + if (WX >= XRES) return; + + base = ((R_LCDC&0x40)?0x1C00:0x1800) + (WT<<5); + tilemap = lcd.vbank[0] + base; + attrmap = lcd.vbank[1] + base; + tilebuf = WND; + cnt = ((XRES - WX) >> 3) + 1; + + if (hw.cgb) + { + if (R_LCDC & 0x10) + for (i = cnt; i > 0; i--) + { + *(tilebuf++) = *(tilemap++) + | (((int)*attrmap & 0x08) << 6) + | (((int)*attrmap & 0x60) << 5); + *(tilebuf++) = (((int)*(attrmap++)&7) << 2); + } + else + for (i = cnt; i > 0; i--) + { + *(tilebuf++) = (256 + ((n8)*(tilemap++))) + | (((int)*attrmap & 0x08) << 6) + | (((int)*attrmap & 0x60) << 5); + *(tilebuf++) = (((int)*(attrmap++)&7) << 2); + } + } + else + { + if (R_LCDC & 0x10) + for (i = cnt; i > 0; i--) + *(tilebuf++) = *(tilemap++); + else + for (i = cnt; i > 0; i--) + *(tilebuf++) = (256 + ((n8)*(tilemap++))); + } +} + + +void bg_scan() +{ + int cnt; + byte *src, *dest; + int *tile; + + if (WX <= 0) return; + cnt = WX; + tile = BG; + dest = BUF; + + src = patpix[*(tile++)][V] + U; + memcpy(dest, src, 8-U); + dest += 8-U; + cnt -= 8-U; + if (cnt <= 0) return; + while (cnt >= 8) + { + src = patpix[*(tile++)][V]; + MEMCPY8(dest, src); + dest += 8; + cnt -= 8; + } + src = patpix[*tile][V]; + while (cnt--) + *(dest++) = *(src++); +} + +void wnd_scan() +{ + int cnt; + byte *src, *dest; + int *tile; + + if (WX >= XRES) return; + cnt = XRES - WX; + tile = WND; + dest = BUF + WX; + + while (cnt >= 8) + { + src = patpix[*(tile++)][WV]; + MEMCPY8(dest, src); + dest += 8; + cnt -= 8; + } + src = patpix[*tile][WV]; + while (cnt--) + *(dest++) = *(src++); +} + +static void blendcpy(byte *dest, byte *src, byte b, int cnt) +{ + while (cnt--) *(dest++) = *(src++) | b; +} + +static int priused(void *attr) +{ + un32 *a = attr; + return (int)((a[0]|a[1]|a[2]|a[3]|a[4]|a[5]|a[6]|a[7])&0x80808080); +} + +void bg_scan_pri() +{ + int cnt, i; + byte *src, *dest; + + if (WX <= 0) return; + i = S; + cnt = WX; + dest = PRI; + src = lcd.vbank[1] + ((R_LCDC&0x08)?0x1C00:0x1800) + (T<<5); + + if (!priused(src)) + { + memset(dest, 0, cnt); + return; + } + + memset(dest, src[i++&31]&128, 8-U); + dest += 8-U; + cnt -= 8-U; + if (cnt <= 0) return; + while (cnt >= 8) + { + memset(dest, src[i++&31]&128, 8); + dest += 8; + cnt -= 8; + } + memset(dest, src[i&31]&128, cnt); +} + +void wnd_scan_pri() +{ + int cnt, i; + byte *src, *dest; + + if (WX >= XRES) return; + i = 0; + cnt = XRES - WX; + dest = PRI + WX; + src = lcd.vbank[1] + ((R_LCDC&0x40)?0x1C00:0x1800) + (WT<<5); + + if (!priused(src)) + { + memset(dest, 0, cnt); + return; + } + + while (cnt >= 8) + { + memset(dest, src[i++]&128, 8); + dest += 8; + cnt -= 8; + } + memset(dest, src[i]&128, cnt); +} + +#ifndef ASM_BG_SCAN_COLOR +void bg_scan_color() +{ + int cnt; + byte *src, *dest; + int *tile; + + if (WX <= 0) return; + cnt = WX; + tile = BG; + dest = BUF; + + src = patpix[*(tile++)][V] + U; + blendcpy(dest, src, *(tile++), 8-U); + dest += 8-U; + cnt -= 8-U; + if (cnt <= 0) return; + while (cnt >= 8) + { + src = patpix[*(tile++)][V]; + blendcpy(dest, src, *(tile++), 8); + dest += 8; + cnt -= 8; + } + src = patpix[*(tile++)][V]; + blendcpy(dest, src, *(tile++), cnt); +} +#endif + +void wnd_scan_color() +{ + int cnt; + byte *src, *dest; + int *tile; + + if (WX >= XRES) return; + cnt = XRES - WX; + tile = WND; + dest = BUF + WX; + + while (cnt >= 8) + { + src = patpix[*(tile++)][WV]; + blendcpy(dest, src, *(tile++), 8); + dest += 8; + cnt -= 8; + } + src = patpix[*(tile++)][WV]; + blendcpy(dest, src, *(tile++), cnt); +} + +static void recolor(byte *buf, byte fill, int cnt) +{ + while (cnt--) *(buf++) |= fill; +} + +void spr_count() +{ + int i; + struct obj *o; + + NS = 0; + if (!(R_LCDC & 0x02)) return; + + o = lcd.oam.obj; + + for (i = 40; i; i--, o++) + { + if (L >= o->y || L + 16 < o->y) + continue; + if (L + 8 >= o->y && !(R_LCDC & 0x04)) + continue; + if (++NS == 10) break; + } +} + +void spr_enum() +{ + int i, j; + struct obj *o; + struct vissprite ts[10]; + int v, pat; + int l, x; + + NS = 0; + if (!(R_LCDC & 0x02)) return; + + o = lcd.oam.obj; + + for (i = 40; i; i--, o++) + { + if (L >= o->y || L + 16 < o->y) + continue; + if (L + 8 >= o->y && !(R_LCDC & 0x04)) + continue; + VS[NS].x = (int)o->x - 8; + v = L - (int)o->y + 16; + if (hw.cgb) + { + pat = o->pat | (((int)o->flags & 0x60) << 5) + | (((int)o->flags & 0x08) << 6); + VS[NS].pal = 32 + ((o->flags & 0x07) << 2); + } + else + { + pat = o->pat | (((int)o->flags & 0x60) << 5); + VS[NS].pal = 32 + ((o->flags & 0x10) >> 2); + } + VS[NS].pri = (o->flags & 0x80) >> 7; + if ((R_LCDC & 0x04)) + { + pat &= ~1; + if (v >= 8) + { + v -= 8; + pat++; + } + if (o->flags & 0x40) pat ^= 1; + } + VS[NS].buf = patpix[pat][v]; + if (++NS == 10) break; + } + if (!sprsort || hw.cgb) return; + /* not quite optimal but it finally works! */ + for (i = 0; i < NS; i++) + { + l = 0; + x = VS[0].x; + for (j = 1; j < NS; j++) + { + if (VS[j].x < x) + { + l = j; + x = VS[j].x; + } + } + ts[i] = VS[l]; + VS[l].x = XRES; + } + memcpy(VS, ts, sizeof VS); +} + +void spr_scan() +{ + int i, x; + byte pal, b, ns = NS; + byte *src, *dest, *bg, *pri; + struct vissprite *vs; + static byte bgdup[256]; + + if (!ns) return; + + memcpy(bgdup, BUF, 256); + vs = &VS[ns-1]; + + for (; ns; ns--, vs--) + { + x = vs->x; + if (x >= XRES) continue; + if (x <= -8) continue; + if (x < 0) + { + src = vs->buf - x; + dest = BUF; + i = 8 + x; + } + else + { + src = vs->buf; + dest = BUF + x; + if (x > 152) i = XRES - x; + else i = 8; + } + pal = vs->pal; + if (vs->pri) + { + bg = bgdup + (dest - BUF); + while (i--) + { + b = src[i]; + if (b && !(bg[i]&3)) dest[i] = pal|b; + } + } + else if (hw.cgb) + { + bg = bgdup + (dest - BUF); + pri = PRI + (dest - BUF); + while (i--) + { + b = src[i]; + if (b && (!pri[i] || !(bg[i]&3))) + dest[i] = pal|b; + } + } + else while (i--) if (src[i]) dest[i] = pal|src[i]; + /* else while (i--) if (src[i]) dest[i] = 31 + ns; */ + } + if (sprdebug) for (i = 0; i < NS; i++) BUF[i<<1] = 36; +} + + + + + + +void lcd_begin() +{ + raster_line = 0; +} + + + +void lcd_refreshline() +{ + if (!(R_LCDC & 0x80)) + return; /* should not happen... */ + + updatepatpix(); + + L = R_LY; + X = R_SCX; + Y = (R_SCY + L) & 0xff; + S = X >> 3; + T = Y >> 3; + U = X & 7; + V = Y & 7; + + WX = R_WX - 7; + if (WY>L || WY<0 || WY>143 || WX<-7 || WX>159 || !(R_LCDC&0x20)) + WX = XRES; + WT = (L - WY) >> 3; + WV = (L - WY) & 7; + + spr_enum(); + + tilebuf(); + if (hw.cgb) + { + bg_scan_color(); + wnd_scan_color(); + if (NS) + { + bg_scan_pri(); + wnd_scan_pri(); + } + } + else + { + bg_scan(); + wnd_scan(); + recolor(BUF+WX, 0x04, XRES-WX); + } + spr_scan(); + + for (int i=0;i> 2; + b = (c & 0x7C00) >> 7; + +#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) ) + + PAL2[i] = RGBVAL16(r,g,b); +} + +void pal_write(int i, byte b) +{ + if (lcd.pal[i] == b) return; + lcd.pal[i] = b; + updatepalette(i>>1); +} + +void pal_write_dmg(int i, int mapnum, byte d) +{ + int j; + int *cmap = dmg_pal[mapnum]; + int c, r, g, b; + + if (hw.cgb) return; + + /* if (mapnum >= 2) d = 0xe4; */ + for (j = 0; j < 8; j += 2) + { + c = cmap[(d >> j) & 3]; + r = (c & 0xf8) >> 3; + g = (c & 0xf800) >> 6; + b = (c & 0xf80000) >> 9; + c = r|g|b; + /* FIXME - handle directly without faking cgb */ + pal_write(i+j, c & 0xff); + pal_write(i+j+1, c >> 8); + } +} + +void vram_write(int a, byte b) +{ + lcd.vbank[R_VBK&1][a] = b; + if (a >= 0x1800) return; + patdirty[((R_VBK&1)<<9)+(a>>4)] = 1; + anydirty = 1; +} + +void vram_dirty() +{ + anydirty = 1; + memset(patdirty, 1, sizeof patdirty); +} + +void pal_dirty() +{ + int i; + if (!hw.cgb) + { + pal_write_dmg(0, 0, R_BGP); + pal_write_dmg(8, 1, R_BGP); + pal_write_dmg(64, 2, R_OBP0); + pal_write_dmg(72, 3, R_OBP1); + } + for (i = 0; i < 64; i++) + updatepalette(i); +} + +void lcd_reset() +{ + memset(&lcd, 0, sizeof lcd); + lcd_begin(); + vram_dirty(); + pal_dirty(); +} + + + + + + + + + + + + + + + + diff --git a/MCUME_teensy/teensygnuboy/lcd.h b/MCUME_teensy/teensygnuboy/lcd.h new file mode 100644 index 0000000..4062431 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/lcd.h @@ -0,0 +1,57 @@ + + +#ifndef __LCD_H__ +#define __LCD_H__ + +#include "defs.h" + +struct vissprite +{ + byte *buf; + int x; + byte pal, pri, pad[6]; +}; + +struct scan +{ + int bg[64]; + int wnd[64]; + byte buf[256]; + un16 pal2[64]; + byte pri[256]; + struct vissprite vs[16]; + int ns, l, x, y, s, t, u, v, wx, wy, wt, wv; +}; + +struct obj +{ + byte y; + byte x; + byte pat; + byte flags; +}; + +struct lcd +{ + byte vbank[2][8192]; + union + { + byte mem[256]; + struct obj obj[40]; + } oam; + byte pal[128]; +}; + +extern struct lcd lcd; +extern struct scan scan; + + +extern void lcd_reset(); +extern void lcd_begin(); + + + +#endif + + + diff --git a/MCUME_teensy/teensygnuboy/lcdc.c b/MCUME_teensy/teensygnuboy/lcdc.c new file mode 100644 index 0000000..8d6aeb1 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/lcdc.c @@ -0,0 +1,172 @@ + + +#include + +#include "defs.h" +#include "hw.h" +#include "cpu.h" +#include "regs.h" + + +#define C (cpu.lcdc) + + +/* + * stat_trigger updates the STAT interrupt line to reflect whether any + * of the conditions set to be tested (by bits 3-6 of R_STAT) are met. + * This function should be called whenever any of the following occur: + * 1) LY or LYC changes. + * 2) A state transition affects the low 2 bits of R_STAT (see below). + * 3) The program writes to the upper bits of R_STAT. + * stat_trigger also updates bit 2 of R_STAT to reflect whether LY=LYC. + */ + +void stat_trigger() +{ + static const int condbits[4] = { 0x08, 0x30, 0x20, 0x00 }; + int flag = 0; + + if ((R_LY < 0x91) && (R_LY == R_LYC)) + { + R_STAT |= 0x04; + if (R_STAT & 0x40) flag = IF_STAT; + } + else R_STAT &= ~0x04; + + if (R_STAT & condbits[R_STAT&3]) flag = IF_STAT; + + if (!(R_LCDC & 0x80)) flag = 0; + + hw_interrupt(flag, IF_STAT); +} + +void stat_write(byte b) +{ + R_STAT = (R_STAT & 0x07) | (b & 0x78); + if (!hw.cgb && !(R_STAT & 2)) /* DMG STAT write bug => interrupt */ + hw_interrupt(IF_STAT, IF_STAT); + stat_trigger(); +} + + +/* + * stat_change is called when a transition results in a change to the + * LCD STAT condition (the low 2 bits of R_STAT). It raises or lowers + * the VBLANK interrupt line appropriately and calls stat_trigger to + * update the STAT interrupt line. + */ + +static void stat_change(int stat) +{ + stat &= 3; + R_STAT = (R_STAT & 0x7C) | stat; + + if (stat != 1) hw_interrupt(0, IF_VBLANK); + /* hw_interrupt((stat == 1) ? IF_VBLANK : 0, IF_VBLANK); */ + stat_trigger(); +} + + +void lcdc_change(byte b) +{ + byte old = R_LCDC; + R_LCDC = b; + if ((R_LCDC ^ old) & 0x80) /* lcd on/off change */ + { + R_LY = 0; + stat_change(2); + C = 40; + lcd_begin(); + } +} + + +void lcdc_trans() +{ + if (!(R_LCDC & 0x80)) + { + while (C <= 0) + { + switch ((byte)(R_STAT & 3)) + { + case 0: + case 1: + stat_change(2); + C += 40; + break; + case 2: + stat_change(3); + C += 86; + break; + case 3: + stat_change(0); + if (hw.hdma & 0x80) + hw_hdma(); + else + C += 102; + break; + } + return; + } + } + while (C <= 0) + { + switch ((byte)(R_STAT & 3)) + { + case 1: + if (!(hw.ilines & IF_VBLANK)) + { + C += 218; + hw_interrupt(IF_VBLANK, IF_VBLANK); + break; + } + if (R_LY == 0) + { + lcd_begin(); + stat_change(2); + C += 40; + break; + } + else if (R_LY < 152) + C += 228; + else if (R_LY == 152) + C += 28; + else + { + R_LY = -1; + C += 200; + } + R_LY++; + stat_trigger(); + break; + case 2: + lcd_refreshline(); + stat_change(3); + C += 86; + break; + case 3: + stat_change(0); + if (hw.hdma & 0x80) + hw_hdma(); + /* FIXME -- how much of the hblank does hdma use?? */ + /* else */ + C += 102; + break; + case 0: + if (++R_LY >= YRES) + { + if (cpu.halt) + { + hw_interrupt(IF_VBLANK, IF_VBLANK); + C += 228; + } + else C += 10; + stat_change(1); + break; + } + stat_change(2); + C += 40; + break; + } + } +} diff --git a/MCUME_teensy/teensygnuboy/loader.c b/MCUME_teensy/teensygnuboy/loader.c new file mode 100644 index 0000000..70f8ea8 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/loader.c @@ -0,0 +1,125 @@ +#include +#include +#include + +#include "defs.h" +#include "regs.h" +#include "mem.h" +#include "hw.h" +#include "rtc.h" +#include "memory.h" + +#include "arduinoproto.h" + +PROGMEM static int mbc_table[256] = +{ + 0, 1, 1, 1, 0, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 3, + 3, 3, 3, 3, 0, 0, 0, 0, 0, 5, 5, 5, MBC_RUMBLE, MBC_RUMBLE, MBC_RUMBLE, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MBC_HUC3, MBC_HUC1 +}; + +PROGMEM static int rtc_table[256] = +{ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 +}; + +PROGMEM static int batt_table[256] = +{ + 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, + 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, + 0 +}; + +PROGMEM static int romsize_table[256] = +{ + 2, 4, 8, 16, 32, 64, 128, 256, 512, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 128, 128, 128 + /* 0, 0, 72, 80, 96 -- actual values but bad to use these! */ +}; + +PROGMEM static int ramsize_table[256] = +{ + 1, 1, 1, 4, 16, + 4 /* FIXME - what value should this be?! */ +}; + + + +static int forcebatt, nobatt; +static int forcedmg=0, gbamode; + +static int memfill = 0, memrand = -1; //-1,-1 + + +static void initmem(void *mem, int size) +{ + char *p = mem; + if (memrand >= 0) + { + srand(memrand ? memrand : time(0)); + while(size--) *(p++) = rand(); + } + else if (memfill >= 0) + memset(p, memfill, size); +} + + +static byte getHeaderByte(int pos) { + return read_rom(pos); +} + + +extern int loadfile(char * name); + +void loader_init(char * romfile) +{ + byte c; + int rlen; + + int len = loadfile(romfile); + c = getHeaderByte(0x0147); + mbc.type = mbc_table[c]; + mbc.batt = (batt_table[c] && !nobatt) || forcebatt; + rtc.batt = rtc_table[c]; + mbc.romsize = romsize_table[getHeaderByte(0x0148)]; + mbc.ramsize = ramsize_table[getHeaderByte(0x0149)]; + if (!mbc.romsize) die("unknown ROM size %02X\n", getHeaderByte(0x0148)); + if (!mbc.ramsize) die("unknown SRAM size %02X\n", getHeaderByte(0x0149)); + rlen = 16384 * mbc.romsize; + ram.sbank = malloc(8192 * mbc.ramsize); + initmem(ram.sbank, 8192 * mbc.ramsize); + initmem(ram.ibank, 4096 * 8); + mbc.rombank = 1; + mbc.rambank = 0; + c = getHeaderByte(0x0143); + hw.cgb = ((c == 0x80) || (c == 0xc0)) && !forcedmg; + hw.gba = (hw.cgb && gbamode); +} + diff --git a/MCUME_teensy/teensygnuboy/loader.h b/MCUME_teensy/teensygnuboy/loader.h new file mode 100644 index 0000000..e8ed6f3 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/loader.h @@ -0,0 +1,9 @@ +#ifndef __LOADER_H__ +#define __LOADER_H__ + +extern void loader_init(char *s); + + +#endif + + diff --git a/MCUME_teensy/teensygnuboy/logo.h b/MCUME_teensy/teensygnuboy/logo.h new file mode 100644 index 0000000..692a06c --- /dev/null +++ b/MCUME_teensy/teensygnuboy/logo.h @@ -0,0 +1,241 @@ +PROGMEM const uint16_t logo[] = { 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diff --git a/MCUME_teensy/teensygnuboy/mem.c b/MCUME_teensy/teensygnuboy/mem.c new file mode 100644 index 0000000..95a34c6 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/mem.c @@ -0,0 +1,578 @@ + + +#include + +#include "defs.h" +#include "hw.h" +#include "regs.h" +#include "mem.h" +#include "rtc.h" +#include "lcd.h" +#include "memory.h" + +struct mbc mbc; +struct ram ram; + + +/* + * In order to make reads and writes efficient, we keep tables + * (indexed by the high nibble of the address) specifying which + * regions can be read/written without a function call. For such + * ranges, the pointer in the map table points to the base of the + * region in host system memory. For ranges that require special + * processing, the pointer is NULL. + * + * mem_updatemap is called whenever bank changes or other operations + * make the old maps potentially invalid. + */ + +void mem_updatemap() +{ + int n; + byte **map; + map = mbc.rmap; + map[0x0] = NULL; //rom.bank[0]; + map[0x1] = NULL; //rom.bank[0]; + map[0x2] = NULL; //rom.bank[0]; + map[0x3] = NULL; //rom.bank[0]; + //if (mbc.rombank < mbc.romsize) + //{ + // map[0x4] = rom.bank[mbc.rombank] - 0x4000; + // map[0x5] = rom.bank[mbc.rombank] - 0x4000; + // map[0x6] = rom.bank[mbc.rombank] - 0x4000; + // map[0x7] = rom.bank[mbc.rombank] - 0x4000; + //} + //else { + map[0x4] = map[0x5] = map[0x6] = map[0x7] = NULL; + //} + if (0 && (R_STAT & 0x03) == 0x03) + { + map[0x8] = NULL; + map[0x9] = NULL; + } + else + { + map[0x8] = lcd.vbank[R_VBK & 1] - 0x8000; + map[0x9] = lcd.vbank[R_VBK & 1] - 0x8000; + } + if (mbc.enableram && !(rtc.sel&8)) + { + map[0xA] = ram.sbank[mbc.rambank] - 0xA000; + map[0xB] = ram.sbank[mbc.rambank] - 0xA000; + } + else map[0xA] = map[0xB] = NULL; + + map[0xC] = ram.ibank[0] - 0xC000; + n = R_SVBK & 0x07; + map[0xD] = ram.ibank[n?n:1] - 0xD000; + map[0xE] = ram.ibank[0] - 0xE000; + map[0xF] = NULL; + + map = mbc.wmap; + map[0x0] = map[0x1] = map[0x2] = map[0x3] = NULL; + map[0x4] = map[0x5] = map[0x6] = map[0x7] = NULL; + map[0x8] = map[0x9] = NULL; + if (mbc.enableram && !(rtc.sel&8)) + { + map[0xA] = ram.sbank[mbc.rambank] - 0xA000; + map[0xB] = ram.sbank[mbc.rambank] - 0xA000; + } + else map[0xA] = map[0xB] = NULL; + map[0xC] = ram.ibank[0] - 0xC000; + n = R_SVBK & 0x07; + map[0xD] = ram.ibank[n?n:1] - 0xD000; + map[0xE] = ram.ibank[0] - 0xE000; + map[0xF] = NULL; +} + + +/* + * ioreg_write handles output to io registers in the FF00-FF7F,FFFF + * range. It takes the register number (low byte of the address) and a + * byte value to be written. + */ + +void ioreg_write(byte r, byte b) +{ + if (!hw.cgb) + { + switch (r) + { + case RI_VBK: + case RI_BCPS: + case RI_OCPS: + case RI_BCPD: + case RI_OCPD: + case RI_SVBK: + case RI_KEY1: + case RI_HDMA1: + case RI_HDMA2: + case RI_HDMA3: + case RI_HDMA4: + case RI_HDMA5: + return; + } + } + + switch(r) + { + case RI_TIMA: + case RI_TMA: + case RI_TAC: + case RI_SCY: + case RI_SCX: + case RI_WY: + case RI_WX: + REG(r) = b; + break; + case RI_BGP: + if (R_BGP == b) break; + pal_write_dmg(0, 0, b); + pal_write_dmg(8, 1, b); + R_BGP = b; + break; + case RI_OBP0: + if (R_OBP0 == b) break; + pal_write_dmg(64, 2, b); + R_OBP0 = b; + break; + case RI_OBP1: + if (R_OBP1 == b) break; + pal_write_dmg(72, 3, b); + R_OBP1 = b; + break; + case RI_IF: + case RI_IE: + REG(r) = b & 0x1F; + break; + case RI_P1: + REG(r) = b; + pad_refresh(); + break; + case RI_SC: + /* FIXME - this is a hack for stupid roms that probe serial */ + if ((b & 0x81) == 0x81) + { + R_SB = 0xff; + hw_interrupt(IF_SERIAL, IF_SERIAL); + hw_interrupt(0, IF_SERIAL); + } + R_SC = b; /* & 0x7f; */ + break; + case RI_DIV: + REG(r) = 0; + break; + case RI_LCDC: + lcdc_change(b); + break; + case RI_STAT: + stat_write(b); + break; + case RI_LYC: + REG(r) = b; + stat_trigger(); + break; + case RI_VBK: + REG(r) = b | 0xFE; + mem_updatemap(); + break; + case RI_BCPS: + R_BCPS = b & 0xBF; + R_BCPD = lcd.pal[b & 0x3F]; + break; + case RI_OCPS: + R_OCPS = b & 0xBF; + R_OCPD = lcd.pal[64 + (b & 0x3F)]; + break; + case RI_BCPD: + R_BCPD = b; + pal_write(R_BCPS & 0x3F, b); + if (R_BCPS & 0x80) R_BCPS = (R_BCPS+1) & 0xBF; + break; + case RI_OCPD: + R_OCPD = b; + pal_write(64 + (R_OCPS & 0x3F), b); + if (R_OCPS & 0x80) R_OCPS = (R_OCPS+1) & 0xBF; + break; + case RI_SVBK: + REG(r) = b & 0x07; + mem_updatemap(); + break; + case RI_DMA: + hw_dma(b); + break; + case RI_KEY1: + REG(r) = (REG(r) & 0x80) | (b & 0x01); + break; + case RI_HDMA1: + REG(r) = b; + break; + case RI_HDMA2: + REG(r) = b & 0xF0; + break; + case RI_HDMA3: + REG(r) = b & 0x1F; + break; + case RI_HDMA4: + REG(r) = b & 0xF0; + break; + case RI_HDMA5: + hw_hdma_cmd(b); + break; + } + switch (r) + { + case RI_BGP: + case RI_OBP0: + case RI_OBP1: + /* printf("palette reg %02X write %02X at LY=%02X\n", r, b, R_LY); */ + case RI_HDMA1: + case RI_HDMA2: + case RI_HDMA3: + case RI_HDMA4: + case RI_HDMA5: + /* printf("HDMA %d: %02X\n", r - RI_HDMA1 + 1, b); */ + break; + } + /* printf("reg %02X => %02X (%02X)\n", r, REG(r), b); */ +} + + +byte ioreg_read(byte r) +{ + switch(r) + { + case RI_SC: + r = R_SC; + R_SC &= 0x7f; + return r; + case RI_P1: + case RI_SB: + case RI_DIV: + case RI_TIMA: + case RI_TMA: + case RI_TAC: + case RI_LCDC: + case RI_STAT: + case RI_SCY: + case RI_SCX: + case RI_LY: + case RI_LYC: + case RI_BGP: + case RI_OBP0: + case RI_OBP1: + case RI_WY: + case RI_WX: + case RI_IE: + case RI_IF: + return REG(r); + case RI_VBK: + case RI_BCPS: + case RI_OCPS: + case RI_BCPD: + case RI_OCPD: + case RI_SVBK: + case RI_KEY1: + case RI_HDMA1: + case RI_HDMA2: + case RI_HDMA3: + case RI_HDMA4: + case RI_HDMA5: + if (hw.cgb) return REG(r); + default: + return 0xff; + } +} + + + +/* + * Memory bank controllers typically intercept write attempts to + * 0000-7FFF, using the address and byte written as instructions to + * change rom or sram banks, control special hardware, etc. + * + * mbc_write takes an address (which should be in the proper range) + * and a byte value written to the address. + */ + +void mbc_write(int a, byte b) +{ + byte ha = (a>>12); + + /* printf("mbc %d: rom bank %02X -[%04X:%02X]-> ", mbc.type, mbc.rombank, a, b); */ + switch (mbc.type) + { + case MBC_MBC1: + switch (ha & 0xE) + { + case 0x0: + mbc.enableram = ((b & 0x0F) == 0x0A); + break; + case 0x2: + if ((b & 0x1F) == 0) b = 0x01; + mbc.rombank = (mbc.rombank & 0x60) | (b & 0x1F); + break; + case 0x4: + if (mbc.model) + { + mbc.rambank = b & 0x03; + break; + } + mbc.rombank = (mbc.rombank & 0x1F) | ((int)(b&3)<<5); + break; + case 0x6: + mbc.model = b & 0x1; + break; + } + break; + case MBC_MBC2: /* is this at all right? */ + if ((a & 0x0100) == 0x0000) + { + mbc.enableram = ((b & 0x0F) == 0x0A); + break; + } + if ((a & 0xE100) == 0x2100) + { + mbc.rombank = b & 0x0F; + break; + } + break; + case MBC_MBC3: + switch (ha & 0xE) + { + case 0x0: + mbc.enableram = ((b & 0x0F) == 0x0A); + break; + case 0x2: + if ((b & 0x7F) == 0) b = 0x01; + mbc.rombank = b & 0x7F; + break; + case 0x4: + rtc.sel = b & 0x0f; + mbc.rambank = b & 0x03; + break; + case 0x6: + rtc_latch(b); + break; + } + break; + case MBC_RUMBLE: + switch (ha & 0xF) + { + case 0x4: + case 0x5: + /* FIXME - save high bit as rumble state */ + /* mask off high bit */ + b &= 0x7; + break; + } + /* fall thru */ + case MBC_MBC5: + switch (ha & 0xF) + { + case 0x0: + case 0x1: + mbc.enableram = ((b & 0x0F) == 0x0A); + break; + case 0x2: + if ((b & 0xFF) == 0) b = 0x01; + mbc.rombank = (mbc.rombank & 0x100) | (b & 0xFF); + break; + case 0x3: + mbc.rombank = (mbc.rombank & 0xFF) | ((int)(b&1)<<8); + break; + case 0x4: + case 0x5: + mbc.rambank = b & 0x0f; + break; + } + break; + case MBC_HUC1: /* FIXME - this is all guesswork -- is it right??? */ + switch (ha & 0xE) + { + case 0x0: + mbc.enableram = ((b & 0x0F) == 0x0A); + break; + case 0x2: + if ((b & 0x1F) == 0) b = 0x01; + mbc.rombank = (mbc.rombank & 0x60) | (b & 0x1F); + break; + case 0x4: + if (mbc.model) + { + mbc.rambank = b & 0x03; + break; + } + mbc.rombank = (mbc.rombank & 0x1F) | ((int)(b&3)<<5); + break; + case 0x6: + mbc.model = b & 0x1; + break; + } + break; + case MBC_HUC3: + switch (ha & 0xE) + { + case 0x0: + mbc.enableram = ((b & 0x0F) == 0x0A); + break; + case 0x2: + b &= 0x7F; + mbc.rombank = b ? b : 1; + break; + case 0x4: + rtc.sel = b & 0x0f; + mbc.rambank = b & 0x03; + break; + case 0x6: + rtc_latch(b); + break; + } + break; + } + mbc.rombank &= (mbc.romsize - 1); + mbc.rambank &= (mbc.ramsize - 1); + /* printf("%02X\n", mbc.rombank); */ + mem_updatemap(); +} + + +/* + * mem_write is the basic write function. Although it should only be + * called when the write map contains a NULL for the requested address + * region, it accepts writes to any address. + */ + +void mem_write(int a, byte b) +{ + int n; + byte ha = (a>>12) & 0xE; + + /* printf("write to 0x%04X: 0x%02X\n", a, b); */ + switch (ha) + { + case 0x0: + case 0x2: + case 0x4: + case 0x6: + mbc_write(a, b); + break; + case 0x8: + /* if ((R_STAT & 0x03) == 0x03) break; */ + vram_write(a & 0x1FFF, b); + break; + case 0xA: + if (!mbc.enableram) break; + if (rtc.sel&8) + { + rtc_write(b); + break; + } + ram.sbank[mbc.rambank][a & 0x1FFF] = b; + break; + case 0xC: + if ((a & 0xF000) == 0xC000) + { + ram.ibank[0][a & 0x0FFF] = b; + break; + } + n = R_SVBK & 0x07; + ram.ibank[n?n:1][a & 0x0FFF] = b; + break; + case 0xE: + if (a < 0xFE00) + { + mem_write(a & 0xDFFF, b); + break; + } + if ((a & 0xFF00) == 0xFE00) + { + /* if (R_STAT & 0x02) break; */ + if (a < 0xFEA0) lcd.oam.mem[a & 0xFF] = b; + break; + } + /* return writehi(a & 0xFF, b); */ + if (a >= 0xFF10 && a <= 0xFF3F) + { + sound_write(a & 0xFF, b); + break; + } + if ((a & 0xFF80) == 0xFF80 && a != 0xFFFF) + { + ram.hi[a & 0xFF] = b; + break; + } + ioreg_write(a & 0xFF, b); + } +} + + +/* + * mem_read is the basic read function...not useful for much anymore + * with the read map, but it's still necessary for the final messy + * region. + */ + +byte mem_read(int a) +{ + int n; + byte ha = (a>>12) & 0xE; + + /* printf("read %04x\n", a); */ + switch (ha) + { + case 0x0: + case 0x2: + return read_rom(a);//rom.bank[0][a]; + case 0x4: + case 0x6: + return read_rom(0x4000*mbc.rombank+(a & 0x3FFF)); //rom.bank[mbc.rombank][a & 0x3FFF]; + case 0x8: + /* if ((R_STAT & 0x03) == 0x03) return 0xFF; */ + return lcd.vbank[R_VBK&1][a & 0x1FFF]; + case 0xA: + if (!mbc.enableram && mbc.type == MBC_HUC3) + return 0x01; + if (!mbc.enableram) + return 0xFF; + if (rtc.sel&8) + return rtc.regs[rtc.sel&7]; + return ram.sbank[mbc.rambank][a & 0x1FFF]; + case 0xC: + if ((a & 0xF000) == 0xC000) + return ram.ibank[0][a & 0x0FFF]; + n = R_SVBK & 0x07; + return ram.ibank[n?n:1][a & 0x0FFF]; + case 0xE: + if (a < 0xFE00) return mem_read(a & 0xDFFF); + if ((a & 0xFF00) == 0xFE00) + { + /* if (R_STAT & 0x02) return 0xFF; */ + if (a < 0xFEA0) return lcd.oam.mem[a & 0xFF]; + return 0xFF; + } + /* return readhi(a & 0xFF); */ + if (a == 0xFFFF) return REG(0xFF); + if (a >= 0xFF10 && a <= 0xFF3F) + return sound_read(a & 0xFF); + if ((a & 0xFF80) == 0xFF80) + return ram.hi[a & 0xFF]; + return ioreg_read(a & 0xFF); + } + return 0xff; /* not reached */ +} + +void mbc_reset() +{ + mbc.rombank = 1; + mbc.rambank = 0; + mbc.enableram = 0; + mem_updatemap(); +} + + + + + + + diff --git a/MCUME_teensy/teensygnuboy/mem.h b/MCUME_teensy/teensygnuboy/mem.h new file mode 100644 index 0000000..ced6caa --- /dev/null +++ b/MCUME_teensy/teensygnuboy/mem.h @@ -0,0 +1,121 @@ + +#ifndef __MEM_H__ +#define __MEM_H__ + + +#include "defs.h" + + + +#define MBC_NONE 0 +#define MBC_MBC1 1 +#define MBC_MBC2 2 +#define MBC_MBC3 3 +#define MBC_MBC5 5 +#define MBC_RUMBLE 15 +#define MBC_HUC1 0xC1 +#define MBC_HUC3 0xC3 + +struct mbc +{ + int type; + int model; + int rombank; + int rambank; + int romsize; + int ramsize; + int enableram; + int batt; + byte *rmap[0x10], *wmap[0x10]; +}; + + +struct ram +{ + byte hi[256]; + byte ibank[8][4096]; + byte (*sbank)[8192]; + int loaded; +}; + + +extern struct mbc mbc; +extern struct rom rom; +extern struct ram ram; + + + + + +void mem_updatemap(void); //gp32 +void ioreg_write(byte r, byte b); +void mbc_write(int a, byte b); +void mem_write(int a, byte b); +byte mem_read(int a); + + +static byte readb(int a) +{ + return mem_read(a); +} + +static void writeb(int a, byte b) +{ + byte *p = mbc.wmap[a>>12]; + if (p) p[a] = b; + else mem_write(a, b); +} + +static int readw(int a) +{ + return mem_read(a) | (mem_read(a+1)<<8); +} + +static void writew(int a, int w) +{ + if ((a+1) & 0xfff) + { + byte *p = mbc.wmap[a>>12]; + if (p) + { +#ifdef IS_LITTLE_ENDIAN +#ifndef ALLOW_UNALIGNED_IO + if (a&1) + { + p[a] = w; + p[a+1] = w >> 8; + return; + } +#endif + *(uint16 *)(p+a) = w; + return; +#else + p[a] = w; + p[a+1] = w >> 8; + return; +#endif + } + } + mem_write(a, w); + mem_write(a+1, w>>8); +} + +static byte readhi(int a) +{ + return readb(a | 0xff00); +} + +static void writehi(int a, byte b) +{ + writeb(a | 0xff00, b); +} + + + +extern void mbc_reset(); + + +#endif + + + diff --git a/MCUME_teensy/teensygnuboy/memory.c b/MCUME_teensy/teensygnuboy/memory.c new file mode 100644 index 0000000..7eb2cc3 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/memory.c @@ -0,0 +1,39 @@ +#include "shared.h" + + +//static uint8 lvram[0x10000]; +//uint8 * vram=&lvram[0]; + +//byte ***mpatpix; +//byte lpatpix[4096][8][8]; + +void mem_init(void) { +/* + mpatpix = &lpatpix[0]; + int i; + for(i = 0; i < 4096; i++) { + mpatpix[i] = &lpatpix[i]; + int j; + for(j = 0; j < 8; j++) { + mpatpix[i][j] = &lpatpix[i][j]; + int k; + for(k = 0; k < 8; k++) { + mpatpix[i][j][k] = &lpatpix[i][j][k]; + mpatpix[i][j][k]=0; + } + } + } + */ +} + + +int mem_test(void) { + return 1; +} + +void memcpy_rom(int dst, int src, int size) { + while (size > 0) { + write_rom(dst++, read_rom(src++)); + size--; + } +} diff --git a/MCUME_teensy/teensygnuboy/memory.h b/MCUME_teensy/teensygnuboy/memory.h new file mode 100644 index 0000000..dd2b848 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/memory.h @@ -0,0 +1,16 @@ +#ifndef _MEMORY_H_ +#define _MEMORY_H_ + +#include "shared.h" + +//extern uint8 * vram; +//extern byte ***patpix; + + +extern void mem_init(void); +extern int mem_test(void); +extern uint8 read_rom(int address); +extern void write_rom(int address, uint8 val); +extern void memcpy_rom(int dst, int src, int size); + +#endif \ No newline at end of file diff --git a/MCUME_teensy/teensygnuboy/noise.h b/MCUME_teensy/teensygnuboy/noise.h new file mode 100644 index 0000000..aad3f53 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/noise.h @@ -0,0 +1,533 @@ + +#ifndef __NOISE_H__ +#define __NOISE_H__ + + +#include "defs.h" +#include "arduinoproto.h" + +PROGMEM const static byte noise7[] = +{ + 0xfd,0xf3,0xd7,0x0d,0xd3,0x15,0x82,0xf1, + 0xdb,0x25,0x21,0x39,0x68,0x8c,0xd5,0x00, +}; + +PROGMEM const static byte noise15[] = +{ + 0xff,0xfd,0xff,0xf3,0xff,0xd7,0xff,0x0f, + 0xfd,0xdf,0xf3,0x3f,0xd5,0x7f,0x00,0xfd, + 0xfd,0xf3,0xf3,0xd7,0xd7,0x0f,0x0d,0xdd, + 0xd3,0x33,0x15,0x55,0x80,0x02,0xff,0xf1, + 0xff,0xdb,0xff,0x27,0xfd,0x2f,0xf1,0x1f, + 0xd9,0xbf,0x2a,0x7d,0x02,0xf1,0xf1,0xdb, + 0xdb,0x27,0x25,0x2d,0x21,0x11,0x39,0x99, + 0x6a,0xa8,0x80,0x0c,0xff,0xd5,0xff,0x03, + 0xfd,0xf7,0xf3,0xcf,0xd7,0x5f,0x0c,0x3d, + 0xd7,0x73,0x0c,0xd5,0xd5,0x03,0x01,0xf5, + 0xfb,0xc3,0xe7,0x77,0xac,0xce,0x15,0x5b, + 0x80,0x26,0xff,0x29,0xfd,0x0b,0xf1,0xc7, + 0xdb,0x6f,0x24,0x9d,0x24,0xb1,0x24,0x59, + 0x26,0x29,0x2b,0x09,0x05,0xc9,0xe3,0x4b, + 0xb4,0x46,0x46,0x6a,0x6a,0x82,0x80,0xf0, + 0xfd,0xdd,0xf3,0x33,0xd5,0x57,0x00,0x0d, + 0xff,0xd3,0xff,0x17,0xfd,0x8f,0xf2,0xdf, + 0xd1,0x3f,0x19,0x7d,0xa8,0xf2,0x0d,0xd3, + 0xd3,0x17,0x15,0x8d,0x82,0xd2,0xf1,0x11, + 0xd9,0x9b,0x2a,0xa5,0x00,0x21,0xff,0x3b, + 0xfd,0x67,0xf0,0xaf,0xdc,0x1f,0x37,0xbd, + 0x4e,0x70,0x5a,0xde,0x21,0x3b,0x39,0x65, + 0x68,0xa0,0x8c,0x3c,0xd7,0x75,0x0c,0xc1, + 0xd5,0x7b,0x00,0xe5,0xfd,0xa3,0xf2,0x37, + 0xd3,0x4f,0x14,0x5d,0x86,0x32,0xeb,0x51, + 0x84,0x1a,0xe7,0xa1,0xae,0x3a,0x1b,0x63, + 0xa4,0xb6,0x24,0x4b,0x26,0x45,0x2a,0x61, + 0x02,0xb9,0xf0,0x6b,0xde,0x87,0x38,0xed, + 0x6d,0x90,0x92,0x9c,0x90,0xb4,0x9c,0x44, + 0xb6,0x64,0x4a,0xa6,0x40,0x2a,0x7f,0x02, + 0xfd,0xf1,0xf3,0xdb,0xd7,0x27,0x0d,0x2d, + 0xd1,0x13,0x19,0x95,0xaa,0x82,0x00,0xf3, + 0xfd,0xd7,0xf3,0x0f,0xd5,0xdf,0x03,0x3d, + 0xf5,0x73,0xc0,0xd7,0x7d,0x0c,0xf1,0xd5, + 0xdb,0x03,0x25,0xf5,0x23,0xc1,0x37,0x79, + 0x4c,0xe8,0x55,0x8e,0x02,0xdb,0xf1,0x27, + 0xd9,0x2f,0x29,0x1d,0x09,0xb1,0xca,0x5b, + 0x42,0x24,0x73,0x26,0xd5,0x29,0x01,0x09, + 0xf9,0xcb,0xeb,0x47,0x84,0x6e,0xe6,0x99, + 0xa8,0xaa,0x0c,0x03,0xd7,0xf7,0x0f,0xcd, + 0xdf,0x53,0x3c,0x15,0x77,0x80,0xce,0xfd, + 0x59,0xf0,0x2b,0xdf,0x07,0x3d,0xed,0x73, + 0x90,0xd6,0x9d,0x08,0xb1,0xcc,0x5b,0x56, + 0x24,0x0b,0x27,0xc5,0x2f,0x61,0x1c,0xb9, + 0xb4,0x6a,0x46,0x82,0x68,0xf2,0x8d,0xd0, + 0xd3,0x1d,0x15,0xb1,0x82,0x5a,0xf2,0x21, + 0xd3,0x3b,0x15,0x65,0x80,0xa2,0xfc,0x31, + 0xf7,0x5b,0xcc,0x27,0x57,0x2c,0x0d,0x17, + 0xd1,0x8f,0x1a,0xdd,0xa1,0x32,0x39,0x53, + 0x68,0x14,0x8f,0x84,0xde,0xe5,0x39,0xa1, + 0x6a,0x38,0x83,0x6c,0xf4,0x95,0xc4,0x83, + 0x64,0xf4,0xa5,0xc4,0x23,0x67,0x34,0xad, + 0x44,0x10,0x67,0x9e,0xae,0xb8,0x18,0x6f, + 0xae,0x9e,0x18,0xbb,0xac,0x66,0x16,0xab, + 0x88,0x06,0xcf,0xe9,0x5f,0x88,0x3e,0xcf, + 0x79,0x5c,0xe8,0x35,0x8f,0x42,0xdc,0x71, + 0x36,0xd9,0x49,0x28,0x49,0x0e,0x49,0xda, + 0x4b,0x22,0x45,0x32,0x61,0x52,0xb8,0x10, + 0x6f,0x9e,0x9e,0xb8,0xb8,0x6c,0x6e,0x96, + 0x98,0x88,0xac,0xcc,0x15,0x57,0x80,0x0e, + 0xff,0xd9,0xff,0x2b,0xfd,0x07,0xf1,0xef, + 0xdb,0x9f,0x26,0xbd,0x28,0x71,0x0e,0xd9, + 0xd9,0x2b,0x29,0x05,0x09,0xe1,0xcb,0xbb, + 0x46,0x64,0x6a,0xa6,0x80,0x28,0xff,0x0d, + 0xfd,0xd3,0xf3,0x17,0xd5,0x8f,0x02,0xdd, + 0xf1,0x33,0xd9,0x57,0x28,0x0d,0x0f,0xd1, + 0xdf,0x1b,0x3d,0xa5,0x72,0x20,0xd3,0x3d, + 0x15,0x71,0x80,0xda,0xfd,0x21,0xf1,0x3b, + 0xd9,0x67,0x28,0xad,0x0c,0x11,0xd7,0x9b, + 0x0e,0xa5,0xd8,0x23,0x2f,0x35,0x1d,0x41, + 0xb0,0x7a,0x5e,0xe2,0x39,0xb3,0x6a,0x54, + 0x82,0x04,0xf3,0xe5,0xd7,0xa3,0x0e,0x35, + 0xdb,0x43,0x24,0x75,0x26,0xc1,0x29,0x79, + 0x08,0xe9,0xcd,0x8b,0x52,0xc4,0x11,0x67, + 0x98,0xae,0xac,0x18,0x17,0xaf,0x8e,0x1e, + 0xdb,0xb9,0x26,0x69,0x2a,0x89,0x00,0xc9, + 0xfd,0x4b,0xf0,0x47,0xde,0x6f,0x3a,0x9d, + 0x60,0xb0,0xbc,0x5c,0x76,0x36,0xcb,0x49, + 0x44,0x48,0x66,0x4e,0xaa,0x58,0x02,0x2f, + 0xf3,0x1f,0xd5,0xbf,0x02,0x7d,0xf2,0xf3, + 0xd1,0xd7,0x1b,0x0d,0xa5,0xd2,0x23,0x13, + 0x35,0x95,0x42,0x80,0x70,0xfe,0xdd,0xf9, + 0x33,0xe9,0x57,0x88,0x0e,0xcf,0xd9,0x5f, + 0x28,0x3d,0x0f,0x71,0xdc,0xdb,0x35,0x25, + 0x41,0x20,0x79,0x3e,0xe9,0x79,0x88,0xea, + 0xcd,0x81,0x52,0xf8,0x11,0xef,0x9b,0x9e, + 0xa6,0xb8,0x28,0x6f,0x0e,0x9d,0xd8,0xb3, + 0x2c,0x55,0x16,0x01,0x8b,0xfa,0xc7,0xe1, + 0x6f,0xb8,0x9e,0x6c,0xba,0x94,0x60,0x86, + 0xbc,0xe8,0x75,0x8e,0xc2,0xd9,0x71,0x28, + 0xd9,0x0d,0x29,0xd1,0x0b,0x19,0xc5,0xab, + 0x62,0x04,0xb3,0xe4,0x57,0xa6,0x0e,0x2b, + 0xdb,0x07,0x25,0xed,0x23,0x91,0x36,0x99, + 0x48,0xa8,0x4c,0x0e,0x57,0xda,0x0f,0x23, + 0xdd,0x37,0x31,0x4d,0x58,0x50,0x2e,0x1f, + 0x1b,0xbd,0xa6,0x72,0x2a,0xd3,0x01,0x15, + 0xf9,0x83,0xea,0xf7,0x81,0xce,0xfb,0x59, + 0xe4,0x2b,0xa7,0x06,0x2d,0xeb,0x13,0x85, + 0x96,0xe2,0x89,0xb0,0xca,0x5d,0x42,0x30, + 0x73,0x5e,0xd4,0x39,0x07,0x69,0xec,0x8b, + 0x94,0xc6,0x85,0x68,0xe0,0x8d,0xbc,0xd2, + 0x75,0x12,0xc1,0x91,0x7a,0x98,0xe0,0xad, + 0xbc,0x12,0x77,0x92,0xce,0x91,0x58,0x98, + 0x2c,0xaf,0x14,0x1d,0x87,0xb2,0xee,0x51, + 0x9a,0x1a,0xa3,0xa0,0x36,0x3f,0x4b,0x7c, + 0x44,0xf6,0x65,0xca,0xa3,0x40,0x34,0x7f, + 0x46,0xfc,0x69,0xf6,0x8b,0xc8,0xc7,0x4d, + 0x6c,0x50,0x96,0x1c,0x8b,0xb4,0xc6,0x45, + 0x6a,0x60,0x82,0xbc,0xf0,0x75,0xde,0xc3, + 0x39,0x75,0x68,0xc0,0x8d,0x7c,0xd0,0xf5, + 0x1d,0xc1,0xb3,0x7a,0x54,0xe2,0x05,0xb3, + 0xe2,0x57,0xb2,0x0e,0x53,0xda,0x17,0x23, + 0x8d,0x36,0xd1,0x49,0x18,0x49,0xae,0x4a, + 0x1a,0x43,0xa2,0x76,0x32,0xcb,0x51,0x44, + 0x18,0x67,0xae,0xae,0x18,0x1b,0xaf,0xa6, + 0x1e,0x2b,0xbb,0x06,0x65,0xea,0xa3,0x80, + 0x36,0xff,0x49,0xfc,0x4b,0xf6,0x47,0xca, + 0x6f,0x42,0x9c,0x70,0xb6,0xdc,0x49,0x36, + 0x49,0x4a,0x48,0x42,0x4e,0x72,0x5a,0xd2, + 0x21,0x13,0x39,0x95,0x6a,0x80,0x80,0xfc, + 0xfd,0xf5,0xf3,0xc3,0xd7,0x77,0x0c,0xcd, + 0xd5,0x53,0x00,0x15,0xff,0x83,0xfe,0xf7, + 0xf9,0xcf,0xeb,0x5f,0x84,0x3e,0xe7,0x79, + 0xac,0xea,0x15,0x83,0x82,0xf6,0xf1,0xc9, + 0xdb,0x4b,0x24,0x45,0x26,0x61,0x2a,0xb9, + 0x00,0x69,0xfe,0x8b,0xf8,0xc7,0xed,0x6f, + 0x90,0x9e,0x9c,0xb8,0xb4,0x6c,0x46,0x96, + 0x68,0x8a,0x8c,0xc0,0xd5,0x7d,0x00,0xf1, + 0xfd,0xdb,0xf3,0x27,0xd5,0x2f,0x01,0x1d, + 0xf9,0xb3,0xea,0x57,0x82,0x0e,0xf3,0xd9, + 0xd7,0x2b,0x0d,0x05,0xd1,0xe3,0x1b,0xb5, + 0xa6,0x42,0x2a,0x73,0x02,0xd5,0xf1,0x03, + 0xd9,0xf7,0x2b,0xcd,0x07,0x51,0xec,0x1b, + 0x97,0xa6,0x8e,0x28,0xdb,0x0d,0x25,0xd1, + 0x23,0x19,0x35,0xa9,0x42,0x08,0x73,0xce, + 0xd7,0x59,0x0c,0x29,0xd7,0x0b,0x0d,0xc5, + 0xd3,0x63,0x14,0xb5,0x84,0x42,0xe6,0x71, + 0xaa,0xda,0x01,0x23,0xf9,0x37,0xe9,0x4f, + 0x88,0x5e,0xce,0x39,0x5b,0x68,0x24,0x8f, + 0x24,0xdd,0x25,0x31,0x21,0x59,0x38,0x29, + 0x6f,0x08,0x9d,0xcc,0xb3,0x54,0x54,0x06, + 0x07,0xeb,0xef,0x87,0x9e,0xee,0xb9,0x98, + 0x6a,0xae,0x80,0x18,0xff,0xad,0xfe,0x13, + 0xfb,0x97,0xe6,0x8f,0xa8,0xde,0x0d,0x3b, + 0xd1,0x67,0x18,0xad,0xac,0x12,0x17,0x93, + 0x8e,0x96,0xd8,0x89,0x2c,0xc9,0x15,0x49, + 0x80,0x4a,0xfe,0x41,0xfa,0x7b,0xe2,0xe7, + 0xb1,0xae,0x5a,0x1a,0x23,0xa3,0x36,0x35, + 0x4b,0x40,0x44,0x7e,0x66,0xfa,0xa9,0xe0, + 0x0b,0xbf,0xc6,0x7f,0x6a,0xfc,0x81,0xf4, + 0xfb,0xc5,0xe7,0x63,0xac,0xb6,0x14,0x4b, + 0x86,0x46,0xea,0x69,0x82,0x8a,0xf0,0xc1, + 0xdd,0x7b,0x30,0xe5,0x5d,0xa0,0x32,0x3f, + 0x53,0x7c,0x14,0xf7,0x85,0xce,0xe3,0x59, + 0xb4,0x2a,0x47,0x02,0x6d,0xf2,0x93,0xd0, + 0x97,0x1c,0x8d,0xb4,0xd2,0x45,0x12,0x61, + 0x92,0xba,0x90,0x60,0x9e,0xbc,0xb8,0x74, + 0x6e,0xc6,0x99,0x68,0xa8,0x8c,0x0c,0xd7, + 0xd5,0x0f,0x01,0xdd,0xfb,0x33,0xe5,0x57, + 0xa0,0x0e,0x3f,0xdb,0x7f,0x24,0xfd,0x25, + 0xf1,0x23,0xd9,0x37,0x29,0x4d,0x08,0x51, + 0xce,0x1b,0x5b,0xa4,0x26,0x27,0x2b,0x2d, + 0x05,0x11,0xe1,0x9b,0xba,0xa6,0x60,0x2a, + 0xbf,0x00,0x7d,0xfe,0xf3,0xf9,0xd7,0xeb, + 0x0f,0x85,0xde,0xe3,0x39,0xb5,0x6a,0x40, + 0x82,0x7c,0xf2,0xf5,0xd1,0xc3,0x1b,0x75, + 0xa4,0xc2,0x25,0x73,0x20,0xd5,0x3d,0x01, + 0x71,0xf8,0xdb,0xed,0x27,0x91,0x2e,0x99, + 0x18,0xa9,0xac,0x0a,0x17,0xc3,0x8f,0x76, + 0xdc,0xc9,0x35,0x49,0x40,0x48,0x7e,0x4e, + 0xfa,0x59,0xe2,0x2b,0xb3,0x06,0x55,0xe2, + 0x03,0x83,0xf6,0xf7,0xc9,0xcf,0x4b,0x5c, + 0x04,0x3e,0x67,0x4e,0xac,0x60,0x17,0x7f, + 0x80,0xfe,0xc1,0xf9,0x7b,0xe8,0xe7,0x87, + 0xae,0xc2,0x19,0x93,0xfc,0x96,0x08,0x8f, + 0xc0,0xe7,0xfc,0x2c,0xf0,0x1d,0xcc,0xc3, + 0x9e,0x70,0x00,0xc0,0x63,0x7f,0x54,0x78, + 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0x5a,0xcc,0x21,0x57,0x38,0x0d,0x6f,0xd0, + 0x9f,0x1c,0xbd,0xb4,0x72,0x46,0xd2,0x69, + 0x12,0x89,0x90,0xca,0x9d,0x40,0xb0,0x7c, + 0x5e,0xf6,0x39,0xcb,0x6b,0x44,0x84,0x64, + 0xe6,0xa5,0xa8,0x22,0x0f,0x33,0xdd,0x57, + 0x30,0x0d,0x5f,0xd0,0x3f,0x1f,0x7d,0xbc, + 0xf2,0x75,0xd2,0xc3,0x11,0x75,0x98,0xc2, + 0xad,0x70,0x10,0xdf,0x9d,0x3e,0xb1,0x78, + 0x58,0xee,0x2d,0x9b,0x12,0xa5,0x90,0x22, + 0x9f,0x30,0xbd,0x5c,0x70,0x36,0xdf,0x49, + 0x3c,0x49,0x76,0x48,0xca,0x4d,0x42,0x50, + 0x72,0x1e,0xd3,0xb9,0x16,0x69,0x8a,0x8a, + 0xc0,0xc1,0x7d,0x78,0xf0,0xed,0xdd,0x93, + 0x32,0x95,0x50,0x80,0x1c,0xff,0xb5,0xfe, + 0x43,0xfa,0x77,0xe2,0xcf,0xb1,0x5e,0x58, + 0x3a,0x2f,0x63,0x1c,0xb5,0xb4,0x42,0x46, + 0x72,0x6a,0xd2,0x81,0x10,0xf9,0x9d,0xea, + 0xb3,0x80,0x56,0xfe,0x09,0xfb,0xcb,0xe7, + 0x47,0xac,0x6e,0x16,0x9b,0x88,0xa6,0xcc, + 0x29,0x57,0x08,0x0d,0xcf,0xd3,0x5f,0x14, + 0x3d,0x87,0x72,0xec,0xd1,0x95,0x1a,0x81, + 0xa0,0xfa,0x3d,0xe3,0x73,0xb4,0xd6,0x45, + 0x0a,0x61,0xc2,0xbb,0x70,0x64,0xde,0xa5, + 0x38,0x21,0x6f,0x38,0x9d,0x6c,0xb0,0x94, + 0x5c,0x86,0x3e,0xeb,0x45,0x84,0x62,0xe6, + 0xb1,0xa8,0x5a,0x0e,0x23,0xfb,0x33,0x25, + 0x47,0x20,0x51,0x3e,0x19,0x7f,0xa8,0x66, + 0x0c,0xfb,0xd0,0x07,0x13,0xe5,0x9f,0x83, + 0xce,0x98,0x58,0xcd,0x2e,0x19,0x14,0x39, + 0x86,0x3f,0xff,0x01,0x85,0xff,0xe1,0xe1, + 0xb3,0xfc,0x46,0x63,0x0f,0xf8,0x00,0x53, + 0xbe,0x1f,0xfb,0xc0,0xe6,0x7e,0xbc,0xf0, + 0x01,0xe3,0xc3,0x9f,0xa6,0xcc,0x48,0x7e, + 0x40,0x82,0x9d,0xf2,0xff,0xd6,0x07,0x13, + 0xf5,0x87,0x80,0x0f,0x71,0x9c,0xfd,0x35, + 0x61,0x43,0xf8,0x78,0x7e,0xcf,0x19,0x99, + 0xa8,0x32,0x00,0x53,0xfc,0x17,0xfb,0x8f, + 0xc6,0xdf,0xa9,0x3e,0x09,0x7b,0xc8,0xe7, + 0x4d,0xac,0x52,0x16,0x13,0x8b,0x96,0xc6, + 0x89,0x68,0xc8,0x8d,0x4c,0xd0,0x55,0x1e, + 0x01,0xbb,0xfa,0x67,0xe2,0xaf,0xb0,0x1e, + 0x5f,0xba,0x3e,0x63,0x7a,0xb4,0xe0,0x45, + 0xbe,0x62,0x7a,0xb2,0xe0,0x51,0xbe,0x1a, + 0x7b,0xa2,0xe6,0x31,0xab,0x5a,0x04,0x23, + 0xe7,0x37,0xad,0x4e,0x10,0x5b,0x9e,0x26, + 0xbb,0x28,0x65,0x0e,0xa1,0xd8,0x3b,0x2f, + 0x65,0x1c,0xa1,0xb4,0x3a,0x47,0x62,0x6c, + 0xb2,0x94,0x50,0x86,0x1c,0xeb,0xb5,0x86, + 0x42,0xea,0x71,0x82,0xda,0xf1,0x21,0xd9, + 0x3b,0x29,0x65,0x08,0xa1,0xcc,0x3b,0x57, + 0x64,0x0c,0xa7,0xd4,0x2f,0x07,0x1d,0xed, + 0xb3,0x92,0x56,0x92,0x08,0x93,0xcc,0x97, + 0x54,0x8c,0x04,0xd7,0xe5,0x0f,0xa1,0xde, + 0x3b,0x3b,0x65,0x64,0xa0,0xa4,0x3c,0x27, + 0x77,0x2c,0xcd,0x15,0x51,0x80,0x1a,0xff, + 0xa1,0xfe,0x3b,0xfb,0x67,0xe4,0xaf,0xa4, + 0x1e,0x27,0xbb,0x2e,0x65,0x1a,0xa1,0xa0, + 0x3a,0x3f,0x63,0x7c,0xb4,0xf4,0x45,0xc6, + 0x63,0x6a,0xb4,0x80,0x44,0xfe,0x65,0xfa, + 0xa3,0xe0,0x37,0xbf,0x4e,0x7c,0x5a,0xf6, + 0x21,0xcb,0x3b,0x45,0x64,0x60,0xa6,0xbc, + 0x28,0x77,0x0e,0xcd,0xd9,0x53,0x28,0x15, + 0x0f,0x81,0xde,0xfb,0x39,0xe5,0x6b,0xa0, + 0x86,0x3c,0xeb,0x75,0x84,0xc2,0xe5,0x71, + 0xa0,0xda,0x3d,0x23,0x71,0x34,0xd9,0x45, + 0x28,0x61,0x0e,0xb9,0xd8,0x6b,0x2e,0x85, + 0x18,0xe1,0xad,0xba,0x12,0x63,0x92,0xb6, + 0x90,0x48,0x9e,0x4c,0xba,0x54,0x62,0x06, + 0xb3,0xe8,0x57,0x8e,0x0e,0xdb,0xd9,0x27, + 0x29,0x2d,0x09,0x11,0xc9,0x9b,0x4a,0xa4, + 0x40,0x26,0x7f,0x2a,0xfd,0x01,0xf1,0xfb, + 0xdb,0xe7,0x27,0xad,0x2e,0x11,0x1b,0x99, + 0xa6,0xaa,0x28,0x03,0x0f,0xf5,0xdf,0xc3, + 0x3f,0x75,0x7c,0xc0,0xf5,0x7d,0xc0,0xf3, + 0x7d,0xd4,0xf3,0x05,0xd5,0xe3,0x03,0xb5, + 0xf6,0x43,0xca,0x77,0x42,0xcc,0x71,0x56, + 0xd8,0x09,0x2f,0xc9,0x1f,0x49,0xbc,0x4a, + 0x76,0x42,0xca,0x71,0x42,0xd8,0x71,0x2e, + 0xd9,0x19,0x29,0xa9,0x0a,0x09,0xc3,0xcb, + 0x77,0x44,0xcc,0x65,0x56,0xa0,0x08,0x3f, + 0xcf,0x7f,0x5c,0xfc,0x35,0xf7,0x43,0xcc, + 0x77,0x56,0xcc,0x09,0x57,0xc8,0x0f,0x4f, + 0xdc,0x5f,0x36,0x3d,0x4b,0x70,0x44,0xde, + 0x65,0x3a,0xa1,0x60,0x38,0xbf,0x6c,0x7c, + 0x96,0xf4,0x89,0xc4,0xcb,0x65,0x44,0xa0, + 0x64,0x3e,0xa7,0x78,0x2c,0xef,0x15,0x9d, + 0x82,0xb2,0xf0,0x51,0xde,0x1b,0x3b,0xa5, + 0x66,0x20,0xab,0x3c,0x05,0x77,0xe0,0xcf, + 0xbd,0x5e,0x70,0x3a,0xdf,0x61,0x3c,0xb9, + 0x74,0x68,0xc6,0x8d,0x68,0xd0,0x8d,0x1c, + 0xd1,0xb5,0x1a,0x41,0xa2,0x7a,0x32,0xe3, + 0x51,0xb4,0x1a,0x47,0xa2,0x6e,0x32,0x9b, + 0x50,0xa4,0x1c,0x27,0xb7,0x2e,0x4d,0x1a, + 0x51,0xa2,0x1a,0x33,0xa3,0x56,0x34,0x0b, + 0x47,0xc4,0x6f,0x66,0x9c,0xa8,0xb4,0x0c, + 0x47,0xd6,0x6f,0x0a,0x9d,0xc0,0xb3,0x7c, + 0x54,0xf6,0x05,0xcb,0xe3,0x47,0xb4,0x6e, + 0x46,0x9a,0x68,0xa2,0x8c,0x30,0xd7,0x5d, + 0x0c,0x31,0xd7,0x5b,0x0c,0x25,0xd7,0x23, + 0x0d,0x35,0xd1,0x43,0x18,0x75,0xae,0xc2, + 0x19,0x73,0xa8,0xd6,0x0d,0x0b,0xd1,0xc7, + 0x1b,0x6d,0xa4,0x92,0x24,0x93,0x24,0x95, + 0x24,0x81,0x24,0xf9,0x25,0xe9,0x23,0x89, + 0x36,0xc9,0x49,0x48,0x48,0x4e,0x4e,0x5a, + 0x5a,0x22,0x23,0x33,0x35,0x55,0x40,0x00, +}; + + +#endif + diff --git a/MCUME_teensy/teensygnuboy/psram_t.cpp b/MCUME_teensy/teensygnuboy/psram_t.cpp new file mode 100644 index 0000000..3a47eb8 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/psram_t.cpp @@ -0,0 +1,356 @@ +/* + PSRAM driver for IPS6404 +*/ + +#include "psram_t.h" + +#include +#include + +#define SPI SPI2 + +//#define SPICLOCK 104000000 +#define SPICLOCK 70000000 +//#define SPICLOCK 144e6 //Just a number..max speed +#define SPI_MODE SPI_MODE0 + +#define RAM_READ 0xB +//#define RAM_READ 0x3 +#define RAM_WRITE 0x2 + + +uint8_t PSRAM_T::_cs, PSRAM_T::_miso, PSRAM_T::_mosi, PSRAM_T::_sclk; +Page PSRAM_T::pages[MAX_PAGES]; +uint8_t PSRAM_T::nbPages=0; +int8_t PSRAM_T::top=0; +int8_t PSRAM_T::last=0; + + +PSRAM_T::PSRAM_T(uint8_t cs, uint8_t mosi, uint8_t sclk, uint8_t miso) +{ + _cs = cs; + _mosi = mosi; + _sclk = sclk; + _miso = miso; + pinMode(_cs, OUTPUT); + digitalWrite(_cs, 1); +} + + +void PSRAM_T::begin(void) +{ + SPI.setMOSI(_mosi); + SPI.setMISO(_miso); + SPI.setSCK(_sclk); + SPI.begin(); + + delay(1); + + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(0x66); + digitalWrite(_cs, 1); + SPI.endTransaction(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + SPI.transfer(0x99); + SPI.endTransaction(); + digitalWrite(_cs, 1); + delayMicroseconds(20); +} + + + +uint8_t PSRAM_T::psram_read(uint32_t addr) +{ + uint8_t val=0; + + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_READ); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); +#if RAM_READ == 0xB + SPI.transfer(0xFF); +#endif + val = SPI.transfer(0xFF); + SPI.endTransaction(); + digitalWrite(_cs, 1); + return val; +} + + +void PSRAM_T::psram_read_n(uint32_t addr, uint8_t * val, int n) +{ + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_READ); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); +#if RAM_READ == 0xB + SPI.transfer(0xFF); +#endif + /* + while (n > 0) { + *val++ = SPI.transfer(0xFF); + n--; + } + */ + SPI.transfer(val,n); + SPI.endTransaction(); + digitalWrite(_cs, 1); +} + + +void PSRAM_T::psram_write(uint32_t addr, uint8_t val) +{ + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + SPI.transfer(val); + SPI.endTransaction(); + digitalWrite(_cs, 1); +} + +static uint8_t resp[PAGE_SIZE]; + + +void PSRAM_T::psram_write_n(uint32_t addr, uint8_t * val, int n) +{ + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + /* + while (n > 0) { + SPI.transfer(*val++); + n--; + } + */ + SPI.transfer(val,&resp[0],n); + SPI.endTransaction(); + digitalWrite(_cs, 1); +} + + +#ifdef DMATRY +#include + +DMAMEM static uint8_t src[PAGE_SIZE+4]; +DMAMEM static uint8_t dst[PAGE_SIZE+4]; +static DMASetting dmasettings[8]; +static DMAChannel dmatx; +static volatile uint8_t rstop = 0; + +#define DMASPI_PRINT(x) do {Serial.printf(x) ; Serial.flush();} while (0); + +static void dmaInterrupt() +{ + dmatx.clearInterrupt(); + rstop = 1; + //DMASPI_PRINT("irq"); +} + +void PSRAM_T::psram_write_n_dma(uint32_t addr, uint8_t * val, int n) { + uint8_t * dstPt = &dst[0]; + //*dstPt++ = RAM_WRITE; + //*dstPt++ = (addr>>16)&0xff; + //*dstPt++ = (addr>>8)&0xff; + //*dstPt++ = addr&0xff; + int cnt = n; + while (cnt > 0) { + *dstPt++ = *val++; + cnt--; + } + arm_dcache_flush(&dst[0], n); + rstop = 0; + dmatx.disable(); + dmatx.attachInterrupt(dmaInterrupt); + + dmasettings[0].sourceBuffer(&dst[0], n); + //dmasettings[0].destination((uint8_t &) LPSPI4_TDR); + dmasettings[0].destination((uint8_t &) IMXRT_LPSPI1_S.TDR); + dmasettings[0].TCD->ATTR_DST = 1; + dmasettings[0].interruptAtCompletion(); + +Serial.printf("A") ; Serial.flush(); + + digitalWrite(_cs, HIGH); + // SPI.begin(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + + digitalWrite(_cs, 0); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + //SPI.transfer(0); + //SPI.transfer(1); +Serial.printf("B") ; Serial.flush(); + +#ifdef XXX + LPSPI4_CR &= ~LPSPI_CR_MEN;//disable LPSPI: + LPSPI4_CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + //LPSPI4_TCR = 15; // Framesize 16 Bits + IMXRT_LPSPI4_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + LPSPI4_DER = LPSPI_DER_TDDE; //TX DMA Request Enable + // IMXRT_LPSPI4_S.DER = LPSPI_DER_TDDE; // | LPSPI_DER_RDDE; //enable DMA on both TX and RX + LPSPI4_CR |= LPSPI_CR_MEN; //enable LPSPI: + //IMXRT_LPSPI4_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + // IMXRT_LPSPI4_S.FCR = 0; + // Lets try to output the first byte to make sure that we are in 8 bit mode... + // IMXRT_LPSPI4_S.SR = 0x3f00; // clear out all of the other status... + + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI4_TX ); +#endif + IMXRT_LPSPI1_S.CR &= ~LPSPI_CR_MEN;//disable LPSPI: + IMXRT_LPSPI1_S.CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + IMXRT_LPSPI1_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + IMXRT_LPSPI1_S.DER = LPSPI_DER_TDDE; //TX DMA Request Enable + IMXRT_LPSPI1_S.CR |= LPSPI_CR_MEN; //enable LPSPI: + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI1_TX ); +Serial.printf("C") ; Serial.flush(); +// SPI.initDMAChannels(); + dmatx = dmasettings[0]; + + dmatx.enable(); +Serial.printf("D") ; Serial.flush(); + while (rstop == 0) {}; + + Serial.printf("E") ; Serial.flush(); + digitalWrite(_cs, 1); +} +#endif + + + + +void PSRAM_T::pswrite(uint32_t addr, uint8_t val) +{ + psram_write(addr, val); + //return; + uint32_t curPage=addr&(~(PAGE_SIZE-1)); + for (int i=0; i + +#define PAGE_SIZE 16 //16 //32 //2048 //1024 +#define MAX_PAGES 8 + +struct Page { + uint8_t page[PAGE_SIZE]; + uint32_t pageid; + int8_t next; + int8_t prev; +}; + +class PSRAM_T +{ + public: + PSRAM_T(uint8_t _CS, uint8_t _MOSI=11, uint8_t _SCLK=13, uint8_t _MISO=12); + void begin(void); + void pswrite(uint32_t addr, uint8_t val); + uint8_t psread(uint32_t addr); + uint16_t psread_w(uint32_t addr); + + private: + static uint8_t psram_read(uint32_t addr); + static void psram_read_n(uint32_t addr, uint8_t * val, int n); + static void psram_write(uint32_t addr, uint8_t val); + static void psram_write_n(uint32_t addr, uint8_t * val, int n); + + protected: + static uint8_t _cs, _miso, _mosi, _sclk; + static Page pages[MAX_PAGES]; + static uint8_t nbPages; + static int8_t top; + static int8_t last; +}; +#endif + +#endif + diff --git a/MCUME_teensy/teensygnuboy/rc.h b/MCUME_teensy/teensygnuboy/rc.h new file mode 100644 index 0000000..7c2be30 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/rc.h @@ -0,0 +1,63 @@ + + + +#ifndef __RC_H__ +#define __RC_H__ + + + +typedef enum rctype +{ + rcv_end, + rcv_int, + rcv_string, + rcv_vector, + rcv_bool +} rcvtype_t; + + +typedef struct rcvar_s +{ + char *name; + int type; + int len; + void *mem; +} rcvar_t; + +#define RCV_END { 0, rcv_end, 0, 0 } +#define RCV_INT(n,v) { (n), rcv_int, 1, (v) } +#define RCV_STRING(n,v) { (n), rcv_string, 0, (v) } +#define RCV_VECTOR(n,v,l) { (n), rcv_vector, (l), (v) } +#define RCV_BOOL(n,v) { (n), rcv_bool, 1, (v) } + +typedef struct rccmd_s +{ + char *name; + int (*func)(int, char **); +} rccmd_t; + +#define RCC(n,f) { (n), (f) } +#define RCC_END { 0, 0 } + +void rc_export(rcvar_t *v); +void rc_exportvars(rcvar_t *vars); + +int rc_findvar(char *name); + +int rc_setvar_n(int i, int c, char **v); +int rc_setvar(char *name, int c, char **v); + +int rc_getint_n(int i); +int *rc_getvec_n(int i); +char *rc_getstr_n(int i); + +int rc_getint(char *name); +int *rc_getvec(char *name); +char *rc_getstr(char *name); + + +#endif + + + + diff --git a/MCUME_teensy/teensygnuboy/regs.h b/MCUME_teensy/teensygnuboy/regs.h new file mode 100644 index 0000000..4457fd9 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/regs.h @@ -0,0 +1,181 @@ + +#ifndef __REGS_H__ +#define __REGS_H__ + + +#include "mem.h" + +/* General internal/io stuff */ + +#define RI_P1 0x00 +#define RI_SB 0x01 +#define RI_SC 0x02 +#define RI_DIV 0x04 +#define RI_TIMA 0x05 +#define RI_TMA 0x06 +#define RI_TAC 0x07 + +#define RI_KEY1 0x4D + +#define RI_RP 0x56 + +#define RI_SVBK 0x70 + + + +/* Interrupts flags */ + +#define RI_IF 0x0F +#define RI_IE 0xFF + + + + +/* LCDC */ + +#define RI_LCDC 0x40 +#define RI_STAT 0x41 +#define RI_SCY 0x42 +#define RI_SCX 0x43 +#define RI_LY 0x44 +#define RI_LYC 0x45 +#define RI_DMA 0x46 +#define RI_BGP 0x47 +#define RI_OBP0 0x48 +#define RI_OBP1 0x49 +#define RI_WY 0x4A +#define RI_WX 0x4B + +#define RI_VBK 0x4F + +#define RI_HDMA1 0x51 +#define RI_HDMA2 0x52 +#define RI_HDMA3 0x53 +#define RI_HDMA4 0x54 +#define RI_HDMA5 0x55 + +#define RI_BCPS 0x68 +#define RI_BCPD 0x69 +#define RI_OCPS 0x6A +#define RI_OCPD 0x6B + + + +/* Sound */ + +#define RI_NR10 0x10 +#define RI_NR11 0x11 +#define RI_NR12 0x12 +#define RI_NR13 0x13 +#define RI_NR14 0x14 +#define RI_NR21 0x16 +#define RI_NR22 0x17 +#define RI_NR23 0x18 +#define RI_NR24 0x19 +#define RI_NR30 0x1A +#define RI_NR31 0x1B +#define RI_NR32 0x1C +#define RI_NR33 0x1D +#define RI_NR34 0x1E +#define RI_NR41 0x20 +#define RI_NR42 0x21 +#define RI_NR43 0x22 +#define RI_NR44 0x23 +#define RI_NR50 0x24 +#define RI_NR51 0x25 +#define RI_NR52 0x26 + + + +#define REG(n) ram.hi[(n)] + + + +/* General internal/io stuff */ + +#define R_P1 REG(RI_P1) +#define R_SB REG(RI_SB) +#define R_SC REG(RI_SC) +#define R_DIV REG(RI_DIV) +#define R_TIMA REG(RI_TIMA) +#define R_TMA REG(RI_TMA) +#define R_TAC REG(RI_TAC) + +#define R_KEY1 REG(RI_KEY1) + +#define R_RP REG(RI_RP) + +#define R_SVBK REG(RI_SVBK) + + + +/* Interrupts flags */ + +#define R_IF REG(RI_IF) +#define R_IE REG(RI_IE) + + + + +/* LCDC */ + +#define R_LCDC REG(RI_LCDC) +#define R_STAT REG(RI_STAT) +#define R_SCY REG(RI_SCY) +#define R_SCX REG(RI_SCX) +#define R_LY REG(RI_LY) +#define R_LYC REG(RI_LYC) +#define R_DMA REG(RI_DMA) +#define R_BGP REG(RI_BGP) +#define R_OBP0 REG(RI_OBP0) +#define R_OBP1 REG(RI_OBP1) +#define R_WY REG(RI_WY) +#define R_WX REG(RI_WX) + +#define R_VBK REG(RI_VBK) + +#define R_HDMA1 REG(RI_HDMA1) +#define R_HDMA2 REG(RI_HDMA2) +#define R_HDMA3 REG(RI_HDMA3) +#define R_HDMA4 REG(RI_HDMA4) +#define R_HDMA5 REG(RI_HDMA5) + +#define R_BCPS REG(RI_BCPS) +#define R_BCPD REG(RI_BCPD) +#define R_OCPS REG(RI_OCPS) +#define R_OCPD REG(RI_OCPD) + + + +/* Sound */ + +#define R_NR10 REG(RI_NR10) +#define R_NR11 REG(RI_NR11) +#define R_NR12 REG(RI_NR12) +#define R_NR13 REG(RI_NR13) +#define R_NR14 REG(RI_NR14) +#define R_NR21 REG(RI_NR21) +#define R_NR22 REG(RI_NR22) +#define R_NR23 REG(RI_NR23) +#define R_NR24 REG(RI_NR24) +#define R_NR30 REG(RI_NR30) +#define R_NR31 REG(RI_NR31) +#define R_NR32 REG(RI_NR32) +#define R_NR33 REG(RI_NR33) +#define R_NR34 REG(RI_NR34) +#define R_NR41 REG(RI_NR41) +#define R_NR42 REG(RI_NR42) +#define R_NR43 REG(RI_NR43) +#define R_NR44 REG(RI_NR44) +#define R_NR50 REG(RI_NR50) +#define R_NR51 REG(RI_NR51) +#define R_NR52 REG(RI_NR52) + + + +#endif + + + + + diff --git a/MCUME_teensy/teensygnuboy/rtc.c b/MCUME_teensy/teensygnuboy/rtc.c new file mode 100644 index 0000000..62b2709 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/rtc.c @@ -0,0 +1,101 @@ +#include + +#include "defs.h" +#include "mem.h" +#include "rtc.h" +#include "rc.h" + +struct rtc rtc; + +static int syncrtc = 1; + +rcvar_t rtc_exports[] = +{ + RCV_BOOL("syncrtc", &syncrtc), + RCV_END +}; + + +void rtc_latch(byte b) +{ + if ((rtc.latch ^ b) & b & 1) + { + rtc.regs[0] = rtc.s; + rtc.regs[1] = rtc.m; + rtc.regs[2] = rtc.h; + rtc.regs[3] = rtc.d; + rtc.regs[4] = (rtc.d>>9) | (rtc.stop<<6) | (rtc.carry<<7); + rtc.regs[5] = 0xff; + rtc.regs[6] = 0xff; + rtc.regs[7] = 0xff; + } + rtc.latch = b; +} + +void rtc_write(byte b) +{ + /* printf("write %02X: %02X (%d)\n", rtc.sel, b, b); */ + if (!(rtc.sel & 8)) return; + switch (rtc.sel & 7) + { + case 0: + rtc.s = rtc.regs[0] = b; + while (rtc.s >= 60) rtc.s -= 60; + break; + case 1: + rtc.m = rtc.regs[1] = b; + while (rtc.m >= 60) rtc.m -= 60; + break; + case 2: + rtc.h = rtc.regs[2] = b; + while (rtc.h >= 24) rtc.h -= 24; + break; + case 3: + rtc.regs[3] = b; + rtc.d = (rtc.d & 0x100) | b; + break; + case 4: + rtc.regs[4] = b; + rtc.d = (rtc.d & 0xff) | ((b&1)<<9); + rtc.stop = (b>>6)&1; + rtc.carry = (b>>7)&1; + break; + } +} + +void rtc_tick() +{ + if (rtc.stop) return; + if (++rtc.t == 60) + { + if (++rtc.s == 60) + { + if (++rtc.m == 60) + { + if (++rtc.h == 24) + { + if (++rtc.d == 365) + { + rtc.d = 0; + rtc.carry = 1; + } + rtc.h = 0; + } + rtc.m = 0; + } + rtc.s = 0; + } + rtc.t = 0; + } +} + + + + + + + + + + + diff --git a/MCUME_teensy/teensygnuboy/rtc.h b/MCUME_teensy/teensygnuboy/rtc.h new file mode 100644 index 0000000..e1e251f --- /dev/null +++ b/MCUME_teensy/teensygnuboy/rtc.h @@ -0,0 +1,26 @@ + + +#ifndef __RTC_H__ +#define __RTC_H__ + + +struct rtc +{ + int batt; + int sel; + int latch; + int d, h, m, s, t; + int stop, carry; + byte regs[8]; +}; + +extern struct rtc rtc; + +extern void rtc_tick(); + + + +#endif + + + diff --git a/MCUME_teensy/teensygnuboy/shared.h b/MCUME_teensy/teensygnuboy/shared.h new file mode 100644 index 0000000..70f389e --- /dev/null +++ b/MCUME_teensy/teensygnuboy/shared.h @@ -0,0 +1,9 @@ + +#ifndef _SHARED_H_ +#define _SHARED_H_ + + +#include "defs.h" +#include "memory.h" + +#endif /* _SHARED_H_ */ diff --git a/MCUME_teensy/teensygnuboy/sound.c b/MCUME_teensy/teensygnuboy/sound.c new file mode 100644 index 0000000..6d7e09f --- /dev/null +++ b/MCUME_teensy/teensygnuboy/sound.c @@ -0,0 +1,582 @@ + + + +#include "defs.h" +#include "sound.h" +#include "cpu.h" +#include "hw.h" +#include "regs.h" +#include "rc.h" +#include "noise.h" + +#include "arduinoproto.h" + +PROGMEM const static byte dmgwave[16] = +{ + 0xac, 0xdd, 0xda, 0x48, + 0x36, 0x02, 0xcf, 0x16, + 0x2c, 0x04, 0xe5, 0x2c, + 0xac, 0xdd, 0xda, 0x48 +}; + +PROGMEM const static byte cgbwave[16] = +{ + 0x00, 0xff, 0x00, 0xff, + 0x00, 0xff, 0x00, 0xff, + 0x00, 0xff, 0x00, 0xff, + 0x00, 0xff, 0x00, 0xff, +}; + +PROGMEM const static byte sqwave[4][8] = +{ + { 0, 0,-1, 0, 0, 0, 0, 0 }, + { 0,-1,-1, 0, 0, 0, 0, 0 }, + { -1,-1,-1,-1, 0, 0, 0, 0 }, + { -1, 0, 0,-1,-1,-1,-1,-1 } +}; + +PROGMEM const static int freqtab[8] = +{ + (1<<14)*2, + (1<<14), + (1<<14)/2, + (1<<14)/3, + (1<<14)/4, + (1<<14)/5, + (1<<14)/6, + (1<<14)/7 +}; + +struct snd snd; + +#define RATE (snd.rate) +#define WAVE (snd.wave) /* ram.hi+0x30 */ +#define S1 (snd.ch[0]) +#define S2 (snd.ch[1]) +#define S3 (snd.ch[2]) +#define S4 (snd.ch[3]) + +rcvar_t sound_exports[] = +{ + RCV_END +}; + + +static void s1_freq_d(int d) +{ + if (RATE > (d<<4)) S1.freq = 0; + else S1.freq = (RATE << 17)/d; +} + +static void s1_freq() +{ + s1_freq_d(2048 - (((R_NR14&7)<<8) + R_NR13)); +} + +static void s2_freq() +{ + int d = 2048 - (((R_NR24&7)<<8) + R_NR23); + if (RATE > (d<<4)) S2.freq = 0; + else S2.freq = (RATE << 17)/d; +} + +static void s3_freq() +{ + int d = 2048 - (((R_NR34&7)<<8) + R_NR33); + if (RATE > (d<<3)) S3.freq = 0; + else S3.freq = (RATE << 21)/d; +} + +static void s4_freq() +{ + S4.freq = (freqtab[R_NR43&7] >> (R_NR43 >> 4)) * RATE; + if (S4.freq >> 18) S4.freq = 1<<18; +} + +void sound_dirty() +{ + S1.swlen = ((R_NR10>>4) & 7) << 14; + S1.len = (64-(R_NR11&63)) << 13; + S1.envol = R_NR12 >> 4; + S1.endir = (R_NR12>>3) & 1; + S1.endir |= S1.endir - 1; + S1.enlen = (R_NR12 & 7) << 15; + s1_freq(); + S2.len = (64-(R_NR21&63)) << 13; + S2.envol = R_NR22 >> 4; + S2.endir = (R_NR22>>3) & 1; + S2.endir |= S2.endir - 1; + S2.enlen = (R_NR22 & 7) << 15; + s2_freq(); + S3.len = (256-R_NR31) << 20; + s3_freq(); + S4.len = (64-(R_NR41&63)) << 13; + S4.envol = R_NR42 >> 4; + S4.endir = (R_NR42>>3) & 1; + S4.endir |= S4.endir - 1; + S4.enlen = (R_NR42 & 7) << 15; + s4_freq(); +} + +void sound_off() +{ + memset(&S1, 0, sizeof S1); + memset(&S2, 0, sizeof S2); + memset(&S3, 0, sizeof S3); + memset(&S4, 0, sizeof S4); + R_NR10 = 0x80; + R_NR11 = 0xBF; + R_NR12 = 0xF3; + R_NR14 = 0xBF; + R_NR21 = 0x3F; + R_NR22 = 0x00; + R_NR24 = 0xBF; + R_NR30 = 0x7F; + R_NR31 = 0xFF; + R_NR32 = 0x9F; + R_NR33 = 0xBF; + R_NR41 = 0xFF; + R_NR42 = 0x00; + R_NR43 = 0x00; + R_NR44 = 0xBF; + R_NR50 = 0x77; + R_NR51 = 0xF3; + R_NR52 = 0xF1; + sound_dirty(); +} + +void sound_reset(int rate) +{ + memset(&snd, 0, sizeof snd); + if (rate) + snd.rate = (1<<21) / rate; + else + snd.rate = 0; + memcpy(WAVE, hw.cgb ? cgbwave : dmgwave, 16); + memcpy(ram.hi+0x30, WAVE, 16); + sound_off(); +} + +void audio_play_sample(int16 *bufl, int16 *bufr, int length) { + int s, l, r, f, n; + int i; + + length=length/2; + + for(i=0;i>6][(S1.pos>>18)&7] & S1.envol; + S1.pos += S1.freq; + if ((R_NR14 & 64) && ((S1.cnt += RATE) >= S1.len)) + S1.on = 0; + if (S1.enlen && (S1.encnt += RATE) >= S1.enlen) + { + S1.encnt -= S1.enlen; + S1.envol += S1.endir; + if (S1.envol < 0) S1.envol = 0; + if (S1.envol > 15) S1.envol = 15; + } + if (S1.swlen && (S1.swcnt += RATE) >= S1.swlen) + { + S1.swcnt -= S1.swlen; + f = S1.swfreq; + n = (R_NR10 & 7); + if (R_NR10 & 8) f -= (f >> n); + else f += (f >> n); + if (f > 2047) + S1.on = 0; + else + { + S1.swfreq = f; + R_NR13 = f; + R_NR14 = (R_NR14 & 0xF8) | (f>>8); + s1_freq_d(2048 - f); + } + } + s <<= 2; + if (R_NR51 & 1) r += s; + if (R_NR51 & 16) l += s; + } + + if (S2.on) + { + s = sqwave[R_NR21>>6][(S2.pos>>18)&7] & S2.envol; + S2.pos += S2.freq; + if ((R_NR24 & 64) && ((S2.cnt += RATE) >= S2.len)) + S2.on = 0; + if (S2.enlen && (S2.encnt += RATE) >= S2.enlen) + { + S2.encnt -= S2.enlen; + S2.envol += S2.endir; + if (S2.envol < 0) S2.envol = 0; + if (S2.envol > 15) S2.envol = 15; + } + s <<= 2; + if (R_NR51 & 2) r += s; + if (R_NR51 & 32) l += s; + } + + if (S3.on) + { + s = WAVE[(S3.pos>>22) & 15]; + if (S3.pos & (1<<21)) s &= 15; + else s >>= 4; + s -= 8; + S3.pos += S3.freq; + if ((R_NR34 & 64) && ((S3.cnt += RATE) >= S3.len)) + S3.on = 0; + if (R_NR32 & 96) s <<= (3 - ((R_NR32>>5)&3)); + else s = 0; + if (R_NR51 & 4) r += s; + if (R_NR51 & 64) l += s; + } + + if (S4.on) + { + if (R_NR43 & 8) s = 1 & (noise7[ + (S4.pos>>20)&15] >> (7-((S4.pos>>17)&7))); + else s = 1 & (noise15[ + (S4.pos>>20)&4095] >> (7-((S4.pos>>17)&7))); + s = (-s) & S4.envol; + S4.pos += S4.freq; + if ((R_NR44 & 64) && ((S4.cnt += RATE) >= S4.len)) + S4.on = 0; + if (S4.enlen && (S4.encnt += RATE) >= S4.enlen) + { + S4.encnt -= S4.enlen; + S4.envol += S4.endir; + if (S4.envol < 0) S4.envol = 0; + if (S4.envol > 15) S4.envol = 15; + } + s += s << 1; + if (R_NR51 & 8) r += s; + if (R_NR51 & 128) l += s; + } + + l *= (R_NR50 & 0x07); + r *= ((R_NR50 & 0x70)>>4); + l >>= 4; + r >>= 4; + + if (l > 127) l = 127; + else if (l < -128) l = -128; + if (r > 127) r = 127; + else if (r < -128) r = -128; + + *bufl++ = l*256; + *bufl++ = r*256; + } + R_NR52 = (R_NR52&0xf0) | S1.on | (S2.on<<1) | (S3.on<<2) | (S4.on<<3); + +} + +/* +void sound_mix() +{ + int s, l, r, f, n; + int i; + + pcm.pos =0; + for(i=0;i>6][(S1.pos>>18)&7] & S1.envol; + S1.pos += S1.freq; + if ((R_NR14 & 64) && ((S1.cnt += RATE) >= S1.len)) + S1.on = 0; + if (S1.enlen && (S1.encnt += RATE) >= S1.enlen) + { + S1.encnt -= S1.enlen; + S1.envol += S1.endir; + if (S1.envol < 0) S1.envol = 0; + if (S1.envol > 15) S1.envol = 15; + } + if (S1.swlen && (S1.swcnt += RATE) >= S1.swlen) + { + S1.swcnt -= S1.swlen; + f = S1.swfreq; + n = (R_NR10 & 7); + if (R_NR10 & 8) f -= (f >> n); + else f += (f >> n); + if (f > 2047) + S1.on = 0; + else + { + S1.swfreq = f; + R_NR13 = f; + R_NR14 = (R_NR14 & 0xF8) | (f>>8); + s1_freq_d(2048 - f); + } + } + s <<= 2; + if (R_NR51 & 1) r += s; + if (R_NR51 & 16) l += s; + } + + if (S2.on) + { + s = sqwave[R_NR21>>6][(S2.pos>>18)&7] & S2.envol; + S2.pos += S2.freq; + if ((R_NR24 & 64) && ((S2.cnt += RATE) >= S2.len)) + S2.on = 0; + if (S2.enlen && (S2.encnt += RATE) >= S2.enlen) + { + S2.encnt -= S2.enlen; + S2.envol += S2.endir; + if (S2.envol < 0) S2.envol = 0; + if (S2.envol > 15) S2.envol = 15; + } + s <<= 2; + if (R_NR51 & 2) r += s; + if (R_NR51 & 32) l += s; + } + + if (S3.on) + { + s = WAVE[(S3.pos>>22) & 15]; + if (S3.pos & (1<<21)) s &= 15; + else s >>= 4; + s -= 8; + S3.pos += S3.freq; + if ((R_NR34 & 64) && ((S3.cnt += RATE) >= S3.len)) + S3.on = 0; + if (R_NR32 & 96) s <<= (3 - ((R_NR32>>5)&3)); + else s = 0; + if (R_NR51 & 4) r += s; + if (R_NR51 & 64) l += s; + } + + if (S4.on) + { + if (R_NR43 & 8) s = 1 & (noise7[ + (S4.pos>>20)&15] >> (7-((S4.pos>>17)&7))); + else s = 1 & (noise15[ + (S4.pos>>20)&4095] >> (7-((S4.pos>>17)&7))); + s = (-s) & S4.envol; + S4.pos += S4.freq; + if ((R_NR44 & 64) && ((S4.cnt += RATE) >= S4.len)) + S4.on = 0; + if (S4.enlen && (S4.encnt += RATE) >= S4.enlen) + { + S4.encnt -= S4.enlen; + S4.envol += S4.endir; + if (S4.envol < 0) S4.envol = 0; + if (S4.envol > 15) S4.envol = 15; + } + s += s << 1; + if (R_NR51 & 8) r += s; + if (R_NR51 & 128) l += s; + } + + l *= (R_NR50 & 0x07); + r *= ((R_NR50 & 0x70)>>4); + l >>= 4; + r >>= 4; + + if (l > 127) l = 127; + else if (l < -128) l = -128; + if (r > 127) r = 127; + else if (r < -128) r = -128; + + + if (pcm.buf) + { + if (pcm.stereo) + { + pcm.buf[pcm.pos++] = l*256; + pcm.buf[pcm.pos++] = r*256; + } + else + pcm.buf[pcm.pos++] = ((l+r)>>1)*256; + } + } + R_NR52 = (R_NR52&0xf0) | S1.on | (S2.on<<1) | (S3.on<<2) | (S4.on<<3); +} +*/ + + +byte sound_read(byte r) +{ +// sound_mix(); //gp32 + /* printf("read %02X: %02X\n", r, REG(r)); */ + return REG(r); +} + +void s1_init() +{ + S1.swcnt = 0; + S1.swfreq = ((R_NR14&7)<<8) + R_NR13; + S1.envol = R_NR12 >> 4; + S1.endir = (R_NR12>>3) & 1; + S1.endir |= S1.endir - 1; + S1.enlen = (R_NR12 & 7) << 15; + if (!S1.on) S1.pos = 0; + S1.on = 1; + S1.cnt = 0; + S1.encnt = 0; +} + +void s2_init() +{ + S2.envol = R_NR22 >> 4; + S2.endir = (R_NR22>>3) & 1; + S2.endir |= S2.endir - 1; + S2.enlen = (R_NR22 & 7) << 15; + if (!S2.on) S2.pos = 0; + S2.on = 1; + S2.cnt = 0; + S2.encnt = 0; +} + +void s3_init() +{ + int i; + if (!S3.on) S3.pos = 0; + S3.cnt = 0; + S3.on = R_NR30 >> 7; + if (S3.on) for (i = 0; i < 16; i++) + ram.hi[i+0x30] = 0x13 ^ ram.hi[i+0x31]; +} + +void s4_init() +{ + S4.envol = R_NR42 >> 4; + S4.endir = (R_NR42>>3) & 1; + S4.endir |= S4.endir - 1; + S4.enlen = (R_NR42 & 7) << 15; + S4.on = 1; + S4.pos = 0; + S4.cnt = 0; + S4.encnt = 0; +} + + +void sound_write(byte r, byte b) +{ +#if 0 + static void *timer; + if (!timer) timer = sys_timer(); + printf("write %02X: %02X @ %d\n", r, b, sys_elapsed(timer)); +#endif + + if (!(R_NR52 & 128) && r != RI_NR52) return; + if ((r & 0xF0) == 0x30) + { + if (S3.on) ;//sound_mix(); //gp32 + if (!S3.on) + WAVE[r-0x30] = ram.hi[r] = b; + return; + } + //sound_mix(); //gp32 + switch (r) + { + case RI_NR10: + R_NR10 = b; + S1.swlen = ((R_NR10>>4) & 7) << 14; + S1.swfreq = ((R_NR14&7)<<8) + R_NR13; + break; + case RI_NR11: + R_NR11 = b; + S1.len = (64-(R_NR11&63)) << 13; + break; + case RI_NR12: + R_NR12 = b; + S1.envol = R_NR12 >> 4; + S1.endir = (R_NR12>>3) & 1; + S1.endir |= S1.endir - 1; + S1.enlen = (R_NR12 & 7) << 15; + break; + case RI_NR13: + R_NR13 = b; + s1_freq(); + break; + case RI_NR14: + R_NR14 = b; + s1_freq(); + if (b & 128) s1_init(); + break; + case RI_NR21: + R_NR21 = b; + S2.len = (64-(R_NR21&63)) << 13; + break; + case RI_NR22: + R_NR22 = b; + S2.envol = R_NR22 >> 4; + S2.endir = (R_NR22>>3) & 1; + S2.endir |= S2.endir - 1; + S2.enlen = (R_NR22 & 7) << 15; + break; + case RI_NR23: + R_NR23 = b; + s2_freq(); + break; + case RI_NR24: + R_NR24 = b; + s2_freq(); + if (b & 128) s2_init(); + break; + case RI_NR30: + R_NR30 = b; + if (!(b & 128)) S3.on = 0; + break; + case RI_NR31: + R_NR31 = b; + S3.len = (256-R_NR31) << 13; + break; + case RI_NR32: + R_NR32 = b; + break; + case RI_NR33: + R_NR33 = b; + s3_freq(); + break; + case RI_NR34: + R_NR34 = b; + s3_freq(); + if (b & 128) s3_init(); + break; + case RI_NR41: + R_NR41 = b; + S4.len = (64-(R_NR41&63)) << 13; + break; + case RI_NR42: + R_NR42 = b; + S4.envol = R_NR42 >> 4; + S4.endir = (R_NR42>>3) & 1; + S4.endir |= S4.endir - 1; + S4.enlen = (R_NR42 & 7) << 15; + break; + case RI_NR43: + R_NR43 = b; + s4_freq(); + break; + case RI_NR44: + R_NR44 = b; + if (b & 128) s4_init(); + break; + case RI_NR50: + R_NR50 = b; + break; + case RI_NR51: + R_NR51 = b; + break; + case RI_NR52: + R_NR52 = b; + if (!(R_NR52 & 128)) + sound_off(); + break; + default: + return; + } +} + + + + diff --git a/MCUME_teensy/teensygnuboy/sound.h b/MCUME_teensy/teensygnuboy/sound.h new file mode 100644 index 0000000..87a5e16 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/sound.h @@ -0,0 +1,38 @@ + + +#ifndef __SOUND_H__ +#define __SOUND_H__ + + +struct sndchan +{ + int on; + unsigned pos; + int cnt, encnt, swcnt; + int len, enlen, swlen; + int swfreq; + int freq; + int envol, endir; +}; + + +struct snd +{ + int rate; + struct sndchan ch[4]; + byte wave[16]; +}; + + +extern struct snd snd; + + +extern void sound_reset(int rate); +extern void audio_play_sample(int16 *bufl, int16 *bufr, int length); + + + + +#endif + + diff --git a/MCUME_teensy/teensygnuboy/teensygnuboy.ino b/MCUME_teensy/teensygnuboy/teensygnuboy.ino new file mode 100644 index 0000000..fad38d6 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/teensygnuboy.ino @@ -0,0 +1,279 @@ +#include "iopins.h" +#include "emuapi.h" + +#include "keyboard_osd.h" +#include "tft_t_dma.h" + +#include "emu.h" + +#ifdef HAS_VGA +#include +uVGA uvga; +#if F_CPU == 144000000 +#define UVGA_144M_326X240 +#define UVGA_XRES 326 +#define UVGA_YRES 240 +#define UVGA_XRES_EXTRA 10 +#elif F_CPU == 180000000 +#define UVGA_180M_360X300 +#define UVGA_XRES 360 +#define UVGA_YRES 300 +#define UVGA_XRES_EXTRA 8 +#elif F_CPU == 240000000 +#define UVGA_240M_452X240 +#define UVGA_XRES 452 +#define UVGA_YRES 240 +#define UVGA_XRES_EXTRA 12 +#else +#error Please select F_CPU=240MHz or F_CPU=180MHz or F_CPU=144MHz +#endif + +#include + +uint8_t * VGA_frame_buffer; +#endif + +TFT_T_DMA tft = TFT_T_DMA(TFT_CS, TFT_DC, TFT_RST, TFT_MOSI, TFT_SCLK, TFT_MISO, TFT_TOUCH_CS, TFT_TOUCH_INT); + +bool vgaMode = false; + +static unsigned char palette8[PALETTE_SIZE]; +static unsigned short palette16[PALETTE_SIZE]; +static IntervalTimer myTimer; +volatile boolean vbl=true; +static int skip=0; +static elapsedMicros tius; + +static void vblCount() { + if (vbl) { + vbl = false; + } else { + vbl = true; + } +} + +void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index) +{ + if (index +#include "AudioPlaySystem.h" + +AudioPlaySystem mymixer; +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) +AudioOutputMQS mqs; +AudioConnection patchCord9(mymixer, 0, mqs, 1); +#else +AudioOutputAnalog dac1; +AudioConnection patchCord1(mymixer, dac1); +#endif + +void emu_sndInit() { + Serial.println("sound init"); + AudioMemory(16); + mymixer.start(); +} + +void emu_sndPlaySound(int chan, int volume, int freq) +{ + if (chan < 6) { + mymixer.sound(chan, freq, volume); + } + /* + Serial.print(chan); + Serial.print(":" ); + Serial.print(volume); + Serial.print(":" ); + Serial.println(freq); + */ +} + +void emu_sndPlayBuzz(int size, int val) { + mymixer.buzz(size,val); + //Serial.print((val==1)?1:0); + //Serial.print(":"); + //Serial.println(size); +} +#endif diff --git a/MCUME_teensy/teensygnuboy/tft_t_dma.cpp b/MCUME_teensy/teensygnuboy/tft_t_dma.cpp new file mode 100644 index 0000000..33c4d32 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/tft_t_dma.cpp @@ -0,0 +1,1182 @@ +/* + Based on C64 ILI9341 dma driver from Frank Bösing, 2017 +*/ + +#include "TFT_T_DMA.h" +#include "font8x8.h" + +//#define SPICLOCK 144e6 //Just a number..max speed +#define SPICLOCK 60000000 +#ifdef ILI9341 +#define SPI_MODE SPI_MODE0 +#endif +#ifdef ST7789 +#define SPI_MODE SPI_MODE2 +#endif + +// touch +#define SPI_SETTING SPISettings(2500000, MSBFIRST, SPI_MODE) +#define XPT2046_CFG_START _BV(7) +#define XPT2046_CFG_MUX(v) ((v&0b111) << (4)) +#define XPT2046_CFG_8BIT _BV(3) +#define XPT2046_CFG_12BIT (0) +#define XPT2046_CFG_SER _BV(2) +#define XPT2046_CFG_DFR (0) +#define XPT2046_CFG_PWR(v) ((v&0b11)) +#define XPT2046_MUX_Y 0b101 +#define XPT2046_MUX_X 0b001 +#define XPT2046_MUX_Z1 0b011 +#define XPT2046_MUX_Z2 0b100 + + +#ifdef TFT_STATICFB +static uint16_t fb0[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t fb1[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t fb2[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t fb3[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t * blocks[NR_OF_BLOCK]={fb0,fb1,fb2,fb3}; +#else +static uint16_t * blocks[NR_OF_BLOCK]; +#endif + + +static DMASetting dmasettings[SCREEN_DMA_NUM_SETTINGS]; +static DMAChannel dmatx;//(false); +static volatile uint8_t rstop = 0; +static volatile bool cancelled = false; +static volatile uint8_t curTransfer = 0; +static uint8_t nbTransfer = 0; + + +PROGMEM static const uint8_t init_commands[] = { +#ifdef ILI9341 + 4, 0xEF, 0x03, 0x80, 0x02, + 4, 0xCF, 0x00, 0XC1, 0X30, + 5, 0xED, 0x64, 0x03, 0X12, 0X81, + 4, 0xE8, 0x85, 0x00, 0x78, + 6, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02, + 2, 0xF7, 0x20, + 3, 0xEA, 0x00, 0x00, + 2, ILI9341_PWCTR1, 0x23, // Power control + 2, ILI9341_PWCTR2, 0x10, // Power control + 3, ILI9341_VMCTR1, 0x3e, 0x28, // VCM control + 2, ILI9341_VMCTR2, 0x86, // VCM control2 + 2, ILI9341_MADCTL, 0x48, // Memory Access Control + 2, ILI9341_PIXFMT, 0x55, + 3, ILI9341_FRMCTR1, 0x00, 0x18, + 4, ILI9341_DFUNCTR, 0x08, 0x82, 0x27, // Display Function Control + 2, 0xF2, 0x00, // Gamma Function Disable + 2, ILI9341_GAMMASET, 0x01, // Gamma curve selected + 16, ILI9341_GMCTRP1, 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, + 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00, // Set Gamma + 16, ILI9341_GMCTRN1, 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, + 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F, // Set Gamma +// 3, 0xb1, 0x00, 0x1f, // FrameRate Control 61Hz + 3, 0xb1, 0x00, 0x10, // FrameRate Control 119Hz + 2, ILI9341_MADCTL, ILI9341_MADCTL_MX | ILI9341_MADCTL_MY | ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR, + 0 +#endif +#ifdef ST7789 +#define DELAY 0x80 + 9, // 9 commands in list: + ST7735_SWRESET, DELAY, // 1: Software reset, no args, w/delay + 150, // 150 ms delay + ST7735_SLPOUT , DELAY, // 2: Out of sleep mode, no args, w/delay + 255, // 255 = 500 ms delay + ST7735_COLMOD , 1+DELAY, // 3: Set color mode, 1 arg + delay: + 0x55, // 16-bit color + 10, // 10 ms delay + ST7735_MADCTL , 1 , // 4: Memory access ctrl (directions), 1 arg: + 0x08, // Row addr/col addr, bottom to top refresh + ST7735_CASET , 4 , // 5: Column addr set, 4 args, no delay: + 0x00, + 0x00, // XSTART = 0 + 0x00, + 240, // XEND = 240 + ST7735_RASET , 4 , // 6: Row addr set, 4 args, no delay: + 0x00, + 0x00, // YSTART = 0 + 320>>8, + 320 & 0xFF, // YEND = 320 + ST7735_INVON , DELAY, // 7: hack + 10, + ST7735_NORON , DELAY, // 8: Normal display on, no args, w/delay + 10, // 10 ms delay + ST7735_DISPON , DELAY, // 9: Main screen turn on, no args, w/delay + 255 +#endif +}; + + +static void dmaInterrupt() { + dmatx.clearInterrupt(); + curTransfer++; + if (curTransfer >= nbTransfer) { + curTransfer = 0; + if (cancelled) { + dmatx.disable(); + rstop = 1; + } + } +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) + arm_dcache_flush(blocks[curTransfer], LINES_PER_BLOCK*TFT_WIDTH*2); +#endif +} + +static void setDmaStruct() { + uint32_t remaining = TFT_HEIGHT*TFT_WIDTH*2; + int i=0; + uint16_t col=RGBVAL16(0x00,0x00,0x00);; + while (remaining > 0) { + uint16_t * fb = blocks[i]; + int32_t len = (remaining >= (LINES_PER_BLOCK*TFT_WIDTH*2)?LINES_PER_BLOCK*TFT_WIDTH*2:remaining); +#ifdef TFT_DEBUG + Serial.println((unsigned long)blocks[i]); + Serial.println(remaining); +#endif + switch (i) { + case 0: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb0[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0x00,0xff,0x00); +#endif + break; + case 1: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb1[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0x00,0xff,0xff); +#endif + break; + case 2: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb2[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0x00,0x00,0xff); +#endif + break; + case 3: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb3[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0xff,0x00,0xff); +#endif + break; + } + blocks[i] = fb; + if (blocks[i] == 0) { + Serial.print("ILI9341 allocaltion failed for block "); + Serial.println(i); + delay(10000); + } + + for (int j=0;jATTR_DST = 1; +#else + dmasettings[i].sourceBuffer(fb, len); + dmasettings[i].destination((uint8_t &) SPI0_PUSHR); + dmasettings[i].TCD->ATTR_DST = 1; +#endif + dmasettings[i].replaceSettingsOnCompletion(dmasettings[i+1]); + dmasettings[i].interruptAtCompletion(); + remaining -= len; + i++; + } + dmasettings[i-1].replaceSettingsOnCompletion(dmasettings[0]); + nbTransfer = i; +#ifdef TFT_DEBUG + Serial.println(nbTransfer); +#endif +} + + +TFT_T_DMA::TFT_T_DMA(uint8_t cs, uint8_t dc, uint8_t rst, uint8_t mosi, uint8_t sclk, uint8_t miso, uint8_t touch_cs, uint8_t touch_irq) +{ + _cs = cs; + _dc = dc; + _rst = rst; + _mosi = mosi; + _sclk = sclk; + _miso = miso; + pinMode(_dc, OUTPUT); + pinMode(_cs, OUTPUT); + digitalWrite(_cs, 1); + digitalWrite(_dc, 1); + if ( (touch_cs != 255) && (touch_irq != 255) ) { + _touch_irq = touch_irq; + _touch_cs = touch_cs; + pinMode(_touch_cs, OUTPUT); + pinMode(touch_irq, INPUT_PULLUP); + digitalWrite(_touch_cs, 1); + } +} + + +void TFT_T_DMA::setArea(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2) { + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + + digitalWrite(_dc, 0); + SPI.transfer(TFT_CASET); + digitalWrite(_dc, 1); + SPI.transfer16(x1); + SPI.transfer16(x2); + + digitalWrite(_dc, 0); + SPI.transfer(TFT_PASET); + digitalWrite(_dc, 1); + SPI.transfer16(y1); + SPI.transfer16(y2); + + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + digitalWrite(_dc, 1); + + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + + +void TFT_T_DMA::begin(void) { + SPI.setMOSI(_mosi); + SPI.setMISO(_miso); + SPI.setSCK(_sclk); + SPI.begin(); + + // Initialize display + if (_rst < 255) { // toggle RST low to reset + pinMode(_rst, OUTPUT); + digitalWrite(_rst, HIGH); + delay(5); + digitalWrite(_rst, LOW); + delay(20); + digitalWrite(_rst, HIGH); + delay(120); + } + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + const uint8_t *addr = init_commands; + digitalWrite(_cs, 0); +#ifdef ILI9341 + while (1) { + uint8_t count = *addr++; + if (count-- == 0) break; + + digitalWrite(_dc, 0); + SPI.transfer(*addr++); + + while (count-- > 0) { + digitalWrite(_dc, 1); + SPI.transfer(*addr++); + } + } + + digitalWrite(_dc, 0); + SPI.transfer(ILI9341_SLPOUT); + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + SPI.endTransaction(); + + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + SPI.endTransaction(); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_dc, 0); + digitalWrite(_cs, 0); + SPI.transfer(ILI9341_DISPON); + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + SPI.endTransaction(); +#endif +#ifdef ST7789 + uint8_t numCommands, numArgs; + uint16_t ms; + numCommands = *addr++; // Number of commands to follow + while(numCommands--) { // For each command... + digitalWrite(_dc, 0); + SPI.transfer(*addr++); + numArgs = *addr++; // Number of args to follow + ms = numArgs & DELAY; // If hibit set, delay follows args + numArgs &= ~DELAY; // Mask out delay bit + while(numArgs > 1) { // For each argument... + digitalWrite(_dc, 1); + SPI.transfer(*addr++); + numArgs--; + } + + if (numArgs) { + digitalWrite(_dc, 1); + SPI.transfer(*addr++); + } + if(ms) { + ms = *addr++; // Read post-command delay time (ms) + if(ms == 255) ms = 500; // If 255, delay for 500 ms + SPI.endTransaction(); + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + delay(ms); + //beginSPITransaction(); + } + } +#endif + + setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1); + + cancelled = false; +#ifdef FLIP_SCREEN + flipscreen(true); +#else + flipscreen(false); +#endif +}; + + + +void TFT_T_DMA::flipscreen(bool flip) +{ + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_dc, 0); + digitalWrite(_cs, 0); + SPI.transfer(TFT_MADCTL); + digitalWrite(_dc, 1); + if (flip) { + flipped=true; +#ifdef ILI9341 + SPI.transfer(ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR); +#endif +#ifdef ST7789 + //SPI.transfer(ST77XX_MADCTL_RGB); + SPI.transfer(ST77XX_MADCTL_MV | ST77XX_MADCTL_RGB); +#endif + } + else { + flipped=false; +#ifdef ILI9341 + SPI.transfer(ILI9341_MADCTL_MX | ILI9341_MADCTL_MY | ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR); +#endif +#ifdef ST7789 + SPI.transfer(ST77XX_MADCTL_MX | ST77XX_MADCTL_MV | ST77XX_MADCTL_RGB); +#endif + } + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + +boolean TFT_T_DMA::isflipped(void) +{ + return(flipped); +} + + +#define PRREG(x) Serial.print(#x" 0x"); Serial.println(x,HEX) + + +void TFT_T_DMA::startDMA(void) { + curTransfer = 0; + rstop = 0; + //dmatx.begin(true); + dmatx.attachInterrupt(dmaInterrupt); + setDmaStruct(); + setArea((TFT_REALWIDTH-TFT_WIDTH)/2, (TFT_REALHEIGHT-TFT_HEIGHT)/2, (TFT_REALWIDTH-TFT_WIDTH)/2 + TFT_WIDTH-1, (TFT_REALHEIGHT-TFT_HEIGHT)/2+TFT_HEIGHT-1); + fillScreen(RGBVAL16(0x00,0x00,0x00)); + + digitalWrite(_cs, HIGH); + SPI.begin(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE0)); +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) + +#ifdef TFT_DEBUG + PRREG(LPSPI4_CCR); + PRREG(LPSPI4_TCR); + PRREG(LPSPI4_FCR); + Serial.printf("SPI CLOCK %d CCR freq %.1f MHz\n", SPICLOCK, 528. / 7 / ((0xff & LPSPI4_CCR) + 2)); +#endif + LPSPI4_CR &= ~LPSPI_CR_MEN;//disable LPSPI: + LPSPI4_CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + LPSPI4_TCR = 15; // Framesize 16 Bits + //LPSPI4_FCR = 0; // Fifo Watermark + LPSPI4_DER = LPSPI_DER_TDDE; //TX DMA Request Enable + LPSPI4_CR |= LPSPI_CR_MEN; //enable LPSPI: + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI4_TX ); +#else + SPI0_RSER |= SPI_RSER_TFFF_DIRS | SPI_RSER_TFFF_RE; // Set ILI_DMA Interrupt Request Select and Enable register + SPI0_MCR &= ~SPI_MCR_HALT; //Start transfers. + SPI0_CTAR0 = SPI0_CTAR1; + (*(volatile uint16_t *)((int)&SPI0_PUSHR + 2)) = (SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT) >> 16; //Enable 16 Bit Transfers + Continue-Bit + dmatx.triggerAtHardwareEvent(DMAMUX_SOURCE_SPI0_TX ); +#endif + dmatx = dmasettings[0]; + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + digitalWrite(_dc, 1); + dmatx.enable(); +} + + +void TFT_T_DMA::stopDMA(void) { + rstop = 0; + wait(); + delay(50); + cancelled = false; + dmatx.detachInterrupt(); + fillScreen(RGBVAL16(0x00,0x00,0x00)); + SPI.end(); +#ifdef ST7789 + begin(); +#endif +#ifdef ILI9341 + SPI.begin(); + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.endTransaction(); + digitalWrite(_cs, 1); + digitalWrite(_dc, 1); +#endif + setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1); +} + +void TFT_T_DMA::wait(void) { + rstop = 1; + unsigned long m = millis(); + cancelled = true; + while (!rstop) { + if ((millis() - m) > 100) break; + delay(10); + asm volatile("wfi"); + }; + rstop = 0; +} + + +/*********************************************************************************************** + Touch functions + ***********************************************************************************************/ +/* Code based on ... + * + * @file XPT2046.cpp + * @date 19.02.2016 + * @author Markus Sattler + * + * Copyright (c) 2015 Markus Sattler. All rights reserved. + * This file is part of the XPT2046 driver for Arduino. + */ + +#define ADC_MAX 0x0fff + +void TFT_T_DMA::enableTouchIrq() +{ + SPI.beginTransaction(SPI_SETTING); + digitalWrite(_touch_cs, LOW); + const uint8_t buf[4] = { (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y)), 0x00, 0x00, 0x00 }; + SPI.transfer((void*)&buf[0],3); + digitalWrite(_touch_cs, HIGH); + SPI.endTransaction(); +} + +//Default callibration for non flipped +#define TX_MIN 30 +#define TY_MIN 20 +#define TX_MAX 300 +#define TY_MAX 220 + +//Default callibration for flipped +#define TFX_MIN 20 +#define TFY_MIN 25 +#define TFX_MAX 288 +#define TFY_MAX 221 + +static uint16_t txMin; +static uint16_t tyMin; +static uint16_t txMax; +static uint16_t tyMax; + + +void TFT_T_DMA::callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax) { + if ( (xMin >= 0) && (yMin >= 0) && (xMax < 320) && (yMax < 200) ) { + txMin = xMin; + tyMin = yMin; + txMax = xMax; + tyMax = yMax; + } + else { + if (flipped) { + txMin = TFX_MIN; + tyMin = TFY_MIN; + txMax = TFX_MAX; + tyMax = TFY_MAX; + } + else { + txMin = TX_MIN; + tyMin = TY_MIN; + txMax = TX_MAX; + tyMax = TY_MAX; + } + } +} + + +void TFT_T_DMA::readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + if ( TOUCH_ENABLED() ) { + uint16_t x = 0; + uint16_t y = 0; + uint16_t z1 = 0; + uint16_t z2 = 0; + uint8_t i = 0; + int16_t xraw=0, yraw=0; + + SPI.beginTransaction(SPI_SETTING); + digitalWrite(_touch_cs, LOW); + + for(; i < 15; i++) { + // SPI requirer 32bit aliment + uint8_t buf[12] = { + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3)), 0x00, 0x00 + }; + SPI.transfer(&buf[0], &buf[0], 12); + y += (buf[1] << 8 | buf[2])>>3; + x += (buf[4] << 8 | buf[5])>>3; + z1 += (buf[7] << 8 | buf[8])>>3; + z2 += (buf[10] << 8 | buf[11])>>3; + } + enableTouchIrq(); + + if(i == 0) { + *oX = 0; + *oY = 0; + *oZ = 0; + } + else { + x /= i; + y /= i; + z1 /= i; + z2 /= i; + } + + digitalWrite(_touch_cs, HIGH); + SPI.endTransaction(); + int z = z1 + ADC_MAX - z2; + if (flipped) { + xraw = x; + yraw = y; + } else { + xraw = ADC_MAX - x; + yraw = ADC_MAX - y; + } + xraw=(xraw*TFT_REALWIDTH)/(ADC_MAX+1); + yraw=(yraw*TFT_REALHEIGHT)/(ADC_MAX+1); + + *oX = xraw; + *oY = yraw; + *oZ = z; + } + else + { + *oX = 0; + *oY = 0; + *oZ = 0; + } +} + +void TFT_T_DMA::readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + readRaw(oX,oY,oZ); + // callibrate ... + if(*oX >= txMin) *oX = ((*oX - txMin)*TFT_REALWIDTH)/(txMax-txMin); + if(*oY >= tyMin) *oY = ((*oY - tyMin)*TFT_REALHEIGHT)/(tyMax-tyMin); + //Serial.print(*oX); + //Serial.print(" "); + //Serial.println(*oY); +} + + +/*********************************************************************************************** + No DMA functions + ***********************************************************************************************/ +void TFT_T_DMA::fillScreenNoDma(uint16_t color) { + setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + int i,j; + for (j=0; j(arx+arw)) || ((x+w)(ary+arh)) || ((y+h) arx) && (x<(arx+arw)) ) { + arw = arw - (x-arx); + arx = arx + (x-arx); + } else { + bmp_offx = arx; + } + if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) { + arw -= (arx+arw-x-w); + } + if ( (y > ary) && (y<(ary+arh)) ) { + arh = arh - (y-ary); + ary = ary + (y-ary); + } else { + bmp_offy = ary; + } + if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) { + arh -= (ary+arh-y-h); + } + } + + setArea(arx, ary, arx+arw-1, ary+arh-1); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + + bitmap = bitmap + bmp_offy*w + bmp_offx; + for (int row=0;row> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + } + bits = *charpt++; + digitalWrite(_dc, 1); + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + } + x +=8; +#ifdef ILI9341 + digitalWrite(_dc, 0); + SPI.transfer(ILI9341_SLPOUT); + digitalWrite(_dc, 1); +#endif + digitalWrite(_cs, 1); + SPI.endTransaction(); + } + + setArea(0, 0, (TFT_REALWIDTH-1), (TFT_REALHEIGHT-1)); +} + + +void TFT_T_DMA::drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color) { + setArea(x,y,x+w-1,y+h-1); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + int i; + for (i=0; i<(w*h); i++) + { + digitalWrite(_dc, 1); + SPI.transfer16(color); + } +#ifdef ILI9341 + digitalWrite(_dc, 0); + SPI.transfer(ILI9341_SLPOUT); + digitalWrite(_dc, 1); +#endif + digitalWrite(_cs, 1); + SPI.endTransaction(); + + setArea(0, 0, (TFT_REALWIDTH-1), (TFT_REALHEIGHT-1)); +} + + + +/*********************************************************************************************** + DMA functions + ***********************************************************************************************/ +uint16_t * TFT_T_DMA::getLineBuffer(int j) +{ + uint16_t * block=blocks[j>>6]; + return(&block[(j&0x3F)*TFT_REALWIDTH]); +} + +void TFT_T_DMA::writeScreen(int width, int height, int stride, uint8_t *buf, uint16_t *palette16) { + uint8_t *buffer=buf; + uint8_t *src; + + int i,j,y=0; + if (width*2 <= TFT_REALWIDTH) { + for (j=0; j>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*TFT_WIDTH]; + src=buffer; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH+(TFT_WIDTH-width)/2]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*TFT_WIDTH+(TFT_WIDTH-width)/2]; + src=buffer; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH]; + if (width > TFT_WIDTH) { +#ifdef TFT_LINEARINT + int delta = (width/(width-TFT_WIDTH))-1; + int pos = delta; + for (int i=0; i> 8]&PAL_COLOR_MASK]; + pos +=step; + } +#endif + } + else if ((width*2) == TFT_WIDTH) { + for (int i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH]; + if (width > TFT_WIDTH) { +#ifdef TFT_LINEARINT + int delta = (width/(width-TFT_WIDTH))-1; + int pos = delta; + for (int i=0; i> 8]; + pos +=step; + } +#endif + } + else if ((width*2) == TFT_WIDTH) { + for (int i=0; i>6]; + uint16_t * dst=&block[(j&0x3F)*TFT_WIDTH]; + for (i=0; i>6]; + uint16_t * dst=&block[(l&0x3F)*TFT_WIDTH+x]; + for (i=0; i>6]; + dst=&block[(l&0x3F)*TFT_WIDTH+x]; + bits = *charpt; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + block=blocks[l>>6]; + dst=&block[(l&0x3F)*TFT_WIDTH+x]; + bits = *charpt++; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + x +=8; + } +} + +void TFT_T_DMA::drawSprite(int16_t x, int16_t y, const uint16_t *bitmap) { + drawSprite(x,y,bitmap, 0,0,0,0); +} + +void TFT_T_DMA::drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t arx, uint16_t ary, uint16_t arw, uint16_t arh) +{ + int bmp_offx = 0; + int bmp_offy = 0; + uint16_t *bmp_ptr; + + int w =*bitmap++; + int h = *bitmap++; + + + if ( (arw == 0) || (arh == 0) ) { + // no crop window + arx = x; + ary = y; + arw = w; + arh = h; + } + else { + if ( (x>(arx+arw)) || ((x+w)(ary+arh)) || ((y+h) arx) && (x<(arx+arw)) ) { + arw = arw - (x-arx); + arx = arx + (x-arx); + } else { + bmp_offx = arx; + } + if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) { + arw -= (arx+arw-x-w); + } + if ( (y > ary) && (y<(ary+arh)) ) { + arh = arh - (y-ary); + ary = ary + (y-ary); + } else { + bmp_offy = ary; + } + if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) { + arh -= (ary+arh-y-h); + } + } + + + int l=ary; + bitmap = bitmap + bmp_offy*w + bmp_offx; + for (int row=0;row>6]; + uint16_t * dst=&block[(l&0x3F)*TFT_WIDTH+arx]; + bmp_ptr = (uint16_t*)bitmap; + for (int col=0;col +#include +#include +#endif + +#include "tft_t_dma_config.h" + +#define RGBVAL32(r,g,b) ( (r<<16) | (g<<8) | b ) +#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) ) +#define RGBVAL8(r,g,b) ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) ) +#define R16(rgb) ((rgb>>8)&0xf8) +#define G16(rgb) ((rgb>>3)&0xfc) +#define B16(rgb) ((rgb<<3)&0xf8) + +#define PAL_COLOR_MASK 0xff + +#define TFT_HEIGHT 144 + +#ifdef ILI9341 +#define TFT_WIDTH 320 +#define TFT_REALWIDTH 320 +#define TFT_REALHEIGHT 240 +#endif +#ifdef ST7789 +#define TFT_WIDTH 240 +#define TFT_REALWIDTH 240 +#define TFT_REALHEIGHT 240 +#endif + +#define LINES_PER_BLOCK 64 +#define NR_OF_BLOCK 4 +#define SCREEN_DMA_NUM_SETTINGS NR_OF_BLOCK + + +#ifdef ILI9341 + +#define ILI9341_NOP 0x00 +#define ILI9341_SWRESET 0x01 +#define ILI9341_RDDID 0x04 +#define ILI9341_RDDST 0x09 + +#define ILI9341_SLPIN 0x10 +#define ILI9341_SLPOUT 0x11 +#define ILI9341_PTLON 0x12 +#define ILI9341_NORON 0x13 + +#define ILI9341_RDMODE 0x0A +#define ILI9341_RDMADCTL 0x0B +#define ILI9341_RDPIXFMT 0x0C +#define ILI9341_RDIMGFMT 0x0D +#define ILI9341_RDSELFDIAG 0x0F + +#define ILI9341_INVOFF 0x20 +#define ILI9341_INVON 0x21 +#define ILI9341_GAMMASET 0x26 +#define ILI9341_DISPOFF 0x28 +#define ILI9341_DISPON 0x29 + +#define ILI9341_CASET 0x2A +#define ILI9341_PASET 0x2B +#define ILI9341_RAMWR 0x2C +#define ILI9341_RAMRD 0x2E + +#define ILI9341_PTLAR 0x30 +#define ILI9341_MADCTL 0x36 +#define ILI9341_VSCRSADD 0x37 +#define ILI9341_PIXFMT 0x3A + +#define ILI9341_FRMCTR1 0xB1 +#define ILI9341_FRMCTR2 0xB2 +#define ILI9341_FRMCTR3 0xB3 +#define ILI9341_INVCTR 0xB4 +#define ILI9341_DFUNCTR 0xB6 + +#define ILI9341_PWCTR1 0xC0 +#define ILI9341_PWCTR2 0xC1 +#define ILI9341_PWCTR3 0xC2 +#define ILI9341_PWCTR4 0xC3 +#define ILI9341_PWCTR5 0xC4 +#define ILI9341_VMCTR1 0xC5 +#define ILI9341_VMCTR2 0xC7 + +#define ILI9341_RDID1 0xDA +#define ILI9341_RDID2 0xDB +#define ILI9341_RDID3 0xDC +#define ILI9341_RDID4 0xDD + +#define ILI9341_GMCTRP1 0xE0 +#define ILI9341_GMCTRN1 0xE1 + +#define ILI9341_MADCTL_MY 0x80 +#define ILI9341_MADCTL_MX 0x40 +#define ILI9341_MADCTL_MV 0x20 +#define ILI9341_MADCTL_ML 0x10 +#define ILI9341_MADCTL_RGB 0x00 +#define ILI9341_MADCTL_BGR 0x08 +#define ILI9341_MADCTL_MH 0x04 + +#define TFT_CASET ILI9341_CASET +#define TFT_PASET ILI9341_PASET +#define TFT_RAMWR ILI9341_RAMWR +#define TFT_MADCTL ILI9341_MADCTL + +#endif + + +#ifdef ST7789 + +#define ST7735_NOP 0x00 +#define ST7735_SWRESET 0x01 +#define ST7735_RDDID 0x04 +#define ST7735_RDDST 0x09 + +#define ST7735_SLPIN 0x10 +#define ST7735_SLPOUT 0x11 +#define ST7735_PTLON 0x12 +#define ST7735_NORON 0x13 + +#define ST7735_INVOFF 0x20 +#define ST7735_INVON 0x21 +#define ST7735_DISPOFF 0x28 +#define ST7735_DISPON 0x29 +#define ST7735_CASET 0x2A +#define ST7735_RASET 0x2B +#define ST7735_RAMWR 0x2C +#define ST7735_RAMRD 0x2E + +#define ST7735_PTLAR 0x30 +#define ST7735_COLMOD 0x3A +#define ST7735_MADCTL 0x36 + +#define ST7735_FRMCTR1 0xB1 +#define ST7735_FRMCTR2 0xB2 +#define ST7735_FRMCTR3 0xB3 +#define ST7735_INVCTR 0xB4 +#define ST7735_DISSET5 0xB6 + +#define ST7735_PWCTR1 0xC0 +#define ST7735_PWCTR2 0xC1 +#define ST7735_PWCTR3 0xC2 +#define ST7735_PWCTR4 0xC3 +#define ST7735_PWCTR5 0xC4 +#define ST7735_VMCTR1 0xC5 + +#define ST7735_RDID1 0xDA +#define ST7735_RDID2 0xDB +#define ST7735_RDID3 0xDC +#define ST7735_RDID4 0xDD + +#define ST7735_PWCTR6 0xFC + +#define ST7735_GMCTRP1 0xE0 +#define ST7735_GMCTRN1 0xE1 + +#define ST77XX_MADCTL_MY 0x80 +#define ST77XX_MADCTL_MX 0x40 +#define ST77XX_MADCTL_MV 0x20 +#define ST77XX_MADCTL_ML 0x10 +#define ST77XX_MADCTL_RGB 0x00 +#define ST77XX_MADCTL_BGR 0x08 +#define ST77XX_MADCTL_MH 0x04 + +#define TFT_CASET ST7735_CASET +#define TFT_PASET ST7735_RASET +#define TFT_RAMWR ST7735_RAMWR +#define TFT_MADCTL ST7735_MADCTL + +#endif + + + +#ifdef __cplusplus + +class TFT_T_DMA +{ + public: + TFT_T_DMA(uint8_t _CS, uint8_t _DC, uint8_t _RST = 255, uint8_t _MOSI=11, uint8_t _SCLK=13, uint8_t _MISO=12, uint8_t touch_cs=38, uint8_t touch_irq=37); + + void setArea(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2); + void begin(void); + void flipscreen(bool flip); + boolean isflipped(void); + void startDMA(void); + void stopDMA(); + + // Touch screen functions + #define TOUCH_ENABLED() ((_touch_cs != 255) && (_touch_irq != 255)) + bool isTouching(void) { return ((!TOUCH_ENABLED())?false:(digitalRead(_touch_irq) == LOW)); } + void readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax); + + // NoDMA functions + void writeScreenNoDma(const uint16_t *pcolors); + void fillScreenNoDma(uint16_t color); + void drawTextNoDma(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize); + void drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color); + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap); + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh); + + // DMA functions + uint16_t * getLineBuffer(int j); + void writeScreen(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int y, uint16_t *buf); + void fillScreen(uint16_t color); + void drawText(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize); + void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh); + + + protected: + uint8_t _rst, _cs, _dc; + uint8_t _miso, _mosi, _sclk; + uint8_t _touch_irq=255, _touch_cs=255; + bool flipped=false; + + void wait(void); + void enableTouchIrq(); +}; + +#endif +#endif + diff --git a/MCUME_teensy/teensygnuboy/tft_t_dma_config.h b/MCUME_teensy/teensygnuboy/tft_t_dma_config.h new file mode 100644 index 0000000..d603857 --- /dev/null +++ b/MCUME_teensy/teensygnuboy/tft_t_dma_config.h @@ -0,0 +1,10 @@ +//#define ST7789 1 +#define ILI9341 1 +#define TFT_LINEARINT 1 +#define LINEARINT_HACK 1 + +//#define FLIP_SCREEN 1 +//#define TFT_DEBUG 1 +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) +//#define TFT_STATICFB 1 +#endif diff --git a/MCUME_teensy/teensylogo/tft_t_dma.cpp b/MCUME_teensy/teensylogo/tft_t_dma.cpp index 79b3e15..b5d87b4 100644 --- a/MCUME_teensy/teensylogo/tft_t_dma.cpp +++ b/MCUME_teensy/teensylogo/tft_t_dma.cpp @@ -6,7 +6,7 @@ #include "font8x8.h" -#define SPICLOCK 144e6 //Just a number..max speed +#define SPICLOCK 60000000 //144e6 //Just a number..max speed #ifdef ILI9341 #define SPI_MODE SPI_MODE0 #endif diff --git a/MCUME_teensy/teensypce/emuapi.cpp b/MCUME_teensy/teensypce/emuapi.cpp index c8499ae..d317c8d 100644 --- a/MCUME_teensy/teensypce/emuapi.cpp +++ b/MCUME_teensy/teensypce/emuapi.cpp @@ -566,8 +566,9 @@ void emu_init(void) rc = f_chdrive(ROMSDIR); } #else - if (!SD.begin(SD_CS)) { + while (!SD.begin(SD_CS)) { emu_printf("SdFat.begin() failed"); + delay(1000); } strcpy(romspath,ROMSDIR); #endif diff --git a/MCUME_teensy/teensypce/psram_t.cpp b/MCUME_teensy/teensypce/psram_t.cpp index ba9d0f8..3a47eb8 100644 --- a/MCUME_teensy/teensypce/psram_t.cpp +++ b/MCUME_teensy/teensypce/psram_t.cpp @@ -10,7 +10,7 @@ #define SPI SPI2 //#define SPICLOCK 104000000 -#define SPICLOCK 60000000 +#define SPICLOCK 70000000 //#define SPICLOCK 144e6 //Just a number..max speed #define SPI_MODE SPI_MODE0 @@ -43,19 +43,20 @@ void PSRAM_T::begin(void) SPI.setMISO(_miso); SPI.setSCK(_sclk); SPI.begin(); - //SPI.setClockDivider(SPI_CLOCK_DIV2); + delay(1); - SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); SPI.transfer(0x66); digitalWrite(_cs, 1); SPI.endTransaction(); SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); digitalWrite(_cs, 0); SPI.transfer(0x99); - digitalWrite(_cs, 1); SPI.endTransaction(); + digitalWrite(_cs, 1); + delayMicroseconds(20); } @@ -64,8 +65,8 @@ uint8_t PSRAM_T::psram_read(uint32_t addr) { uint8_t val=0; + digitalWrite(_cs, 0); SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); - digitalWrite(_cs, 0); SPI.transfer(RAM_READ); SPI.transfer((addr>>16)&0xff); SPI.transfer((addr>>8)&0xff); @@ -73,17 +74,17 @@ uint8_t PSRAM_T::psram_read(uint32_t addr) #if RAM_READ == 0xB SPI.transfer(0xFF); #endif - val = SPI.transfer(0xFF); - digitalWrite(_cs, 1); + val = SPI.transfer(0xFF); SPI.endTransaction(); + digitalWrite(_cs, 1); return val; } void PSRAM_T::psram_read_n(uint32_t addr, uint8_t * val, int n) { - SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); SPI.transfer(RAM_READ); SPI.transfer((addr>>16)&0xff); SPI.transfer((addr>>8)&0xff); @@ -98,22 +99,22 @@ void PSRAM_T::psram_read_n(uint32_t addr, uint8_t * val, int n) } */ SPI.transfer(val,n); - digitalWrite(_cs, 1); SPI.endTransaction(); + digitalWrite(_cs, 1); } void PSRAM_T::psram_write(uint32_t addr, uint8_t val) { - SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); SPI.transfer(RAM_WRITE); SPI.transfer((addr>>16)&0xff); SPI.transfer((addr>>8)&0xff); SPI.transfer(addr&0xff); SPI.transfer(val); - digitalWrite(_cs, 1); SPI.endTransaction(); + digitalWrite(_cs, 1); } static uint8_t resp[PAGE_SIZE]; @@ -121,8 +122,8 @@ static uint8_t resp[PAGE_SIZE]; void PSRAM_T::psram_write_n(uint32_t addr, uint8_t * val, int n) { - SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); SPI.transfer(RAM_WRITE); SPI.transfer((addr>>16)&0xff); SPI.transfer((addr>>8)&0xff); @@ -134,8 +135,8 @@ void PSRAM_T::psram_write_n(uint32_t addr, uint8_t * val, int n) } */ SPI.transfer(val,&resp[0],n); - digitalWrite(_cs, 1); - SPI.endTransaction(); + SPI.endTransaction(); + digitalWrite(_cs, 1); } @@ -244,13 +245,15 @@ void PSRAM_T::pswrite(uint32_t addr, uint8_t val) } } -#include "emuapi.h" + + uint8_t PSRAM_T::psread(uint32_t addr) { - //return psram_read(addr); - + //uint8_t val = psram_read(addr); + //return val; uint32_t curPage=addr&(~(PAGE_SIZE-1)); + uint32_t offs = addr&(PAGE_SIZE-1); for (int i=0; i> 8]]; + *dst++=palette16[buf[pos >> 8]&PAL_COLOR_MASK]; pos +=step; } #endif } - else { + else if ((width*2) == TFT_WIDTH) { for (int i=0; i>3)&0xfc) #define B16(rgb) ((rgb<<3)&0xf8) +#define PAL_COLOR_MASK 0xff #define TFT_HEIGHT 240 diff --git a/MCUME_teensy/.DS_Store b/MCUME_teensy/teensysms/.DS_Store similarity index 82% rename from MCUME_teensy/.DS_Store rename to MCUME_teensy/teensysms/.DS_Store index e04ebeb1f3ffab0417a92d4ad6f48afac20f97a6..5008ddfcf53c02e82d7eee2e57c38e5672ef89f6 100644 GIT binary patch delta 70 zcmZoMXfc=|#>AjHu~2NHo+1YW5HK<@2y9-+n8vnw1EUw?W_AvK4xj>{$am(+{342+ UKzW7)kiy9(Jj$D6L{=~Z04H+~3jhEB delta 226 zcmZoMXfc=|#>B`mF;Q%yo}wrV0|Nsi1A_nqLoq`ogDHa%g8_rV#Kh(GAPFvp5{6VD z%tMwe3ogpb$+*x!4OTJ4@G}6Ln6?w5{5(}hH@aY5?S%a#B8?7 m1|lq*xjDEwfIirm_?>w&zlb6$6VNFNlMO|LH+zWeVFmzYDlPc{ diff --git a/MCUME_teensy/teensysms/AudioPlaySystem.cpp b/MCUME_teensy/teensysms/AudioPlaySystem.cpp new file mode 100644 index 0000000..cdcd71b --- /dev/null +++ b/MCUME_teensy/teensysms/AudioPlaySystem.cpp @@ -0,0 +1,196 @@ +#include "emuapi.h" + +#ifdef HAS_SND + +#include "AudioPlaySystem.h" +#include +#define SAMPLERATE AUDIO_SAMPLE_RATE_EXACT +#define CLOCKFREQ 985248 + +#ifndef CUSTOM_SND +PROGMEM static const short square[]={ +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +32767,32767,32767,32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767, +}; + +PROGMEM const short noise[] { +-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767, +-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,-32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,-32767,32767,32767,-32767, +-32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,-32767,-32767, +32767,-32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,-32767,32767,-32767,32767,32767,32767,-32767,-32767, +32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,-32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767, +32767,32767,-32767,-32767,-32767,32767,-32767,-32767,-32767,-32767,32767,32767,32767,32767,32767,-32767, +32767,-32767,32767,-32767,-32767,32767,32767,32767,32767,32767,-32767,32767,-32767,32767,-32767,-32767, +}; + +#define NOISEBSIZE 0x100 + +typedef struct +{ + unsigned int spos; + unsigned int sinc; + unsigned int vol; +} Channel; + +static Channel chan[6] = { + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0}, + {0,0,0} }; + +#endif + +volatile bool playing = false; + + + + +PROGMEM static void snd_Reset(void) +{ +#ifndef CUSTOM_SND + chan[0].vol = 0; + chan[1].vol = 0; + chan[2].vol = 0; + chan[3].vol = 0; + chan[4].vol = 0; + chan[5].vol = 0; + chan[0].sinc = 0; + chan[1].sinc = 0; + chan[2].sinc = 0; + chan[3].sinc = 0; + chan[4].sinc = 0; + chan[5].sinc = 0; +#endif +} + + +#ifdef CUSTOM_SND +void SND_Process(void *sndbuffer, int sndn); +#endif + +PROGMEM static void snd_Mixer(short * stream, int len ) +{ + if (playing) + { +#ifdef CUSTOM_SND + SND_Process((void*)stream, len); +#else + int i; + long s; + len = len >> 1; + + short v0=chan[0].vol; + short v1=chan[1].vol; + short v2=chan[2].vol; + short v3=chan[3].vol; + short v4=chan[4].vol; + short v5=chan[5].vol; + for (i=0;i>8)&0x3f])>>11); + s+=((v1*square[(chan[1].spos>>8)&0x3f])>>11); + s+=((v2*square[(chan[2].spos>>8)&0x3f])>>11); + s+=((v3*noise[(chan[3].spos>>8)&(NOISEBSIZE-1)])>>11); + s+=((v4*noise[(chan[4].spos>>8)&(NOISEBSIZE-1)])>>11); + s+=((v5*noise[(chan[5].spos>>8)&(NOISEBSIZE-1)])>>11); + *stream++ = (short)(s); + *stream++ = (short)(s); + chan[0].spos += chan[0].sinc; + chan[1].spos += chan[1].sinc; + chan[2].spos += chan[2].sinc; + chan[3].spos += chan[3].sinc; + chan[4].spos += chan[4].sinc; + chan[5].spos += chan[5].sinc; + } +#endif + } +} + +PROGMEM void AudioPlaySystem::begin(void) +{ + //emu_printf("AudioPlaySystem constructor"); + this->reset(); + setSampleParameters(CLOCKFREQ, SAMPLERATE); +} + +PROGMEM void AudioPlaySystem::start(void) +{ + //emu_printf("allocating sound buf"); + playing = true; +} + +PROGMEM void AudioPlaySystem::setSampleParameters(float clockfreq, float samplerate) { +} + +PROGMEM void AudioPlaySystem::reset(void) +{ + snd_Reset(); +} + +PROGMEM void AudioPlaySystem::stop(void) +{ + //__disable_irq(); + playing = false; + //__enable_irq(); +} + +PROGMEM bool AudioPlaySystem::isPlaying(void) +{ + return playing; +} + +PROGMEM void AudioPlaySystem::update(void) { + audio_block_t *block; + + // only update if we're playing + if (!playing) return; + + // allocate the audio blocks to transmit + block = allocate(); + if (block == NULL) return; + + snd_Mixer((short*)block->data,AUDIO_BLOCK_SAMPLES); + //memset( (void*)block->data, 0, AUDIO_BLOCK_SAMPLES*2); + + transmit(block); + release(block); +} + +PROGMEM void AudioPlaySystem::sound(int C, int F, int V) { +#ifndef CUSTOM_SND + if (C < 6) { + chan[C].vol = V; + chan[C].sinc = F>>1; + } +#endif +} + +PROGMEM void AudioPlaySystem::step(void) { +} +#endif + diff --git a/MCUME_teensy/teensysms/AudioPlaySystem.h b/MCUME_teensy/teensysms/AudioPlaySystem.h new file mode 100644 index 0000000..0333adb --- /dev/null +++ b/MCUME_teensy/teensysms/AudioPlaySystem.h @@ -0,0 +1,28 @@ +#ifndef audioplaysystem_h_ +#define audioplaysystem_h_ + +#ifdef HAS_SND + +#include + +class AudioPlaySystem : public AudioStream +{ +public: + AudioPlaySystem(void) : AudioStream(0, NULL) { begin(); } + void begin(void); + void setSampleParameters(float clockfreq, float samplerate); + void reset(void); + void start(void); + void stop(void); + bool isPlaying(void); + void sound(int C, int F, int V); + void buzz(int size, int val); + void step(void); + +private: + virtual void update(void); +}; +#endif + +#endif + diff --git a/MCUME_teensy/teensysms/arduinoproto.h b/MCUME_teensy/teensysms/arduinoproto.h new file mode 100644 index 0000000..289030c --- /dev/null +++ b/MCUME_teensy/teensysms/arduinoproto.h @@ -0,0 +1,7 @@ +#ifndef _ARDUINOPROTO_H_ +#define _ARDUINOPROTO_H_ + +#include +//#define PROGMEM + +#endif diff --git a/MCUME_teensy/teensysms/cpuintrf.h b/MCUME_teensy/teensysms/cpuintrf.h new file mode 100644 index 0000000..db20fd4 --- /dev/null +++ b/MCUME_teensy/teensysms/cpuintrf.h @@ -0,0 +1,383 @@ +#ifndef CPUINTRF_H +#define CPUINTRF_H + + +/* The old system is obsolete and no longer supported by the core */ +#define NEW_INTERRUPT_SYSTEM 1 + +#define MAX_IRQ_LINES 8 /* maximum number of IRQ lines per CPU */ + +#define CLEAR_LINE 0 /* clear (a fired, held or pulsed) line */ +#define ASSERT_LINE 1 /* assert an interrupt immediately */ +#define HOLD_LINE 2 /* hold interrupt line until enable is true */ +#define PULSE_LINE 3 /* pulse interrupt line for one instruction */ + +#define MAX_REGS 64 /* maximum number of register of any CPU */ + +/* Values passed to the cpu_info function of a core to retrieve information */ +enum { + CPU_INFO_REG, + CPU_INFO_FLAGS=MAX_REGS, + CPU_INFO_NAME, + CPU_INFO_FAMILY, + CPU_INFO_VERSION, + CPU_INFO_FILE, + CPU_INFO_CREDITS, + CPU_INFO_REG_LAYOUT, + CPU_INFO_WIN_LAYOUT +}; + +#define CPU_IS_LE 0 /* emulated CPU is little endian */ +#define CPU_IS_BE 1 /* emulated CPU is big endian */ + +/* + * This value is passed to cpu_get_reg to retrieve the previous + * program counter value, ie. before a CPU emulation started + * to fetch opcodes and arguments for the current instrution. + */ +#define REG_PREVIOUSPC -1 + +/* + * This value is passed to cpu_get_reg/cpu_set_reg, instead of one of + * the names from the enum a CPU core defines for it's registers, + * to get or set the contents of the memory pointed to by a stack pointer. + * You can specify the n'th element on the stack by (REG_SP_CONTENTS-n), + * ie. lower negative values. The actual element size (UINT16 or UINT32) + * depends on the CPU core. + * This is also used to replace the cpu_geturnpc() function. + */ +#define REG_SP_CONTENTS -2 + + +/* ASG 971222 -- added this generic structure */ +struct cpu_interface +{ + unsigned cpu_num; + void (*reset)(void *param); + void (*exit)(void); + int (*execute)(int cycles); + void (*burn)(int cycles); + unsigned (*get_context)(void *reg); + void (*set_context)(void *reg); + unsigned (*get_pc)(void); + void (*set_pc)(unsigned val); + unsigned (*get_sp)(void); + void (*set_sp)(unsigned val); + unsigned (*get_reg)(int regnum); + void (*set_reg)(int regnum, unsigned val); + void (*set_nmi_line)(int linestate); + void (*set_irq_line)(int irqline, int linestate); + void (*set_irq_callback)(int(*callback)(int irqline)); + void (*internal_interrupt)(int type); + void (*cpu_state_save)(void *file); + void (*cpu_state_load)(void *file); + const char* (*cpu_info)(void *context,int regnum); + unsigned (*cpu_dasm)(char *buffer,unsigned pc); + unsigned num_irqs; + int default_vector; + int *icount; + double overclock; + int no_int, irq_int, nmi_int; + int (*memory_read)(int offset); + void (*memory_write)(int offset, int data); + void (*set_op_base)(int pc); + int address_shift; + unsigned address_bits, endianess, align_unit, max_inst_len; + unsigned abits1, abits2, abitsmin; +}; + +extern struct cpu_interface cpuintf[]; + +void cpu_init(void); +void cpu_run(void); + +/* optional watchdog */ +void watchdog_reset_w(int offset,int data); +int watchdog_reset_r(int offset); +/* Use this function to reset the machine */ +void machine_reset(void); +/* Use this function to reset a single CPU */ +void cpu_set_reset_line(int cpu,int state); +/* Use this function to halt a single CPU */ +void cpu_set_halt_line(int cpu,int state); + +/* This function returns CPUNUM current status (running or halted) */ +int cpu_getstatus(int cpunum); +int cpu_gettotalcpu(void); +int cpu_getactivecpu(void); +void cpu_setactivecpu(int cpunum); + +/* Returns the current program counter */ +unsigned cpu_get_pc(void); +/* Set the current program counter */ +void cpu_set_pc(unsigned val); + +/* Returns the current stack pointer */ +unsigned cpu_get_sp(void); +/* Set the current stack pointer */ +void cpu_set_sp(unsigned val); + +/* Get the active CPUs context and return it's size */ +unsigned cpu_get_context(void *context); +/* Set the active CPUs context */ +void cpu_set_context(void *context); + +/* Returns a specific register value (mamedbg) */ +unsigned cpu_get_reg(int regnum); +/* Sets a specific register value (mamedbg) */ +void cpu_set_reg(int regnum, unsigned val); + +/* Returns previous pc (start of opcode causing read/write) */ +/* int cpu_getpreviouspc(void); */ +#define cpu_getpreviouspc() cpu_get_reg(REG_PREVIOUSPC) + +/* Returns the return address from the top of the stack (Z80 only) */ +/* int cpu_getreturnpc(void); */ +/* This can now be handled with a generic function */ +#define cpu_geturnpc() cpu_get_reg(REG_SP_CONTENTS) + +int cycles_currently_ran(void); +int cycles_left_to_run(void); + +/* Returns the number of CPU cycles which take place in one video frame */ +int cpu_gettotalcycles(void); +/* Returns the number of CPU cycles before the next interrupt handler call */ +int cpu_geticount(void); +/* Returns the number of CPU cycles before the end of the current video frame */ +int cpu_getfcount(void); +/* Returns the number of CPU cycles in one video frame */ +int cpu_getfperiod(void); +/* Scales a given value by the ratio of fcount / fperiod */ +int cpu_scalebyfcount(int value); +/* Returns the current scanline number */ +int cpu_getscanline(void); +/* Returns the amount of time until a given scanline */ +double cpu_getscanlinetime(int scanline); +/* Returns the duration of a single scanline */ +double cpu_getscanlineperiod(void); +/* Returns the duration of a single scanline in cycles */ +int cpu_getscanlinecycles(void); +/* Returns the number of cycles since the beginning of this frame */ +int cpu_getcurrentcycles(void); +/* Returns the current horizontal beam position in pixels */ +int cpu_gethorzbeampos(void); +/* + Returns the number of times the interrupt handler will be called before + the end of the current video frame. This is can be useful to interrupt + handlers to synchronize their operation. If you call this from outside + an interrupt handler, add 1 to the result, i.e. if it returns 0, it means + that the interrupt handler will be called once. +*/ +int cpu_getiloops(void); + +/* Returns the current VBLANK state */ +int cpu_getvblank(void); + +/* Returns the number of the video frame we are currently playing */ +int cpu_getcurrentframe(void); + + +/* generate a trigger after a specific period of time */ +void cpu_triggertime (double duration, int trigger); +/* generate a trigger now */ +void cpu_trigger (int trigger); + +/* burn CPU cycles until a timer trigger */ +void cpu_spinuntil_trigger (int trigger); +/* burn CPU cycles until the next interrupt */ +void cpu_spinuntil_int (void); +/* burn CPU cycles until our timeslice is up */ +void cpu_spin (void); +/* burn CPU cycles for a specific period of time */ +void cpu_spinuntil_time (double duration); + +/* yield our timeslice for a specific period of time */ +void cpu_yielduntil_trigger (int trigger); +/* yield our timeslice until the next interrupt */ +void cpu_yielduntil_int (void); +/* yield our current timeslice */ +void cpu_yield (void); +/* yield our timeslice for a specific period of time */ +void cpu_yielduntil_time (double duration); + +/* set the NMI line state for a CPU, normally use PULSE_LINE */ +void cpu_set_nmi_line(int cpunum, int state); +/* set the IRQ line state for a specific irq line of a CPU */ +/* normally use state HOLD_LINE, irqline 0 for first IRQ type of a cpu */ +void cpu_set_irq_line(int cpunum, int irqline, int state); +/* this is to be called by CPU cores only! */ +void cpu_generate_internal_interrupt(int cpunum, int type); +/* set the vector to be returned during a CPU's interrupt acknowledge cycle */ +void cpu_irq_line_vector_w(int cpunum, int irqline, int vector); + +/* use these in your write memory/port handles to set an IRQ vector */ +/* offset corresponds to the irq line number here */ +void cpu_0_irq_line_vector_w(int offset, int data); +void cpu_1_irq_line_vector_w(int offset, int data); +void cpu_2_irq_line_vector_w(int offset, int data); +void cpu_3_irq_line_vector_w(int offset, int data); +void cpu_4_irq_line_vector_w(int offset, int data); +void cpu_5_irq_line_vector_w(int offset, int data); +void cpu_6_irq_line_vector_w(int offset, int data); +void cpu_7_irq_line_vector_w(int offset, int data); + +/* Obsolete functions: avoid to use them in new drivers if possible. */ + +/* cause an interrupt on a CPU */ +void cpu_cause_interrupt(int cpu,int type); +void cpu_clear_pending_interrupts(int cpu); +void interrupt_enable_w(int offset,int data); +void interrupt_vector_w(int offset,int data); +int interrupt(void); +int nmi_interrupt(void); +int m68_level1_irq(void); +int m68_level2_irq(void); +int m68_level3_irq(void); +int m68_level4_irq(void); +int m68_level5_irq(void); +int m68_level6_irq(void); +int m68_level7_irq(void); +int ignore_interrupt(void); + +/* CPU context access */ +void* cpu_getcontext (int _activecpu); +int cpu_is_saving_context(int _activecpu); + +/*************************************************************************** + * Get information for the currently active CPU + * cputype is a value from the CPU enum in driver.h + ***************************************************************************/ +/* Return number of address bits */ +unsigned cpu_address_bits(void); +/* Return address mask */ +unsigned cpu_address_mask(void); +/* Return address shift factor (TMS34010 bit addressing mode) */ +int cpu_address_shift(void); +/* Return endianess of the emulated CPU (CPU_IS_LE or CPU_IS_BE) */ +unsigned cpu_endianess(void); +/* Return opcode align unit (1 byte, 2 word, 4 dword) */ +unsigned cpu_align_unit(void); +/* Return maximum instruction length */ +unsigned cpu_max_inst_len(void); + +/* Return name of the active CPU */ +const char *cpu_name(void); +/* Return family name of the active CPU */ +const char *cpu_core_family(void); +/* Return core version of the active CPU */ +const char *cpu_core_version(void); +/* Return core filename of the active CPU */ +const char *cpu_core_file(void); +/* Return credits info for of the active CPU */ +const char *cpu_core_credits(void); +/* Return register layout definition for the active CPU */ +const char *cpu_reg_layout(void); +/* Return (debugger) window layout definition for the active CPU */ +const char *cpu_win_layout(void); + +/* Disassemble an instruction at PC into the given buffer */ +unsigned cpu_dasm(char *buffer, unsigned pc); +/* Return a string describing the currently set flag (status) bits of the active CPU */ +const char *cpu_flags(void); +/* Return a string with a register name and hex value for the active CPU */ +/* regnum is a value defined in the CPU cores header files */ +const char *cpu_dump_reg(int regnum); +/* Return a string describing the active CPUs current state */ +const char *cpu_dump_state(void); + +/*************************************************************************** + * Get information for a specific CPU type + * cputype is a value from the CPU enum in driver.h + ***************************************************************************/ +/* Return address shift factor */ +/* TMS320C10 -1: word addressing mode, TMS34010 3: bit addressing mode */ +int cputype_address_shift(int cputype); +/* Return number of address bits */ +unsigned cputype_address_bits(int cputype); +/* Return address mask */ +unsigned cputype_address_mask(int cputype); +/* Return endianess of the emulated CPU (CPU_IS_LE or CPU_IS_BE) */ +unsigned cputype_endianess(int cputype); +/* Return opcode align unit (1 byte, 2 word, 4 dword) */ +unsigned cputype_align_unit(int cputype); +/* Return maximum instruction length */ +unsigned cputype_max_inst_len(int cputype); + +/* Return name of the CPU */ +const char *cputype_name(int cputype); +/* Return family name of the CPU */ +const char *cputype_core_family(int cputype); +/* Return core version number of the CPU */ +const char *cputype_core_version(int cputype); +/* Return core filename of the CPU */ +const char *cputype_core_file(int cputype); +/* Return credits for the CPU core */ +const char *cputype_core_credits(int cputype); +/* Return register layout definition for the CPU core */ +const char *cputype_reg_layout(int cputype); +/* Return (debugger) window layout definition for the CPU core */ +const char *cputype_win_layout(int cputype); + +/*************************************************************************** + * Get (or set) information for a numbered CPU of the running machine + * cpunum is a value between 0 and cpu_gettotalcpu() - 1 + ***************************************************************************/ +/* Return number of address bits */ +unsigned cpunum_address_bits(int cputype); +/* Return address mask */ +unsigned cpunum_address_mask(int cputype); +/* Return endianess of the emulated CPU (CPU_LSB_FIRST or CPU_MSB_FIRST) */ +unsigned cpunum_endianess(int cputype); +/* Return opcode align unit (1 byte, 2 word, 4 dword) */ +unsigned cpunum_align_unit(int cputype); +/* Return maximum instruction length */ +unsigned cpunum_max_inst_len(int cputype); + +/* Get a register value for the specified CPU number of the running machine */ +unsigned cpunum_get_reg(int cpunum, int regnum); +/* Set a register value for the specified CPU number of the running machine */ +void cpunum_set_reg(int cpunum, int regnum, unsigned val); + +/* Return (debugger) register layout definition for the CPU core */ +const char *cpunum_reg_layout(int cpunum); +/* Return (debugger) window layout definition for the CPU core */ +const char *cpunum_win_layout(int cpunum); + +unsigned cpunum_dasm(int cpunum,char *buffer,unsigned pc); +/* Return a string describing the currently set flag (status) bits of the CPU */ +const char *cpunum_flags(int cpunum); +/* Return a string with a register name and value */ +/* regnum is a value defined in the CPU cores header files */ +const char *cpunum_dump_reg(int cpunum, int regnum); +/* Return a string describing the CPUs current state */ +const char *cpunum_dump_state(int cpunum); +/* Return a name for the specified cpu number */ +const char *cpunum_name(int cpunum); +/* Return a family name for the specified cpu number */ +const char *cpunum_core_family(int cpunum); +/* Return a version for the specified cpu number */ +const char *cpunum_core_version(int cpunum); +/* Return a the source filename for the specified cpu number */ +const char *cpunum_core_file(int cpunum); +/* Return a the credits for the specified cpu number */ +const char *cpunum_core_credits(int cpunum); + +/* Dump all of the running machines CPUs state to stderr */ +void cpu_dump_states(void); + +/* daisy-chain link */ +typedef struct { + void (*reset)(int); /* reset callback */ + int (*interrupt_entry)(int); /* entry callback */ + void (*interrupt_reti)(int); /* reti callback */ + int irq_param; /* callback paramater */ +} Z80_DaisyChain; + +#define Z80_MAXDAISY 4 /* maximum of daisy chan device */ + +#define Z80_INT_REQ 0x01 /* interrupt request mask */ +#define Z80_INT_IEO 0x02 /* interrupt disable mask(IEO) */ + +#define Z80_VECTOR(device,state) (((device)<<8)|(state)) + +#endif /* CPUINTRF_H */ diff --git a/MCUME_teensy/teensysms/emu.cpp b/MCUME_teensy/teensysms/emu.cpp new file mode 100644 index 0000000..feb0191 --- /dev/null +++ b/MCUME_teensy/teensysms/emu.cpp @@ -0,0 +1,159 @@ +#include + +#include "emuapi.h" +#include "tft_t_dma.h" +#include "psram_t.h" +#include "iopins.h" + +extern "C" { +#include "shared.h" +} + +static int rom_offset = 0; + +PSRAM_T psram = PSRAM_T(PSRAM_CS, PSRAM_MOSI, PSRAM_SCLK, PSRAM_MISO); + + +extern "C" uint8 read_rom(int address) { + return (psram.psread(address+rom_offset)); +} + +//extern "C" uint8 readb_swap_rom(int address) { +// return(psram.psread(address^1)); +//} + +//extern "C" uint16 readw_swap_rom(int address) { +// return psram.psread_w(address); +//} + +extern "C" void write_rom(int address, uint8 val) { + psram.pswrite(address,val); +} + + + + +void gen_Init(void) +{ + emu_printf("Allocating MEM"); + psram.begin(); + mem_init(); + emu_printf("Allocating MEM done"); +} + + +static int hk = 0; +static int k = 0; + + +void gen_Input(int click) { + hk = emu_ReadI2CKeyboard(); + k = emu_ReadKeys(); +} + + + +void gen_Start(char * filename) +{ + emu_printf("load and init"); + + int size = emu_FileSize(filename); + int pos = 0; + int n; + int i; + char * buf = (char*)cache; + + if (emu_FileOpen(filename)) { + while ( (n = emu_FileRead(buf,CACHE_SIZE) ) ) { + for (int i=0; i 4) { + if ( (!strcmp(&filename[namelen-4],".sms")) || (!strcmp(&filename[namelen-4],".SMS")) ) { + emu_printf("Master system"); + cart.type = TYPE_SMS; + } + else { + emu_printf("Game Gear"); + cart.type = TYPE_GG; + } + } + + + + + +#ifdef SOUND_PRESENT +#ifdef HAS_SND + system_init(22050); + emu_sndInit(); +#endif +#else + system_init(0); +#endif + + + emu_printf("init done"); +} + +void gen_Step(void) +{ + input.pad[0]=0; + + if (( k & MASK_JOY1_RIGHT) || ( k & MASK_JOY2_RIGHT)) { + input.pad[0] |= INPUT_RIGHT; + } + if (( k & MASK_JOY1_LEFT) || ( k & MASK_JOY2_LEFT)) { + input.pad[0] |= INPUT_LEFT; + } + if (( k & MASK_JOY1_UP) || ( k & MASK_JOY2_UP)) { + input.pad[0] |= INPUT_UP; + } + if (( k & MASK_JOY1_DOWN) || ( k & MASK_JOY2_DOWN)) { + input.pad[0] |= INPUT_DOWN; + } + if ( k & MASK_JOY2_BTN) { + input.pad[0] |= INPUT_BUTTON1; + } + + if (k & MASK_KEY_USER1) { + input.pad[0] |= INPUT_BUTTON2; + } + +// if(check_key(KEY_DEL)) input.system |= INPUT_HARD_RESET; +// if(check_key(KEY_TAB)) input.system |= (IS_GG) ? INPUT_HARD_RESET : INPUT_SOFT_RESET; + if (k & MASK_KEY_USER2) input.system |= (IS_GG) ? INPUT_START : INPUT_PAUSE; + + sms_frame(0); + //emu_printi(emu_FrameSkip()); + + emu_DrawVsync(); +} + +void SND_Process(void *stream, int len) { +#ifdef SOUND_PRESENT +#ifdef HAS_SND + audio_play_sample(stream, 0, len); +#endif +#endif +} + + + + diff --git a/MCUME_teensy/teensysms/emu.h b/MCUME_teensy/teensysms/emu.h new file mode 100644 index 0000000..960a514 --- /dev/null +++ b/MCUME_teensy/teensysms/emu.h @@ -0,0 +1,5 @@ +extern void gen_Init(void); +extern void gen_Step(void); +extern void gen_Start(char * filename); +extern void gen_Input(int click); + diff --git a/MCUME_teensy/teensysms/emuapi.cpp b/MCUME_teensy/teensysms/emuapi.cpp new file mode 100644 index 0000000..d317c8d --- /dev/null +++ b/MCUME_teensy/teensysms/emuapi.cpp @@ -0,0 +1,1196 @@ +#define KEYMAP_PRESENT 1 + +extern "C" { + #include "emuapi.h" + #include "iopins.h" +} + +#include "tft_t_dma.h" +//#include "logo.h" +//#include "bmpjoy.h" +//#include "bmpvbar.h" +//#include "bmpvga.h" +//#include "bmptft.h" + +#ifndef SD_CS +#define USE_SDFS 1 +#endif + +#ifdef HAS_I2CKBD +#include +#endif + +#ifdef USE_SDFS +#define SDFSDEV "2:" + +#include "uSDFS.h" +static FATFS fatfs; +static FIL file; +#else +#include +static File file; +#endif + +extern TFT_T_DMA tft; +static char romspath[64]; +static int16_t calMinX=-1,calMinY=-1,calMaxX=-1,calMaxY=-1; +static bool i2cKeyboardPresent = false; +const uint16_t deflogo[] = { + 0x0000,0x0000 +}; +static const uint16_t * logo = deflogo; + +#ifdef USE_SDFS +#define CALIBRATION_FILE SDFSDEV "/cal.cfg" +#else +#define CALIBRATION_FILE "/cal.cfg" +#endif +#define MAX_FILES 128 +#define MAX_FILENAME_SIZE 28 +#define MAX_MENULINES (MKEY_L9) +#define TEXT_HEIGHT 16 +#define TEXT_WIDTH 8 +#define MENU_FILE_XOFFSET (6*TEXT_WIDTH) +#define MENU_FILE_YOFFSET (2*TEXT_HEIGHT) +#define MENU_FILE_W (MAX_FILENAME_SIZE*TEXT_WIDTH) +#define MENU_FILE_H (MAX_MENULINES*TEXT_HEIGHT) +#define MENU_FILE_BGCOLOR RGBVAL16(0x00,0x00,0x20) +#define MENU_JOYS_YOFFSET (12*TEXT_HEIGHT) +#define MENU_VBAR_XOFFSET (0*TEXT_WIDTH) +#define MENU_VBAR_YOFFSET (MENU_FILE_YOFFSET) + +#define MENU_TFT_XOFFSET (MENU_FILE_XOFFSET+MENU_FILE_W+8) +#define MENU_TFT_YOFFSET (MENU_VBAR_YOFFSET+32) +//#define MENU_VGA_XOFFSET (MENU_FILE_XOFFSET+MENU_FILE_W+8) +//#define MENU_VGA_YOFFSET (MENU_VBAR_YOFFSET+MENU_FILE_H-32-37) + + +#define MKEY_L1 1 +#define MKEY_L2 2 +#define MKEY_L3 3 +#define MKEY_L4 4 +#define MKEY_L5 5 +#define MKEY_L6 6 +#define MKEY_L7 7 +#define MKEY_L8 8 +#define MKEY_L9 9 +#define MKEY_UP 20 +#define MKEY_DOWN 21 +#define MKEY_JOY 22 +#define MKEY_TFT 23 +#define MKEY_VGA 24 + +const unsigned short menutouchareas[] = { + TAREA_XY,MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, + TAREA_WH,MENU_FILE_W, TEXT_HEIGHT, + TAREA_NEW_COL,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT,TEXT_HEIGHT, + + TAREA_XY,MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET, + TAREA_WH,32,48, + TAREA_NEW_COL, 72,72,8,40, + + TAREA_XY,MENU_TFT_XOFFSET,MENU_TFT_YOFFSET, + TAREA_WH,32,37, + TAREA_NEW_COL, 38,38, + + TAREA_END}; + +const unsigned short menutouchactions[] = { + MKEY_L1,MKEY_L2,MKEY_L3,MKEY_L4,MKEY_L5,MKEY_L6,MKEY_L7,MKEY_L8,MKEY_L9, + MKEY_UP,MKEY_DOWN,ACTION_NONE,MKEY_JOY, + MKEY_TFT,MKEY_VGA}; + + +static bool menuOn=true; +static bool callibrationOn=false; +static int callibrationStep=0; +static bool menuRedraw=true; +static int nbFiles=0; +static int curFile=0; +static int topFile=0; +static char selection[MAX_FILENAME_SIZE+1]=""; +static uint8_t prev_zt=0; + +static char files[MAX_FILES][MAX_FILENAME_SIZE]; + +static int readNbFiles(void) { + int totalFiles = 0; + +#ifdef USE_SDFS + DIR dir; + FILINFO entry; + f_opendir(&dir, romspath); + while ( (true) && (totalFiles= y1) && (yt < y2) && (xt >= x1) && (xt < x2) ) { + *rx = x1; + *ry = y1; + *rw = x2-x1; + *rh = y2-y1; + return (actions[k]); + } + k++; + } + } + } + prev_zt =1; + } else { + prev_zt=0; + } + + return ACTION_NONE; +} + +void toggleMenu(bool on) { + if (on) { + callibrationOn=false; + menuOn=true; + menuRedraw=true; + tft.fillScreenNoDma(RGBVAL16(0x00,0x00,0x00)); + tft.drawTextNoDma(0,0, TITLE, RGBVAL16(0x00,0xff,0xff), RGBVAL16(0x00,0x00,0xff), true); + //tft.drawSpriteNoDma(MENU_VBAR_XOFFSET,MENU_VBAR_YOFFSET,(uint16_t*)bmpvbar); + //tft.drawSpriteNoDma(MENU_TFT_XOFFSET,MENU_TFT_YOFFSET,(uint16_t*)bmptft); + //tft.drawSpriteNoDma(MENU_VGA_XOFFSET,MENU_VGA_YOFFSET,(uint16_t*)bmpvga); + } else { + menuOn = false; + } +} + + +static void callibrationInit(void) +{ + callibrationOn=true; + menuOn=false; + callibrationStep = 0; + calMinX=0,calMinY=0,calMaxX=0,calMaxY=0; + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration process:", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " Hit the red cross at each corner", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + prev_zt = 1; +} + + +static void readCallibration(void) +{ + char fileBuffer[64]; + +#ifdef USE_SDFS + FIL file; + int retval; + if( !(f_open(&file, CALIBRATION_FILE, FA_READ)) ) { + if( !(f_read (&file, fileBuffer, 64, &retval)) ) { + if (retval == 64) { + sscanf(fileBuffer,"%d %d %d %d", &calMinX,&calMinY,&calMaxX,&calMaxY); + } + } + f_close(&file); + } +#else + File file = SD.open(CALIBRATION_FILE, O_READ); + if (file) { + if ( file.read(fileBuffer, 64) ) { + sscanf(fileBuffer,"%d %d %d %d", &calMinX,&calMinY,&calMaxX,&calMaxY); + } + file.close(); + Serial.println("Current callibration params:"); + Serial.println(calMinX); + Serial.println(calMinY); + Serial.println(calMaxX); + Serial.println(calMaxY); + } + else { + Serial.println("Callibration read error"); + } +#endif + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); +} + +static void writeCallibration(void) +{ + tft.callibrateTouch(calMinX,calMinY,calMaxX,calMaxY); +#ifdef USE_SDFS + FIL file; + int retval; + if( !(f_open(&file, CALIBRATION_FILE, FA_WRITE)) ) { + //if( !(f_read (&file, fileBuffer, 64, &retval)) ) { + // if (retval == 64) { + // sscanf(fileBuffer,"%d %d %d %d", &calMinX,&calMinY,&calMaxX,&calMaxY); + // } + //} + f_close(&file); + } + +#else + File file = SD.open(CALIBRATION_FILE, O_WRITE | O_CREAT | O_TRUNC); + if (file) { + file.print(calMinX); + file.print(" "); + file.print(calMinY); + file.print(" "); + file.print(calMaxX); + file.print(" "); + file.println(calMaxY); + file.close(); + } + else { + Serial.println("Callibration write error"); + } +#endif +} + + +bool callibrationActive(void) +{ + return (callibrationOn); +} + + + +int handleCallibration(uint16_t bClick) { + uint16_t xt=0; + uint16_t yt=0; + uint16_t zt=0; + if (tft.isTouching()) { + if (prev_zt == 0) { + prev_zt = 1; + tft.readRaw(&xt,&yt,&zt); + if (zt < 1000) { + return 0; + } + switch (callibrationStep) + { + case 0: + callibrationStep++; + tft.drawTextNoDma(0,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(TFT_REALWIDTH-8,0, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMinX += xt; + calMinY += yt; + break; + case 1: + callibrationStep++; + tft.drawTextNoDma(TFT_REALWIDTH-8,0, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(TFT_REALWIDTH-8,TFT_REALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMinY += yt; + break; + case 2: + callibrationStep++; + tft.drawTextNoDma(TFT_REALWIDTH-8,TFT_REALHEIGHT-16, " ", RGBVAL16(0xff,0xff,0xff), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,TFT_REALHEIGHT-16, "+", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + calMaxX += xt; + calMaxY += yt; + break; + case 3: + tft.fillScreenNoDma(RGBVAL16(0xff,0xff,0xff)); + tft.drawTextNoDma(0,100, " Callibration done!", RGBVAL16(0x00,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + tft.drawTextNoDma(0,116, " (Click center to exit)", RGBVAL16(0xff,0x00,0x00), RGBVAL16(0xff,0xff,0xff), true); + callibrationStep++; + calMinX += xt; + calMaxY += yt; + break; + case 4: + //Serial.println(xt); + //Serial.println(yt); + if ( (xt > (TFT_REALWIDTH/4)) && (xt < (TFT_REALWIDTH*3)/4) + && (yt > (TFT_REALHEIGHT/4)) && (yt < (TFT_REALHEIGHT*3)/4) ) { + calMinX /= 2; + calMinY /= 2; + calMaxX /= 2; + calMaxY /= 2; + writeCallibration(); + toggleMenu(true); + } + else { + callibrationInit(); + } + break; + + } + delay(100); + } + } + else { + prev_zt = 0; + } +} + + + +bool menuActive(void) +{ + return (menuOn); +} + +int handleMenu(uint16_t bClick) +{ + int action = ACTION_NONE; + + char newpath[80]; + strcpy(newpath, romspath); + strcat(newpath, "/"); + strcat(newpath, selection); + + int rx=0,ry=0,rw=0,rh=0; + char c = captureTouchZone(menutouchareas, menutouchactions, &rx,&ry,&rw,&rh); + + if ( (bClick & MASK_JOY2_BTN) || (c == MKEY_TFT) ) { + emu_printf(newpath); +#ifdef USE_SDFS + FILINFO entry; + f_stat(newpath, &entry); + if ( (entry.fattrib & AM_DIR) ) { +#else + File file = SD.open(newpath); + if (file.isDirectory()) { +#endif + strcpy(romspath,newpath); + curFile = 0; + nbFiles = readNbFiles(); + } + else { + action = ACTION_RUNTFT; + } + menuRedraw=true; + } + else if ( (bClick & MASK_KEY_USER1) || (c == MKEY_VGA) ) { + menuRedraw=true; + action = ACTION_RUNVGA; + } + else if ( (c >= MKEY_L1) && (c <= MKEY_L9) ) { + if ( (topFile+(int)c-1) <= (nbFiles-1) ) + { + curFile = topFile + (int)c -1; + menuRedraw=true; + //tft.drawRectNoDma( rx,ry,rw,rh, KEYBOARD_HIT_COLOR ); + } + } + else if (bClick & MASK_JOY2_UP) { + if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if ( (bClick & MASK_JOY2_RIGHT) || (bClick & MASK_JOY1_RIGHT) || (c == MKEY_UP) ) { + if ((curFile-9)>=0) { + menuRedraw=true; + curFile -= 9; + } else if (curFile!=0) { + menuRedraw=true; + curFile--; + } + } + else if (bClick & MASK_JOY2_DOWN) { + if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_JOY2_LEFT) || (bClick & MASK_JOY1_LEFT) || (c == MKEY_DOWN) ) { + if ((curFile<(nbFiles-9)) && (nbFiles)) { + curFile += 9; + menuRedraw=true; + } + else if ((curFile<(nbFiles-1)) && (nbFiles)) { + curFile++; + menuRedraw=true; + } + } + else if ( (bClick & MASK_KEY_USER2) || (c == MKEY_JOY) ) { + emu_SwapJoysticks(0); + menuRedraw=true; + } + + if (menuRedraw && nbFiles) { + int fileIndex = 0; + tft.drawRectNoDma(MENU_FILE_XOFFSET,MENU_FILE_YOFFSET, MENU_FILE_W, MENU_FILE_H, MENU_FILE_BGCOLOR); +// if (curFile <= (MAX_MENULINES/2-1)) topFile=0; +// else topFile=curFile-(MAX_MENULINES/2); + if (curFile <= (MAX_MENULINES-1)) topFile=0; + else topFile=curFile-(MAX_MENULINES/2); + + //Serial.print("curfile: "); + //Serial.println(curFile); + //Serial.print("topFile: "); + //Serial.println(topFile); + + int i=0; + while (i=nbFiles) { + // no more files + break; + } + char * filename = &files[fileIndex][0]; + if (fileIndex >= topFile) { + if ((i+topFile) < nbFiles ) { + if ((i+topFile)==curFile) { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, filename, RGBVAL16(0xff,0xff,0x00), RGBVAL16(0xff,0x00,0x00), true); + strcpy(selection,filename); + } + else { + tft.drawTextNoDma(MENU_FILE_XOFFSET,i*TEXT_HEIGHT+MENU_FILE_YOFFSET, filename, 0xFFFF, 0x0000, true); + } + } + i++; + } + fileIndex++; + } + + //tft.drawSpriteNoDma(0,MENU_JOYS_YOFFSET,(uint16_t*)bmpjoy); + tft.drawTextNoDma(48,MENU_JOYS_YOFFSET+8, (emu_SwapJoysticks(1)?(char*)"SWAP=1":(char*)"SWAP=0"), RGBVAL16(0x00,0xff,0xff), RGBVAL16(0xff,0x00,0x00), false); + menuRedraw=false; + } + + return (action); +} + +char * menuSelection(void) +{ + return (selection); +} + + + + +void emu_init(void) +{ + Serial.begin(115200); + //while (!Serial) {} +#ifdef USE_SDFS + strcpy(romspath,SDFSDEV); + strcat(romspath,ROMSDIR); + FRESULT rc; + if((rc = f_mount (&fatfs, romspath, 1))) { + emu_printf("Fail mounting SDFS"); + } + else { + rc = f_chdrive(ROMSDIR); + } +#else + while (!SD.begin(SD_CS)) { + emu_printf("SdFat.begin() failed"); + delay(1000); + } + strcpy(romspath,ROMSDIR); +#endif + nbFiles = readNbFiles(); + + Serial.print("SD initialized, files found: "); + Serial.println(nbFiles); + + emu_InitJoysticks(); + readCallibration(); + + if ((tft.isTouching()) || (emu_ReadKeys() & MASK_JOY2_BTN) ) { + callibrationInit(); + } + else + { + toggleMenu(true); + } + +#ifdef HAS_I2CKBD + byte msg[7]={0,0,0,0,0,0,0}; + Wire.begin(); // join i2c bus SDA2/SCL2 + Wire.requestFrom(8, 7); // request 7 bytes from slave device #8 + int i = 0; + while (Wire.available() && (i<7) ) { // slave may send less than requested + byte b = Wire.read(); // receive a byte + msg[i++] = b; + } + /* + Serial.println(msg[0], BIN); + Serial.println(msg[1], BIN); + Serial.println(msg[2], BIN); + Serial.println(msg[3], BIN); + Serial.println(msg[4], BIN); + Serial.println(msg[5], BIN); + Serial.println(msg[6], BIN); + */ + if ( (msg[0] == 0xff) && (msg[1] == 0xff) && + (msg[2] == 0xff) && (msg[3] == 0xff) && + (msg[4] == 0xff) && (msg[5] == 0xff) && (msg[6] == 0xff)) { + i2cKeyboardPresent = true; + Serial.println("i2C keyboard found"); + } +#endif +} + + +void emu_printf(char * text) +{ + Serial.println(text); +} + +void emu_printf(int val) +{ + Serial.println(val); +} + +void emu_printi(int val) +{ + Serial.println(val); +} + +void emu_printh(int val) +{ + Serial.println(val,HEX); +} + +static int malbufpt = 0; +static char malbuf[EXTRA_HEAP]; + +void * emu_Malloc(int size) +{ + void * retval = malloc(size); + if (!retval) { + emu_printf("failled to allocate"); + emu_printf(size); + emu_printf("fallback"); + if ( (malbufpt+size) < sizeof(malbuf) ) { + retval = (void *)&malbuf[malbufpt]; + malbufpt += size; + } + else { + emu_printf("failure to allocate"); + } + } + else { + emu_printf("could allocate "); + emu_printf(size); + } + + return retval; +} + +void emu_Free(void * pt) +{ + free(pt); +} + + + +int emu_FileOpen(char * filename) +{ + int retval = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("FileOpen..."); + emu_printf(filepath); +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { +#else + if ((file = SD.open(filepath, O_READ))) { +#endif + retval = 1; + } + else { + emu_printf("FileOpen failed"); + } + return (retval); +} + +int emu_FileRead(char * buf, int size) +{ + unsigned char buffer[256]; + + int remaining = size; + int byteread = 0; + int retval=0; + while (remaining>0) { +#ifdef USE_SDFS + if( !(f_read (&file, buffer, 256, &retval)) ) + //f_read (&file, buffer, 256, &retval); +#else + retval = file.read(buffer, 256); +#endif + if (retval>0) { + //emu_printi(retval); + memcpy(buf,buffer,retval); + buf += retval; + byteread += retval; + remaining -= retval; + } + else { + break; + } + } + + return byteread; +} + +unsigned char emu_FileGetc(void) { + unsigned char c; +#ifdef USE_SDFS + int retval=0; + if( !(f_read (&file, &c, 1, &retval)) ) +#else + int retval = file.read(&c, 1); +#endif + if (retval != 1) { + emu_printf("emu_FileGetc failed"); + } + return c; +} + + +void emu_FileClose(void) +{ +#ifdef USE_SDFS + f_close(&file); +#else + file.close(); +#endif +} + +int emu_FileSize(char * filename) +{ + int filesize=0; + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("FileSize..."); + emu_printf(filepath); +#ifdef USE_SDFS + FILINFO entry; + f_stat(filepath, &entry); + filesize = entry.fsize; +#else + if ((file = SD.open(filepath, O_READ))) + { + emu_printf("filesize is..."); + filesize = file.size(); + emu_printf(filesize); + file.close(); + } +#endif + + return(filesize); +} + +int emu_FileSeek(int seek) +{ +#ifdef USE_SDFS + f_lseek(&file, seek); +#else + file.seek(seek); +#endif + return (seek); +} + +int emu_FileTell(void) +{ +#ifdef USE_SDFS + return (f_tell(&file)); +#else + return (50); +#endif +} + + +int emu_LoadFile(char * filename, char * buf, int size) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("LoadFile..."); + emu_printf(filepath); +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { + filesize = f_size(&file); + emu_printf(filesize); + if (size >= filesize) + { + int retval=0; + if( (f_read (&file, buf, filesize, &retval)) ) { + emu_printf("File read failed"); + } + } + f_close(&file); + } +#else + if ((file = SD.open(filepath, O_READ))) + { + filesize = file.size(); + emu_printf(filesize); + + if (size >= filesize) + { + if (emu_FileRead(buf, filesize) != filesize) + { + emu_printf("File read failed"); + } + } + file.close(); + } +#endif + + return(filesize); +} + +int emu_LoadFileSeek(char * filename, char * buf, int size, int seek) +{ + int filesize = 0; + + char filepath[80]; + strcpy(filepath, romspath); + strcat(filepath, "/"); + strcat(filepath, filename); + emu_printf("LoadFileSeek..."); + emu_printf(filepath); +#ifdef USE_SDFS + if( !(f_open(&file, filepath, FA_READ)) ) { + f_lseek(&file, seek); + emu_printf(size); + if (size >= filesize) + { + int retval=0; + if( (!f_read (&file, buf, size, &retval)) ) + if (retval != size) + { + emu_printf("File read failed"); + } + } + f_close(&file); + } +#else + if ((file = SD.open(filepath, O_READ))) + { + file.seek(seek); + emu_printf(size); + if (file.read(buf, size) != size) { + emu_printf("File read failed"); + } + file.close(); + } +#endif + + return(filesize); +} + +static int keypadval=0; +static boolean joySwapped = false; +static uint16_t bLastState; +static int xRef; +static int yRef; + + +int emu_ReadAnalogJoyX(int min, int max) +{ + int val = analogRead(PIN_JOY2_A1X); +#if INVX + val = 4095 - val; +#endif + val = val-xRef; + val = ((val*140)/100); + if ( (val > -512) && (val < 512) ) val = 0; + val = val+2048; + return (val*(max-min))/4096; +} + +int emu_ReadAnalogJoyY(int min, int max) +{ + int val = analogRead(PIN_JOY2_A2Y); +#if INVY + val = 4095 - val; +#endif + val = val-yRef; + val = ((val*120)/100); + if ( (val > -512) && (val < 512) ) val = 0; + //val = (val*(max-min))/4096; + val = val+2048; + //return val+(max-min)/2; + return (val*(max-min))/4096; +} + + +static uint16_t readAnalogJoystick(void) +{ + uint16_t joysval = 0; + + int xReading = emu_ReadAnalogJoyX(0,256); + if (xReading > 128) joysval |= MASK_JOY2_LEFT; + else if (xReading < 128) joysval |= MASK_JOY2_RIGHT; + + int yReading = emu_ReadAnalogJoyY(0,256); + if (yReading < 128) joysval |= MASK_JOY2_UP; + else if (yReading > 128) joysval |= MASK_JOY2_DOWN; + +#ifdef PIN_JOY2_BTN + joysval |= (digitalRead(PIN_JOY2_BTN) == HIGH ? 0 : MASK_JOY2_BTN); +#endif + return (joysval); +} + + +int emu_SwapJoysticks(int statusOnly) { + if (!statusOnly) { + if (joySwapped) { + joySwapped = false; + } + else { + joySwapped = true; + } + } + return(joySwapped?1:0); +} + +int emu_GetPad(void) +{ + return(keypadval|((joySwapped?1:0)<<7)); +} + +int emu_ReadKeys(void) +{ + uint16_t retval; + uint16_t j1 = readAnalogJoystick(); + uint16_t j2 = 0; + + // Second joystick +#ifdef PIN_JOY1_1 + if ( digitalRead(PIN_JOY1_1) == LOW ) j2 |= MASK_JOY2_UP; +#endif +#ifdef PIN_JOY1_2 + if ( digitalRead(PIN_JOY1_2) == LOW ) j2 |= MASK_JOY2_DOWN; +#endif +#ifdef PIN_JOY1_3 + if ( digitalRead(PIN_JOY1_3) == LOW ) j2 |= MASK_JOY2_RIGHT; +#endif +#ifdef PIN_JOY1_4 + if ( digitalRead(PIN_JOY1_4) == LOW ) j2 |= MASK_JOY2_LEFT; +#endif +#ifdef PIN_JOY1_BTN + if ( digitalRead(PIN_JOY1_BTN) == LOW ) j2 |= MASK_JOY2_BTN; +#endif + if (joySwapped) { + retval = ((j1 << 8) | j2); + } + else { + retval = ((j2 << 8) | j1); + } + +#ifdef PIN_KEY_USER1 + if ( digitalRead(PIN_KEY_USER1) == LOW ) retval |= MASK_KEY_USER1; +#endif +#ifdef PIN_KEY_USER2 + if ( digitalRead(PIN_KEY_USER2) == LOW ) retval |= MASK_KEY_USER2; +#endif +#ifdef PIN_KEY_USER3 + if ( digitalRead(PIN_KEY_USER3) == LOW ) retval |= MASK_KEY_USER3; +#endif +#ifdef PIN_KEY_USER4 + if ( digitalRead(PIN_KEY_USER4) == LOW ) retval |= MASK_KEY_USER4; +#endif + + //Serial.println(j1,HEX); + + return (retval); +} + +unsigned short emu_DebounceLocalKeys(void) +{ + uint16_t bCurState = emu_ReadKeys(); + uint16_t bClick = bCurState & ~bLastState; + bLastState = bCurState; + + return (bClick); +} + +int emu_ReadI2CKeyboard(void) { + int retval=0; +#ifdef HAS_I2CKBD + if (i2cKeyboardPresent) { + byte msg[7]={0,0,0,0,0,0,0}; + Wire.requestFrom(8, 7); // request 7 bytes from slave device #8 + int i = 0; + int hitindex=-1; + while (Wire.available() && (i<7) ) { // slave may send less than requested + byte b = Wire.read(); // receive a byte + if (b != 0xff) hitindex=i; + msg[i++] = b; + } + + if (hitindex >=0 ) { + /* + Serial.println(msg[0], BIN); + Serial.println(msg[1], BIN); + Serial.println(msg[2], BIN); + Serial.println(msg[3], BIN); + Serial.println(msg[4], BIN); + Serial.println(msg[5], BIN); + Serial.println(msg[6], BIN); + */ + unsigned short match = (~msg[hitindex])&0x00FF | (hitindex<<8); + //Serial.println(match,HEX); + for (i=0; i=1) && (c <= ACTION_MAXKBDVAL) ) { + + keypadval = c; + keyPressCount = 10; + delay(50); + vkeyRefresh = true; + exitVkbd = true; + } + else if (c == ACTION_EXITKBD) { + vkeyRefresh = true; + exitVkbd = true; + } + } + } + + if (vkeyRefresh) { + vkeyRefresh = false; + tft.drawSpriteNoDma(0,0,(uint16_t*)logo, rx, ry, rw, rh); + } + + if ( (exitVkbd) && (vkbActive) ) { + if (!vkbKeepOn) { + toggleVirtualkeyboard(false); + } + else { + toggleVirtualkeyboard(true); + } + } +} + +int emu_setKeymap(int index) { + if (index) { + } + else { + } +} + + + diff --git a/MCUME_teensy/teensysms/emuapi.h b/MCUME_teensy/teensysms/emuapi.h new file mode 100644 index 0000000..3539c8c --- /dev/null +++ b/MCUME_teensy/teensysms/emuapi.h @@ -0,0 +1,152 @@ +#ifndef EMUAPI_H +#define EMUAPI_H + +//#define INVX 1 +//#define INVY 1 +#define HAS_SND 1 +#define CUSTOM_SND 1 +//#define HAS_I2CKBD 1 +//#define TIMER_REND 1 + +#define EXTRA_HEAP 0x10 //0x9000 + +// Title: < > +#define TITLE " Master System Emulator " +#define ROMSDIR "/sms" + +#define emu_Init(ROM) {gen_Init(); gen_Start(ROM);} +#define emu_Step(x) {gen_Step();} +#define emu_Input(x) {gen_Input(x);} + +#define PALETTE_SIZE 32 +#define VID_FRAME_SKIP 0x0 +#define TFT_VBUFFER_YCROP 0 +#define SINGLELINE_RENDERING 1 + +#define R32(rgb) ((rgb>>16)&0xff) +#define G32(rgb) ((rgb>>8)&0xff) +#define B32(rgb) (rgb & 0xff) + +#define ACTION_NONE 0 +#define ACTION_MAXKBDVAL 16 +#define ACTION_EXITKBD 128 +#define ACTION_RUNTFT 129 +#define ACTION_RUNVGA 130 + +#ifdef KEYMAP_PRESENT + +#define TAREA_W_DEF 32 +#define TAREA_H_DEF 32 +#define TAREA_END 255 +#define TAREA_NEW_ROW 254 +#define TAREA_NEW_COL 253 +#define TAREA_XY 252 +#define TAREA_WH 251 + +#define KEYBOARD_X 16 +#define KEYBOARD_Y 32 +#define KEYBOARD_KEY_H 30 +#define KEYBOARD_KEY_W 28 +#define KEYBOARD_HIT_COLOR RGBVAL16(0xff,0x00,0x00) + +const unsigned short keysw[]= +{ TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + //TAREA_NEW_ROW,18,18,18,18,18,18,18,18,18,18, + TAREA_END}; + +const unsigned short keys[]={ + +59, 60, 61, 62, 63, 64, 65, 66, 67, 68, +109,110,111,112,106,107,108,17,18,19, +20,21,22,23,24,25,26,27,28,29, +30,31,32,33,34,35,36,37,38,57 }; + + + + +#ifdef HAS_I2CKBD +const unsigned short i2ckeys[] = { + 0X0080,0X0008,0X0180,0X0108,0X0280,0X0208,0X0380,0X0308,0X0480,0X0408, + 0X0040,0X0004,0X0140,0X0104,0X0240,0X0204,0X0340,0X0304,0X0440,0X0404, + 0X0020,0X0002,0X0120,0X0102,0X0220,0X0202,0X0320,0X0302,0X0420,0X0402, + 0X0010,0X0001,0X0110,0X0101,0X0210,0X0201,0X0310,0X0301,0X0410,0X0401 }; + //0X0580,0X0540,0X0520,0X0510,0X0508,0X0504,0X0502,0X0501,0X0680,0X0640 }; +#endif + +#endif + + + +#define MASK_JOY2_RIGHT 0x0001 +#define MASK_JOY2_LEFT 0x0002 +#define MASK_JOY2_UP 0x0004 +#define MASK_JOY2_DOWN 0x0008 +#define MASK_JOY2_BTN 0x0010 +#define MASK_KEY_USER1 0x0020 +#define MASK_KEY_USER2 0x0040 +#define MASK_KEY_USER3 0x0080 +#define MASK_JOY1_RIGHT 0x0100 +#define MASK_JOY1_LEFT 0x0200 +#define MASK_JOY1_UP 0x0400 +#define MASK_JOY1_DOWN 0x0800 +#define MASK_JOY1_BTN 0x1000 +#define MASK_KEY_USER4 0x2000 + + + +#ifdef __cplusplus +extern "C" { +#endif +extern void emu_init(void); +extern void emu_printf(char * text); +extern void emu_printi(int val); +extern void emu_printh(int val); +extern void * emu_Malloc(int size); +extern void emu_Free(void * pt); + + +extern int emu_FileOpen(char * filename); +extern int emu_FileRead(char * buf, int size); +extern unsigned char emu_FileGetc(void); +extern int emu_FileTell(void); +extern int emu_FileSeek(int seek); +extern void emu_FileClose(void); +extern int emu_FileSize(char * filename); +extern int emu_LoadFile(char * filename, char * buf, int size); +extern int emu_LoadFileSeek(char * filename, char * buf, int size, int seek); +extern void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index); +extern void emu_DrawScreen(unsigned char * VBuf, int width, int height, int stride); +extern void emu_DrawLine(unsigned char * VBuf, int width, int height, int line); +extern void emu_DrawLine16(unsigned short * VBuf, int width, int height, int line); +extern void emu_DrawVsync(void); +extern int emu_FrameSkip(void); +extern void * emu_LineBuffer(int line); + +extern void emu_InitJoysticks(void); +extern int emu_SwapJoysticks(int statusOnly); +extern unsigned short emu_DebounceLocalKeys(void); +extern int emu_ReadKeys(void); +extern int emu_GetPad(void); +extern int emu_ReadAnalogJoyX(int min, int max); +extern int emu_ReadAnalogJoyY(int min, int max); +extern int emu_ReadI2CKeyboard(void); +extern void emu_sndPlaySound(int chan, int volume, int freq); +extern void emu_sndPlayBuzz(int size, int val); +extern void emu_sndInit(); +extern void emu_resetus(void); +extern int emu_us(void); + +extern int emu_setKeymap(int index); + +#ifdef __cplusplus +} +#endif + +#endif + + + + diff --git a/MCUME_teensy/teensysms/fmopl.c b/MCUME_teensy/teensysms/fmopl.c new file mode 100644 index 0000000..72872a7 --- /dev/null +++ b/MCUME_teensy/teensysms/fmopl.c @@ -0,0 +1,1319 @@ +/* +** +** File: fmopl.c -- software implementation of FM sound generator +** +** Copyright (C) 1999 Tatsuyuki Satoh , MultiArcadeMachineEmurator development +** +** Version 0.36f +** +*/ + +#define BUILD_YM3812 1 + +/* + preliminary : + Problem : + note: +*/ + +#include "shared.h" + +#ifndef PI +#define PI 3.14159265358979323846 +#endif + +/* -------------------- preliminary define section --------------------- */ +/* attack/decay rate time rate */ +#define OPL_ARRATE 141280 /* RATE 4 = 2826.24ms @ 3.6MHz */ +#define OPL_DRRATE 1956000 /* RATE 4 = 39280.64ms @ 3.6MHz */ + +#define DELTAT_MIXING_LEVEL (1) /* DELTA-T ADPCM MIXING LEVEL */ + +#define FREQ_BITS 24 /* frequency turn */ + +/* counter bits = 20 , octerve 7 */ +#define FREQ_RATE (1<<(FREQ_BITS-20)) +#define TL_BITS (FREQ_BITS+2) + +/* final output shift , limit minimum and maximum */ +#define OPL_OUTSB (TL_BITS+3-16) /* OPL output final shift 16bit */ +#define OPL_MAXOUT (0x7fff< max ) + val = max; + else if ( val < min ) + val = min; + + return val; +} + +/* status set and IRQ handling */ +static __inline__ void OPL_STATUS_SET(FM_OPL *OPL,int flag) +{ + /* set status flag */ + OPL->status |= flag; + if(!(OPL->status & 0x80)) + { + if(OPL->status & OPL->statusmask) + { /* IRQ on */ + OPL->status |= 0x80; + /* callback user interrupt handler (IRQ is OFF to ON) */ + if(OPL->IRQHandler) (OPL->IRQHandler)(OPL->IRQParam,1); + } + } +} + +/* status reset and IRQ handling */ +static __inline__ void OPL_STATUS_RESET(FM_OPL *OPL,int flag) +{ + /* reset status flag */ + OPL->status &=~flag; + if((OPL->status & 0x80)) + { + if (!(OPL->status & OPL->statusmask) ) + { + OPL->status &= 0x7f; + /* callback user interrupt handler (IRQ is ON to OFF) */ + if(OPL->IRQHandler) (OPL->IRQHandler)(OPL->IRQParam,0); + } + } +} + +/* IRQ mask set */ +static __inline__ void OPL_STATUSMASK_SET(FM_OPL *OPL,int flag) +{ + OPL->statusmask = flag; + /* IRQ handling check */ + OPL_STATUS_SET(OPL,0); + OPL_STATUS_RESET(OPL,0); +} + +/* ----- key on ----- */ +static __inline__ void OPL_KEYON(OPL_SLOT *SLOT) +{ + /* sin wave restart */ + SLOT->Cnt = 0; + /* set attack */ + SLOT->evm = ENV_MOD_AR; + SLOT->evs = SLOT->evsa; + SLOT->evc = EG_AST; + SLOT->eve = EG_AED; +} +/* ----- key off ----- */ +static __inline__ void OPL_KEYOFF(OPL_SLOT *SLOT) +{ + if( SLOT->evm > ENV_MOD_RR) + { + /* set envelope counter from envleope output */ + SLOT->evm = ENV_MOD_RR; + if( !(SLOT->evc&EG_DST) ) + /*SLOT->evc = (ENV_CURVE[SLOT->evc>>ENV_BITS]<evc = EG_DST; + SLOT->eve = EG_DED; + SLOT->evs = SLOT->evsr; + } +} + +/* ---------- calcrate Envelope Generator & Phase Generator ---------- */ +/* return : envelope output */ +static __inline__ UINT32 OPL_CALC_SLOT( OPL_SLOT *SLOT ) +{ + /* calcrate envelope generator */ + if( (SLOT->evc+=SLOT->evs) >= SLOT->eve ) + { + switch( SLOT->evm ){ + case ENV_MOD_AR: /* ATTACK -> DECAY1 */ + /* next DR */ + SLOT->evm = ENV_MOD_DR; + SLOT->evc = EG_DST; + SLOT->eve = SLOT->SL; + SLOT->evs = SLOT->evsd; + break; + case ENV_MOD_DR: /* DECAY -> SL or RR */ + SLOT->evc = SLOT->SL; + SLOT->eve = EG_DED; + if(SLOT->eg_typ) + { + SLOT->evs = 0; + } + else + { + SLOT->evm = ENV_MOD_RR; + SLOT->evs = SLOT->evsr; + } + break; + case ENV_MOD_RR: /* RR -> OFF */ + SLOT->evc = EG_OFF; + SLOT->eve = EG_OFF+1; + SLOT->evs = 0; + break; + } + } + /* calcrate envelope */ + return SLOT->TLL+ENV_CURVE[SLOT->evc>>ENV_BITS]+(SLOT->ams ? ams : 0); +} + +/* set algorythm connection */ +static void set_algorythm( OPL_CH *CH) +{ + INT32 *carrier = &outd[0]; + CH->connect1 = CH->CON ? carrier : &feedback2; + CH->connect2 = carrier; +} + +/* ---------- frequency counter for operater update ---------- */ +static __inline__ void CALC_FCSLOT(OPL_CH *CH,OPL_SLOT *SLOT) +{ + int ksr; + + /* frequency step counter */ + SLOT->Incr = CH->fc * SLOT->mul; + ksr = CH->kcode >> SLOT->KSR; + + if( SLOT->ksr != ksr ) + { + SLOT->ksr = ksr; + /* attack , decay rate recalcration */ + SLOT->evsa = SLOT->AR[ksr]; + SLOT->evsd = SLOT->DR[ksr]; + SLOT->evsr = SLOT->RR[ksr]; + } + SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl); +} + +/* set multi,am,vib,EG-TYP,KSR,mul */ +static __inline__ void set_mul(FM_OPL *OPL,int slot,int v) +{ + OPL_CH *CH = &OPL->P_CH[slot/2]; + OPL_SLOT *SLOT = &CH->SLOT[slot&1]; + + SLOT->mul = MUL_TABLE[v&0x0f]; + SLOT->KSR = (v&0x10) ? 0 : 2; + SLOT->eg_typ = (v&0x20)>>5; + SLOT->vib = (v&0x40); + SLOT->ams = (v&0x80); + CALC_FCSLOT(CH,SLOT); +} + +/* set ksl & tl */ +static __inline__ void set_ksl_tl(FM_OPL *OPL,int slot,int v) +{ + OPL_CH *CH = &OPL->P_CH[slot/2]; + OPL_SLOT *SLOT = &CH->SLOT[slot&1]; + int ksl = v>>6; /* 0 / 1.5 / 3 / 6 db/OCT */ + + SLOT->ksl = ksl ? 3-ksl : 31; + SLOT->TL = (v&0x3f)*(0.75/EG_STEP); /* 0.75db step */ + + if( !(OPL->mode&0x80) ) + { /* not CSM latch total level */ + SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl); + } +} + +/* set attack rate & decay rate */ +static __inline__ void set_ar_dr(FM_OPL *OPL,int slot,int v) +{ + OPL_CH *CH = &OPL->P_CH[slot/2]; + OPL_SLOT *SLOT = &CH->SLOT[slot&1]; + int ar = v>>4; + int dr = v&0x0f; + + SLOT->AR = ar ? &OPL->AR_TABLE[ar<<2] : RATE_0; + SLOT->evsa = SLOT->AR[SLOT->ksr]; + if( SLOT->evm == ENV_MOD_AR ) SLOT->evs = SLOT->evsa; + + SLOT->DR = dr ? &OPL->DR_TABLE[dr<<2] : RATE_0; + SLOT->evsd = SLOT->DR[SLOT->ksr]; + if( SLOT->evm == ENV_MOD_DR ) SLOT->evs = SLOT->evsd; +} + +/* set sustain level & release rate */ +static __inline__ void set_sl_rr(FM_OPL *OPL,int slot,int v) +{ + OPL_CH *CH = &OPL->P_CH[slot/2]; + OPL_SLOT *SLOT = &CH->SLOT[slot&1]; + int sl = v>>4; + int rr = v & 0x0f; + + SLOT->SL = SL_TABLE[sl]; + if( SLOT->evm == ENV_MOD_DR ) SLOT->eve = SLOT->SL; + SLOT->RR = &OPL->DR_TABLE[rr<<2]; + SLOT->evsr = SLOT->RR[SLOT->ksr]; + if( SLOT->evm == ENV_MOD_RR ) SLOT->evs = SLOT->evsr; +} + +/* operator output calcrator */ +#define OP_OUT(slot,env,con) slot->wavetable[((slot->Cnt+con)/(0x1000000/SIN_ENT))&(SIN_ENT-1)][env] +/* ---------- calcrate one of channel ---------- */ +static __inline__ void OPL_CALC_CH( OPL_CH *CH ) +{ + UINT32 env_out; + OPL_SLOT *SLOT; + + feedback2 = 0; + /* SLOT 1 */ + SLOT = &CH->SLOT[SLOT1]; + env_out=OPL_CALC_SLOT(SLOT); + if( env_out < EG_ENT-1 ) + { + /* PG */ + if(SLOT->vib) SLOT->Cnt += (SLOT->Incr*vib/VIB_RATE); + else SLOT->Cnt += SLOT->Incr; + /* connectoion */ + if(CH->FB) + { + int feedback1 = (CH->op1_out[0]+CH->op1_out[1])>>CH->FB; + CH->op1_out[1] = CH->op1_out[0]; + *CH->connect1 += CH->op1_out[0] = OP_OUT(SLOT,env_out,feedback1); + } + else + { + *CH->connect1 += OP_OUT(SLOT,env_out,0); + } + }else + { + CH->op1_out[1] = CH->op1_out[0]; + CH->op1_out[0] = 0; + } + /* SLOT 2 */ + SLOT = &CH->SLOT[SLOT2]; + env_out=OPL_CALC_SLOT(SLOT); + if( env_out < EG_ENT-1 ) + { + /* PG */ + if(SLOT->vib) SLOT->Cnt += (SLOT->Incr*vib/VIB_RATE); + else SLOT->Cnt += SLOT->Incr; + /* connectoion */ + outd[0] += OP_OUT(SLOT,env_out, feedback2); + } +} + +/* ---------- calcrate rythm block ---------- */ +#define WHITE_NOISE_db 6.0 +static __inline__ void OPL_CALC_RH( OPL_CH *CH ) +{ + UINT32 env_tam,env_sd,env_top,env_hh; + int whitenoise = (rand()&1)*(WHITE_NOISE_db/EG_STEP); + INT32 tone8; + + OPL_SLOT *SLOT; + int env_out; + + /* BD : same as FM serial mode and output level is large */ + feedback2 = 0; + /* SLOT 1 */ + SLOT = &CH[6].SLOT[SLOT1]; + env_out=OPL_CALC_SLOT(SLOT); + if( env_out < EG_ENT-1 ) + { + /* PG */ + if(SLOT->vib) SLOT->Cnt += (SLOT->Incr*vib/VIB_RATE); + else SLOT->Cnt += SLOT->Incr; + /* connectoion */ + if(CH[6].FB) + { + int feedback1 = (CH[6].op1_out[0]+CH[6].op1_out[1])>>CH[6].FB; + CH[6].op1_out[1] = CH[6].op1_out[0]; + feedback2 = CH[6].op1_out[0] = OP_OUT(SLOT,env_out,feedback1); + } + else + { + feedback2 = OP_OUT(SLOT,env_out,0); + } + }else + { + feedback2 = 0; + CH[6].op1_out[1] = CH[6].op1_out[0]; + CH[6].op1_out[0] = 0; + } + /* SLOT 2 */ + SLOT = &CH[6].SLOT[SLOT2]; + env_out=OPL_CALC_SLOT(SLOT); + if( env_out < EG_ENT-1 ) + { + /* PG */ + if(SLOT->vib) SLOT->Cnt += (SLOT->Incr*vib/VIB_RATE); + else SLOT->Cnt += SLOT->Incr; + /* connectoion */ + outd[0] += OP_OUT(SLOT,env_out, feedback2)*2; + } + /* + SD (17) = mul14[fnum7] + white noise + TAM (15) = mul15[fnum8] + TOP (18) = fnum6(mul18[fnum8]+whitenoise) + HH (14) = fnum7(mul18[fnum8]+whitenoise) + white noise + */ + env_sd =OPL_CALC_SLOT(SLOT7_2) + whitenoise; + env_tam=OPL_CALC_SLOT(SLOT8_1); + env_top=OPL_CALC_SLOT(SLOT8_2); + env_hh =OPL_CALC_SLOT(SLOT7_1) + whitenoise; + + /* PG */ + if(SLOT7_1->vib) SLOT7_1->Cnt += (2*SLOT7_1->Incr*vib/VIB_RATE); + else SLOT7_1->Cnt += 2*SLOT7_1->Incr; + if(SLOT7_2->vib) SLOT7_2->Cnt += ((CH[7].fc*8)*vib/VIB_RATE); + else SLOT7_2->Cnt += (CH[7].fc*8); + if(SLOT8_1->vib) SLOT8_1->Cnt += (SLOT8_1->Incr*vib/VIB_RATE); + else SLOT8_1->Cnt += SLOT8_1->Incr; + if(SLOT8_2->vib) SLOT8_2->Cnt += ((CH[8].fc*48)*vib/VIB_RATE); + else SLOT8_2->Cnt += (CH[8].fc*48); + + tone8 = OP_OUT(SLOT8_2,whitenoise,0 ); + + /* SD */ + if( env_sd < EG_ENT-1 ) + outd[0] += OP_OUT(SLOT7_1,env_sd, 0)*8; + /* TAM */ + if( env_tam < EG_ENT-1 ) + outd[0] += OP_OUT(SLOT8_1,env_tam, 0)*2; + /* TOP-CY */ + if( env_top < EG_ENT-1 ) + outd[0] += OP_OUT(SLOT7_2,env_top,tone8)*2; + /* HH */ + if( env_hh < EG_ENT-1 ) + outd[0] += OP_OUT(SLOT7_2,env_hh,tone8)*2; +} + +/* ----------- initialize time tabls ----------- */ +static void init_timetables( FM_OPL *OPL , int ARRATE , int DRRATE ) +{ + int i; + double rate; + + /* make attack rate & decay rate tables */ + for (i = 0;i < 4;i++) OPL->AR_TABLE[i] = OPL->DR_TABLE[i] = 0; + for (i = 4;i <= 60;i++){ + rate = OPL->freqbase; /* frequency rate */ + if( i < 60 ) rate *= 1.0+(i&3)*0.25; /* b0-1 : x1 , x1.25 , x1.5 , x1.75 */ + rate *= 1<<((i>>2)-1); /* b2-5 : shift bit */ + rate *= (double)(EG_ENT<AR_TABLE[i] = rate / ARRATE; + OPL->DR_TABLE[i] = rate / DRRATE; + } + for (i = 60;i < 76;i++) + { + OPL->AR_TABLE[i] = EG_AED-1; + OPL->DR_TABLE[i] = OPL->DR_TABLE[60]; + } +#if 0 + for (i = 0;i < 64 ;i++){ /* make for overflow area */ + Log(LOG_WAR,"rate %2d , ar %f ms , dr %f ms \n",i, + ((double)(EG_ENT<AR_TABLE[i]) * (1000.0 / OPL->rate), + ((double)(EG_ENT<DR_TABLE[i]) * (1000.0 / OPL->rate) ); + } +#endif +} + +/* ---------- generic table initialize ---------- */ +static int OPLOpenTable( void ) +{ + int s,t; + double rate; + int i,j; + double pom; + + /* allocate dynamic tables */ + if( (TL_TABLE = emu_Malloc(TL_MAX*2*sizeof(INT32))) == NULL) + return 0; + if( (SIN_TABLE = emu_Malloc(SIN_ENT*4 *sizeof(INT32 *))) == NULL) + { + emu_Free(TL_TABLE); + return 0; + } + if( (AMS_TABLE = emu_Malloc(AMS_ENT*2 *sizeof(INT32))) == NULL) + { + emu_Free(TL_TABLE); + emu_Free(SIN_TABLE); + return 0; + } + if( (VIB_TABLE = emu_Malloc(VIB_ENT*2 *sizeof(INT32))) == NULL) + { + emu_Free(TL_TABLE); + emu_Free(SIN_TABLE); + emu_Free(AMS_TABLE); + return 0; + } + + /* make total level table */ + for (t = 0;t < EG_ENT-1 ;t++){ + rate = ((1< voltage */ + TL_TABLE[ t] = (int)rate; + TL_TABLE[TL_MAX+t] = -TL_TABLE[t]; +/* Log(LOG_INF,"TotalLevel(%3d) = %x\n",t,TL_TABLE[t]);*/ + } + /* fill volume off area */ + for ( t = EG_ENT-1; t < TL_MAX ;t++){ + TL_TABLE[t] = TL_TABLE[TL_MAX+t] = 0; + } + + /* make sinwave table (total level offet) */ + /* degree 0 = degree 180 = off */ + SIN_TABLE[0] = SIN_TABLE[SIN_ENT/2] = &TL_TABLE[EG_ENT-1]; + for (s = 1;s <= SIN_ENT/4;s++){ + pom = sin(2*PI*s/SIN_ENT); /* sin */ + pom = 20*log10(1/pom); /* decibel */ + j = pom / EG_STEP; /* TL_TABLE steps */ + + /* degree 0 - 90 , degree 180 - 90 : plus section */ + SIN_TABLE[ s] = SIN_TABLE[SIN_ENT/2-s] = &TL_TABLE[j]; + /* degree 180 - 270 , degree 360 - 270 : minus section */ + SIN_TABLE[SIN_ENT/2+s] = SIN_TABLE[SIN_ENT -s] = &TL_TABLE[TL_MAX+j]; +/* Log(LOG_INF,"sin(%3d) = %f:%f db\n",s,pom,(double)j * EG_STEP);*/ + } + for (s = 0;s < SIN_ENT;s++) + { + SIN_TABLE[SIN_ENT*1+s] = s<(SIN_ENT/2) ? SIN_TABLE[s] : &TL_TABLE[EG_ENT]; + SIN_TABLE[SIN_ENT*2+s] = SIN_TABLE[s % (SIN_ENT/2)]; + SIN_TABLE[SIN_ENT*3+s] = (s/(SIN_ENT/4))&1 ? &TL_TABLE[EG_ENT] : SIN_TABLE[SIN_ENT*2+s]; + } + + /* envelope counter -> envelope output table */ + for (i=0; i= EG_ENT ) pom = EG_ENT-1; */ + ENV_CURVE[i] = (int)pom; + /* DECAY ,RELEASE curve */ + ENV_CURVE[(EG_DST>>ENV_BITS)+i]= i; + } + /* off */ + ENV_CURVE[EG_OFF>>ENV_BITS]= EG_ENT-1; + /* make LFO ams table */ + for (i=0; iSLOT[SLOT1]; + OPL_SLOT *slot2 = &CH->SLOT[SLOT2]; + /* all key off */ + OPL_KEYOFF(slot1); + OPL_KEYOFF(slot2); + /* total level latch */ + slot1->TLL = slot1->TL + (CH->ksl_base>>slot1->ksl); + slot1->TLL = slot1->TL + (CH->ksl_base>>slot1->ksl); + /* key on */ + CH->op1_out[0] = CH->op1_out[1] = 0; + OPL_KEYON(slot1); + OPL_KEYON(slot2); +} + +/* ---------- opl initialize ---------- */ +static void OPL_initalize(FM_OPL *OPL) +{ + int fn; + + /* frequency base */ + OPL->freqbase = (OPL->rate) ? ((double)OPL->clock / OPL->rate) / 72 : 0; + /* Timer base time */ + OPL->TimerBase = 1.0/((double)OPL->clock / 72.0 ); + /* make time tables */ + init_timetables( OPL , OPL_ARRATE , OPL_DRRATE ); + /* make fnumber -> increment counter table */ + for( fn=0 ; fn < 1024 ; fn++ ) + { + OPL->FN_TABLE[fn] = OPL->freqbase * fn * FREQ_RATE * (1<<7) / 2; + } + /* LFO freq.table */ + OPL->amsIncr = OPL->rate ? (double)AMS_ENT*(1<rate * 3.7 * ((double)OPL->clock/3600000) : 0; + OPL->vibIncr = OPL->rate ? (double)VIB_ENT*(1<rate * 6.4 * ((double)OPL->clock/3600000) : 0; +} + +/* ---------- write a OPL registers ---------- */ +void OPLWriteReg(FM_OPL *OPL, int r, int v) +{ + OPL_CH *CH; + int slot; + int block_fnum; + + switch(r&0xe0) + { + case 0x00: /* 00-1f:controll */ + switch(r&0x1f) + { + case 0x01: + /* wave selector enable */ + if(OPL->type&OPL_TYPE_WAVESEL) + { + OPL->wavesel = v&0x20; + if(!OPL->wavesel) + { + /* preset compatible mode */ + int c; + for(c=0;cmax_ch;c++) + { + OPL->P_CH[c].SLOT[SLOT1].wavetable = &SIN_TABLE[0]; + OPL->P_CH[c].SLOT[SLOT2].wavetable = &SIN_TABLE[0]; + } + } + } + return; + case 0x02: /* Timer 1 */ + OPL->T[0] = (256-v)*4; + break; + case 0x03: /* Timer 2 */ + OPL->T[1] = (256-v)*16; + return; + case 0x04: /* IRQ clear / mask and Timer enable */ + if(v&0x80) + { /* IRQ flag clear */ + OPL_STATUS_RESET(OPL,0x7f); + } + else + { /* set IRQ mask ,timer enable*/ + UINT8 st1 = v&1; + UINT8 st2 = (v>>1)&1; + /* IRQRST,T1MSK,t2MSK,EOSMSK,BRMSK,x,ST2,ST1 */ + OPL_STATUS_RESET(OPL,v&0x78); + OPL_STATUSMASK_SET(OPL,((~v)&0x78)|0x01); + /* timer 2 */ + if(OPL->st[1] != st2) + { + double interval = st2 ? (double)OPL->T[1]*OPL->TimerBase : 0.0; + OPL->st[1] = st2; + if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+1,interval); + } + /* timer 1 */ + if(OPL->st[0] != st1) + { + double interval = st1 ? (double)OPL->T[0]*OPL->TimerBase : 0.0; + OPL->st[0] = st1; + if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+0,interval); + } + } + return; +#if BUILD_Y8950 + case 0x06: /* Key Board OUT */ + if(OPL->type&OPL_TYPE_KEYBOARD) + { + if(OPL->keyboardhandler_w) + OPL->keyboardhandler_w(OPL->keyboard_param,v); + else + Log(LOG_WAR,"OPL:write unmapped KEYBOARD port\n"); + } + return; + case 0x07: /* DELTA-T controll : START,REC,MEMDATA,REPT,SPOFF,x,x,RST */ + if(OPL->type&OPL_TYPE_ADPCM) + YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v); + return; + case 0x08: /* MODE,DELTA-T : CSM,NOTESEL,x,x,smpl,da/ad,64k,rom */ + OPL->mode = v; + v&=0x1f; /* for DELTA-T unit */ + case 0x09: /* START ADD */ + case 0x0a: + case 0x0b: /* STOP ADD */ + case 0x0c: + case 0x0d: /* PRESCALE */ + case 0x0e: + case 0x0f: /* ADPCM data */ + case 0x10: /* DELTA-N */ + case 0x11: /* DELTA-N */ + case 0x12: /* EG-CTRL */ + if(OPL->type&OPL_TYPE_ADPCM) + YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v); + return; +#if 0 + case 0x15: /* DAC data */ + case 0x16: + case 0x17: /* SHIFT */ + return; + case 0x18: /* I/O CTRL (Direction) */ + if(OPL->type&OPL_TYPE_IO) + OPL->portDirection = v&0x0f; + return; + case 0x19: /* I/O DATA */ + if(OPL->type&OPL_TYPE_IO) + { + OPL->portLatch = v; + if(OPL->porthandler_w) + OPL->porthandler_w(OPL->port_param,v&OPL->portDirection); + } + return; + case 0x1a: /* PCM data */ + return; +#endif +#endif + } + break; + case 0x20: /* am,vib,ksr,eg type,mul */ + slot = slot_array[r&0x1f]; + if(slot == -1) return; + set_mul(OPL,slot,v); + return; + case 0x40: + slot = slot_array[r&0x1f]; + if(slot == -1) return; + set_ksl_tl(OPL,slot,v); + return; + case 0x60: + slot = slot_array[r&0x1f]; + if(slot == -1) return; + set_ar_dr(OPL,slot,v); + return; + case 0x80: + slot = slot_array[r&0x1f]; + if(slot == -1) return; + set_sl_rr(OPL,slot,v); + return; + case 0xa0: + switch(r) + { + case 0xbd: + /* amsep,vibdep,r,bd,sd,tom,tc,hh */ + { + UINT8 rkey = OPL->rythm^v; + OPL->ams_table = &AMS_TABLE[v&0x80 ? AMS_ENT : 0]; + OPL->vib_table = &VIB_TABLE[v&0x40 ? VIB_ENT : 0]; + OPL->rythm = v&0x3f; + if(OPL->rythm&0x20) + { +#if 0 + usrintf_showmessage("OPL Rythm mode select"); +#endif + /* BD key on/off */ + if(rkey&0x10) + { + if(v&0x10) + { + OPL->P_CH[6].op1_out[0] = OPL->P_CH[6].op1_out[1] = 0; + OPL_KEYON(&OPL->P_CH[6].SLOT[SLOT1]); + OPL_KEYON(&OPL->P_CH[6].SLOT[SLOT2]); + } + else + { + OPL_KEYOFF(&OPL->P_CH[6].SLOT[SLOT1]); + OPL_KEYOFF(&OPL->P_CH[6].SLOT[SLOT2]); + } + } + /* SD key on/off */ + if(rkey&0x08) + { + if(v&0x08) OPL_KEYON(&OPL->P_CH[7].SLOT[SLOT2]); + else OPL_KEYOFF(&OPL->P_CH[7].SLOT[SLOT2]); + }/* TAM key on/off */ + if(rkey&0x04) + { + if(v&0x04) OPL_KEYON(&OPL->P_CH[8].SLOT[SLOT1]); + else OPL_KEYOFF(&OPL->P_CH[8].SLOT[SLOT1]); + } + /* TOP-CY key on/off */ + if(rkey&0x02) + { + if(v&0x02) OPL_KEYON(&OPL->P_CH[8].SLOT[SLOT2]); + else OPL_KEYOFF(&OPL->P_CH[8].SLOT[SLOT2]); + } + /* HH key on/off */ + if(rkey&0x01) + { + if(v&0x01) OPL_KEYON(&OPL->P_CH[7].SLOT[SLOT1]); + else OPL_KEYOFF(&OPL->P_CH[7].SLOT[SLOT1]); + } + } + } + return; + } + /* keyon,block,fnum */ + if( (r&0x0f) > 8) return; + CH = &OPL->P_CH[r&0x0f]; + if(!(r&0x10)) + { /* a0-a8 */ + block_fnum = (CH->block_fnum&0x1f00) | v; + } + else + { /* b0-b8 */ + int keyon = (v>>5)&1; + block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff); + if(CH->keyon != keyon) + { + if( (CH->keyon=keyon) ) + { + CH->op1_out[0] = CH->op1_out[1] = 0; + OPL_KEYON(&CH->SLOT[SLOT1]); + OPL_KEYON(&CH->SLOT[SLOT2]); + } + else + { + OPL_KEYOFF(&CH->SLOT[SLOT1]); + OPL_KEYOFF(&CH->SLOT[SLOT2]); + } + } + } + /* update */ + if(CH->block_fnum != block_fnum) + { + int blockRv = 7-(block_fnum>>10); + int fnum = block_fnum&0x3ff; + CH->block_fnum = block_fnum; + + CH->ksl_base = KSL_TABLE[block_fnum>>6]; + CH->fc = OPL->FN_TABLE[fnum]>>blockRv; + CH->kcode = CH->block_fnum>>9; + if( (OPL->mode&0x40) && CH->block_fnum&0x100) CH->kcode |=1; + CALC_FCSLOT(CH,&CH->SLOT[SLOT1]); + CALC_FCSLOT(CH,&CH->SLOT[SLOT2]); + } + return; + case 0xc0: + /* FB,C */ + if( (r&0x0f) > 8) return; + CH = &OPL->P_CH[r&0x0f]; + { + int feedback = (v>>1)&7; + CH->FB = feedback ? (8+1) - feedback : 0; + CH->CON = v&1; + set_algorythm(CH); + } + return; + case 0xe0: /* wave type */ + slot = slot_array[r&0x1f]; + if(slot == -1) return; + CH = &OPL->P_CH[slot/2]; + if(OPL->wavesel) + { + /* Log(LOG_INF,"OPL SLOT %d wave select %d\n",slot,v&3); */ + CH->SLOT[slot&1].wavetable = &SIN_TABLE[(v&0x03)*SIN_ENT]; + } + return; + } +} + +/* lock/unlock for common table */ +static int OPL_LockTable(void) +{ + num_lock++; + if(num_lock>1) return 0; + /* first time */ + cur_chip = NULL; + /* allocate total level table (128kb space) */ + if( !OPLOpenTable() ) + { + num_lock--; + return -1; + } + return 0; +} + +static void OPL_UnLockTable(void) +{ + if(num_lock) num_lock--; + if(num_lock) return; + /* last time */ + cur_chip = NULL; + OPLCloseTable(); +} + +#if (BUILD_YM3812 || BUILD_YM3526) +/*******************************************************************************/ +/* YM3812 local section */ +/*******************************************************************************/ + +/* ---------- update one of chip ----------- */ +void YM3812UpdateOne(FM_OPL *OPL, INT16 *buffer, int length) +{ + int i; + int data; + FMSAMPLE *buf = buffer; + UINT32 amsCnt = OPL->amsCnt; + UINT32 vibCnt = OPL->vibCnt; + UINT8 rythm = OPL->rythm&0x20; + OPL_CH *CH,*R_CH; + + if( (void *)OPL != cur_chip ){ + cur_chip = (void *)OPL; + /* channel pointers */ + S_CH = OPL->P_CH; + E_CH = &S_CH[9]; + /* rythm slot */ + SLOT7_1 = &S_CH[7].SLOT[SLOT1]; + SLOT7_2 = &S_CH[7].SLOT[SLOT2]; + SLOT8_1 = &S_CH[8].SLOT[SLOT1]; + SLOT8_2 = &S_CH[8].SLOT[SLOT2]; + /* LFO state */ + amsIncr = OPL->amsIncr; + vibIncr = OPL->vibIncr; + ams_table = OPL->ams_table; + vib_table = OPL->vib_table; + } + R_CH = rythm ? &S_CH[6] : E_CH; + for( i=0; i < length ; i++ ) + { + /* channel A channel B channel C */ + /* LFO */ + ams = ams_table[(amsCnt+=amsIncr)>>AMS_SHIFT]; + vib = vib_table[(vibCnt+=vibIncr)>>VIB_SHIFT]; + outd[0] = 0; + /* FM part */ + for(CH=S_CH ; CH < R_CH ; CH++) + OPL_CALC_CH(CH); + /* Rythn part */ + if(rythm) + OPL_CALC_RH(S_CH); + /* limit check */ + data = Limit( outd[0] , OPL_MAXOUT, OPL_MINOUT ); + /* store to sound buffer */ + buf[i] = data >> OPL_OUTSB; + } + + OPL->amsCnt = amsCnt; + OPL->vibCnt = vibCnt; +} +#endif /* (BUILD_YM3812 || BUILD_YM3526) */ + +#if BUILD_Y8950 + +void Y8950UpdateOne(FM_OPL *OPL, INT16 *buffer, int length) +{ + int i; + int data; + FMSAMPLE *buf = buffer; + UINT32 amsCnt = OPL->amsCnt; + UINT32 vibCnt = OPL->vibCnt; + UINT8 rythm = OPL->rythm&0x20; + OPL_CH *CH,*R_CH; + YM_DELTAT *DELTAT = OPL->deltat; + + /* setup DELTA-T unit */ + YM_DELTAT_DECODE_PRESET(DELTAT); + + if( (void *)OPL != cur_chip ){ + cur_chip = (void *)OPL; + /* channel pointers */ + S_CH = OPL->P_CH; + E_CH = &S_CH[9]; + /* rythm slot */ + SLOT7_1 = &S_CH[7].SLOT[SLOT1]; + SLOT7_2 = &S_CH[7].SLOT[SLOT2]; + SLOT8_1 = &S_CH[8].SLOT[SLOT1]; + SLOT8_2 = &S_CH[8].SLOT[SLOT2]; + /* LFO state */ + amsIncr = OPL->amsIncr; + vibIncr = OPL->vibIncr; + ams_table = OPL->ams_table; + vib_table = OPL->vib_table; + } + R_CH = rythm ? &S_CH[6] : E_CH; + for( i=0; i < length ; i++ ) + { + /* channel A channel B channel C */ + /* LFO */ + ams = ams_table[(amsCnt+=amsIncr)>>AMS_SHIFT]; + vib = vib_table[(vibCnt+=vibIncr)>>VIB_SHIFT]; + outd[0] = 0; + /* deltaT ADPCM */ + if( DELTAT->flag ) + YM_DELTAT_ADPCM_CALC(DELTAT); + /* FM part */ + for(CH=S_CH ; CH < R_CH ; CH++) + OPL_CALC_CH(CH); + /* Rythn part */ + if(rythm) + OPL_CALC_RH(S_CH); + /* limit check */ + data = Limit( outd[0] , OPL_MAXOUT, OPL_MINOUT ); + /* store to sound buffer */ + buf[i] = data >> OPL_OUTSB; + } + OPL->amsCnt = amsCnt; + OPL->vibCnt = vibCnt; + /* deltaT START flag */ + if( !DELTAT->flag ) + OPL->status &= 0xfe; +} +#endif + +/* ---------- reset one of chip ---------- */ +void OPLResetChip(FM_OPL *OPL) +{ + int c,s; + int i; + + /* reset chip */ + OPL->mode = 0; /* normal mode */ + OPL_STATUS_RESET(OPL,0x7f); + /* reset with register write */ + OPLWriteReg(OPL,0x01,0); /* wabesel disable */ + OPLWriteReg(OPL,0x02,0); /* Timer1 */ + OPLWriteReg(OPL,0x03,0); /* Timer2 */ + OPLWriteReg(OPL,0x04,0); /* IRQ mask clear */ + for(i = 0xff ; i >= 0x20 ; i-- ) OPLWriteReg(OPL,i,0); + /* reset OPerator paramater */ + for( c = 0 ; c < OPL->max_ch ; c++ ) + { + OPL_CH *CH = &OPL->P_CH[c]; + /* OPL->P_CH[c].PAN = OPN_CENTER; */ + for(s = 0 ; s < 2 ; s++ ) + { + /* wave table */ + CH->SLOT[s].wavetable = &SIN_TABLE[0]; + /* CH->SLOT[s].evm = ENV_MOD_RR; */ + CH->SLOT[s].evc = EG_OFF; + CH->SLOT[s].eve = EG_OFF+1; + CH->SLOT[s].evs = 0; + } + } +#if BUILD_Y8950 + if(OPL->type&OPL_TYPE_ADPCM) + { + YM_DELTAT *DELTAT = OPL->deltat; + + DELTAT->freqbase = OPL->freqbase; + DELTAT->output_pointer = outd; + DELTAT->portshift = 5; + DELTAT->output_range = DELTAT_MIXING_LEVEL<P_CH = (OPL_CH *)ptr; ptr+=sizeof(OPL_CH)*max_ch; +#if BUILD_Y8950 + if(type&OPL_TYPE_ADPCM) OPL->deltat = (YM_DELTAT *)ptr; ptr+=sizeof(YM_DELTAT); +#endif + /* set channel state pointer */ + OPL->type = type; + OPL->clock = clock; + OPL->rate = rate; + OPL->max_ch = max_ch; + /* init grobal tables */ + OPL_initalize(OPL); + /* reset chip */ + OPLResetChip(OPL); + return OPL; +} + +/* ---------- Destroy one of vietual YM3812 ---------- */ +void OPLDestroy(FM_OPL *OPL) +{ + OPL_UnLockTable(); + emu_Free(OPL); +} + +/* ---------- Option handlers ---------- */ + +void OPLSetTimerHandler(FM_OPL *OPL,OPL_TIMERHANDLER TimerHandler,int channelOffset) +{ + OPL->TimerHandler = TimerHandler; + OPL->TimerParam = channelOffset; +} +void OPLSetIRQHandler(FM_OPL *OPL,OPL_IRQHANDLER IRQHandler,int param) +{ + OPL->IRQHandler = IRQHandler; + OPL->IRQParam = param; +} +void OPLSetUpdateHandler(FM_OPL *OPL,OPL_UPDATEHANDLER UpdateHandler,int param) +{ + OPL->UpdateHandler = UpdateHandler; + OPL->UpdateParam = param; +} +#if BUILD_Y8950 +void OPLSetPortHandler(FM_OPL *OPL,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,int param) +{ + OPL->porthandler_w = PortHandler_w; + OPL->porthandler_r = PortHandler_r; + OPL->port_param = param; +} + +void OPLSetKeyboardHandler(FM_OPL *OPL,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,int param) +{ + OPL->keyboardhandler_w = KeyboardHandler_w; + OPL->keyboardhandler_r = KeyboardHandler_r; + OPL->keyboard_param = param; +} +#endif +/* ---------- YM3812 I/O interface ---------- */ +int OPLWrite(FM_OPL *OPL,int a,int v) +{ + if( !(a&1) ) + { /* address port */ + OPL->address = v & 0xff; + } + else + { /* data port */ + if(OPL->UpdateHandler) OPL->UpdateHandler(OPL->UpdateParam,0); + OPLWriteReg(OPL,OPL->address,v); + } + return OPL->status>>7; +} + +unsigned char OPLRead(FM_OPL *OPL,int a) +{ + if( !(a&1) ) + { /* status port */ + return OPL->status & (OPL->statusmask|0x80); + } + /* data port */ + switch(OPL->address) + { + case 0x05: /* KeyBoard IN */ + if(OPL->type&OPL_TYPE_KEYBOARD) + { + if(OPL->keyboardhandler_r) + return OPL->keyboardhandler_r(OPL->keyboard_param); + else + Log(LOG_WAR,"OPL:read unmapped KEYBOARD port\n"); + } + return 0; +#if 0 + case 0x0f: /* ADPCM-DATA */ + return 0; +#endif + case 0x19: /* I/O DATA */ + if(OPL->type&OPL_TYPE_IO) + { + if(OPL->porthandler_r) + return OPL->porthandler_r(OPL->port_param); + else + Log(LOG_WAR,"OPL:read unmapped I/O port\n"); + } + return 0; + case 0x1a: /* PCM-DATA */ + return 0; + } + return 0; +} + +int OPLTimerOver(FM_OPL *OPL,int c) +{ + if( c ) + { /* Timer B */ + OPL_STATUS_SET(OPL,0x20); + } + else + { /* Timer A */ + OPL_STATUS_SET(OPL,0x40); + /* CSM mode key,TL controll */ + if( OPL->mode & 0x80 ) + { /* CSM mode total level latch and auto key on */ + int ch; + if(OPL->UpdateHandler) OPL->UpdateHandler(OPL->UpdateParam,0); + for(ch=0;ch<9;ch++) + CSMKeyControll( &OPL->P_CH[ch] ); + } + } + /* reload timer */ + if (OPL->TimerHandler) (OPL->TimerHandler)(OPL->TimerParam+c,(double)OPL->T[c]*OPL->TimerBase); + return OPL->status>>7; +} diff --git a/MCUME_teensy/teensysms/fmopl.h b/MCUME_teensy/teensysms/fmopl.h new file mode 100644 index 0000000..a3484cd --- /dev/null +++ b/MCUME_teensy/teensysms/fmopl.h @@ -0,0 +1,142 @@ +#ifndef __FMOPL_H_ +#define __FMOPL_H_ + +typedef void (*OPL_TIMERHANDLER)(int channel,double interval_Sec); +typedef void (*OPL_IRQHANDLER)(int param,int irq); +typedef void (*OPL_UPDATEHANDLER)(int param,int min_interval_us); +typedef void (*OPL_PORTHANDLER_W)(int param,unsigned char data); +typedef unsigned char (*OPL_PORTHANDLER_R)(int param); + +/* !!!!! here is private section , do not access there member direct !!!!! */ + +#define OPL_TYPE_WAVESEL 0x01 /* waveform select */ +#define OPL_TYPE_ADPCM 0x02 /* DELTA-T ADPCM unit */ +#define OPL_TYPE_KEYBOARD 0x04 /* keyboard interface */ +#define OPL_TYPE_IO 0x08 /* I/O port */ + +/* ---------- OPL one of slot ---------- */ +typedef struct fm_opl_slot { + INT32 TL; /* total level :TL << 8 */ + INT32 TLL; /* adjusted now TL */ + UINT8 KSR; /* key scale rate :(shift down bit) */ + INT32 *AR; /* attack rate :&AR_TABLE[AR<<2] */ + INT32 *DR; /* decay rate :&DR_TALBE[DR<<2] */ + INT32 SL; /* sustin level :SL_TALBE[SL] */ + INT32 *RR; /* release rate :&DR_TABLE[RR<<2] */ + UINT8 ksl; /* keyscale level :(shift down bits) */ + UINT8 ksr; /* key scale rate :kcode>>KSR */ + UINT32 mul; /* multiple :ML_TABLE[ML] */ + UINT32 Cnt; /* frequency count : */ + UINT32 Incr; /* frequency step : */ + /* envelope generator state */ + UINT8 eg_typ; /* envelope type flag */ + UINT8 evm; /* envelope phase */ + INT32 evc; /* envelope counter */ + INT32 eve; /* envelope counter end point */ + INT32 evs; /* envelope counter step */ + INT32 evsa; /* envelope step for AR :AR[ksr] */ + INT32 evsd; /* envelope step for DR :DR[ksr] */ + INT32 evsr; /* envelope step for RR :RR[ksr] */ + /* LFO */ + UINT8 ams; /* ams flag */ + UINT8 vib; /* vibrate flag */ + /* wave selector */ + INT32 **wavetable; +}OPL_SLOT; + +/* ---------- OPL one of channel ---------- */ +typedef struct fm_opl_channel { + OPL_SLOT SLOT[2]; + UINT8 CON; /* connection type */ + UINT8 FB; /* feed back :(shift down bit) */ + INT32 *connect1; /* slot1 output pointer */ + INT32 *connect2; /* slot2 output pointer */ + INT32 op1_out[2]; /* slot1 output for selfeedback */ + /* phase generator state */ + UINT32 block_fnum; /* block+fnum : */ + UINT8 kcode; /* key code : KeyScaleCode */ + UINT32 fc; /* Freq. Increment base */ + UINT32 ksl_base; /* KeyScaleLevel Base step */ + UINT8 keyon; /* key on/off flag */ +} OPL_CH; + +/* OPL state */ +typedef struct fm_opl_f { + UINT8 type; /* chip type */ + int clock; /* master clock (Hz) */ + int rate; /* sampling rate (Hz) */ + double freqbase; /* frequency base */ + double TimerBase; /* Timer base time (==sampling time) */ + UINT8 address; /* address register */ + UINT8 status; /* status flag */ + UINT8 statusmask; /* status mask */ + UINT32 mode; /* Reg.08 : CSM , notesel,etc. */ + /* Timer */ + int T[2]; /* timer counter */ + UINT8 st[2]; /* timer enable */ + /* FM channel slots */ + OPL_CH *P_CH; /* pointer of CH */ + int max_ch; /* maximum channel */ + /* Rythm sention */ + UINT8 rythm; /* Rythm mode , key flag */ +#if BUILD_Y8950 + /* Delta-T ADPCM unit (Y8950) */ + YM_DELTAT *deltat; /* DELTA-T ADPCM */ +#endif + /* Keyboard / I/O interface unit (Y8950) */ + UINT8 portDirection; + UINT8 portLatch; + OPL_PORTHANDLER_R porthandler_r; + OPL_PORTHANDLER_W porthandler_w; + int port_param; + OPL_PORTHANDLER_R keyboardhandler_r; + OPL_PORTHANDLER_W keyboardhandler_w; + int keyboard_param; + /* time tables */ + INT32 AR_TABLE[75]; /* atttack rate tables */ + INT32 DR_TABLE[75]; /* decay rate tables */ + UINT32 FN_TABLE[1024]; /* fnumber -> increment counter */ + /* LFO */ + INT32 *ams_table; + INT32 *vib_table; + INT32 amsCnt; + INT32 amsIncr; + INT32 vibCnt; + INT32 vibIncr; + /* wave selector enable flag */ + UINT8 wavesel; + /* external event callback handler */ + OPL_TIMERHANDLER TimerHandler; /* TIMER handler */ + int TimerParam; /* TIMER parameter */ + OPL_IRQHANDLER IRQHandler; /* IRQ handler */ + int IRQParam; /* IRQ parameter */ + OPL_UPDATEHANDLER UpdateHandler; /* stream update handler */ + int UpdateParam; /* stream update parameter */ +} FM_OPL; + +/* ---------- Generic interface section ---------- */ +#define OPL_TYPE_YM3526 (0) +#define OPL_TYPE_YM3812 (OPL_TYPE_WAVESEL) +#define OPL_TYPE_Y8950 (OPL_TYPE_ADPCM|OPL_TYPE_KEYBOARD|OPL_TYPE_IO) + +FM_OPL *OPLCreate(int type, int clock, int rate); +void OPLDestroy(FM_OPL *OPL); +void OPLSetTimerHandler(FM_OPL *OPL,OPL_TIMERHANDLER TimerHandler,int channelOffset); +void OPLSetIRQHandler(FM_OPL *OPL,OPL_IRQHANDLER IRQHandler,int param); +void OPLSetUpdateHandler(FM_OPL *OPL,OPL_UPDATEHANDLER UpdateHandler,int param); +/* Y8950 port handlers */ +void OPLSetPortHandler(FM_OPL *OPL,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,int param); +void OPLSetKeyboardHandler(FM_OPL *OPL,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,int param); + +void OPLResetChip(FM_OPL *OPL); +int OPLWrite(FM_OPL *OPL,int a,int v); +void OPLWriteReg(FM_OPL *OPL, int r, int v); +unsigned char OPLRead(FM_OPL *OPL,int a); +int OPLTimerOver(FM_OPL *OPL,int c); + +/* YM3626/YM3812 local section */ +void YM3812UpdateOne(FM_OPL *OPL, INT16 *buffer, int length); + +void Y8950UpdateOne(FM_OPL *OPL, INT16 *buffer, int length); + +#endif diff --git a/MCUME_teensy/teensysms/font8x8.h b/MCUME_teensy/teensysms/font8x8.h new file mode 100644 index 0000000..2b2ab25 --- /dev/null +++ b/MCUME_teensy/teensysms/font8x8.h @@ -0,0 +1,135 @@ + +// Font: c64_lower.64c + +PROGMEM const unsigned char font8x8[128][8] = +{ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0000 (nul) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0001 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0002 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0003 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0004 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0005 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0006 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0007 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0008 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0009 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+000F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0010 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0011 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0012 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0013 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0014 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0015 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0016 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0017 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0018 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0019 + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001A + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001B + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001C + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001E + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+001F + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0020 (space) + { 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00}, // U+0021 (!) + { 0x36, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0022 (") + { 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36, 0x00}, // U+0023 (#) + { 0x0C, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x0C, 0x00}, // U+0024 ($) + { 0x00, 0x63, 0x33, 0x18, 0x0C, 0x66, 0x63, 0x00}, // U+0025 (%) + { 0x1C, 0x36, 0x1C, 0x6E, 0x3B, 0x33, 0x6E, 0x00}, // U+0026 (&) + { 0x06, 0x06, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0027 (') + { 0x18, 0x0C, 0x06, 0x06, 0x06, 0x0C, 0x18, 0x00}, // U+0028 (() + { 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06, 0x00}, // U+0029 ()) + { 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00}, // U+002A (*) + { 0x00, 0x0C, 0x0C, 0x3F, 0x0C, 0x0C, 0x00, 0x00}, // U+002B (+) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+002C (,) + { 0x00, 0x00, 0x00, 0x3F, 0x00, 0x00, 0x00, 0x00}, // U+002D (-) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+002E (.) + { 0x60, 0x30, 0x18, 0x0C, 0x06, 0x03, 0x01, 0x00}, // U+002F (/) + { 0x3E, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x3E, 0x00}, // U+0030 (0) + { 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x3F, 0x00}, // U+0031 (1) + { 0x1E, 0x33, 0x30, 0x1C, 0x06, 0x33, 0x3F, 0x00}, // U+0032 (2) + { 0x1E, 0x33, 0x30, 0x1C, 0x30, 0x33, 0x1E, 0x00}, // U+0033 (3) + { 0x38, 0x3C, 0x36, 0x33, 0x7F, 0x30, 0x78, 0x00}, // U+0034 (4) + { 0x3F, 0x03, 0x1F, 0x30, 0x30, 0x33, 0x1E, 0x00}, // U+0035 (5) + { 0x1C, 0x06, 0x03, 0x1F, 0x33, 0x33, 0x1E, 0x00}, // U+0036 (6) + { 0x3F, 0x33, 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x00}, // U+0037 (7) + { 0x1E, 0x33, 0x33, 0x1E, 0x33, 0x33, 0x1E, 0x00}, // U+0038 (8) + { 0x1E, 0x33, 0x33, 0x3E, 0x30, 0x18, 0x0E, 0x00}, // U+0039 (9) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x00}, // U+003A (:) + { 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x0C, 0x0C, 0x06}, // U+003B (//) + { 0x18, 0x0C, 0x06, 0x03, 0x06, 0x0C, 0x18, 0x00}, // U+003C (<) + { 0x00, 0x00, 0x3F, 0x00, 0x00, 0x3F, 0x00, 0x00}, // U+003D (=) + { 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06, 0x00}, // U+003E (>) + { 0x1E, 0x33, 0x30, 0x18, 0x0C, 0x00, 0x0C, 0x00}, // U+003F (?) + { 0x3E, 0x63, 0x7B, 0x7B, 0x7B, 0x03, 0x1E, 0x00}, // U+0040 (@) + { 0x0C, 0x1E, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x00}, // U+0041 (A) + { 0x3F, 0x66, 0x66, 0x3E, 0x66, 0x66, 0x3F, 0x00}, // U+0042 (B) + { 0x3C, 0x66, 0x03, 0x03, 0x03, 0x66, 0x3C, 0x00}, // U+0043 (C) + { 0x1F, 0x36, 0x66, 0x66, 0x66, 0x36, 0x1F, 0x00}, // U+0044 (D) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x46, 0x7F, 0x00}, // U+0045 (E) + { 0x7F, 0x46, 0x16, 0x1E, 0x16, 0x06, 0x0F, 0x00}, // U+0046 (F) + { 0x3C, 0x66, 0x03, 0x03, 0x73, 0x66, 0x7C, 0x00}, // U+0047 (G) + { 0x33, 0x33, 0x33, 0x3F, 0x33, 0x33, 0x33, 0x00}, // U+0048 (H) + { 0x1E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0049 (I) + { 0x78, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E, 0x00}, // U+004A (J) + { 0x67, 0x66, 0x36, 0x1E, 0x36, 0x66, 0x67, 0x00}, // U+004B (K) + { 0x0F, 0x06, 0x06, 0x06, 0x46, 0x66, 0x7F, 0x00}, // U+004C (L) + { 0x63, 0x77, 0x7F, 0x7F, 0x6B, 0x63, 0x63, 0x00}, // U+004D (M) + { 0x63, 0x67, 0x6F, 0x7B, 0x73, 0x63, 0x63, 0x00}, // U+004E (N) + { 0x1C, 0x36, 0x63, 0x63, 0x63, 0x36, 0x1C, 0x00}, // U+004F (O) + { 0x3F, 0x66, 0x66, 0x3E, 0x06, 0x06, 0x0F, 0x00}, // U+0050 (P) + { 0x1E, 0x33, 0x33, 0x33, 0x3B, 0x1E, 0x38, 0x00}, // U+0051 (Q) + { 0x3F, 0x66, 0x66, 0x3E, 0x36, 0x66, 0x67, 0x00}, // U+0052 (R) + { 0x1E, 0x33, 0x07, 0x0E, 0x38, 0x33, 0x1E, 0x00}, // U+0053 (S) + { 0x3F, 0x2D, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0054 (T) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x33, 0x3F, 0x00}, // U+0055 (U) + { 0x33, 0x33, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0056 (V) + { 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63, 0x00}, // U+0057 (W) + { 0x63, 0x63, 0x36, 0x1C, 0x1C, 0x36, 0x63, 0x00}, // U+0058 (X) + { 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x0C, 0x1E, 0x00}, // U+0059 (Y) + { 0x7F, 0x63, 0x31, 0x18, 0x4C, 0x66, 0x7F, 0x00}, // U+005A (Z) + { 0x1E, 0x06, 0x06, 0x06, 0x06, 0x06, 0x1E, 0x00}, // U+005B ([) + { 0x03, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x40, 0x00}, // U+005C (\) + { 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E, 0x00}, // U+005D (]) + { 0x08, 0x1C, 0x36, 0x63, 0x00, 0x00, 0x00, 0x00}, // U+005E (^) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF}, // U+005F (_) + { 0x0C, 0x0C, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+0060 (`) + { 0x00, 0x00, 0x1E, 0x30, 0x3E, 0x33, 0x6E, 0x00}, // U+0061 (a) + { 0x07, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3B, 0x00}, // U+0062 (b) + { 0x00, 0x00, 0x1E, 0x33, 0x03, 0x33, 0x1E, 0x00}, // U+0063 (c) + { 0x38, 0x30, 0x30, 0x3e, 0x33, 0x33, 0x6E, 0x00}, // U+0064 (d) + { 0x00, 0x00, 0x1E, 0x33, 0x3f, 0x03, 0x1E, 0x00}, // U+0065 (e) + { 0x1C, 0x36, 0x06, 0x0f, 0x06, 0x06, 0x0F, 0x00}, // U+0066 (f) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0067 (g) + { 0x07, 0x06, 0x36, 0x6E, 0x66, 0x66, 0x67, 0x00}, // U+0068 (h) + { 0x0C, 0x00, 0x0E, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+0069 (i) + { 0x30, 0x00, 0x30, 0x30, 0x30, 0x33, 0x33, 0x1E}, // U+006A (j) + { 0x07, 0x06, 0x66, 0x36, 0x1E, 0x36, 0x67, 0x00}, // U+006B (k) + { 0x0E, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x1E, 0x00}, // U+006C (l) + { 0x00, 0x00, 0x33, 0x7F, 0x7F, 0x6B, 0x63, 0x00}, // U+006D (m) + { 0x00, 0x00, 0x1F, 0x33, 0x33, 0x33, 0x33, 0x00}, // U+006E (n) + { 0x00, 0x00, 0x1E, 0x33, 0x33, 0x33, 0x1E, 0x00}, // U+006F (o) + { 0x00, 0x00, 0x3B, 0x66, 0x66, 0x3E, 0x06, 0x0F}, // U+0070 (p) + { 0x00, 0x00, 0x6E, 0x33, 0x33, 0x3E, 0x30, 0x78}, // U+0071 (q) + { 0x00, 0x00, 0x3B, 0x6E, 0x66, 0x06, 0x0F, 0x00}, // U+0072 (r) + { 0x00, 0x00, 0x3E, 0x03, 0x1E, 0x30, 0x1F, 0x00}, // U+0073 (s) + { 0x08, 0x0C, 0x3E, 0x0C, 0x0C, 0x2C, 0x18, 0x00}, // U+0074 (t) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x33, 0x6E, 0x00}, // U+0075 (u) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x1E, 0x0C, 0x00}, // U+0076 (v) + { 0x00, 0x00, 0x63, 0x6B, 0x7F, 0x7F, 0x36, 0x00}, // U+0077 (w) + { 0x00, 0x00, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x00}, // U+0078 (x) + { 0x00, 0x00, 0x33, 0x33, 0x33, 0x3E, 0x30, 0x1F}, // U+0079 (y) + { 0x00, 0x00, 0x3F, 0x19, 0x0C, 0x26, 0x3F, 0x00}, // U+007A (z) + { 0x38, 0x0C, 0x0C, 0x07, 0x0C, 0x0C, 0x38, 0x00}, // U+007B ({) + { 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18, 0x00}, // U+007C (|) + { 0x07, 0x0C, 0x0C, 0x38, 0x0C, 0x0C, 0x07, 0x00}, // U+007D (}) + { 0x6E, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // U+007E (~) + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} // U+007F +}; + diff --git a/MCUME_teensy/teensysms/iopins.h b/MCUME_teensy/teensysms/iopins.h new file mode 100644 index 0000000..f57086c --- /dev/null +++ b/MCUME_teensy/teensysms/iopins.h @@ -0,0 +1,98 @@ +#ifndef IOPINS_H +#define IOPINS_H + +//#define OLD_LAYOUT 1 + +#include "tft_t_dma_config.h" + +#ifndef OLD_LAYOUT + +#ifdef ST7789 +// ST7789 +#define TFT_SCLK 13 +#define TFT_MOSI 11 +#define TFT_MISO 12 +#define TFT_TOUCH_CS 255 +#define TFT_TOUCH_INT 255 +#define TFT_DC 9 +#define TFT_CS 255 +#define TFT_RST 23 +#else +// ILI9341 +#define TFT_SCLK 13 +#define TFT_MOSI 11 +#define TFT_MISO 12 +#define TFT_TOUCH_CS 255 //38 +#define TFT_TOUCH_INT 255 //37 +#define TFT_DC 9 +#define TFT_CS 23 +#define TFT_RST 255 +#endif + +// PSRAM +#define PSRAM_CS 36 +#define PSRAM_MOSI 35 +#define PSRAM_MISO 34 +#define PSRAM_SCLK 37 + +// SD +#define SD_SCLK 13 +#define SD_MOSI 11 +#define SD_MISO 12 +//#define SD_CS BUILTIN_SDCARD +#define SD_CS 5 + +// I2C keyboard +#define I2C_SCL_IO 19 +#define I2C_SDA_IO 18 + +// Analog joystick (primary) for JOY2 and 5 extra buttons +#define PIN_JOY2_A1X A1 +#define PIN_JOY2_A2Y A2 +#define PIN_JOY2_BTN 17 +#define PIN_KEY_USER1 3 //34 +#define PIN_KEY_USER2 4 //35 +//#define PIN_KEY_USER3 255 +//#define PIN_KEY_USER4 255 + + +#else // OLD LAYOUT!!!! + +#define HAS_VGA 1 + +// ILI9341 +#define TFT_SCLK 13 +#define TFT_MOSI 11 +#define TFT_MISO 12 +#define TFT_TOUCH_CS 38 +#define TFT_TOUCH_INT 37 +#define TFT_DC 9 +#define TFT_CS 10 +#define TFT_RST 255 //connected to 3.3V + +// I2C keyboard +#define I2C_SCL_IO 3 +#define I2C_SDA_IO 4 + +// Analog joystick (primary) for JOY2 and 5 extra buttons +#define PIN_JOY2_A1X A12 +#define PIN_JOY2_A2Y A13 +#define PIN_JOY2_BTN 36 +#define PIN_KEY_USER1 35 +#define PIN_KEY_USER2 34 +#define PIN_KEY_USER3 33 +#define PIN_KEY_USER4 39 + +// Second joystick +#define PIN_JOY1_BTN 30 +#define PIN_JOY1_1 16 +#define PIN_JOY1_2 17 +#define PIN_JOY1_3 18 +#define PIN_JOY1_4 19 +#endif + +#endif + + + + diff --git a/MCUME_teensy/teensysms/keyboard_osd.h b/MCUME_teensy/teensysms/keyboard_osd.h new file mode 100644 index 0000000..062eb4e --- /dev/null +++ b/MCUME_teensy/teensysms/keyboard_osd.h @@ -0,0 +1,20 @@ + +#ifndef keyboard_osd_h_ +#define keyboard_osd_h_ + +extern bool virtualkeyboardIsActive(void); +extern void drawVirtualkeyboard(void); +extern void toggleVirtualkeyboard(bool keepOn); +extern void handleVirtualkeyboard(void); + +extern bool callibrationActive(void); +extern int handleCallibration(uint16_t bClick); + +extern bool menuActive(void); +extern char * menuSelection(void); +extern void toggleMenu(bool on); +extern int handleMenu(uint16_t bClick); + + +#endif + diff --git a/MCUME_teensy/teensysms/logo.h b/MCUME_teensy/teensysms/logo.h new file mode 100644 index 0000000..692a06c --- /dev/null +++ b/MCUME_teensy/teensysms/logo.h @@ -0,0 +1,241 @@ +PROGMEM const uint16_t logo[] = { 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diff --git a/MCUME_teensy/teensysms/memory.c b/MCUME_teensy/teensysms/memory.c new file mode 100644 index 0000000..872d82a --- /dev/null +++ b/MCUME_teensy/teensysms/memory.c @@ -0,0 +1,25 @@ +#include "shared.h" + + +uint8 * cache; + + + +void mem_init(void) { + cache = emu_Malloc(CACHE_SIZE); +} + + +int mem_test(void) { +// for (int i=0x40000;i 0) { + write_rom(dst++, read_rom(src++)); + size--; + } +} diff --git a/MCUME_teensy/teensysms/memory.h b/MCUME_teensy/teensysms/memory.h new file mode 100644 index 0000000..f5aac9d --- /dev/null +++ b/MCUME_teensy/teensysms/memory.h @@ -0,0 +1,22 @@ +#ifndef _MEMORY_H_ +#define _MEMORY_H_ + +#include "shared.h" + +#define CACHE_SIZE 0x20000 + + +extern uint8 * cache; + + +extern void mem_init(void); +extern int mem_test(void); +extern uint8 rom_version(void); +extern uint8 readb_rom(int address); +extern uint8 readb_swap_rom(int address); +extern uint16 readw_swap_rom(int address); +extern void write_rom(int address, uint8 val); + +extern void memcpy_rom(int dst, int src, int size); + +#endif diff --git a/MCUME_teensy/teensysms/psram_t.cpp b/MCUME_teensy/teensysms/psram_t.cpp new file mode 100644 index 0000000..3a47eb8 --- /dev/null +++ b/MCUME_teensy/teensysms/psram_t.cpp @@ -0,0 +1,356 @@ +/* + PSRAM driver for IPS6404 +*/ + +#include "psram_t.h" + +#include +#include + +#define SPI SPI2 + +//#define SPICLOCK 104000000 +#define SPICLOCK 70000000 +//#define SPICLOCK 144e6 //Just a number..max speed +#define SPI_MODE SPI_MODE0 + +#define RAM_READ 0xB +//#define RAM_READ 0x3 +#define RAM_WRITE 0x2 + + +uint8_t PSRAM_T::_cs, PSRAM_T::_miso, PSRAM_T::_mosi, PSRAM_T::_sclk; +Page PSRAM_T::pages[MAX_PAGES]; +uint8_t PSRAM_T::nbPages=0; +int8_t PSRAM_T::top=0; +int8_t PSRAM_T::last=0; + + +PSRAM_T::PSRAM_T(uint8_t cs, uint8_t mosi, uint8_t sclk, uint8_t miso) +{ + _cs = cs; + _mosi = mosi; + _sclk = sclk; + _miso = miso; + pinMode(_cs, OUTPUT); + digitalWrite(_cs, 1); +} + + +void PSRAM_T::begin(void) +{ + SPI.setMOSI(_mosi); + SPI.setMISO(_miso); + SPI.setSCK(_sclk); + SPI.begin(); + + delay(1); + + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(0x66); + digitalWrite(_cs, 1); + SPI.endTransaction(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + SPI.transfer(0x99); + SPI.endTransaction(); + digitalWrite(_cs, 1); + delayMicroseconds(20); +} + + + +uint8_t PSRAM_T::psram_read(uint32_t addr) +{ + uint8_t val=0; + + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_READ); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); +#if RAM_READ == 0xB + SPI.transfer(0xFF); +#endif + val = SPI.transfer(0xFF); + SPI.endTransaction(); + digitalWrite(_cs, 1); + return val; +} + + +void PSRAM_T::psram_read_n(uint32_t addr, uint8_t * val, int n) +{ + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_READ); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); +#if RAM_READ == 0xB + SPI.transfer(0xFF); +#endif + /* + while (n > 0) { + *val++ = SPI.transfer(0xFF); + n--; + } + */ + SPI.transfer(val,n); + SPI.endTransaction(); + digitalWrite(_cs, 1); +} + + +void PSRAM_T::psram_write(uint32_t addr, uint8_t val) +{ + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + SPI.transfer(val); + SPI.endTransaction(); + digitalWrite(_cs, 1); +} + +static uint8_t resp[PAGE_SIZE]; + + +void PSRAM_T::psram_write_n(uint32_t addr, uint8_t * val, int n) +{ + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + /* + while (n > 0) { + SPI.transfer(*val++); + n--; + } + */ + SPI.transfer(val,&resp[0],n); + SPI.endTransaction(); + digitalWrite(_cs, 1); +} + + +#ifdef DMATRY +#include + +DMAMEM static uint8_t src[PAGE_SIZE+4]; +DMAMEM static uint8_t dst[PAGE_SIZE+4]; +static DMASetting dmasettings[8]; +static DMAChannel dmatx; +static volatile uint8_t rstop = 0; + +#define DMASPI_PRINT(x) do {Serial.printf(x) ; Serial.flush();} while (0); + +static void dmaInterrupt() +{ + dmatx.clearInterrupt(); + rstop = 1; + //DMASPI_PRINT("irq"); +} + +void PSRAM_T::psram_write_n_dma(uint32_t addr, uint8_t * val, int n) { + uint8_t * dstPt = &dst[0]; + //*dstPt++ = RAM_WRITE; + //*dstPt++ = (addr>>16)&0xff; + //*dstPt++ = (addr>>8)&0xff; + //*dstPt++ = addr&0xff; + int cnt = n; + while (cnt > 0) { + *dstPt++ = *val++; + cnt--; + } + arm_dcache_flush(&dst[0], n); + rstop = 0; + dmatx.disable(); + dmatx.attachInterrupt(dmaInterrupt); + + dmasettings[0].sourceBuffer(&dst[0], n); + //dmasettings[0].destination((uint8_t &) LPSPI4_TDR); + dmasettings[0].destination((uint8_t &) IMXRT_LPSPI1_S.TDR); + dmasettings[0].TCD->ATTR_DST = 1; + dmasettings[0].interruptAtCompletion(); + +Serial.printf("A") ; Serial.flush(); + + digitalWrite(_cs, HIGH); + // SPI.begin(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + + digitalWrite(_cs, 0); + SPI.transfer(RAM_WRITE); + SPI.transfer((addr>>16)&0xff); + SPI.transfer((addr>>8)&0xff); + SPI.transfer(addr&0xff); + //SPI.transfer(0); + //SPI.transfer(1); +Serial.printf("B") ; Serial.flush(); + +#ifdef XXX + LPSPI4_CR &= ~LPSPI_CR_MEN;//disable LPSPI: + LPSPI4_CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + //LPSPI4_TCR = 15; // Framesize 16 Bits + IMXRT_LPSPI4_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + LPSPI4_DER = LPSPI_DER_TDDE; //TX DMA Request Enable + // IMXRT_LPSPI4_S.DER = LPSPI_DER_TDDE; // | LPSPI_DER_RDDE; //enable DMA on both TX and RX + LPSPI4_CR |= LPSPI_CR_MEN; //enable LPSPI: + //IMXRT_LPSPI4_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + // IMXRT_LPSPI4_S.FCR = 0; + // Lets try to output the first byte to make sure that we are in 8 bit mode... + // IMXRT_LPSPI4_S.SR = 0x3f00; // clear out all of the other status... + + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI4_TX ); +#endif + IMXRT_LPSPI1_S.CR &= ~LPSPI_CR_MEN;//disable LPSPI: + IMXRT_LPSPI1_S.CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + IMXRT_LPSPI1_S.TCR = (IMXRT_LPSPI4_S.TCR & ~(LPSPI_TCR_FRAMESZ(31))) | LPSPI_TCR_FRAMESZ(7); + IMXRT_LPSPI1_S.DER = LPSPI_DER_TDDE; //TX DMA Request Enable + IMXRT_LPSPI1_S.CR |= LPSPI_CR_MEN; //enable LPSPI: + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI1_TX ); +Serial.printf("C") ; Serial.flush(); +// SPI.initDMAChannels(); + dmatx = dmasettings[0]; + + dmatx.enable(); +Serial.printf("D") ; Serial.flush(); + while (rstop == 0) {}; + + Serial.printf("E") ; Serial.flush(); + digitalWrite(_cs, 1); +} +#endif + + + + +void PSRAM_T::pswrite(uint32_t addr, uint8_t val) +{ + psram_write(addr, val); + //return; + uint32_t curPage=addr&(~(PAGE_SIZE-1)); + for (int i=0; i + +#define PAGE_SIZE 16 //16 //32 //2048 //1024 +#define MAX_PAGES 8 + +struct Page { + uint8_t page[PAGE_SIZE]; + uint32_t pageid; + int8_t next; + int8_t prev; +}; + +class PSRAM_T +{ + public: + PSRAM_T(uint8_t _CS, uint8_t _MOSI=11, uint8_t _SCLK=13, uint8_t _MISO=12); + void begin(void); + void pswrite(uint32_t addr, uint8_t val); + uint8_t psread(uint32_t addr); + uint16_t psread_w(uint32_t addr); + + private: + static uint8_t psram_read(uint32_t addr); + static void psram_read_n(uint32_t addr, uint8_t * val, int n); + static void psram_write(uint32_t addr, uint8_t val); + static void psram_write_n(uint32_t addr, uint8_t * val, int n); + + protected: + static uint8_t _cs, _miso, _mosi, _sclk; + static Page pages[MAX_PAGES]; + static uint8_t nbPages; + static int8_t top; + static int8_t last; +}; +#endif + +#endif + diff --git a/MCUME_teensy/teensysms/render.c b/MCUME_teensy/teensysms/render.c new file mode 100644 index 0000000..7cd6cea --- /dev/null +++ b/MCUME_teensy/teensysms/render.c @@ -0,0 +1,512 @@ +#include "shared.h" + +/* Background drawing function */ +static void (*render_bg)(int line); + +/* Pointer to output buffer */ +static byte *linebuf; + +/* Internal buffer for drawing non 8-bit displays */ +static byte internal_buffer[0x100]; + +/* Pattern cache */ +//static byte cache[0x20000]; + +/* Dirty pattern info */ +byte svram_dirty[0x200]; +byte sis_vram_dirty; + +/* Pixel look-up table */ +//#include "genlut.h" +#include "smslut.h" +//static byte lut[0x10000]; + + +/* Attribute expansion table */ +static UINT32 atex[4] = +{ + 0x00000000, + 0x10101010, + 0x20202020, + 0x30303030, +}; + +/* Display sizes */ +static int vp_vstart; +static int vp_vend; +static int vp_hstart; +static int vp_hend; + + +/* Macros to access memory 32-bits at a time (from MAME's drawgfx.c) */ + +#ifdef ALIGN_DWORD + +static __inline__ UINT32 read_dword(void *address) +{ + if ((UINT32)address & 3) + { +#ifdef LSB_FIRST /* little endian version */ + return ( *((byte *)address) + + (*((byte *)address+1) << 8) + + (*((byte *)address+2) << 16) + + (*((byte *)address+3) << 24) ); +#else /* big endian version */ + return ( *((byte *)address+3) + + (*((byte *)address+2) << 8) + + (*((byte *)address+1) << 16) + + (*((byte *)address) << 24) ); +#endif + } + else + return *(UINT32 *)address; +} + + +static __inline__ void write_dword(void *address, UINT32 data) +{ + if ((UINT32)address & 3) + { +#ifdef LSB_FIRST + *((byte *)address) = data; + *((byte *)address+1) = (data >> 8); + *((byte *)address+2) = (data >> 16); + *((byte *)address+3) = (data >> 24); +#else + *((byte *)address+3) = data; + *((byte *)address+2) = (data >> 8); + *((byte *)address+1) = (data >> 16); + *((byte *)address) = (data >> 24); +#endif + return; + } + else + *(UINT32 *)address = data; +} +#else +#define read_dword(address) *(UINT32 *)address +#define write_dword(address,data) *(UINT32 *)address=data +#endif + + +/****************************************************************************/ + + +/* Initialize the rendering data */ +void render_init(void) +{ + render_reset(); +} + + +/* Reset the rendering data */ +void render_reset(void) +{ + int i; + + /* Clear display bitmap */ +// memset(sbitmap.data, 0, sbitmap.pitch * sbitmap.height); + + /* Clear palette */ + for(i = 0; i < PALETTE_SIZE; i += 1) + { + palette_sync(i); + } + + /* Invalidate pattern cache */ + sis_vram_dirty = 1; + memset(svram_dirty, 1, 0x200); + memset(cache, 0, CACHE_SIZE); + + /* Set up viewport size */ + if(IS_GG) + { + vp_vstart = 24; + vp_vend = 168; + vp_hstart = 6; + vp_hend = 26; + } + else + { + vp_vstart = 0; + vp_vend = 192; + vp_hstart = 0; + vp_hend = 32; + } + + /* Pick render routine */ + render_bg = IS_GG ? render_bg_gg : render_bg_sms; +} + + +/* Draw a line of the display */ +void render_line(int line) +{ + /* Ensure we're within the viewport range */ + if((line < vp_vstart) || (line >= vp_vend)) return; + + /* Point to current line in output buffer */ + linebuf = &internal_buffer[0]; + + /* Update pattern cache */ + update_cache(); + + /* Blank line */ + if( (!(vdp.reg[1] & 0x40)) || (((vdp.reg[2] & 1) == 0) && (IS_SMS))) + { + memset(linebuf + (vp_hstart << 3), BACKDROP_COLOR, BMP_WIDTH); + } + else + { + /* Draw background */ + render_bg(line); + + /* Draw sprites */ + render_obj(line); + + /* Blank leftmost column of display */ + if(vdp.reg[0] & 0x20) + { + memset(linebuf, BACKDROP_COLOR, 8); + } + } + + emu_DrawLine(&internal_buffer[BMP_X_OFFSET], BMP_WIDTH , BMP_HEIGHT, line); +} + + +/* Draw the Master System background */ +void render_bg_sms(int line) +{ + int locked = 0; + int v_line = (line + vdp.reg[9]) % 224; + int v_row = (v_line & 7) << 3; + int hscroll = ((vdp.reg[0] & 0x40) && (line < 0x10)) ? 0 : (0x100 - vdp.reg[8]); + int column = vp_hstart; + UINT16 attr; + UINT16 *nt = (UINT16 *)&vdp.vram[vdp.ntab + ((v_line >> 3) << 6)]; + int nt_scroll = (hscroll >> 3); + int shift = (hscroll & 7); + UINT32 atex_mask; + UINT32 *cache_ptr; + UINT32 *linebuf_ptr = (UINT32 *)&linebuf[0 - shift]; + + /* Draw first column (clipped) */ + if(shift) + { + int x, c, a; + + attr = nt[(column + nt_scroll) & 0x1F]; + +#ifndef LSB_FIRST + attr = (((attr & 0xFF) << 8) | ((attr & 0xFF00) >> 8)); +#endif + a = (attr >> 7) & 0x30; + + for(x = shift; x < 8; x += 1) + { + c = cache[((attr & 0x7FF) << 6) | (v_row) | (x)]; + linebuf[(0 - shift) + (x) ] = ((c) | (a)); + } + + column += 1; + } + + /* Draw a line of the background */ + for(; column < vp_hend; column += 1) + { + /* Stop vertical scrolling for leftmost eight columns */ + if((vdp.reg[0] & 0x80) && (!locked) && (column >= 24)) + { + locked = 1; + v_row = (line & 7) << 3; + nt = (UINT16 *)&vdp.vram[((vdp.reg[2] << 10) & 0x3800) + ((line >> 3) << 6)]; + } + + /* Get name table attribute word */ + attr = nt[(column + nt_scroll) & 0x1F]; + +#ifndef LSB_FIRST + attr = (((attr & 0xFF) << 8) | ((attr & 0xFF00) >> 8)); +#endif + /* Expand priority and palette bits */ + atex_mask = atex[(attr >> 11) & 3]; + + /* Point to a line of pattern data in cache */ + cache_ptr = (UINT32 *)&cache[((attr & 0x7FF) << 6) | (v_row)]; + + /* Copy the left half, adding the attribute bits in */ + write_dword( &linebuf_ptr[(column << 1)] , read_dword( &cache_ptr[0] ) | (atex_mask)); + + /* Copy the right half, adding the attribute bits in */ + write_dword( &linebuf_ptr[(column << 1) | (1)], read_dword( &cache_ptr[1] ) | (atex_mask)); + } + + /* Draw last column (clipped) */ + if(shift) + { + int x, c, a; + + char *p = &linebuf[(0 - shift)+(column << 3)]; + + attr = nt[(column + nt_scroll) & 0x1F]; + +#ifndef LSB_FIRST + attr = (((attr & 0xFF) << 8) | ((attr & 0xFF00) >> 8)); +#endif + a = (attr >> 7) & 0x30; + + for(x = 0; x < shift; x += 1) + { + c = cache[((attr & 0x7FF) << 6) | (v_row) | (x)]; + p[x] = ((c) | (a)); + } + } +} + + +/* Draw the Game Gear background */ +void render_bg_gg(int line) +{ + int v_line = (line + vdp.reg[9]) % 224; + int v_row = (v_line & 7) << 3; + int hscroll = (0x100 - vdp.reg[8]); + int column; + UINT16 attr; + UINT16 *nt = (UINT16 *)&vdp.vram[vdp.ntab + ((v_line >> 3) << 6)]; + int nt_scroll = (hscroll >> 3); + UINT32 atex_mask; + UINT32 *cache_ptr; + UINT32 *linebuf_ptr = (UINT32 *)&linebuf[0 - (hscroll & 7)]; + + /* Draw a line of the background */ + for(column = vp_hstart; column <= vp_hend; column += 1) + { + /* Get name table attribute word */ + attr = nt[(column + nt_scroll) & 0x1F]; + +#ifndef LSB_FIRST + attr = (((attr & 0xFF) << 8) | ((attr & 0xFF00) >> 8)); +#endif + /* Expand priority and palette bits */ + atex_mask = atex[(attr >> 11) & 3]; + + /* Point to a line of pattern data in cache */ + cache_ptr = (UINT32 *)&cache[((attr & 0x7FF) << 6) | (v_row)]; + + /* Copy the left half, adding the attribute bits in */ + write_dword( &linebuf_ptr[(column << 1)] , read_dword( &cache_ptr[0] ) | (atex_mask)); + + /* Copy the right half, adding the attribute bits in */ + write_dword( &linebuf_ptr[(column << 1) | (1)], read_dword( &cache_ptr[1] ) | (atex_mask)); + } +} + + +/* Draw sprites */ +void render_obj(int line) +{ + int i; + + /* Sprite count for current line (8 max.) */ + int count = 0; + + /* Sprite dimensions */ + int width = 8; + int height = (vdp.reg[1] & 0x02) ? 16 : 8; + + /* Pointer to sprite attribute table */ + byte *st = (byte *)&vdp.vram[vdp.satb]; + + /* Adjust dimensions for double size sprites */ + if(vdp.reg[1] & 0x01) + { + width *= 2; + height *= 2; + } + + /* Draw sprites in front-to-back order */ + for(i = 0; i < 64; i += 1) + { + /* Sprite Y position */ + int yp = st[i]; + + /* End of sprite list marker? */ + if(yp == 208) return; + + /* Actual Y position is +1 */ + yp += 1; + + /* Wrap Y coordinate for sprites > 240 */ + if(yp > 240) yp -= 256; + + /* Check if sprite falls on current line */ + if((line >= yp) && (line < (yp + height))) + { + byte *linebuf_ptr; + + /* Width of sprite */ + int start = 0; + int end = width; + + /* Sprite X position */ + int xp = st[0x80 + (i << 1)]; + + /* Pattern name */ + int n = st[0x81 + (i << 1)]; + + /* Bump sprite count */ + count += 1; + + /* Too many sprites on this line ? */ + if((vdp.limit) && (count == 9)) return; + + /* X position shift */ + if(vdp.reg[0] & 0x08) xp -= 8; + + /* Add MSB of pattern name */ + if(vdp.reg[6] & 0x04) n |= 0x0100; + + /* Mask LSB for 8x16 sprites */ + if(vdp.reg[1] & 0x02) n &= 0x01FE; + + /* Point to offset in line buffer */ + linebuf_ptr = (byte *)&linebuf[xp]; + + /* Clip sprites on left edge */ + if(xp < 0) + { + start = (0 - xp); + } + + /* Clip sprites on right edge */ + if((xp + width) > 256) + { + end = (256 - xp); + } + + /* Draw double size sprite */ + if(vdp.reg[1] & 0x01) + { + int x; + byte *cache_ptr = (byte *)&cache[(n << 6) | (((line - yp) >> 1) << 3)]; + + /* Draw sprite line */ + for(x = start; x < end; x += 1) + { + /* Source pixel from cache */ + byte sp = cache_ptr[(x >> 1)]; + + /* Only draw opaque sprite pixels */ + if(sp) + { + /* Background pixel from line buffer */ + byte bg = linebuf_ptr[x]; + + /* Look up result */ + linebuf_ptr[x] = lut[(bg << 8) | (sp)]; /* + COL_OFFSET; */ + + /* Set sprite collision flag */ + if(bg & 0x40) vdp.status |= 0x20; + } + } + } + else /* Regular size sprite (8x8 / 8x16) */ + { + int x; + byte *cache_ptr = (byte *)&cache[(n << 6) | ((line - yp) << 3)]; + + /* Draw sprite line */ + for(x = start; x < end; x += 1) + { + /* Source pixel from cache */ + byte sp = cache_ptr[x]; + + /* Only draw opaque sprite pixels */ + if(sp) + { + /* Background pixel from line buffer */ + byte bg = linebuf_ptr[x]; + + /* Look up result */ + linebuf_ptr[x] = lut[(bg << 8) | (sp)]; /* + COL_OFFSET; */ + + /* Set sprite collision flag */ + if(bg & 0x40) vdp.status |= 0x20; + } + } + } + } + } +} + + +/* Update pattern cache with modified tiles */ +void update_cache(void) +{ + int i, x, y, c; + int b0, b1, b2, b3; + int i0, i1, i2, i3; + + if(!sis_vram_dirty) return; + sis_vram_dirty = 0; + + for(i = 0; i < 0x200; i += 1) + { + if(svram_dirty[i]) + { + svram_dirty[i] = 0; + + for(y = 0; y < 8; y += 1) + { + b0 = vdp.vram[(i << 5) | (y << 2) | (0)]; + b1 = vdp.vram[(i << 5) | (y << 2) | (1)]; + b2 = vdp.vram[(i << 5) | (y << 2) | (2)]; + b3 = vdp.vram[(i << 5) | (y << 2) | (3)]; + + for(x = 0; x < 8; x += 1) + { + i0 = (b0 >> (7 - x)) & 1; + i1 = (b1 >> (7 - x)) & 1; + i2 = (b2 >> (7 - x)) & 1; + i3 = (b3 >> (7 - x)) & 1; + + c = (i3 << 3 | i2 << 2 | i1 << 1 | i0); + + cache[0x00000 | (i << 6) | ((y ) << 3) | (x )] = c; + cache[0x08000 | (i << 6) | ((y ) << 3) | (7-x)] = c; + cache[0x10000 | (i << 6) | ((7-y) << 3) | (x )] = c; + cache[0x18000 | (i << 6) | ((7-y) << 3) | (7-x)] = c; + } + } + } + } +} + +/* Update a palette entry */ +void palette_sync(int index) +{ + int r, g, b; + + if(IS_GG) + { + r = ((vdp.cram[(index << 1) | 0] >> 1) & 7) << 5; + g = ((vdp.cram[(index << 1) | 0] >> 5) & 7) << 5; + b = ((vdp.cram[(index << 1) | 1] >> 1) & 7) << 5; + } + else + { + r = ((vdp.cram[index] >> 0) & 3) << 6; + g = ((vdp.cram[index] >> 2) & 3) << 6; + b = ((vdp.cram[index] >> 4) & 3) << 6; + } + + emu_SetPaletteEntry(r,g,b,index); + + sbitmap.pal.dirty[index] = sbitmap.pal.update = 1; +} + + + + + diff --git a/MCUME_teensy/teensysms/render.h b/MCUME_teensy/teensysms/render.h new file mode 100644 index 0000000..35ab6f0 --- /dev/null +++ b/MCUME_teensy/teensysms/render.h @@ -0,0 +1,23 @@ + +#ifndef _RENDER_H_ +#define _RENDER_H_ + + +/* Used for blanking a line in whole or in part */ +#define BACKDROP_COLOR (0x10 | (vdp.reg[7] & 0x0F)) + +/* Global data - used by 'vdp.c' */ +extern byte svram_dirty[0x200]; +extern byte sis_vram_dirty; + +/* Function prototypes */ +void render_init(void); +void render_reset(void); +void render_bg_gg(int line); +void render_bg_sms(int line); +void render_obj(int line); +void render_line(int line); +void update_cache(void); +void palette_sync(int index); + +#endif /* _RENDER_H_ */ diff --git a/MCUME_teensy/teensysms/shared.h b/MCUME_teensy/teensysms/shared.h new file mode 100644 index 0000000..9c68474 --- /dev/null +++ b/MCUME_teensy/teensysms/shared.h @@ -0,0 +1,60 @@ + +#ifndef _SHARED_H_ +#define _SHARED_H_ + +#define VERSION "0.9.3" + +//#define ALIGN_DWORD 1 +#define LSB_FIRST 1 +#define SOUND_PRESENT 1 + +/* Data types */ + +typedef unsigned char byte; + +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef signed char INT8; +typedef signed short INT16; +typedef signed int INT32; + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed int int32; + +#define NULL 0 + +typedef union { +#ifdef LSB_FIRST + struct { UINT8 l,h,h2,h3; } b; + struct { UINT16 l,h; } w; +#else + struct { UINT8 h3,h2,h,l; } b; + struct { UINT16 h,l; } w; +#endif + UINT32 d; +} PAIR; + +#define __inline__ + +/* To keep the MAME code happy */ +#define HAS_YM3812 1 +typedef signed short int FMSAMPLE; + + +#include "memory.h" +#include "z80.h" +#include "sms.h" +#include "vdp.h" +#include "render.h" +#include "sn76496.h" +#include "fmopl.h" +#include "ym2413.h" +#include "system.h" + +#endif /* _SHARED_H_ */ + diff --git a/MCUME_teensy/teensysms/sms.c b/MCUME_teensy/teensysms/sms.c new file mode 100644 index 0000000..16afca3 --- /dev/null +++ b/MCUME_teensy/teensysms/sms.c @@ -0,0 +1,316 @@ +#include "shared.h" + +/* SMS context */ +t_sms sms; +t_input input; /* Controller input */ + +/* Run the virtual console emulation for one frame */ +void sms_frame(int skip_render) +{ + /* Take care of hard resets */ + if(input.system & INPUT_HARD_RESET) + { + system_reset(); + } + + /* Debounce pause key */ + if(input.system & INPUT_PAUSE) + { + if(!sms.paused) + { + sms.paused = 1; + + z80_set_nmi_line(ASSERT_LINE); + z80_set_nmi_line(CLEAR_LINE); + } + } + else + { + sms.paused = 0; + } + + if(smssnd.log) smssnd.callback(0x00); + + for(vdp.line = 0; vdp.line < 262; vdp.line += 1) + { + /* Handle VDP line events */ + vdp_run(); + + /* Draw the current frame */ + if(!skip_render) render_line(vdp.line); + + /* Run the Z80 for a line */ + z80_execute(227); + } +} + +void audio_play_sample(int16 *bufl, int16 *bufr, int length) +{ + length = length/2; + + if(smssnd.enabled) + { + int count; + + SN76496Update(0, smssnd.psg_buffer, length, sms.psg_mask); + if(sms.use_fm) YM3812UpdateOne(ym3812, smssnd.fm_buffer, length); + + for(count = 0; count < length; count += 1) + { + signed short left = 0; + signed short right = 0; + if (sms.use_fm) left = right = smssnd.fm_buffer[count]; + left += smssnd.psg_buffer[0][count]; + right += smssnd.psg_buffer[1][count]; + *bufl++ = left; + *bufl++ = right; + } + } + +} + + + +void sms_init(void) +{ +#if PSX + z80_set_context((void *)0x1F800000); +#endif + cpu_reset(); + sms_reset(); +} + + +void sms_reset(void) +{ + memset(&input, 0, sizeof(t_input)); + + /* Clear SMS context */ + memset(sms.dummy, 0, 0x2000); + memset(sms.ram, 0, 0x2000); + memset(sms.sram, 0, 0x8000); + sms.paused = sms.save = sms.port_3F = sms.port_F2 = sms.irq = 0x00; + sms.psg_mask = 0xFF; + + /* Load memory maps with default values */ + cpu_readmap[0] = 0x0000; + cpu_readmap[1] = 0x2000; + cpu_readmap[2] = 0x4000; + cpu_readmap[3] = 0x6000; + cpu_readmap[4] = 0x0000; + cpu_readmap[5] = 0x2000; + cpu_readmap[6] = sms.ram; + cpu_readmap[7] = sms.ram; + + cpu_writemap[0] = sms.dummy; + cpu_writemap[1] = sms.dummy; + cpu_writemap[2] = sms.dummy; + cpu_writemap[3] = sms.dummy; + cpu_writemap[4] = sms.dummy; + cpu_writemap[5] = sms.dummy; + cpu_writemap[6] = sms.ram; + cpu_writemap[7] = sms.ram; + + sms.fcr[0] = 0x00; + sms.fcr[1] = 0x00; + sms.fcr[2] = 0x01; + sms.fcr[3] = 0x00; +} + + +/* Reset Z80 emulator */ +void cpu_reset(void) +{ + z80_reset(0); + z80_set_irq_callback(sms_irq_callback); +} + + +/* Write to memory */ +void cpu_writemem16(int address, int data) +{ + cpu_writemap[(address >> 13)][(address & 0x1FFF)] = data; + if(address >= 0xFFFC) sms_mapper_w(address & 3, data); +} + + +/* Write to an I/O port */ +void cpu_writeport(int port, int data) +{ + switch(port & 0xFF) + { + case 0x01: /* GG SIO */ + case 0x02: + case 0x03: + case 0x04: + case 0x05: + break; + + case 0x06: /* GG STEREO */ + if(smssnd.log) { + smssnd.callback(0x04); + smssnd.callback(data); + } + sms.psg_mask = (data & 0xFF); + break; + + case 0x7E: /* SN76489 PSG */ + case 0x7F: + if(smssnd.log) { + smssnd.callback(0x03); + smssnd.callback(data); + } + if(smssnd.enabled) SN76496Write(0, data); + break; + + case 0xBE: /* VDP DATA */ + vdp_data_w(data); + break; + + case 0xBD: /* VDP CTRL */ + case 0xBF: + vdp_ctrl_w(data); + break; + + case 0xF0: /* YM2413 */ + case 0xF1: + if(smssnd.log) { + smssnd.callback((port & 1) ? 0x06 : 0x05); + smssnd.callback(data); + } + if(smssnd.enabled && sms.use_fm) ym2413_write(0, port & 1, data); + break; + + case 0xF2: /* YM2413 DETECT */ + if(sms.use_fm) sms.port_F2 = (data & 1); + break; + + case 0x3F: /* TERRITORY CTRL. */ + sms.port_3F = ((data & 0x80) | (data & 0x20) << 1) & 0xC0; + if(sms.country == TYPE_DOMESTIC) sms.port_3F ^= 0xC0; + break; + } +} + + +/* Read from an I/O port */ +int cpu_readport(int port) +{ + byte temp = 0xFF; + + switch(port & 0xFF) + { + case 0x01: /* GG SIO */ + case 0x02: + case 0x03: + case 0x04: + case 0x05: + return (0x00); + + case 0x7E: /* V COUNTER */ + return (vdp_vcounter_r()); + break; + + case 0x7F: /* H COUNTER */ + return (vdp_hcounter_r()); + break; + + case 0x00: /* INPUT #2 */ + temp = 0xFF; + if(input.system & INPUT_START) temp &= ~0x80; + if(sms.country == TYPE_DOMESTIC) temp &= ~0x40; + return (temp); + + case 0xC0: /* INPUT #0 */ + case 0xDC: + temp = 0xFF; + if(input.pad[0] & INPUT_UP) temp &= ~0x01; + if(input.pad[0] & INPUT_DOWN) temp &= ~0x02; + if(input.pad[0] & INPUT_LEFT) temp &= ~0x04; + if(input.pad[0] & INPUT_RIGHT) temp &= ~0x08; + if(input.pad[0] & INPUT_BUTTON2) temp &= ~0x10; + if(input.pad[0] & INPUT_BUTTON1) temp &= ~0x20; + if(input.pad[1] & INPUT_UP) temp &= ~0x40; + if(input.pad[1] & INPUT_DOWN) temp &= ~0x80; + return (temp); + + case 0xC1: /* INPUT #1 */ + case 0xDD: + temp = 0xFF; + if(input.pad[1] & INPUT_LEFT) temp &= ~0x01; + if(input.pad[1] & INPUT_RIGHT) temp &= ~0x02; + if(input.pad[1] & INPUT_BUTTON2) temp &= ~0x04; + if(input.pad[1] & INPUT_BUTTON1) temp &= ~0x08; + if(input.system & INPUT_SOFT_RESET) temp &= ~0x10; + return ((temp & 0x3F) | (sms.port_3F & 0xC0)); + + case 0xBE: /* VDP DATA */ + return (vdp_data_r()); + + case 0xBD: + case 0xBF: /* VDP CTRL */ + return (vdp_ctrl_r()); + + case 0xF2: /* YM2413 DETECT */ + if(sms.use_fm) return (sms.port_F2); + break; + } + return (0xFF); +} + + +void sms_mapper_w(int address, int data) +{ + /* Calculate ROM page index */ + byte page = (data % cart.pages); + + /* Save frame control register data */ + sms.fcr[address] = data; + + switch(address) + { + case 0: + if(data & 8) + { + sms.save = 1; + /* Page in ROM */ + cpu_readmap[4] = &sms.sram[(data & 4) ? 0x4000 : 0x0000]; + cpu_readmap[5] = &sms.sram[(data & 4) ? 0x6000 : 0x2000]; + cpu_writemap[4] = &sms.sram[(data & 4) ? 0x4000 : 0x0000]; + cpu_writemap[5] = &sms.sram[(data & 4) ? 0x6000 : 0x2000]; + } + else + { + /* Page in RAM */ + cpu_readmap[4] = ((sms.fcr[3] % cart.pages) << 14) + 0x0000; + cpu_readmap[5] = ((sms.fcr[3] % cart.pages) << 14) + 0x2000; + cpu_writemap[4] = sms.dummy; + cpu_writemap[5] = sms.dummy; + } + break; + + case 1: + cpu_readmap[0] = (page << 14) + 0x0000; + cpu_readmap[1] = (page << 14) + 0x2000; + break; + + case 2: + cpu_readmap[2] = (page << 14) + 0x0000; + cpu_readmap[3] = (page << 14) + 0x2000; + break; + + case 3: + if(!(sms.fcr[0] & 0x08)) + { + cpu_readmap[4] = (page << 14) + 0x0000; + cpu_readmap[5] = (page << 14) + 0x2000; + } + break; + } +} + + +int sms_irq_callback(int param) +{ + return (0xFF); +} diff --git a/MCUME_teensy/teensysms/sms.h b/MCUME_teensy/teensysms/sms.h new file mode 100644 index 0000000..c938447 --- /dev/null +++ b/MCUME_teensy/teensysms/sms.h @@ -0,0 +1,36 @@ + +#ifndef _SMS_H_ +#define _SMS_H_ + +#define TYPE_OVERSEAS (0) +#define TYPE_DOMESTIC (1) + +/* SMS context */ +typedef struct +{ + byte dummy[0x2000]; + byte ram[0x2000]; + byte sram[0x8000]; + byte fcr[4]; + byte paused; + byte save; + byte country; + byte port_3F; + byte port_F2; + byte use_fm; + byte irq; + byte psg_mask; +}t_sms; + +/* Global data */ +extern t_sms sms; + +/* Function prototypes */ +void sms_frame(int skip_render); +void sms_init(void); +void sms_reset(void); +int sms_irq_callback(int param); +void sms_mapper_w(int address, int data); +void cpu_reset(void); + +#endif /* _SMS_H_ */ diff --git a/MCUME_teensy/teensysms/smslut.h b/MCUME_teensy/teensysms/smslut.h new file mode 100644 index 0000000..affb52d --- /dev/null +++ b/MCUME_teensy/teensysms/smslut.h @@ -0,0 +1,4099 @@ +#include "arduinoproto.h" +PROGMEM const uint8 lut[65536] = { +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, +0x00,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,0x5A,0x5B,0x5C,0x5D,0x5E,0x5F, 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0x3f0) | (data & 0x0f); + switch (r) + { + case 0: /* tone 0 : frequency */ + case 2: /* tone 1 : frequency */ + case 4: /* tone 2 : frequency */ + R->Period[c] = R->UpdateStep * R->Register[r]; + if (R->Period[c] == 0) R->Period[c] = R->UpdateStep; + if (r == 4) + { + /* update noise shift frequency */ + if ((R->Register[6] & 0x03) == 0x03) + R->Period[3] = 2 * R->Period[2]; + } + break; + case 1: /* tone 0 : volume */ + case 3: /* tone 1 : volume */ + case 5: /* tone 2 : volume */ + case 7: /* noise : volume */ + R->Volume[c] = R->VolTable[data & 0x0f]; + break; + case 6: /* noise : frequency, mode */ + { + int n = R->Register[6]; + R->NoiseFB = (n & 4) ? FB_WNOISE : FB_PNOISE; + n &= 3; + /* N/512,N/1024,N/2048,Tone #3 output */ + R->Period[3] = (n == 3) ? 2 * R->Period[2] : (R->UpdateStep << (5+n)); + + /* reset noise shifter */ + R->RNG = NG_PRESET; + R->Output[3] = R->RNG & 1; + } + break; + } + } + else + { + int r = R->LastRegister; + int c = r/2; + + switch (r) + { + case 0: /* tone 0 : frequency */ + case 2: /* tone 1 : frequency */ + case 4: /* tone 2 : frequency */ + R->Register[r] = (R->Register[r] & 0x0f) | ((data & 0x3f) << 4); + R->Period[c] = R->UpdateStep * R->Register[r]; + if (R->Period[c] == 0) R->Period[c] = R->UpdateStep; + if (r == 4) + { + /* update noise shift frequency */ + if ((R->Register[6] & 0x03) == 0x03) + R->Period[3] = 2 * R->Period[2]; + } + break; + } + } +} + + +void SN76496Update(int chip,INT16 *buffer[2],int length, unsigned char mask) +{ + int i, j; + int buffer_index = 0; + t_SN76496 *R = &sn[chip]; + + /* If the volume is 0, increase the counter */ + for (i = 0;i < 4;i++) + { + if (R->Volume[i] == 0) + { + /* note that I do count += length, NOT count = length + 1. You might think */ + /* it's the same since the volume is 0, but doing the latter could cause */ + /* interferencies when the program is rapidly modulating the volume. */ + if (R->Count[i] <= length*STEP) R->Count[i] += length*STEP; + } + } + + while (length > 0) + { + int vol[4]; + unsigned int out[2]; + int left; + + + /* vol[] keeps track of how long each square wave stays */ + /* in the 1 position during the sample period. */ + vol[0] = vol[1] = vol[2] = vol[3] = 0; + + for (i = 0;i < 3;i++) + { + if (R->Output[i]) vol[i] += R->Count[i]; + R->Count[i] -= STEP; + /* Period[i] is the half period of the square wave. Here, in each */ + /* loop I add Period[i] twice, so that at the end of the loop the */ + /* square wave is in the same status (0 or 1) it was at the start. */ + /* vol[i] is also incremented by Period[i], since the wave has been 1 */ + /* exactly half of the time, regardless of the initial position. */ + /* If we exit the loop in the middle, Output[i] has to be inverted */ + /* and vol[i] incremented only if the exit status of the square */ + /* wave is 1. */ + while (R->Count[i] <= 0) + { + R->Count[i] += R->Period[i]; + if (R->Count[i] > 0) + { + R->Output[i] ^= 1; + if (R->Output[i]) vol[i] += R->Period[i]; + break; + } + R->Count[i] += R->Period[i]; + vol[i] += R->Period[i]; + } + if (R->Output[i]) vol[i] -= R->Count[i]; + } + + left = STEP; + do + { + int nextevent; + + + if (R->Count[3] < left) nextevent = R->Count[3]; + else nextevent = left; + + if (R->Output[3]) vol[3] += R->Count[3]; + R->Count[3] -= nextevent; + if (R->Count[3] <= 0) + { + if (R->RNG & 1) R->RNG ^= R->NoiseFB; + R->RNG >>= 1; + R->Output[3] = R->RNG & 1; + R->Count[3] += R->Period[3]; + if (R->Output[3]) vol[3] += R->Period[3]; + } + if (R->Output[3]) vol[3] -= R->Count[3]; + + left -= nextevent; + } while (left > 0); + + out[0] = out[1] = 0; + for(j = 0; j < 4; j += 1) + { + int k = vol[j] * R->Volume[j]; + if(mask & (1 << (4+j))) out[0] += k; + if(mask & (1 << (0+j))) out[1] += k; + } + + if(out[0] > MAX_OUTPUT * STEP) out[0] = MAX_OUTPUT * STEP; + if(out[1] > MAX_OUTPUT * STEP) out[1] = MAX_OUTPUT * STEP; + buffer[0][buffer_index] = out[0] / STEP; + buffer[1][buffer_index] = out[1] / STEP; + + /* Next sample set */ + buffer_index += 1; + + length--; + } +} + + + +void SN76496_set_clock(int chip,int clock) +{ + t_SN76496 *R = &sn[chip]; + + R->UpdateStep = ((double)STEP * R->SampleRate * 16) / clock; +} + + + +void SN76496_set_gain(int chip,int gain) +{ + t_SN76496 *R = &sn[chip]; + int i; + double out; + + gain &= 0xff; + out = MAX_OUTPUT / 3; + while (gain-- > 0) + out *= 1.023292992; + + for (i = 0;i < 15;i++) + { + if (out > MAX_OUTPUT / 3) R->VolTable[i] = MAX_OUTPUT / 3; + else R->VolTable[i] = out; + out /= 1.258925412; + } + + R->VolTable[15] = 0; +} + + + +int SN76496_init(int chip,int clock,int volume,int sample_rate) +{ + int i; + t_SN76496 *R = &sn[chip]; + + R->SampleRate = sample_rate; + SN76496_set_clock(chip,clock); + + for (i = 0;i < 4;i++) R->Volume[i] = 0; + + R->LastRegister = 0; + for (i = 0;i < 8;i+=2) + { + R->Register[i] = 0; + R->Register[i + 1] = 0x0f; /* volume = 0 */ + } + + for (i = 0;i < 4;i++) + { + R->Output[i] = 0; + R->Period[i] = R->Count[i] = R->UpdateStep; + } + R->RNG = NG_PRESET; + R->Output[3] = R->RNG & 1; + + SN76496_set_gain(0, (volume >> 8) & 0xFF); + + return 0; +} diff --git a/MCUME_teensy/teensysms/sn76496.h b/MCUME_teensy/teensysms/sn76496.h new file mode 100644 index 0000000..daff3c9 --- /dev/null +++ b/MCUME_teensy/teensysms/sn76496.h @@ -0,0 +1,30 @@ +#ifndef SN76496_H +#define SN76496_H + +#define MAX_76496 4 + +typedef struct +{ + int Channel; + int SampleRate; + unsigned int UpdateStep; + int VolTable[16]; + int Register[8]; + int LastRegister; + int Volume[4]; + unsigned int RNG; + int NoiseFB; + int Period[4]; + int Count[4]; + int Output[4]; +}t_SN76496; + +extern t_SN76496 sn[MAX_76496]; + +void SN76496Write(int chip,int data); +void SN76496Update(int chip, signed short int *buffer[2],int length,unsigned char mask); +void SN76496_set_clock(int chip,int clock); +void SN76496_set_gain(int chip,int gain); +int SN76496_init(int chip,int clock,int volume,int sample_rate); + +#endif diff --git a/MCUME_teensy/teensysms/system.c b/MCUME_teensy/teensysms/system.c new file mode 100644 index 0000000..5809abc --- /dev/null +++ b/MCUME_teensy/teensysms/system.c @@ -0,0 +1,231 @@ +/* + Copyright (C) 1998, 1999, 2000 Charles Mac Donald + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include "shared.h" + + +t_bitmap sbitmap; +t_cart cart; +t_snd smssnd; +static t_input minput; +FM_OPL *ym3812; + + +void system_init(int rate) +{ + /* Initialize the VDP emulation */ + vdp_init(); + + /* Initialize the SMS emulation */ + sms_init(); + + /* Initialize the look-up tables and related data */ + render_init(); + + /* Enable sound emulation if the sample rate was specified */ + audio_init(rate); + + /* Don't save SRAM by default */ + sms.save = 0; + + /* Clear emulated button state */ + memset(&minput, 0, sizeof(t_input)); +} + + +void audio_init(int rate) +{ + /* Clear sound context */ + memset(&smssnd, 0, sizeof(t_snd)); + + /* Reset logging data */ + smssnd.log = 0; + smssnd.callback = NULL; + + /* Oops.. sound is disabled */ + if(!rate) return; + + /* Calculate buffer size in samples */ + smssnd.bufsize = (rate / 50); + + /* YM3812/YM2413 sound stream */ + smssnd.fm_buffer = (signed short int *)emu_Malloc(smssnd.bufsize * 2); + if(!smssnd.fm_buffer) return; + + /* SN76489 sound stream */ + smssnd.psg_buffer[0] = (signed short int *)emu_Malloc(smssnd.bufsize * 2); + smssnd.psg_buffer[1] = (signed short int *)emu_Malloc(smssnd.bufsize * 2); + if(!smssnd.psg_buffer[0] || !smssnd.psg_buffer[1]) return; + + /* Set up SN76489 emulation */ + SN76496_init(0, MASTER_CLOCK, 255, rate); + + /* Set up YM3812 emulation */ + ym3812 = OPLCreate(OPL_TYPE_YM3812, MASTER_CLOCK, rate); + if(!ym3812) return; + + /* Set up YM2413 emulation */ + ym2413_init(1); + + /* Inform other functions that we can use sound */ + smssnd.enabled = 1; +} + + +void system_shutdown(void) +{ + if(smssnd.enabled) OPLDestroy(ym3812); +} + + +void system_reset(void) +{ + cpu_reset(); + vdp_reset(); + sms_reset(); + render_reset(); +// system_load_sram(); + if(smssnd.enabled) + { + OPLResetChip(ym3812); + ym2413_reset(0); + } +} + + +void system_save_state(void *fd) +{ + /* Save VDP context */ + fwrite(&vdp, sizeof(t_vdp), 1, fd); + + /* Save SMS context */ + fwrite(&sms, sizeof(t_sms), 1, fd); + + /* Save Z80 context */ + fwrite(Z80_Context, sizeof(Z80_Regs), 1, fd); + fwrite(&after_EI, sizeof(int), 1, fd); + + /* Save YM2413 registers */ + fwrite(&ym2413[0].reg[0], 0x40, 1, fd); + + /* Save SN76489 context */ + fwrite(&sn[0], sizeof(t_SN76496), 1, fd); +} + + +void system_load_state(void *fd) +{ + int i; + byte reg[0x40]; + + /* Initialize everything */ + cpu_reset(); + system_reset(); + + /* Load VDP context */ + fread(&vdp, sizeof(t_vdp), 1, fd); + + /* Load SMS context */ + fread(&sms, sizeof(t_sms), 1, fd); + + /* Load Z80 context */ + fread(Z80_Context, sizeof(Z80_Regs), 1, fd); + fread(&after_EI, sizeof(int), 1, fd); + + /* Load YM2413 registers */ + fread(reg, 0x40, 1, fd); + + /* Load SN76489 context */ + fread(&sn[0], sizeof(t_SN76496), 1, fd); + + /* Restore callbacks */ + z80_set_irq_callback(sms_irq_callback); + + cpu_readmap[0] = 0x0000; /* 0000-3FFF */ + cpu_readmap[1] = 0x2000; + cpu_readmap[2] = 0x4000; /* 4000-7FFF */ + cpu_readmap[3] = 0x6000; + cpu_readmap[4] = 0x0000; /* 0000-3FFF */ + cpu_readmap[5] = 0x2000; + cpu_readmap[6] = sms.ram; + cpu_readmap[7] = sms.ram; + + cpu_writemap[0] = sms.dummy; + cpu_writemap[1] = sms.dummy; + cpu_writemap[2] = sms.dummy; + cpu_writemap[3] = sms.dummy; + cpu_writemap[4] = sms.dummy; + cpu_writemap[5] = sms.dummy; + cpu_writemap[6] = sms.ram; + cpu_writemap[7] = sms.ram; + + sms_mapper_w(3, sms.fcr[3]); + sms_mapper_w(2, sms.fcr[2]); + sms_mapper_w(1, sms.fcr[1]); + sms_mapper_w(0, sms.fcr[0]); + + /* Force full pattern cache update */ + sis_vram_dirty = 1; + memset(svram_dirty, 1, 0x200); + + /* Restore palette */ + for(i = 0; i < PALETTE_SIZE; i += 1) + palette_sync(i); + + /* Restore sound state */ + if(smssnd.enabled) + { + /* Restore YM2413 emulation */ + OPLResetChip(ym3812); + + /* Clear YM2413 context */ + ym2413_reset(0); + + /* Restore rhythm enable first */ + ym2413_write(0, 0, 0x0E); + ym2413_write(0, 1, reg[0x0E]); + + /* User instrument settings */ + for(i = 0x00; i <= 0x07; i += 1) + { + ym2413_write(0, 0, i); + ym2413_write(0, 1, reg[i]); + } + + /* Channel frequency */ + for(i = 0x10; i <= 0x18; i += 1) + { + ym2413_write(0, 0, i); + ym2413_write(0, 1, reg[i]); + } + + /* Channel frequency + ctrl. */ + for(i = 0x20; i <= 0x28; i += 1) + { + ym2413_write(0, 0, i); + ym2413_write(0, 1, reg[i]); + } + + /* Instrument and volume settings */ + for(i = 0x30; i <= 0x38; i += 1) + { + ym2413_write(0, 0, i); + ym2413_write(0, 1, reg[i]); + } + } +} diff --git a/MCUME_teensy/teensysms/system.h b/MCUME_teensy/teensysms/system.h new file mode 100644 index 0000000..6b12d7a --- /dev/null +++ b/MCUME_teensy/teensysms/system.h @@ -0,0 +1,92 @@ + +#ifndef _SYSTEM_H_ +#define _SYSTEM_H_ + +#define PALETTE_SIZE (0x20) + +/* Console / cartridge types */ +#define TYPE_SMS (0) +#define TYPE_GG (1) + +#define IS_GG (cart.type == TYPE_GG) +#define IS_SMS (cart.type == TYPE_SMS) + +/* Macro to get offset to actual display within bitmap */ +#define BMP_X_OFFSET ((cart.type == TYPE_GG) ? 48 : 0) +#define BMP_Y_OFFSET ((cart.type == TYPE_GG) ? 24 : 0) + +#define BMP_WIDTH (IS_GG ? 160 : 256) +#define BMP_HEIGHT (IS_GG ? 144 : 192) + +/* Mask for removing unused pixel data */ +#define PIXEL_MASK (0x1F) + +/* These can be used for 'input.pad[]' */ +#define INPUT_UP (0x00000001) +#define INPUT_DOWN (0x00000002) +#define INPUT_LEFT (0x00000004) +#define INPUT_RIGHT (0x00000008) +#define INPUT_BUTTON2 (0x00000010) +#define INPUT_BUTTON1 (0x00000020) + +/* These can be used for 'input.system' */ +#define INPUT_START (0x00000001) /* Game Gear only */ +#define INPUT_PAUSE (0x00000002) /* Master System only */ +#define INPUT_SOFT_RESET (0x00000004) /* Master System only */ +#define INPUT_HARD_RESET (0x00000008) /* Works for either console type */ + +/* User input structure */ +typedef struct +{ + int pad[2]; + int system; +}t_input; + +/* Sound emulation structure */ +typedef struct +{ + int enabled; + int bufsize; + signed short *fm_buffer; /* internal use only */ + signed short *psg_buffer[2]; /* internal use only */ + int log; + void (*callback)(int data); +}t_snd; + +/* Game image structure */ +typedef struct +{ + //byte *rom; + byte pages; + byte type; +}t_cart; + +/* Bitmap structure */ +typedef struct +{ + struct + { + byte color[32][3]; + byte dirty[32]; + byte update; + }pal; +}t_bitmap; + +/* Global variables */ +extern t_bitmap sbitmap; /* Display bitmap */ +extern t_snd smssnd; /* Sound streams */ +extern t_cart cart; /* Game cartridge data */ +extern t_input input; /* Controller input */ +extern FM_OPL *ym3812; /* YM3812 emulator data */ + +/* Function prototypes */ +void system_init(int rate); +void system_shutdown(void); +void system_reset(void); +void system_load_sram(void); +void system_save_state(void *fd); +void system_load_state(void *fd); +void audio_init(int rate); +void audio_play_sample(int16 *bufl, int16 *bufr, int length); + +#endif /* _SYSTEM_H_ */ diff --git a/MCUME_teensy/teensysms/teensysms.ino b/MCUME_teensy/teensysms/teensysms.ino new file mode 100644 index 0000000..fad38d6 --- /dev/null +++ b/MCUME_teensy/teensysms/teensysms.ino @@ -0,0 +1,279 @@ +#include "iopins.h" +#include "emuapi.h" + +#include "keyboard_osd.h" +#include "tft_t_dma.h" + +#include "emu.h" + +#ifdef HAS_VGA +#include +uVGA uvga; +#if F_CPU == 144000000 +#define UVGA_144M_326X240 +#define UVGA_XRES 326 +#define UVGA_YRES 240 +#define UVGA_XRES_EXTRA 10 +#elif F_CPU == 180000000 +#define UVGA_180M_360X300 +#define UVGA_XRES 360 +#define UVGA_YRES 300 +#define UVGA_XRES_EXTRA 8 +#elif F_CPU == 240000000 +#define UVGA_240M_452X240 +#define UVGA_XRES 452 +#define UVGA_YRES 240 +#define UVGA_XRES_EXTRA 12 +#else +#error Please select F_CPU=240MHz or F_CPU=180MHz or F_CPU=144MHz +#endif + +#include + +uint8_t * VGA_frame_buffer; +#endif + +TFT_T_DMA tft = TFT_T_DMA(TFT_CS, TFT_DC, TFT_RST, TFT_MOSI, TFT_SCLK, TFT_MISO, TFT_TOUCH_CS, TFT_TOUCH_INT); + +bool vgaMode = false; + +static unsigned char palette8[PALETTE_SIZE]; +static unsigned short palette16[PALETTE_SIZE]; +static IntervalTimer myTimer; +volatile boolean vbl=true; +static int skip=0; +static elapsedMicros tius; + +static void vblCount() { + if (vbl) { + vbl = false; + } else { + vbl = true; + } +} + +void emu_SetPaletteEntry(unsigned char r, unsigned char g, unsigned char b, int index) +{ + if (index +#include "AudioPlaySystem.h" + +AudioPlaySystem mymixer; +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) +AudioOutputMQS mqs; +AudioConnection patchCord9(mymixer, 0, mqs, 1); +#else +AudioOutputAnalog dac1; +AudioConnection patchCord1(mymixer, dac1); +#endif + +void emu_sndInit() { + Serial.println("sound init"); + AudioMemory(16); + mymixer.start(); +} + +void emu_sndPlaySound(int chan, int volume, int freq) +{ + if (chan < 6) { + mymixer.sound(chan, freq, volume); + } + /* + Serial.print(chan); + Serial.print(":" ); + Serial.print(volume); + Serial.print(":" ); + Serial.println(freq); + */ +} + +void emu_sndPlayBuzz(int size, int val) { + mymixer.buzz(size,val); + //Serial.print((val==1)?1:0); + //Serial.print(":"); + //Serial.println(size); +} +#endif diff --git a/MCUME_teensy/teensysms/tft_t_dma.cpp b/MCUME_teensy/teensysms/tft_t_dma.cpp new file mode 100644 index 0000000..33c4d32 --- /dev/null +++ b/MCUME_teensy/teensysms/tft_t_dma.cpp @@ -0,0 +1,1182 @@ +/* + Based on C64 ILI9341 dma driver from Frank Bösing, 2017 +*/ + +#include "TFT_T_DMA.h" +#include "font8x8.h" + +//#define SPICLOCK 144e6 //Just a number..max speed +#define SPICLOCK 60000000 +#ifdef ILI9341 +#define SPI_MODE SPI_MODE0 +#endif +#ifdef ST7789 +#define SPI_MODE SPI_MODE2 +#endif + +// touch +#define SPI_SETTING SPISettings(2500000, MSBFIRST, SPI_MODE) +#define XPT2046_CFG_START _BV(7) +#define XPT2046_CFG_MUX(v) ((v&0b111) << (4)) +#define XPT2046_CFG_8BIT _BV(3) +#define XPT2046_CFG_12BIT (0) +#define XPT2046_CFG_SER _BV(2) +#define XPT2046_CFG_DFR (0) +#define XPT2046_CFG_PWR(v) ((v&0b11)) +#define XPT2046_MUX_Y 0b101 +#define XPT2046_MUX_X 0b001 +#define XPT2046_MUX_Z1 0b011 +#define XPT2046_MUX_Z2 0b100 + + +#ifdef TFT_STATICFB +static uint16_t fb0[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t fb1[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t fb2[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t fb3[LINES_PER_BLOCK*TFT_WIDTH]; +static uint16_t * blocks[NR_OF_BLOCK]={fb0,fb1,fb2,fb3}; +#else +static uint16_t * blocks[NR_OF_BLOCK]; +#endif + + +static DMASetting dmasettings[SCREEN_DMA_NUM_SETTINGS]; +static DMAChannel dmatx;//(false); +static volatile uint8_t rstop = 0; +static volatile bool cancelled = false; +static volatile uint8_t curTransfer = 0; +static uint8_t nbTransfer = 0; + + +PROGMEM static const uint8_t init_commands[] = { +#ifdef ILI9341 + 4, 0xEF, 0x03, 0x80, 0x02, + 4, 0xCF, 0x00, 0XC1, 0X30, + 5, 0xED, 0x64, 0x03, 0X12, 0X81, + 4, 0xE8, 0x85, 0x00, 0x78, + 6, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02, + 2, 0xF7, 0x20, + 3, 0xEA, 0x00, 0x00, + 2, ILI9341_PWCTR1, 0x23, // Power control + 2, ILI9341_PWCTR2, 0x10, // Power control + 3, ILI9341_VMCTR1, 0x3e, 0x28, // VCM control + 2, ILI9341_VMCTR2, 0x86, // VCM control2 + 2, ILI9341_MADCTL, 0x48, // Memory Access Control + 2, ILI9341_PIXFMT, 0x55, + 3, ILI9341_FRMCTR1, 0x00, 0x18, + 4, ILI9341_DFUNCTR, 0x08, 0x82, 0x27, // Display Function Control + 2, 0xF2, 0x00, // Gamma Function Disable + 2, ILI9341_GAMMASET, 0x01, // Gamma curve selected + 16, ILI9341_GMCTRP1, 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08, + 0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00, // Set Gamma + 16, ILI9341_GMCTRN1, 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07, + 0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F, // Set Gamma +// 3, 0xb1, 0x00, 0x1f, // FrameRate Control 61Hz + 3, 0xb1, 0x00, 0x10, // FrameRate Control 119Hz + 2, ILI9341_MADCTL, ILI9341_MADCTL_MX | ILI9341_MADCTL_MY | ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR, + 0 +#endif +#ifdef ST7789 +#define DELAY 0x80 + 9, // 9 commands in list: + ST7735_SWRESET, DELAY, // 1: Software reset, no args, w/delay + 150, // 150 ms delay + ST7735_SLPOUT , DELAY, // 2: Out of sleep mode, no args, w/delay + 255, // 255 = 500 ms delay + ST7735_COLMOD , 1+DELAY, // 3: Set color mode, 1 arg + delay: + 0x55, // 16-bit color + 10, // 10 ms delay + ST7735_MADCTL , 1 , // 4: Memory access ctrl (directions), 1 arg: + 0x08, // Row addr/col addr, bottom to top refresh + ST7735_CASET , 4 , // 5: Column addr set, 4 args, no delay: + 0x00, + 0x00, // XSTART = 0 + 0x00, + 240, // XEND = 240 + ST7735_RASET , 4 , // 6: Row addr set, 4 args, no delay: + 0x00, + 0x00, // YSTART = 0 + 320>>8, + 320 & 0xFF, // YEND = 320 + ST7735_INVON , DELAY, // 7: hack + 10, + ST7735_NORON , DELAY, // 8: Normal display on, no args, w/delay + 10, // 10 ms delay + ST7735_DISPON , DELAY, // 9: Main screen turn on, no args, w/delay + 255 +#endif +}; + + +static void dmaInterrupt() { + dmatx.clearInterrupt(); + curTransfer++; + if (curTransfer >= nbTransfer) { + curTransfer = 0; + if (cancelled) { + dmatx.disable(); + rstop = 1; + } + } +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) + arm_dcache_flush(blocks[curTransfer], LINES_PER_BLOCK*TFT_WIDTH*2); +#endif +} + +static void setDmaStruct() { + uint32_t remaining = TFT_HEIGHT*TFT_WIDTH*2; + int i=0; + uint16_t col=RGBVAL16(0x00,0x00,0x00);; + while (remaining > 0) { + uint16_t * fb = blocks[i]; + int32_t len = (remaining >= (LINES_PER_BLOCK*TFT_WIDTH*2)?LINES_PER_BLOCK*TFT_WIDTH*2:remaining); +#ifdef TFT_DEBUG + Serial.println((unsigned long)blocks[i]); + Serial.println(remaining); +#endif + switch (i) { + case 0: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb0[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0x00,0xff,0x00); +#endif + break; + case 1: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb1[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0x00,0xff,0xff); +#endif + break; + case 2: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb2[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0x00,0x00,0xff); +#endif + break; + case 3: + if (fb == 0) fb = (uint16_t*)((int)malloc(len+64)&0xffffffe0); + //fb=&fb3[0]; +#ifdef TFT_DEBUG + col = RGBVAL16(0xff,0x00,0xff); +#endif + break; + } + blocks[i] = fb; + if (blocks[i] == 0) { + Serial.print("ILI9341 allocaltion failed for block "); + Serial.println(i); + delay(10000); + } + + for (int j=0;jATTR_DST = 1; +#else + dmasettings[i].sourceBuffer(fb, len); + dmasettings[i].destination((uint8_t &) SPI0_PUSHR); + dmasettings[i].TCD->ATTR_DST = 1; +#endif + dmasettings[i].replaceSettingsOnCompletion(dmasettings[i+1]); + dmasettings[i].interruptAtCompletion(); + remaining -= len; + i++; + } + dmasettings[i-1].replaceSettingsOnCompletion(dmasettings[0]); + nbTransfer = i; +#ifdef TFT_DEBUG + Serial.println(nbTransfer); +#endif +} + + +TFT_T_DMA::TFT_T_DMA(uint8_t cs, uint8_t dc, uint8_t rst, uint8_t mosi, uint8_t sclk, uint8_t miso, uint8_t touch_cs, uint8_t touch_irq) +{ + _cs = cs; + _dc = dc; + _rst = rst; + _mosi = mosi; + _sclk = sclk; + _miso = miso; + pinMode(_dc, OUTPUT); + pinMode(_cs, OUTPUT); + digitalWrite(_cs, 1); + digitalWrite(_dc, 1); + if ( (touch_cs != 255) && (touch_irq != 255) ) { + _touch_irq = touch_irq; + _touch_cs = touch_cs; + pinMode(_touch_cs, OUTPUT); + pinMode(touch_irq, INPUT_PULLUP); + digitalWrite(_touch_cs, 1); + } +} + + +void TFT_T_DMA::setArea(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2) { + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + + digitalWrite(_dc, 0); + SPI.transfer(TFT_CASET); + digitalWrite(_dc, 1); + SPI.transfer16(x1); + SPI.transfer16(x2); + + digitalWrite(_dc, 0); + SPI.transfer(TFT_PASET); + digitalWrite(_dc, 1); + SPI.transfer16(y1); + SPI.transfer16(y2); + + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + digitalWrite(_dc, 1); + + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + + +void TFT_T_DMA::begin(void) { + SPI.setMOSI(_mosi); + SPI.setMISO(_miso); + SPI.setSCK(_sclk); + SPI.begin(); + + // Initialize display + if (_rst < 255) { // toggle RST low to reset + pinMode(_rst, OUTPUT); + digitalWrite(_rst, HIGH); + delay(5); + digitalWrite(_rst, LOW); + delay(20); + digitalWrite(_rst, HIGH); + delay(120); + } + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + const uint8_t *addr = init_commands; + digitalWrite(_cs, 0); +#ifdef ILI9341 + while (1) { + uint8_t count = *addr++; + if (count-- == 0) break; + + digitalWrite(_dc, 0); + SPI.transfer(*addr++); + + while (count-- > 0) { + digitalWrite(_dc, 1); + SPI.transfer(*addr++); + } + } + + digitalWrite(_dc, 0); + SPI.transfer(ILI9341_SLPOUT); + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + SPI.endTransaction(); + + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + SPI.endTransaction(); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_dc, 0); + digitalWrite(_cs, 0); + SPI.transfer(ILI9341_DISPON); + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + SPI.endTransaction(); +#endif +#ifdef ST7789 + uint8_t numCommands, numArgs; + uint16_t ms; + numCommands = *addr++; // Number of commands to follow + while(numCommands--) { // For each command... + digitalWrite(_dc, 0); + SPI.transfer(*addr++); + numArgs = *addr++; // Number of args to follow + ms = numArgs & DELAY; // If hibit set, delay follows args + numArgs &= ~DELAY; // Mask out delay bit + while(numArgs > 1) { // For each argument... + digitalWrite(_dc, 1); + SPI.transfer(*addr++); + numArgs--; + } + + if (numArgs) { + digitalWrite(_dc, 1); + SPI.transfer(*addr++); + } + if(ms) { + ms = *addr++; // Read post-command delay time (ms) + if(ms == 255) ms = 500; // If 255, delay for 500 ms + SPI.endTransaction(); + digitalWrite(_dc, 1); + digitalWrite(_cs, 1); + delay(ms); + //beginSPITransaction(); + } + } +#endif + + setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1); + + cancelled = false; +#ifdef FLIP_SCREEN + flipscreen(true); +#else + flipscreen(false); +#endif +}; + + + +void TFT_T_DMA::flipscreen(bool flip) +{ + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_dc, 0); + digitalWrite(_cs, 0); + SPI.transfer(TFT_MADCTL); + digitalWrite(_dc, 1); + if (flip) { + flipped=true; +#ifdef ILI9341 + SPI.transfer(ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR); +#endif +#ifdef ST7789 + //SPI.transfer(ST77XX_MADCTL_RGB); + SPI.transfer(ST77XX_MADCTL_MV | ST77XX_MADCTL_RGB); +#endif + } + else { + flipped=false; +#ifdef ILI9341 + SPI.transfer(ILI9341_MADCTL_MX | ILI9341_MADCTL_MY | ILI9341_MADCTL_MV | ILI9341_MADCTL_BGR); +#endif +#ifdef ST7789 + SPI.transfer(ST77XX_MADCTL_MX | ST77XX_MADCTL_MV | ST77XX_MADCTL_RGB); +#endif + } + digitalWrite(_cs, 1); + SPI.endTransaction(); +} + +boolean TFT_T_DMA::isflipped(void) +{ + return(flipped); +} + + +#define PRREG(x) Serial.print(#x" 0x"); Serial.println(x,HEX) + + +void TFT_T_DMA::startDMA(void) { + curTransfer = 0; + rstop = 0; + //dmatx.begin(true); + dmatx.attachInterrupt(dmaInterrupt); + setDmaStruct(); + setArea((TFT_REALWIDTH-TFT_WIDTH)/2, (TFT_REALHEIGHT-TFT_HEIGHT)/2, (TFT_REALWIDTH-TFT_WIDTH)/2 + TFT_WIDTH-1, (TFT_REALHEIGHT-TFT_HEIGHT)/2+TFT_HEIGHT-1); + fillScreen(RGBVAL16(0x00,0x00,0x00)); + + digitalWrite(_cs, HIGH); + SPI.begin(); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE0)); +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) + +#ifdef TFT_DEBUG + PRREG(LPSPI4_CCR); + PRREG(LPSPI4_TCR); + PRREG(LPSPI4_FCR); + Serial.printf("SPI CLOCK %d CCR freq %.1f MHz\n", SPICLOCK, 528. / 7 / ((0xff & LPSPI4_CCR) + 2)); +#endif + LPSPI4_CR &= ~LPSPI_CR_MEN;//disable LPSPI: + LPSPI4_CFGR1 |= LPSPI_CFGR1_NOSTALL; //prevent stall from RX + LPSPI4_TCR = 15; // Framesize 16 Bits + //LPSPI4_FCR = 0; // Fifo Watermark + LPSPI4_DER = LPSPI_DER_TDDE; //TX DMA Request Enable + LPSPI4_CR |= LPSPI_CR_MEN; //enable LPSPI: + dmatx.triggerAtHardwareEvent( DMAMUX_SOURCE_LPSPI4_TX ); +#else + SPI0_RSER |= SPI_RSER_TFFF_DIRS | SPI_RSER_TFFF_RE; // Set ILI_DMA Interrupt Request Select and Enable register + SPI0_MCR &= ~SPI_MCR_HALT; //Start transfers. + SPI0_CTAR0 = SPI0_CTAR1; + (*(volatile uint16_t *)((int)&SPI0_PUSHR + 2)) = (SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT) >> 16; //Enable 16 Bit Transfers + Continue-Bit + dmatx.triggerAtHardwareEvent(DMAMUX_SOURCE_SPI0_TX ); +#endif + dmatx = dmasettings[0]; + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + digitalWrite(_dc, 1); + dmatx.enable(); +} + + +void TFT_T_DMA::stopDMA(void) { + rstop = 0; + wait(); + delay(50); + cancelled = false; + dmatx.detachInterrupt(); + fillScreen(RGBVAL16(0x00,0x00,0x00)); + SPI.end(); +#ifdef ST7789 + begin(); +#endif +#ifdef ILI9341 + SPI.begin(); + digitalWrite(_cs, 0); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + SPI.endTransaction(); + digitalWrite(_cs, 1); + digitalWrite(_dc, 1); +#endif + setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1); +} + +void TFT_T_DMA::wait(void) { + rstop = 1; + unsigned long m = millis(); + cancelled = true; + while (!rstop) { + if ((millis() - m) > 100) break; + delay(10); + asm volatile("wfi"); + }; + rstop = 0; +} + + +/*********************************************************************************************** + Touch functions + ***********************************************************************************************/ +/* Code based on ... + * + * @file XPT2046.cpp + * @date 19.02.2016 + * @author Markus Sattler + * + * Copyright (c) 2015 Markus Sattler. All rights reserved. + * This file is part of the XPT2046 driver for Arduino. + */ + +#define ADC_MAX 0x0fff + +void TFT_T_DMA::enableTouchIrq() +{ + SPI.beginTransaction(SPI_SETTING); + digitalWrite(_touch_cs, LOW); + const uint8_t buf[4] = { (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y)), 0x00, 0x00, 0x00 }; + SPI.transfer((void*)&buf[0],3); + digitalWrite(_touch_cs, HIGH); + SPI.endTransaction(); +} + +//Default callibration for non flipped +#define TX_MIN 30 +#define TY_MIN 20 +#define TX_MAX 300 +#define TY_MAX 220 + +//Default callibration for flipped +#define TFX_MIN 20 +#define TFY_MIN 25 +#define TFX_MAX 288 +#define TFY_MAX 221 + +static uint16_t txMin; +static uint16_t tyMin; +static uint16_t txMax; +static uint16_t tyMax; + + +void TFT_T_DMA::callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax) { + if ( (xMin >= 0) && (yMin >= 0) && (xMax < 320) && (yMax < 200) ) { + txMin = xMin; + tyMin = yMin; + txMax = xMax; + tyMax = yMax; + } + else { + if (flipped) { + txMin = TFX_MIN; + tyMin = TFY_MIN; + txMax = TFX_MAX; + tyMax = TFY_MAX; + } + else { + txMin = TX_MIN; + tyMin = TY_MIN; + txMax = TX_MAX; + tyMax = TY_MAX; + } + } +} + + +void TFT_T_DMA::readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + if ( TOUCH_ENABLED() ) { + uint16_t x = 0; + uint16_t y = 0; + uint16_t z1 = 0; + uint16_t z2 = 0; + uint8_t i = 0; + int16_t xraw=0, yraw=0; + + SPI.beginTransaction(SPI_SETTING); + digitalWrite(_touch_cs, LOW); + + for(; i < 15; i++) { + // SPI requirer 32bit aliment + uint8_t buf[12] = { + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Y) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_X) | XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z1)| XPT2046_CFG_PWR(3)), 0x00, 0x00, + (XPT2046_CFG_START | XPT2046_CFG_12BIT | XPT2046_CFG_DFR | XPT2046_CFG_MUX(XPT2046_MUX_Z2)| XPT2046_CFG_PWR(3)), 0x00, 0x00 + }; + SPI.transfer(&buf[0], &buf[0], 12); + y += (buf[1] << 8 | buf[2])>>3; + x += (buf[4] << 8 | buf[5])>>3; + z1 += (buf[7] << 8 | buf[8])>>3; + z2 += (buf[10] << 8 | buf[11])>>3; + } + enableTouchIrq(); + + if(i == 0) { + *oX = 0; + *oY = 0; + *oZ = 0; + } + else { + x /= i; + y /= i; + z1 /= i; + z2 /= i; + } + + digitalWrite(_touch_cs, HIGH); + SPI.endTransaction(); + int z = z1 + ADC_MAX - z2; + if (flipped) { + xraw = x; + yraw = y; + } else { + xraw = ADC_MAX - x; + yraw = ADC_MAX - y; + } + xraw=(xraw*TFT_REALWIDTH)/(ADC_MAX+1); + yraw=(yraw*TFT_REALHEIGHT)/(ADC_MAX+1); + + *oX = xraw; + *oY = yraw; + *oZ = z; + } + else + { + *oX = 0; + *oY = 0; + *oZ = 0; + } +} + +void TFT_T_DMA::readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ) { + readRaw(oX,oY,oZ); + // callibrate ... + if(*oX >= txMin) *oX = ((*oX - txMin)*TFT_REALWIDTH)/(txMax-txMin); + if(*oY >= tyMin) *oY = ((*oY - tyMin)*TFT_REALHEIGHT)/(tyMax-tyMin); + //Serial.print(*oX); + //Serial.print(" "); + //Serial.println(*oY); +} + + +/*********************************************************************************************** + No DMA functions + ***********************************************************************************************/ +void TFT_T_DMA::fillScreenNoDma(uint16_t color) { + setArea(0, 0, TFT_REALWIDTH-1, TFT_REALHEIGHT-1); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + int i,j; + for (j=0; j(arx+arw)) || ((x+w)(ary+arh)) || ((y+h) arx) && (x<(arx+arw)) ) { + arw = arw - (x-arx); + arx = arx + (x-arx); + } else { + bmp_offx = arx; + } + if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) { + arw -= (arx+arw-x-w); + } + if ( (y > ary) && (y<(ary+arh)) ) { + arh = arh - (y-ary); + ary = ary + (y-ary); + } else { + bmp_offy = ary; + } + if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) { + arh -= (ary+arh-y-h); + } + } + + setArea(arx, ary, arx+arw-1, ary+arh-1); + + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + + bitmap = bitmap + bmp_offy*w + bmp_offx; + for (int row=0;row> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + } + bits = *charpt++; + digitalWrite(_dc, 1); + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + bits = bits >> 1; + if (bits&0x01) SPI.transfer16(fgcolor); + else SPI.transfer16(bgcolor); + } + x +=8; +#ifdef ILI9341 + digitalWrite(_dc, 0); + SPI.transfer(ILI9341_SLPOUT); + digitalWrite(_dc, 1); +#endif + digitalWrite(_cs, 1); + SPI.endTransaction(); + } + + setArea(0, 0, (TFT_REALWIDTH-1), (TFT_REALHEIGHT-1)); +} + + +void TFT_T_DMA::drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color) { + setArea(x,y,x+w-1,y+h-1); + SPI.beginTransaction(SPISettings(SPICLOCK, MSBFIRST, SPI_MODE)); + digitalWrite(_cs, 0); + digitalWrite(_dc, 0); + SPI.transfer(TFT_RAMWR); + int i; + for (i=0; i<(w*h); i++) + { + digitalWrite(_dc, 1); + SPI.transfer16(color); + } +#ifdef ILI9341 + digitalWrite(_dc, 0); + SPI.transfer(ILI9341_SLPOUT); + digitalWrite(_dc, 1); +#endif + digitalWrite(_cs, 1); + SPI.endTransaction(); + + setArea(0, 0, (TFT_REALWIDTH-1), (TFT_REALHEIGHT-1)); +} + + + +/*********************************************************************************************** + DMA functions + ***********************************************************************************************/ +uint16_t * TFT_T_DMA::getLineBuffer(int j) +{ + uint16_t * block=blocks[j>>6]; + return(&block[(j&0x3F)*TFT_REALWIDTH]); +} + +void TFT_T_DMA::writeScreen(int width, int height, int stride, uint8_t *buf, uint16_t *palette16) { + uint8_t *buffer=buf; + uint8_t *src; + + int i,j,y=0; + if (width*2 <= TFT_REALWIDTH) { + for (j=0; j>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*TFT_WIDTH]; + src=buffer; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH+(TFT_WIDTH-width)/2]; + src=buffer; + for (i=0; i>6]; + dst=&block[(y&0x3F)*TFT_WIDTH+(TFT_WIDTH-width)/2]; + src=buffer; + for (i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH]; + if (width > TFT_WIDTH) { +#ifdef TFT_LINEARINT + int delta = (width/(width-TFT_WIDTH))-1; + int pos = delta; + for (int i=0; i> 8]&PAL_COLOR_MASK]; + pos +=step; + } +#endif + } + else if ((width*2) == TFT_WIDTH) { + for (int i=0; i>6]; + uint16_t * dst=&block[(y&0x3F)*TFT_WIDTH]; + if (width > TFT_WIDTH) { +#ifdef TFT_LINEARINT + int delta = (width/(width-TFT_WIDTH))-1; + int pos = delta; + for (int i=0; i> 8]; + pos +=step; + } +#endif + } + else if ((width*2) == TFT_WIDTH) { + for (int i=0; i>6]; + uint16_t * dst=&block[(j&0x3F)*TFT_WIDTH]; + for (i=0; i>6]; + uint16_t * dst=&block[(l&0x3F)*TFT_WIDTH+x]; + for (i=0; i>6]; + dst=&block[(l&0x3F)*TFT_WIDTH+x]; + bits = *charpt; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + block=blocks[l>>6]; + dst=&block[(l&0x3F)*TFT_WIDTH+x]; + bits = *charpt++; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + bits = bits >> 1; + if (bits&0x01) *dst++=fgcolor; + else *dst++=bgcolor; + l++; + } + x +=8; + } +} + +void TFT_T_DMA::drawSprite(int16_t x, int16_t y, const uint16_t *bitmap) { + drawSprite(x,y,bitmap, 0,0,0,0); +} + +void TFT_T_DMA::drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t arx, uint16_t ary, uint16_t arw, uint16_t arh) +{ + int bmp_offx = 0; + int bmp_offy = 0; + uint16_t *bmp_ptr; + + int w =*bitmap++; + int h = *bitmap++; + + + if ( (arw == 0) || (arh == 0) ) { + // no crop window + arx = x; + ary = y; + arw = w; + arh = h; + } + else { + if ( (x>(arx+arw)) || ((x+w)(ary+arh)) || ((y+h) arx) && (x<(arx+arw)) ) { + arw = arw - (x-arx); + arx = arx + (x-arx); + } else { + bmp_offx = arx; + } + if ( ((x+w) > arx) && ((x+w)<(arx+arw)) ) { + arw -= (arx+arw-x-w); + } + if ( (y > ary) && (y<(ary+arh)) ) { + arh = arh - (y-ary); + ary = ary + (y-ary); + } else { + bmp_offy = ary; + } + if ( ((y+h) > ary) && ((y+h)<(ary+arh)) ) { + arh -= (ary+arh-y-h); + } + } + + + int l=ary; + bitmap = bitmap + bmp_offy*w + bmp_offx; + for (int row=0;row>6]; + uint16_t * dst=&block[(l&0x3F)*TFT_WIDTH+arx]; + bmp_ptr = (uint16_t*)bitmap; + for (int col=0;col +#include +#include +#endif + +#include "tft_t_dma_config.h" + +#define RGBVAL32(r,g,b) ( (r<<16) | (g<<8) | b ) +#define RGBVAL16(r,g,b) ( (((r>>3)&0x1f)<<11) | (((g>>2)&0x3f)<<5) | (((b>>3)&0x1f)<<0) ) +#define RGBVAL8(r,g,b) ( (((r>>5)&0x07)<<5) | (((g>>5)&0x07)<<2) | (((b>>6)&0x3)<<0) ) +#define R16(rgb) ((rgb>>8)&0xf8) +#define G16(rgb) ((rgb>>3)&0xfc) +#define B16(rgb) ((rgb<<3)&0xf8) + +#define PAL_COLOR_MASK 0x1f + +#define TFT_HEIGHT 192 + +#ifdef ILI9341 +#define TFT_WIDTH 256 +#define TFT_REALWIDTH 320 +#define TFT_REALHEIGHT 240 +#endif +#ifdef ST7789 +#define TFT_WIDTH 240 +#define TFT_REALWIDTH 240 +#define TFT_REALHEIGHT 240 +#endif + +#define LINES_PER_BLOCK 64 +#define NR_OF_BLOCK 4 +#define SCREEN_DMA_NUM_SETTINGS NR_OF_BLOCK + + +#ifdef ILI9341 + +#define ILI9341_NOP 0x00 +#define ILI9341_SWRESET 0x01 +#define ILI9341_RDDID 0x04 +#define ILI9341_RDDST 0x09 + +#define ILI9341_SLPIN 0x10 +#define ILI9341_SLPOUT 0x11 +#define ILI9341_PTLON 0x12 +#define ILI9341_NORON 0x13 + +#define ILI9341_RDMODE 0x0A +#define ILI9341_RDMADCTL 0x0B +#define ILI9341_RDPIXFMT 0x0C +#define ILI9341_RDIMGFMT 0x0D +#define ILI9341_RDSELFDIAG 0x0F + +#define ILI9341_INVOFF 0x20 +#define ILI9341_INVON 0x21 +#define ILI9341_GAMMASET 0x26 +#define ILI9341_DISPOFF 0x28 +#define ILI9341_DISPON 0x29 + +#define ILI9341_CASET 0x2A +#define ILI9341_PASET 0x2B +#define ILI9341_RAMWR 0x2C +#define ILI9341_RAMRD 0x2E + +#define ILI9341_PTLAR 0x30 +#define ILI9341_MADCTL 0x36 +#define ILI9341_VSCRSADD 0x37 +#define ILI9341_PIXFMT 0x3A + +#define ILI9341_FRMCTR1 0xB1 +#define ILI9341_FRMCTR2 0xB2 +#define ILI9341_FRMCTR3 0xB3 +#define ILI9341_INVCTR 0xB4 +#define ILI9341_DFUNCTR 0xB6 + +#define ILI9341_PWCTR1 0xC0 +#define ILI9341_PWCTR2 0xC1 +#define ILI9341_PWCTR3 0xC2 +#define ILI9341_PWCTR4 0xC3 +#define ILI9341_PWCTR5 0xC4 +#define ILI9341_VMCTR1 0xC5 +#define ILI9341_VMCTR2 0xC7 + +#define ILI9341_RDID1 0xDA +#define ILI9341_RDID2 0xDB +#define ILI9341_RDID3 0xDC +#define ILI9341_RDID4 0xDD + +#define ILI9341_GMCTRP1 0xE0 +#define ILI9341_GMCTRN1 0xE1 + +#define ILI9341_MADCTL_MY 0x80 +#define ILI9341_MADCTL_MX 0x40 +#define ILI9341_MADCTL_MV 0x20 +#define ILI9341_MADCTL_ML 0x10 +#define ILI9341_MADCTL_RGB 0x00 +#define ILI9341_MADCTL_BGR 0x08 +#define ILI9341_MADCTL_MH 0x04 + +#define TFT_CASET ILI9341_CASET +#define TFT_PASET ILI9341_PASET +#define TFT_RAMWR ILI9341_RAMWR +#define TFT_MADCTL ILI9341_MADCTL + +#endif + + +#ifdef ST7789 + +#define ST7735_NOP 0x00 +#define ST7735_SWRESET 0x01 +#define ST7735_RDDID 0x04 +#define ST7735_RDDST 0x09 + +#define ST7735_SLPIN 0x10 +#define ST7735_SLPOUT 0x11 +#define ST7735_PTLON 0x12 +#define ST7735_NORON 0x13 + +#define ST7735_INVOFF 0x20 +#define ST7735_INVON 0x21 +#define ST7735_DISPOFF 0x28 +#define ST7735_DISPON 0x29 +#define ST7735_CASET 0x2A +#define ST7735_RASET 0x2B +#define ST7735_RAMWR 0x2C +#define ST7735_RAMRD 0x2E + +#define ST7735_PTLAR 0x30 +#define ST7735_COLMOD 0x3A +#define ST7735_MADCTL 0x36 + +#define ST7735_FRMCTR1 0xB1 +#define ST7735_FRMCTR2 0xB2 +#define ST7735_FRMCTR3 0xB3 +#define ST7735_INVCTR 0xB4 +#define ST7735_DISSET5 0xB6 + +#define ST7735_PWCTR1 0xC0 +#define ST7735_PWCTR2 0xC1 +#define ST7735_PWCTR3 0xC2 +#define ST7735_PWCTR4 0xC3 +#define ST7735_PWCTR5 0xC4 +#define ST7735_VMCTR1 0xC5 + +#define ST7735_RDID1 0xDA +#define ST7735_RDID2 0xDB +#define ST7735_RDID3 0xDC +#define ST7735_RDID4 0xDD + +#define ST7735_PWCTR6 0xFC + +#define ST7735_GMCTRP1 0xE0 +#define ST7735_GMCTRN1 0xE1 + +#define ST77XX_MADCTL_MY 0x80 +#define ST77XX_MADCTL_MX 0x40 +#define ST77XX_MADCTL_MV 0x20 +#define ST77XX_MADCTL_ML 0x10 +#define ST77XX_MADCTL_RGB 0x00 +#define ST77XX_MADCTL_BGR 0x08 +#define ST77XX_MADCTL_MH 0x04 + +#define TFT_CASET ST7735_CASET +#define TFT_PASET ST7735_RASET +#define TFT_RAMWR ST7735_RAMWR +#define TFT_MADCTL ST7735_MADCTL + +#endif + + + +#ifdef __cplusplus + +class TFT_T_DMA +{ + public: + TFT_T_DMA(uint8_t _CS, uint8_t _DC, uint8_t _RST = 255, uint8_t _MOSI=11, uint8_t _SCLK=13, uint8_t _MISO=12, uint8_t touch_cs=38, uint8_t touch_irq=37); + + void setArea(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2); + void begin(void); + void flipscreen(bool flip); + boolean isflipped(void); + void startDMA(void); + void stopDMA(); + + // Touch screen functions + #define TOUCH_ENABLED() ((_touch_cs != 255) && (_touch_irq != 255)) + bool isTouching(void) { return ((!TOUCH_ENABLED())?false:(digitalRead(_touch_irq) == LOW)); } + void readRaw(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void readCal(uint16_t * oX, uint16_t * oY, uint16_t * oZ); + void callibrateTouch(uint16_t xMin,uint16_t yMin,uint16_t xMax,uint16_t yMax); + + // NoDMA functions + void writeScreenNoDma(const uint16_t *pcolors); + void fillScreenNoDma(uint16_t color); + void drawTextNoDma(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize); + void drawRectNoDma(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color); + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap); + void drawSpriteNoDma(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh); + + // DMA functions + uint16_t * getLineBuffer(int j); + void writeScreen(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int stride, uint8_t *buffer, uint16_t *palette16); + void writeLine(int width, int height, int y, uint16_t *buf); + void fillScreen(uint16_t color); + void drawText(int16_t x, int16_t y, const char * text, uint16_t fgcolor, uint16_t bgcolor, bool doublesize); + void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap); + void drawSprite(int16_t x, int16_t y, const uint16_t *bitmap, uint16_t croparx, uint16_t cropary, uint16_t croparw, uint16_t croparh); + + + protected: + uint8_t _rst, _cs, _dc; + uint8_t _miso, _mosi, _sclk; + uint8_t _touch_irq=255, _touch_cs=255; + bool flipped=false; + + void wait(void); + void enableTouchIrq(); +}; + +#endif +#endif + diff --git a/MCUME_teensy/teensysms/tft_t_dma_config.h b/MCUME_teensy/teensysms/tft_t_dma_config.h new file mode 100644 index 0000000..3006874 --- /dev/null +++ b/MCUME_teensy/teensysms/tft_t_dma_config.h @@ -0,0 +1,10 @@ +//#define ST7789 1 +#define ILI9341 1 +#define TFT_LINEARINT 1 +#define LINEARINT_HACK 1 + +//#define FLIP_SCREEN 1 +//#define TFT_DEBUG 1 +#if defined(__IMXRT1052__) || defined(__IMXRT1062__) +#define TFT_STATICFB 1 +#endif diff --git a/MCUME_teensy/teensysms/vdp.c b/MCUME_teensy/teensysms/vdp.c new file mode 100644 index 0000000..ac056a7 --- /dev/null +++ b/MCUME_teensy/teensysms/vdp.c @@ -0,0 +1,297 @@ +#include "shared.h" + + +/* VDP context */ +t_vdp vdp; + + +/* Return values from the V counter */ +byte vcnt[0x200] = +{ + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, + 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, +}; + +/* Return values from the H counter */ +byte hcnt[0x200] = +{ + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D, 0x5E, 0x5F, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x7F, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, + 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0x9E, 0x9F, + 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, + 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF, + 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, + 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0xDF, + 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, + 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF, +}; + + +/*--------------------------------------------------------------------------*/ + + +/* Initialize VDP emulation */ +void vdp_init(void) +{ + vdp_reset(); +} + + +/* Reset VDP emulation */ +void vdp_reset(void) +{ + memset(&vdp, 0, sizeof(t_vdp)); + vdp.limit = 1; +} + + +/* Write data to the VDP's control port */ +void vdp_ctrl_w(int data) +{ + /* Waiting for the reset of the command? */ + if(vdp.pending == 0) + { + /* Save data for later */ + vdp.latch = data; + + /* Set pending flag */ + vdp.pending = 1; + } + else + { + /* Clear pending flag */ + vdp.pending = 0; + + /* VDP register write */ + if((data & 0xF0) == 0x80) + { + int r = (data & 0x0F); + int d = vdp.latch; + + /* Store register data */ + vdp.reg[r] = d; + + /* Update table addresses */ + vdp.ntab = (vdp.reg[2] << 10) & 0x3800; + vdp.satb = (vdp.reg[5] << 7) & 0x3F00; + + vdp.addr = vdp.code = 0; + } + else + { + /* Extract code bits */ + vdp.code = (data >> 6) & 3; + + /* Make address */ + vdp.addr = (data << 8 | vdp.latch); + + /* Read VRAM for code 0x00 */ + if(vdp.code == 0x00) + { + /* Load buffer with current VRAM byte */ + vdp.buffer = vdp.vram[(vdp.addr & 0x3FFF)]; + + /* Bump address */ + vdp.addr += 1; + } + } + } +} + + +/* Read the status flags */ +int vdp_ctrl_r(void) +{ + /* Save the status flags */ + byte temp = vdp.status; + + /* Clear pending flag */ + vdp.pending = 0; + + /* Clear pending interrupt and sprite collision flags */ + vdp.status &= ~(0x80 | 0x40 | 0x20); + + /* Lower the IRQ line */ + if(sms.irq == 1) + { + sms.irq = 0; + z80_set_irq_line(0, CLEAR_LINE); + } + + /* Return the old status flags */ + return (temp); +} + + +/* Write data to the VDP's data port */ +void vdp_data_w(int data) +{ + int index; + + /* Clear the pending flag */ + vdp.pending = 0; + + switch(vdp.code) + { + case 0: /* VRAM write */ + case 1: /* VRAM write */ + case 2: /* VRAM write */ + + /* Get current address in VRAM */ + index = (vdp.addr & 0x3FFF); + + /* Only update if data is new */ + if(data != vdp.vram[index]) + { + /* Store VRAM byte */ + vdp.vram[index] = data; + + /* Mark patterns as dirty */ + svram_dirty[(index >> 5)] = sis_vram_dirty = 1; + } + break; + + case 3: /* CRAM write */ + if(cart.type == TYPE_GG) + { + index = (vdp.addr & 0x3F); + if(data != vdp.cram[index]) + { + vdp.cram[index] = data; + index = (vdp.addr >> 1) & 0x1F; + palette_sync(index); + } + } + else + { + index = (vdp.addr & 0x1F); + if(data != vdp.cram[index]) + { + vdp.cram[index] = data; + palette_sync(index); + } + } + break; + } + + /* Bump the VRAM address */ + vdp.addr += 1; +} + + +/* Read data from the VDP's data port */ +int vdp_data_r(void) +{ + byte temp = 0; + + /* Clear the pending flag */ + vdp.pending = 0; + + switch(vdp.code) + { + case 0: /* VRAM read */ + case 1: /* VRAM read */ + case 2: /* VRAM read */ + + /* Return the buffered value */ + temp = vdp.buffer; + + /* Get data from the current VRAM address */ + vdp.buffer = vdp.vram[(vdp.addr & 0x3FFF)]; + break; + + case 3: /* Undefined */ + /* Return 'no value' data */ + temp = 0xFF; + break; + } + + /* Bump address register */ + vdp.addr += 1; + return (temp); +} + + +/* Process frame events */ +void vdp_run(void) +{ + if(vdp.line <= 0xC0) + { + if(vdp.line == 0xC0) + { + vdp.status |= 0x80; + } + + if(vdp.line == 0) + { + vdp.left = vdp.reg[10]; + } + + if(vdp.left == 0) + { + vdp.left = vdp.reg[10]; + vdp.status |= 0x40; + } + else + { + vdp.left -= 1; + } + + if((vdp.status & 0x40) && (vdp.reg[0] & 0x10)) + { + sms.irq = 1; + z80_set_irq_line(0, ASSERT_LINE); + } + } + else + { + vdp.left = vdp.reg[10]; + + if((vdp.line < 0xE0) && (vdp.status & 0x80) && (vdp.reg[1] & 0x20)) + { + sms.irq = 1; + z80_set_irq_line(0, ASSERT_LINE); + } + } +} + + +byte vdp_vcounter_r(void) +{ + return (vcnt[(vdp.line & 0x1FF)]); +} + + +byte vdp_hcounter_r(void) +{ + int pixel = (((z80_ICount % CYCLES_PER_LINE) / 4) * 3) * 2; + return (hcnt[((pixel >> 1) & 0x1FF)]); +} diff --git a/MCUME_teensy/teensysms/vdp.h b/MCUME_teensy/teensysms/vdp.h new file mode 100644 index 0000000..4e633e8 --- /dev/null +++ b/MCUME_teensy/teensysms/vdp.h @@ -0,0 +1,45 @@ + +#ifndef _VDP_H_ +#define _VDP_H_ + +/* Display timing (NTSC) */ +#define MASTER_CLOCK (3579545) +#define LINES_PER_FRAME (262) +#define FRAMES_PER_SECOND (60) +#define CYCLES_PER_LINE ((MASTER_CLOCK / FRAMES_PER_SECOND) / LINES_PER_FRAME) + +/* VDP context */ +typedef struct +{ + byte vram[0x4000]; + byte cram[0x40]; + byte reg[0x10]; + byte status; + byte latch; + byte pending; + byte buffer; + byte code; + UINT16 addr; + int ntab; + int satb; + int line; + int left; + byte limit; +}t_vdp; + +/* Global data */ +extern t_vdp vdp; + +/* Function prototypes */ +void vdp_init(void); +void vdp_reset(void); +void vdp_ctrl_w(int data); +int vdp_ctrl_r(void); +byte vdp_vcounter_r(void); +byte vdp_hcounter_r(void); +void vdp_data_w(int data); +int vdp_data_r(void); +void vdp_run(void); + +#endif /* _VDP_H_ */ + diff --git a/MCUME_teensy/teensysms/ym2413.c b/MCUME_teensy/teensysms/ym2413.c new file mode 100644 index 0000000..bd9af27 --- /dev/null +++ b/MCUME_teensy/teensysms/ym2413.c @@ -0,0 +1,397 @@ +/* + Copyright (C) 2000 Charles Mac Donald + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + YM2413 (OPLL) emulator + by Charles Mac Donald + E-mail: cgfm2@hooked.net + WWW: http://cgfm2.emuviews.com + + Change log: + + [061300] + - Fixed bug where channel numbers larger than 9 could be written to + register groups $10-18, $20-28, $30-38. + + [060800] + - Now the YM2413 chip number is passed to the OPL_WRITE macro, + and the user instrument data is stored in the YM2413 context, + both for multiple YM2413 emulation. + + [060100] + - Added alternate instrument table taken from Allegro's 'fm_inst.h'. + - Changed source so it can compile seperately from SMS Plus. + - Added 'ym2413_reset' function and changed ym2413_init. + + Known issues: + + - The sustain on/off flag (bit 5 of register group $20-28) is not + emulated. According to the manual, the release rate is set to + five when this bit is set. + + - The table of fixed instrument values probably need to be compared + against a real YM2413, so they can be hand-tuned. + + - The rhythm instruments sound good, but are too loud. + The same settings are used for channels 7, 8, 9, which can't be right. + + I based the YM2413 emulation on the following documents. If you want + to improve it or make changes, I'd advise reading the following: + + - Yamaha's YMF-272 (OPL-3) programmer's manual. (ymf272.pdf) + (Has useful table of how the operators map to YM3812 registers) + + - Yamaha's YM2413 programmer's manual. (ym2413.lzh) + + - Vladimir Arnost's OPL-3 programmer's guide. (opl3.txt) + (Explains operator allocation in rhythm mode) + + - The YM2413 emulation from MAME. (ym2413.c/2413intf.h) +*/ + +#include "shared.h" + +/* You can replace this to output to another YM3812 emulator + or a perhaps a real OPL-2/OPL-3 sound chip */ +#if USE_ADLIB +#define OPL_WRITE(c,r,d) { outp(0x388+c*2, r); outp(0x389+c*2, d); } +#else +#define OPL_WRITE(c,r,d) OPLWriteReg(ym3812, r, d) +#endif + +/* YM2413 chip contexts */ +t_ym2413 ym2413[MAX_YM2413]; + +/* Fixed instrument settings, from MAME's YM2413 emulation */ +/* This might need some tweaking... */ +unsigned char table[16][11] = +{ + /* 20 23 40 43 60 63 80 83 E0 E3 C0 */ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, +#if 1 /* Instrument settings from MAME */ + { 0x01, 0x22, 0x23, 0x07, 0xF0, 0xF0, 0x07, 0x18, 0x00, 0x00, 0x00 }, + { 0x23, 0x01, 0x68, 0x05, 0xF2, 0x74, 0x6C, 0x89, 0x00, 0x00, 0x00 }, + { 0x13, 0x11, 0x25, 0x00, 0xD2, 0xB2, 0xF4, 0xF4, 0x00, 0x00, 0x00 }, + { 0x22, 0x21, 0x1B, 0x05, 0xC0, 0xA1, 0x18, 0x08, 0x00, 0x00, 0x00 }, + { 0x22, 0x21, 0x2C, 0x03, 0xD2, 0xA1, 0x18, 0x57, 0x00, 0x00, 0x00 }, + { 0x01, 0x22, 0xBA, 0x01, 0xF1, 0xF1, 0x1E, 0x04, 0x00, 0x00, 0x00 }, + { 0x21, 0x21, 0x28, 0x06, 0xF1, 0xF1, 0x6B, 0x3E, 0x00, 0x00, 0x00 }, + { 0x27, 0x21, 0x60, 0x00, 0xF0, 0xF0, 0x0D, 0x0F, 0x00, 0x00, 0x00 }, + { 0x20, 0x21, 0x2B, 0x06, 0x85, 0xF1, 0x6D, 0x89, 0x00, 0x00, 0x00 }, + { 0x01, 0x21, 0xBF, 0x02, 0x53, 0x62, 0x5F, 0xAE, 0x01, 0x00, 0x00 }, + { 0x23, 0x21, 0x70, 0x07, 0xD4, 0xA3, 0x4E, 0x64, 0x01, 0x00, 0x00 }, + { 0x2B, 0x21, 0xA4, 0x07, 0xF6, 0x93, 0x5C, 0x4D, 0x00, 0x00, 0x00 }, + { 0x21, 0x23, 0xAD, 0x07, 0x77, 0xF1, 0x18, 0x37, 0x00, 0x00, 0x00 }, + { 0x21, 0x21, 0x2A, 0x03, 0xF3, 0xE2, 0x29, 0x46, 0x00, 0x00, 0x00 }, + { 0x21, 0x23, 0x37, 0x03, 0xF3, 0xE2, 0x29, 0x46, 0x00, 0x00, 0x00 }, +#else /* Instrument settings from Allegro */ + { 0x31, 0x21, 0x15, 0x09, 0xdd, 0x56, 0x13, 0x26, 0x01, 0x00, 0x08 }, /* Violin */ + { 0x03, 0x11, 0x54, 0x09, 0xf3, 0xf1, 0x9a, 0xe7, 0x01, 0x00, 0x0c }, /* Acoustic Guitar(steel) */ + { 0x21, 0x21, 0x8f, 0x0c, 0xf2, 0xf2, 0x45, 0x76, 0x00, 0x00, 0x08 }, /* Acoustic Grand */ + { 0xe1, 0xe1, 0x46, 0x09, 0x88, 0x65, 0x5f, 0x1a, 0x00, 0x00, 0x00 }, /* Flute */ + { 0x32, 0x21, 0x90, 0x09, 0x9b, 0x72, 0x21, 0x17, 0x00, 0x00, 0x04 }, /* Clarinet */ + { 0x21, 0x21, 0x4b, 0x09, 0xaa, 0x8f, 0x16, 0x0a, 0x01, 0x00, 0x08 }, /* Oboe */ + { 0x21, 0x21, 0x92, 0x0a, 0x85, 0x8f, 0x17, 0x09, 0x00, 0x00, 0x0c }, /* Trumpet */ + { 0x23, 0xb1, 0x93, 0x09, 0x97, 0x55, 0x23, 0x14, 0x01, 0x00, 0x04 }, /* Church Organ */ + { 0x21, 0x21, 0x9b, 0x09, 0x61, 0x7f, 0x6a, 0x0a, 0x00, 0x00, 0x02 }, /* French Horn */ + { 0x71, 0x72, 0x57, 0x09, 0x54, 0x7a, 0x05, 0x05, 0x00, 0x00, 0x0c }, /* Synth Voice */ + { 0x21, 0x36, 0x80, 0x17, 0xa2, 0xf1, 0x01, 0xd5, 0x00, 0x00, 0x08 }, /* Harpsichord */ + { 0x18, 0x81, 0x62, 0x09, 0xf3, 0xf2, 0xe6, 0xf6, 0x00, 0x00, 0x00 }, /* Vibraphone */ + { 0x31, 0x31, 0x8b, 0x09, 0xf4, 0xf1, 0xe8, 0x78, 0x00, 0x00, 0x0a }, /* Synth Bass 1 */ + { 0x21, 0xa2, 0x1e, 0x09, 0x94, 0xc3, 0x06, 0xa6, 0x00, 0x00, 0x02 }, /* Acoustic Bass */ + { 0x03, 0x21, 0x87, 0x89, 0xf6, 0xf3, 0x22, 0xf8, 0x01, 0x00, 0x06 }, /* Electric Guitar(clean) */ +#endif +}; + + +/*--------------------------------------------------------------------------*/ + + +void ym2413_init(int count) +{ + int n; + for(n = 0; n < count; n += 1) + { + /* Reset YM2413 data */ + ym2413_reset(n); + } +} + + +void ym2413_reset(int chip) +{ + int n; + + /* Point to current YM2413 context */ + t_ym2413 *opll = &ym2413[chip]; + + /* Clear channel data context */ + memset(opll, 0, sizeof(t_ym2413)); + + /* Clear all YM3812 registers */ + for(n = 0; n < 0x100; n += 1) + { + OPL_WRITE(chip, n, 0x00); + } + + /* Turn off rhythm mode and key-on bits */ + opll->rhythm = 0; + OPL_WRITE(chip, 0xBD, 0x00); + + /* Enable waveform select */ + OPL_WRITE(chip, 0x01, 0x20); +} + + +void ym2413_write(int chip, int address, int data) +{ + /* Point to current YM2413 context */ + t_ym2413 *opll = &ym2413[chip]; + + if(address & 1) /* Data port */ + { + /* Store register data */ + opll->reg[opll->latch] = data; + + switch(opll->latch & 0x30) + { + case 0x00: /* User instrument registers */ + switch(opll->latch & 0x0F) + { + case 0x00: /* Misc. ctrl. (modulator) */ + case 0x01: /* Misc. ctrl. (carrier) */ + case 0x02: /* Key scale level and total level (modulator) */ + case 0x04: /* Attack / Decay (modulator) */ + case 0x05: /* Attack / Decay (carrier) */ + case 0x06: /* Sustain / Release (modulator) */ + case 0x07: /* Sustain / Release (carrier) */ + opll->user[(opll->latch & 0x07)] = data; + break; + + case 0x03: /* Key scale level, carrier/modulator waveform, feedback */ + + /* Key scale level (carrier) */ + /* Don't touch the total level (channel volume) */ + opll->user[3] = (opll->user[3] & 0x3F) | (data & 0xC0); + + /* Waveform select for the modulator */ + opll->user[8] = (data >> 3) & 1; + + /* Waveform select for the carrier */ + opll->user[9] = (data >> 4) & 1; + + /* Store feedback level in YM3812 format */ + opll->user[10] = ((data & 0x07) << 1) & 0x0E; + break; + + case 0x0E: /* Rhythm enable and key-on bits */ + if((data & 0x20) && (opll->rhythm == 0)) + { + opll->rhythm = 1; + rhythm_mode_init(chip); + } + else + { + opll->rhythm = 0; + } + OPL_WRITE(chip, 0xBD, (data & 0x3F)); + break; + } + + /* If the user instrument registers were accessed, then + go through each channel and update the ones that were + currently using the user instrument. We can skip the + last three channels in rhythm mode since they can + only use percussion sounds anyways. */ + if(opll->latch <= 0x07) + { + int x; + for(x = 0; x < ((opll->reg[0x0E] & 0x20) ? 6 : 9); x += 1) + if(opll->channel[x].instrument == 0x00) + load_instrument(chip, x, 0x00, opll->channel[x].volume); + } + break; + + case 0x10: /* Channel Frequency (LSB) */ + case 0x20: /* Channel Frequency (MSB) + key-on and sustain control */ + { + int block; + int frequency; + int ch = (opll->latch & 0x0F); + + /* Ensure proper channel range */ + if(ch > 0x08) break; + + /* Get YM2413 channel frequency */ + frequency = ((opll->reg[0x10 + ch] & 0xFF) | ((opll->reg[0x20 + ch] & 0x01) << 8)); + + /* Scale 9 bit frequency to 10 bits */ + frequency = (frequency << 1) & 0x1FFF; + + /* Get YM2413 block */ + block = (opll->reg[0x20 + ch] >> 1) & 7; + + /* Add in block */ + frequency |= (block << 10); + + /* Add key-on flag */ + if(opll->reg[0x20 + ch] & 0x10) frequency |= 0x2000; + + /* Save current frequency/block/key-on setting */ + opll->channel[ch].frequency = (frequency & 0x3FFF); + + /* TODO: Handle sustain flag (bit 5) before key-on */ + + /* Write changes to YM3812 */ + OPL_WRITE(chip, 0xA0 + ch, (opll->channel[ch].frequency >> 0) & 0xFF); + OPL_WRITE(chip, 0xB0 + ch, (opll->channel[ch].frequency >> 8) & 0xFF); + } + break; + + case 0x30: /* Channel Volume Level and Instrument Select */ + + /* Ensure proper channel range */ + if(opll->latch > 0x38) break; + + /* If we're accessing registers 36, 37, or 38, and we're + in rhythm mode, then update the individual volume + settings. */ + if((opll->latch >= 0x36) && (opll->reg[0x0E] & 0x20)) + { + switch(opll->latch & 0x0F) + { + case 0x06: /* Bass drum */ + OPL_WRITE(chip, 0x53, ((data >> 0) & 0x0F) << 2); + break; + + case 0x07: /* High hat and snare drum */ + OPL_WRITE(chip, 0x51, ((data >> 4) & 0x0F) << 2); + OPL_WRITE(chip, 0x54, ((data >> 0) & 0x0F) << 2); + break; + + case 0x08: /* Tom-top and top cymbal */ + OPL_WRITE(chip, 0x52, ((data >> 4) & 0x0F) << 2); + OPL_WRITE(chip, 0x55, ((data >> 0) & 0x0F) << 2); + break; + } + } + else /* Set the new instrument and volume for this channel */ + { + int ch = (opll->latch & 0x0F); + int inst = (data >> 4) & 0x0F; + int vol = (data & 0x0F) << 2; + + load_instrument(chip, ch, inst, vol); + } + break; + } + } + else /* Register latch */ + { + opll->latch = (data & 0x3F); + } +} + + +void rhythm_mode_init(int chip) +{ + /* Point to current YM2413 context */ + t_ym2413 *opll = &ym2413[chip]; + + /* Load instrument settings for channel seven. (Bass drum) */ + OPL_WRITE(chip, 0x30, 0x13); + OPL_WRITE(chip, 0x33, 0x11); + OPL_WRITE(chip, 0x50, 0x25); + OPL_WRITE(chip, 0x53, ((opll->reg[0x36] >> 0) & 0x0F) << 2); + OPL_WRITE(chip, 0x70, 0xD7); + OPL_WRITE(chip, 0x73, 0xB7); + OPL_WRITE(chip, 0x90, 0xF4); + OPL_WRITE(chip, 0x93, 0xF4); + OPL_WRITE(chip, 0xF0, 0x00); + OPL_WRITE(chip, 0xF3, 0x00); + OPL_WRITE(chip, 0xC6, 0x00); + /* Use old frequency, but strip key-on bit */ + OPL_WRITE(chip, 0xA6, (opll->channel[6].frequency >> 0) & 0xFF); + OPL_WRITE(chip, 0xB6, (opll->channel[6].frequency >> 8) & 0x1F); + + /* Load instrument settings for channel eight. (High hat and snare drum) */ + OPL_WRITE(chip, 0x31, 0x13); + OPL_WRITE(chip, 0x34, 0x11); + OPL_WRITE(chip, 0x51, ((opll->reg[0x37] >> 4) & 0x0f) << 2); + OPL_WRITE(chip, 0x54, ((opll->reg[0x37] >> 0) & 0x0f) << 2); + OPL_WRITE(chip, 0x71, 0xD7); + OPL_WRITE(chip, 0x74, 0xB7); + OPL_WRITE(chip, 0x91, 0xF4); + OPL_WRITE(chip, 0x94, 0xF4); + OPL_WRITE(chip, 0xF1, 0x00); + OPL_WRITE(chip, 0xF4, 0x00); + OPL_WRITE(chip, 0xC7, 0x00); + /* Use old frequency, but strip key-on bit */ + OPL_WRITE(chip, 0xA7, (opll->channel[7].frequency >> 0) & 0xFF); + OPL_WRITE(chip, 0xB7, (opll->channel[7].frequency >> 8) & 0x1F); + + /* Load instrument settings for channel nine. (Tom-tom and top cymbal) */ + OPL_WRITE(chip, 0x32, 0x13); + OPL_WRITE(chip, 0x35, 0x11); + OPL_WRITE(chip, 0x52, ((opll->reg[0x38] >> 4) & 0x0F) << 2); + OPL_WRITE(chip, 0x55, ((opll->reg[0x38] >> 0) & 0x0F) << 2); + OPL_WRITE(chip, 0x72, 0xD7); + OPL_WRITE(chip, 0x75, 0xB7); + OPL_WRITE(chip, 0x92, 0xF4); + OPL_WRITE(chip, 0x95, 0xF4); + OPL_WRITE(chip, 0xF2, 0x00); + OPL_WRITE(chip, 0xF5, 0x00); + OPL_WRITE(chip, 0xC8, 0x00); + /* Use old frequency, but strip key-on bit */ + OPL_WRITE(chip, 0xA8, (opll->channel[8].frequency >> 0) & 0xFF); + OPL_WRITE(chip, 0xB8, (opll->channel[8].frequency >> 8) & 0x1F); +} + + +/* channel (0-9), instrument (0-F), volume (0-3F, YM3812 format) */ +void load_instrument(int chip, int ch, int inst, int vol) +{ + /* Point to current YM2413 context */ + t_ym2413 *opll = &ym2413[chip]; + + /* Point to fixed instrument or user table */ + unsigned char *param = (inst == 0) ? &opll->user[0] : &table[inst][0]; + + /* Maps channels to operator registers */ + unsigned char ch2op[] = {0, 1, 2, 8, 9, 10, 16, 17, 18}; + + /* Make operator offset from requested channel */ + int op = ch2op[ch]; + + /* Store volume level */ + opll->channel[ch].volume = (vol & 0x3F); + + /* Store instrument number */ + opll->channel[ch].instrument = (inst & 0x0F); + + /* Update instrument settings, except frequency registers */ + OPL_WRITE(chip, 0x20 + op, param[0]); + OPL_WRITE(chip, 0x23 + op, param[1]); + OPL_WRITE(chip, 0x40 + op, param[2]); + OPL_WRITE(chip, 0x43 + op, (param[3] & 0xC0) | opll->channel[ch].volume); + OPL_WRITE(chip, 0x60 + op, param[4]); + OPL_WRITE(chip, 0x63 + op, param[5]); + OPL_WRITE(chip, 0x80 + op, param[6]); + OPL_WRITE(chip, 0x83 + op, param[7]); + OPL_WRITE(chip, 0xE0 + op, param[8]); + OPL_WRITE(chip, 0xE3 + op, param[9]); + OPL_WRITE(chip, 0xC0 + ch, param[10]); +} diff --git a/MCUME_teensy/teensysms/ym2413.h b/MCUME_teensy/teensysms/ym2413.h new file mode 100644 index 0000000..0ec4d4c --- /dev/null +++ b/MCUME_teensy/teensysms/ym2413.h @@ -0,0 +1,33 @@ + +#ifndef _YM2413_H_ +#define _YM2413_H_ + +/* Total # of YM2413's that can be used at once - change as needed */ +#define MAX_YM2413 (4) + +/* YM2413 context */ +typedef struct +{ + unsigned char reg[0x40]; /* 64 registers */ + unsigned char latch; /* Register latch */ + unsigned char rhythm; /* Rhythm instruments loaded flag */ + unsigned char user[0x10]; /* User instrument settings */ + struct + { + unsigned short int frequency; /* Channel frequency */ + unsigned char volume; /* Channel volume */ + unsigned char instrument; /* Channel instrument */ + }channel[9]; +}t_ym2413; + +/* Global data */ +extern t_ym2413 ym2413[MAX_YM2413]; + +/* Function prototypes */ +void ym2413_init(int count); +void ym2413_reset(int chip); +void ym2413_write(int chip, int address, int data); +void load_instrument(int chip, int ch, int inst, int vol); +void rhythm_mode_init(int chip); + +#endif /* _YM2413_H_ */ diff --git a/MCUME_teensy/teensysms/z80.c b/MCUME_teensy/teensysms/z80.c new file mode 100644 index 0000000..0ae5a7a --- /dev/null +++ b/MCUME_teensy/teensysms/z80.c @@ -0,0 +1,4390 @@ +/***************************************************************************** + * + * z80.c + * Portable Z80 emulator V2.7 + * + * Copyright (C) 1998,1999,2000 Juergen Buchmueller, all rights reserved. + * + * - This source code is released as cpu_readmapfreeware for non-commercial purposes. + * - You are free to use and redistribute this code in modified or + * unmodified form, provided you list me in the credits. + * - If you modify this source code, you must add a notice to each modified + * source file that it has been changed. If you're a nice person, you + * will clearly mark each change too. :) + * - If you wish to use this for commercial purposes, please contact me at + * pullmoll@t-online.de + * - The author of this copywritten work reserves the right to change the + * terms of its usage and license at any time, including retroactively + * - This entire notice must remain in the source code. + * + * Changes in 2.7: + * - removed z80_vm specific code, it's not needed (and never was). + * Changes in 2.6: + * - BUSY_LOOP_HACKS needed to call change_pc16() earlier, before + * checking the opcodes at the new address, because otherwise they + * might access the old (wrong or even NULL) banked memory region. + * Thanks to Sean Young for finding this nasty bug. + * Changes in 2.5: + * - Burning cycles always adjusts the ICount by a multiple of 4. + * - In REPEAT_AT_ONCE cases the R register wasn't incremented twice + * per repetition as it should have been. Those repeated opcodes + * could also underflow the ICount. + * - Simplified TIME_LOOP_HACKS for BC and added two more for DE + HL + * timing loops. I think those hacks weren't endian safe before too. + * Changes in 2.4: + * - z80_reset zaps the entire context, sets IX and IY to 0xffff(!) and + * sets the Z flag. With these changes the Tehkan World Cup driver + * _seems_ to work again. + * Changes in 2.3: + * - External termination of the execution loop calls z80_burn() and + * z80_vm_burn() to burn an amount of cycles (R adjustment) + * - Shortcuts which burn CPU cycles (BUSY_LOOP_HACKS and TIME_LOOP_HACKS) + * now also adjust the R register depending on the skipped opcodes. + * Changes in 2.2: + * - Fixed bugs in CPL, SCF and CCF instructions flag handling. + * - Changed variable EA and ARG16() function to UINT32; this + * produces slightly more efficient code. + * - The DD/FD XY CB opcodes where XY is 40-7F and Y is not 6/E + * are changed to calls to the X6/XE opcodes to reduce object size. + * They're hardly ever used so this should not yield a speed penalty. + * New in 2.0: + * - Optional more exact Z80 emulation (#define Z80_EXACT 1) according + * to a detailed description by Sean Young which can be found at: + * http://www.msxnet.org/tech/Z80/z80undoc.txt + *****************************************************************************/ + +#include "cpuintrf.h" +#include "shared.h" + + +#include "shared.h" +extern void cpu_writemem16(int address, int data); +extern void cpu_writeport(int port, int data); +extern int cpu_readport(int port); +unsigned char *cpu_readmap[8]; +unsigned char *cpu_writemap[8]; + +#define cpu_readmem16(a) ((cpu_readmap[(a) >> 13] <0x80000)?read_rom(cpu_readmap[(a) >> 13]+(a & 0x1FFF)):cpu_readmap[(a) >> 13][(a) & 0x1FFF]) +#define cpu_readop(a) ((cpu_readmap[(a) >> 13] <0x80000)?read_rom(cpu_readmap[(a) >> 13]+(a & 0x1FFF)):cpu_readmap[(a) >> 13][(a) & 0x1FFF]) +#define cpu_readop_arg(a) ((cpu_readmap[(a) >> 13] <0x80000)?read_rom(cpu_readmap[(a) >> 13]+(a & 0x1FFF)):cpu_readmap[(a) >> 13][(a) & 0x1FFF]) + +//#define cpu_readmem16(a) cpu_readmap[(a) >> 13][(a) & 0x1FFF] +//#define cpu_readop(a) cpu_readmap[(a) >> 13][(a) & 0x1FFF] +//#define cpu_readop_arg(a) cpu_readmap[(a) >> 13][(a) & 0x1FFF] + +/* execute main opcodes inside a big switch statement */ +#ifndef BIG_SWITCH +#define BIG_SWITCH 1 +#endif + +/* big flags array for ADD/ADC/SUB/SBC/CP results */ +#define BIG_FLAGS_ARRAY 1 + +/* Set to 1 for a more exact (but somewhat slower) Z80 emulation */ +#define Z80_EXACT 1 + +/* repetitive commands (ldir,cpdr etc.) repeat at + once until cycles used up or B(C) counted down. */ +#define REPEAT_AT_ONCE 1 + +/* on JP and JR opcodes check for tight loops */ +#define BUSY_LOOP_HACKS 1 + +/* check for delay loops counting down BC */ +#define TIME_LOOP_HACKS 1 + +/* #ifdef X86_ASM */ +#undef BIG_FLAGS_ARRAY +#define BIG_FLAGS_ARRAY 0 +/*#endif */ + +/* +#ifdef PSX +#undef BIG_FLAGS_ARRAY +#define BIG_FLAGS_ARRAY 0 +#endif +*/ + +#define CF 0x01 +#define NF 0x02 +#define PF 0x04 +#define VF PF +#define XF 0x08 +#define HF 0x10 +#define YF 0x20 +#define ZF 0x40 +#define SF 0x80 + +#define INT_IRQ 0x01 +#define NMI_IRQ 0x02 + +#define _PPC Z80.PREPC.d /* previous program counter */ + +#define _PCD Z80.PC.d +#define _PC Z80.PC.w.l + +#define _SPD Z80.SP.d +#define _SP Z80.SP.w.l + +#define _AFD Z80.AF.d +#define _AF Z80.AF.w.l +#define _A Z80.AF.b.h +#define _F Z80.AF.b.l + +#define _BCD Z80.BC.d +#define _BC Z80.BC.w.l +#define _B Z80.BC.b.h +#define _C Z80.BC.b.l + +#define _DED Z80.DE.d +#define _DE Z80.DE.w.l +#define _D Z80.DE.b.h +#define _E Z80.DE.b.l + +#define _HLD Z80.HL.d +#define _HL Z80.HL.w.l +#define _H Z80.HL.b.h +#define _L Z80.HL.b.l + +#define _IXD Z80.IX.d +#define _IX Z80.IX.w.l +#define _HX Z80.IX.b.h +#define _LX Z80.IX.b.l + +#define _IYD Z80.IY.d +#define _IY Z80.IY.w.l +#define _HY Z80.IY.b.h +#define _LY Z80.IY.b.l + +#define _I Z80.I +#define _R Z80.R +#define _R2 Z80.R2 +#define _IM Z80.IM +#define _IFF1 Z80.IFF1 +#define _IFF2 Z80.IFF2 +#define _HALT Z80.HALT + +int z80_ICount; +static Z80_Regs Z80; +Z80_Regs *Z80_Context = &Z80; +static UINT32 EA; +int after_EI = 0; + +static UINT8 SZ[256]; /* zero and sign flags */ +static UINT8 SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */ +static UINT8 SZP[256]; /* zero, sign and parity flags */ +static UINT8 SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */ +static UINT8 SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */ +#include "z80daa.h" +/* +#if BIG_FLAGS_ARRAY +#include +static UINT8 *SZHVC_add = 0; +static UINT8 *SZHVC_sub = 0; +#endif +*/ + +#if Z80_EXACT +/* tmp1 value for ini/inir/outi/otir for [C.1-0][io.1-0] */ +static UINT8 irep_tmp1[4][4] = { + {0,0,1,0},{0,1,0,1},{1,0,1,1},{0,1,1,0} +}; + +/* tmp1 value for ind/indr/outd/otdr for [C.1-0][io.1-0] */ +static UINT8 drep_tmp1[4][4] = { + {0,1,0,0},{1,0,0,1},{0,0,1,0},{0,1,0,1} +}; + +/* tmp2 value for all in/out repeated opcodes for B.7-0 */ +static UINT8 breg_tmp2[256] = { + 0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1, + 0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0, + 1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1 +}; +#endif + +#include "arduinoproto.h" +PROGMEM static UINT8 cc_op[0x100] = { + 4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4, + 8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4, + 7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4, + 7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4, + 5,10,10,10,10,11, 7,11, 5, 4,10, 0,10,10, 7,11, + 5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11, + 5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11, + 5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11}; + + +PROGMEM static UINT8 cc_cb[0x100] = { + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8, + 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8}; + +PROGMEM static UINT8 cc_dd[0x100] = { + 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4, + 4,14,20,10, 9, 9, 9, 4, 4,15,20,10, 9, 9, 9, 4, + 4, 4, 4, 4,23,23,19, 4, 4,15, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9, +19,19,19,19,19,19, 4,19, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, + 4,14, 4,23, 4,15, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4, + 4, 4, 4, 4, 4, 4, 4, 4, 4,10, 4, 4, 4, 4, 4, 4}; + +/* dd/fd cycles are identical */ +#define cc_fd cc_dd + +PROGMEM static UINT8 cc_xxcb[0x100] = { +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23, +23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23}; + +PROGMEM static UINT8 cc_ed[0x100] = { + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, +12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9, +12,12,15,20, 8, 8, 8, 9,12,12,15,20, 8, 8, 8, 9, +12,12,15,20, 8, 8, 8,18,12,12,15,20, 8, 8, 8,18, +12,12,15,20, 8, 8, 8, 8,12,12,15,20, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, +16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, +16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, + 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8}; + +static void take_interrupt(void); + +#define PROTOTYPES(tablename,prefix) \ + static __inline__ void prefix##_00(void); static __inline__ void prefix##_01(void); static __inline__ void prefix##_02(void); static __inline__ void prefix##_03(void); \ + static __inline__ void prefix##_04(void); static __inline__ void prefix##_05(void); static __inline__ void prefix##_06(void); static __inline__ void prefix##_07(void); \ + static __inline__ void prefix##_08(void); static __inline__ void prefix##_09(void); static __inline__ void prefix##_0a(void); static __inline__ void prefix##_0b(void); \ + static __inline__ void prefix##_0c(void); static __inline__ void prefix##_0d(void); static __inline__ void prefix##_0e(void); static __inline__ void prefix##_0f(void); \ + static __inline__ void prefix##_10(void); static __inline__ void prefix##_11(void); static __inline__ void prefix##_12(void); static __inline__ void prefix##_13(void); \ + static __inline__ void prefix##_14(void); static __inline__ void prefix##_15(void); static __inline__ void prefix##_16(void); static __inline__ void prefix##_17(void); \ + static __inline__ void prefix##_18(void); static __inline__ void prefix##_19(void); static __inline__ void prefix##_1a(void); static __inline__ void prefix##_1b(void); \ + static __inline__ void prefix##_1c(void); static __inline__ void prefix##_1d(void); static __inline__ void prefix##_1e(void); static __inline__ void prefix##_1f(void); \ + static __inline__ void prefix##_20(void); static __inline__ void prefix##_21(void); static __inline__ void prefix##_22(void); static __inline__ void prefix##_23(void); \ + static __inline__ void prefix##_24(void); static __inline__ void prefix##_25(void); static __inline__ void prefix##_26(void); static __inline__ void prefix##_27(void); \ + static __inline__ void prefix##_28(void); static __inline__ void prefix##_29(void); static __inline__ void prefix##_2a(void); static __inline__ void prefix##_2b(void); \ + static __inline__ void prefix##_2c(void); static __inline__ void prefix##_2d(void); static __inline__ void prefix##_2e(void); static __inline__ void prefix##_2f(void); \ + static __inline__ void prefix##_30(void); static __inline__ void prefix##_31(void); static __inline__ void prefix##_32(void); static __inline__ void prefix##_33(void); \ + static __inline__ void prefix##_34(void); static __inline__ void prefix##_35(void); static __inline__ void prefix##_36(void); static __inline__ void prefix##_37(void); \ + static __inline__ void prefix##_38(void); static __inline__ void prefix##_39(void); static __inline__ void prefix##_3a(void); static __inline__ void prefix##_3b(void); \ + static __inline__ void prefix##_3c(void); static __inline__ void prefix##_3d(void); static __inline__ void prefix##_3e(void); static __inline__ void prefix##_3f(void); \ + static __inline__ void prefix##_40(void); static __inline__ void prefix##_41(void); static __inline__ void prefix##_42(void); static __inline__ void prefix##_43(void); \ + static __inline__ void prefix##_44(void); static __inline__ void prefix##_45(void); static __inline__ void prefix##_46(void); static __inline__ void prefix##_47(void); \ + static __inline__ void prefix##_48(void); static __inline__ void prefix##_49(void); static __inline__ void prefix##_4a(void); static __inline__ void prefix##_4b(void); \ + static __inline__ void prefix##_4c(void); static __inline__ void prefix##_4d(void); static __inline__ void prefix##_4e(void); static __inline__ void prefix##_4f(void); \ + static __inline__ void prefix##_50(void); static __inline__ void prefix##_51(void); static __inline__ void prefix##_52(void); static __inline__ void prefix##_53(void); \ + static __inline__ void prefix##_54(void); static __inline__ void prefix##_55(void); static __inline__ void prefix##_56(void); static __inline__ void prefix##_57(void); \ + static __inline__ void prefix##_58(void); static __inline__ void prefix##_59(void); static __inline__ void prefix##_5a(void); static __inline__ void prefix##_5b(void); \ + static __inline__ void prefix##_5c(void); static __inline__ void prefix##_5d(void); static __inline__ void prefix##_5e(void); static __inline__ void prefix##_5f(void); \ + static __inline__ void prefix##_60(void); static __inline__ void prefix##_61(void); static __inline__ void prefix##_62(void); static __inline__ void prefix##_63(void); \ + static __inline__ void prefix##_64(void); static __inline__ void prefix##_65(void); static __inline__ void prefix##_66(void); static __inline__ void prefix##_67(void); \ + static __inline__ void prefix##_68(void); static __inline__ void prefix##_69(void); static __inline__ void prefix##_6a(void); static __inline__ void prefix##_6b(void); \ + static __inline__ void prefix##_6c(void); static __inline__ void prefix##_6d(void); static __inline__ void prefix##_6e(void); static __inline__ void prefix##_6f(void); \ + static __inline__ void prefix##_70(void); static __inline__ void prefix##_71(void); static __inline__ void prefix##_72(void); static __inline__ void prefix##_73(void); \ + static __inline__ void prefix##_74(void); static __inline__ void prefix##_75(void); static __inline__ void prefix##_76(void); static __inline__ void prefix##_77(void); \ + static __inline__ void prefix##_78(void); static __inline__ void prefix##_79(void); static __inline__ void prefix##_7a(void); static __inline__ void prefix##_7b(void); \ + static __inline__ void prefix##_7c(void); static __inline__ void prefix##_7d(void); static __inline__ void prefix##_7e(void); static __inline__ void prefix##_7f(void); \ + static __inline__ void prefix##_80(void); static __inline__ void prefix##_81(void); static __inline__ void prefix##_82(void); static __inline__ void prefix##_83(void); \ + static __inline__ void prefix##_84(void); static __inline__ void prefix##_85(void); static __inline__ void prefix##_86(void); static __inline__ void prefix##_87(void); \ + static __inline__ void prefix##_88(void); static __inline__ void prefix##_89(void); static __inline__ void prefix##_8a(void); static __inline__ void prefix##_8b(void); \ + static __inline__ void prefix##_8c(void); static __inline__ void prefix##_8d(void); static __inline__ void prefix##_8e(void); static __inline__ void prefix##_8f(void); \ + static __inline__ void prefix##_90(void); static __inline__ void prefix##_91(void); static __inline__ void prefix##_92(void); static __inline__ void prefix##_93(void); \ + static __inline__ void prefix##_94(void); static __inline__ void prefix##_95(void); static __inline__ void prefix##_96(void); static __inline__ void prefix##_97(void); \ + static __inline__ void prefix##_98(void); static __inline__ void prefix##_99(void); static __inline__ void prefix##_9a(void); static __inline__ void prefix##_9b(void); \ + static __inline__ void prefix##_9c(void); static __inline__ void prefix##_9d(void); static __inline__ void prefix##_9e(void); static __inline__ void prefix##_9f(void); \ + static __inline__ void prefix##_a0(void); static __inline__ void prefix##_a1(void); static __inline__ void prefix##_a2(void); static __inline__ void prefix##_a3(void); \ + static __inline__ void prefix##_a4(void); static __inline__ void prefix##_a5(void); static __inline__ void prefix##_a6(void); static __inline__ void prefix##_a7(void); \ + static __inline__ void prefix##_a8(void); static __inline__ void prefix##_a9(void); static __inline__ void prefix##_aa(void); static __inline__ void prefix##_ab(void); \ + static __inline__ void prefix##_ac(void); static __inline__ void prefix##_ad(void); static __inline__ void prefix##_ae(void); static __inline__ void prefix##_af(void); \ + static __inline__ void prefix##_b0(void); static __inline__ void prefix##_b1(void); static __inline__ void prefix##_b2(void); static __inline__ void prefix##_b3(void); \ + static __inline__ void prefix##_b4(void); static __inline__ void prefix##_b5(void); static __inline__ void prefix##_b6(void); static __inline__ void prefix##_b7(void); \ + static __inline__ void prefix##_b8(void); static __inline__ void prefix##_b9(void); static __inline__ void prefix##_ba(void); static __inline__ void prefix##_bb(void); \ + static __inline__ void prefix##_bc(void); static __inline__ void prefix##_bd(void); static __inline__ void prefix##_be(void); static __inline__ void prefix##_bf(void); \ + static __inline__ void prefix##_c0(void); static __inline__ void prefix##_c1(void); static __inline__ void prefix##_c2(void); static __inline__ void prefix##_c3(void); \ + static __inline__ void prefix##_c4(void); static __inline__ void prefix##_c5(void); static __inline__ void prefix##_c6(void); static __inline__ void prefix##_c7(void); \ + static __inline__ void prefix##_c8(void); static __inline__ void prefix##_c9(void); static __inline__ void prefix##_ca(void); static __inline__ void prefix##_cb(void); \ + static __inline__ void prefix##_cc(void); static __inline__ void prefix##_cd(void); static __inline__ void prefix##_ce(void); static __inline__ void prefix##_cf(void); \ + static __inline__ void prefix##_d0(void); static __inline__ void prefix##_d1(void); static __inline__ void prefix##_d2(void); static __inline__ void prefix##_d3(void); \ + static __inline__ void prefix##_d4(void); static __inline__ void prefix##_d5(void); static __inline__ void prefix##_d6(void); static __inline__ void prefix##_d7(void); \ + static __inline__ void prefix##_d8(void); static __inline__ void prefix##_d9(void); static __inline__ void prefix##_da(void); static __inline__ void prefix##_db(void); \ + static __inline__ void prefix##_dc(void); static __inline__ void prefix##_dd(void); static __inline__ void prefix##_de(void); static __inline__ void prefix##_df(void); \ + static __inline__ void prefix##_e0(void); static __inline__ void prefix##_e1(void); static __inline__ void prefix##_e2(void); static __inline__ void prefix##_e3(void); \ + static __inline__ void prefix##_e4(void); static __inline__ void prefix##_e5(void); static __inline__ void prefix##_e6(void); static __inline__ void prefix##_e7(void); \ + static __inline__ void prefix##_e8(void); static __inline__ void prefix##_e9(void); static __inline__ void prefix##_ea(void); static __inline__ void prefix##_eb(void); \ + static __inline__ void prefix##_ec(void); static __inline__ void prefix##_ed(void); static __inline__ void prefix##_ee(void); static __inline__ void prefix##_ef(void); \ + static __inline__ void prefix##_f0(void); static __inline__ void prefix##_f1(void); static __inline__ void prefix##_f2(void); static __inline__ void prefix##_f3(void); \ + static __inline__ void prefix##_f4(void); static __inline__ void prefix##_f5(void); static __inline__ void prefix##_f6(void); static __inline__ void prefix##_f7(void); \ + static __inline__ void prefix##_f8(void); static __inline__ void prefix##_f9(void); static __inline__ void prefix##_fa(void); static __inline__ void prefix##_fb(void); \ + static __inline__ void prefix##_fc(void); static __inline__ void prefix##_fd(void); static __inline__ void prefix##_fe(void); static __inline__ void prefix##_ff(void); \ +PROGMEM static void (*tablename[0x100])(void) = { \ + prefix##_00,prefix##_01,prefix##_02,prefix##_03,prefix##_04,prefix##_05,prefix##_06,prefix##_07, \ + prefix##_08,prefix##_09,prefix##_0a,prefix##_0b,prefix##_0c,prefix##_0d,prefix##_0e,prefix##_0f, \ + prefix##_10,prefix##_11,prefix##_12,prefix##_13,prefix##_14,prefix##_15,prefix##_16,prefix##_17, \ + prefix##_18,prefix##_19,prefix##_1a,prefix##_1b,prefix##_1c,prefix##_1d,prefix##_1e,prefix##_1f, \ + prefix##_20,prefix##_21,prefix##_22,prefix##_23,prefix##_24,prefix##_25,prefix##_26,prefix##_27, \ + prefix##_28,prefix##_29,prefix##_2a,prefix##_2b,prefix##_2c,prefix##_2d,prefix##_2e,prefix##_2f, \ + prefix##_30,prefix##_31,prefix##_32,prefix##_33,prefix##_34,prefix##_35,prefix##_36,prefix##_37, \ + prefix##_38,prefix##_39,prefix##_3a,prefix##_3b,prefix##_3c,prefix##_3d,prefix##_3e,prefix##_3f, \ + prefix##_40,prefix##_41,prefix##_42,prefix##_43,prefix##_44,prefix##_45,prefix##_46,prefix##_47, \ + prefix##_48,prefix##_49,prefix##_4a,prefix##_4b,prefix##_4c,prefix##_4d,prefix##_4e,prefix##_4f, \ + prefix##_50,prefix##_51,prefix##_52,prefix##_53,prefix##_54,prefix##_55,prefix##_56,prefix##_57, \ + prefix##_58,prefix##_59,prefix##_5a,prefix##_5b,prefix##_5c,prefix##_5d,prefix##_5e,prefix##_5f, \ + prefix##_60,prefix##_61,prefix##_62,prefix##_63,prefix##_64,prefix##_65,prefix##_66,prefix##_67, \ + prefix##_68,prefix##_69,prefix##_6a,prefix##_6b,prefix##_6c,prefix##_6d,prefix##_6e,prefix##_6f, \ + prefix##_70,prefix##_71,prefix##_72,prefix##_73,prefix##_74,prefix##_75,prefix##_76,prefix##_77, \ + prefix##_78,prefix##_79,prefix##_7a,prefix##_7b,prefix##_7c,prefix##_7d,prefix##_7e,prefix##_7f, \ + prefix##_80,prefix##_81,prefix##_82,prefix##_83,prefix##_84,prefix##_85,prefix##_86,prefix##_87, \ + prefix##_88,prefix##_89,prefix##_8a,prefix##_8b,prefix##_8c,prefix##_8d,prefix##_8e,prefix##_8f, \ + prefix##_90,prefix##_91,prefix##_92,prefix##_93,prefix##_94,prefix##_95,prefix##_96,prefix##_97, \ + prefix##_98,prefix##_99,prefix##_9a,prefix##_9b,prefix##_9c,prefix##_9d,prefix##_9e,prefix##_9f, \ + prefix##_a0,prefix##_a1,prefix##_a2,prefix##_a3,prefix##_a4,prefix##_a5,prefix##_a6,prefix##_a7, \ + prefix##_a8,prefix##_a9,prefix##_aa,prefix##_ab,prefix##_ac,prefix##_ad,prefix##_ae,prefix##_af, \ + prefix##_b0,prefix##_b1,prefix##_b2,prefix##_b3,prefix##_b4,prefix##_b5,prefix##_b6,prefix##_b7, \ + prefix##_b8,prefix##_b9,prefix##_ba,prefix##_bb,prefix##_bc,prefix##_bd,prefix##_be,prefix##_bf, \ + prefix##_c0,prefix##_c1,prefix##_c2,prefix##_c3,prefix##_c4,prefix##_c5,prefix##_c6,prefix##_c7, \ + prefix##_c8,prefix##_c9,prefix##_ca,prefix##_cb,prefix##_cc,prefix##_cd,prefix##_ce,prefix##_cf, \ + prefix##_d0,prefix##_d1,prefix##_d2,prefix##_d3,prefix##_d4,prefix##_d5,prefix##_d6,prefix##_d7, \ + prefix##_d8,prefix##_d9,prefix##_da,prefix##_db,prefix##_dc,prefix##_dd,prefix##_de,prefix##_df, \ + prefix##_e0,prefix##_e1,prefix##_e2,prefix##_e3,prefix##_e4,prefix##_e5,prefix##_e6,prefix##_e7, \ + prefix##_e8,prefix##_e9,prefix##_ea,prefix##_eb,prefix##_ec,prefix##_ed,prefix##_ee,prefix##_ef, \ + prefix##_f0,prefix##_f1,prefix##_f2,prefix##_f3,prefix##_f4,prefix##_f5,prefix##_f6,prefix##_f7, \ + prefix##_f8,prefix##_f9,prefix##_fa,prefix##_fb,prefix##_fc,prefix##_fd,prefix##_fe,prefix##_ff \ +} + +PROTOTYPES(Z80op,op); +PROTOTYPES(Z80cb,cb); +PROTOTYPES(Z80dd,dd); +PROTOTYPES(Z80ed,ed); +PROTOTYPES(Z80fd,fd); +PROTOTYPES(Z80xxcb,xxcb); + +/****************************************************************************/ +/* Burn an odd amount of cycles, that is instructions taking something */ +/* different from 4 T-states per opcode (and R increment) */ +/****************************************************************************/ +static __inline__ void BURNODD(int cycles, int opcodes, int cyclesum) +{ + if( cycles > 0 ) + { + _R += (cycles / cyclesum) * opcodes; + z80_ICount -= (cycles / cyclesum) * cyclesum; + } +} + +/*************************************************************** + * define an opcode function + ***************************************************************/ +#define OP(prefix,opcode) static __inline__ void prefix##_##opcode(void) + +/*************************************************************** + * adjust cycle count by n T-states + ***************************************************************/ +#define CY(cycles) z80_ICount -= cycles + +/*************************************************************** + * execute an opcode + ***************************************************************/ +#define EXEC(prefix,opcode) \ +{ \ + unsigned op = opcode; \ + CY(cc_##prefix[op]); \ + (*Z80##prefix[op])(); \ +} + +#if BIG_SWITCH +#define EXEC_INLINE(prefix,opcode) \ +{ \ + unsigned op = opcode; \ + CY(cc_##prefix[op]); \ + switch(op) \ + { \ + case 0x00:prefix##_##00();break; case 0x01:prefix##_##01();break; case 0x02:prefix##_##02();break; case 0x03:prefix##_##03();break; \ + case 0x04:prefix##_##04();break; case 0x05:prefix##_##05();break; case 0x06:prefix##_##06();break; case 0x07:prefix##_##07();break; \ + case 0x08:prefix##_##08();break; case 0x09:prefix##_##09();break; case 0x0a:prefix##_##0a();break; case 0x0b:prefix##_##0b();break; \ + case 0x0c:prefix##_##0c();break; case 0x0d:prefix##_##0d();break; case 0x0e:prefix##_##0e();break; case 0x0f:prefix##_##0f();break; \ + case 0x10:prefix##_##10();break; case 0x11:prefix##_##11();break; case 0x12:prefix##_##12();break; case 0x13:prefix##_##13();break; \ + case 0x14:prefix##_##14();break; case 0x15:prefix##_##15();break; case 0x16:prefix##_##16();break; case 0x17:prefix##_##17();break; \ + case 0x18:prefix##_##18();break; case 0x19:prefix##_##19();break; case 0x1a:prefix##_##1a();break; case 0x1b:prefix##_##1b();break; \ + case 0x1c:prefix##_##1c();break; case 0x1d:prefix##_##1d();break; case 0x1e:prefix##_##1e();break; case 0x1f:prefix##_##1f();break; \ + case 0x20:prefix##_##20();break; case 0x21:prefix##_##21();break; case 0x22:prefix##_##22();break; case 0x23:prefix##_##23();break; \ + case 0x24:prefix##_##24();break; case 0x25:prefix##_##25();break; case 0x26:prefix##_##26();break; case 0x27:prefix##_##27();break; \ + case 0x28:prefix##_##28();break; case 0x29:prefix##_##29();break; case 0x2a:prefix##_##2a();break; case 0x2b:prefix##_##2b();break; \ + case 0x2c:prefix##_##2c();break; case 0x2d:prefix##_##2d();break; case 0x2e:prefix##_##2e();break; case 0x2f:prefix##_##2f();break; \ + case 0x30:prefix##_##30();break; case 0x31:prefix##_##31();break; case 0x32:prefix##_##32();break; case 0x33:prefix##_##33();break; \ + case 0x34:prefix##_##34();break; case 0x35:prefix##_##35();break; case 0x36:prefix##_##36();break; case 0x37:prefix##_##37();break; \ + case 0x38:prefix##_##38();break; case 0x39:prefix##_##39();break; case 0x3a:prefix##_##3a();break; case 0x3b:prefix##_##3b();break; \ + case 0x3c:prefix##_##3c();break; case 0x3d:prefix##_##3d();break; case 0x3e:prefix##_##3e();break; case 0x3f:prefix##_##3f();break; \ + case 0x40:prefix##_##40();break; case 0x41:prefix##_##41();break; case 0x42:prefix##_##42();break; case 0x43:prefix##_##43();break; \ + case 0x44:prefix##_##44();break; case 0x45:prefix##_##45();break; case 0x46:prefix##_##46();break; case 0x47:prefix##_##47();break; \ + case 0x48:prefix##_##48();break; case 0x49:prefix##_##49();break; case 0x4a:prefix##_##4a();break; case 0x4b:prefix##_##4b();break; \ + case 0x4c:prefix##_##4c();break; case 0x4d:prefix##_##4d();break; case 0x4e:prefix##_##4e();break; case 0x4f:prefix##_##4f();break; \ + case 0x50:prefix##_##50();break; case 0x51:prefix##_##51();break; case 0x52:prefix##_##52();break; case 0x53:prefix##_##53();break; \ + case 0x54:prefix##_##54();break; case 0x55:prefix##_##55();break; case 0x56:prefix##_##56();break; case 0x57:prefix##_##57();break; \ + case 0x58:prefix##_##58();break; case 0x59:prefix##_##59();break; case 0x5a:prefix##_##5a();break; case 0x5b:prefix##_##5b();break; \ + case 0x5c:prefix##_##5c();break; case 0x5d:prefix##_##5d();break; case 0x5e:prefix##_##5e();break; case 0x5f:prefix##_##5f();break; \ + case 0x60:prefix##_##60();break; case 0x61:prefix##_##61();break; case 0x62:prefix##_##62();break; case 0x63:prefix##_##63();break; \ + case 0x64:prefix##_##64();break; case 0x65:prefix##_##65();break; case 0x66:prefix##_##66();break; case 0x67:prefix##_##67();break; \ + case 0x68:prefix##_##68();break; case 0x69:prefix##_##69();break; case 0x6a:prefix##_##6a();break; case 0x6b:prefix##_##6b();break; \ + case 0x6c:prefix##_##6c();break; case 0x6d:prefix##_##6d();break; case 0x6e:prefix##_##6e();break; case 0x6f:prefix##_##6f();break; \ + case 0x70:prefix##_##70();break; case 0x71:prefix##_##71();break; case 0x72:prefix##_##72();break; case 0x73:prefix##_##73();break; \ + case 0x74:prefix##_##74();break; case 0x75:prefix##_##75();break; case 0x76:prefix##_##76();break; case 0x77:prefix##_##77();break; \ + case 0x78:prefix##_##78();break; case 0x79:prefix##_##79();break; case 0x7a:prefix##_##7a();break; case 0x7b:prefix##_##7b();break; \ + case 0x7c:prefix##_##7c();break; case 0x7d:prefix##_##7d();break; case 0x7e:prefix##_##7e();break; case 0x7f:prefix##_##7f();break; \ + case 0x80:prefix##_##80();break; case 0x81:prefix##_##81();break; case 0x82:prefix##_##82();break; case 0x83:prefix##_##83();break; \ + case 0x84:prefix##_##84();break; case 0x85:prefix##_##85();break; case 0x86:prefix##_##86();break; case 0x87:prefix##_##87();break; \ + case 0x88:prefix##_##88();break; case 0x89:prefix##_##89();break; case 0x8a:prefix##_##8a();break; case 0x8b:prefix##_##8b();break; \ + case 0x8c:prefix##_##8c();break; case 0x8d:prefix##_##8d();break; case 0x8e:prefix##_##8e();break; case 0x8f:prefix##_##8f();break; \ + case 0x90:prefix##_##90();break; case 0x91:prefix##_##91();break; case 0x92:prefix##_##92();break; case 0x93:prefix##_##93();break; \ + case 0x94:prefix##_##94();break; case 0x95:prefix##_##95();break; case 0x96:prefix##_##96();break; case 0x97:prefix##_##97();break; \ + case 0x98:prefix##_##98();break; case 0x99:prefix##_##99();break; case 0x9a:prefix##_##9a();break; case 0x9b:prefix##_##9b();break; \ + case 0x9c:prefix##_##9c();break; case 0x9d:prefix##_##9d();break; case 0x9e:prefix##_##9e();break; case 0x9f:prefix##_##9f();break; \ + case 0xa0:prefix##_##a0();break; case 0xa1:prefix##_##a1();break; case 0xa2:prefix##_##a2();break; case 0xa3:prefix##_##a3();break; \ + case 0xa4:prefix##_##a4();break; case 0xa5:prefix##_##a5();break; case 0xa6:prefix##_##a6();break; case 0xa7:prefix##_##a7();break; \ + case 0xa8:prefix##_##a8();break; case 0xa9:prefix##_##a9();break; case 0xaa:prefix##_##aa();break; case 0xab:prefix##_##ab();break; \ + case 0xac:prefix##_##ac();break; case 0xad:prefix##_##ad();break; case 0xae:prefix##_##ae();break; case 0xaf:prefix##_##af();break; \ + case 0xb0:prefix##_##b0();break; case 0xb1:prefix##_##b1();break; case 0xb2:prefix##_##b2();break; case 0xb3:prefix##_##b3();break; \ + case 0xb4:prefix##_##b4();break; case 0xb5:prefix##_##b5();break; case 0xb6:prefix##_##b6();break; case 0xb7:prefix##_##b7();break; \ + case 0xb8:prefix##_##b8();break; case 0xb9:prefix##_##b9();break; case 0xba:prefix##_##ba();break; case 0xbb:prefix##_##bb();break; \ + case 0xbc:prefix##_##bc();break; case 0xbd:prefix##_##bd();break; case 0xbe:prefix##_##be();break; case 0xbf:prefix##_##bf();break; \ + case 0xc0:prefix##_##c0();break; case 0xc1:prefix##_##c1();break; case 0xc2:prefix##_##c2();break; case 0xc3:prefix##_##c3();break; \ + case 0xc4:prefix##_##c4();break; case 0xc5:prefix##_##c5();break; case 0xc6:prefix##_##c6();break; case 0xc7:prefix##_##c7();break; \ + case 0xc8:prefix##_##c8();break; case 0xc9:prefix##_##c9();break; case 0xca:prefix##_##ca();break; case 0xcb:prefix##_##cb();break; \ + case 0xcc:prefix##_##cc();break; case 0xcd:prefix##_##cd();break; case 0xce:prefix##_##ce();break; case 0xcf:prefix##_##cf();break; \ + case 0xd0:prefix##_##d0();break; case 0xd1:prefix##_##d1();break; case 0xd2:prefix##_##d2();break; case 0xd3:prefix##_##d3();break; \ + case 0xd4:prefix##_##d4();break; case 0xd5:prefix##_##d5();break; case 0xd6:prefix##_##d6();break; case 0xd7:prefix##_##d7();break; \ + case 0xd8:prefix##_##d8();break; case 0xd9:prefix##_##d9();break; case 0xda:prefix##_##da();break; case 0xdb:prefix##_##db();break; \ + case 0xdc:prefix##_##dc();break; case 0xdd:prefix##_##dd();break; case 0xde:prefix##_##de();break; case 0xdf:prefix##_##df();break; \ + case 0xe0:prefix##_##e0();break; case 0xe1:prefix##_##e1();break; case 0xe2:prefix##_##e2();break; case 0xe3:prefix##_##e3();break; \ + case 0xe4:prefix##_##e4();break; case 0xe5:prefix##_##e5();break; case 0xe6:prefix##_##e6();break; case 0xe7:prefix##_##e7();break; \ + case 0xe8:prefix##_##e8();break; case 0xe9:prefix##_##e9();break; case 0xea:prefix##_##ea();break; case 0xeb:prefix##_##eb();break; \ + case 0xec:prefix##_##ec();break; case 0xed:prefix##_##ed();break; case 0xee:prefix##_##ee();break; case 0xef:prefix##_##ef();break; \ + case 0xf0:prefix##_##f0();break; case 0xf1:prefix##_##f1();break; case 0xf2:prefix##_##f2();break; case 0xf3:prefix##_##f3();break; \ + case 0xf4:prefix##_##f4();break; case 0xf5:prefix##_##f5();break; case 0xf6:prefix##_##f6();break; case 0xf7:prefix##_##f7();break; \ + case 0xf8:prefix##_##f8();break; case 0xf9:prefix##_##f9();break; case 0xfa:prefix##_##fa();break; case 0xfb:prefix##_##fb();break; \ + case 0xfc:prefix##_##fc();break; case 0xfd:prefix##_##fd();break; case 0xfe:prefix##_##fe();break; case 0xff:prefix##_##ff();break; \ + } \ +} +#else +#define EXEC_INLINE EXEC +#endif + + +/*************************************************************** + * Enter HALT state; write 1 to fake port on first execution + ***************************************************************/ +#define ENTER_HALT { \ + _PC--; \ + _HALT = 1; \ + if( !after_EI ) \ + z80_burn( z80_ICount ); \ +} + +/*************************************************************** + * Leave HALT state; write 0 to fake port + ***************************************************************/ +#define LEAVE_HALT { \ + if( _HALT ) \ + { \ + _HALT = 0; \ + _PC++; \ + } \ +} + +/*************************************************************** + * Input a byte from given I/O port + ***************************************************************/ +#define IN(port) ((UINT8)cpu_readport(port)) + +/*************************************************************** + * Output a byte to given I/O port + ***************************************************************/ +#define OUT(port,value) cpu_writeport(port,value) + +/*************************************************************** + * Read a byte from given memory location + ***************************************************************/ +#define RM(addr) (UINT8)cpu_readmem16(addr) + +/*************************************************************** + * Read a word from given memory location + ***************************************************************/ +static __inline__ void RM16( UINT32 addr, PAIR *r ) +{ + r->b.l = RM(addr); + r->b.h = RM((addr+1)&0xffff); +} + +/*************************************************************** + * Write a byte to given memory location + ***************************************************************/ +#define WM(addr,value) cpu_writemem16(addr,value) + +/*************************************************************** + * Write a word to given memory location + ***************************************************************/ +static __inline__ void WM16( UINT32 addr, PAIR *r ) +{ + WM(addr,r->b.l); + WM((addr+1)&0xffff,r->b.h); +} + +/*************************************************************** + * ROP() is identical to RM() except it is used for + * reading opcodes. In case of system with memory mapped I/O, + * this function can be used to greatly speed up emulation + ***************************************************************/ +static __inline__ UINT8 ROP(void) +{ + unsigned pc = _PCD; + _PC++; + return cpu_readop(pc); +} + +/**************************************************************** + * ARG() is identical to ROP() except it is used + * for reading opcode arguments. This difference can be used to + * support systems that use different encoding mechanisms for + * opcodes and opcode arguments + ***************************************************************/ +static __inline__ UINT8 ARG(void) +{ + unsigned pc = _PCD; + _PC++; + return cpu_readop_arg(pc); +} + +static __inline__ UINT32 ARG16(void) +{ + unsigned pc = _PCD; + _PC += 2; + return cpu_readop_arg(pc) | (cpu_readop_arg((pc+1)&0xffff) << 8); +} + +/*************************************************************** + * Calculate the effective address EA of an opcode using + * IX+offset resp. IY+offset addressing. + ***************************************************************/ +#define EAX EA = (UINT32)(UINT16)(_IX+(INT8)ARG()) +#define EAY EA = (UINT32)(UINT16)(_IY+(INT8)ARG()) + +/*************************************************************** + * POP + ***************************************************************/ +#define POP(DR) { RM16( _SPD, &Z80.DR ); _SP += 2; } + +/*************************************************************** + * PUSH + ***************************************************************/ +#define PUSH(SR) { _SP -= 2; WM16( _SPD, &Z80.SR ); } + +/*************************************************************** + * JP + ***************************************************************/ +#if BUSY_LOOP_HACKS +#define JP { \ + unsigned oldpc = _PCD-1; \ + _PCD = ARG16(); \ + /* speed up busy loop */ \ + if( _PCD == oldpc ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount, 1, 10 ); \ + } \ + else \ + { \ + UINT8 op = cpu_readop(_PCD); \ + if( _PCD == oldpc-1 ) \ + { \ + /* NOP - JP $-1 or EI - JP $-1 */ \ + if ( op == 0x00 || op == 0xfb ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount-4, 2, 4+10 ); \ + } \ + } \ + else \ + /* LD SP,#xxxx - JP $-3 (Galaga) */ \ + if( _PCD == oldpc-3 && op == 0x31 ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount-10, 2, 10+10 ); \ + } \ + } \ +} +#else +#define JP { \ + _PCD = ARG16(); \ +} +#endif + +/*************************************************************** + * JP_COND + ***************************************************************/ + +#define JP_COND(cond) \ + if( cond ) \ + { \ + _PCD = ARG16(); \ + } \ + else \ + { \ + _PC += 2; \ + } + +/*************************************************************** + * JR + ***************************************************************/ +#define JR() \ +{ \ + unsigned oldpc = _PCD-1; \ + INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \ + _PC += arg; /* so don't do _PC += ARG() */ \ + /* speed up busy loop */ \ + if( _PCD == oldpc ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount, 1, 12 ); \ + } \ + else \ + { \ + UINT8 op = cpu_readop(_PCD); \ + if( _PCD == oldpc-1 ) \ + { \ + /* NOP - JR $-1 or EI - JR $-1 */ \ + if ( op == 0x00 || op == 0xfb ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount-4, 2, 4+12 ); \ + } \ + } \ + else \ + /* LD SP,#xxxx - JR $-3 */ \ + if( _PCD == oldpc-3 && op == 0x31 ) \ + { \ + if( !after_EI ) \ + BURNODD( z80_ICount-12, 2, 10+12 ); \ + } \ + } \ +} + +/*************************************************************** + * JR_COND + ***************************************************************/ +#define JR_COND(cond) \ + if( cond ) \ + { \ + INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \ + _PC += arg; /* so don't do _PC += ARG() */ \ + CY(5); \ + } \ + else _PC++; \ + +/*************************************************************** + * CALL + ***************************************************************/ +#define CALL(cond) \ + if( cond ) \ + { \ + EA = ARG16(); \ + PUSH( PC ); \ + _PCD = EA; \ + CY(7); \ + } \ + else \ + { \ + _PC+=2; \ + } + +/*************************************************************** + * RET + ***************************************************************/ +#define RET(cond) \ + if( cond ) \ + { \ + POP(PC); \ + CY(6); \ + } + +/*************************************************************** + * RETN + ***************************************************************/ +#define RETN { \ + RET(1); \ + if( _IFF1 == 0 && _IFF2 == 1 ) \ + { \ + _IFF1 = 1; \ + if( Z80.irq_state != CLEAR_LINE || \ + Z80.request_irq >= 0 ) \ + { \ + take_interrupt(); \ + } \ + } \ + else _IFF1 = _IFF2; \ +} + +/*************************************************************** + * RETI + ***************************************************************/ +#define RETI { \ + int device = Z80.service_irq; \ + RET(1); \ +/* according to http://www.msxnet.org/tech/Z80/z80undoc.txt */ \ +/* _IFF1 = _IFF2; */ \ + if( device >= 0 ) \ + { \ + Z80.irq[device].interrupt_reti(Z80.irq[device].irq_param); \ + } \ +} + +/*************************************************************** + * LD R,A + ***************************************************************/ +#define LD_R_A { \ + _R = _A; \ + _R2 = _A & 0x80; /* keep bit 7 of R */ \ +} + +/*************************************************************** + * LD A,R + ***************************************************************/ +#define LD_A_R { \ + _A = (_R & 0x7f) | _R2; \ + _F = (_F & CF) | SZ[_A] | ( _IFF2 << 2 ); \ +} + +/*************************************************************** + * LD I,A + ***************************************************************/ +#define LD_I_A { \ + _I = _A; \ +} + +/*************************************************************** + * LD A,I + ***************************************************************/ +#define LD_A_I { \ + _A = _I; \ + _F = (_F & CF) | SZ[_A] | ( _IFF2 << 2 ); \ +} + +/*************************************************************** + * RST + ***************************************************************/ +#define RST(addr) \ + PUSH( PC ); \ + _PCD = addr; + +/*************************************************************** + * INC r8 + ***************************************************************/ +static __inline__ UINT8 INC(UINT8 value) +{ + UINT8 res = value + 1; + _F = (_F & CF) | SZHV_inc[res]; + return (UINT8)res; +} + +/*************************************************************** + * DEC r8 + ***************************************************************/ +static __inline__ UINT8 DEC(UINT8 value) +{ + UINT8 res = value - 1; + _F = (_F & CF) | SZHV_dec[res]; + return res; +} + +/*************************************************************** + * RLCA + ***************************************************************/ +#if Z80_EXACT +#define RLCA \ + _A = (_A << 1) | (_A >> 7); \ + _F = (_F & (SF | ZF | PF)) | (_A & (YF | XF | CF)) +#else +#define RLCA \ + _A = (_A << 1) | (_A >> 7); \ + _F = (_F & (SF | ZF | YF | XF | PF)) | (_A & CF) +#endif + +/*************************************************************** + * RRCA + ***************************************************************/ +#if Z80_EXACT +#define RRCA \ + _F = (_F & (SF | ZF | PF)) | (_A & (YF | XF | CF)); \ + _A = (_A >> 1) | (_A << 7) +#else +#define RRCA \ + _F = (_F & (SF | ZF | YF | XF | PF)) | (_A & CF); \ + _A = (_A >> 1) | (_A << 7) +#endif + +/*************************************************************** + * RLA + ***************************************************************/ +#if Z80_EXACT +#define RLA { \ + UINT8 res = (_A << 1) | (_F & CF); \ + UINT8 c = (_A & 0x80) ? CF : 0; \ + _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \ + _A = res; \ +} +#else +#define RLA { \ + UINT8 res = (_A << 1) | (_F & CF); \ + UINT8 c = (_A & 0x80) ? CF : 0; \ + _F = (_F & (SF | ZF | YF | XF | PF)) | c; \ + _A = res; \ +} +#endif + +/*************************************************************** + * RRA + ***************************************************************/ +#if Z80_EXACT +#define RRA { \ + UINT8 res = (_A >> 1) | (_F << 7); \ + UINT8 c = (_A & 0x01) ? CF : 0; \ + _F = (_F & (SF | ZF | PF)) | c | (res & (YF | XF)); \ + _A = res; \ +} +#else +#define RRA { \ + UINT8 res = (_A >> 1) | (_F << 7); \ + UINT8 c = (_A & 0x01) ? CF : 0; \ + _F = (_F & (SF | ZF | YF | XF | PF)) | c; \ + _A = res; \ +} +#endif + +/*************************************************************** + * RRD + ***************************************************************/ +#define RRD { \ + UINT8 n = RM(_HL); \ + WM( _HL, (n >> 4) | (_A << 4) ); \ + _A = (_A & 0xf0) | (n & 0x0f); \ + _F = (_F & CF) | SZP[_A]; \ +} + +/*************************************************************** + * RLD + ***************************************************************/ +#define RLD { \ + UINT8 n = RM(_HL); \ + WM( _HL, (n << 4) | (_A & 0x0f) ); \ + _A = (_A & 0xf0) | (n >> 4); \ + _F = (_F & CF) | SZP[_A]; \ +} + +/*************************************************************** + * ADD A,n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define ADD(value) \ + asm ( \ + " addb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " addb %1,%1 \n" \ + " addb %1,%1 \n" /* shift to P/V bit position */ \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" \ + " movb %0,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define ADD(value) \ + asm ( \ + " addb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " addb %1,%1 \n" \ + " addb %1,%1 \n" /* shift to P/V bit position */ \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define ADD(value) \ +{ \ + UINT32 ah = _AFD & 0xff00; \ + UINT32 res = (UINT8)((ah >> 8) + value); \ + _F = SZHVC_add[ah | res]; \ + _A = res; \ +} +#else +#define ADD(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A + val; \ + _F = SZ[(UINT8)res] | ((res >> 8) & CF) | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \ + _A = (UINT8)res; \ +} +#endif +#endif + +/*************************************************************** + * ADC A,n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define ADC(value) \ + asm ( \ + " shrb $1,%1 \n" \ + " adcb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " addb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + " movb %0,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define ADC(value) \ + asm ( \ + " shrb $1,%1 \n" \ + " adcb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " addb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define ADC(value) \ +{ \ + UINT32 ah = _AFD & 0xff00, c = _AFD & 1; \ + UINT32 res = (UINT8)((ah >> 8) + value + c); \ + _F = SZHVC_add[(c << 16) | ah | res]; \ + _A = res; \ +} +#else +#define ADC(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A + val + (_F & CF); \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A ^ 0x80) & (val ^ res) & 0x80) >> 5); \ + _A = res; \ +} +#endif +#endif + +/*************************************************************** + * SUB n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define SUB(value) \ + asm ( \ + " subb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + " movb %0,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define SUB(value) \ + asm ( \ + " subb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define SUB(value) \ +{ \ + UINT32 ah = _AFD & 0xff00; \ + UINT32 res = (UINT8)((ah >> 8) - value); \ + _F = SZHVC_sub[ah | res]; \ + _A = res; \ +} +#else +#define SUB(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A - val; \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A) & (_A ^ res) & 0x80) >> 5); \ + _A = res; \ +} +#endif +#endif + +/*************************************************************** + * SBC A,n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define SBC(value) \ + asm ( \ + " shrb $1,%1 \n" \ + " sbbb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + " movb %0,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define SBC(value) \ + asm ( \ + " shrb $1,%1 \n" \ + " sbbb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define SBC(value) \ +{ \ + UINT32 ah = _AFD & 0xff00, c = _AFD & 1; \ + UINT32 res = (UINT8)((ah >> 8) - value - c); \ + _F = SZHVC_sub[(c<<16) | ah | res]; \ + _A = res; \ +} +#else +#define SBC(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A - val - (_F & CF); \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ + ((_A ^ res ^ val) & HF) | \ + (((val ^ _A) & (_A ^ res) & 0x80) >> 5); \ + _A = res; \ +} +#endif +#endif + +/*************************************************************** + * NEG + ***************************************************************/ +#define NEG { \ + UINT8 value = _A; \ + _A = 0; \ + SUB(value); \ +} + +/*************************************************************** + * DAA + ***************************************************************/ +#define DAA { \ + int idx = _A; \ + if( _F & CF ) idx |= 0x100; \ + if( _F & HF ) idx |= 0x200; \ + if( _F & NF ) idx |= 0x400; \ + _AF = DAATable[idx]; \ +} + +/*************************************************************** + * AND n + ***************************************************************/ +#define AND(value) \ + _A &= value; \ + _F = SZP[_A] | HF + +/*************************************************************** + * OR n + ***************************************************************/ +#define OR(value) \ + _A |= value; \ + _F = SZP[_A] + +/*************************************************************** + * XOR n + ***************************************************************/ +#define XOR(value) \ + _A ^= value; \ + _F = SZP[_A] + +/*************************************************************** + * CP n + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define CP(value) \ + asm ( \ + " cmpb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + " movb %2,%%ah \n" /* get result */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#else +#define CP(value) \ + asm ( \ + " cmpb %2,%0 \n" \ + " lahf \n" \ + " setob %1 \n" /* al = 1 if overflow */ \ + " stc \n" /* prepare to set N flag */ \ + " adcb %1,%1 \n" /* shift to P/V bit position */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign, zero, half carry, carry */ \ + " orb %%ah,%1 \n" /* combine with P/V */ \ + :"=r" (_A), "=r" (_F) \ + :"r" (value), "1" (_F), "0" (_A) \ + ) +#endif +#else +#if BIG_FLAGS_ARRAY +#define CP(value) \ +{ \ + UINT32 ah = _AFD & 0xff00; \ + UINT32 res = (UINT8)((ah >> 8) - value); \ + _F = SZHVC_sub[ah | res]; \ +} +#else +#define CP(value) \ +{ \ + unsigned val = value; \ + unsigned res = _A - val; \ + _F = SZ[res & 0xff] | ((res >> 8) & CF) | NF | \ + ((_A ^ res ^ val) & HF) | \ + ((((val ^ _A) & (_A ^ res)) >> 5) & VF); \ +} +#endif +#endif + +/*************************************************************** + * EX AF,AF' + ***************************************************************/ +#define EX_AF { \ + PAIR tmp; \ + tmp = Z80.AF; Z80.AF = Z80.AF2; Z80.AF2 = tmp; \ +} + +/*************************************************************** + * EX DE,HL + ***************************************************************/ +#define EX_DE_HL { \ + PAIR tmp; \ + tmp = Z80.DE; Z80.DE = Z80.HL; Z80.HL = tmp; \ +} + +/*************************************************************** + * EXX + ***************************************************************/ +#define EXX { \ + PAIR tmp; \ + tmp = Z80.BC; Z80.BC = Z80.BC2; Z80.BC2 = tmp; \ + tmp = Z80.DE; Z80.DE = Z80.DE2; Z80.DE2 = tmp; \ + tmp = Z80.HL; Z80.HL = Z80.HL2; Z80.HL2 = tmp; \ +} + +/*************************************************************** + * EX (SP),r16 + ***************************************************************/ +#define EXSP(DR) \ +{ \ + PAIR tmp = { { 0, 0, 0, 0 } }; \ + RM16( _SPD, &tmp ); \ + WM16( _SPD, &Z80.DR ); \ + Z80.DR = tmp; \ +} + + +/*************************************************************** + * ADD16 + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define ADD16(DR,SR) \ + asm ( \ + " andb $0xc4,%1 \n" \ + " addb %%dl,%%cl \n" \ + " adcb %%dh,%%ch \n" \ + " lahf \n" \ + " andb $0x11,%%ah \n" \ + " orb %%ah,%1 \n" \ + " movb %%ch,%%ah \n" /* get result MSB */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=c" (Z80.DR.d), "=r" (_F) \ + :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d) \ + ) +#else +#define ADD16(DR,SR) \ + asm ( \ + " andb $0xc4,%1 \n" \ + " addb %%dl,%%cl \n" \ + " adcb %%dh,%%ch \n" \ + " lahf \n" \ + " andb $0x11,%%ah \n" \ + " orb %%ah,%1 \n" \ + :"=c" (Z80.DR.d), "=r" (_F) \ + :"0" (Z80.DR.d), "1" (_F), "d" (Z80.SR.d) \ + ) +#endif +#else +#define ADD16(DR,SR) \ +{ \ + UINT32 res = Z80.DR.d + Z80.SR.d; \ + _F = (_F & (SF | ZF | VF)) | \ + (((Z80.DR.d ^ res ^ Z80.SR.d) >> 8) & HF) | \ + ((res >> 16) & CF); \ + Z80.DR.w.l = (UINT16)res; \ +} +#endif + +/*************************************************************** + * ADC r16,r16 + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define ADC16(Reg) \ + asm ( \ + " shrb $1,%1 \n" \ + " adcb %%dl,%%cl \n" \ + " lahf \n" \ + " movb %%ah,%%dl \n" \ + " adcb %%dh,%%ch \n" \ + " lahf \n" \ + " setob %1 \n" \ + " orb $0xbf,%%dl \n" /* set all but zero */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ + " addb %1,%1 \n" \ + " orb %%ah,%1 \n" /* overflow into P/V */ \ + " andb %%dl,%1 \n" /* mask zero */ \ + " movb %%ch,%%ah \n" /* get result MSB */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=c" (_HLD), "=r" (_F) \ + :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ + ) +#else +#define ADC16(Reg) \ + asm ( \ + " shrb $1,%1 \n" \ + " adcb %%dl,%%cl \n" \ + " lahf \n" \ + " movb %%ah,%%dl \n" \ + " adcb %%dh,%%ch \n" \ + " lahf \n" \ + " setob %1 \n" \ + " orb $0xbf,%%dl \n" /* set all but zero */ \ + " addb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ + " addb %1,%1 \n" \ + " orb %%ah,%1 \n" /* overflow into P/V */ \ + " andb %%dl,%1 \n" /* mask zero */ \ + :"=c" (_HLD), "=r" (_F) \ + :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ + ) +#endif +#else +#define ADC16(Reg) \ +{ \ + UINT32 res = _HLD + Z80.Reg.d + (_F & CF); \ + _F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) | \ + ((res >> 16) & CF) | \ + ((res >> 8) & SF) | \ + ((res & 0xffff) ? 0 : ZF) | \ + (((Z80.Reg.d ^ _HLD ^ 0x8000) & (Z80.Reg.d ^ res) & 0x8000) >> 13); \ + _HL = (UINT16)res; \ +} +#endif + +/*************************************************************** + * SBC r16,r16 + ***************************************************************/ +#ifdef X86_ASM +#if Z80_EXACT +#define SBC16(Reg) \ +asm ( \ + " shrb $1,%1 \n" \ + " sbbb %%dl,%%cl \n" \ + " lahf \n" \ + " movb %%ah,%%dl \n" \ + " sbbb %%dh,%%ch \n" \ + " lahf \n" \ + " setob %1 \n" \ + " orb $0xbf,%%dl \n" /* set all but zero */ \ + " stc \n" \ + " adcb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ + " addb %1,%1 \n" \ + " orb %%ah,%1 \n" /* overflow into P/V */ \ + " andb %%dl,%1 \n" /* mask zero */ \ + " movb %%ch,%%ah \n" /* get result MSB */ \ + " andb $0x28,%%ah \n" /* maks flags 5+3 */ \ + " orb %%ah,%1 \n" /* put them into flags */ \ + :"=c" (_HLD), "=r" (_F) \ + :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ + ) +#else +#define SBC16(Reg) \ +asm ( \ + " shrb $1,%1 \n" \ + " sbbb %%dl,%%cl \n" \ + " lahf \n" \ + " movb %%ah,%%dl \n" \ + " sbbb %%dh,%%ch \n" \ + " lahf \n" \ + " setob %1 \n" \ + " orb $0xbf,%%dl \n" /* set all but zero */ \ + " stc \n" \ + " adcb %1,%1 \n" \ + " andb $0xd1,%%ah \n" /* sign,zero,half carry and carry */\ + " addb %1,%1 \n" \ + " orb %%ah,%1 \n" /* overflow into P/V */ \ + " andb %%dl,%1 \n" /* mask zero */ \ + :"=c" (_HLD), "=r" (_F) \ + :"0" (_HLD), "1" (_F), "d" (Z80.Reg.d) \ + ) +#endif +#else +#define SBC16(Reg) \ +{ \ + UINT32 res = _HLD - Z80.Reg.d - (_F & CF); \ + _F = (((_HLD ^ res ^ Z80.Reg.d) >> 8) & HF) | NF | \ + ((res >> 16) & CF) | \ + ((res >> 8) & SF) | \ + ((res & 0xffff) ? 0 : ZF) | \ + (((Z80.Reg.d ^ _HLD) & (_HLD ^ res) &0x8000) >> 13); \ + _HL = (UINT16)res; \ +} +#endif + +/*************************************************************** + * RLC r8 + ***************************************************************/ +static __inline__ UINT8 RLC(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x80) ? CF : 0; + res = ((res << 1) | (res >> 7)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * RRC r8 + ***************************************************************/ +static __inline__ UINT8 RRC(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x01) ? CF : 0; + res = ((res >> 1) | (res << 7)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * RL r8 + ***************************************************************/ +static __inline__ UINT8 RL(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x80) ? CF : 0; + res = ((res << 1) | (_F & CF)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * RR r8 + ***************************************************************/ +static __inline__ UINT8 RR(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x01) ? CF : 0; + res = ((res >> 1) | (_F << 7)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * SLA r8 + ***************************************************************/ +static __inline__ UINT8 SLA(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x80) ? CF : 0; + res = (res << 1) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * SRA r8 + ***************************************************************/ +static __inline__ UINT8 SRA(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x01) ? CF : 0; + res = ((res >> 1) | (res & 0x80)) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * SLL r8 + ***************************************************************/ +static __inline__ UINT8 SLL(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x80) ? CF : 0; + res = ((res << 1) | 0x01) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * SRL r8 + ***************************************************************/ +static __inline__ UINT8 SRL(UINT8 value) +{ + unsigned res = value; + unsigned c = (res & 0x01) ? CF : 0; + res = (res >> 1) & 0xff; + _F = SZP[res] | c; + return res; +} + +/*************************************************************** + * BIT bit,r8 + ***************************************************************/ +#define BIT(bit,reg) \ + _F = (_F & CF) | HF | SZ_BIT[reg & (1<>8) & (YF|XF)) +#else +#define BIT_XY BIT +#endif + +/*************************************************************** + * RES bit,r8 + ***************************************************************/ +static __inline__ UINT8 RES(UINT8 bit, UINT8 value) +{ + return value & ~(1< flag 5 */ \ + if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + _HL++; _DE++; _BC--; \ + if( _BC ) _F |= VF; \ +} +#else +#define LDI { \ + WM( _DE, RM(_HL) ); \ + _F &= SF | ZF | YF | XF | CF; \ + _HL++; _DE++; _BC--; \ + if( _BC ) _F |= VF; \ +} +#endif + +/*************************************************************** + * CPI + ***************************************************************/ +#if Z80_EXACT +#define CPI { \ + UINT8 val = RM(_HL); \ + UINT8 res = _A - val; \ + _HL++; _BC--; \ + _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF; \ + if( _F & HF ) res -= 1; \ + if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ + if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + if( _BC ) _F |= VF; \ +} +#else +#define CPI { \ + UINT8 val = RM(_HL); \ + UINT8 res = _A - val; \ + _HL++; _BC--; \ + _F = (_F & CF) | SZ[res] | ((_A ^ val ^ res) & HF) | NF; \ + if( _BC ) _F |= VF; \ +} +#endif + +/*************************************************************** + * INI + ***************************************************************/ +#if Z80_EXACT +#define INI { \ + UINT8 io = IN(_BC); \ + _B--; \ + WM( _HL, io ); \ + _HL++; \ + _F = SZ[_B]; \ + if( io & SF ) _F |= NF; \ + if( (_C + io + 1) & 0x100 ) _F |= HF | CF; \ + if( (irep_tmp1[_C & 3][io & 3] ^ \ + breg_tmp2[_B] ^ \ + (_C >> 2) ^ \ + (io >> 2)) & 1 ) \ + _F |= PF; \ +} +#else +#define INI { \ + _B--; \ + WM( _HL, IN(_BC) ); \ + _HL++; \ + _F = (_B) ? NF : NF | ZF; \ +} +#endif + +/*************************************************************** + * OUTI + ***************************************************************/ +#if Z80_EXACT +#define OUTI { \ + UINT8 io = RM(_HL); \ + OUT( _BC, io ); \ + _B--; \ + _HL++; \ + _F = SZ[_B]; \ + if( io & SF ) _F |= NF; \ + if( (_C + io + 1) & 0x100 ) _F |= HF | CF; \ + if( (irep_tmp1[_C & 3][io & 3] ^ \ + breg_tmp2[_B] ^ \ + (_C >> 2) ^ \ + (io >> 2)) & 1 ) \ + _F |= PF; \ +} +#else +#define OUTI { \ + OUT( _BC, RM(_HL) ); \ + _B--; \ + _HL++; \ + _F = (_B) ? NF : NF | ZF; \ +} +#endif + +/*************************************************************** + * LDD + ***************************************************************/ +#if Z80_EXACT +#define LDD { \ + UINT8 io = RM(_HL); \ + WM( _DE, io ); \ + _F &= SF | ZF | CF; \ + if( (_A + io) & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ + if( (_A + io) & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + _HL--; _DE--; _BC--; \ + if( _BC ) _F |= VF; \ +} +#else +#define LDD { \ + WM( _DE, RM(_HL) ); \ + _F &= SF | ZF | YF | XF | CF; \ + _HL--; _DE--; _BC--; \ + if( _BC ) _F |= VF; \ +} +#endif + +/*************************************************************** + * CPD + ***************************************************************/ +#if Z80_EXACT +#define CPD { \ + UINT8 val = RM(_HL); \ + UINT8 res = _A - val; \ + _HL--; _BC--; \ + _F = (_F & CF) | (SZ[res] & ~(YF|XF)) | ((_A ^ val ^ res) & HF) | NF; \ + if( _F & HF ) res -= 1; \ + if( res & 0x02 ) _F |= YF; /* bit 1 -> flag 5 */ \ + if( res & 0x08 ) _F |= XF; /* bit 3 -> flag 3 */ \ + if( _BC ) _F |= VF; \ +} +#else +#define CPD { \ + UINT8 val = RM(_HL); \ + UINT8 res = _A - val; \ + _HL--; _BC--; \ + _F = (_F & CF) | SZ[res] | ((_A ^ val ^ res) & HF) | NF; \ + if( _BC ) _F |= VF; \ +} +#endif + +/*************************************************************** + * IND + ***************************************************************/ +#if Z80_EXACT +#define IND { \ + UINT8 io = IN(_BC); \ + _B--; \ + WM( _HL, io ); \ + _HL--; \ + _F = SZ[_B]; \ + if( io & SF ) _F |= NF; \ + if( (_C + io - 1) & 0x100 ) _F |= HF | CF; \ + if( (drep_tmp1[_C & 3][io & 3] ^ \ + breg_tmp2[_B] ^ \ + (_C >> 2) ^ \ + (io >> 2)) & 1 ) \ + _F |= PF; \ +} +#else +#define IND { \ + _B--; \ + WM( _HL, IN(_BC) ); \ + _HL--; \ + _F = (_B) ? NF : NF | ZF; \ +} +#endif + +/*************************************************************** + * OUTD + ***************************************************************/ +#if Z80_EXACT +#define OUTD { \ + UINT8 io = RM(_HL); \ + OUT( _BC, io ); \ + _B--; \ + _HL--; \ + _F = SZ[_B]; \ + if( io & SF ) _F |= NF; \ + if( (_C + io - 1) & 0x100 ) _F |= HF | CF; \ + if( (drep_tmp1[_C & 3][io & 3] ^ \ + breg_tmp2[_B] ^ \ + (_C >> 2) ^ \ + (io >> 2)) & 1 ) \ + _F |= PF; \ +} +#else +#define OUTD { \ + OUT( _BC, RM(_HL) ); \ + _B--; \ + _HL--; \ + _F = (_B) ? NF : NF | ZF; \ +} +#endif + +/*************************************************************** + * LDIR + ***************************************************************/ +#if REPEAT_AT_ONCE +#define LDIR { \ + CY(5); \ + _PC -= 2; \ + do \ + { \ + LDI; \ + if( _BC ) \ + { \ + if( z80_ICount > 0 ) \ + { \ + _R += 2; /* increment R twice */ \ + CY(21); \ + } \ + else break; \ + } \ + else \ + { \ + _PC += 2; \ + z80_ICount += 5; \ + break; \ + } \ + } while( z80_ICount > 0 ); \ +} +#else +#define LDIR LDI; if( _BC ) { _PC -= 2; CY(5); } +#endif + +/*************************************************************** + * CPIR + ***************************************************************/ +#if REPEAT_AT_ONCE +#define CPIR { \ + CY(5); \ + _PC -= 2; \ + do \ + { \ + CPI; \ + if( _BC && !(_F & ZF) ) \ + { \ + if( z80_ICount > 0 ) \ + { \ + _R += 2; /* increment R twice */ \ + CY(21); \ + } \ + else break; \ + } \ + else \ + { \ + _PC += 2; \ + z80_ICount += 5; \ + break; \ + } \ + } while( z80_ICount > 0 ); \ +} +#else +#define CPIR CPI; if( _BC && !(_F & ZF) ) { _PC -= 2; CY(5); } +#endif + +/*************************************************************** + * INIR + ***************************************************************/ +#if REPEAT_AT_ONCE +#define INIR { \ + CY(5); \ + _PC -= 2; \ + do \ + { \ + INI; \ + if( _B ) \ + { \ + if( z80_ICount > 0 ) \ + { \ + _R += 2; /* increment R twice */ \ + CY(21); \ + } \ + else break; \ + } \ + else \ + { \ + _PC += 2; \ + z80_ICount += 5; \ + break; \ + } \ + } while( z80_ICount > 0 ); \ +} +#else +#define INIR INI; if( _B ) { _PC -= 2; CY(5); } +#endif + +/*************************************************************** + * OTIR + ***************************************************************/ +#if REPEAT_AT_ONCE +#define OTIR { \ + CY(5); \ + _PC -= 2; \ + do \ + { \ + OUTI; \ + if( _B ) \ + { \ + if( z80_ICount > 0 ) \ + { \ + _R += 2; /* increment R twice */ \ + CY(21); \ + } \ + else break; \ + } \ + else \ + { \ + _PC += 2; \ + z80_ICount += 5; \ + break; \ + } \ + } while( z80_ICount > 0 ); \ +} +#else +#define OTIR OUTI; if( _B ) { _PC -= 2; CY(5); } +#endif + +/*************************************************************** + * LDDR + ***************************************************************/ +#if REPEAT_AT_ONCE +#define LDDR { \ + CY(5); \ + _PC -= 2; \ + do \ + { \ + LDD; \ + if( _BC ) \ + { \ + if( z80_ICount > 0 ) \ + { \ + _R += 2; /* increment R twice */ \ + CY(21); \ + } \ + else break; \ + } \ + else \ + { \ + _PC += 2; \ + z80_ICount += 5; \ + break; \ + } \ + } while( z80_ICount > 0 ); \ +} +#else +#define LDDR LDD; if( _BC ) { _PC -= 2; CY(5); } +#endif + +/*************************************************************** + * CPDR + ***************************************************************/ +#if REPEAT_AT_ONCE +#define CPDR { \ + CY(5); \ + _PC -= 2; \ + do \ + { \ + CPD; \ + if( _BC && !(_F & ZF) ) \ + { \ + if( z80_ICount > 0 ) \ + { \ + _R += 2; /* increment R twice */ \ + CY(21); \ + } \ + else break; \ + } \ + else \ + { \ + _PC += 2; \ + z80_ICount += 5; \ + break; \ + } \ + } while( z80_ICount > 0 ); \ +} +#else +#define CPDR CPD; if( _BC && !(_F & ZF) ) { _PC -= 2; CY(5); } +#endif + +/*************************************************************** + * INDR + ***************************************************************/ +#if REPEAT_AT_ONCE +#define INDR { \ + CY(5); \ + _PC -= 2; \ + do \ + { \ + IND; \ + if( _B ) \ + { \ + if( z80_ICount > 0 ) \ + { \ + _R += 2; /* increment R twice */ \ + CY(21); \ + } \ + else break; \ + } \ + else \ + { \ + _PC += 2; \ + z80_ICount += 5; \ + break; \ + } \ + } while( z80_ICount > 0 ); \ +} +#else +#define INDR IND; if( _B ) { _PC -= 2; CY(5); } +#endif + +/*************************************************************** + * OTDR + ***************************************************************/ +#if REPEAT_AT_ONCE +#define OTDR { \ + CY(5); \ + _PC -= 2; \ + do \ + { \ + OUTD; \ + if( _B ) \ + { \ + if( z80_ICount > 0 ) \ + { \ + _R += 2; /* increment R twice */ \ + CY(21); \ + } \ + else break; \ + } \ + else \ + { \ + _PC += 2; \ + z80_ICount += 5; \ + break; \ + } \ + } while( z80_ICount > 0 ); \ +} +#else +#define OTDR OUTD; if( _B ) { _PC -= 2; CY(5); } +#endif + +/*************************************************************** + * EI + ***************************************************************/ +#define EI { \ + /* If interrupts were disabled, execute one more \ + * instruction and check the IRQ line. \ + * If not, simply set interrupt flip-flop 2 \ + */ \ + if( _IFF1 == 0 ) \ + { \ + _IFF1 = _IFF2 = 1; \ + _PPC = _PCD; \ + _R++; \ + if( Z80.irq_state != CLEAR_LINE || \ + Z80.request_irq >= 0 ) \ + { \ + after_EI = 1; /* avoid cycle skip hacks */ \ + EXEC(op,ROP()); \ + after_EI = 0; \ + take_interrupt(); \ + } \ + else EXEC(op,ROP()); \ + } else _IFF2 = 1; \ +} + +/********************************************************** + * opcodes with CB prefix + * rotate, shift and bit operations + **********************************************************/ +OP(cb,00) { _B = RLC(_B); } /* RLC B */ +OP(cb,01) { _C = RLC(_C); } /* RLC C */ +OP(cb,02) { _D = RLC(_D); } /* RLC D */ +OP(cb,03) { _E = RLC(_E); } /* RLC E */ +OP(cb,04) { _H = RLC(_H); } /* RLC H */ +OP(cb,05) { _L = RLC(_L); } /* RLC L */ +OP(cb,06) { WM( _HL, RLC(RM(_HL)) ); } /* RLC (HL) */ +OP(cb,07) { _A = RLC(_A); } /* RLC A */ + +OP(cb,08) { _B = RRC(_B); } /* RRC B */ +OP(cb,09) { _C = RRC(_C); } /* RRC C */ +OP(cb,0a) { _D = RRC(_D); } /* RRC D */ +OP(cb,0b) { _E = RRC(_E); } /* RRC E */ +OP(cb,0c) { _H = RRC(_H); } /* RRC H */ +OP(cb,0d) { _L = RRC(_L); } /* RRC L */ +OP(cb,0e) { WM( _HL, RRC(RM(_HL)) ); } /* RRC (HL) */ +OP(cb,0f) { _A = RRC(_A); } /* RRC A */ + +OP(cb,10) { _B = RL(_B); } /* RL B */ +OP(cb,11) { _C = RL(_C); } /* RL C */ +OP(cb,12) { _D = RL(_D); } /* RL D */ +OP(cb,13) { _E = RL(_E); } /* RL E */ +OP(cb,14) { _H = RL(_H); } /* RL H */ +OP(cb,15) { _L = RL(_L); } /* RL L */ +OP(cb,16) { WM( _HL, RL(RM(_HL)) ); } /* RL (HL) */ +OP(cb,17) { _A = RL(_A); } /* RL A */ + +OP(cb,18) { _B = RR(_B); } /* RR B */ +OP(cb,19) { _C = RR(_C); } /* RR C */ +OP(cb,1a) { _D = RR(_D); } /* RR D */ +OP(cb,1b) { _E = RR(_E); } /* RR E */ +OP(cb,1c) { _H = RR(_H); } /* RR H */ +OP(cb,1d) { _L = RR(_L); } /* RR L */ +OP(cb,1e) { WM( _HL, RR(RM(_HL)) ); } /* RR (HL) */ +OP(cb,1f) { _A = RR(_A); } /* RR A */ + +OP(cb,20) { _B = SLA(_B); } /* SLA B */ +OP(cb,21) { _C = SLA(_C); } /* SLA C */ +OP(cb,22) { _D = SLA(_D); } /* SLA D */ +OP(cb,23) { _E = SLA(_E); } /* SLA E */ +OP(cb,24) { _H = SLA(_H); } /* SLA H */ +OP(cb,25) { _L = SLA(_L); } /* SLA L */ +OP(cb,26) { WM( _HL, SLA(RM(_HL)) ); } /* SLA (HL) */ +OP(cb,27) { _A = SLA(_A); } /* SLA A */ + +OP(cb,28) { _B = SRA(_B); } /* SRA B */ +OP(cb,29) { _C = SRA(_C); } /* SRA C */ +OP(cb,2a) { _D = SRA(_D); } /* SRA D */ +OP(cb,2b) { _E = SRA(_E); } /* SRA E */ +OP(cb,2c) { _H = SRA(_H); } /* SRA H */ +OP(cb,2d) { _L = SRA(_L); } /* SRA L */ +OP(cb,2e) { WM( _HL, SRA(RM(_HL)) ); } /* SRA (HL) */ +OP(cb,2f) { _A = SRA(_A); } /* SRA A */ + +OP(cb,30) { _B = SLL(_B); } /* SLL B */ +OP(cb,31) { _C = SLL(_C); } /* SLL C */ +OP(cb,32) { _D = SLL(_D); } /* SLL D */ +OP(cb,33) { _E = SLL(_E); } /* SLL E */ +OP(cb,34) { _H = SLL(_H); } /* SLL H */ +OP(cb,35) { _L = SLL(_L); } /* SLL L */ +OP(cb,36) { WM( _HL, SLL(RM(_HL)) ); } /* SLL (HL) */ +OP(cb,37) { _A = SLL(_A); } /* SLL A */ + +OP(cb,38) { _B = SRL(_B); } /* SRL B */ +OP(cb,39) { _C = SRL(_C); } /* SRL C */ +OP(cb,3a) { _D = SRL(_D); } /* SRL D */ +OP(cb,3b) { _E = SRL(_E); } /* SRL E */ +OP(cb,3c) { _H = SRL(_H); } /* SRL H */ +OP(cb,3d) { _L = SRL(_L); } /* SRL L */ +OP(cb,3e) { WM( _HL, SRL(RM(_HL)) ); } /* SRL (HL) */ +OP(cb,3f) { _A = SRL(_A); } /* SRL A */ + +OP(cb,40) { BIT(0,_B); } /* BIT 0,B */ +OP(cb,41) { BIT(0,_C); } /* BIT 0,C */ +OP(cb,42) { BIT(0,_D); } /* BIT 0,D */ +OP(cb,43) { BIT(0,_E); } /* BIT 0,E */ +OP(cb,44) { BIT(0,_H); } /* BIT 0,H */ +OP(cb,45) { BIT(0,_L); } /* BIT 0,L */ +OP(cb,46) { BIT(0,RM(_HL)); } /* BIT 0,(HL) */ +OP(cb,47) { BIT(0,_A); } /* BIT 0,A */ + +OP(cb,48) { BIT(1,_B); } /* BIT 1,B */ +OP(cb,49) { BIT(1,_C); } /* BIT 1,C */ +OP(cb,4a) { BIT(1,_D); } /* BIT 1,D */ +OP(cb,4b) { BIT(1,_E); } /* BIT 1,E */ +OP(cb,4c) { BIT(1,_H); } /* BIT 1,H */ +OP(cb,4d) { BIT(1,_L); } /* BIT 1,L */ +OP(cb,4e) { BIT(1,RM(_HL)); } /* BIT 1,(HL) */ +OP(cb,4f) { BIT(1,_A); } /* BIT 1,A */ + +OP(cb,50) { BIT(2,_B); } /* BIT 2,B */ +OP(cb,51) { BIT(2,_C); } /* BIT 2,C */ +OP(cb,52) { BIT(2,_D); } /* BIT 2,D */ +OP(cb,53) { BIT(2,_E); } /* BIT 2,E */ +OP(cb,54) { BIT(2,_H); } /* BIT 2,H */ +OP(cb,55) { BIT(2,_L); } /* BIT 2,L */ +OP(cb,56) { BIT(2,RM(_HL)); } /* BIT 2,(HL) */ +OP(cb,57) { BIT(2,_A); } /* BIT 2,A */ + +OP(cb,58) { BIT(3,_B); } /* BIT 3,B */ +OP(cb,59) { BIT(3,_C); } /* BIT 3,C */ +OP(cb,5a) { BIT(3,_D); } /* BIT 3,D */ +OP(cb,5b) { BIT(3,_E); } /* BIT 3,E */ +OP(cb,5c) { BIT(3,_H); } /* BIT 3,H */ +OP(cb,5d) { BIT(3,_L); } /* BIT 3,L */ +OP(cb,5e) { BIT(3,RM(_HL)); } /* BIT 3,(HL) */ +OP(cb,5f) { BIT(3,_A); } /* BIT 3,A */ + +OP(cb,60) { BIT(4,_B); } /* BIT 4,B */ +OP(cb,61) { BIT(4,_C); } /* BIT 4,C */ +OP(cb,62) { BIT(4,_D); } /* BIT 4,D */ +OP(cb,63) { BIT(4,_E); } /* BIT 4,E */ +OP(cb,64) { BIT(4,_H); } /* BIT 4,H */ +OP(cb,65) { BIT(4,_L); } /* BIT 4,L */ +OP(cb,66) { BIT(4,RM(_HL)); } /* BIT 4,(HL) */ +OP(cb,67) { BIT(4,_A); } /* BIT 4,A */ + +OP(cb,68) { BIT(5,_B); } /* BIT 5,B */ +OP(cb,69) { BIT(5,_C); } /* BIT 5,C */ +OP(cb,6a) { BIT(5,_D); } /* BIT 5,D */ +OP(cb,6b) { BIT(5,_E); } /* BIT 5,E */ +OP(cb,6c) { BIT(5,_H); } /* BIT 5,H */ +OP(cb,6d) { BIT(5,_L); } /* BIT 5,L */ +OP(cb,6e) { BIT(5,RM(_HL)); } /* BIT 5,(HL) */ +OP(cb,6f) { BIT(5,_A); } /* BIT 5,A */ + +OP(cb,70) { BIT(6,_B); } /* BIT 6,B */ +OP(cb,71) { BIT(6,_C); } /* BIT 6,C */ +OP(cb,72) { BIT(6,_D); } /* BIT 6,D */ +OP(cb,73) { BIT(6,_E); } /* BIT 6,E */ +OP(cb,74) { BIT(6,_H); } /* BIT 6,H */ +OP(cb,75) { BIT(6,_L); } /* BIT 6,L */ +OP(cb,76) { BIT(6,RM(_HL)); } /* BIT 6,(HL) */ +OP(cb,77) { BIT(6,_A); } /* BIT 6,A */ + +OP(cb,78) { BIT(7,_B); } /* BIT 7,B */ +OP(cb,79) { BIT(7,_C); } /* BIT 7,C */ +OP(cb,7a) { BIT(7,_D); } /* BIT 7,D */ +OP(cb,7b) { BIT(7,_E); } /* BIT 7,E */ +OP(cb,7c) { BIT(7,_H); } /* BIT 7,H */ +OP(cb,7d) { BIT(7,_L); } /* BIT 7,L */ +OP(cb,7e) { BIT(7,RM(_HL)); } /* BIT 7,(HL) */ +OP(cb,7f) { BIT(7,_A); } /* BIT 7,A */ + +OP(cb,80) { _B = RES(0,_B); } /* RES 0,B */ +OP(cb,81) { _C = RES(0,_C); } /* RES 0,C */ +OP(cb,82) { _D = RES(0,_D); } /* RES 0,D */ +OP(cb,83) { _E = RES(0,_E); } /* RES 0,E */ +OP(cb,84) { _H = RES(0,_H); } /* RES 0,H */ +OP(cb,85) { _L = RES(0,_L); } /* RES 0,L */ +OP(cb,86) { WM( _HL, RES(0,RM(_HL)) ); } /* RES 0,(HL) */ +OP(cb,87) { _A = RES(0,_A); } /* RES 0,A */ + +OP(cb,88) { _B = RES(1,_B); } /* RES 1,B */ +OP(cb,89) { _C = RES(1,_C); } /* RES 1,C */ +OP(cb,8a) { _D = RES(1,_D); } /* RES 1,D */ +OP(cb,8b) { _E = RES(1,_E); } /* RES 1,E */ +OP(cb,8c) { _H = RES(1,_H); } /* RES 1,H */ +OP(cb,8d) { _L = RES(1,_L); } /* RES 1,L */ +OP(cb,8e) { WM( _HL, RES(1,RM(_HL)) ); } /* RES 1,(HL) */ +OP(cb,8f) { _A = RES(1,_A); } /* RES 1,A */ + +OP(cb,90) { _B = RES(2,_B); } /* RES 2,B */ +OP(cb,91) { _C = RES(2,_C); } /* RES 2,C */ +OP(cb,92) { _D = RES(2,_D); } /* RES 2,D */ +OP(cb,93) { _E = RES(2,_E); } /* RES 2,E */ +OP(cb,94) { _H = RES(2,_H); } /* RES 2,H */ +OP(cb,95) { _L = RES(2,_L); } /* RES 2,L */ +OP(cb,96) { WM( _HL, RES(2,RM(_HL)) ); } /* RES 2,(HL) */ +OP(cb,97) { _A = RES(2,_A); } /* RES 2,A */ + +OP(cb,98) { _B = RES(3,_B); } /* RES 3,B */ +OP(cb,99) { _C = RES(3,_C); } /* RES 3,C */ +OP(cb,9a) { _D = RES(3,_D); } /* RES 3,D */ +OP(cb,9b) { _E = RES(3,_E); } /* RES 3,E */ +OP(cb,9c) { _H = RES(3,_H); } /* RES 3,H */ +OP(cb,9d) { _L = RES(3,_L); } /* RES 3,L */ +OP(cb,9e) { WM( _HL, RES(3,RM(_HL)) ); } /* RES 3,(HL) */ +OP(cb,9f) { _A = RES(3,_A); } /* RES 3,A */ + +OP(cb,a0) { _B = RES(4,_B); } /* RES 4,B */ +OP(cb,a1) { _C = RES(4,_C); } /* RES 4,C */ +OP(cb,a2) { _D = RES(4,_D); } /* RES 4,D */ +OP(cb,a3) { _E = RES(4,_E); } /* RES 4,E */ +OP(cb,a4) { _H = RES(4,_H); } /* RES 4,H */ +OP(cb,a5) { _L = RES(4,_L); } /* RES 4,L */ +OP(cb,a6) { WM( _HL, RES(4,RM(_HL)) ); } /* RES 4,(HL) */ +OP(cb,a7) { _A = RES(4,_A); } /* RES 4,A */ + +OP(cb,a8) { _B = RES(5,_B); } /* RES 5,B */ +OP(cb,a9) { _C = RES(5,_C); } /* RES 5,C */ +OP(cb,aa) { _D = RES(5,_D); } /* RES 5,D */ +OP(cb,ab) { _E = RES(5,_E); } /* RES 5,E */ +OP(cb,ac) { _H = RES(5,_H); } /* RES 5,H */ +OP(cb,ad) { _L = RES(5,_L); } /* RES 5,L */ +OP(cb,ae) { WM( _HL, RES(5,RM(_HL)) ); } /* RES 5,(HL) */ +OP(cb,af) { _A = RES(5,_A); } /* RES 5,A */ + +OP(cb,b0) { _B = RES(6,_B); } /* RES 6,B */ +OP(cb,b1) { _C = RES(6,_C); } /* RES 6,C */ +OP(cb,b2) { _D = RES(6,_D); } /* RES 6,D */ +OP(cb,b3) { _E = RES(6,_E); } /* RES 6,E */ +OP(cb,b4) { _H = RES(6,_H); } /* RES 6,H */ +OP(cb,b5) { _L = RES(6,_L); } /* RES 6,L */ +OP(cb,b6) { WM( _HL, RES(6,RM(_HL)) ); } /* RES 6,(HL) */ +OP(cb,b7) { _A = RES(6,_A); } /* RES 6,A */ + +OP(cb,b8) { _B = RES(7,_B); } /* RES 7,B */ +OP(cb,b9) { _C = RES(7,_C); } /* RES 7,C */ +OP(cb,ba) { _D = RES(7,_D); } /* RES 7,D */ +OP(cb,bb) { _E = RES(7,_E); } /* RES 7,E */ +OP(cb,bc) { _H = RES(7,_H); } /* RES 7,H */ +OP(cb,bd) { _L = RES(7,_L); } /* RES 7,L */ +OP(cb,be) { WM( _HL, RES(7,RM(_HL)) ); } /* RES 7,(HL) */ +OP(cb,bf) { _A = RES(7,_A); } /* RES 7,A */ + +OP(cb,c0) { _B = SET(0,_B); } /* SET 0,B */ +OP(cb,c1) { _C = SET(0,_C); } /* SET 0,C */ +OP(cb,c2) { _D = SET(0,_D); } /* SET 0,D */ +OP(cb,c3) { _E = SET(0,_E); } /* SET 0,E */ +OP(cb,c4) { _H = SET(0,_H); } /* SET 0,H */ +OP(cb,c5) { _L = SET(0,_L); } /* SET 0,L */ +OP(cb,c6) { WM( _HL, SET(0,RM(_HL)) ); } /* SET 0,(HL) */ +OP(cb,c7) { _A = SET(0,_A); } /* SET 0,A */ + +OP(cb,c8) { _B = SET(1,_B); } /* SET 1,B */ +OP(cb,c9) { _C = SET(1,_C); } /* SET 1,C */ +OP(cb,ca) { _D = SET(1,_D); } /* SET 1,D */ +OP(cb,cb) { _E = SET(1,_E); } /* SET 1,E */ +OP(cb,cc) { _H = SET(1,_H); } /* SET 1,H */ +OP(cb,cd) { _L = SET(1,_L); } /* SET 1,L */ +OP(cb,ce) { WM( _HL, SET(1,RM(_HL)) ); } /* SET 1,(HL) */ +OP(cb,cf) { _A = SET(1,_A); } /* SET 1,A */ + +OP(cb,d0) { _B = SET(2,_B); } /* SET 2,B */ +OP(cb,d1) { _C = SET(2,_C); } /* SET 2,C */ +OP(cb,d2) { _D = SET(2,_D); } /* SET 2,D */ +OP(cb,d3) { _E = SET(2,_E); } /* SET 2,E */ +OP(cb,d4) { _H = SET(2,_H); } /* SET 2,H */ +OP(cb,d5) { _L = SET(2,_L); } /* SET 2,L */ +OP(cb,d6) { WM( _HL, SET(2,RM(_HL)) ); }/* SET 2,(HL) */ +OP(cb,d7) { _A = SET(2,_A); } /* SET 2,A */ + +OP(cb,d8) { _B = SET(3,_B); } /* SET 3,B */ +OP(cb,d9) { _C = SET(3,_C); } /* SET 3,C */ +OP(cb,da) { _D = SET(3,_D); } /* SET 3,D */ +OP(cb,db) { _E = SET(3,_E); } /* SET 3,E */ +OP(cb,dc) { _H = SET(3,_H); } /* SET 3,H */ +OP(cb,dd) { _L = SET(3,_L); } /* SET 3,L */ +OP(cb,de) { WM( _HL, SET(3,RM(_HL)) ); } /* SET 3,(HL) */ +OP(cb,df) { _A = SET(3,_A); } /* SET 3,A */ + +OP(cb,e0) { _B = SET(4,_B); } /* SET 4,B */ +OP(cb,e1) { _C = SET(4,_C); } /* SET 4,C */ +OP(cb,e2) { _D = SET(4,_D); } /* SET 4,D */ +OP(cb,e3) { _E = SET(4,_E); } /* SET 4,E */ +OP(cb,e4) { _H = SET(4,_H); } /* SET 4,H */ +OP(cb,e5) { _L = SET(4,_L); } /* SET 4,L */ +OP(cb,e6) { WM( _HL, SET(4,RM(_HL)) ); } /* SET 4,(HL) */ +OP(cb,e7) { _A = SET(4,_A); } /* SET 4,A */ + +OP(cb,e8) { _B = SET(5,_B); } /* SET 5,B */ +OP(cb,e9) { _C = SET(5,_C); } /* SET 5,C */ +OP(cb,ea) { _D = SET(5,_D); } /* SET 5,D */ +OP(cb,eb) { _E = SET(5,_E); } /* SET 5,E */ +OP(cb,ec) { _H = SET(5,_H); } /* SET 5,H */ +OP(cb,ed) { _L = SET(5,_L); } /* SET 5,L */ +OP(cb,ee) { WM( _HL, SET(5,RM(_HL)) ); } /* SET 5,(HL) */ +OP(cb,ef) { _A = SET(5,_A); } /* SET 5,A */ + +OP(cb,f0) { _B = SET(6,_B); } /* SET 6,B */ +OP(cb,f1) { _C = SET(6,_C); } /* SET 6,C */ +OP(cb,f2) { _D = SET(6,_D); } /* SET 6,D */ +OP(cb,f3) { _E = SET(6,_E); } /* SET 6,E */ +OP(cb,f4) { _H = SET(6,_H); } /* SET 6,H */ +OP(cb,f5) { _L = SET(6,_L); } /* SET 6,L */ +OP(cb,f6) { WM( _HL, SET(6,RM(_HL)) ); } /* SET 6,(HL) */ +OP(cb,f7) { _A = SET(6,_A); } /* SET 6,A */ + +OP(cb,f8) { _B = SET(7,_B); } /* SET 7,B */ +OP(cb,f9) { _C = SET(7,_C); } /* SET 7,C */ +OP(cb,fa) { _D = SET(7,_D); } /* SET 7,D */ +OP(cb,fb) { _E = SET(7,_E); } /* SET 7,E */ +OP(cb,fc) { _H = SET(7,_H); } /* SET 7,H */ +OP(cb,fd) { _L = SET(7,_L); } /* SET 7,L */ +OP(cb,fe) { WM( _HL, SET(7,RM(_HL)) ); } /* SET 7,(HL) */ +OP(cb,ff) { _A = SET(7,_A); } /* SET 7,A */ + + +/********************************************************** +* opcodes with DD/FD CB prefix +* rotate, shift and bit operations with (IX+o) +**********************************************************/ +OP(xxcb,00) { _B = RLC( RM(EA) ); WM( EA,_B ); } /* RLC B=(XY+o) */ +OP(xxcb,01) { _C = RLC( RM(EA) ); WM( EA,_C ); } /* RLC C=(XY+o) */ +OP(xxcb,02) { _D = RLC( RM(EA) ); WM( EA,_D ); } /* RLC D=(XY+o) */ +OP(xxcb,03) { _E = RLC( RM(EA) ); WM( EA,_E ); } /* RLC E=(XY+o) */ +OP(xxcb,04) { _H = RLC( RM(EA) ); WM( EA,_H ); } /* RLC H=(XY+o) */ +OP(xxcb,05) { _L = RLC( RM(EA) ); WM( EA,_L ); } /* RLC L=(XY+o) */ +OP(xxcb,06) { WM( EA, RLC( RM(EA) ) ); } /* RLC (XY+o) */ +OP(xxcb,07) { _A = RLC( RM(EA) ); WM( EA,_A ); } /* RLC A=(XY+o) */ + +OP(xxcb,08) { _B = RRC( RM(EA) ); WM( EA,_B ); } /* RRC B=(XY+o) */ +OP(xxcb,09) { _C = RRC( RM(EA) ); WM( EA,_C ); } /* RRC C=(XY+o) */ +OP(xxcb,0a) { _D = RRC( RM(EA) ); WM( EA,_D ); } /* RRC D=(XY+o) */ +OP(xxcb,0b) { _E = RRC( RM(EA) ); WM( EA,_E ); } /* RRC E=(XY+o) */ +OP(xxcb,0c) { _H = RRC( RM(EA) ); WM( EA,_H ); } /* RRC H=(XY+o) */ +OP(xxcb,0d) { _L = RRC( RM(EA) ); WM( EA,_L ); } /* RRC L=(XY+o) */ +OP(xxcb,0e) { WM( EA,RRC( RM(EA) ) ); } /* RRC (XY+o) */ +OP(xxcb,0f) { _A = RRC( RM(EA) ); WM( EA,_A ); } /* RRC A=(XY+o) */ + +OP(xxcb,10) { _B = RL( RM(EA) ); WM( EA,_B ); } /* RL B=(XY+o) */ +OP(xxcb,11) { _C = RL( RM(EA) ); WM( EA,_C ); } /* RL C=(XY+o) */ +OP(xxcb,12) { _D = RL( RM(EA) ); WM( EA,_D ); } /* RL D=(XY+o) */ +OP(xxcb,13) { _E = RL( RM(EA) ); WM( EA,_E ); } /* RL E=(XY+o) */ +OP(xxcb,14) { _H = RL( RM(EA) ); WM( EA,_H ); } /* RL H=(XY+o) */ +OP(xxcb,15) { _L = RL( RM(EA) ); WM( EA,_L ); } /* RL L=(XY+o) */ +OP(xxcb,16) { WM( EA,RL( RM(EA) ) ); } /* RL (XY+o) */ +OP(xxcb,17) { _A = RL( RM(EA) ); WM( EA,_A ); } /* RL A=(XY+o) */ + +OP(xxcb,18) { _B = RR( RM(EA) ); WM( EA,_B ); } /* RR B=(XY+o) */ +OP(xxcb,19) { _C = RR( RM(EA) ); WM( EA,_C ); } /* RR C=(XY+o) */ +OP(xxcb,1a) { _D = RR( RM(EA) ); WM( EA,_D ); } /* RR D=(XY+o) */ +OP(xxcb,1b) { _E = RR( RM(EA) ); WM( EA,_E ); } /* RR E=(XY+o) */ +OP(xxcb,1c) { _H = RR( RM(EA) ); WM( EA,_H ); } /* RR H=(XY+o) */ +OP(xxcb,1d) { _L = RR( RM(EA) ); WM( EA,_L ); } /* RR L=(XY+o) */ +OP(xxcb,1e) { WM( EA,RR( RM(EA) ) ); } /* RR (XY+o) */ +OP(xxcb,1f) { _A = RR( RM(EA) ); WM( EA,_A ); } /* RR A=(XY+o) */ + +OP(xxcb,20) { _B = SLA( RM(EA) ); WM( EA,_B ); } /* SLA B=(XY+o) */ +OP(xxcb,21) { _C = SLA( RM(EA) ); WM( EA,_C ); } /* SLA C=(XY+o) */ +OP(xxcb,22) { _D = SLA( RM(EA) ); WM( EA,_D ); } /* SLA D=(XY+o) */ +OP(xxcb,23) { _E = SLA( RM(EA) ); WM( EA,_E ); } /* SLA E=(XY+o) */ +OP(xxcb,24) { _H = SLA( RM(EA) ); WM( EA,_H ); } /* SLA H=(XY+o) */ +OP(xxcb,25) { _L = SLA( RM(EA) ); WM( EA,_L ); } /* SLA L=(XY+o) */ +OP(xxcb,26) { WM( EA,SLA( RM(EA) ) ); } /* SLA (XY+o) */ +OP(xxcb,27) { _A = SLA( RM(EA) ); WM( EA,_A ); } /* SLA A=(XY+o) */ + +OP(xxcb,28) { _B = SRA( RM(EA) ); WM( EA,_B ); } /* SRA B=(XY+o) */ +OP(xxcb,29) { _C = SRA( RM(EA) ); WM( EA,_C ); } /* SRA C=(XY+o) */ +OP(xxcb,2a) { _D = SRA( RM(EA) ); WM( EA,_D ); } /* SRA D=(XY+o) */ +OP(xxcb,2b) { _E = SRA( RM(EA) ); WM( EA,_E ); } /* SRA E=(XY+o) */ +OP(xxcb,2c) { _H = SRA( RM(EA) ); WM( EA,_H ); } /* SRA H=(XY+o) */ +OP(xxcb,2d) { _L = SRA( RM(EA) ); WM( EA,_L ); } /* SRA L=(XY+o) */ +OP(xxcb,2e) { WM( EA,SRA( RM(EA) ) ); } /* SRA (XY+o) */ +OP(xxcb,2f) { _A = SRA( RM(EA) ); WM( EA,_A ); } /* SRA A=(XY+o) */ + +OP(xxcb,30) { _B = SLL( RM(EA) ); WM( EA,_B ); } /* SLL B=(XY+o) */ +OP(xxcb,31) { _C = SLL( RM(EA) ); WM( EA,_C ); } /* SLL C=(XY+o) */ +OP(xxcb,32) { _D = SLL( RM(EA) ); WM( EA,_D ); } /* SLL D=(XY+o) */ +OP(xxcb,33) { _E = SLL( RM(EA) ); WM( EA,_E ); } /* SLL E=(XY+o) */ +OP(xxcb,34) { _H = SLL( RM(EA) ); WM( EA,_H ); } /* SLL H=(XY+o) */ +OP(xxcb,35) { _L = SLL( RM(EA) ); WM( EA,_L ); } /* SLL L=(XY+o) */ +OP(xxcb,36) { WM( EA,SLL( RM(EA) ) ); } /* SLL (XY+o) */ +OP(xxcb,37) { _A = SLL( RM(EA) ); WM( EA,_A ); } /* SLL A=(XY+o) */ + +OP(xxcb,38) { _B = SRL( RM(EA) ); WM( EA,_B ); } /* SRL B=(XY+o) */ +OP(xxcb,39) { _C = SRL( RM(EA) ); WM( EA,_C ); } /* SRL C=(XY+o) */ +OP(xxcb,3a) { _D = SRL( RM(EA) ); WM( EA,_D ); } /* SRL D=(XY+o) */ +OP(xxcb,3b) { _E = SRL( RM(EA) ); WM( EA,_E ); } /* SRL E=(XY+o) */ +OP(xxcb,3c) { _H = SRL( RM(EA) ); WM( EA,_H ); } /* SRL H=(XY+o) */ +OP(xxcb,3d) { _L = SRL( RM(EA) ); WM( EA,_L ); } /* SRL L=(XY+o) */ +OP(xxcb,3e) { WM( EA,SRL( RM(EA) ) ); } /* SRL (XY+o) */ +OP(xxcb,3f) { _A = SRL( RM(EA) ); WM( EA,_A ); } /* SRL A=(XY+o) */ + +OP(xxcb,40) { xxcb_46(); } /* BIT 0,B=(XY+o) */ +OP(xxcb,41) { xxcb_46(); } /* BIT 0,C=(XY+o) */ +OP(xxcb,42) { xxcb_46(); } /* BIT 0,D=(XY+o) */ +OP(xxcb,43) { xxcb_46(); } /* BIT 0,E=(XY+o) */ +OP(xxcb,44) { xxcb_46(); } /* BIT 0,H=(XY+o) */ +OP(xxcb,45) { xxcb_46(); } /* BIT 0,L=(XY+o) */ +OP(xxcb,46) { BIT_XY(0,RM(EA)); } /* BIT 0,(XY+o) */ +OP(xxcb,47) { xxcb_46(); } /* BIT 0,A=(XY+o) */ + +OP(xxcb,48) { xxcb_4e(); } /* BIT 1,B=(XY+o) */ +OP(xxcb,49) { xxcb_4e(); } /* BIT 1,C=(XY+o) */ +OP(xxcb,4a) { xxcb_4e(); } /* BIT 1,D=(XY+o) */ +OP(xxcb,4b) { xxcb_4e(); } /* BIT 1,E=(XY+o) */ +OP(xxcb,4c) { xxcb_4e(); } /* BIT 1,H=(XY+o) */ +OP(xxcb,4d) { xxcb_4e(); } /* BIT 1,L=(XY+o) */ +OP(xxcb,4e) { BIT_XY(1,RM(EA)); } /* BIT 1,(XY+o) */ +OP(xxcb,4f) { xxcb_4e(); } /* BIT 1,A=(XY+o) */ + +OP(xxcb,50) { xxcb_56(); } /* BIT 2,B=(XY+o) */ +OP(xxcb,51) { xxcb_56(); } /* BIT 2,C=(XY+o) */ +OP(xxcb,52) { xxcb_56(); } /* BIT 2,D=(XY+o) */ +OP(xxcb,53) { xxcb_56(); } /* BIT 2,E=(XY+o) */ +OP(xxcb,54) { xxcb_56(); } /* BIT 2,H=(XY+o) */ +OP(xxcb,55) { xxcb_56(); } /* BIT 2,L=(XY+o) */ +OP(xxcb,56) { BIT_XY(2,RM(EA)); } /* BIT 2,(XY+o) */ +OP(xxcb,57) { xxcb_56(); } /* BIT 2,A=(XY+o) */ + +OP(xxcb,58) { xxcb_5e(); } /* BIT 3,B=(XY+o) */ +OP(xxcb,59) { xxcb_5e(); } /* BIT 3,C=(XY+o) */ +OP(xxcb,5a) { xxcb_5e(); } /* BIT 3,D=(XY+o) */ +OP(xxcb,5b) { xxcb_5e(); } /* BIT 3,E=(XY+o) */ +OP(xxcb,5c) { xxcb_5e(); } /* BIT 3,H=(XY+o) */ +OP(xxcb,5d) { xxcb_5e(); } /* BIT 3,L=(XY+o) */ +OP(xxcb,5e) { BIT_XY(3,RM(EA)); } /* BIT 3,(XY+o) */ +OP(xxcb,5f) { xxcb_5e(); } /* BIT 3,A=(XY+o) */ + +OP(xxcb,60) { xxcb_66(); } /* BIT 4,B=(XY+o) */ +OP(xxcb,61) { xxcb_66(); } /* BIT 4,C=(XY+o) */ +OP(xxcb,62) { xxcb_66(); } /* BIT 4,D=(XY+o) */ +OP(xxcb,63) { xxcb_66(); } /* BIT 4,E=(XY+o) */ +OP(xxcb,64) { xxcb_66(); } /* BIT 4,H=(XY+o) */ +OP(xxcb,65) { xxcb_66(); } /* BIT 4,L=(XY+o) */ +OP(xxcb,66) { BIT_XY(4,RM(EA)); } /* BIT 4,(XY+o) */ +OP(xxcb,67) { xxcb_66(); } /* BIT 4,A=(XY+o) */ + +OP(xxcb,68) { xxcb_6e(); } /* BIT 5,B=(XY+o) */ +OP(xxcb,69) { xxcb_6e(); } /* BIT 5,C=(XY+o) */ +OP(xxcb,6a) { xxcb_6e(); } /* BIT 5,D=(XY+o) */ +OP(xxcb,6b) { xxcb_6e(); } /* BIT 5,E=(XY+o) */ +OP(xxcb,6c) { xxcb_6e(); } /* BIT 5,H=(XY+o) */ +OP(xxcb,6d) { xxcb_6e(); } /* BIT 5,L=(XY+o) */ +OP(xxcb,6e) { BIT_XY(5,RM(EA)); } /* BIT 5,(XY+o) */ +OP(xxcb,6f) { xxcb_6e(); } /* BIT 5,A=(XY+o) */ + +OP(xxcb,70) { xxcb_76(); } /* BIT 6,B=(XY+o) */ +OP(xxcb,71) { xxcb_76(); } /* BIT 6,C=(XY+o) */ +OP(xxcb,72) { xxcb_76(); } /* BIT 6,D=(XY+o) */ +OP(xxcb,73) { xxcb_76(); } /* BIT 6,E=(XY+o) */ +OP(xxcb,74) { xxcb_76(); } /* BIT 6,H=(XY+o) */ +OP(xxcb,75) { xxcb_76(); } /* BIT 6,L=(XY+o) */ +OP(xxcb,76) { BIT_XY(6,RM(EA)); } /* BIT 6,(XY+o) */ +OP(xxcb,77) { xxcb_76(); } /* BIT 6,A=(XY+o) */ + +OP(xxcb,78) { xxcb_7e(); } /* BIT 7,B=(XY+o) */ +OP(xxcb,79) { xxcb_7e(); } /* BIT 7,C=(XY+o) */ +OP(xxcb,7a) { xxcb_7e(); } /* BIT 7,D=(XY+o) */ +OP(xxcb,7b) { xxcb_7e(); } /* BIT 7,E=(XY+o) */ +OP(xxcb,7c) { xxcb_7e(); } /* BIT 7,H=(XY+o) */ +OP(xxcb,7d) { xxcb_7e(); } /* BIT 7,L=(XY+o) */ +OP(xxcb,7e) { BIT_XY(7,RM(EA)); } /* BIT 7,(XY+o) */ +OP(xxcb,7f) { xxcb_7e(); } /* BIT 7,A=(XY+o) */ + +OP(xxcb,80) { _B = RES(0, RM(EA) ); WM( EA,_B ); } /* RES 0,B=(XY+o) */ +OP(xxcb,81) { _C = RES(0, RM(EA) ); WM( EA,_C ); } /* RES 0,C=(XY+o) */ +OP(xxcb,82) { _D = RES(0, RM(EA) ); WM( EA,_D ); } /* RES 0,D=(XY+o) */ +OP(xxcb,83) { _E = RES(0, RM(EA) ); WM( EA,_E ); } /* RES 0,E=(XY+o) */ +OP(xxcb,84) { _H = RES(0, RM(EA) ); WM( EA,_H ); } /* RES 0,H=(XY+o) */ +OP(xxcb,85) { _L = RES(0, RM(EA) ); WM( EA,_L ); } /* RES 0,L=(XY+o) */ +OP(xxcb,86) { WM( EA, RES(0,RM(EA)) ); } /* RES 0,(XY+o) */ +OP(xxcb,87) { _A = RES(0, RM(EA) ); WM( EA,_A ); } /* RES 0,A=(XY+o) */ + +OP(xxcb,88) { _B = RES(1, RM(EA) ); WM( EA,_B ); } /* RES 1,B=(XY+o) */ +OP(xxcb,89) { _C = RES(1, RM(EA) ); WM( EA,_C ); } /* RES 1,C=(XY+o) */ +OP(xxcb,8a) { _D = RES(1, RM(EA) ); WM( EA,_D ); } /* RES 1,D=(XY+o) */ +OP(xxcb,8b) { _E = RES(1, RM(EA) ); WM( EA,_E ); } /* RES 1,E=(XY+o) */ +OP(xxcb,8c) { _H = RES(1, RM(EA) ); WM( EA,_H ); } /* RES 1,H=(XY+o) */ +OP(xxcb,8d) { _L = RES(1, RM(EA) ); WM( EA,_L ); } /* RES 1,L=(XY+o) */ +OP(xxcb,8e) { WM( EA, RES(1,RM(EA)) ); } /* RES 1,(XY+o) */ +OP(xxcb,8f) { _A = RES(1, RM(EA) ); WM( EA,_A ); } /* RES 1,A=(XY+o) */ + +OP(xxcb,90) { _B = RES(2, RM(EA) ); WM( EA,_B ); } /* RES 2,B=(XY+o) */ +OP(xxcb,91) { _C = RES(2, RM(EA) ); WM( EA,_C ); } /* RES 2,C=(XY+o) */ +OP(xxcb,92) { _D = RES(2, RM(EA) ); WM( EA,_D ); } /* RES 2,D=(XY+o) */ +OP(xxcb,93) { _E = RES(2, RM(EA) ); WM( EA,_E ); } /* RES 2,E=(XY+o) */ +OP(xxcb,94) { _H = RES(2, RM(EA) ); WM( EA,_H ); } /* RES 2,H=(XY+o) */ +OP(xxcb,95) { _L = RES(2, RM(EA) ); WM( EA,_L ); } /* RES 2,L=(XY+o) */ +OP(xxcb,96) { WM( EA, RES(2,RM(EA)) ); } /* RES 2,(XY+o) */ +OP(xxcb,97) { _A = RES(2, RM(EA) ); WM( EA,_A ); } /* RES 2,A=(XY+o) */ + +OP(xxcb,98) { _B = RES(3, RM(EA) ); WM( EA,_B ); } /* RES 3,B=(XY+o) */ +OP(xxcb,99) { _C = RES(3, RM(EA) ); WM( EA,_C ); } /* RES 3,C=(XY+o) */ +OP(xxcb,9a) { _D = RES(3, RM(EA) ); WM( EA,_D ); } /* RES 3,D=(XY+o) */ +OP(xxcb,9b) { _E = RES(3, RM(EA) ); WM( EA,_E ); } /* RES 3,E=(XY+o) */ +OP(xxcb,9c) { _H = RES(3, RM(EA) ); WM( EA,_H ); } /* RES 3,H=(XY+o) */ +OP(xxcb,9d) { _L = RES(3, RM(EA) ); WM( EA,_L ); } /* RES 3,L=(XY+o) */ +OP(xxcb,9e) { WM( EA, RES(3,RM(EA)) ); } /* RES 3,(XY+o) */ +OP(xxcb,9f) { _A = RES(3, RM(EA) ); WM( EA,_A ); } /* RES 3,A=(XY+o) */ + +OP(xxcb,a0) { _B = RES(4, RM(EA) ); WM( EA,_B ); } /* RES 4,B=(XY+o) */ +OP(xxcb,a1) { _C = RES(4, RM(EA) ); WM( EA,_C ); } /* RES 4,C=(XY+o) */ +OP(xxcb,a2) { _D = RES(4, RM(EA) ); WM( EA,_D ); } /* RES 4,D=(XY+o) */ +OP(xxcb,a3) { _E = RES(4, RM(EA) ); WM( EA,_E ); } /* RES 4,E=(XY+o) */ +OP(xxcb,a4) { _H = RES(4, RM(EA) ); WM( EA,_H ); } /* RES 4,H=(XY+o) */ +OP(xxcb,a5) { _L = RES(4, RM(EA) ); WM( EA,_L ); } /* RES 4,L=(XY+o) */ +OP(xxcb,a6) { WM( EA, RES(4,RM(EA)) ); } /* RES 4,(XY+o) */ +OP(xxcb,a7) { _A = RES(4, RM(EA) ); WM( EA,_A ); } /* RES 4,A=(XY+o) */ + +OP(xxcb,a8) { _B = RES(5, RM(EA) ); WM( EA,_B ); } /* RES 5,B=(XY+o) */ +OP(xxcb,a9) { _C = RES(5, RM(EA) ); WM( EA,_C ); } /* RES 5,C=(XY+o) */ +OP(xxcb,aa) { _D = RES(5, RM(EA) ); WM( EA,_D ); } /* RES 5,D=(XY+o) */ +OP(xxcb,ab) { _E = RES(5, RM(EA) ); WM( EA,_E ); } /* RES 5,E=(XY+o) */ +OP(xxcb,ac) { _H = RES(5, RM(EA) ); WM( EA,_H ); } /* RES 5,H=(XY+o) */ +OP(xxcb,ad) { _L = RES(5, RM(EA) ); WM( EA,_L ); } /* RES 5,L=(XY+o) */ +OP(xxcb,ae) { WM( EA, RES(5,RM(EA)) ); } /* RES 5,(XY+o) */ +OP(xxcb,af) { _A = RES(5, RM(EA) ); WM( EA,_A ); } /* RES 5,A=(XY+o) */ + +OP(xxcb,b0) { _B = RES(6, RM(EA) ); WM( EA,_B ); } /* RES 6,B=(XY+o) */ +OP(xxcb,b1) { _C = RES(6, RM(EA) ); WM( EA,_C ); } /* RES 6,C=(XY+o) */ +OP(xxcb,b2) { _D = RES(6, RM(EA) ); WM( EA,_D ); } /* RES 6,D=(XY+o) */ +OP(xxcb,b3) { _E = RES(6, RM(EA) ); WM( EA,_E ); } /* RES 6,E=(XY+o) */ +OP(xxcb,b4) { _H = RES(6, RM(EA) ); WM( EA,_H ); } /* RES 6,H=(XY+o) */ +OP(xxcb,b5) { _L = RES(6, RM(EA) ); WM( EA,_L ); } /* RES 6,L=(XY+o) */ +OP(xxcb,b6) { WM( EA, RES(6,RM(EA)) ); } /* RES 6,(XY+o) */ +OP(xxcb,b7) { _A = RES(6, RM(EA) ); WM( EA,_A ); } /* RES 6,A=(XY+o) */ + +OP(xxcb,b8) { _B = RES(7, RM(EA) ); WM( EA,_B ); } /* RES 7,B=(XY+o) */ +OP(xxcb,b9) { _C = RES(7, RM(EA) ); WM( EA,_C ); } /* RES 7,C=(XY+o) */ +OP(xxcb,ba) { _D = RES(7, RM(EA) ); WM( EA,_D ); } /* RES 7,D=(XY+o) */ +OP(xxcb,bb) { _E = RES(7, RM(EA) ); WM( EA,_E ); } /* RES 7,E=(XY+o) */ +OP(xxcb,bc) { _H = RES(7, RM(EA) ); WM( EA,_H ); } /* RES 7,H=(XY+o) */ +OP(xxcb,bd) { _L = RES(7, RM(EA) ); WM( EA,_L ); } /* RES 7,L=(XY+o) */ +OP(xxcb,be) { WM( EA, RES(7,RM(EA)) ); } /* RES 7,(XY+o) */ +OP(xxcb,bf) { _A = RES(7, RM(EA) ); WM( EA,_A ); } /* RES 7,A=(XY+o) */ + +OP(xxcb,c0) { _B = SET(0, RM(EA) ); WM( EA,_B ); } /* SET 0,B=(XY+o) */ +OP(xxcb,c1) { _C = SET(0, RM(EA) ); WM( EA,_C ); } /* SET 0,C=(XY+o) */ +OP(xxcb,c2) { _D = SET(0, RM(EA) ); WM( EA,_D ); } /* SET 0,D=(XY+o) */ +OP(xxcb,c3) { _E = SET(0, RM(EA) ); WM( EA,_E ); } /* SET 0,E=(XY+o) */ +OP(xxcb,c4) { _H = SET(0, RM(EA) ); WM( EA,_H ); } /* SET 0,H=(XY+o) */ +OP(xxcb,c5) { _L = SET(0, RM(EA) ); WM( EA,_L ); } /* SET 0,L=(XY+o) */ +OP(xxcb,c6) { WM( EA, SET(0,RM(EA)) ); } /* SET 0,(XY+o) */ +OP(xxcb,c7) { _A = SET(0, RM(EA) ); WM( EA,_A ); } /* SET 0,A=(XY+o) */ + +OP(xxcb,c8) { _B = SET(1, RM(EA) ); WM( EA,_B ); } /* SET 1,B=(XY+o) */ +OP(xxcb,c9) { _C = SET(1, RM(EA) ); WM( EA,_C ); } /* SET 1,C=(XY+o) */ +OP(xxcb,ca) { _D = SET(1, RM(EA) ); WM( EA,_D ); } /* SET 1,D=(XY+o) */ +OP(xxcb,cb) { _E = SET(1, RM(EA) ); WM( EA,_E ); } /* SET 1,E=(XY+o) */ +OP(xxcb,cc) { _H = SET(1, RM(EA) ); WM( EA,_H ); } /* SET 1,H=(XY+o) */ +OP(xxcb,cd) { _L = SET(1, RM(EA) ); WM( EA,_L ); } /* SET 1,L=(XY+o) */ +OP(xxcb,ce) { WM( EA, SET(1,RM(EA)) ); } /* SET 1,(XY+o) */ +OP(xxcb,cf) { _A = SET(1, RM(EA) ); WM( EA,_A ); } /* SET 1,A=(XY+o) */ + +OP(xxcb,d0) { _B = SET(2, RM(EA) ); WM( EA,_B ); } /* SET 2,B=(XY+o) */ +OP(xxcb,d1) { _C = SET(2, RM(EA) ); WM( EA,_C ); } /* SET 2,C=(XY+o) */ +OP(xxcb,d2) { _D = SET(2, RM(EA) ); WM( EA,_D ); } /* SET 2,D=(XY+o) */ +OP(xxcb,d3) { _E = SET(2, RM(EA) ); WM( EA,_E ); } /* SET 2,E=(XY+o) */ +OP(xxcb,d4) { _H = SET(2, RM(EA) ); WM( EA,_H ); } /* SET 2,H=(XY+o) */ +OP(xxcb,d5) { _L = SET(2, RM(EA) ); WM( EA,_L ); } /* SET 2,L=(XY+o) */ +OP(xxcb,d6) { WM( EA, SET(2,RM(EA)) ); } /* SET 2,(XY+o) */ +OP(xxcb,d7) { _A = SET(2, RM(EA) ); WM( EA,_A ); } /* SET 2,A=(XY+o) */ + +OP(xxcb,d8) { _B = SET(3, RM(EA) ); WM( EA,_B ); } /* SET 3,B=(XY+o) */ +OP(xxcb,d9) { _C = SET(3, RM(EA) ); WM( EA,_C ); } /* SET 3,C=(XY+o) */ +OP(xxcb,da) { _D = SET(3, RM(EA) ); WM( EA,_D ); } /* SET 3,D=(XY+o) */ +OP(xxcb,db) { _E = SET(3, RM(EA) ); WM( EA,_E ); } /* SET 3,E=(XY+o) */ +OP(xxcb,dc) { _H = SET(3, RM(EA) ); WM( EA,_H ); } /* SET 3,H=(XY+o) */ +OP(xxcb,dd) { _L = SET(3, RM(EA) ); WM( EA,_L ); } /* SET 3,L=(XY+o) */ +OP(xxcb,de) { WM( EA, SET(3,RM(EA)) ); } /* SET 3,(XY+o) */ +OP(xxcb,df) { _A = SET(3, RM(EA) ); WM( EA,_A ); } /* SET 3,A=(XY+o) */ + +OP(xxcb,e0) { _B = SET(4, RM(EA) ); WM( EA,_B ); } /* SET 4,B=(XY+o) */ +OP(xxcb,e1) { _C = SET(4, RM(EA) ); WM( EA,_C ); } /* SET 4,C=(XY+o) */ +OP(xxcb,e2) { _D = SET(4, RM(EA) ); WM( EA,_D ); } /* SET 4,D=(XY+o) */ +OP(xxcb,e3) { _E = SET(4, RM(EA) ); WM( EA,_E ); } /* SET 4,E=(XY+o) */ +OP(xxcb,e4) { _H = SET(4, RM(EA) ); WM( EA,_H ); } /* SET 4,H=(XY+o) */ +OP(xxcb,e5) { _L = SET(4, RM(EA) ); WM( EA,_L ); } /* SET 4,L=(XY+o) */ +OP(xxcb,e6) { WM( EA, SET(4,RM(EA)) ); } /* SET 4,(XY+o) */ +OP(xxcb,e7) { _A = SET(4, RM(EA) ); WM( EA,_A ); } /* SET 4,A=(XY+o) */ + +OP(xxcb,e8) { _B = SET(5, RM(EA) ); WM( EA,_B ); } /* SET 5,B=(XY+o) */ +OP(xxcb,e9) { _C = SET(5, RM(EA) ); WM( EA,_C ); } /* SET 5,C=(XY+o) */ +OP(xxcb,ea) { _D = SET(5, RM(EA) ); WM( EA,_D ); } /* SET 5,D=(XY+o) */ +OP(xxcb,eb) { _E = SET(5, RM(EA) ); WM( EA,_E ); } /* SET 5,E=(XY+o) */ +OP(xxcb,ec) { _H = SET(5, RM(EA) ); WM( EA,_H ); } /* SET 5,H=(XY+o) */ +OP(xxcb,ed) { _L = SET(5, RM(EA) ); WM( EA,_L ); } /* SET 5,L=(XY+o) */ +OP(xxcb,ee) { WM( EA, SET(5,RM(EA)) ); } /* SET 5,(XY+o) */ +OP(xxcb,ef) { _A = SET(5, RM(EA) ); WM( EA,_A ); } /* SET 5,A=(XY+o) */ + +OP(xxcb,f0) { _B = SET(6, RM(EA) ); WM( EA,_B ); } /* SET 6,B=(XY+o) */ +OP(xxcb,f1) { _C = SET(6, RM(EA) ); WM( EA,_C ); } /* SET 6,C=(XY+o) */ +OP(xxcb,f2) { _D = SET(6, RM(EA) ); WM( EA,_D ); } /* SET 6,D=(XY+o) */ +OP(xxcb,f3) { _E = SET(6, RM(EA) ); WM( EA,_E ); } /* SET 6,E=(XY+o) */ +OP(xxcb,f4) { _H = SET(6, RM(EA) ); WM( EA,_H ); } /* SET 6,H=(XY+o) */ +OP(xxcb,f5) { _L = SET(6, RM(EA) ); WM( EA,_L ); } /* SET 6,L=(XY+o) */ +OP(xxcb,f6) { WM( EA, SET(6,RM(EA)) ); } /* SET 6,(XY+o) */ +OP(xxcb,f7) { _A = SET(6, RM(EA) ); WM( EA,_A ); } /* SET 6,A=(XY+o) */ + +OP(xxcb,f8) { _B = SET(7, RM(EA) ); WM( EA,_B ); } /* SET 7,B=(XY+o) */ +OP(xxcb,f9) { _C = SET(7, RM(EA) ); WM( EA,_C ); } /* SET 7,C=(XY+o) */ +OP(xxcb,fa) { _D = SET(7, RM(EA) ); WM( EA,_D ); } /* SET 7,D=(XY+o) */ +OP(xxcb,fb) { _E = SET(7, RM(EA) ); WM( EA,_E ); } /* SET 7,E=(XY+o) */ +OP(xxcb,fc) { _H = SET(7, RM(EA) ); WM( EA,_H ); } /* SET 7,H=(XY+o) */ +OP(xxcb,fd) { _L = SET(7, RM(EA) ); WM( EA,_L ); } /* SET 7,L=(XY+o) */ +OP(xxcb,fe) { WM( EA, SET(7,RM(EA)) ); } /* SET 7,(XY+o) */ +OP(xxcb,ff) { _A = SET(7, RM(EA) ); WM( EA,_A ); } /* SET 7,A=(XY+o) */ + +OP(illegal,1) { + _PC--; +} + +/********************************************************** + * IX register related opcodes (DD prefix) + **********************************************************/ +OP(dd,00) { illegal_1(); } /* DB DD */ +OP(dd,01) { illegal_1(); } /* DB DD */ +OP(dd,02) { illegal_1(); } /* DB DD */ +OP(dd,03) { illegal_1(); } /* DB DD */ +OP(dd,04) { illegal_1(); } /* DB DD */ +OP(dd,05) { illegal_1(); } /* DB DD */ +OP(dd,06) { illegal_1(); } /* DB DD */ +OP(dd,07) { illegal_1(); } /* DB DD */ + +OP(dd,08) { illegal_1(); } /* DB DD */ +OP(dd,09) { ADD16(IX,BC); } /* ADD IX,BC */ +OP(dd,0a) { illegal_1(); } /* DB DD */ +OP(dd,0b) { illegal_1(); } /* DB DD */ +OP(dd,0c) { illegal_1(); } /* DB DD */ +OP(dd,0d) { illegal_1(); } /* DB DD */ +OP(dd,0e) { illegal_1(); } /* DB DD */ +OP(dd,0f) { illegal_1(); } /* DB DD */ + +OP(dd,10) { illegal_1(); } /* DB DD */ +OP(dd,11) { illegal_1(); } /* DB DD */ +OP(dd,12) { illegal_1(); } /* DB DD */ +OP(dd,13) { illegal_1(); } /* DB DD */ +OP(dd,14) { illegal_1(); } /* DB DD */ +OP(dd,15) { illegal_1(); } /* DB DD */ +OP(dd,16) { illegal_1(); } /* DB DD */ +OP(dd,17) { illegal_1(); } /* DB DD */ + +OP(dd,18) { illegal_1(); } /* DB DD */ +OP(dd,19) { ADD16(IX,DE); } /* ADD IX,DE */ +OP(dd,1a) { illegal_1(); } /* DB DD */ +OP(dd,1b) { illegal_1(); } /* DB DD */ +OP(dd,1c) { illegal_1(); } /* DB DD */ +OP(dd,1d) { illegal_1(); } /* DB DD */ +OP(dd,1e) { illegal_1(); } /* DB DD */ +OP(dd,1f) { illegal_1(); } /* DB DD */ + +OP(dd,20) { illegal_1(); } /* DB DD */ +OP(dd,21) { _IX = ARG16(); } /* LD IX,w */ +OP(dd,22) { EA = ARG16(); WM16( EA, &Z80.IX ); } /* LD (w),IX */ +OP(dd,23) { _IX++; } /* INC IX */ +OP(dd,24) { _HX = INC(_HX); } /* INC HX */ +OP(dd,25) { _HX = DEC(_HX); } /* DEC HX */ +OP(dd,26) { _HX = ARG(); } /* LD HX,n */ +OP(dd,27) { illegal_1(); } /* DB DD */ + +OP(dd,28) { illegal_1(); } /* DB DD */ +OP(dd,29) { ADD16(IX,IX); } /* ADD IX,IX */ +OP(dd,2a) { EA = ARG16(); RM16( EA, &Z80.IX ); } /* LD IX,(w) */ +OP(dd,2b) { _IX--; } /* DEC IX */ +OP(dd,2c) { _LX = INC(_LX); } /* INC LX */ +OP(dd,2d) { _LX = DEC(_LX); } /* DEC LX */ +OP(dd,2e) { _LX = ARG(); } /* LD LX,n */ +OP(dd,2f) { illegal_1(); } /* DB DD */ + +OP(dd,30) { illegal_1(); } /* DB DD */ +OP(dd,31) { illegal_1(); } /* DB DD */ +OP(dd,32) { illegal_1(); } /* DB DD */ +OP(dd,33) { illegal_1(); } /* DB DD */ +OP(dd,34) { EAX; WM( EA, INC(RM(EA)) ); } /* INC (IX+o) */ +OP(dd,35) { EAX; WM( EA, DEC(RM(EA)) ); } /* DEC (IX+o) */ +OP(dd,36) { EAX; WM( EA, ARG() ); } /* LD (IX+o),n */ +OP(dd,37) { illegal_1(); } /* DB DD */ + +OP(dd,38) { illegal_1(); } /* DB DD */ +OP(dd,39) { ADD16(IX,SP); } /* ADD IX,SP */ +OP(dd,3a) { illegal_1(); } /* DB DD */ +OP(dd,3b) { illegal_1(); } /* DB DD */ +OP(dd,3c) { illegal_1(); } /* DB DD */ +OP(dd,3d) { illegal_1(); } /* DB DD */ +OP(dd,3e) { illegal_1(); } /* DB DD */ +OP(dd,3f) { illegal_1(); } /* DB DD */ + +OP(dd,40) { illegal_1(); } /* DB DD */ +OP(dd,41) { illegal_1(); } /* DB DD */ +OP(dd,42) { illegal_1(); } /* DB DD */ +OP(dd,43) { illegal_1(); } /* DB DD */ +OP(dd,44) { _B = _HX; } /* LD B,HX */ +OP(dd,45) { _B = _LX; } /* LD B,LX */ +OP(dd,46) { EAX; _B = RM(EA); } /* LD B,(IX+o) */ +OP(dd,47) { illegal_1(); } /* DB DD */ + +OP(dd,48) { illegal_1(); } /* DB DD */ +OP(dd,49) { illegal_1(); } /* DB DD */ +OP(dd,4a) { illegal_1(); } /* DB DD */ +OP(dd,4b) { illegal_1(); } /* DB DD */ +OP(dd,4c) { _C = _HX; } /* LD C,HX */ +OP(dd,4d) { _C = _LX; } /* LD C,LX */ +OP(dd,4e) { EAX; _C = RM(EA); } /* LD C,(IX+o) */ +OP(dd,4f) { illegal_1(); } /* DB DD */ + +OP(dd,50) { illegal_1(); } /* DB DD */ +OP(dd,51) { illegal_1(); } /* DB DD */ +OP(dd,52) { illegal_1(); } /* DB DD */ +OP(dd,53) { illegal_1(); } /* DB DD */ +OP(dd,54) { _D = _HX; } /* LD D,HX */ +OP(dd,55) { _D = _LX; } /* LD D,LX */ +OP(dd,56) { EAX; _D = RM(EA); } /* LD D,(IX+o) */ +OP(dd,57) { illegal_1(); } /* DB DD */ + +OP(dd,58) { illegal_1(); } /* DB DD */ +OP(dd,59) { illegal_1(); } /* DB DD */ +OP(dd,5a) { illegal_1(); } /* DB DD */ +OP(dd,5b) { illegal_1(); } /* DB DD */ +OP(dd,5c) { _E = _HX; } /* LD E,HX */ +OP(dd,5d) { _E = _LX; } /* LD E,LX */ +OP(dd,5e) { EAX; _E = RM(EA); } /* LD E,(IX+o) */ +OP(dd,5f) { illegal_1(); } /* DB DD */ + +OP(dd,60) { _HX = _B; } /* LD HX,B */ +OP(dd,61) { _HX = _C; } /* LD HX,C */ +OP(dd,62) { _HX = _D; } /* LD HX,D */ +OP(dd,63) { _HX = _E; } /* LD HX,E */ +OP(dd,64) { } /* LD HX,HX */ +OP(dd,65) { _HX = _LX; } /* LD HX,LX */ +OP(dd,66) { EAX; _H = RM(EA); } /* LD H,(IX+o) */ +OP(dd,67) { _HX = _A; } /* LD HX,A */ + +OP(dd,68) { _LX = _B; } /* LD LX,B */ +OP(dd,69) { _LX = _C; } /* LD LX,C */ +OP(dd,6a) { _LX = _D; } /* LD LX,D */ +OP(dd,6b) { _LX = _E; } /* LD LX,E */ +OP(dd,6c) { _LX = _HX; } /* LD LX,HX */ +OP(dd,6d) { } /* LD LX,LX */ +OP(dd,6e) { EAX; _L = RM(EA); } /* LD L,(IX+o) */ +OP(dd,6f) { _LX = _A; } /* LD LX,A */ + +OP(dd,70) { EAX; WM( EA, _B ); } /* LD (IX+o),B */ +OP(dd,71) { EAX; WM( EA, _C ); } /* LD (IX+o),C */ +OP(dd,72) { EAX; WM( EA, _D ); } /* LD (IX+o),D */ +OP(dd,73) { EAX; WM( EA, _E ); } /* LD (IX+o),E */ +OP(dd,74) { EAX; WM( EA, _H ); } /* LD (IX+o),H */ +OP(dd,75) { EAX; WM( EA, _L ); } /* LD (IX+o),L */ +OP(dd,76) { illegal_1(); } /* DB DD */ +OP(dd,77) { EAX; WM( EA, _A ); } /* LD (IX+o),A */ + +OP(dd,78) { illegal_1(); } /* DB DD */ +OP(dd,79) { illegal_1(); } /* DB DD */ +OP(dd,7a) { illegal_1(); } /* DB DD */ +OP(dd,7b) { illegal_1(); } /* DB DD */ +OP(dd,7c) { _A = _HX; } /* LD A,HX */ +OP(dd,7d) { _A = _LX; } /* LD A,LX */ +OP(dd,7e) { EAX; _A = RM(EA); } /* LD A,(IX+o) */ +OP(dd,7f) { illegal_1(); } /* DB DD */ + +OP(dd,80) { illegal_1(); } /* DB DD */ +OP(dd,81) { illegal_1(); } /* DB DD */ +OP(dd,82) { illegal_1(); } /* DB DD */ +OP(dd,83) { illegal_1(); } /* DB DD */ +OP(dd,84) { ADD(_HX); } /* ADD A,HX */ +OP(dd,85) { ADD(_LX); } /* ADD A,LX */ +OP(dd,86) { EAX; ADD(RM(EA)); } /* ADD A,(IX+o) */ +OP(dd,87) { illegal_1(); } /* DB DD */ + +OP(dd,88) { illegal_1(); } /* DB DD */ +OP(dd,89) { illegal_1(); } /* DB DD */ +OP(dd,8a) { illegal_1(); } /* DB DD */ +OP(dd,8b) { illegal_1(); } /* DB DD */ +OP(dd,8c) { ADC(_HX); } /* ADC A,HX */ +OP(dd,8d) { ADC(_LX); } /* ADC A,LX */ +OP(dd,8e) { EAX; ADC(RM(EA)); } /* ADC A,(IX+o) */ +OP(dd,8f) { illegal_1(); } /* DB DD */ + +OP(dd,90) { illegal_1(); } /* DB DD */ +OP(dd,91) { illegal_1(); } /* DB DD */ +OP(dd,92) { illegal_1(); } /* DB DD */ +OP(dd,93) { illegal_1(); } /* DB DD */ +OP(dd,94) { SUB(_HX); } /* SUB HX */ +OP(dd,95) { SUB(_LX); } /* SUB LX */ +OP(dd,96) { EAX; SUB(RM(EA)); } /* SUB (IX+o) */ +OP(dd,97) { illegal_1(); } /* DB DD */ + +OP(dd,98) { illegal_1(); } /* DB DD */ +OP(dd,99) { illegal_1(); } /* DB DD */ +OP(dd,9a) { illegal_1(); } /* DB DD */ +OP(dd,9b) { illegal_1(); } /* DB DD */ +OP(dd,9c) { SBC(_HX); } /* SBC A,HX */ +OP(dd,9d) { SBC(_LX); } /* SBC A,LX */ +OP(dd,9e) { EAX; SBC(RM(EA)); } /* SBC A,(IX+o) */ +OP(dd,9f) { illegal_1(); } /* DB DD */ + +OP(dd,a0) { illegal_1(); } /* DB DD */ +OP(dd,a1) { illegal_1(); } /* DB DD */ +OP(dd,a2) { illegal_1(); } /* DB DD */ +OP(dd,a3) { illegal_1(); } /* DB DD */ +OP(dd,a4) { AND(_HX); } /* AND HX */ +OP(dd,a5) { AND(_LX); } /* AND LX */ +OP(dd,a6) { EAX; AND(RM(EA)); } /* AND (IX+o) */ +OP(dd,a7) { illegal_1(); } /* DB DD */ + +OP(dd,a8) { illegal_1(); } /* DB DD */ +OP(dd,a9) { illegal_1(); } /* DB DD */ +OP(dd,aa) { illegal_1(); } /* DB DD */ +OP(dd,ab) { illegal_1(); } /* DB DD */ +OP(dd,ac) { XOR(_HX); } /* XOR HX */ +OP(dd,ad) { XOR(_LX); } /* XOR LX */ +OP(dd,ae) { EAX; XOR(RM(EA)); } /* XOR (IX+o) */ +OP(dd,af) { illegal_1(); } /* DB DD */ + +OP(dd,b0) { illegal_1(); } /* DB DD */ +OP(dd,b1) { illegal_1(); } /* DB DD */ +OP(dd,b2) { illegal_1(); } /* DB DD */ +OP(dd,b3) { illegal_1(); } /* DB DD */ +OP(dd,b4) { OR(_HX); } /* OR HX */ +OP(dd,b5) { OR(_LX); } /* OR LX */ +OP(dd,b6) { EAX; OR(RM(EA)); } /* OR (IX+o) */ +OP(dd,b7) { illegal_1(); } /* DB DD */ + +OP(dd,b8) { illegal_1(); } /* DB DD */ +OP(dd,b9) { illegal_1(); } /* DB DD */ +OP(dd,ba) { illegal_1(); } /* DB DD */ +OP(dd,bb) { illegal_1(); } /* DB DD */ +OP(dd,bc) { CP(_HX); } /* CP HX */ +OP(dd,bd) { CP(_LX); } /* CP LX */ +OP(dd,be) { EAX; CP(RM(EA)); } /* CP (IX+o) */ +OP(dd,bf) { illegal_1(); } /* DB DD */ + +OP(dd,c0) { illegal_1(); } /* DB DD */ +OP(dd,c1) { illegal_1(); } /* DB DD */ +OP(dd,c2) { illegal_1(); } /* DB DD */ +OP(dd,c3) { illegal_1(); } /* DB DD */ +OP(dd,c4) { illegal_1(); } /* DB DD */ +OP(dd,c5) { illegal_1(); } /* DB DD */ +OP(dd,c6) { illegal_1(); } /* DB DD */ +OP(dd,c7) { illegal_1(); } /* DB DD */ + +OP(dd,c8) { illegal_1(); } /* DB DD */ +OP(dd,c9) { illegal_1(); } /* DB DD */ +OP(dd,ca) { illegal_1(); } /* DB DD */ +OP(dd,cb) { EAX; EXEC(xxcb,ARG()); } /* ** DD CB xx */ +OP(dd,cc) { illegal_1(); } /* DB DD */ +OP(dd,cd) { illegal_1(); } /* DB DD */ +OP(dd,ce) { illegal_1(); } /* DB DD */ +OP(dd,cf) { illegal_1(); } /* DB DD */ + +OP(dd,d0) { illegal_1(); } /* DB DD */ +OP(dd,d1) { illegal_1(); } /* DB DD */ +OP(dd,d2) { illegal_1(); } /* DB DD */ +OP(dd,d3) { illegal_1(); } /* DB DD */ +OP(dd,d4) { illegal_1(); } /* DB DD */ +OP(dd,d5) { illegal_1(); } /* DB DD */ +OP(dd,d6) { illegal_1(); } /* DB DD */ +OP(dd,d7) { illegal_1(); } /* DB DD */ + +OP(dd,d8) { illegal_1(); } /* DB DD */ +OP(dd,d9) { illegal_1(); } /* DB DD */ +OP(dd,da) { illegal_1(); } /* DB DD */ +OP(dd,db) { illegal_1(); } /* DB DD */ +OP(dd,dc) { illegal_1(); } /* DB DD */ +OP(dd,dd) { illegal_1(); } /* DB DD */ +OP(dd,de) { illegal_1(); } /* DB DD */ +OP(dd,df) { illegal_1(); } /* DB DD */ + +OP(dd,e0) { illegal_1(); } /* DB DD */ +OP(dd,e1) { POP(IX); } /* POP IX */ +OP(dd,e2) { illegal_1(); } /* DB DD */ +OP(dd,e3) { EXSP(IX); } /* EX (SP),IX */ +OP(dd,e4) { illegal_1(); } /* DB DD */ +OP(dd,e5) { PUSH( IX ); } /* PUSH IX */ +OP(dd,e6) { illegal_1(); } /* DB DD */ +OP(dd,e7) { illegal_1(); } /* DB DD */ + +OP(dd,e8) { illegal_1(); } /* DB DD */ +OP(dd,e9) { _PC = _IX; } /* JP (IX) */ +OP(dd,ea) { illegal_1(); } /* DB DD */ +OP(dd,eb) { illegal_1(); } /* DB DD */ +OP(dd,ec) { illegal_1(); } /* DB DD */ +OP(dd,ed) { illegal_1(); } /* DB DD */ +OP(dd,ee) { illegal_1(); } /* DB DD */ +OP(dd,ef) { illegal_1(); } /* DB DD */ + +OP(dd,f0) { illegal_1(); } /* DB DD */ +OP(dd,f1) { illegal_1(); } /* DB DD */ +OP(dd,f2) { illegal_1(); } /* DB DD */ +OP(dd,f3) { illegal_1(); } /* DB DD */ +OP(dd,f4) { illegal_1(); } /* DB DD */ +OP(dd,f5) { illegal_1(); } /* DB DD */ +OP(dd,f6) { illegal_1(); } /* DB DD */ +OP(dd,f7) { illegal_1(); } /* DB DD */ + +OP(dd,f8) { illegal_1(); } /* DB DD */ +OP(dd,f9) { _SP = _IX; } /* LD SP,IX */ +OP(dd,fa) { illegal_1(); } /* DB DD */ +OP(dd,fb) { illegal_1(); } /* DB DD */ +OP(dd,fc) { illegal_1(); } /* DB DD */ +OP(dd,fd) { illegal_1(); } /* DB DD */ +OP(dd,fe) { illegal_1(); } /* DB DD */ +OP(dd,ff) { illegal_1(); } /* DB DD */ + +/********************************************************** + * IY register related opcodes (FD prefix) + **********************************************************/ +OP(fd,00) { illegal_1(); } /* DB FD */ +OP(fd,01) { illegal_1(); } /* DB FD */ +OP(fd,02) { illegal_1(); } /* DB FD */ +OP(fd,03) { illegal_1(); } /* DB FD */ +OP(fd,04) { illegal_1(); } /* DB FD */ +OP(fd,05) { illegal_1(); } /* DB FD */ +OP(fd,06) { illegal_1(); } /* DB FD */ +OP(fd,07) { illegal_1(); } /* DB FD */ + +OP(fd,08) { illegal_1(); } /* DB FD */ +OP(fd,09) { ADD16(IY,BC); } /* ADD IY,BC */ +OP(fd,0a) { illegal_1(); } /* DB FD */ +OP(fd,0b) { illegal_1(); } /* DB FD */ +OP(fd,0c) { illegal_1(); } /* DB FD */ +OP(fd,0d) { illegal_1(); } /* DB FD */ +OP(fd,0e) { illegal_1(); } /* DB FD */ +OP(fd,0f) { illegal_1(); } /* DB FD */ + +OP(fd,10) { illegal_1(); } /* DB FD */ +OP(fd,11) { illegal_1(); } /* DB FD */ +OP(fd,12) { illegal_1(); } /* DB FD */ +OP(fd,13) { illegal_1(); } /* DB FD */ +OP(fd,14) { illegal_1(); } /* DB FD */ +OP(fd,15) { illegal_1(); } /* DB FD */ +OP(fd,16) { illegal_1(); } /* DB FD */ +OP(fd,17) { illegal_1(); } /* DB FD */ + +OP(fd,18) { illegal_1(); } /* DB FD */ +OP(fd,19) { ADD16(IY,DE); } /* ADD IY,DE */ +OP(fd,1a) { illegal_1(); } /* DB FD */ +OP(fd,1b) { illegal_1(); } /* DB FD */ +OP(fd,1c) { illegal_1(); } /* DB FD */ +OP(fd,1d) { illegal_1(); } /* DB FD */ +OP(fd,1e) { illegal_1(); } /* DB FD */ +OP(fd,1f) { illegal_1(); } /* DB FD */ + +OP(fd,20) { illegal_1(); } /* DB FD */ +OP(fd,21) { _IY = ARG16(); } /* LD IY,w */ +OP(fd,22) { EA = ARG16(); WM16( EA, &Z80.IY ); } /* LD (w),IY */ +OP(fd,23) { _IY++; } /* INC IY */ +OP(fd,24) { _HY = INC(_HY); } /* INC HY */ +OP(fd,25) { _HY = DEC(_HY); } /* DEC HY */ +OP(fd,26) { _HY = ARG(); } /* LD HY,n */ +OP(fd,27) { illegal_1(); } /* DB FD */ + +OP(fd,28) { illegal_1(); } /* DB FD */ +OP(fd,29) { ADD16(IY,IY); } /* ADD IY,IY */ +OP(fd,2a) { EA = ARG16(); RM16( EA, &Z80.IY ); } /* LD IY,(w) */ +OP(fd,2b) { _IY--; } /* DEC IY */ +OP(fd,2c) { _LY = INC(_LY); } /* INC LY */ +OP(fd,2d) { _LY = DEC(_LY); } /* DEC LY */ +OP(fd,2e) { _LY = ARG(); } /* LD LY,n */ +OP(fd,2f) { illegal_1(); } /* DB FD */ + +OP(fd,30) { illegal_1(); } /* DB FD */ +OP(fd,31) { illegal_1(); } /* DB FD */ +OP(fd,32) { illegal_1(); } /* DB FD */ +OP(fd,33) { illegal_1(); } /* DB FD */ +OP(fd,34) { EAY; WM( EA, INC(RM(EA)) ); } /* INC (IY+o) */ +OP(fd,35) { EAY; WM( EA, DEC(RM(EA)) ); } /* DEC (IY+o) */ +OP(fd,36) { EAY; WM( EA, ARG() ); } /* LD (IY+o),n */ +OP(fd,37) { illegal_1(); } /* DB FD */ + +OP(fd,38) { illegal_1(); } /* DB FD */ +OP(fd,39) { ADD16(IY,SP); } /* ADD IY,SP */ +OP(fd,3a) { illegal_1(); } /* DB FD */ +OP(fd,3b) { illegal_1(); } /* DB FD */ +OP(fd,3c) { illegal_1(); } /* DB FD */ +OP(fd,3d) { illegal_1(); } /* DB FD */ +OP(fd,3e) { illegal_1(); } /* DB FD */ +OP(fd,3f) { illegal_1(); } /* DB FD */ + +OP(fd,40) { illegal_1(); } /* DB FD */ +OP(fd,41) { illegal_1(); } /* DB FD */ +OP(fd,42) { illegal_1(); } /* DB FD */ +OP(fd,43) { illegal_1(); } /* DB FD */ +OP(fd,44) { _B = _HY; } /* LD B,HY */ +OP(fd,45) { _B = _LY; } /* LD B,LY */ +OP(fd,46) { EAY; _B = RM(EA); } /* LD B,(IY+o) */ +OP(fd,47) { illegal_1(); } /* DB FD */ + +OP(fd,48) { illegal_1(); } /* DB FD */ +OP(fd,49) { illegal_1(); } /* DB FD */ +OP(fd,4a) { illegal_1(); } /* DB FD */ +OP(fd,4b) { illegal_1(); } /* DB FD */ +OP(fd,4c) { _C = _HY; } /* LD C,HY */ +OP(fd,4d) { _C = _LY; } /* LD C,LY */ +OP(fd,4e) { EAY; _C = RM(EA); } /* LD C,(IY+o) */ +OP(fd,4f) { illegal_1(); } /* DB FD */ + +OP(fd,50) { illegal_1(); } /* DB FD */ +OP(fd,51) { illegal_1(); } /* DB FD */ +OP(fd,52) { illegal_1(); } /* DB FD */ +OP(fd,53) { illegal_1(); } /* DB FD */ +OP(fd,54) { _D = _HY; } /* LD D,HY */ +OP(fd,55) { _D = _LY; } /* LD D,LY */ +OP(fd,56) { EAY; _D = RM(EA); } /* LD D,(IY+o) */ +OP(fd,57) { illegal_1(); } /* DB FD */ + +OP(fd,58) { illegal_1(); } /* DB FD */ +OP(fd,59) { illegal_1(); } /* DB FD */ +OP(fd,5a) { illegal_1(); } /* DB FD */ +OP(fd,5b) { illegal_1(); } /* DB FD */ +OP(fd,5c) { _E = _HY; } /* LD E,HY */ +OP(fd,5d) { _E = _LY; } /* LD E,LY */ +OP(fd,5e) { EAY; _E = RM(EA); } /* LD E,(IY+o) */ +OP(fd,5f) { illegal_1(); } /* DB FD */ + +OP(fd,60) { _HY = _B; } /* LD HY,B */ +OP(fd,61) { _HY = _C; } /* LD HY,C */ +OP(fd,62) { _HY = _D; } /* LD HY,D */ +OP(fd,63) { _HY = _E; } /* LD HY,E */ +OP(fd,64) { } /* LD HY,HY */ +OP(fd,65) { _HY = _LY; } /* LD HY,LY */ +OP(fd,66) { EAY; _H = RM(EA); } /* LD H,(IY+o) */ +OP(fd,67) { _HY = _A; } /* LD HY,A */ + +OP(fd,68) { _LY = _B; } /* LD LY,B */ +OP(fd,69) { _LY = _C; } /* LD LY,C */ +OP(fd,6a) { _LY = _D; } /* LD LY,D */ +OP(fd,6b) { _LY = _E; } /* LD LY,E */ +OP(fd,6c) { _LY = _HY; } /* LD LY,HY */ +OP(fd,6d) { } /* LD LY,LY */ +OP(fd,6e) { EAY; _L = RM(EA); } /* LD L,(IY+o) */ +OP(fd,6f) { _LY = _A; } /* LD LY,A */ + +OP(fd,70) { EAY; WM( EA, _B ); } /* LD (IY+o),B */ +OP(fd,71) { EAY; WM( EA, _C ); } /* LD (IY+o),C */ +OP(fd,72) { EAY; WM( EA, _D ); } /* LD (IY+o),D */ +OP(fd,73) { EAY; WM( EA, _E ); } /* LD (IY+o),E */ +OP(fd,74) { EAY; WM( EA, _H ); } /* LD (IY+o),H */ +OP(fd,75) { EAY; WM( EA, _L ); } /* LD (IY+o),L */ +OP(fd,76) { illegal_1(); } /* DB FD */ +OP(fd,77) { EAY; WM( EA, _A ); } /* LD (IY+o),A */ + +OP(fd,78) { illegal_1(); } /* DB FD */ +OP(fd,79) { illegal_1(); } /* DB FD */ +OP(fd,7a) { illegal_1(); } /* DB FD */ +OP(fd,7b) { illegal_1(); } /* DB FD */ +OP(fd,7c) { _A = _HY; } /* LD A,HY */ +OP(fd,7d) { _A = _LY; } /* LD A,LY */ +OP(fd,7e) { EAY; _A = RM(EA); } /* LD A,(IY+o) */ +OP(fd,7f) { illegal_1(); } /* DB FD */ + +OP(fd,80) { illegal_1(); } /* DB FD */ +OP(fd,81) { illegal_1(); } /* DB FD */ +OP(fd,82) { illegal_1(); } /* DB FD */ +OP(fd,83) { illegal_1(); } /* DB FD */ +OP(fd,84) { ADD(_HY); } /* ADD A,HY */ +OP(fd,85) { ADD(_LY); } /* ADD A,LY */ +OP(fd,86) { EAY; ADD(RM(EA)); } /* ADD A,(IY+o) */ +OP(fd,87) { illegal_1(); } /* DB FD */ + +OP(fd,88) { illegal_1(); } /* DB FD */ +OP(fd,89) { illegal_1(); } /* DB FD */ +OP(fd,8a) { illegal_1(); } /* DB FD */ +OP(fd,8b) { illegal_1(); } /* DB FD */ +OP(fd,8c) { ADC(_HY); } /* ADC A,HY */ +OP(fd,8d) { ADC(_LY); } /* ADC A,LY */ +OP(fd,8e) { EAY; ADC(RM(EA)); } /* ADC A,(IY+o) */ +OP(fd,8f) { illegal_1(); } /* DB FD */ + +OP(fd,90) { illegal_1(); } /* DB FD */ +OP(fd,91) { illegal_1(); } /* DB FD */ +OP(fd,92) { illegal_1(); } /* DB FD */ +OP(fd,93) { illegal_1(); } /* DB FD */ +OP(fd,94) { SUB(_HY); } /* SUB HY */ +OP(fd,95) { SUB(_LY); } /* SUB LY */ +OP(fd,96) { EAY; SUB(RM(EA)); } /* SUB (IY+o) */ +OP(fd,97) { illegal_1(); } /* DB FD */ + +OP(fd,98) { illegal_1(); } /* DB FD */ +OP(fd,99) { illegal_1(); } /* DB FD */ +OP(fd,9a) { illegal_1(); } /* DB FD */ +OP(fd,9b) { illegal_1(); } /* DB FD */ +OP(fd,9c) { SBC(_HY); } /* SBC A,HY */ +OP(fd,9d) { SBC(_LY); } /* SBC A,LY */ +OP(fd,9e) { EAY; SBC(RM(EA)); } /* SBC A,(IY+o) */ +OP(fd,9f) { illegal_1(); } /* DB FD */ + +OP(fd,a0) { illegal_1(); } /* DB FD */ +OP(fd,a1) { illegal_1(); } /* DB FD */ +OP(fd,a2) { illegal_1(); } /* DB FD */ +OP(fd,a3) { illegal_1(); } /* DB FD */ +OP(fd,a4) { AND(_HY); } /* AND HY */ +OP(fd,a5) { AND(_LY); } /* AND LY */ +OP(fd,a6) { EAY; AND(RM(EA)); } /* AND (IY+o) */ +OP(fd,a7) { illegal_1(); } /* DB FD */ + +OP(fd,a8) { illegal_1(); } /* DB FD */ +OP(fd,a9) { illegal_1(); } /* DB FD */ +OP(fd,aa) { illegal_1(); } /* DB FD */ +OP(fd,ab) { illegal_1(); } /* DB FD */ +OP(fd,ac) { XOR(_HY); } /* XOR HY */ +OP(fd,ad) { XOR(_LY); } /* XOR LY */ +OP(fd,ae) { EAY; XOR(RM(EA)); } /* XOR (IY+o) */ +OP(fd,af) { illegal_1(); } /* DB FD */ + +OP(fd,b0) { illegal_1(); } /* DB FD */ +OP(fd,b1) { illegal_1(); } /* DB FD */ +OP(fd,b2) { illegal_1(); } /* DB FD */ +OP(fd,b3) { illegal_1(); } /* DB FD */ +OP(fd,b4) { OR(_HY); } /* OR HY */ +OP(fd,b5) { OR(_LY); } /* OR LY */ +OP(fd,b6) { EAY; OR(RM(EA)); } /* OR (IY+o) */ +OP(fd,b7) { illegal_1(); } /* DB FD */ + +OP(fd,b8) { illegal_1(); } /* DB FD */ +OP(fd,b9) { illegal_1(); } /* DB FD */ +OP(fd,ba) { illegal_1(); } /* DB FD */ +OP(fd,bb) { illegal_1(); } /* DB FD */ +OP(fd,bc) { CP(_HY); } /* CP HY */ +OP(fd,bd) { CP(_LY); } /* CP LY */ +OP(fd,be) { EAY; CP(RM(EA)); } /* CP (IY+o) */ +OP(fd,bf) { illegal_1(); } /* DB FD */ + +OP(fd,c0) { illegal_1(); } /* DB FD */ +OP(fd,c1) { illegal_1(); } /* DB FD */ +OP(fd,c2) { illegal_1(); } /* DB FD */ +OP(fd,c3) { illegal_1(); } /* DB FD */ +OP(fd,c4) { illegal_1(); } /* DB FD */ +OP(fd,c5) { illegal_1(); } /* DB FD */ +OP(fd,c6) { illegal_1(); } /* DB FD */ +OP(fd,c7) { illegal_1(); } /* DB FD */ + +OP(fd,c8) { illegal_1(); } /* DB FD */ +OP(fd,c9) { illegal_1(); } /* DB FD */ +OP(fd,ca) { illegal_1(); } /* DB FD */ +OP(fd,cb) { EAY; EXEC(xxcb,ARG()); } /* ** FD CB xx */ +OP(fd,cc) { illegal_1(); } /* DB FD */ +OP(fd,cd) { illegal_1(); } /* DB FD */ +OP(fd,ce) { illegal_1(); } /* DB FD */ +OP(fd,cf) { illegal_1(); } /* DB FD */ + +OP(fd,d0) { illegal_1(); } /* DB FD */ +OP(fd,d1) { illegal_1(); } /* DB FD */ +OP(fd,d2) { illegal_1(); } /* DB FD */ +OP(fd,d3) { illegal_1(); } /* DB FD */ +OP(fd,d4) { illegal_1(); } /* DB FD */ +OP(fd,d5) { illegal_1(); } /* DB FD */ +OP(fd,d6) { illegal_1(); } /* DB FD */ +OP(fd,d7) { illegal_1(); } /* DB FD */ + +OP(fd,d8) { illegal_1(); } /* DB FD */ +OP(fd,d9) { illegal_1(); } /* DB FD */ +OP(fd,da) { illegal_1(); } /* DB FD */ +OP(fd,db) { illegal_1(); } /* DB FD */ +OP(fd,dc) { illegal_1(); } /* DB FD */ +OP(fd,dd) { illegal_1(); } /* DB FD */ +OP(fd,de) { illegal_1(); } /* DB FD */ +OP(fd,df) { illegal_1(); } /* DB FD */ + +OP(fd,e0) { illegal_1(); } /* DB FD */ +OP(fd,e1) { POP(IY); } /* POP IY */ +OP(fd,e2) { illegal_1(); } /* DB FD */ +OP(fd,e3) { EXSP(IY); } /* EX (SP),IY */ +OP(fd,e4) { illegal_1(); } /* DB FD */ +OP(fd,e5) { PUSH( IY ); } /* PUSH IY */ +OP(fd,e6) { illegal_1(); } /* DB FD */ +OP(fd,e7) { illegal_1(); } /* DB FD */ + +OP(fd,e8) { illegal_1(); } /* DB FD */ +OP(fd,e9) { _PC = _IY; } /* JP (IY) */ +OP(fd,ea) { illegal_1(); } /* DB FD */ +OP(fd,eb) { illegal_1(); } /* DB FD */ +OP(fd,ec) { illegal_1(); } /* DB FD */ +OP(fd,ed) { illegal_1(); } /* DB FD */ +OP(fd,ee) { illegal_1(); } /* DB FD */ +OP(fd,ef) { illegal_1(); } /* DB FD */ + +OP(fd,f0) { illegal_1(); } /* DB FD */ +OP(fd,f1) { illegal_1(); } /* DB FD */ +OP(fd,f2) { illegal_1(); } /* DB FD */ +OP(fd,f3) { illegal_1(); } /* DB FD */ +OP(fd,f4) { illegal_1(); } /* DB FD */ +OP(fd,f5) { illegal_1(); } /* DB FD */ +OP(fd,f6) { illegal_1(); } /* DB FD */ +OP(fd,f7) { illegal_1(); } /* DB FD */ + +OP(fd,f8) { illegal_1(); } /* DB FD */ +OP(fd,f9) { _SP = _IY; } /* LD SP,IY */ +OP(fd,fa) { illegal_1(); } /* DB FD */ +OP(fd,fb) { illegal_1(); } /* DB FD */ +OP(fd,fc) { illegal_1(); } /* DB FD */ +OP(fd,fd) { illegal_1(); } /* DB FD */ +OP(fd,fe) { illegal_1(); } /* DB FD */ +OP(fd,ff) { illegal_1(); } /* DB FD */ + +OP(illegal,2) +{ +} + +/********************************************************** + * special opcodes (ED prefix) + **********************************************************/ +OP(ed,00) { illegal_2(); } /* DB ED */ +OP(ed,01) { illegal_2(); } /* DB ED */ +OP(ed,02) { illegal_2(); } /* DB ED */ +OP(ed,03) { illegal_2(); } /* DB ED */ +OP(ed,04) { illegal_2(); } /* DB ED */ +OP(ed,05) { illegal_2(); } /* DB ED */ +OP(ed,06) { illegal_2(); } /* DB ED */ +OP(ed,07) { illegal_2(); } /* DB ED */ + +OP(ed,08) { illegal_2(); } /* DB ED */ +OP(ed,09) { illegal_2(); } /* DB ED */ +OP(ed,0a) { illegal_2(); } /* DB ED */ +OP(ed,0b) { illegal_2(); } /* DB ED */ +OP(ed,0c) { illegal_2(); } /* DB ED */ +OP(ed,0d) { illegal_2(); } /* DB ED */ +OP(ed,0e) { illegal_2(); } /* DB ED */ +OP(ed,0f) { illegal_2(); } /* DB ED */ + +OP(ed,10) { illegal_2(); } /* DB ED */ +OP(ed,11) { illegal_2(); } /* DB ED */ +OP(ed,12) { illegal_2(); } /* DB ED */ +OP(ed,13) { illegal_2(); } /* DB ED */ +OP(ed,14) { illegal_2(); } /* DB ED */ +OP(ed,15) { illegal_2(); } /* DB ED */ +OP(ed,16) { illegal_2(); } /* DB ED */ +OP(ed,17) { illegal_2(); } /* DB ED */ + +OP(ed,18) { illegal_2(); } /* DB ED */ +OP(ed,19) { illegal_2(); } /* DB ED */ +OP(ed,1a) { illegal_2(); } /* DB ED */ +OP(ed,1b) { illegal_2(); } /* DB ED */ +OP(ed,1c) { illegal_2(); } /* DB ED */ +OP(ed,1d) { illegal_2(); } /* DB ED */ +OP(ed,1e) { illegal_2(); } /* DB ED */ +OP(ed,1f) { illegal_2(); } /* DB ED */ + +OP(ed,20) { illegal_2(); } /* DB ED */ +OP(ed,21) { illegal_2(); } /* DB ED */ +OP(ed,22) { illegal_2(); } /* DB ED */ +OP(ed,23) { illegal_2(); } /* DB ED */ +OP(ed,24) { illegal_2(); } /* DB ED */ +OP(ed,25) { illegal_2(); } /* DB ED */ +OP(ed,26) { illegal_2(); } /* DB ED */ +OP(ed,27) { illegal_2(); } /* DB ED */ + +OP(ed,28) { illegal_2(); } /* DB ED */ +OP(ed,29) { illegal_2(); } /* DB ED */ +OP(ed,2a) { illegal_2(); } /* DB ED */ +OP(ed,2b) { illegal_2(); } /* DB ED */ +OP(ed,2c) { illegal_2(); } /* DB ED */ +OP(ed,2d) { illegal_2(); } /* DB ED */ +OP(ed,2e) { illegal_2(); } /* DB ED */ +OP(ed,2f) { illegal_2(); } /* DB ED */ + +OP(ed,30) { illegal_2(); } /* DB ED */ +OP(ed,31) { illegal_2(); } /* DB ED */ +OP(ed,32) { illegal_2(); } /* DB ED */ +OP(ed,33) { illegal_2(); } /* DB ED */ +OP(ed,34) { illegal_2(); } /* DB ED */ +OP(ed,35) { illegal_2(); } /* DB ED */ +OP(ed,36) { illegal_2(); } /* DB ED */ +OP(ed,37) { illegal_2(); } /* DB ED */ + +OP(ed,38) { illegal_2(); } /* DB ED */ +OP(ed,39) { illegal_2(); } /* DB ED */ +OP(ed,3a) { illegal_2(); } /* DB ED */ +OP(ed,3b) { illegal_2(); } /* DB ED */ +OP(ed,3c) { illegal_2(); } /* DB ED */ +OP(ed,3d) { illegal_2(); } /* DB ED */ +OP(ed,3e) { illegal_2(); } /* DB ED */ +OP(ed,3f) { illegal_2(); } /* DB ED */ + +OP(ed,40) { _B = IN(_BC); _F = (_F & CF) | SZP[_B]; } /* IN B,(C) */ +OP(ed,41) { OUT(_BC,_B); } /* OUT (C),B */ +OP(ed,42) { SBC16( BC ); } /* SBC HL,BC */ +OP(ed,43) { EA = ARG16(); WM16( EA, &Z80.BC ); } /* LD (w),BC */ +OP(ed,44) { NEG; } /* NEG */ +OP(ed,45) { RETN; } /* RETN; */ +OP(ed,46) { _IM = 0; } /* IM 0 */ +OP(ed,47) { LD_I_A; } /* LD I,A */ + +OP(ed,48) { _C = IN(_BC); _F = (_F & CF) | SZP[_C]; } /* IN C,(C) */ +OP(ed,49) { OUT(_BC,_C); } /* OUT (C),C */ +OP(ed,4a) { ADC16( BC ); } /* ADC HL,BC */ +OP(ed,4b) { EA = ARG16(); RM16( EA, &Z80.BC ); } /* LD BC,(w) */ +OP(ed,4c) { NEG; } /* NEG */ +OP(ed,4d) { RETI; } /* RETI */ +OP(ed,4e) { _IM = 0; } /* IM 0 */ +OP(ed,4f) { LD_R_A; } /* LD R,A */ + +OP(ed,50) { _D = IN(_BC); _F = (_F & CF) | SZP[_D]; } /* IN D,(C) */ +OP(ed,51) { OUT(_BC,_D); } /* OUT (C),D */ +OP(ed,52) { SBC16( DE ); } /* SBC HL,DE */ +OP(ed,53) { EA = ARG16(); WM16( EA, &Z80.DE ); } /* LD (w),DE */ +OP(ed,54) { NEG; } /* NEG */ +OP(ed,55) { RETN; } /* RETN; */ +OP(ed,56) { _IM = 1; } /* IM 1 */ +OP(ed,57) { LD_A_I; } /* LD A,I */ + +OP(ed,58) { _E = IN(_BC); _F = (_F & CF) | SZP[_E]; } /* IN E,(C) */ +OP(ed,59) { OUT(_BC,_E); } /* OUT (C),E */ +OP(ed,5a) { ADC16( DE ); } /* ADC HL,DE */ +OP(ed,5b) { EA = ARG16(); RM16( EA, &Z80.DE ); } /* LD DE,(w) */ +OP(ed,5c) { NEG; } /* NEG */ +OP(ed,5d) { RETI; } /* RETI */ +OP(ed,5e) { _IM = 2; } /* IM 2 */ +OP(ed,5f) { LD_A_R; } /* LD A,R */ + +OP(ed,60) { _H = IN(_BC); _F = (_F & CF) | SZP[_H]; } /* IN H,(C) */ +OP(ed,61) { OUT(_BC,_H); } /* OUT (C),H */ +OP(ed,62) { SBC16( HL ); } /* SBC HL,HL */ +OP(ed,63) { EA = ARG16(); WM16( EA, &Z80.HL ); } /* LD (w),HL */ +OP(ed,64) { NEG; } /* NEG */ +OP(ed,65) { RETN; } /* RETN; */ +OP(ed,66) { _IM = 0; } /* IM 0 */ +OP(ed,67) { RRD; } /* RRD (HL) */ + +OP(ed,68) { _L = IN(_BC); _F = (_F & CF) | SZP[_L]; } /* IN L,(C) */ +OP(ed,69) { OUT(_BC,_L); } /* OUT (C),L */ +OP(ed,6a) { ADC16( HL ); } /* ADC HL,HL */ +OP(ed,6b) { EA = ARG16(); RM16( EA, &Z80.HL ); } /* LD HL,(w) */ +OP(ed,6c) { NEG; } /* NEG */ +OP(ed,6d) { RETI; } /* RETI */ +OP(ed,6e) { _IM = 0; } /* IM 0 */ +OP(ed,6f) { RLD; } /* RLD (HL) */ + +OP(ed,70) { UINT8 res = IN(_BC); _F = (_F & CF) | SZP[res]; } /* IN 0,(C) */ +OP(ed,71) { OUT(_BC,0); } /* OUT (C),0 */ +OP(ed,72) { SBC16( SP ); } /* SBC HL,SP */ +OP(ed,73) { EA = ARG16(); WM16( EA, &Z80.SP ); } /* LD (w),SP */ +OP(ed,74) { NEG; } /* NEG */ +OP(ed,75) { RETN; } /* RETN; */ +OP(ed,76) { _IM = 1; } /* IM 1 */ +OP(ed,77) { illegal_2(); } /* DB ED,77 */ + +OP(ed,78) { _A = IN(_BC); _F = (_F & CF) | SZP[_A]; } /* IN E,(C) */ +OP(ed,79) { OUT(_BC,_A); } /* OUT (C),E */ +OP(ed,7a) { ADC16( SP ); } /* ADC HL,SP */ +OP(ed,7b) { EA = ARG16(); RM16( EA, &Z80.SP ); } /* LD SP,(w) */ +OP(ed,7c) { NEG; } /* NEG */ +OP(ed,7d) { RETI; } /* RETI */ +OP(ed,7e) { _IM = 2; } /* IM 2 */ +OP(ed,7f) { illegal_2(); } /* DB ED,7F */ + +OP(ed,80) { illegal_2(); } /* DB ED */ +OP(ed,81) { illegal_2(); } /* DB ED */ +OP(ed,82) { illegal_2(); } /* DB ED */ +OP(ed,83) { illegal_2(); } /* DB ED */ +OP(ed,84) { illegal_2(); } /* DB ED */ +OP(ed,85) { illegal_2(); } /* DB ED */ +OP(ed,86) { illegal_2(); } /* DB ED */ +OP(ed,87) { illegal_2(); } /* DB ED */ + +OP(ed,88) { illegal_2(); } /* DB ED */ +OP(ed,89) { illegal_2(); } /* DB ED */ +OP(ed,8a) { illegal_2(); } /* DB ED */ +OP(ed,8b) { illegal_2(); } /* DB ED */ +OP(ed,8c) { illegal_2(); } /* DB ED */ +OP(ed,8d) { illegal_2(); } /* DB ED */ +OP(ed,8e) { illegal_2(); } /* DB ED */ +OP(ed,8f) { illegal_2(); } /* DB ED */ + +OP(ed,90) { illegal_2(); } /* DB ED */ +OP(ed,91) { illegal_2(); } /* DB ED */ +OP(ed,92) { illegal_2(); } /* DB ED */ +OP(ed,93) { illegal_2(); } /* DB ED */ +OP(ed,94) { illegal_2(); } /* DB ED */ +OP(ed,95) { illegal_2(); } /* DB ED */ +OP(ed,96) { illegal_2(); } /* DB ED */ +OP(ed,97) { illegal_2(); } /* DB ED */ + +OP(ed,98) { illegal_2(); } /* DB ED */ +OP(ed,99) { illegal_2(); } /* DB ED */ +OP(ed,9a) { illegal_2(); } /* DB ED */ +OP(ed,9b) { illegal_2(); } /* DB ED */ +OP(ed,9c) { illegal_2(); } /* DB ED */ +OP(ed,9d) { illegal_2(); } /* DB ED */ +OP(ed,9e) { illegal_2(); } /* DB ED */ +OP(ed,9f) { illegal_2(); } /* DB ED */ + +OP(ed,a0) { LDI; } /* LDI */ +OP(ed,a1) { CPI; } /* CPI */ +OP(ed,a2) { INI; } /* INI */ +OP(ed,a3) { OUTI; } /* OUTI */ +OP(ed,a4) { illegal_2(); } /* DB ED */ +OP(ed,a5) { illegal_2(); } /* DB ED */ +OP(ed,a6) { illegal_2(); } /* DB ED */ +OP(ed,a7) { illegal_2(); } /* DB ED */ + +OP(ed,a8) { LDD; } /* LDD */ +OP(ed,a9) { CPD; } /* CPD */ +OP(ed,aa) { IND; } /* IND */ +OP(ed,ab) { OUTD; } /* OUTD */ +OP(ed,ac) { illegal_2(); } /* DB ED */ +OP(ed,ad) { illegal_2(); } /* DB ED */ +OP(ed,ae) { illegal_2(); } /* DB ED */ +OP(ed,af) { illegal_2(); } /* DB ED */ + +OP(ed,b0) { LDIR; } /* LDIR */ +OP(ed,b1) { CPIR; } /* CPIR */ +OP(ed,b2) { INIR; } /* INIR */ +OP(ed,b3) { OTIR; } /* OTIR */ +OP(ed,b4) { illegal_2(); } /* DB ED */ +OP(ed,b5) { illegal_2(); } /* DB ED */ +OP(ed,b6) { illegal_2(); } /* DB ED */ +OP(ed,b7) { illegal_2(); } /* DB ED */ + +OP(ed,b8) { LDDR; } /* LDDR */ +OP(ed,b9) { CPDR; } /* CPDR */ +OP(ed,ba) { INDR; } /* INDR */ +OP(ed,bb) { OTDR; } /* OTDR */ +OP(ed,bc) { illegal_2(); } /* DB ED */ +OP(ed,bd) { illegal_2(); } /* DB ED */ +OP(ed,be) { illegal_2(); } /* DB ED */ +OP(ed,bf) { illegal_2(); } /* DB ED */ + +OP(ed,c0) { illegal_2(); } /* DB ED */ +OP(ed,c1) { illegal_2(); } /* DB ED */ +OP(ed,c2) { illegal_2(); } /* DB ED */ +OP(ed,c3) { illegal_2(); } /* DB ED */ +OP(ed,c4) { illegal_2(); } /* DB ED */ +OP(ed,c5) { illegal_2(); } /* DB ED */ +OP(ed,c6) { illegal_2(); } /* DB ED */ +OP(ed,c7) { illegal_2(); } /* DB ED */ + +OP(ed,c8) { illegal_2(); } /* DB ED */ +OP(ed,c9) { illegal_2(); } /* DB ED */ +OP(ed,ca) { illegal_2(); } /* DB ED */ +OP(ed,cb) { illegal_2(); } /* DB ED */ +OP(ed,cc) { illegal_2(); } /* DB ED */ +OP(ed,cd) { illegal_2(); } /* DB ED */ +OP(ed,ce) { illegal_2(); } /* DB ED */ +OP(ed,cf) { illegal_2(); } /* DB ED */ + +OP(ed,d0) { illegal_2(); } /* DB ED */ +OP(ed,d1) { illegal_2(); } /* DB ED */ +OP(ed,d2) { illegal_2(); } /* DB ED */ +OP(ed,d3) { illegal_2(); } /* DB ED */ +OP(ed,d4) { illegal_2(); } /* DB ED */ +OP(ed,d5) { illegal_2(); } /* DB ED */ +OP(ed,d6) { illegal_2(); } /* DB ED */ +OP(ed,d7) { illegal_2(); } /* DB ED */ + +OP(ed,d8) { illegal_2(); } /* DB ED */ +OP(ed,d9) { illegal_2(); } /* DB ED */ +OP(ed,da) { illegal_2(); } /* DB ED */ +OP(ed,db) { illegal_2(); } /* DB ED */ +OP(ed,dc) { illegal_2(); } /* DB ED */ +OP(ed,dd) { illegal_2(); } /* DB ED */ +OP(ed,de) { illegal_2(); } /* DB ED */ +OP(ed,df) { illegal_2(); } /* DB ED */ + +OP(ed,e0) { illegal_2(); } /* DB ED */ +OP(ed,e1) { illegal_2(); } /* DB ED */ +OP(ed,e2) { illegal_2(); } /* DB ED */ +OP(ed,e3) { illegal_2(); } /* DB ED */ +OP(ed,e4) { illegal_2(); } /* DB ED */ +OP(ed,e5) { illegal_2(); } /* DB ED */ +OP(ed,e6) { illegal_2(); } /* DB ED */ +OP(ed,e7) { illegal_2(); } /* DB ED */ + +OP(ed,e8) { illegal_2(); } /* DB ED */ +OP(ed,e9) { illegal_2(); } /* DB ED */ +OP(ed,ea) { illegal_2(); } /* DB ED */ +OP(ed,eb) { illegal_2(); } /* DB ED */ +OP(ed,ec) { illegal_2(); } /* DB ED */ +OP(ed,ed) { illegal_2(); } /* DB ED */ +OP(ed,ee) { illegal_2(); } /* DB ED */ +OP(ed,ef) { illegal_2(); } /* DB ED */ + +OP(ed,f0) { illegal_2(); } /* DB ED */ +OP(ed,f1) { illegal_2(); } /* DB ED */ +OP(ed,f2) { illegal_2(); } /* DB ED */ +OP(ed,f3) { illegal_2(); } /* DB ED */ +OP(ed,f4) { illegal_2(); } /* DB ED */ +OP(ed,f5) { illegal_2(); } /* DB ED */ +OP(ed,f6) { illegal_2(); } /* DB ED */ +OP(ed,f7) { illegal_2(); } /* DB ED */ + +OP(ed,f8) { illegal_2(); } /* DB ED */ +OP(ed,f9) { illegal_2(); } /* DB ED */ +OP(ed,fa) { illegal_2(); } /* DB ED */ +OP(ed,fb) { illegal_2(); } /* DB ED */ +OP(ed,fc) { illegal_2(); } /* DB ED */ +OP(ed,fd) { illegal_2(); } /* DB ED */ +OP(ed,fe) { illegal_2(); } /* DB ED */ +OP(ed,ff) { illegal_2(); } /* DB ED */ + +#if TIME_LOOP_HACKS + +#define CHECK_BC_LOOP \ +if( _BC > 1 && _PCD < 0xfffc ) { \ + UINT8 op1 = cpu_readop(_PCD); \ + UINT8 op2 = cpu_readop(_PCD+1); \ + if( (op1==0x78 && op2==0xb1) || (op1==0x79 && op2==0xb0) ) \ + { \ + UINT8 op3 = cpu_readop(_PCD+2); \ + UINT8 op4 = cpu_readop(_PCD+3); \ + if( op3==0x20 && op4==0xfb ) \ + { \ + while( _BC > 0 && z80_ICount > 4+4+12+6 ) \ + { \ + BURNODD( 4+4+12+6, 4, 4+4+12+6 ); \ + _BC--; \ + } \ + } \ + else \ + if( op3 == 0xc2 ) \ + { \ + UINT8 ad1 = cpu_readop_arg(_PCD+3); \ + UINT8 ad2 = cpu_readop_arg(_PCD+4); \ + if( (ad1 + 256 * ad2) == (_PCD - 1) ) \ + { \ + while( _BC > 0 && z80_ICount > 4+4+10+6 ) \ + { \ + BURNODD( 4+4+10+6, 4, 4+4+10+6 ); \ + _BC--; \ + } \ + } \ + } \ + } \ +} + +#define CHECK_DE_LOOP \ +if( _DE > 1 && _PCD < 0xfffc ) { \ + UINT8 op1 = cpu_readop(_PCD); \ + UINT8 op2 = cpu_readop(_PCD+1); \ + if( (op1==0x7a && op2==0xb3) || (op1==0x7b && op2==0xb2) ) \ + { \ + UINT8 op3 = cpu_readop(_PCD+2); \ + UINT8 op4 = cpu_readop(_PCD+3); \ + if( op3==0x20 && op4==0xfb ) \ + { \ + while( _DE > 0 && z80_ICount > 4+4+12+6 ) \ + { \ + BURNODD( 4+4+12+6, 4, 4+4+12+6 ); \ + _DE--; \ + } \ + } \ + else \ + if( op3==0xc2 ) \ + { \ + UINT8 ad1 = cpu_readop_arg(_PCD+3); \ + UINT8 ad2 = cpu_readop_arg(_PCD+4); \ + if( (ad1 + 256 * ad2) == (_PCD - 1) ) \ + { \ + while( _DE > 0 && z80_ICount > 4+4+10+6 ) \ + { \ + BURNODD( 4+4+10+6, 4, 4+4+10+6 ); \ + _DE--; \ + } \ + } \ + } \ + } \ +} + +#define CHECK_HL_LOOP \ +if( _HL > 1 && _PCD < 0xfffc ) { \ + UINT8 op1 = cpu_readop(_PCD); \ + UINT8 op2 = cpu_readop(_PCD+1); \ + if( (op1==0x7c && op2==0xb5) || (op1==0x7d && op2==0xb4) ) \ + { \ + UINT8 op3 = cpu_readop(_PCD+2); \ + UINT8 op4 = cpu_readop(_PCD+3); \ + if( op3==0x20 && op4==0xfb ) \ + { \ + while( _HL > 0 && z80_ICount > 4+4+12+6 ) \ + { \ + BURNODD( 4+4+12+6, 4, 4+4+12+6 ); \ + _HL--; \ + } \ + } \ + else \ + if( op3==0xc2 ) \ + { \ + UINT8 ad1 = cpu_readop_arg(_PCD+3); \ + UINT8 ad2 = cpu_readop_arg(_PCD+4); \ + if( (ad1 + 256 * ad2) == (_PCD - 1) ) \ + { \ + while( _HL > 0 && z80_ICount > 4+4+10+6 ) \ + { \ + BURNODD( 4+4+10+6, 4, 4+4+10+6 ); \ + _HL--; \ + } \ + } \ + } \ + } \ +} + +#else + +#define CHECK_BC_LOOP +#define CHECK_DE_LOOP +#define CHECK_HL_LOOP + +#endif + +/********************************************************** + * main opcodes + **********************************************************/ +OP(op,00) { } /* NOP */ +OP(op,01) { _BC = ARG16(); } /* LD BC,w */ +OP(op,02) { WM( _BC, _A ); } /* LD (BC),A */ +OP(op,03) { _BC++; } /* INC BC */ +OP(op,04) { _B = INC(_B); } /* INC B */ +OP(op,05) { _B = DEC(_B); } /* DEC B */ +OP(op,06) { _B = ARG(); } /* LD B,n */ +OP(op,07) { RLCA; } /* RLCA */ + +OP(op,08) { EX_AF; } /* EX AF,AF' */ +OP(op,09) { ADD16(HL,BC); } /* ADD HL,BC */ +OP(op,0a) { _A = RM(_BC); } /* LD A,(BC) */ +OP(op,0b) { _BC--; CHECK_BC_LOOP; } /* DEC BC */ +OP(op,0c) { _C = INC(_C); } /* INC C */ +OP(op,0d) { _C = DEC(_C); } /* DEC C */ +OP(op,0e) { _C = ARG(); } /* LD C,n */ +OP(op,0f) { RRCA; } /* RRCA */ + +OP(op,10) { _B--; JR_COND(_B); } /* DJNZ o */ +OP(op,11) { _DE = ARG16(); } /* LD DE,w */ +OP(op,12) { WM( _DE, _A ); } /* LD (DE),A */ +OP(op,13) { _DE++; } /* INC DE */ +OP(op,14) { _D = INC(_D); } /* INC D */ +OP(op,15) { _D = DEC(_D); } /* DEC D */ +OP(op,16) { _D = ARG(); } /* LD D,n */ +OP(op,17) { RLA; } /* RLA */ + +OP(op,18) { JR(); } /* JR o */ +OP(op,19) { ADD16(HL,DE); } /* ADD HL,DE */ +OP(op,1a) { _A = RM(_DE); } /* LD A,(DE) */ +OP(op,1b) { _DE--; CHECK_DE_LOOP; } /* DEC DE */ +OP(op,1c) { _E = INC(_E); } /* INC E */ +OP(op,1d) { _E = DEC(_E); } /* DEC E */ +OP(op,1e) { _E = ARG(); } /* LD E,n */ +OP(op,1f) { RRA; } /* RRA */ + +OP(op,20) { JR_COND( !(_F & ZF) ); } /* JR NZ,o */ +OP(op,21) { _HL = ARG16(); } /* LD HL,w */ +OP(op,22) { EA = ARG16(); WM16( EA, &Z80.HL ); } /* LD (w),HL */ +OP(op,23) { _HL++; } /* INC HL */ +OP(op,24) { _H = INC(_H); } /* INC H */ +OP(op,25) { _H = DEC(_H); } /* DEC H */ +OP(op,26) { _H = ARG(); } /* LD H,n */ +OP(op,27) { DAA; } /* DAA */ + +OP(op,28) { JR_COND( _F & ZF ); } /* JR Z,o */ +OP(op,29) { ADD16(HL,HL); } /* ADD HL,HL */ +OP(op,2a) { EA = ARG16(); RM16( EA, &Z80.HL ); } /* LD HL,(w) */ +OP(op,2b) { _HL--; CHECK_HL_LOOP; } /* DEC HL */ +OP(op,2c) { _L = INC(_L); } /* INC L */ +OP(op,2d) { _L = DEC(_L); } /* DEC L */ +OP(op,2e) { _L = ARG(); } /* LD L,n */ +OP(op,2f) { _A ^= 0xff; _F = (_F&(SF|ZF|PF|CF))|HF|NF|(_A&(YF|XF)); } /* CPL */ + +OP(op,30) { JR_COND( !(_F & CF) ); } /* JR NC,o */ +OP(op,31) { _SP = ARG16(); } /* LD SP,w */ +OP(op,32) { EA = ARG16(); WM( EA, _A ); } /* LD (w),A */ +OP(op,33) { _SP++; } /* INC SP */ +OP(op,34) { WM( _HL, INC(RM(_HL)) ); } /* INC (HL) */ +OP(op,35) { WM( _HL, DEC(RM(_HL)) ); } /* DEC (HL) */ +OP(op,36) { WM( _HL, ARG() ); } /* LD (HL),n */ +OP(op,37) { _F = (_F & (SF|ZF|PF)) | CF | (_A & (YF|XF)); } /* SCF */ + +OP(op,38) { JR_COND( _F & CF ); } /* JR C,o */ +OP(op,39) { ADD16(HL,SP); } /* ADD HL,SP */ +OP(op,3a) { EA = ARG16(); _A = RM( EA ); } /* LD A,(w) */ +OP(op,3b) { _SP--; } /* DEC SP */ +OP(op,3c) { _A = INC(_A); } /* INC A */ +OP(op,3d) { _A = DEC(_A); } /* DEC A */ +OP(op,3e) { _A = ARG(); } /* LD A,n */ +OP(op,3f) { _F = ((_F&(SF|ZF|PF|CF))|((_F&CF)<<4)|(_A&(YF|XF)))^CF; } /* CCF */ +/*OP(op,3f) { _F = ((_F & ~(HF|NF)) | ((_F & CF)<<4)) ^ CF; } */ /* CCF */ + +OP(op,40) { } /* LD B,B */ +OP(op,41) { _B = _C; } /* LD B,C */ +OP(op,42) { _B = _D; } /* LD B,D */ +OP(op,43) { _B = _E; } /* LD B,E */ +OP(op,44) { _B = _H; } /* LD B,H */ +OP(op,45) { _B = _L; } /* LD B,L */ +OP(op,46) { _B = RM(_HL); } /* LD B,(HL) */ +OP(op,47) { _B = _A; } /* LD B,A */ + +OP(op,48) { _C = _B; } /* LD C,B */ +OP(op,49) { } /* LD C,C */ +OP(op,4a) { _C = _D; } /* LD C,D */ +OP(op,4b) { _C = _E; } /* LD C,E */ +OP(op,4c) { _C = _H; } /* LD C,H */ +OP(op,4d) { _C = _L; } /* LD C,L */ +OP(op,4e) { _C = RM(_HL); } /* LD C,(HL) */ +OP(op,4f) { _C = _A; } /* LD C,A */ + +OP(op,50) { _D = _B; } /* LD D,B */ +OP(op,51) { _D = _C; } /* LD D,C */ +OP(op,52) { } /* LD D,D */ +OP(op,53) { _D = _E; } /* LD D,E */ +OP(op,54) { _D = _H; } /* LD D,H */ +OP(op,55) { _D = _L; } /* LD D,L */ +OP(op,56) { _D = RM(_HL); } /* LD D,(HL) */ +OP(op,57) { _D = _A; } /* LD D,A */ + +OP(op,58) { _E = _B; } /* LD E,B */ +OP(op,59) { _E = _C; } /* LD E,C */ +OP(op,5a) { _E = _D; } /* LD E,D */ +OP(op,5b) { } /* LD E,E */ +OP(op,5c) { _E = _H; } /* LD E,H */ +OP(op,5d) { _E = _L; } /* LD E,L */ +OP(op,5e) { _E = RM(_HL); } /* LD E,(HL) */ +OP(op,5f) { _E = _A; } /* LD E,A */ + +OP(op,60) { _H = _B; } /* LD H,B */ +OP(op,61) { _H = _C; } /* LD H,C */ +OP(op,62) { _H = _D; } /* LD H,D */ +OP(op,63) { _H = _E; } /* LD H,E */ +OP(op,64) { } /* LD H,H */ +OP(op,65) { _H = _L; } /* LD H,L */ +OP(op,66) { _H = RM(_HL); } /* LD H,(HL) */ +OP(op,67) { _H = _A; } /* LD H,A */ + +OP(op,68) { _L = _B; } /* LD L,B */ +OP(op,69) { _L = _C; } /* LD L,C */ +OP(op,6a) { _L = _D; } /* LD L,D */ +OP(op,6b) { _L = _E; } /* LD L,E */ +OP(op,6c) { _L = _H; } /* LD L,H */ +OP(op,6d) { } /* LD L,L */ +OP(op,6e) { _L = RM(_HL); } /* LD L,(HL) */ +OP(op,6f) { _L = _A; } /* LD L,A */ + +OP(op,70) { WM( _HL, _B ); } /* LD (HL),B */ +OP(op,71) { WM( _HL, _C ); } /* LD (HL),C */ +OP(op,72) { WM( _HL, _D ); } /* LD (HL),D */ +OP(op,73) { WM( _HL, _E ); } /* LD (HL),E */ +OP(op,74) { WM( _HL, _H ); } /* LD (HL),H */ +OP(op,75) { WM( _HL, _L ); } /* LD (HL),L */ +OP(op,76) { ENTER_HALT; } /* HALT */ +OP(op,77) { WM( _HL, _A ); } /* LD (HL),A */ + +OP(op,78) { _A = _B; } /* LD A,B */ +OP(op,79) { _A = _C; } /* LD A,C */ +OP(op,7a) { _A = _D; } /* LD A,D */ +OP(op,7b) { _A = _E; } /* LD A,E */ +OP(op,7c) { _A = _H; } /* LD A,H */ +OP(op,7d) { _A = _L; } /* LD A,L */ +OP(op,7e) { _A = RM(_HL); } /* LD A,(HL) */ +OP(op,7f) { } /* LD A,A */ + +OP(op,80) { ADD(_B); } /* ADD A,B */ +OP(op,81) { ADD(_C); } /* ADD A,C */ +OP(op,82) { ADD(_D); } /* ADD A,D */ +OP(op,83) { ADD(_E); } /* ADD A,E */ +OP(op,84) { ADD(_H); } /* ADD A,H */ +OP(op,85) { ADD(_L); } /* ADD A,L */ +OP(op,86) { ADD(RM(_HL)); } /* ADD A,(HL) */ +OP(op,87) { ADD(_A); } /* ADD A,A */ + +OP(op,88) { ADC(_B); } /* ADC A,B */ +OP(op,89) { ADC(_C); } /* ADC A,C */ +OP(op,8a) { ADC(_D); } /* ADC A,D */ +OP(op,8b) { ADC(_E); } /* ADC A,E */ +OP(op,8c) { ADC(_H); } /* ADC A,H */ +OP(op,8d) { ADC(_L); } /* ADC A,L */ +OP(op,8e) { ADC(RM(_HL)); } /* ADC A,(HL) */ +OP(op,8f) { ADC(_A); } /* ADC A,A */ + +OP(op,90) { SUB(_B); } /* SUB B */ +OP(op,91) { SUB(_C); } /* SUB C */ +OP(op,92) { SUB(_D); } /* SUB D */ +OP(op,93) { SUB(_E); } /* SUB E */ +OP(op,94) { SUB(_H); } /* SUB H */ +OP(op,95) { SUB(_L); } /* SUB L */ +OP(op,96) { SUB(RM(_HL)); } /* SUB (HL) */ +OP(op,97) { SUB(_A); } /* SUB A */ + +OP(op,98) { SBC(_B); } /* SBC A,B */ +OP(op,99) { SBC(_C); } /* SBC A,C */ +OP(op,9a) { SBC(_D); } /* SBC A,D */ +OP(op,9b) { SBC(_E); } /* SBC A,E */ +OP(op,9c) { SBC(_H); } /* SBC A,H */ +OP(op,9d) { SBC(_L); } /* SBC A,L */ +OP(op,9e) { SBC(RM(_HL)); } /* SBC A,(HL) */ +OP(op,9f) { SBC(_A); } /* SBC A,A */ + +OP(op,a0) { AND(_B); } /* AND B */ +OP(op,a1) { AND(_C); } /* AND C */ +OP(op,a2) { AND(_D); } /* AND D */ +OP(op,a3) { AND(_E); } /* AND E */ +OP(op,a4) { AND(_H); } /* AND H */ +OP(op,a5) { AND(_L); } /* AND L */ +OP(op,a6) { AND(RM(_HL)); } /* AND (HL) */ +OP(op,a7) { AND(_A); } /* AND A */ + +OP(op,a8) { XOR(_B); } /* XOR B */ +OP(op,a9) { XOR(_C); } /* XOR C */ +OP(op,aa) { XOR(_D); } /* XOR D */ +OP(op,ab) { XOR(_E); } /* XOR E */ +OP(op,ac) { XOR(_H); } /* XOR H */ +OP(op,ad) { XOR(_L); } /* XOR L */ +OP(op,ae) { XOR(RM(_HL)); } /* XOR (HL) */ +OP(op,af) { XOR(_A); } /* XOR A */ + +OP(op,b0) { OR(_B); } /* OR B */ +OP(op,b1) { OR(_C); } /* OR C */ +OP(op,b2) { OR(_D); } /* OR D */ +OP(op,b3) { OR(_E); } /* OR E */ +OP(op,b4) { OR(_H); } /* OR H */ +OP(op,b5) { OR(_L); } /* OR L */ +OP(op,b6) { OR(RM(_HL)); } /* OR (HL) */ +OP(op,b7) { OR(_A); } /* OR A */ + +OP(op,b8) { CP(_B); } /* CP B */ +OP(op,b9) { CP(_C); } /* CP C */ +OP(op,ba) { CP(_D); } /* CP D */ +OP(op,bb) { CP(_E); } /* CP E */ +OP(op,bc) { CP(_H); } /* CP H */ +OP(op,bd) { CP(_L); } /* CP L */ +OP(op,be) { CP(RM(_HL)); } /* CP (HL) */ +OP(op,bf) { CP(_A); } /* CP A */ + +OP(op,c0) { RET( !(_F & ZF) ); } /* RET NZ */ +OP(op,c1) { POP(BC); } /* POP BC */ +OP(op,c2) { JP_COND( !(_F & ZF) ); } /* JP NZ,a */ +OP(op,c3) { JP; } /* JP a */ +OP(op,c4) { CALL( !(_F & ZF) ); } /* CALL NZ,a */ +OP(op,c5) { PUSH( BC ); } /* PUSH BC */ +OP(op,c6) { ADD(ARG()); } /* ADD A,n */ +OP(op,c7) { RST(0x00); } /* RST 0 */ + +OP(op,c8) { RET( _F & ZF ); } /* RET Z */ +OP(op,c9) { RET(1); } /* RET */ +OP(op,ca) { JP_COND( _F & ZF ); } /* JP Z,a */ +OP(op,cb) { _R++; EXEC(cb,ROP()); } /* **** CB xx */ +OP(op,cc) { CALL( _F & ZF ); } /* CALL Z,a */ +OP(op,cd) { CALL(1); } /* CALL a */ +OP(op,ce) { ADC(ARG()); } /* ADC A,n */ +OP(op,cf) { RST(0x08); } /* RST 1 */ + +OP(op,d0) { RET( !(_F & CF) ); } /* RET NC */ +OP(op,d1) { POP(DE); } /* POP DE */ +OP(op,d2) { JP_COND( !(_F & CF) ); } /* JP NC,a */ +OP(op,d3) { unsigned n = ARG() | (_A << 8); OUT( n, _A ); } /* OUT (n),A */ +OP(op,d4) { CALL( !(_F & CF) ); } /* CALL NC,a */ +OP(op,d5) { PUSH( DE ); } /* PUSH DE */ +OP(op,d6) { SUB(ARG()); } /* SUB n */ +OP(op,d7) { RST(0x10); } /* RST 2 */ + +OP(op,d8) { RET( _F & CF ); } /* RET C */ +OP(op,d9) { EXX; } /* EXX */ +OP(op,da) { JP_COND( _F & CF ); } /* JP C,a */ +OP(op,db) { unsigned n = ARG() | (_A << 8); _A = IN( n ); } /* IN A,(n) */ +OP(op,dc) { CALL( _F & CF ); } /* CALL C,a */ +OP(op,dd) { _R++; EXEC(dd,ROP()); } /* **** DD xx */ +OP(op,de) { SBC(ARG()); } /* SBC A,n */ +OP(op,df) { RST(0x18); } /* RST 3 */ + +OP(op,e0) { RET( !(_F & PF) ); } /* RET PO */ +OP(op,e1) { POP(HL); } /* POP HL */ +OP(op,e2) { JP_COND( !(_F & PF) ); } /* JP PO,a */ +OP(op,e3) { EXSP(HL); } /* EX HL,(SP) */ +OP(op,e4) { CALL( !(_F & PF) ); } /* CALL PO,a */ +OP(op,e5) { PUSH( HL ); } /* PUSH HL */ +OP(op,e6) { AND(ARG()); } /* AND n */ +OP(op,e7) { RST(0x20); } /* RST 4 */ + +OP(op,e8) { RET( _F & PF ); } /* RET PE */ +OP(op,e9) { _PC = _HL; } /* JP (HL) */ +OP(op,ea) { JP_COND( _F & PF ); } /* JP PE,a */ +OP(op,eb) { EX_DE_HL; } /* EX DE,HL */ +OP(op,ec) { CALL( _F & PF ); } /* CALL PE,a */ +OP(op,ed) { _R++; EXEC(ed,ROP()); } /* **** ED xx */ +OP(op,ee) { XOR(ARG()); } /* XOR n */ +OP(op,ef) { RST(0x28); } /* RST 5 */ + +OP(op,f0) { RET( !(_F & SF) ); } /* RET P */ +OP(op,f1) { POP(AF); } /* POP AF */ +OP(op,f2) { JP_COND( !(_F & SF) ); } /* JP P,a */ +OP(op,f3) { _IFF1 = _IFF2 = 0; } /* DI */ +OP(op,f4) { CALL( !(_F & SF) ); } /* CALL P,a */ +OP(op,f5) { PUSH( AF ); } /* PUSH AF */ +OP(op,f6) { OR(ARG()); } /* OR n */ +OP(op,f7) { RST(0x30); } /* RST 6 */ + +OP(op,f8) { RET(_F & SF); } /* RET M */ +OP(op,f9) { _SP = _HL; } /* LD SP,HL */ +OP(op,fa) { JP_COND(_F & SF); } /* JP M,a */ +OP(op,fb) { EI; } /* EI */ +OP(op,fc) { CALL(_F & SF); } /* CALL M,a */ +OP(op,fd) { _R++; EXEC(fd,ROP()); } /* **** FD xx */ +OP(op,fe) { CP(ARG()); } /* CP n */ +OP(op,ff) { RST(0x38); } /* RST 7 */ + + +static void take_interrupt(void) +{ + if( _IFF1 ) + { + int irq_vector; + + /* there isn't a valid previous program counter */ + _PPC = -1; + + /* Check if processor was halted */ + LEAVE_HALT; + + if( Z80.irq_max ) /* daisy chain mode */ + { + if( Z80.request_irq >= 0 ) + { + /* Clear both interrupt flip flops */ + _IFF1 = _IFF2 = 0; + irq_vector = Z80.irq[Z80.request_irq].interrupt_entry(Z80.irq[Z80.request_irq].irq_param); + Z80.request_irq = -1; + } else return; + } + else + { + /* Clear both interrupt flip flops */ + _IFF1 = _IFF2 = 0; + /* call back the cpu interface to retrieve the vector */ + irq_vector = (*Z80.irq_callback)(0); + } + + /* Interrupt mode 2. Call [Z80.I:databyte] */ + if( _IM == 2 ) + { + irq_vector = (irq_vector & 0xff) | (_I << 8); + PUSH( PC ); + RM16( irq_vector, &Z80.PC ); + Z80.extra_cycles += 19; + } + else + /* Interrupt mode 1. RST 38h */ + if( _IM == 1 ) + { + PUSH( PC ); + _PCD = 0x0038; + Z80.extra_cycles += 11+2; /* RST $38 + 2 cycles */ + } + else + { + /* Interrupt mode 0. We check for CALL and JP instructions, */ + /* if neither of these were found we assume a 1 byte opcode */ + /* was placed on the databus */ + switch (irq_vector & 0xff0000) + { + case 0xcd0000: /* call */ + PUSH( PC ); + Z80.extra_cycles += 5; /* CALL $xxxx cycles (JP $xxxx follows)*/ + case 0xc30000: /* jump */ + _PCD = irq_vector & 0xffff; + Z80.extra_cycles += 10 + 2; /* JP $xxxx + 2 cycles */ + break; + default: /* rst */ + PUSH( PC ); + _PCD = irq_vector & 0x0038; + Z80.extra_cycles += 11 + 2; /* RST $xx + 2 cycles */ + break; + } + } + } +} + +/**************************************************************************** + * Reset registers to their initial values + ****************************************************************************/ +void z80_reset(void *param) +{ + Z80_DaisyChain *daisy_chain = (Z80_DaisyChain *)param; + int i, p; +#if BIG_FLAGS_ARRAY + if( !SZHVC_add || !SZHVC_sub ) + { + int oldval, newval, val; + UINT8 *padd, *padc, *psub, *psbc; + /* allocate big flag arrays once */ + SZHVC_add = (UINT8 *)malloc(2*256*256); + SZHVC_sub = (UINT8 *)malloc(2*256*256); + if( !SZHVC_add || !SZHVC_sub ) + { + raise(SIGABRT); + } + padd = &SZHVC_add[ 0*256]; + padc = &SZHVC_add[256*256]; + psub = &SZHVC_sub[ 0*256]; + psbc = &SZHVC_sub[256*256]; + for (oldval = 0; oldval < 256; oldval++) + { + for (newval = 0; newval < 256; newval++) + { + /* add or adc w/o carry set */ + val = newval - oldval; + *padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF; +#if Z80_EXACT + *padd |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF; + if( newval < oldval ) *padd |= CF; + if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF; + padd++; + + /* adc with carry set */ + val = newval - oldval - 1; + *padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF; +#if Z80_EXACT + *padc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF; + if( newval <= oldval ) *padc |= CF; + if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF; + padc++; + + /* cp, sub or sbc w/o carry set */ + val = oldval - newval; + *psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF); +#if Z80_EXACT + *psub |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF; + if( newval > oldval ) *psub |= CF; + if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF; + psub++; + + /* sbc with carry set */ + val = oldval - newval - 1; + *psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF); +#if Z80_EXACT + *psbc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF; + if( newval >= oldval ) *psbc |= CF; + if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF; + psbc++; + } + } + } +#endif + for (i = 0; i < 256; i++) + { + p = 0; + if( i&0x01 ) ++p; + if( i&0x02 ) ++p; + if( i&0x04 ) ++p; + if( i&0x08 ) ++p; + if( i&0x10 ) ++p; + if( i&0x20 ) ++p; + if( i&0x40 ) ++p; + if( i&0x80 ) ++p; + SZ[i] = i ? i & SF : ZF; +#if Z80_EXACT + SZ[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + SZ_BIT[i] = i ? i & SF : ZF | PF; +#if Z80_EXACT + SZ_BIT[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */ +#endif + SZP[i] = SZ[i] | ((p & 1) ? 0 : PF); + SZHV_inc[i] = SZ[i]; + if( i == 0x80 ) SZHV_inc[i] |= VF; + if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF; + SZHV_dec[i] = SZ[i] | NF; + if( i == 0x7f ) SZHV_dec[i] |= VF; + if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF; + } + + memset(&Z80, 0, sizeof(Z80)); + _IX = _IY = 0xffff; /* IX and IY are FFFF after a reset! */ + _F = ZF; /* Zero flag is set */ + Z80.request_irq = -1; + Z80.service_irq = -1; + Z80.nmi_state = CLEAR_LINE; + Z80.irq_state = CLEAR_LINE; + + if( daisy_chain ) + { + while( daisy_chain->irq_param != -1 && Z80.irq_max < Z80_MAXDAISY ) + { + /* set callbackhandler after reti */ + Z80.irq[Z80.irq_max] = *daisy_chain; + /* device reset */ + if( Z80.irq[Z80.irq_max].reset ) + Z80.irq[Z80.irq_max].reset(Z80.irq[Z80.irq_max].irq_param); + Z80.irq_max++; + daisy_chain++; + } + } +} + +void z80_exit(void) +{ +#if BIG_FLAGS_ARRAY + if (SZHVC_add) free(SZHVC_add); + SZHVC_add = 0; + if (SZHVC_sub) free(SZHVC_sub); + SZHVC_sub = 0; +#endif +} + +/**************************************************************************** + * Execute 'cycles' T-states. Return number of T-states really executed + ****************************************************************************/ +int z80_execute(int cycles) +{ + z80_ICount = cycles - Z80.extra_cycles; + Z80.extra_cycles = 0; + + do + { + _PPC = _PCD; + _R++; + EXEC_INLINE(op,ROP()); + } while( z80_ICount > 0 ); + + z80_ICount -= Z80.extra_cycles; + Z80.extra_cycles = 0; + + return cycles - z80_ICount; +} + +/**************************************************************************** + * Burn 'cycles' T-states. Adjust R register for the lost time + ****************************************************************************/ +void z80_burn(int cycles) +{ + if( cycles > 0 ) + { + /* NOP takes 4 cycles per instruction */ + int n = (cycles + 3) / 4; + _R += n; + z80_ICount -= 4 * n; + } +} + +/**************************************************************************** + * Get all registers in given buffer + ****************************************************************************/ +unsigned z80_get_context (void *dst) +{ + if( dst ) + *(Z80_Regs*)dst = Z80; + return sizeof(Z80_Regs); +} + +/**************************************************************************** + * Set all registers to given values + ****************************************************************************/ +void z80_set_context (void *src) +{ + if( src ) + Z80 = *(Z80_Regs*)src; +} + +/**************************************************************************** + * Return program counter + ****************************************************************************/ +unsigned z80_get_pc (void) +{ + return _PCD; +} + +/**************************************************************************** + * Set program counter + ****************************************************************************/ +void z80_set_pc (unsigned val) +{ + _PC = val; +} + +/**************************************************************************** + * Return stack pointer + ****************************************************************************/ +unsigned z80_get_sp (void) +{ + return _SPD; +} + +/**************************************************************************** + * Set stack pointer + ****************************************************************************/ +void z80_set_sp (unsigned val) +{ + _SP = val; +} + +/**************************************************************************** + * Return a specific register + ****************************************************************************/ +unsigned z80_get_reg (int regnum) +{ + switch( regnum ) + { + case Z80_PC: return Z80.PC.w.l; + case Z80_SP: return Z80.SP.w.l; + case Z80_AF: return Z80.AF.w.l; + case Z80_BC: return Z80.BC.w.l; + case Z80_DE: return Z80.DE.w.l; + case Z80_HL: return Z80.HL.w.l; + case Z80_IX: return Z80.IX.w.l; + case Z80_IY: return Z80.IY.w.l; + case Z80_R: return (Z80.R & 0x7f) | (Z80.R2 & 0x80); + case Z80_I: return Z80.I; + case Z80_AF2: return Z80.AF2.w.l; + case Z80_BC2: return Z80.BC2.w.l; + case Z80_DE2: return Z80.DE2.w.l; + case Z80_HL2: return Z80.HL2.w.l; + case Z80_IM: return Z80.IM; + case Z80_IFF1: return Z80.IFF1; + case Z80_IFF2: return Z80.IFF2; + case Z80_HALT: return Z80.HALT; + case Z80_NMI_STATE: return Z80.nmi_state; + case Z80_IRQ_STATE: return Z80.irq_state; + case Z80_DC0: return Z80.int_state[0]; + case Z80_DC1: return Z80.int_state[1]; + case Z80_DC2: return Z80.int_state[2]; + case Z80_DC3: return Z80.int_state[3]; + case REG_PREVIOUSPC: return Z80.PREPC.w.l; + default: + if( regnum <= REG_SP_CONTENTS ) + { + unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum); + if( offset < 0xffff ) + return RM( offset ) | ( RM( offset + 1) << 8 ); + } + } + return 0; +} + +/**************************************************************************** + * Set a specific register + ****************************************************************************/ +void z80_set_reg (int regnum, unsigned val) +{ + switch( regnum ) + { + case Z80_PC: Z80.PC.w.l = val; break; + case Z80_SP: Z80.SP.w.l = val; break; + case Z80_AF: Z80.AF.w.l = val; break; + case Z80_BC: Z80.BC.w.l = val; break; + case Z80_DE: Z80.DE.w.l = val; break; + case Z80_HL: Z80.HL.w.l = val; break; + case Z80_IX: Z80.IX.w.l = val; break; + case Z80_IY: Z80.IY.w.l = val; break; + case Z80_R: Z80.R = val; Z80.R2 = val & 0x80; break; + case Z80_I: Z80.I = val; break; + case Z80_AF2: Z80.AF2.w.l = val; break; + case Z80_BC2: Z80.BC2.w.l = val; break; + case Z80_DE2: Z80.DE2.w.l = val; break; + case Z80_HL2: Z80.HL2.w.l = val; break; + case Z80_IM: Z80.IM = val; break; + case Z80_IFF1: Z80.IFF1 = val; break; + case Z80_IFF2: Z80.IFF2 = val; break; + case Z80_HALT: Z80.HALT = val; break; + case Z80_NMI_STATE: z80_set_nmi_line(val); break; + case Z80_IRQ_STATE: z80_set_irq_line(0,val); break; + case Z80_DC0: Z80.int_state[0] = val; break; + case Z80_DC1: Z80.int_state[1] = val; break; + case Z80_DC2: Z80.int_state[2] = val; break; + case Z80_DC3: Z80.int_state[3] = val; break; + default: + if( regnum <= REG_SP_CONTENTS ) + { + unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum); + if( offset < 0xffff ) + { + WM( offset, val & 0xff ); + WM( offset+1, (val >> 8) & 0xff ); + } + } + } +} + +/**************************************************************************** + * Set NMI line state + ****************************************************************************/ +void z80_set_nmi_line(int state) +{ + if( Z80.nmi_state == state ) return; + + Z80.nmi_state = state; + if( state == CLEAR_LINE ) return; + + _PPC = -1; /* there isn't a valid previous program counter */ + LEAVE_HALT; /* Check if processor was halted */ + + _IFF1 = 0; + PUSH( PC ); + _PCD = 0x0066; + Z80.extra_cycles += 11; +} + +/**************************************************************************** + * Set IRQ line state + ****************************************************************************/ +void z80_set_irq_line(int irqline, int state) +{ + Z80.irq_state = state; + if( state == CLEAR_LINE ) return; + + if( Z80.irq_max ) + { + int daisychain, device, int_state; + daisychain = (*Z80.irq_callback)(irqline); + device = daisychain >> 8; + int_state = daisychain & 0xff; + + if( Z80.int_state[device] != int_state ) + { + /* set new interrupt status */ + Z80.int_state[device] = int_state; + /* check interrupt status */ + Z80.request_irq = Z80.service_irq = -1; + + /* search higher IRQ or IEO */ + for( device = 0 ; device < Z80.irq_max ; device ++ ) + { + /* IEO = disable ? */ + if( Z80.int_state[device] & Z80_INT_IEO ) + { + Z80.request_irq = -1; /* if IEO is disable , masking lower IRQ */ + Z80.service_irq = device; /* set highest interrupt service device */ + } + /* IRQ = request ? */ + if( Z80.int_state[device] & Z80_INT_REQ ) + Z80.request_irq = device; + } + if( Z80.request_irq < 0 ) return; + } + else + { + return; + } + } + take_interrupt(); +} + +/**************************************************************************** + * Set IRQ vector callback + ****************************************************************************/ +void z80_set_irq_callback(int (*callback)(int)) +{ + Z80.irq_callback = callback; +} diff --git a/MCUME_teensy/teensysms/z80.h b/MCUME_teensy/teensysms/z80.h new file mode 100644 index 0000000..283dd0e --- /dev/null +++ b/MCUME_teensy/teensysms/z80.h @@ -0,0 +1,76 @@ +#ifndef Z80_H +#define Z80_H + + +/*#define CLEAR_LINE 0*/ /* clear (a fired, held or pulsed) line */ +/*#define ASSERT_LINE 1*/ /* assert an interrupt immediately */ + +#include "cpuintrf.h" + +enum { + Z80_PC=1, Z80_SP, Z80_AF, Z80_BC, Z80_DE, Z80_HL, + Z80_IX, Z80_IY, Z80_AF2, Z80_BC2, Z80_DE2, Z80_HL2, + Z80_R, Z80_I, Z80_IM, Z80_IFF1, Z80_IFF2, Z80_HALT, + Z80_NMI_STATE, Z80_IRQ_STATE, Z80_DC0, Z80_DC1, Z80_DC2, Z80_DC3, + Z80_NMI_NESTING +}; + +extern int z80_ICount; /* T-state count */ + +#define Z80_IGNORE_INT -1 /* Ignore interrupt */ +#define Z80_NMI_INT -2 /* Execute NMI */ +#define Z80_IRQ_INT -1000 /* Execute IRQ */ + +/* Port number written to when entering/leaving HALT state */ +#define Z80_HALT_PORT 0x10000 + +extern void z80_reset (void *param); +extern void z80_exit (void); +extern int z80_execute(int cycles); +extern void z80_burn(int cycles); +extern unsigned z80_get_context (void *dst); +extern void z80_set_context (void *src); +extern unsigned z80_get_pc (void); +extern void z80_set_pc (unsigned val); +extern unsigned z80_get_sp (void); +extern void z80_set_sp (unsigned val); +extern unsigned z80_get_reg (int regnum); +extern void z80_set_reg (int regnum, unsigned val); +extern void z80_set_nmi_line(int state); +extern void z80_set_irq_line(int irqline, int state); +extern void z80_set_irq_callback(int (*irq_callback)(int)); +extern void z80_state_save(void *file); +extern void z80_state_load(void *file); +extern const char *z80_info(void *context, int regnum); +extern unsigned z80_dasm(char *buffer, unsigned pc); + +#ifdef MAME_DEBUG +extern unsigned DasmZ80(char *buffer, unsigned pc); +#endif + +/****************************************************************************/ +/* The Z80 registers. HALT is set to 1 when the CPU is halted, the refresh */ +/* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128) */ +/****************************************************************************/ +typedef struct { +/* 00 */ PAIR PREPC,PC,SP,AF,BC,DE,HL,IX,IY; +/* 24 */ PAIR AF2,BC2,DE2,HL2; +/* 34 */ UINT8 R,R2,IFF1,IFF2,HALT,IM,I; +/* 3B */ UINT8 irq_max; /* number of daisy chain devices */ +/* 3C */ INT8 request_irq; /* daisy chain next request device */ +/* 3D */ INT8 service_irq; /* daisy chain next reti handling device */ +/* 3E */ UINT8 nmi_state; /* nmi line state */ +/* 3F */ UINT8 irq_state; /* irq line state */ +/* 40 */ UINT8 int_state[Z80_MAXDAISY]; +/* 44 */ Z80_DaisyChain irq[Z80_MAXDAISY]; +/* 84 */ int (*irq_callback)(int irqline); +/* 88 */ int extra_cycles; /* extra cycles for interrupts */ +} Z80_Regs; + +extern Z80_Regs *Z80_Context; +extern int after_EI; +extern unsigned char *cpu_readmap[8]; +extern unsigned char *cpu_writemap[8]; + +#endif + diff --git a/MCUME_teensy/teensysms/z80daa.h b/MCUME_teensy/teensysms/z80daa.h new file mode 100644 index 0000000..d9c9e0d --- /dev/null +++ b/MCUME_teensy/teensysms/z80daa.h @@ -0,0 +1,2052 @@ +#include "arduinoproto.h" +PROGMEM static UINT16 DAATable[0x800] = { + (0x00<<8) +ZF +VF , + (0x01<<8) , + (0x02<<8) , + (0x03<<8) +VF , + (0x04<<8) , + (0x05<<8) +VF , + (0x06<<8) +VF , + (0x07<<8) , + (0x08<<8) +XF , + (0x09<<8) +XF+VF , + (0x10<<8) +HF , + (0x11<<8) +HF +VF , + (0x12<<8) +HF +VF , + (0x13<<8) +HF , + (0x14<<8) +HF +VF , + (0x15<<8) +HF , + (0x10<<8) , + (0x11<<8) +VF , + (0x12<<8) +VF , + (0x13<<8) , + (0x14<<8) +VF , + (0x15<<8) , + (0x16<<8) , + (0x17<<8) +VF , + (0x18<<8) +XF+VF , + (0x19<<8) +XF , + (0x20<<8) +YF+HF , + (0x21<<8) +YF+HF +VF , + (0x22<<8) +YF+HF +VF , + (0x23<<8) +YF+HF , + (0x24<<8) +YF+HF +VF , + (0x25<<8) +YF+HF , + (0x20<<8) +YF , + (0x21<<8) +YF +VF , + (0x22<<8) +YF +VF , + (0x23<<8) +YF , + (0x24<<8) +YF +VF , + (0x25<<8) +YF , + (0x26<<8) +YF , + (0x27<<8) +YF +VF , + (0x28<<8) +YF +XF+VF , + (0x29<<8) +YF +XF , + (0x30<<8) +YF+HF +VF , + (0x31<<8) +YF+HF , + (0x32<<8) +YF+HF , + (0x33<<8) +YF+HF +VF , + (0x34<<8) +YF+HF , + (0x35<<8) +YF+HF +VF , + (0x30<<8) +YF +VF , + (0x31<<8) +YF , + (0x32<<8) +YF , + (0x33<<8) +YF +VF , + (0x34<<8) +YF , + (0x35<<8) +YF +VF , + (0x36<<8) +YF +VF , + (0x37<<8) +YF , + (0x38<<8) +YF +XF , + (0x39<<8) +YF +XF+VF , + (0x40<<8) +HF , + (0x41<<8) +HF +VF , + (0x42<<8) +HF +VF , + (0x43<<8) +HF , + (0x44<<8) +HF +VF , + (0x45<<8) +HF , + (0x40<<8) , + (0x41<<8) +VF , + (0x42<<8) +VF , + (0x43<<8) , + (0x44<<8) +VF , + (0x45<<8) , + (0x46<<8) , + (0x47<<8) +VF , + (0x48<<8) +XF+VF , + (0x49<<8) +XF , + (0x50<<8) +HF +VF , + (0x51<<8) +HF , + (0x52<<8) +HF , + (0x53<<8) +HF +VF , + (0x54<<8) +HF , + (0x55<<8) +HF +VF , + (0x50<<8) +VF , + (0x51<<8) , + (0x52<<8) , + (0x53<<8) +VF , + (0x54<<8) , + (0x55<<8) +VF , + (0x56<<8) +VF , + (0x57<<8) , + (0x58<<8) +XF , + (0x59<<8) +XF+VF , + (0x60<<8) +YF+HF +VF , + (0x61<<8) +YF+HF , + (0x62<<8) +YF+HF , + (0x63<<8) +YF+HF +VF , + (0x64<<8) +YF+HF , + (0x65<<8) +YF+HF +VF , + (0x60<<8) +YF +VF , + (0x61<<8) +YF , + (0x62<<8) +YF , + (0x63<<8) +YF +VF , + (0x64<<8) +YF , + (0x65<<8) +YF +VF , + (0x66<<8) +YF +VF , + (0x67<<8) +YF , + (0x68<<8) +YF +XF , + (0x69<<8) +YF +XF+VF , + (0x70<<8) +YF+HF , + (0x71<<8) +YF+HF +VF , + (0x72<<8) +YF+HF +VF , + (0x73<<8) +YF+HF , + (0x74<<8) +YF+HF +VF , + (0x75<<8) +YF+HF , + (0x70<<8) +YF , + (0x71<<8) +YF +VF , + (0x72<<8) +YF +VF , + (0x73<<8) +YF , + (0x74<<8) +YF +VF , + (0x75<<8) +YF , + (0x76<<8) +YF , + (0x77<<8) +YF +VF , + (0x78<<8) +YF +XF+VF , + (0x79<<8) +YF +XF , + (0x80<<8)+SF +HF , + (0x81<<8)+SF +HF +VF , + (0x82<<8)+SF +HF +VF , + (0x83<<8)+SF +HF , + (0x84<<8)+SF +HF +VF , + (0x85<<8)+SF +HF , + (0x80<<8)+SF , + (0x81<<8)+SF +VF , + (0x82<<8)+SF +VF , + (0x83<<8)+SF , + (0x84<<8)+SF +VF , + (0x85<<8)+SF , + (0x86<<8)+SF , + (0x87<<8)+SF +VF , + (0x88<<8)+SF +XF+VF , + (0x89<<8)+SF +XF , + (0x90<<8)+SF +HF +VF , + (0x91<<8)+SF +HF , + (0x92<<8)+SF +HF , + (0x93<<8)+SF +HF +VF , + (0x94<<8)+SF +HF , + (0x95<<8)+SF +HF +VF , + (0x90<<8)+SF +VF , + (0x91<<8)+SF , + (0x92<<8)+SF , + (0x93<<8)+SF +VF , + (0x94<<8)+SF , + (0x95<<8)+SF +VF , + (0x96<<8)+SF +VF , + (0x97<<8)+SF , + (0x98<<8)+SF +XF , + (0x99<<8)+SF +XF+VF , + (0x00<<8) +ZF +HF +VF +CF, + (0x01<<8) +HF +CF, + (0x02<<8) +HF +CF, + (0x03<<8) +HF +VF +CF, + (0x04<<8) +HF +CF, + (0x05<<8) +HF +VF +CF, + (0x00<<8) +ZF +VF +CF, + (0x01<<8) +CF, + (0x02<<8) +CF, + (0x03<<8) +VF +CF, + (0x04<<8) +CF, + (0x05<<8) +VF +CF, + (0x06<<8) +VF +CF, + (0x07<<8) +CF, + (0x08<<8) +XF +CF, + (0x09<<8) +XF+VF +CF, + (0x10<<8) +HF +CF, + (0x11<<8) +HF +VF +CF, + (0x12<<8) +HF +VF +CF, + (0x13<<8) +HF +CF, + (0x14<<8) +HF +VF +CF, + (0x15<<8) +HF +CF, + (0x10<<8) +CF, + (0x11<<8) +VF +CF, + (0x12<<8) +VF +CF, + (0x13<<8) +CF, + (0x14<<8) +VF +CF, + (0x15<<8) +CF, + (0x16<<8) +CF, + (0x17<<8) +VF +CF, + (0x18<<8) +XF+VF +CF, + (0x19<<8) +XF +CF, + (0x20<<8) +YF+HF +CF, + (0x21<<8) +YF+HF +VF +CF, + (0x22<<8) +YF+HF +VF +CF, + (0x23<<8) +YF+HF +CF, + (0x24<<8) +YF+HF +VF +CF, + (0x25<<8) +YF+HF +CF, + (0x20<<8) +YF +CF, + (0x21<<8) +YF +VF +CF, + (0x22<<8) +YF +VF +CF, + (0x23<<8) +YF +CF, + (0x24<<8) +YF +VF +CF, + (0x25<<8) +YF +CF, + (0x26<<8) +YF +CF, + (0x27<<8) +YF +VF +CF, + (0x28<<8) +YF +XF+VF +CF, + (0x29<<8) +YF +XF +CF, + (0x30<<8) +YF+HF +VF +CF, + (0x31<<8) +YF+HF +CF, + (0x32<<8) +YF+HF +CF, + (0x33<<8) +YF+HF +VF +CF, + (0x34<<8) +YF+HF +CF, + (0x35<<8) +YF+HF +VF +CF, + (0x30<<8) +YF +VF +CF, + (0x31<<8) +YF +CF, + (0x32<<8) +YF +CF, + (0x33<<8) +YF +VF +CF, + (0x34<<8) +YF +CF, + (0x35<<8) +YF +VF +CF, + (0x36<<8) +YF +VF +CF, + (0x37<<8) +YF +CF, + (0x38<<8) +YF +XF +CF, + (0x39<<8) +YF +XF+VF +CF, + (0x40<<8) +HF +CF, + (0x41<<8) +HF +VF +CF, + (0x42<<8) +HF +VF +CF, + (0x43<<8) +HF +CF, + (0x44<<8) +HF +VF +CF, + (0x45<<8) +HF +CF, + (0x40<<8) +CF, + (0x41<<8) +VF +CF, + (0x42<<8) +VF +CF, + (0x43<<8) +CF, + (0x44<<8) +VF +CF, + (0x45<<8) +CF, + (0x46<<8) +CF, + (0x47<<8) +VF +CF, + (0x48<<8) +XF+VF +CF, + (0x49<<8) +XF +CF, + (0x50<<8) +HF +VF +CF, + (0x51<<8) +HF +CF, + (0x52<<8) +HF +CF, + (0x53<<8) +HF +VF +CF, + (0x54<<8) +HF +CF, + (0x55<<8) +HF +VF +CF, + (0x50<<8) +VF +CF, + (0x51<<8) +CF, + (0x52<<8) +CF, + (0x53<<8) +VF +CF, + (0x54<<8) +CF, + (0x55<<8) +VF +CF, + (0x56<<8) +VF +CF, + (0x57<<8) +CF, + (0x58<<8) +XF +CF, + (0x59<<8) +XF+VF +CF, + (0x60<<8) +YF+HF +VF +CF, + (0x61<<8) +YF+HF +CF, + (0x62<<8) +YF+HF +CF, + (0x63<<8) +YF+HF +VF +CF, + (0x64<<8) +YF+HF +CF, + (0x65<<8) +YF+HF +VF +CF, + (0x60<<8) +YF +VF +CF, + (0x61<<8) +YF +CF, + (0x62<<8) +YF +CF, + (0x63<<8) +YF +VF +CF, + (0x64<<8) +YF +CF, + (0x65<<8) +YF +VF +CF, + (0x66<<8) +YF +VF +CF, + (0x67<<8) +YF +CF, + (0x68<<8) +YF +XF +CF, + (0x69<<8) +YF +XF+VF +CF, + (0x70<<8) +YF+HF +CF, + (0x71<<8) +YF+HF +VF +CF, + (0x72<<8) +YF+HF +VF +CF, + (0x73<<8) +YF+HF +CF, + (0x74<<8) +YF+HF +VF +CF, + (0x75<<8) +YF+HF +CF, + (0x70<<8) +YF +CF, + (0x71<<8) +YF +VF +CF, + (0x72<<8) +YF +VF +CF, + (0x73<<8) +YF +CF, + (0x74<<8) +YF +VF +CF, + (0x75<<8) +YF +CF, + (0x76<<8) +YF +CF, + (0x77<<8) +YF +VF +CF, + (0x78<<8) +YF +XF+VF +CF, + (0x79<<8) +YF +XF +CF, + (0x80<<8)+SF +HF +CF, + (0x81<<8)+SF +HF +VF +CF, + (0x82<<8)+SF +HF +VF +CF, + (0x83<<8)+SF +HF +CF, + (0x84<<8)+SF +HF +VF +CF, + (0x85<<8)+SF +HF +CF, + (0x80<<8)+SF +CF, + (0x81<<8)+SF +VF +CF, + (0x82<<8)+SF +VF +CF, + (0x83<<8)+SF +CF, + (0x84<<8)+SF +VF +CF, + (0x85<<8)+SF +CF, + (0x86<<8)+SF +CF, + (0x87<<8)+SF +VF +CF, + (0x88<<8)+SF +XF+VF +CF, + (0x89<<8)+SF +XF +CF, + (0x90<<8)+SF +HF +VF +CF, + (0x91<<8)+SF +HF +CF, + (0x92<<8)+SF +HF +CF, + (0x93<<8)+SF +HF +VF +CF, + (0x94<<8)+SF +HF +CF, + (0x95<<8)+SF +HF +VF +CF, + (0x90<<8)+SF +VF +CF, + (0x91<<8)+SF +CF, + (0x92<<8)+SF +CF, + (0x93<<8)+SF +VF +CF, + (0x94<<8)+SF +CF, + (0x95<<8)+SF +VF +CF, + (0x96<<8)+SF +VF +CF, + (0x97<<8)+SF +CF, + (0x98<<8)+SF +XF +CF, + (0x99<<8)+SF +XF+VF +CF, + (0xA0<<8)+SF +YF+HF +VF +CF, + (0xA1<<8)+SF +YF+HF +CF, + (0xA2<<8)+SF +YF+HF +CF, + (0xA3<<8)+SF +YF+HF +VF +CF, + (0xA4<<8)+SF +YF+HF +CF, + (0xA5<<8)+SF +YF+HF +VF +CF, + (0xA0<<8)+SF +YF +VF +CF, + (0xA1<<8)+SF +YF +CF, + (0xA2<<8)+SF +YF +CF, + (0xA3<<8)+SF +YF +VF +CF, + (0xA4<<8)+SF +YF +CF, + (0xA5<<8)+SF +YF +VF +CF, + (0xA6<<8)+SF +YF +VF +CF, + (0xA7<<8)+SF +YF +CF, + (0xA8<<8)+SF +YF +XF +CF, + (0xA9<<8)+SF +YF +XF+VF +CF, + (0xB0<<8)+SF +YF+HF +CF, + (0xB1<<8)+SF +YF+HF +VF +CF, + (0xB2<<8)+SF +YF+HF +VF +CF, + (0xB3<<8)+SF +YF+HF +CF, + (0xB4<<8)+SF +YF+HF +VF +CF, + (0xB5<<8)+SF +YF+HF +CF, + (0xB0<<8)+SF +YF +CF, + (0xB1<<8)+SF +YF +VF +CF, + (0xB2<<8)+SF +YF +VF +CF, + (0xB3<<8)+SF +YF +CF, + (0xB4<<8)+SF +YF +VF +CF, + (0xB5<<8)+SF +YF +CF, + (0xB6<<8)+SF +YF +CF, + (0xB7<<8)+SF +YF +VF +CF, + (0xB8<<8)+SF +YF +XF+VF +CF, + (0xB9<<8)+SF +YF +XF +CF, + (0xC0<<8)+SF +HF +VF +CF, + (0xC1<<8)+SF +HF +CF, + (0xC2<<8)+SF +HF +CF, + (0xC3<<8)+SF +HF +VF +CF, + (0xC4<<8)+SF +HF +CF, + (0xC5<<8)+SF +HF +VF +CF, + (0xC0<<8)+SF +VF +CF, + (0xC1<<8)+SF +CF, + (0xC2<<8)+SF +CF, + (0xC3<<8)+SF +VF +CF, + (0xC4<<8)+SF +CF, + (0xC5<<8)+SF +VF +CF, + (0xC6<<8)+SF +VF +CF, + (0xC7<<8)+SF +CF, + (0xC8<<8)+SF +XF +CF, + (0xC9<<8)+SF +XF+VF +CF, + (0xD0<<8)+SF +HF +CF, + (0xD1<<8)+SF +HF +VF +CF, + (0xD2<<8)+SF +HF +VF +CF, + (0xD3<<8)+SF +HF +CF, + (0xD4<<8)+SF +HF +VF +CF, + (0xD5<<8)+SF +HF +CF, + (0xD0<<8)+SF +CF, + (0xD1<<8)+SF +VF +CF, + (0xD2<<8)+SF +VF +CF, + (0xD3<<8)+SF +CF, + (0xD4<<8)+SF +VF +CF, + (0xD5<<8)+SF +CF, + (0xD6<<8)+SF +CF, + (0xD7<<8)+SF +VF +CF, + (0xD8<<8)+SF +XF+VF +CF, + (0xD9<<8)+SF +XF +CF, + (0xE0<<8)+SF +YF+HF +CF, + (0xE1<<8)+SF +YF+HF +VF +CF, + (0xE2<<8)+SF +YF+HF +VF +CF, + (0xE3<<8)+SF +YF+HF +CF, + (0xE4<<8)+SF +YF+HF +VF +CF, + (0xE5<<8)+SF +YF+HF +CF, + (0xE0<<8)+SF +YF +CF, + (0xE1<<8)+SF +YF +VF +CF, + (0xE2<<8)+SF +YF +VF +CF, + (0xE3<<8)+SF +YF +CF, + (0xE4<<8)+SF +YF +VF +CF, + (0xE5<<8)+SF +YF +CF, + (0xE6<<8)+SF +YF +CF, + (0xE7<<8)+SF +YF +VF +CF, + (0xE8<<8)+SF +YF +XF+VF +CF, + (0xE9<<8)+SF +YF +XF +CF, + (0xF0<<8)+SF +YF+HF +VF +CF, + (0xF1<<8)+SF +YF+HF +CF, + (0xF2<<8)+SF +YF+HF +CF, + (0xF3<<8)+SF +YF+HF +VF +CF, + (0xF4<<8)+SF +YF+HF +CF, + (0xF5<<8)+SF +YF+HF +VF +CF, + (0xF0<<8)+SF +YF +VF +CF, + (0xF1<<8)+SF +YF +CF, + (0xF2<<8)+SF +YF +CF, + (0xF3<<8)+SF +YF +VF +CF, + (0xF4<<8)+SF +YF +CF, + (0xF5<<8)+SF +YF +VF +CF, + (0xF6<<8)+SF +YF +VF +CF, + (0xF7<<8)+SF +YF +CF, + (0xF8<<8)+SF +YF +XF +CF, + (0xF9<<8)+SF +YF +XF+VF +CF, + (0x00<<8) +ZF +HF +VF +CF, + (0x01<<8) +HF +CF, + (0x02<<8) +HF +CF, + (0x03<<8) +HF +VF +CF, + (0x04<<8) +HF +CF, + (0x05<<8) +HF +VF +CF, + (0x00<<8) +ZF +VF +CF, + (0x01<<8) +CF, + (0x02<<8) +CF, + (0x03<<8) +VF +CF, + (0x04<<8) +CF, + (0x05<<8) +VF +CF, + (0x06<<8) +VF +CF, + (0x07<<8) +CF, + (0x08<<8) +XF +CF, + (0x09<<8) +XF+VF +CF, + (0x10<<8) +HF +CF, + (0x11<<8) +HF +VF +CF, + (0x12<<8) +HF +VF +CF, + (0x13<<8) +HF +CF, + (0x14<<8) +HF +VF +CF, + (0x15<<8) +HF +CF, + (0x10<<8) +CF, + (0x11<<8) +VF +CF, + (0x12<<8) +VF +CF, + (0x13<<8) +CF, + (0x14<<8) +VF +CF, + (0x15<<8) +CF, + (0x16<<8) +CF, + (0x17<<8) +VF +CF, + (0x18<<8) +XF+VF +CF, + (0x19<<8) +XF +CF, + (0x20<<8) +YF+HF +CF, + (0x21<<8) +YF+HF +VF +CF, + (0x22<<8) +YF+HF +VF +CF, + (0x23<<8) +YF+HF +CF, + (0x24<<8) +YF+HF +VF +CF, + (0x25<<8) +YF+HF +CF, + (0x20<<8) +YF +CF, + (0x21<<8) +YF +VF +CF, + (0x22<<8) +YF +VF +CF, + (0x23<<8) +YF +CF, + (0x24<<8) +YF +VF +CF, + (0x25<<8) +YF +CF, + (0x26<<8) +YF +CF, + (0x27<<8) +YF +VF +CF, + (0x28<<8) +YF +XF+VF +CF, + (0x29<<8) +YF +XF +CF, + (0x30<<8) +YF+HF +VF +CF, + (0x31<<8) +YF+HF +CF, + (0x32<<8) +YF+HF +CF, + (0x33<<8) +YF+HF +VF +CF, + (0x34<<8) +YF+HF +CF, + (0x35<<8) +YF+HF +VF +CF, + (0x30<<8) +YF +VF +CF, + (0x31<<8) +YF +CF, + (0x32<<8) +YF +CF, + (0x33<<8) +YF +VF +CF, + (0x34<<8) +YF +CF, + (0x35<<8) +YF +VF +CF, + (0x36<<8) +YF +VF +CF, + (0x37<<8) +YF +CF, + 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(0x41<<8) +VF+NF+CF, + (0x42<<8) +VF+NF+CF, + (0x43<<8) +NF+CF, + (0x44<<8) +VF+NF+CF, + (0x45<<8) +NF+CF, + (0x46<<8) +NF+CF, + (0x47<<8) +VF+NF+CF, + (0x48<<8) +XF+VF+NF+CF, + (0x49<<8) +XF +NF+CF, + (0x4A<<8) +HF+XF +NF+CF, + (0x4B<<8) +HF+XF+VF+NF+CF, + (0x4C<<8) +HF+XF +NF+CF, + (0x4D<<8) +HF+XF+VF+NF+CF, + (0x4E<<8) +HF+XF+VF+NF+CF, + (0x4F<<8) +HF+XF +NF+CF, + (0x50<<8) +VF+NF+CF, + (0x51<<8) +NF+CF, + (0x52<<8) +NF+CF, + (0x53<<8) +VF+NF+CF, + (0x54<<8) +NF+CF, + (0x55<<8) +VF+NF+CF, + (0x56<<8) +VF+NF+CF, + (0x57<<8) +NF+CF, + (0x58<<8) +XF +NF+CF, + (0x59<<8) +XF+VF+NF+CF, + (0x5A<<8) +HF+XF+VF+NF+CF, + (0x5B<<8) +HF+XF +NF+CF, + (0x5C<<8) +HF+XF+VF+NF+CF, + (0x5D<<8) +HF+XF +NF+CF, + (0x5E<<8) +HF+XF +NF+CF, + (0x5F<<8) +HF+XF+VF+NF+CF, + (0x60<<8) +YF +VF+NF+CF, + (0x61<<8) +YF +NF+CF, + (0x62<<8) +YF +NF+CF, + (0x63<<8) +YF +VF+NF+CF, + (0x64<<8) +YF +NF+CF, + (0x65<<8) +YF +VF+NF+CF, + (0x66<<8) +YF +VF+NF+CF, + (0x67<<8) +YF +NF+CF, + (0x68<<8) +YF +XF +NF+CF, + (0x69<<8) +YF +XF+VF+NF+CF, + (0x6A<<8) +YF+HF+XF+VF+NF+CF, + (0x6B<<8) +YF+HF+XF +NF+CF, + (0x6C<<8) +YF+HF+XF+VF+NF+CF, + (0x6D<<8) +YF+HF+XF +NF+CF, + (0x6E<<8) +YF+HF+XF +NF+CF, + (0x6F<<8) +YF+HF+XF+VF+NF+CF, + (0x70<<8) +YF +NF+CF, + (0x71<<8) +YF +VF+NF+CF, + (0x72<<8) +YF +VF+NF+CF, + (0x73<<8) +YF +NF+CF, + (0x74<<8) +YF +VF+NF+CF, + (0x75<<8) +YF +NF+CF, + (0x76<<8) +YF +NF+CF, + (0x77<<8) +YF +VF+NF+CF, + (0x78<<8) +YF +XF+VF+NF+CF, + (0x79<<8) +YF +XF +NF+CF, + (0x7A<<8) +YF+HF+XF +NF+CF, + (0x7B<<8) +YF+HF+XF+VF+NF+CF, + (0x7C<<8) +YF+HF+XF +NF+CF, + (0x7D<<8) +YF+HF+XF+VF+NF+CF, + (0x7E<<8) +YF+HF+XF+VF+NF+CF, + (0x7F<<8) +YF+HF+XF +NF+CF, + (0x80<<8)+SF +NF+CF, + (0x81<<8)+SF +VF+NF+CF, + (0x82<<8)+SF +VF+NF+CF, + (0x83<<8)+SF +NF+CF, + (0x84<<8)+SF +VF+NF+CF, + (0x85<<8)+SF +NF+CF, + (0x86<<8)+SF +NF+CF, + (0x87<<8)+SF +VF+NF+CF, + (0x88<<8)+SF +XF+VF+NF+CF, + (0x89<<8)+SF +XF +NF+CF, + (0x8A<<8)+SF +HF+XF +NF+CF, + (0x8B<<8)+SF +HF+XF+VF+NF+CF, + (0x8C<<8)+SF +HF+XF +NF+CF, + (0x8D<<8)+SF +HF+XF+VF+NF+CF, + (0x8E<<8)+SF +HF+XF+VF+NF+CF, + (0x8F<<8)+SF +HF+XF +NF+CF, + (0x90<<8)+SF +VF+NF+CF, + (0x91<<8)+SF +NF+CF, + (0x92<<8)+SF +NF+CF, + (0x93<<8)+SF +VF+NF+CF, + (0x94<<8)+SF +NF+CF, + (0x95<<8)+SF +VF+NF+CF, + (0x96<<8)+SF +VF+NF+CF, + (0x97<<8)+SF +NF+CF, + (0x98<<8)+SF +XF +NF+CF, + (0x99<<8)+SF +XF+VF+NF+CF, + (0x9A<<8)+SF +HF+XF+VF+NF+CF, + (0x9B<<8)+SF +HF+XF +NF+CF, + (0x9C<<8)+SF +HF+XF+VF+NF+CF, + (0x9D<<8)+SF +HF+XF +NF+CF, + (0x9E<<8)+SF +HF+XF +NF+CF, + (0x9F<<8)+SF +HF+XF+VF+NF+CF, + (0xA0<<8)+SF +YF +VF+NF+CF, + (0xA1<<8)+SF +YF +NF+CF, + (0xA2<<8)+SF +YF +NF+CF, + (0xA3<<8)+SF +YF +VF+NF+CF, + (0xA4<<8)+SF +YF +NF+CF, + (0xA5<<8)+SF +YF +VF+NF+CF, + (0xA6<<8)+SF +YF +VF+NF+CF, + (0xA7<<8)+SF +YF +NF+CF, + (0xA8<<8)+SF +YF +XF +NF+CF, + (0xA9<<8)+SF +YF +XF+VF+NF+CF, + (0xAA<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xAB<<8)+SF +YF+HF+XF +NF+CF, + (0xAC<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xAD<<8)+SF +YF+HF+XF +NF+CF, + (0xAE<<8)+SF +YF+HF+XF +NF+CF, + (0xAF<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xB0<<8)+SF +YF +NF+CF, + (0xB1<<8)+SF +YF +VF+NF+CF, + (0xB2<<8)+SF +YF +VF+NF+CF, + (0xB3<<8)+SF +YF +NF+CF, + (0xB4<<8)+SF +YF +VF+NF+CF, + (0xB5<<8)+SF +YF +NF+CF, + (0xB6<<8)+SF +YF +NF+CF, + (0xB7<<8)+SF +YF +VF+NF+CF, + (0xB8<<8)+SF +YF +XF+VF+NF+CF, + (0xB9<<8)+SF +YF +XF +NF+CF, + (0xBA<<8)+SF +YF+HF+XF +NF+CF, + (0xBB<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xBC<<8)+SF +YF+HF+XF +NF+CF, + (0xBD<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xBE<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xBF<<8)+SF +YF+HF+XF +NF+CF, + (0xC0<<8)+SF +VF+NF+CF, + (0xC1<<8)+SF +NF+CF, + (0xC2<<8)+SF +NF+CF, + (0xC3<<8)+SF +VF+NF+CF, + (0xC4<<8)+SF +NF+CF, + (0xC5<<8)+SF +VF+NF+CF, + (0xC6<<8)+SF +VF+NF+CF, + (0xC7<<8)+SF +NF+CF, + (0xC8<<8)+SF +XF +NF+CF, + (0xC9<<8)+SF +XF+VF+NF+CF, + (0xCA<<8)+SF +HF+XF+VF+NF+CF, + (0xCB<<8)+SF +HF+XF +NF+CF, + (0xCC<<8)+SF +HF+XF+VF+NF+CF, + (0xCD<<8)+SF +HF+XF +NF+CF, + (0xCE<<8)+SF +HF+XF +NF+CF, + (0xCF<<8)+SF +HF+XF+VF+NF+CF, + (0xD0<<8)+SF +NF+CF, + (0xD1<<8)+SF +VF+NF+CF, + (0xD2<<8)+SF +VF+NF+CF, + (0xD3<<8)+SF +NF+CF, + (0xD4<<8)+SF +VF+NF+CF, + (0xD5<<8)+SF +NF+CF, + (0xD6<<8)+SF +NF+CF, + (0xD7<<8)+SF +VF+NF+CF, + (0xD8<<8)+SF +XF+VF+NF+CF, + (0xD9<<8)+SF +XF +NF+CF, + (0xDA<<8)+SF +HF+XF +NF+CF, + (0xDB<<8)+SF +HF+XF+VF+NF+CF, + (0xDC<<8)+SF +HF+XF +NF+CF, + (0xDD<<8)+SF +HF+XF+VF+NF+CF, + (0xDE<<8)+SF +HF+XF+VF+NF+CF, + (0xDF<<8)+SF +HF+XF +NF+CF, + (0xE0<<8)+SF +YF +NF+CF, + (0xE1<<8)+SF +YF +VF+NF+CF, + (0xE2<<8)+SF +YF +VF+NF+CF, + (0xE3<<8)+SF +YF +NF+CF, + (0xE4<<8)+SF +YF +VF+NF+CF, + (0xE5<<8)+SF +YF +NF+CF, + (0xE6<<8)+SF +YF +NF+CF, + (0xE7<<8)+SF +YF +VF+NF+CF, + (0xE8<<8)+SF +YF +XF+VF+NF+CF, + (0xE9<<8)+SF +YF +XF +NF+CF, + (0xEA<<8)+SF +YF+HF+XF +NF+CF, + (0xEB<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xEC<<8)+SF +YF+HF+XF +NF+CF, + (0xED<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xEE<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xEF<<8)+SF +YF+HF+XF +NF+CF, + (0xF0<<8)+SF +YF +VF+NF+CF, + (0xF1<<8)+SF +YF +NF+CF, + (0xF2<<8)+SF +YF +NF+CF, + (0xF3<<8)+SF +YF +VF+NF+CF, + (0xF4<<8)+SF +YF +NF+CF, + (0xF5<<8)+SF +YF +VF+NF+CF, + (0xF6<<8)+SF +YF +VF+NF+CF, + (0xF7<<8)+SF +YF +NF+CF, + (0xF8<<8)+SF +YF +XF +NF+CF, + (0xF9<<8)+SF +YF +XF+VF+NF+CF, + (0xFA<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xFB<<8)+SF +YF+HF+XF +NF+CF, + (0xFC<<8)+SF +YF+HF+XF+VF+NF+CF, + (0xFD<<8)+SF +YF+HF+XF +NF+CF, + (0xFE<<8)+SF +YF+HF+XF +NF+CF, + (0xFF<<8)+SF +YF+HF+XF+VF+NF+CF, + (0x00<<8) +ZF +VF+NF+CF, + (0x01<<8) +NF+CF, + (0x02<<8) +NF+CF, + (0x03<<8) +VF+NF+CF, + (0x04<<8) +NF+CF, + (0x05<<8) +VF+NF+CF, + (0x06<<8) +VF+NF+CF, + (0x07<<8) +NF+CF, + (0x08<<8) +XF +NF+CF, + (0x09<<8) +XF+VF+NF+CF, + (0x0A<<8) +HF+XF+VF+NF+CF, + (0x0B<<8) +HF+XF +NF+CF, + (0x0C<<8) +HF+XF+VF+NF+CF, + (0x0D<<8) +HF+XF +NF+CF, + (0x0E<<8) +HF+XF +NF+CF, + (0x0F<<8) +HF+XF+VF+NF+CF, + (0x10<<8) +NF+CF, + (0x11<<8) +VF+NF+CF, + (0x12<<8) +VF+NF+CF, + (0x13<<8) +NF+CF, + (0x14<<8) +VF+NF+CF, + (0x15<<8) +NF+CF, + (0x16<<8) +NF+CF, + (0x17<<8) +VF+NF+CF, + (0x18<<8) +XF+VF+NF+CF, + (0x19<<8) +XF +NF+CF, + (0x1A<<8) +HF+XF +NF+CF, + (0x1B<<8) +HF+XF+VF+NF+CF, + (0x1C<<8) +HF+XF +NF+CF, + (0x1D<<8) +HF+XF+VF+NF+CF, + (0x1E<<8) +HF+XF+VF+NF+CF, + (0x1F<<8) +HF+XF +NF+CF, + (0x20<<8) +YF +NF+CF, + (0x21<<8) +YF +VF+NF+CF, + (0x22<<8) +YF +VF+NF+CF, + (0x23<<8) +YF +NF+CF, + (0x24<<8) +YF +VF+NF+CF, + (0x25<<8) +YF +NF+CF, + (0x26<<8) +YF +NF+CF, + (0x27<<8) +YF +VF+NF+CF, + (0x28<<8) +YF +XF+VF+NF+CF, + (0x29<<8) +YF +XF +NF+CF, + (0x2A<<8) +YF+HF+XF +NF+CF, + (0x2B<<8) +YF+HF+XF+VF+NF+CF, + (0x2C<<8) +YF+HF+XF +NF+CF, + (0x2D<<8) +YF+HF+XF+VF+NF+CF, + (0x2E<<8) +YF+HF+XF+VF+NF+CF, + (0x2F<<8) +YF+HF+XF +NF+CF, + (0x30<<8) +YF +VF+NF+CF, + (0x31<<8) +YF +NF+CF, + (0x32<<8) +YF +NF+CF, + (0x33<<8) +YF +VF+NF+CF, + (0x34<<8) +YF +NF+CF, + (0x35<<8) +YF +VF+NF+CF, + (0x36<<8) +YF +VF+NF+CF, + (0x37<<8) +YF +NF+CF, + (0x38<<8) +YF +XF +NF+CF, + (0x39<<8) +YF +XF+VF+NF+CF, + (0x3A<<8) +YF+HF+XF+VF+NF+CF, + (0x3B<<8) +YF+HF+XF +NF+CF, + (0x3C<<8) +YF+HF+XF+VF+NF+CF, + (0x3D<<8) +YF+HF+XF +NF+CF, + (0x3E<<8) +YF+HF+XF +NF+CF, + (0x3F<<8) +YF+HF+XF+VF+NF+CF, + (0x40<<8) +NF+CF, + (0x41<<8) +VF+NF+CF, + (0x42<<8) +VF+NF+CF, + (0x43<<8) +NF+CF, + (0x44<<8) +VF+NF+CF, + (0x45<<8) +NF+CF, + (0x46<<8) +NF+CF, + (0x47<<8) +VF+NF+CF, + (0x48<<8) +XF+VF+NF+CF, + (0x49<<8) +XF +NF+CF, + (0x4A<<8) +HF+XF +NF+CF, + (0x4B<<8) +HF+XF+VF+NF+CF, + (0x4C<<8) +HF+XF +NF+CF, + (0x4D<<8) +HF+XF+VF+NF+CF, + (0x4E<<8) +HF+XF+VF+NF+CF, + (0x4F<<8) +HF+XF +NF+CF, + (0x50<<8) +VF+NF+CF, + (0x51<<8) +NF+CF, + (0x52<<8) +NF+CF, + (0x53<<8) +VF+NF+CF, + (0x54<<8) +NF+CF, + (0x55<<8) +VF+NF+CF, + (0x56<<8) +VF+NF+CF, + (0x57<<8) +NF+CF, + (0x58<<8) +XF +NF+CF, + (0x59<<8) +XF+VF+NF+CF, + (0x5A<<8) +HF+XF+VF+NF+CF, + (0x5B<<8) +HF+XF +NF+CF, + (0x5C<<8) +HF+XF+VF+NF+CF, + (0x5D<<8) +HF+XF +NF+CF, + (0x5E<<8) +HF+XF +NF+CF, + (0x5F<<8) +HF+XF+VF+NF+CF, + (0x60<<8) +YF +VF+NF+CF, + (0x61<<8) +YF +NF+CF, + (0x62<<8) +YF +NF+CF, + (0x63<<8) +YF +VF+NF+CF, + (0x64<<8) +YF +NF+CF, + (0x65<<8) +YF +VF+NF+CF, + (0x66<<8) +YF +VF+NF+CF, + (0x67<<8) +YF +NF+CF, + (0x68<<8) +YF +XF +NF+CF, + (0x69<<8) +YF +XF+VF+NF+CF, + (0x6A<<8) +YF+HF+XF+VF+NF+CF, + (0x6B<<8) +YF+HF+XF +NF+CF, + (0x6C<<8) +YF+HF+XF+VF+NF+CF, + (0x6D<<8) +YF+HF+XF +NF+CF, + (0x6E<<8) +YF+HF+XF +NF+CF, + (0x6F<<8) +YF+HF+XF+VF+NF+CF, + (0x70<<8) +YF +NF+CF, + (0x71<<8) +YF +VF+NF+CF, + (0x72<<8) +YF +VF+NF+CF, + (0x73<<8) +YF +NF+CF, + (0x74<<8) +YF +VF+NF+CF, + (0x75<<8) +YF +NF+CF, + (0x76<<8) +YF +NF+CF, + (0x77<<8) +YF +VF+NF+CF, + (0x78<<8) +YF +XF+VF+NF+CF, + (0x79<<8) +YF +XF +NF+CF, + (0x7A<<8) +YF+HF+XF +NF+CF, + (0x7B<<8) +YF+HF+XF+VF+NF+CF, + (0x7C<<8) +YF+HF+XF +NF+CF, + (0x7D<<8) +YF+HF+XF+VF+NF+CF, + (0x7E<<8) +YF+HF+XF+VF+NF+CF, + (0x7F<<8) +YF+HF+XF +NF+CF, + (0x80<<8)+SF +NF+CF, + (0x81<<8)+SF +VF+NF+CF, + (0x82<<8)+SF +VF+NF+CF, + (0x83<<8)+SF +NF+CF, + (0x84<<8)+SF +VF+NF+CF, + (0x85<<8)+SF +NF+CF, + (0x86<<8)+SF +NF+CF, + (0x87<<8)+SF +VF+NF+CF, + (0x88<<8)+SF +XF+VF+NF+CF, + (0x89<<8)+SF +XF +NF+CF, + (0x8A<<8)+SF +HF+XF +NF+CF, + (0x8B<<8)+SF +HF+XF+VF+NF+CF, + (0x8C<<8)+SF +HF+XF +NF+CF, + (0x8D<<8)+SF +HF+XF+VF+NF+CF, + (0x8E<<8)+SF +HF+XF+VF+NF+CF, + (0x8F<<8)+SF +HF+XF +NF+CF, + (0x90<<8)+SF +VF+NF+CF, + (0x91<<8)+SF +NF+CF, + (0x92<<8)+SF +NF+CF, + (0x93<<8)+SF +VF+NF+CF, + (0x94<<8)+SF +NF+CF, + (0x95<<8)+SF +VF+NF+CF, + (0x96<<8)+SF +VF+NF+CF, + (0x97<<8)+SF +NF+CF, + (0x98<<8)+SF +XF +NF+CF, + (0x99<<8)+SF +XF+VF+NF+CF +}; + diff --git a/i2ckeyboard/atmegai2ckeyboard/atmegai2ckeyboard.ino b/i2ckeyboard/atmegai2ckeyboard/atmegai2ckeyboard.ino index 7ecd627..2b5cd43 100644 --- a/i2ckeyboard/atmegai2ckeyboard/atmegai2ckeyboard.ino +++ b/i2ckeyboard/atmegai2ckeyboard/atmegai2ckeyboard.ino @@ -5,159 +5,160 @@ static byte msg[7]; // rows are inputs -static byte rows[] = {11,10,9,12,13,8,7,6,5,4};// {2,3,4}; -const int rowCount = sizeof(rows)/sizeof(rows[0]); - -// cols are outputs -static byte cols[] = {A3,A2,A1,A0,3}; //{8,9,10,11}; -const int colCount = sizeof(cols)/sizeof(cols[0]); - -static byte keys[colCount][rowCount]; - -void setup() { - //Serial.begin(115200); - - Wire.begin(8); // join i2c bus with address #8 - Wire.onRequest(requestEvent); // register event +//static byte rows[] = {11, 10, 9, 12, 13, 8, 7, 6, 5, 4}; // {2,3,4}; +static byte rows[] = {4, 5, 6, 7, 8, 13, 12, 9, 10, 11}; // {2,3,4}; +const int rowCount = sizeof(rows) / sizeof(rows[0]); + +// cols are outputs +static byte cols[] = {A3, A2, A1, A0, 3}; //{8,9,10,11}; +const int colCount = sizeof(cols) / sizeof(cols[0]); + +static byte keys[colCount][rowCount]; + +void setup() { + //Serial.begin(115200); + + Wire.begin(8); // join i2c bus with address #8 + Wire.onRequest(requestEvent); // register event + + for (int x = 0; x < rowCount; x++) { + //Serial.print(rows[x]); Serial.println(" as input"); + pinMode(rows[x], INPUT); + } + + for (int x = 0; x < colCount; x++) { + //Serial.print(cols[x]); Serial.println(" as input-pullup"); + pinMode(cols[x], INPUT_PULLUP); + } - for(int x=0; xfHGrMPZ&lCOJP>1aj?9cnPcAb4yD(ZRIQ+X@aCvC(kcOr_frV_x@UMT<;i<6!4Nb5J4bA%xG&H1tr1u*% zH2yL)G+S?IXjIc_Xt=$z8eXXX8({W+`pTDvhK2J#CoN4z7SBHoEN-S2eijD$stzDe zDLY4yy^~a+r}sZJ4UKxB>c6I^lb_wqKu-@ZU)4Yjq5ndt{%ik-EG=~NzaW0@8bTHZ z&u?mhe4K9Hmr{_D5z@SL^X5%;A4g|ZSJEh8r_Cnxz2A?X|BE(O-zlHoSIgg!u9emup{oFuaH~%Bo&K~6Nry(Tt zA4UKB_-{M?+?@Z9CNJOraqFLh(*GHemX(r`{@=3yv8w-vs%q@y3-a*)kNB5fZho3_ z>i-4)f64zx+kbOufjqr^oP2%%v1!Ww56k~e`+xC9K5kC`{QHlZ|Be5@Y5y<&xhu#I z^e@&vZVtL$eoj9Bl>HC)|1$9ZAMro3)TRFuuKz21|DBuvqW(*c<|TFM|D9;fOB~ww zl4)oj(C9vXXc|cCNSVrz(EV~}gBYz`?qud(C9ueXfaGj zivBvM;nO*1^-|j+J(}C@$_o>D>OS=xMgbzB=VapQ3<$V(ytq1mK}iENo0>w22glmP zlNpe$CX9G+a9?^|S{h)}0;L>$0T#i6h-)26xkga|!Uk^Vq=U^vOd1wS*>TWI8hg?J6+}}pPZ8a$;D*sF+A4|g^#2H&E>0lj5MGwHK zM8Iv){(@FIbQEae{pq%i+nJ(zFZEzUzNCdwZ(}OjChTAp?ZLm;tVt1AB%C=!+x$Ig zmqI&%iI-!MW(jcEKYKy2v+V&Y1xdk7pK7r__h|baV-sd|zK?g&8%9Rsh)e-3PRXE0 zR;s&gy4-Rd-w~u+#~wGGM+n~n2ur@fkGUxu#|OJH_mruJKOn9cJP~e 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