MCUME/MCUME_pico/vga_t4/scanvideo.pio.h
2021-04-10 12:28:04 +02:00

131 lines
5.9 KiB
C

// -------------------------------------------------- //
// This file is autogenerated by pioasm; do not edit! //
// -------------------------------------------------- //
#if !PICO_NO_HARDWARE
#include "hardware/pio.h"
#endif
// ------------------------------ //
// video_24mhz_composable_default //
// ------------------------------ //
#define video_24mhz_composable_default_wrap_target 11
#define video_24mhz_composable_default_wrap 13
#define video_24mhz_composable_default_offset_end_of_scanline_skip_ALIGN 0u
#define video_24mhz_composable_default_offset_end_of_scanline_ALIGN 1u
#define video_24mhz_composable_default_offset_entry_point 1u
#define video_24mhz_composable_default_offset_nop_raw 2u
#define video_24mhz_composable_default_offset_delay_h_0 3u
#define video_24mhz_composable_default_offset_color_run 3u
#define video_24mhz_composable_default_offset_delay_a_1 5u
#define video_24mhz_composable_default_offset_nop_extra1 6u
#define video_24mhz_composable_default_offset_delay_b_1 6u
#define video_24mhz_composable_default_offset_raw_run 7u
#define video_24mhz_composable_default_offset_delay_c_0 7u
#define video_24mhz_composable_default_offset_delay_d_0 9u
#define video_24mhz_composable_default_offset_raw_1p 11u
#define video_24mhz_composable_default_offset_delay_e_0 11u
#define video_24mhz_composable_default_offset_raw_2p 13u
#define video_24mhz_composable_default_offset_delay_f_1 13u
#define video_24mhz_composable_default_offset_raw_1p_skip_ALIGN 14u
#define video_24mhz_composable_default_offset_nop_extra0 15u
#define video_24mhz_composable_default_offset_delay_g_0 15u
static const uint16_t video_24mhz_composable_default_program_instructions[] = {
0x6060, // 0: out null, 32
0x20c4, // 1: wait 1 irq, 4
0x60b0, // 2: out pc, 16
0x6010, // 3: out pins, 16
0x6030, // 4: out x, 16
0x0045, // 5: jmp x--, 5
0x60b0, // 6: out pc, 16
0x6010, // 7: out pins, 16
0x6030, // 8: out x, 16
0x6010, // 9: out pins, 16
0x0049, // 10: jmp x--, 9
// .wrap_target
0x6010, // 11: out pins, 16
0x60b0, // 12: out pc, 16
0x6010, // 13: out pins, 16
// .wrap
0x6000, // 14: out pins, 32
0x60b0, // 15: out pc, 16
};
#if !PICO_NO_HARDWARE
static const struct pio_program video_24mhz_composable_default_program = {
.instructions = video_24mhz_composable_default_program_instructions,
.length = 16,
.origin = 0,
};
static inline pio_sm_config video_24mhz_composable_default_program_get_default_config(uint offset) {
pio_sm_config c = pio_get_default_sm_config();
sm_config_set_wrap(&c, offset + video_24mhz_composable_default_wrap_target, offset + video_24mhz_composable_default_wrap);
return c;
}
#endif
// ----------------------------------- //
// video_24mhz_composable_raw1p_2cycle //
// ----------------------------------- //
#define video_24mhz_composable_raw1p_2cycle_wrap_target 11
#define video_24mhz_composable_raw1p_2cycle_wrap 13
#define video_24mhz_composable_raw1p_2cycle_offset_end_of_scanline_skip_ALIGN 0u
#define video_24mhz_composable_raw1p_2cycle_offset_end_of_scanline_ALIGN 1u
#define video_24mhz_composable_raw1p_2cycle_offset_entry_point 1u
#define video_24mhz_composable_raw1p_2cycle_offset_nop_raw 2u
#define video_24mhz_composable_raw1p_2cycle_offset_color_run 3u
#define video_24mhz_composable_raw1p_2cycle_offset_delay_h_0 3u
#define video_24mhz_composable_raw1p_2cycle_offset_delay_a_1 5u
#define video_24mhz_composable_raw1p_2cycle_offset_nop_extra1 6u
#define video_24mhz_composable_raw1p_2cycle_offset_delay_b_1 6u
#define video_24mhz_composable_raw1p_2cycle_offset_raw_run 7u
#define video_24mhz_composable_raw1p_2cycle_offset_delay_c_0 7u
#define video_24mhz_composable_raw1p_2cycle_offset_delay_d_0 9u
#define video_24mhz_composable_raw1p_2cycle_offset_raw_1p 11u
#define video_24mhz_composable_raw1p_2cycle_offset_delay_e_0 11u
#define video_24mhz_composable_raw1p_2cycle_offset_raw_2p 13u
#define video_24mhz_composable_raw1p_2cycle_offset_delay_f_1 13u
#define video_24mhz_composable_raw1p_2cycle_offset_raw_1p_2cycle 14u
#define video_24mhz_composable_raw1p_2cycle_offset_delay_g_0 14u
static const uint16_t video_24mhz_composable_raw1p_2cycle_program_instructions[] = {
0x6060, // 0: out null, 32
0x20c4, // 1: wait 1 irq, 4
0x60b0, // 2: out pc, 16
0x6010, // 3: out pins, 16
0x6030, // 4: out x, 16
0x0045, // 5: jmp x--, 5
0x60b0, // 6: out pc, 16
0x6010, // 7: out pins, 16
0x6030, // 8: out x, 16
0x6010, // 9: out pins, 16
0x0049, // 10: jmp x--, 9
// .wrap_target
0x6010, // 11: out pins, 16
0x60b0, // 12: out pc, 16
0x6010, // 13: out pins, 16
// .wrap
0x6010, // 14: out pins, 16
0x60b0, // 15: out pc, 16
};
#if !PICO_NO_HARDWARE
static const struct pio_program video_24mhz_composable_raw1p_2cycle_program = {
.instructions = video_24mhz_composable_raw1p_2cycle_program_instructions,
.length = 16,
.origin = 0,
};
static inline pio_sm_config video_24mhz_composable_raw1p_2cycle_program_get_default_config(uint offset) {
pio_sm_config c = pio_get_default_sm_config();
sm_config_set_wrap(&c, offset + video_24mhz_composable_raw1p_2cycle_wrap_target, offset + video_24mhz_composable_raw1p_2cycle_wrap);
return c;
}
#endif