diff --git a/software/libdvi/dvi_serialiser.c b/software/libdvi/dvi_serialiser.c index 308f23f..6a08d6e 100644 --- a/software/libdvi/dvi_serialiser.c +++ b/software/libdvi/dvi_serialiser.c @@ -63,6 +63,8 @@ void dvi_serialiser_enable(struct dvi_serialiser_cfg *cfg, bool enable) { for (int i = 0; i < N_TMDS_LANES; ++i) mask |= 1u << (cfg->sm_tmds[i] + PIO_CTRL_SM_ENABLE_LSB); if (enable) { + // The DVI spec allows for phase offset between clock and data links. + // So PWM and PIO do not need to be synchronised perfectly. hw_set_bits(&cfg->pio->ctrl, mask); pwm_set_enabled(pwm_gpio_to_slice_num(cfg->pins_clk), true); } diff --git a/software/libdvi/dvi_timing.c b/software/libdvi/dvi_timing.c index ec17ff7..7594db0 100644 --- a/software/libdvi/dvi_timing.c +++ b/software/libdvi/dvi_timing.c @@ -217,7 +217,7 @@ static uint32_t __attribute__((aligned(8))) __dvi_const(empty_scanline_tmds)[6] void dvi_timing_state_init(struct dvi_timing_state *t) { t->v_ctr = 0; t->v_state = DVI_STATE_FRONT_PORCH; -}; +} void __dvi_func(dvi_timing_state_advance)(const struct dvi_timing *t, struct dvi_timing_state *s) { s->v_ctr++; @@ -252,7 +252,7 @@ static void _set_data_cb(dma_cb_t *cb, const struct dvi_lane_dma_cfg *dma_cfg, channel_config_set_chain_to(&cb->c, dma_cfg->chan_ctrl); // Note we never send a null trigger, so IRQ_QUIET is an IRQ suppression flag channel_config_set_irq_quiet(&cb->c, !irq_on_finish); -}; +} void dvi_setup_scanline_for_vblank(const struct dvi_timing *t, const struct dvi_lane_dma_cfg dma_cfg[], bool vsync_asserted, struct dvi_scanline_dma_list *l) { diff --git a/software/libdvi/tmds_encode.c b/software/libdvi/tmds_encode.c index 472b1a9..43a81c2 100644 --- a/software/libdvi/tmds_encode.c +++ b/software/libdvi/tmds_encode.c @@ -191,7 +191,7 @@ static void tmds_encode_symbols(uint8_t pixel, uint32_t* negative_balance_sym, u } int imbalance = byte_imbalance(sym & 0xFF); - if (imbalance == 0) { + if (imbalance == 0) { if ((sym & 0x100) == 0) sym ^= 0x2ff; *positive_balance_sym = sym; *negative_balance_sym = sym;