Maple STM32F1 added
This commit is contained in:
Bill Greiman
parent
c092796599
commit
fe80cc35c4
3 changed files with 214 additions and 37 deletions
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@ -27,7 +27,7 @@
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#include "utility/FatLib.h"
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//------------------------------------------------------------------------------
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/** SdFat version YYYYMMDD */
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#define SD_FAT_VERSION 20150321
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#define SD_FAT_VERSION 20150324
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//==============================================================================
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/**
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* \class SdBaseFile
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171
SdFat/SdSpiSTM32F1.cpp
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171
SdFat/SdSpiSTM32F1.cpp
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@ -0,0 +1,171 @@
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/* Arduino SdSpi Library
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* Copyright (C) 2013 by William Greiman
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*
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* STM32F1 code for Maple and Maple Mini support, 2015 by Victor Perez
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*
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* This file is part of the Arduino SdSpi Library
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*
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* This Library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This Library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the Arduino SdSpi Library. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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#if defined(__STM32F1__)
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#include "SdSpi.h"
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#include <SPI.h>
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#include <libmaple/dma.h>
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/** Use STM32 DMAC if nonzero */
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#define USE_STM32F1_DMAC 1
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/** Time in ms for DMA receive timeout */
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#define STM32F1_DMA_TIMEOUT 100
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/** DMAC receive channel */
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#define SPI1_DMAC_RX_CH DMA_CH2
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/** DMAC transmit channel */
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#define SPI1_DMAC_TX_CH DMA_CH3
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volatile bool SPI_DMA_TX_Active = false;
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volatile bool SPI_DMA_RX_Active = false;
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/** ISR for DMA TX event. */
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inline void SPI_DMA_TX_Event() {
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SPI_DMA_TX_Active = false;
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dma_disable(DMA1, SPI_DMAC_TX_CH);
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}
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/** ISR for DMA RX event. */
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inline void SPI_DMA_RX_Event() {
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SPI_DMA_RX_Active = false;
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dma_disable(DMA1, SPI1_DMAC_RX_CH);
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}
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//------------------------------------------------------------------------------
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/** Disable DMA Channel. */
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static void dmac_channel_disable(dma_channel ul_num) {
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dma_disable(DMA1, ul_num);
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}
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/** Enable DMA Channel. */
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static void dmac_channel_enable(dma_channel ul_num) {
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dma_enable(DMA1, ul_num);
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}
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//------------------------------------------------------------------------------
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void SdSpi::begin() {
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SPI.begin();
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}
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//------------------------------------------------------------------------------
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// start RX DMA
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static void spiDmaRX(uint8_t* dst, uint16_t count) {
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// spi_rx_dma_enable(SPI1);
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if (count < 1) return;
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dma_setup_transfer(DMA1, SPI1_DMAC_RX_CH, &SPI1->regs->DR, DMA_SIZE_8BITS,
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dst, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));
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dma_set_num_transfers(DMA1, SPI1_DMAC_RX_CH, count); // 2 bytes per pixel
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SPI_DMA_RX_Active = true;
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dma_enable(DMA1, SPI1_DMAC_RX_CH);
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}
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//------------------------------------------------------------------------------
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// start TX DMA
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static void spiDmaTX(const uint8_t* src, uint16_t count) {
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if (count < 1) return;
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static uint8_t ff = 0XFF;
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if (!src) {
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src = &ff;
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dma_setup_transfer(DMA1, SPI1_DMAC_TX_CH, &SPI1->regs->DR, DMA_SIZE_8BITS,
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const_cast<uint8_t*>(src), DMA_SIZE_8BITS,
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(DMA_FROM_MEM | DMA_TRNS_CMPLT));
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} else {
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dma_setup_transfer(DMA1, SPI1_DMAC_TX_CH, &SPI1->regs->DR, DMA_SIZE_8BITS,
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const_cast<uint8_t*>(src), DMA_SIZE_8BITS,
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(DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT));
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}
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dma_set_num_transfers(DMA1, SPI1_DMAC_TX_CH, count); // 2 bytes per pixel
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SPI_DMA_TX_Active = true;
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dma_enable(DMA1, SPI1_DMAC_TX_CH);
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}
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//------------------------------------------------------------------------------
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// initialize SPI controller STM32F1
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void SdSpi::init(uint8_t sckDivisor) {
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if (sckDivisor < SPI_CLOCK_DIV2 || sckDivisor > SPI_CLOCK_DIV256) {
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sckDivisor = SPI_CLOCK_DIV2; // may not be needed, testing.
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}
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SPI.setClockDivider(sckDivisor);
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SPI.setBitOrder(MSBFIRST);
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SPI.setDataMode(SPI_MODE0);
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#if USE_STM32F1_DMAC
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dma_init(DMA1);
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dma_attach_interrupt(DMA1, SPI1_DMAC_TX_CH, SPI_DMA_TX_Event);
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dma_attach_interrupt(DMA1, SPI1_DMAC_RX_CH, SPI_DMA_RX_Event);
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spi_tx_dma_enable(SPI1);
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spi_rx_dma_enable(SPI1);
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#endif // USE_STM32F1_DMAC
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}
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//------------------------------------------------------------------------------
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// STM32
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static inline uint8_t spiTransfer(uint8_t b) {
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return SPI.transfer(b);
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}
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//------------------------------------------------------------------------------
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// should be valid for STM32
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/** SPI receive a byte */
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uint8_t SdSpi::receive() {
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return spiTransfer(0xFF);
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}
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//------------------------------------------------------------------------------
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/** SPI receive multiple bytes */
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// check and finish.
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uint8_t SdSpi::receive(uint8_t* buf, size_t n) {
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int rtn = 0;
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#if USE_STM32F1_DMAC
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spiDmaRX(buf, n);
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spiDmaTX(0, n);
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uint32_t m = millis();
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while (SPI_DMA_RX_Active) {
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if ((millis() - m) > STM32F1_DMA_TIMEOUT) {
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dmac_channel_disable(SPI_DMAC_RX_CH);
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dmac_channel_disable(SPI_DMAC_TX_CH);
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rtn = 2;
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break;
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}
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}
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#else // USE_STM32F1_DMAC
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for (size_t i = 0; i < n; i++) {
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buf[i] = SPI.transfer(0xFF);
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}
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#endif // USE_STM32F1_DMAC
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return rtn;
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}
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//------------------------------------------------------------------------------
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/** SPI send a byte */
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void SdSpi::send(uint8_t b) {
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spiTransfer(b);
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}
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//------------------------------------------------------------------------------
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void SdSpi::send(const uint8_t* buf , size_t n) {
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#if USE_STM32F1_DMAC
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spiDmaTX(buf, n);
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while (SPI_DMA_TX_Active) {}
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#else // #if USE_STM32F1_DMAC
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SPI.write(buf, n);
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#endif // #if USE_STM32F1_DMAC
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// leave RX register empty
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// while (spi_is_rx_nonempty(SPI1))
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uint8_t b = spi_rx_reg(SPI1);
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}
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#endif // USE_NATIVE_STM32F1_SPI
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@ -213,41 +213,47 @@ static const pin_map_t pinMap[] = {
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#ifdef PORT_D0
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// Newer version of 1284P
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static const pin_map_t pinMap[] = {
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{PORT_TO_MODE(PORT_D0), PORT_TO_INPUT(PORT_D0), PORT_TO_OUTPUT(PORT_D0), BIT_D0},
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{PORT_TO_MODE(PORT_D1), PORT_TO_INPUT(PORT_D1), PORT_TO_OUTPUT(PORT_D1), BIT_D1},
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{PORT_TO_MODE(PORT_D2), PORT_TO_INPUT(PORT_D2), PORT_TO_OUTPUT(PORT_D2), BIT_D2},
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{PORT_TO_MODE(PORT_D3), PORT_TO_INPUT(PORT_D3), PORT_TO_OUTPUT(PORT_D3), BIT_D3},
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{PORT_TO_MODE(PORT_D4), PORT_TO_INPUT(PORT_D4), PORT_TO_OUTPUT(PORT_D4), BIT_D4},
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{PORT_TO_MODE(PORT_D5), PORT_TO_INPUT(PORT_D5), PORT_TO_OUTPUT(PORT_D5), BIT_D5},
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{PORT_TO_MODE(PORT_D6), PORT_TO_INPUT(PORT_D6), PORT_TO_OUTPUT(PORT_D6), BIT_D6},
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{PORT_TO_MODE(PORT_D7), PORT_TO_INPUT(PORT_D7), PORT_TO_OUTPUT(PORT_D7), BIT_D7},
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{PORT_TO_MODE(PORT_D8), PORT_TO_INPUT(PORT_D8), PORT_TO_OUTPUT(PORT_D8), BIT_D8},
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{PORT_TO_MODE(PORT_D9), PORT_TO_INPUT(PORT_D9), PORT_TO_OUTPUT(PORT_D9), BIT_D9},
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{PORT_TO_MODE(PORT_D10), PORT_TO_INPUT(PORT_D10), PORT_TO_OUTPUT(PORT_D10), BIT_D10},
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{PORT_TO_MODE(PORT_D11), PORT_TO_INPUT(PORT_D11), PORT_TO_OUTPUT(PORT_D11), BIT_D11},
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{PORT_TO_MODE(PORT_D12), PORT_TO_INPUT(PORT_D12), PORT_TO_OUTPUT(PORT_D12), BIT_D12},
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{PORT_TO_MODE(PORT_D13), PORT_TO_INPUT(PORT_D13), PORT_TO_OUTPUT(PORT_D13), BIT_D13},
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{PORT_TO_MODE(PORT_D14), PORT_TO_INPUT(PORT_D14), PORT_TO_OUTPUT(PORT_D14), BIT_D14},
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{PORT_TO_MODE(PORT_D15), PORT_TO_INPUT(PORT_D15), PORT_TO_OUTPUT(PORT_D15), BIT_D15},
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{PORT_TO_MODE(PORT_D16), PORT_TO_INPUT(PORT_D16), PORT_TO_OUTPUT(PORT_D16), BIT_D16},
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{PORT_TO_MODE(PORT_D17), PORT_TO_INPUT(PORT_D17), PORT_TO_OUTPUT(PORT_D17), BIT_D17},
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{PORT_TO_MODE(PORT_D18), PORT_TO_INPUT(PORT_D18), PORT_TO_OUTPUT(PORT_D18), BIT_D18},
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{PORT_TO_MODE(PORT_D19), PORT_TO_INPUT(PORT_D19), PORT_TO_OUTPUT(PORT_D19), BIT_D19},
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{PORT_TO_MODE(PORT_D20), PORT_TO_INPUT(PORT_D20), PORT_TO_OUTPUT(PORT_D20), BIT_D20},
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{PORT_TO_MODE(PORT_D21), PORT_TO_INPUT(PORT_D21), PORT_TO_OUTPUT(PORT_D21), BIT_D21},
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{PORT_TO_MODE(PORT_D22), PORT_TO_INPUT(PORT_D22), PORT_TO_OUTPUT(PORT_D22), BIT_D22},
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{PORT_TO_MODE(PORT_D23), PORT_TO_INPUT(PORT_D23), PORT_TO_OUTPUT(PORT_D23), BIT_D23},
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{PORT_TO_MODE(PORT_D24), PORT_TO_INPUT(PORT_D24), PORT_TO_OUTPUT(PORT_D24), BIT_D24},
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{PORT_TO_MODE(PORT_D25), PORT_TO_INPUT(PORT_D25), PORT_TO_OUTPUT(PORT_D25), BIT_D25},
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{PORT_TO_MODE(PORT_D26), PORT_TO_INPUT(PORT_D26), PORT_TO_OUTPUT(PORT_D26), BIT_D26},
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{PORT_TO_MODE(PORT_D27), PORT_TO_INPUT(PORT_D27), PORT_TO_OUTPUT(PORT_D27), BIT_D27},
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{PORT_TO_MODE(PORT_D28), PORT_TO_INPUT(PORT_D28), PORT_TO_OUTPUT(PORT_D28), BIT_D28},
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{PORT_TO_MODE(PORT_D29), PORT_TO_INPUT(PORT_D29), PORT_TO_OUTPUT(PORT_D29), BIT_D29},
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{PORT_TO_MODE(PORT_D30), PORT_TO_INPUT(PORT_D30), PORT_TO_OUTPUT(PORT_D30), BIT_D30},
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{PORT_TO_MODE(PORT_D31), PORT_TO_INPUT(PORT_D31), PORT_TO_OUTPUT(PORT_D31), BIT_D31}
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#define DPM(x) {PORT_TO_MODE(PORT_D##x), PORT_TO_INPUT(PORT_D##x), \
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PORT_TO_OUTPUT(PORT_D##x), BIT_D##x}
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static const pin_map_t pinMap[] = {
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DPM(0),
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DPM(1),
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DPM(2),
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DPM(3),
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DPM(4),
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DPM(5),
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DPM(6),
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DPM(7),
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DPM(8),
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DPM(9),
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DPM(10),
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DPM(11),
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DPM(12),
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DPM(13),
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DPM(14),
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DPM(15),
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DPM(16),
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DPM(17),
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DPM(18),
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DPM(19),
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DPM(20),
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DPM(21),
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DPM(22),
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DPM(23),
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DPM(24),
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DPM(25),
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DPM(26),
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DPM(27),
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DPM(28),
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DPM(29),
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DPM(30),
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DPM(31)
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};
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#elif analogInputToDigitalPin(0)==24
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#undef DPM
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#elif analogInputToDigitalPin(0) == 24
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// Mighty Layout
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static const pin_map_t pinMap[] = {
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{&DDRB, &PINB, &PORTB, 0}, // B0 0
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@ -283,7 +289,7 @@ static const pin_map_t pinMap[] = {
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{&DDRA, &PINA, &PORTA, 6}, // A6 30
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{&DDRA, &PINA, &PORTA, 7} // A7 31
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};
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#elif analogInputToDigitalPin(0)==21
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#elif analogInputToDigitalPin(0) == 21
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// Bobuino Layout
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static const pin_map_t pinMap[] = {
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{&DDRD, &PIND, &PORTD, 0}, // D0 0
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@ -319,7 +325,7 @@ static const pin_map_t pinMap[] = {
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{&DDRD, &PIND, &PORTD, 4}, // D4 30
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{&DDRD, &PIND, &PORTD, 7} // D7 31
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};
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#elif analogInputToDigitalPin(0)==31
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#elif analogInputToDigitalPin(0) == 31
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// Standard Layout
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static const pin_map_t pinMap[] = {
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{&DDRB, &PINB, &PORTB, 0}, // B0 0
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