528 lines
No EOL
25 KiB
C
528 lines
No EOL
25 KiB
C
/**
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* \file
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* \brief Definitions for Teensy HDHC.
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*/
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#pragma once
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// From Paul's SD.h driver.
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#if defined(__IMXRT1062__)
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#define MAKE_REG_MASK(m, s) (((uint32_t)(((uint32_t)(m) << s))))
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#define MAKE_REG_GET(x, m, s) (((uint32_t)(((uint32_t)(x) >> s) & m)))
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#define MAKE_REG_SET(x, m, s) (((uint32_t)(((uint32_t)(x) & m) << s)))
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#define SDHC_BLKATTR_BLKSIZE_MASK \
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MAKE_REG_MASK( \
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0x1FFF, 0) // uint32_t)(((n) & 0x1FFF)<<0) // Transfer Block Size Mask
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#define SDHC_BLKATTR_BLKSIZE(n) \
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MAKE_REG_SET(n, 0x1FFF, \
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0) // uint32_t)(((n) & 0x1FFF)<<0) // Transfer Block Size
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#define SDHC_BLKATTR_BLKCNT_MASK \
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MAKE_REG_MASK(0x1FFF, 16) //((uint32_t)0x1FFF<<16)
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#define SDHC_BLKATTR_BLKCNT(n) \
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MAKE_REG_SET(n, 0x1FFF, 16) //(uint32_t)(((n) & 0x1FFF)<<16) // Blocks Count
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// For Current Transfer
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#define SDHC_XFERTYP_CMDINX(n) \
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MAKE_REG_SET(n, 0x3F, 24) //(uint32_t)(((n) & 0x3F)<<24)// Command Index
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#define SDHC_XFERTYP_CMDTYP(n) \
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MAKE_REG_SET(n, 0x3, 22) //(uint32_t)(((n) & 0x3)<<22) // Command Type
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#define SDHC_XFERTYP_DPSEL \
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MAKE_REG_MASK(0x1, 21) //((uint32_t)0x00200000) // Data Present Select
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#define SDHC_XFERTYP_CICEN \
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MAKE_REG_MASK(0x1, \
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20) //((uint32_t)0x00100000) // Command Index Check Enable
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#define SDHC_XFERTYP_CCCEN \
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MAKE_REG_MASK(0x1, \
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19) //((uint32_t)0x00080000) // Command CRC Check Enable
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#define SDHC_XFERTYP_RSPTYP(n) \
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MAKE_REG_SET(n, 0x3, \
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16) //(uint32_t)(((n) & 0x3)<<16) // Response Type Select
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#define SDHC_XFERTYP_MSBSEL \
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MAKE_REG_MASK(0x1, 5) //((uint32_t)0x00000020) // Multi/Single Block Select
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#define SDHC_XFERTYP_DTDSEL \
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MAKE_REG_MASK( \
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0x1, 4) //((uint32_t)0x00000010) // Data Transfer Direction Select
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#define SDHC_XFERTYP_AC12EN \
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MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Auto CMD12 Enable
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#define SDHC_XFERTYP_BCEN \
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MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Block Count Enable
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#define SDHC_XFERTYP_DMAEN \
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MAKE_REG_MASK(0x3, 0) //((uint32_t)0x00000001) // DMA Enable
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#define SDHC_PRSSTAT_DLSL_MASK \
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MAKE_REG_MASK(0xFF, 24) //((uint32_t)0xFF000000) // DAT Line Signal Level
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#define SDHC_PRSSTAT_CLSL \
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MAKE_REG_MASK(0x1, 23) //((uint32_t)0x00800000) // CMD Line Signal Level
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#define SDHC_PRSSTAT_WPSPL MAKE_REG_MASK(0x1, 19) //
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#define SDHC_PRSSTAT_CDPL MAKE_REG_MASK(0x1, 18) //
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#define SDHC_PRSSTAT_CINS \
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MAKE_REG_MASK(0x1, 16) //((uint32_t)0x00010000) // Card Inserted
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#define SDHC_PRSSTAT_TSCD MAKE_REG_MASK(0x1, 15)
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#define SDHC_PRSSTAT_RTR MAKE_REG_MASK(0x1, 12)
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#define SDHC_PRSSTAT_BREN \
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MAKE_REG_MASK(0x1, 11) //((uint32_t)0x00000800) // Buffer Read Enable
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#define SDHC_PRSSTAT_BWEN \
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MAKE_REG_MASK(0x1, 10) //((uint32_t)0x00000400) // Buffer Write Enable
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#define SDHC_PRSSTAT_RTA \
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MAKE_REG_MASK(0x1, 9) //((uint32_t)0x00000200) // Read Transfer Active
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#define SDHC_PRSSTAT_WTA \
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MAKE_REG_MASK(0x1, 8) //((uint32_t)0x00000100) // Write Transfer Active
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#define SDHC_PRSSTAT_SDOFF \
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MAKE_REG_MASK( \
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0x1, 7) //((uint32_t)0x00000080) // SD Clock Gated Off Internally
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#define SDHC_PRSSTAT_PEROFF \
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MAKE_REG_MASK( \
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0x1, 6) //((uint32_t)0x00000040) // SDHC clock Gated Off Internally
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#define SDHC_PRSSTAT_HCKOFF \
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MAKE_REG_MASK( \
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0x1, 5) //((uint32_t)0x00000020) // System Clock Gated Off Internally
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#define SDHC_PRSSTAT_IPGOFF \
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MAKE_REG_MASK( \
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0x1, 4) //((uint32_t)0x00000010) // Bus Clock Gated Off Internally
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#define SDHC_PRSSTAT_SDSTB \
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MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // SD Clock Stable
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#define SDHC_PRSSTAT_DLA \
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MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Data Line Active
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#define SDHC_PRSSTAT_CDIHB \
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MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Command Inhibit (DAT)
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#define SDHC_PRSSTAT_CIHB \
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MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Command Inhibit (CMD)
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#define SDHC_PROTCT_NONEXACT_BLKRD MAKE_REG_MASK(0x1, 30) //
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#define SDHC_PROTCT_BURST_LENEN(n) MAKE_REG_SET(n, 0x7, 12) //
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#define SDHC_PROCTL_WECRM \
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MAKE_REG_MASK(0x1, 26) //((uint32_t)0x04000000) // Wakeup Event Enable On
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// SD Card Removal
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#define SDHC_PROCTL_WECINS \
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MAKE_REG_MASK(0x1, 25) //((uint32_t)0x02000000) // Wakeup Event Enable On
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// SD Card Insertion
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#define SDHC_PROCTL_WECINT \
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MAKE_REG_MASK(0x1, 24) //((uint32_t)0x01000000) // Wakeup Event Enable On
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// Card Interrupt
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#define SDHC_PROCTL_RD_DONE_NOBLK MAKE_REG_MASK(0x1, 20) //
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#define SDHC_PROCTL_IABG \
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MAKE_REG_MASK(0x1, 19) //((uint32_t)0x00080000) // Interrupt At Block Gap
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#define SDHC_PROCTL_RWCTL \
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MAKE_REG_MASK(0x1, 18) //((uint32_t)0x00040000) // Read Wait Control
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#define SDHC_PROCTL_CREQ \
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MAKE_REG_MASK(0x1, 17) //((uint32_t)0x00020000) // Continue Request
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#define SDHC_PROCTL_SABGREQ \
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MAKE_REG_MASK(0x1, \
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16) //((uint32_t)0x00010000) // Stop At Block Gap Request
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#define SDHC_PROCTL_DMAS(n) \
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MAKE_REG_SET(n, 0x3, 8) //(uint32_t)(((n) & 0x3)<<8) // DMA Select
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#define SDHC_PROCTL_CDSS \
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MAKE_REG_MASK(0x1, \
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7) //((uint32_t)0x00000080) // Card Detect Signal Selection
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#define SDHC_PROCTL_CDTL \
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MAKE_REG_MASK(0x1, 6) //((uint32_t)0x00000040) // Card Detect Test Level
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#define SDHC_PROCTL_EMODE(n) \
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MAKE_REG_SET(n, 0x3, 4) //(uint32_t)(((n) & 0x3)<<4) // Endian Mode
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#define SDHC_PROCTL_EMODE_MASK \
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MAKE_REG_MASK(0x3, 4) //(uint32_t)((0x3)<<4) // Endian Mode
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#define SDHC_PROCTL_D3CD \
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MAKE_REG_MASK(0x1, \
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3) //((uint32_t)0x00000008) // DAT3 As Card Detection Pin
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#define SDHC_PROCTL_DTW(n) \
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MAKE_REG_SET(n, 0x3, 1) //(uint32_t)(((n) & 0x3)<<1) // Data Transfer Width,
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// 0=1bit, 1=4bit, 2=8bit
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#define SDHC_PROCTL_DTW_MASK MAKE_REG_MASK(0x3, 1) //((uint32_t)0x00000006)
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#define SDHC_PROCTL_LCTL \
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MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // LED Control
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#define SDHC_SYSCTL_RSTT MAKE_REG_MASK(0x1, 28) //
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#define SDHC_SYSCTL_INITA \
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MAKE_REG_MASK(0x1, 27) //((uint32_t)0x08000000) // Initialization Active
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#define SDHC_SYSCTL_RSTD \
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MAKE_REG_MASK( \
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0x1, 26) //((uint32_t)0x04000000) // Software Reset For DAT Line
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#define SDHC_SYSCTL_RSTC \
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MAKE_REG_MASK( \
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0x1, 25) //((uint32_t)0x02000000) // Software Reset For CMD Line
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#define SDHC_SYSCTL_RSTA \
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MAKE_REG_MASK(0x1, 24) //((uint32_t)0x01000000) // Software Reset For ALL
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#define SDHC_SYSCTL_DTOCV(n) \
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MAKE_REG_SET( \
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n, 0xF, \
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16) //(uint32_t)(((n) & 0xF)<<16) // Data Timeout Counter Value
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#define SDHC_SYSCTL_DTOCV_MASK MAKE_REG_MASK(0xF, 16) //((uint32_t)0x000F0000)
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#define SDHC_SYSCTL_SDCLKFS(n) \
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MAKE_REG_SET(n, 0xFF, \
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8) //(uint32_t)(((n) & 0xFF)<<8) // SDCLK Frequency Select
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#define SDHC_SYSCTL_SDCLKFS_MASK \
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MAKE_REG_MASK(0xFF, 8) //((uint32_t)0x0000FF00)
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#define SDHC_SYSCTL_DVS(n) \
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MAKE_REG_SET(n, 0xF, 4) //(uint32_t)(((n) & 0xF)<<4) // Divisor
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#define SDHC_SYSCTL_DVS_MASK MAKE_REG_MASK(0xF, 4) //((uint32_t)0x000000F0)
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#define SDHC_SYSCTL_SDCLKEN ((uint32_t)0x00000008) // SD Clock Enable
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#define SDHC_SYSCTL_PEREN ((uint32_t)0x00000004) // Peripheral Clock Enable
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#define SDHC_SYSCTL_HCKEN ((uint32_t)0x00000002) // System Clock Enable
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#define SDHC_SYSCTL_IPGEN ((uint32_t)0x00000001) // IPG Clock Enable
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#define SDHC_IRQSTAT_DMAE \
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MAKE_REG_MASK(0x1, 28) //((uint32_t)0x10000000) // DMA Error
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#define SDHC_IRQSTAT_TNE MAKE_REG_MASK(0x1, 26) //
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#define SDHC_IRQSTAT_AC12E \
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MAKE_REG_MASK(0x1, 24) //((uint32_t)0x01000000) // Auto CMD12 Error
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#define SDHC_IRQSTAT_DEBE \
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MAKE_REG_MASK(0x1, 22) //((uint32_t)0x00400000) // Data End Bit Error
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#define SDHC_IRQSTAT_DCE \
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MAKE_REG_MASK(0x1, 21) //((uint32_t)0x00200000) // Data CRC Error
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#define SDHC_IRQSTAT_DTOE \
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MAKE_REG_MASK(0x1, 20) //((uint32_t)0x00100000) // Data Timeout Error
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#define SDHC_IRQSTAT_CIE \
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MAKE_REG_MASK(0x1, 19) //((uint32_t)0x00080000) // Command Index Error
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#define SDHC_IRQSTAT_CEBE \
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MAKE_REG_MASK(0x1, 18) //((uint32_t)0x00040000) // Command End Bit Error
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#define SDHC_IRQSTAT_CCE \
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MAKE_REG_MASK(0x1, 17) //((uint32_t)0x00020000) // Command CRC Error
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#define SDHC_IRQSTAT_CTOE \
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MAKE_REG_MASK(0x1, 16) //((uint32_t)0x00010000) // Command Timeout Error
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#define SDHC_IRQSTAT_TP MAKE_REG_MASK(0x1, 14) //
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#define SDHC_IRQSTAT_RTE MAKE_REG_MASK(0x1, 12) //
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#define SDHC_IRQSTAT_CINT \
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MAKE_REG_MASK(0x1, 8) //((uint32_t)0x00000100) // Card Interrupt
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#define SDHC_IRQSTAT_CRM \
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MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // Card Removal
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#define SDHC_IRQSTAT_CINS \
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MAKE_REG_MASK(0x1, 6) //((uint32_t)0x00000040) // Card Insertion
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#define SDHC_IRQSTAT_BRR \
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MAKE_REG_MASK(0x1, 5) //((uint32_t)0x00000020) // Buffer Read Ready
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#define SDHC_IRQSTAT_BWR \
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MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Buffer Write Ready
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#define SDHC_IRQSTAT_DINT \
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MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // DMA Interrupt
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#define SDHC_IRQSTAT_BGE \
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MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Block Gap Event
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#define SDHC_IRQSTAT_TC \
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MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Transfer Complete
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#define SDHC_IRQSTAT_CC \
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MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Command Complete
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#define SDHC_IRQSTATEN_DMAESEN \
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MAKE_REG_MASK(0x1, 28) //((uint32_t)0x10000000) // DMA Error Status Enable
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#define SDHC_IRQSTATEN_TNESEN MAKE_REG_MASK(0x1, 26) //
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#define SDHC_IRQSTATEN_AC12ESEN \
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MAKE_REG_MASK( \
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0x1, 24) //((uint32_t)0x01000000) // Auto CMD12 Error Status Enable
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#define SDHC_IRQSTATEN_DEBESEN \
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MAKE_REG_MASK( \
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0x1, \
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22) //((uint32_t)0x00400000) // Data End Bit Error Status Enable
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#define SDHC_IRQSTATEN_DCESEN \
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MAKE_REG_MASK( \
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0x1, 21) //((uint32_t)0x00200000) // Data CRC Error Status Enable
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#define SDHC_IRQSTATEN_DTOESEN \
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MAKE_REG_MASK( \
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0x1, \
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20) //((uint32_t)0x00100000) // Data Timeout Error Status Enable
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#define SDHC_IRQSTATEN_CIESEN \
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MAKE_REG_MASK( \
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0x1, \
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19) //((uint32_t)0x00080000) // Command Index Error Status Enable
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#define SDHC_IRQSTATEN_CEBESEN \
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MAKE_REG_MASK( \
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0x1, \
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18) //((uint32_t)0x00040000) // Command End Bit Error Status Enable
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#define SDHC_IRQSTATEN_CCESEN \
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MAKE_REG_MASK( \
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0x1, 17) //((uint32_t)0x00020000) // Command CRC Error Status Enable
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#define SDHC_IRQSTATEN_CTOESEN \
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MAKE_REG_MASK( \
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0x1, \
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16) //((uint32_t)0x00010000) // Command Timeout Error Status Enable
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#define SDHC_IRQSTATEN_TPSEN MAKE_REG_MASK(0x1, 14) //
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#define SDHC_IRQSTATEN_RTESEN MAKE_REG_MASK(0x1, 12) //
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#define SDHC_IRQSTATEN_CINTSEN \
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MAKE_REG_MASK(0x1, \
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8) //((uint32_t)0x00000100) // Card Interrupt Status Enable
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#define SDHC_IRQSTATEN_CRMSEN \
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MAKE_REG_MASK(0x1, \
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7) //((uint32_t)0x00000080) // Card Removal Status Enable
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#define SDHC_IRQSTATEN_CINSEN \
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MAKE_REG_MASK(0x1, \
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6) //((uint32_t)0x00000040) // Card Insertion Status Enable
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#define SDHC_IRQSTATEN_BRRSEN \
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MAKE_REG_MASK( \
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0x1, 5) //((uint32_t)0x00000020) // Buffer Read Ready Status Enable
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#define SDHC_IRQSTATEN_BWRSEN \
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MAKE_REG_MASK( \
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0x1, 4) //((uint32_t)0x00000010) // Buffer Write Ready Status Enable
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#define SDHC_IRQSTATEN_DINTSEN \
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MAKE_REG_MASK(0x1, \
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3) //((uint32_t)0x00000008) // DMA Interrupt Status Enable
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#define SDHC_IRQSTATEN_BGESEN \
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MAKE_REG_MASK( \
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0x1, 2) //((uint32_t)0x00000004) // Block Gap Event Status Enable
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#define SDHC_IRQSTATEN_TCSEN \
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MAKE_REG_MASK( \
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0x1, 1) //((uint32_t)0x00000002) // Transfer Complete Status Enable
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#define SDHC_IRQSTATEN_CCSEN \
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MAKE_REG_MASK( \
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0x1, 0) //((uint32_t)0x00000001) // Command Complete Status Enable
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#define SDHC_IRQSIGEN_DMAEIEN \
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MAKE_REG_MASK(0x1, \
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28) //((uint32_t)0x10000000) // DMA Error Interrupt Enable
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#define SDHC_IRQSIGEN_TNEIEN MAKE_REG_MASK(0x1, 26) //
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#define SDHC_IRQSIGEN_AC12EIEN \
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MAKE_REG_MASK( \
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0x1, \
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24) //((uint32_t)0x01000000) // Auto CMD12 Error Interrupt Enable
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#define SDHC_IRQSIGEN_DEBEIEN \
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MAKE_REG_MASK( \
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0x1, \
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22) //((uint32_t)0x00400000) // Data End Bit Error Interrupt Enable
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#define SDHC_IRQSIGEN_DCEIEN \
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MAKE_REG_MASK( \
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0x1, 21) //((uint32_t)0x00200000) // Data CRC Error Interrupt Enable
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#define SDHC_IRQSIGEN_DTOEIEN \
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MAKE_REG_MASK( \
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0x1, \
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20) //((uint32_t)0x00100000) // Data Timeout Error Interrupt Enable
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#define SDHC_IRQSIGEN_CIEIEN \
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MAKE_REG_MASK( \
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0x1, \
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19) //((uint32_t)0x00080000) // Command Index Error Interrupt Enable
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#define SDHC_IRQSIGEN_CEBEIEN \
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MAKE_REG_MASK(0x1, 18) //((uint32_t)0x00040000) // Command End Bit Error
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// Interrupt Enable
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#define SDHC_IRQSIGEN_CCEIEN \
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MAKE_REG_MASK( \
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0x1, \
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17) //((uint32_t)0x00020000) // Command CRC Error Interrupt Enable
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#define SDHC_IRQSIGEN_CTOEIEN \
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MAKE_REG_MASK(0x1, 16) //((uint32_t)0x00010000) // Command Timeout Error
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// Interrupt Enable
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#define SDHC_IRQSIGEN_TPIEN MAKE_REG_MASK(0x1, 14) //
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#define SDHC_IRQSIGEN_RTEIEN MAKE_REG_MASK(0x1, 12) //
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#define SDHC_IRQSIGEN_CINTIEN \
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MAKE_REG_MASK( \
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0x1, 8) //((uint32_t)0x00000100) // Card Interrupt Interrupt Enable
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#define SDHC_IRQSIGEN_CRMIEN \
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MAKE_REG_MASK( \
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0x1, 7) //((uint32_t)0x00000080) // Card Removal Interrupt Enable
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#define SDHC_IRQSIGEN_CINSIEN \
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MAKE_REG_MASK( \
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0x1, 6) //((uint32_t)0x00000040) // Card Insertion Interrupt Enable
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#define SDHC_IRQSIGEN_BRRIEN \
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MAKE_REG_MASK( \
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0x1, \
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5) //((uint32_t)0x00000020) // Buffer Read Ready Interrupt Enable
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#define SDHC_IRQSIGEN_BWRIEN \
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MAKE_REG_MASK( \
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0x1, \
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4) //((uint32_t)0x00000010) // Buffer Write Ready Interrupt Enable
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#define SDHC_IRQSIGEN_DINTIEN \
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MAKE_REG_MASK( \
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0x1, 3) //((uint32_t)0x00000008) // DMA Interrupt Interrupt Enable
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#define SDHC_IRQSIGEN_BGEIEN \
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MAKE_REG_MASK( \
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0x1, 2) //((uint32_t)0x00000004) // Block Gap Event Interrupt Enable
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#define SDHC_IRQSIGEN_TCIEN \
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MAKE_REG_MASK( \
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0x1, \
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1) //((uint32_t)0x00000002) // Transfer Complete Interrupt Enable
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#define SDHC_IRQSIGEN_CCIEN \
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MAKE_REG_MASK( \
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0x1, \
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0) //((uint32_t)0x00000001) // Command Complete Interrupt Enable
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#define SDHC_AC12ERR_SMPLCLK_SEL MAKE_REG_MASK(0x1, 23) //
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#define SDHC_AC12ERR_EXEC_TUNING MAKE_REG_MASK(0x1, 22) //
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#define SDHC_AC12ERR_CNIBAC12E \
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MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // Command Not Issued By
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// Auto CMD12 Error
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#define SDHC_AC12ERR_AC12IE \
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MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Auto CMD12 Index Error
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#define SDHC_AC12ERR_AC12CE \
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MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // Auto CMD12 CRC Error
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#define SDHC_AC12ERR_AC12EBE \
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MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004) // Auto CMD12 End Bit Error
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#define SDHC_AC12ERR_AC12TOE \
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MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Auto CMD12 Timeout Error
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#define SDHC_AC12ERR_AC12NE \
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MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Auto CMD12 Not Executed
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#define SDHC_HTCAPBLT_VS18 MAKE_REG_MASK(0x1, 26) //
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#define SDHC_HTCAPBLT_VS30 MAKE_REG_MASK(0x1, 25) //
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#define SDHC_HTCAPBLT_VS33 MAKE_REG_MASK(0x1, 24) //
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#define SDHC_HTCAPBLT_SRS MAKE_REG_MASK(0x1, 23) //
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#define SDHC_HTCAPBLT_DMAS MAKE_REG_MASK(0x1, 22) //
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#define SDHC_HTCAPBLT_HSS MAKE_REG_MASK(0x1, 21) //
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#define SDHC_HTCAPBLT_ADMAS MAKE_REG_MASK(0x1, 20) //
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#define SDHC_HTCAPBLT_MBL_VAL MAKE_REG_GET((USDHC1_HOST_CTRL_CAP), 0x7, 16) //
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#define SDHC_HTCAPBLT_RETUN_MODE \
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MAKE_REG_GET((USDHC1_HOST_CTRL_CAP), 0x3, 14) //
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#define SDHC_HTCAPBLT_TUNE_SDR50 MAKE_REG_MASK(0x1, 13) //
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#define SDHC_HTCAPBLT_TIME_RETUN(n) MAKE_REG_SET(n, 0xF, 8) //
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#define SDHC_WML_WR_BRSTLEN_MASK MAKE_REG_MASK(0x1F, 24) //
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#define SDHC_WML_RD_BRSTLEN_MASK MAKE_REG_MASK(0x1F, 8) //
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#define SDHC_WML_WR_WML_MASK MAKE_REG_MASK(0xFF, 16) //
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#define SDHC_WML_RD_WML_MASK MAKE_REG_MASK(0xFF, 0) //
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#define SDHC_WML_WR_BRSTLEN(n) \
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MAKE_REG_SET(n, 0x1F, 24) //(uint32_t)(((n) & 0x7F)<<16) // Write Burst Len
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#define SDHC_WML_RD_BRSTLEN(n) \
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MAKE_REG_SET(n, 0x1F, 8) //(uint32_t)(((n) & 0x7F)<<0) // Read Burst Len
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#define SDHC_WML_WR_WML(n) \
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MAKE_REG_SET(n, 0xFF, \
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16) //(uint32_t)(((n) & 0x7F)<<16) // Write Watermark Level
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#define SDHC_WML_RD_WML(n) \
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MAKE_REG_SET(n, 0xFF, \
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0) //(uint32_t)(((n) & 0x7F)<<0) // Read Watermark Level
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#define SDHC_WML_WRWML(n) \
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MAKE_REG_SET(n, 0xFF, \
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16) //(uint32_t)(((n) & 0x7F)<<16) // Write Watermark Level
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#define SDHC_WML_RDWML(n) \
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MAKE_REG_SET(n, 0xFF, \
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0) //(uint32_t)(((n) & 0x7F)<<0) // Read Watermark Level
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// Teensy 4.0 only
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#define SDHC_MIX_CTRL_DMAEN MAKE_REG_MASK(0x1, 0) //
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#define SDHC_MIX_CTRL_BCEN MAKE_REG_MASK(0x1, 1) //
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#define SDHC_MIX_CTRL_AC12EN MAKE_REG_MASK(0x1, 2) //
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#define SDHC_MIX_CTRL_DDR_EN MAKE_REG_MASK(0x1, 3) //
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#define SDHC_MIX_CTRL_DTDSEL MAKE_REG_MASK(0x1, 4) //
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#define SDHC_MIX_CTRL_MSBSEL MAKE_REG_MASK(0x1, 5) //
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#define SDHC_MIX_CTRL_NIBBLE_POS MAKE_REG_MASK(0x1, 6) //
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#define SDHC_MIX_CTRL_AC23EN MAKE_REG_MASK(0x1, 7) //
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#define SDHC_FEVT_CINT \
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MAKE_REG_MASK(0x1, \
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31) //((uint32_t)0x80000000) // Force Event Card Interrupt
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#define SDHC_FEVT_DMAE \
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MAKE_REG_MASK(0x1, 28) //((uint32_t)0x10000000) // Force Event DMA Error
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#define SDHC_FEVT_AC12E \
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MAKE_REG_MASK( \
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0x1, 24) //((uint32_t)0x01000000) // Force Event Auto CMD12 Error
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#define SDHC_FEVT_DEBE \
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MAKE_REG_MASK( \
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0x1, 22) //((uint32_t)0x00400000) // Force Event Data End Bit Error
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#define SDHC_FEVT_DCE \
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MAKE_REG_MASK(0x1, \
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21) //((uint32_t)0x00200000) // Force Event Data CRC Error
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#define SDHC_FEVT_DTOE \
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MAKE_REG_MASK( \
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0x1, 20) //((uint32_t)0x00100000) // Force Event Data Timeout Error
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#define SDHC_FEVT_CIE \
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MAKE_REG_MASK( \
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0x1, 19) //((uint32_t)0x00080000) // Force Event Command Index Error
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#define SDHC_FEVT_CEBE \
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MAKE_REG_MASK( \
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0x1, \
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18) //((uint32_t)0x00040000) // Force Event Command End Bit Error
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#define SDHC_FEVT_CCE \
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MAKE_REG_MASK( \
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0x1, 17) //((uint32_t)0x00020000) // Force Event Command CRC Error
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#define SDHC_FEVT_CTOE \
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MAKE_REG_MASK( \
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0x1, \
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16) //((uint32_t)0x00010000) // Force Event Command Timeout Error
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#define SDHC_FEVT_CNIBAC12E \
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MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // Force Event Command Not
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// Executed By Auto Command 12 Error
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#define SDHC_FEVT_AC12IE \
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MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Force Event Auto Command
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// 12 Index Error
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#define SDHC_FEVT_AC12EBE \
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MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008) // Force Event Auto Command
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// 12 End Bit Error
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#define SDHC_FEVT_AC12CE \
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MAKE_REG_MASK( \
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0x1, \
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2) //((uint32_t)0x00000004) // Force Event Auto Command 12 CRC Error
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#define SDHC_FEVT_AC12TOE \
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MAKE_REG_MASK(0x1, 1) //((uint32_t)0x00000002) // Force Event Auto Command
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// 12 Time Out Error
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#define SDHC_FEVT_AC12NE \
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MAKE_REG_MASK(0x1, 0) //((uint32_t)0x00000001) // Force Event Auto Command
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// 12 Not Executed
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#define SDHC_ADMAES_ADMADCE MAKE_REG_MASK(0x1, 3) //((uint32_t)0x00000008)
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#define SDHC_ADMAES_ADMALME MAKE_REG_MASK(0x1, 2) //((uint32_t)0x00000004)
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#define SDHC_ADMAES_ADMAES_MASK MAKE_REG_MASK(0x3, 0) //((uint32_t)0x00000003)
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#define SDHC_MMCBOOT_BOOTBLKCNT(n) \
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MAKE_REG_MASK(0xFF, 16) //(uint32_t)(((n) & 0xFFF)<<16) // stop at block gap
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// value of automatic mode
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#define SDHC_MMCBOOT_AUTOSABGEN \
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MAKE_REG_MASK(0x1, 7) //((uint32_t)0x00000080) // enable auto stop at
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// block gap function
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#define SDHC_MMCBOOT_BOOTEN \
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MAKE_REG_MASK(0x1, 6) //((uint32_t)0x00000040) // Boot Mode Enable
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#define SDHC_MMCBOOT_BOOTMODE \
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MAKE_REG_MASK(0x1, 5) //((uint32_t)0x00000020) // Boot Mode Select
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#define SDHC_MMCBOOT_BOOTACK \
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MAKE_REG_MASK(0x1, 4) //((uint32_t)0x00000010) // Boot Ack Mode Select
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#define SDHC_MMCBOOT_DTOCVACK(n) \
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MAKE_REG_MASK( \
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0xF, \
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0) //(uint32_t)(((n) & 0xF)<<0) // Boot ACK Time Out Counter Value
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// #define SDHC_HOSTVER (*(volatile uint32_t*)0x400B10FC) // Host Controller
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// Version
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#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK 0x3f
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#define CCM_ANALOG_PFD_528_PFD0_FRAC(n) \
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((n) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3f << 8)
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#define CCM_ANALOG_PFD_528_PFD1_FRAC(n) \
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(((n) << 8) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3f << 16)
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#define CCM_ANALOG_PFD_528_PFD2_FRAC(n) \
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(((n) << 16) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
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#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK ((0x3f<<24)
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#define CCM_ANALOG_PFD_528_PFD3_FRAC(n) \
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(((n) << 24) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
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#define SDHC_DSADDR (USDHC1_DS_ADDR) // DMA System Address register
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#define SDHC_BLKATTR (USDHC1_BLK_ATT) // Block Attributes register
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#define SDHC_CMDARG (USDHC1_CMD_ARG) // Command Argument register
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#define SDHC_XFERTYP (USDHC1_CMD_XFR_TYP) // Transfer Type register
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#define SDHC_CMDRSP0 (USDHC1_CMD_RSP0) // Command Response 0
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#define SDHC_CMDRSP1 (USDHC1_CMD_RSP1) // Command Response 1
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#define SDHC_CMDRSP2 (USDHC1_CMD_RSP2) // Command Response 2
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#define SDHC_CMDRSP3 (USDHC1_CMD_RSP3) // Command Response 3
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#define SDHC_DATPORT (USDHC1_DATA_BUFF_ACC_PORT) // Buffer Data Port register
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#define SDHC_PRSSTAT (USDHC1_PRES_STATE) // Present State register
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#define SDHC_PROCTL (USDHC1_PROT_CTRL) // Protocol Control register
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#define SDHC_SYSCTL (USDHC1_SYS_CTRL) // System Control register
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#define SDHC_IRQSTAT (USDHC1_INT_STATUS) // Interrupt Status register
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#define SDHC_IRQSTATEN \
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(USDHC1_INT_STATUS_EN) // Interrupt Status Enable register
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#define SDHC_IRQSIGEN \
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(USDHC1_INT_SIGNAL_EN) // Interrupt Signal Enable register
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#define SDHC_AC12ERR \
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(USDHC1_AUTOCMD12_ERR_STATUS) // Auto CMD12 Error Status Register
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#define SDHC_HTCAPBLT (USDHC1_HOST_CTRL_CAP) // Host Controller Capabilities
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#define SDHC_WML (USDHC1_WTMK_LVL) // Watermark Level Register
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#define SDHC_MIX_CTRL (USDHC1_MIX_CTRL) // Mixer Control
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#define SDHC_FEVT (USDHC1_FORCE_EVENT) // Force Event register
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#define SDHC_ADMAES (USDHC1_ADMA_ERR_STATUS) // ADMA Error Status register
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#define SDHC_ADSADDR (USDHC1_ADMA_SYS_ADDR) // ADMA System Addressregister
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#define SDHC_VENDOR (USDHC1_VEND_SPEC) // Vendor Specific register
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#define SDHC_MMCBOOT (USDHC1_MMC_BOOT) // MMC Boot register
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#define SDHC_VENDOR2 (USDHC2_VEND_SPEC2) // Vendor Specific2 register
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//
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#define IRQ_SDHC IRQ_SDHC1
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#define SDHC_MAX_DVS (0xF + 1U)
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#define SDHC_MAX_CLKFS (0xFF + 1U)
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#define SDHC_PREV_DVS(x) ((x) -= 1U)
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#define SDHC_PREV_CLKFS(x, y) ((x) >>= (y))
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#define CCM_CSCDR1_USDHC1_CLK_PODF_MASK (0x7 << 11)
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#define CCM_CSCDR1_USDHC1_CLK_PODF(n) (((n) & 0x7) << 11)
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#define IOMUXC_SW_PAD_CTL_PAD_SRE ((0x1 <) < 0)
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#define IOMUXC_SW_PAD_CTL_PAD_PKE ((0x1) << 12)
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#define IOMUXC_SW_PAD_CTL_PAD_PUE ((0x1) << 13)
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#define IOMUXC_SW_PAD_CTL_PAD_HYS ((0x1) << 16)
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#define IOMUXC_SW_PAD_CTL_PAD_SPEED(n) (((n) & 0x3) << 6)
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#define IOMUXC_SW_PAD_CTL_PAD_PUS(n) (((n) & 0x3) << 14)
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#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK ((0x3) << 14)
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#define IOMUXC_SW_PAD_CTL_PAD_DSE(n) (((n) & 0x7) << 3)
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#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK ((0x7) << 3)
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#endif // defined(__IMXRT1062__)
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