Add an option to force IDF's default UART clock source (#11191)
* Add an option to force IDF's default UART clock source * feat(uart): adds function to set clock source * feat(uart): add uart clock source selection method * feat(uart): add uart hall function to set the uart clock source * feat(uart): add function to set the uart clock source * feat(uart): set clock source as necessary * fix(uart): missing class qualifier declaration * fix(uart): fixing a typo and non LP UART SoC clk src setting * fix(uart): variable name, typo error * fix(uart): retores previous identation reducing diff load * feat(uart): apply CONFIG_ARDUINO_SERIAL_FORCE_IDF_DEFAULT_CLOCK_SOURCE to LP UART * feat(uart): adds option for UART_CLK_SRC_DEFAULT * feat(uart): adds option for setting default uart clock source from IDF * feat(uart): documents UART_CLK_SRC_DEFAULT as option in header file * feat(uart): documents using the IDF default uart clock source * fix(uart): type missmatch may cause error * fix(uart): type missmatch may cause error, test for -1 * feat(uart): considering both HP and LP default uart clock source * feat(uart): improve the defined value for UART_CLK_SRC_DEFAULT * fix(uart): using uart_sclk_t as hal level parameter * feat(uart): apply default LP uart clock source * fix(uart): considers that it may set the LP UART as well * feat(uart): using UART SCLK enum for uart clock source values * fix(uart): using UART_CLK_SRC_RTC now * fix(uart): documentation using UART_CLK_SRC_RTC now * fix(uart): fix old commentary that is not correct anymore * fix(uart): wrong identation in code line * fix(uart): using uart number as argument instead * fix(uart): using uart number as argument in setClockSource() * fix(uart): using uart number as parameter in uartSetClockSource() * feat(uart): update Kconfig.projbuild to reflect functionality * feat(uart): removing Kconfig.projbuild option to force default clk src * feat(uart): removes kconfig option to force uart default clk src * fix(uart): replacing #if #endif by #if #elif #endif for the same enum * ci(pre-commit): Apply automatic fixes --------- Co-authored-by: Sugar Glider <rodrigo.garcia@espressif.com> Co-authored-by: pre-commit-ci-lite[bot] <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com>
This commit is contained in:
Gonzalo Brusco
GitHub
parent
b333bf2697
commit
0cc8eab836
4 changed files with 184 additions and 45 deletions
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@ -607,6 +607,24 @@ bool HardwareSerial::setMode(SerialMode mode) {
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return uartSetMode(_uart, mode);
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}
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// Sets the UART Clock Source based on the compatible SoC options
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// This method must be called before starting UART using begin(), otherwise it won't have any effect.
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// Clock Source Options are:
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// UART_CLK_SRC_DEFAULT :: any SoC - it will set whatever IDF defines as the default UART Clock Source
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// UART_CLK_SRC_APB :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
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// UART_CLK_SRC_PLL :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
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// UART_CLK_SRC_XTAL :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
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// UART_CLK_SRC_RTC :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
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// UART_CLK_SRC_REF_TICK :: ESP32 and ESP32-S2
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// Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
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// Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
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bool HardwareSerial::setClockSource(SerialClkSrc clkSrc) {
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if (_uart) {
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log_e("No Clock Source change was done. This function must be called before beginning UART%d.", _uart_nr);
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return false;
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}
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return uartSetClockSource(_uart_nr, (uart_sclk_t)clkSrc);
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}
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// minimum total RX Buffer size is the UART FIFO space (128 bytes for most SoC) + 1. IDF imposition.
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// LP UART has FIFO of 16 bytes
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size_t HardwareSerial::setRxBufferSize(size_t new_size) {
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@ -96,6 +96,29 @@ typedef enum {
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UART_PARITY_ERROR
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} hardwareSerial_error_t;
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typedef enum {
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UART_CLK_SRC_DEFAULT = UART_SCLK_DEFAULT,
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#if SOC_UART_SUPPORT_APB_CLK
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UART_CLK_SRC_APB = UART_SCLK_APB,
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#endif
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#if SOC_UART_SUPPORT_PLL_F40M_CLK
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UART_CLK_SRC_PLL = UART_SCLK_PLL_F40M,
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#elif SOC_UART_SUPPORT_PLL_F80M_CLK
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UART_CLK_SRC_PLL = UART_SCLK_PLL_F80M,
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#elif CONFIG_IDF_TARGET_ESP32H2
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UART_CLK_SRC_PLL = UART_SCLK_PLL_F48M,
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#endif
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#if SOC_UART_SUPPORT_XTAL_CLK
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UART_CLK_SRC_XTAL = UART_SCLK_XTAL,
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#endif
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#if SOC_UART_SUPPORT_RTC_CLK
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UART_CLK_SRC_RTC = UART_SCLK_RTC,
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#endif
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#if SOC_UART_SUPPORT_REF_TICK
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UART_CLK_SRC_REF_TICK = UART_SCLK_REF_TICK,
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#endif
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} SerialClkSrc;
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#ifndef ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
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#ifndef CONFIG_ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE
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#define ARDUINO_SERIAL_EVENT_TASK_STACK_SIZE 2048
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@ -344,6 +367,17 @@ public:
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// UART_MODE_RS485_COLLISION_DETECT = 0x03 mode: RS485 collision detection UART mode (used for test purposes)
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// UART_MODE_RS485_APP_CTRL = 0x04 mode: application control RS485 UART mode (used for test purposes)
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bool setMode(SerialMode mode);
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// Used to set the UART clock source mode. It must be set before calling begin(), otherwise it won't have any effect.
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// Not all clock source are available to every SoC. The compatible option are listed here:
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// UART_CLK_SRC_DEFAULT :: any SoC - it will set whatever IDF defines as the default UART Clock Source
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// UART_CLK_SRC_APB :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
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// UART_CLK_SRC_PLL :: ESP32-C2, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2 and ESP32-P4
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// UART_CLK_SRC_XTAL :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
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// UART_CLK_SRC_RTC :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
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// UART_CLK_SRC_REF_TICK :: ESP32 and ESP32-S2
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// Note: CLK_SRC_PLL Freq depends on the SoC - ESP32-C2 has 40MHz, ESP32-H2 has 48MHz and ESP32-C5, C6, C61 and P4 has 80MHz
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// Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only RTC_FAST or XTAL/2 as Clock Source
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bool setClockSource(SerialClkSrc clkSrc);
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size_t setRxBufferSize(size_t new_size);
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size_t setTxBufferSize(size_t new_size);
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@ -58,6 +58,7 @@ struct uart_struct_t {
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uint16_t _rx_buffer_size, _tx_buffer_size; // UART RX and TX buffer sizes
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bool _inverted; // UART inverted signal
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uint8_t _rxfifo_full_thrhd; // UART RX FIFO full threshold
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int8_t _uart_clock_source; // UART Clock Source used when it is started using uartBegin()
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};
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#if CONFIG_DISABLE_HAL_LOCKS
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@ -66,21 +67,21 @@ struct uart_struct_t {
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#define UART_MUTEX_UNLOCK()
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static uart_t _uart_bus_array[] = {
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{0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#if SOC_UART_NUM > 1
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{1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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#if SOC_UART_NUM > 2
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{2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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#if SOC_UART_NUM > 3
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{3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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#if SOC_UART_NUM > 4
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{4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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#if SOC_UART_NUM > 5
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{5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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};
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@ -95,21 +96,21 @@ static uart_t _uart_bus_array[] = {
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xSemaphoreGive(uart->lock)
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static uart_t _uart_bus_array[] = {
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{NULL, 0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{NULL, 0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#if SOC_UART_NUM > 1
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{NULL, 1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{NULL, 1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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#if SOC_UART_NUM > 2
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{NULL, 2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{NULL, 2, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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#if SOC_UART_NUM > 3
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{NULL, 3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{NULL, 3, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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#if SOC_UART_NUM > 4
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{NULL, 4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{NULL, 4, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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#if SOC_UART_NUM > 5
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{NULL, 5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
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{NULL, 5, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0, -1},
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#endif
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};
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@ -664,30 +665,40 @@ uart_t *uartBegin(
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rxfifo_full_thrhd = uart_config.rx_flow_ctrl_thresh; // makes sure that it will be set correctly in the struct
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uart_config.baud_rate = baudrate;
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#if SOC_UART_LP_NUM >= 1
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if (uart_nr >= SOC_UART_HP_NUM) { // it is a LP UART NUM
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uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT; // use default LP clock
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log_v("Setting UART%d to use LP clock", uart_nr);
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} else
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#endif
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{
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// there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
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// therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
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#if SOC_UART_SUPPORT_XTAL_CLK
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uart_config.source_clk = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4
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log_v("Setting UART%d to use XTAL clock", uart_nr);
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#elif SOC_UART_SUPPORT_REF_TICK
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if (baudrate <= REF_TICK_BAUDRATE_LIMIT) {
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uart_config.source_clk = UART_SCLK_REF_TICK; // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
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log_v("Setting UART%d to use REF_TICK clock", uart_nr);
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if (uart_nr >= SOC_UART_HP_NUM) { // it is a LP UART NUM
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if (uart->_uart_clock_source > 0) {
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uart_config.lp_source_clk = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source; // use user defined LP UART clock
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log_v("Setting UART%d to user defined LP clock source (%d) ", uart_nr, uart->_uart_clock_source);
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} else {
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uart_config.source_clk = UART_SCLK_APB; // baudrate may change with the APB Frequency!
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log_v("Setting UART%d to use APB clock", uart_nr);
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uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT; // use default LP clock
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log_v("Setting UART%d to Default LP clock source", uart_nr);
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}
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} else
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#endif // SOC_UART_LP_NUM >= 1
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{
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if (uart->_uart_clock_source >= 0) {
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uart_config.source_clk = (soc_module_clk_t)uart->_uart_clock_source; // use user defined HP UART clock
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log_v("Setting UART%d to user defined HP clock source (%d) ", uart_nr, uart->_uart_clock_source);
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} else {
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// there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
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// therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
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#if SOC_UART_SUPPORT_XTAL_CLK
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uart_config.source_clk = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4
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log_v("Setting UART%d to use XTAL clock", uart_nr);
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#elif SOC_UART_SUPPORT_REF_TICK
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if (baudrate <= REF_TICK_BAUDRATE_LIMIT) {
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uart_config.source_clk = UART_SCLK_REF_TICK; // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
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log_v("Setting UART%d to use REF_TICK clock", uart_nr);
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} else {
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uart_config.source_clk = UART_SCLK_APB; // baudrate may change with the APB Frequency!
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log_v("Setting UART%d to use APB clock", uart_nr);
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}
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#else
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// Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6
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uart_config.source_clk = UART_SCLK_DEFAULT; // baudrate may change with the APB Frequency!
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log_v("Setting UART%d to use DEFAULT clock", uart_nr);
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#endif
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// Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
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uart_config.source_clk = UART_SCLK_DEFAULT; // baudrate may change with the APB Frequency!
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log_v("Setting UART%d to use DEFAULT clock", uart_nr);
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#endif // SOC_UART_SUPPORT_XTAL_CLK
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}
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}
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UART_MUTEX_LOCK();
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@ -716,6 +727,14 @@ uart_t *uartBegin(
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uart->_tx_buffer_size = tx_buffer_size;
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uart->has_peek = false;
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uart->peek_byte = 0;
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#if SOC_UART_LP_NUM >= 1
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if (uart_nr >= SOC_UART_HP_NUM) {
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uart->_uart_clock_source = uart_config.lp_source_clk;
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} else
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#endif
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{
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uart->_uart_clock_source = uart_config.source_clk;
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}
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}
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UART_MUTEX_UNLOCK();
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@ -975,22 +994,52 @@ bool uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
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return false;
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}
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bool retCode = true;
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UART_MUTEX_LOCK();
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#if SOC_UART_SUPPORT_XTAL_CLK // ESP32-S3, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-H2 and ESP32-P4
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soc_module_clk_t newClkSrc = UART_SCLK_XTAL;
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soc_module_clk_t newClkSrc = UART_SCLK_DEFAULT;
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int8_t previousClkSrc = uart->_uart_clock_source;
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#if SOC_UART_LP_NUM >= 1
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if (uart->num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
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newClkSrc = LP_UART_SCLK_DEFAULT; // use default LP clock
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if (uart->_uart_clock_source > 0) {
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newClkSrc = (soc_periph_lp_uart_clk_src_t)uart->_uart_clock_source; // use user defined LP UART clock
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log_v("Setting UART%d to user defined LP clock source (%d) ", uart->num, newClkSrc);
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} else {
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newClkSrc = LP_UART_SCLK_DEFAULT; // use default LP clock
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log_v("Setting UART%d to Default LP clock source", uart->num);
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}
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} else
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#endif // SOC_UART_LP_NUM >= 1
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{
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if (uart->_uart_clock_source >= 0) {
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newClkSrc = (soc_module_clk_t)uart->_uart_clock_source; // use user defined HP UART clock
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log_v("Setting UART%d to use HP clock source (%d) ", uart->num, newClkSrc);
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} else {
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// there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
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// therefore, uart clock source will set to XTAL for all SoC that support it. This fix solves the C6|H2 issue.
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#if SOC_UART_SUPPORT_XTAL_CLK
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newClkSrc = UART_SCLK_XTAL; // valid for C2, S3, C3, C6, H2 and P4
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log_v("Setting UART%d to use XTAL clock", uart->num);
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#elif SOC_UART_SUPPORT_REF_TICK
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if (baud_rate <= REF_TICK_BAUDRATE_LIMIT) {
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newClkSrc = UART_SCLK_REF_TICK; // valid for ESP32, S2 - MAX supported baud rate is 250 Kbps
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log_v("Setting UART%d to use REF_TICK clock", uart->num);
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} else {
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newClkSrc = UART_SCLK_APB; // baudrate may change with the APB Frequency!
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log_v("Setting UART%d to use APB clock", uart->num);
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}
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#else
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// Default CLK Source: CLK_APB for ESP32|S2|S3|C3 -- CLK_PLL_F40M for C2 -- CLK_PLL_F48M for H2 -- CLK_PLL_F80M for C6|P4
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// using newClkSrc = UART_SCLK_DEFAULT as defined in the variable declaration
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log_v("Setting UART%d to use DEFAULT clock", uart->num);
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#endif // SOC_UART_SUPPORT_XTAL_CLK
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}
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}
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#endif
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// ESP32-P4 demands an atomic operation for setting the clock source
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HP_UART_SRC_CLK_ATOMIC() {
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uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
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UART_MUTEX_LOCK();
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// if necessary, set the correct UART Clock Source before changing the baudrate
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if (previousClkSrc < 0 || previousClkSrc != newClkSrc) {
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HP_UART_SRC_CLK_ATOMIC() {
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uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
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}
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uart->_uart_clock_source = newClkSrc;
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}
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#else // ESP32, ESP32-S2
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soc_module_clk_t newClkSrc = baud_rate <= REF_TICK_BAUDRATE_LIMIT ? SOC_MOD_CLK_REF_TICK : SOC_MOD_CLK_APB;
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uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
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#endif
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if (uart_set_baudrate(uart->num, baud_rate) == ESP_OK) {
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||||
log_v("Setting UART%d baud rate to %ld.", uart->num, baud_rate);
|
||||
uart->_baudrate = baud_rate;
|
||||
|
|
@ -1084,6 +1133,31 @@ bool uartSetMode(uart_t *uart, uart_mode_t mode) {
|
|||
return retCode;
|
||||
}
|
||||
|
||||
// this function will set the uart clock source
|
||||
// it must be called before uartBegin(), otherwise it won't change any thing.
|
||||
bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc) {
|
||||
if (uartNum >= SOC_UART_NUM) {
|
||||
log_e("UART%d is invalid. This device has %d UARTs, from 0 to %d.", uartNum, SOC_UART_NUM, SOC_UART_NUM - 1);
|
||||
return false;
|
||||
}
|
||||
uart_t *uart = &_uart_bus_array[uartNum];
|
||||
#if SOC_UART_LP_NUM >= 1
|
||||
if (uart->num >= SOC_UART_HP_NUM) {
|
||||
switch (clkSrc) {
|
||||
case UART_SCLK_XTAL: uart->_uart_clock_source = LP_UART_SCLK_XTAL_D2; break;
|
||||
case UART_SCLK_RTC: uart->_uart_clock_source = LP_UART_SCLK_LP_FAST; break;
|
||||
case UART_SCLK_DEFAULT:
|
||||
default: uart->_uart_clock_source = LP_UART_SCLK_DEFAULT;
|
||||
}
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
uart->_uart_clock_source = clkSrc;
|
||||
}
|
||||
//log_i("UART%d set clock source to %d", uart->num, uart->_uart_clock_source);
|
||||
return true;
|
||||
}
|
||||
|
||||
void uartSetDebug(uart_t *uart) {
|
||||
// LP UART is not supported for debug
|
||||
if (uart == NULL || uart->num >= SOC_UART_HP_NUM) {
|
||||
|
|
|
|||
|
|
@ -97,6 +97,19 @@ bool uartSetHwFlowCtrlMode(uart_t *uart, uart_hw_flowcontrol_t mode, uint8_t thr
|
|||
// UART_MODE_RS485_APP_CTRL = 0x04 mode: application control RS485 UART mode (used for test purposes)
|
||||
bool uartSetMode(uart_t *uart, uart_mode_t mode);
|
||||
|
||||
// Used to set the UART clock source mode. It must be set before calling uartBegin(), otherwise it won't have any effect.
|
||||
// Not all clock source are available to every SoC. The compatible option are listed here:
|
||||
// UART_SCLK_DEFAULT :: any SoC - it will set whatever IDF defines as the default UART Clock Source
|
||||
// UART_SCLK_APB :: ESP32, ESP32-S2, ESP32-C3 and ESP32-S3
|
||||
// UART_SCLK_PLL_F80M :: ESP32-C5, ESP32-C6, ESP32-C61 and ESP32-P4
|
||||
// UART_SCLK_PLL_F40M :: ESP32-C2
|
||||
// UART_SCLK_PLL_F48M :: ESP32-H2
|
||||
// UART_SCLK_XTAL :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
|
||||
// UART_SCLK_RTC :: ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61, ESP32-H2, ESP32-S3 and ESP32-P4
|
||||
// UART_SCLK_REF_TICK :: ESP32 and ESP32-S2
|
||||
// Note: ESP32-C6, C61, ESP32-P4 and ESP32-C5 have LP UART that will use only LP_UART_SCLK_LP_FAST (RTC_FAST) or LP_UART_SCLK_XTAL_D2 (XTAL/2) as Clock Source
|
||||
bool uartSetClockSource(uint8_t uartNum, uart_sclk_t clkSrc);
|
||||
|
||||
void uartStartDetectBaudrate(uart_t *uart);
|
||||
unsigned long uartDetectBaudrate(uart_t *uart);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue