From 100ed8e89524d5228ea2fc8d5220eba775462519 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20Proch=C3=A1zka?= <90197375+P-R-O-C-H-Y@users.noreply.github.com> Date: Wed, 22 Jan 2025 12:56:41 +0100 Subject: [PATCH] fix(c5): Update debug log in setCpuFrequencyMhz --- cores/esp32/esp32-hal-cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/cores/esp32/esp32-hal-cpu.c b/cores/esp32/esp32-hal-cpu.c index 8c13a4077..30c7e3a2b 100644 --- a/cores/esp32/esp32-hal-cpu.c +++ b/cores/esp32/esp32-hal-cpu.c @@ -267,6 +267,12 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) { (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M")), conf.source_freq_mhz, conf.div, conf.freq_mhz, apb ); +#elif defined(CONFIG_IDF_TARGET_ESP32C5) + log_d( + "%s: %u / %u = %u Mhz, APB: %u Hz", + (conf.source == SOC_CPU_CLK_SRC_PLL_F240M || conf.source == SOC_CPU_CLK_SRC_PLL_F160M) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M"), + conf.source_freq_mhz, conf.div, conf.freq_mhz, apb + ); #else log_d( "%s: %u / %u = %u Mhz, APB: %u Hz", (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "17.5M"),