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Initial S3 Support

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Just so we can compile and test! Some things might/will not work. SPI and UART baud detect need to be looked at.
This commit is contained in:
me-no-dev 2022-01-21 00:43:07 +02:00
parent a61609376a
commit 6326608275
2518 changed files with 562002 additions and 56 deletions
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179
boards.txt
View file

@ -161,6 +161,185 @@ esp32c3.menu.DebugLevel.verbose.build.code_debug=5
##############################################################
esp32s3.name=ESP32S3 Dev Module
esp32s3.vid.0=0x303a
esp32s3.pid.0=0x0002
esp32s3.upload.tool=esptool_py
esp32s3.upload.maximum_size=1310720
esp32s3.upload.maximum_data_size=327680
esp32s3.upload.flags=
esp32s3.upload.extra_flags=
esp32s3.upload.use_1200bps_touch=false
esp32s3.upload.wait_for_upload_port=false
esp32s3.serial.disableDTR=false
esp32s3.serial.disableRTS=false
esp32s3.build.tarch=xtensa
esp32s3.build.bootloader_addr=0x1000
esp32s3.build.target=esp32s3
esp32s3.build.mcu=esp32s3
esp32s3.build.core=esp32
esp32s3.build.variant=esp32s3
esp32s3.build.board=ESP32S3_DEV
esp32s3.build.cdc_on_boot=0
esp32s3.build.msc_on_boot=0
esp32s3.build.dfu_on_boot=0
esp32s3.build.f_cpu=240000000L
esp32s3.build.flash_size=4MB
esp32s3.build.flash_freq=80m
esp32s3.build.flash_mode=dio
esp32s3.build.boot=qio
esp32s3.build.partitions=default
esp32s3.build.defines=
esp32s3.build.loop_core=
esp32s3.build.event_core=
esp32s3.menu.LoopCore.1=Core 1
esp32s3.menu.LoopCore.1.build.loop_core=-DARDUINO_RUNNING_CORE=1
esp32s3.menu.LoopCore.0=Core 0
esp32s3.menu.LoopCore.0.build.loop_core=-DARDUINO_RUNNING_CORE=0
esp32s3.menu.EventsCore.1=Core 1
esp32s3.menu.EventsCore.1.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=1
esp32s3.menu.EventsCore.0=Core 0
esp32s3.menu.EventsCore.0.build.event_core=-DARDUINO_EVENT_RUNNING_CORE=0
esp32s3.menu.CDCOnBoot.default=Disabled
esp32s3.menu.CDCOnBoot.default.build.cdc_on_boot=0
esp32s3.menu.CDCOnBoot.cdc=Enabled
esp32s3.menu.CDCOnBoot.cdc.build.cdc_on_boot=1
esp32s3.menu.MSCOnBoot.default=Disabled
esp32s3.menu.MSCOnBoot.default.build.msc_on_boot=0
esp32s3.menu.MSCOnBoot.msc=Enabled
esp32s3.menu.MSCOnBoot.msc.build.msc_on_boot=1
esp32s3.menu.DFUOnBoot.default=Disabled
esp32s3.menu.DFUOnBoot.default.build.dfu_on_boot=0
esp32s3.menu.DFUOnBoot.dfu=Enabled
esp32s3.menu.DFUOnBoot.dfu.build.dfu_on_boot=1
esp32s3.menu.UploadMode.default=UART0
esp32s3.menu.UploadMode.default.upload.use_1200bps_touch=false
esp32s3.menu.UploadMode.default.upload.wait_for_upload_port=false
esp32s3.menu.UploadMode.cdc=Internal USB
esp32s3.menu.UploadMode.cdc.upload.use_1200bps_touch=true
esp32s3.menu.UploadMode.cdc.upload.wait_for_upload_port=true
esp32s3.menu.PSRAM.disabled=Disabled
esp32s3.menu.PSRAM.disabled.build.defines=
esp32s3.menu.PSRAM.enabled=Enabled
esp32s3.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
esp32s3.menu.PartitionScheme.default=Default 4MB with spiffs (1.2MB APP/1.5MB SPIFFS)
esp32s3.menu.PartitionScheme.default.build.partitions=default
esp32s3.menu.PartitionScheme.defaultffat=Default 4MB with ffat (1.2MB APP/1.5MB FATFS)
esp32s3.menu.PartitionScheme.defaultffat.build.partitions=default_ffat
esp32s3.menu.PartitionScheme.default_8MB=8M Flash (3MB APP/1.5MB FAT)
esp32s3.menu.PartitionScheme.default_8MB.build.partitions=default_8MB
esp32s3.menu.PartitionScheme.default_8MB.upload.maximum_size=3342336
esp32s3.menu.PartitionScheme.minimal=Minimal (1.3MB APP/700KB SPIFFS)
esp32s3.menu.PartitionScheme.minimal.build.partitions=minimal
esp32s3.menu.PartitionScheme.no_ota=No OTA (2MB APP/2MB SPIFFS)
esp32s3.menu.PartitionScheme.no_ota.build.partitions=no_ota
esp32s3.menu.PartitionScheme.no_ota.upload.maximum_size=2097152
esp32s3.menu.PartitionScheme.noota_3g=No OTA (1MB APP/3MB SPIFFS)
esp32s3.menu.PartitionScheme.noota_3g.build.partitions=noota_3g
esp32s3.menu.PartitionScheme.noota_3g.upload.maximum_size=1048576
esp32s3.menu.PartitionScheme.noota_ffat=No OTA (2MB APP/2MB FATFS)
esp32s3.menu.PartitionScheme.noota_ffat.build.partitions=noota_ffat
esp32s3.menu.PartitionScheme.noota_ffat.upload.maximum_size=2097152
esp32s3.menu.PartitionScheme.noota_3gffat=No OTA (1MB APP/3MB FATFS)
esp32s3.menu.PartitionScheme.noota_3gffat.build.partitions=noota_3gffat
esp32s3.menu.PartitionScheme.noota_3gffat.upload.maximum_size=1048576
esp32s3.menu.PartitionScheme.huge_app=Huge APP (3MB No OTA/1MB SPIFFS)
esp32s3.menu.PartitionScheme.huge_app.build.partitions=huge_app
esp32s3.menu.PartitionScheme.huge_app.upload.maximum_size=3145728
esp32s3.menu.PartitionScheme.min_spiffs=Minimal SPIFFS (1.9MB APP with OTA/190KB SPIFFS)
esp32s3.menu.PartitionScheme.min_spiffs.build.partitions=min_spiffs
esp32s3.menu.PartitionScheme.min_spiffs.upload.maximum_size=1966080
esp32s3.menu.PartitionScheme.fatflash=16M Flash (2MB APP/12.5MB FAT)
esp32s3.menu.PartitionScheme.fatflash.build.partitions=ffat
esp32s3.menu.PartitionScheme.fatflash.upload.maximum_size=2097152
esp32s3.menu.PartitionScheme.app3M_fat9M_16MB=16M Flash (3MB APP/9MB FATFS)
esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.build.partitions=app3M_fat9M_16MB
esp32s3.menu.PartitionScheme.app3M_fat9M_16MB.upload.maximum_size=3145728
esp32s3.menu.CPUFreq.240=240MHz (WiFi)
esp32s3.menu.CPUFreq.240.build.f_cpu=240000000L
esp32s3.menu.CPUFreq.160=160MHz (WiFi)
esp32s3.menu.CPUFreq.160.build.f_cpu=160000000L
esp32s3.menu.CPUFreq.80=80MHz (WiFi)
esp32s3.menu.CPUFreq.80.build.f_cpu=80000000L
esp32s3.menu.CPUFreq.40=40MHz
esp32s3.menu.CPUFreq.40.build.f_cpu=40000000L
esp32s3.menu.CPUFreq.20=20MHz
esp32s3.menu.CPUFreq.20.build.f_cpu=20000000L
esp32s3.menu.CPUFreq.10=10MHz
esp32s3.menu.CPUFreq.10.build.f_cpu=10000000L
esp32s3.menu.FlashMode.qio=QIO
esp32s3.menu.FlashMode.qio.build.flash_mode=dio
esp32s3.menu.FlashMode.qio.build.boot=qio
esp32s3.menu.FlashMode.dio=DIO
esp32s3.menu.FlashMode.dio.build.flash_mode=dio
esp32s3.menu.FlashMode.dio.build.boot=dio
esp32s3.menu.FlashMode.qout=QOUT
esp32s3.menu.FlashMode.qout.build.flash_mode=dout
esp32s3.menu.FlashMode.qout.build.boot=qout
esp32s3.menu.FlashMode.dout=DOUT
esp32s3.menu.FlashMode.dout.build.flash_mode=dout
esp32s3.menu.FlashMode.dout.build.boot=dout
esp32s3.menu.FlashFreq.80=80MHz
esp32s3.menu.FlashFreq.80.build.flash_freq=80m
esp32s3.menu.FlashFreq.40=40MHz
esp32s3.menu.FlashFreq.40.build.flash_freq=40m
esp32s3.menu.FlashSize.4M=4MB (32Mb)
esp32s3.menu.FlashSize.4M.build.flash_size=4MB
esp32s3.menu.FlashSize.8M=8MB (64Mb)
esp32s3.menu.FlashSize.8M.build.flash_size=8MB
esp32s3.menu.FlashSize.8M.build.partitions=default_8MB
esp32s3.menu.FlashSize.2M=2MB (16Mb)
esp32s3.menu.FlashSize.2M.build.flash_size=2MB
esp32s3.menu.FlashSize.2M.build.partitions=minimal
esp32s3.menu.FlashSize.16M=16MB (128Mb)
esp32s3.menu.FlashSize.16M.build.flash_size=16MB
esp32s3.menu.UploadSpeed.921600=921600
esp32s3.menu.UploadSpeed.921600.upload.speed=921600
esp32s3.menu.UploadSpeed.115200=115200
esp32s3.menu.UploadSpeed.115200.upload.speed=115200
esp32s3.menu.UploadSpeed.256000.windows=256000
esp32s3.menu.UploadSpeed.256000.upload.speed=256000
esp32s3.menu.UploadSpeed.230400.windows.upload.speed=256000
esp32s3.menu.UploadSpeed.230400=230400
esp32s3.menu.UploadSpeed.230400.upload.speed=230400
esp32s3.menu.UploadSpeed.460800.linux=460800
esp32s3.menu.UploadSpeed.460800.macosx=460800
esp32s3.menu.UploadSpeed.460800.upload.speed=460800
esp32s3.menu.UploadSpeed.512000.windows=512000
esp32s3.menu.UploadSpeed.512000.upload.speed=512000
esp32s3.menu.DebugLevel.none=None
esp32s3.menu.DebugLevel.none.build.code_debug=0
esp32s3.menu.DebugLevel.error=Error
esp32s3.menu.DebugLevel.error.build.code_debug=1
esp32s3.menu.DebugLevel.warn=Warn
esp32s3.menu.DebugLevel.warn.build.code_debug=2
esp32s3.menu.DebugLevel.info=Info
esp32s3.menu.DebugLevel.info.build.code_debug=3
esp32s3.menu.DebugLevel.debug=Debug
esp32s3.menu.DebugLevel.debug.build.code_debug=4
esp32s3.menu.DebugLevel.verbose=Verbose
esp32s3.menu.DebugLevel.verbose.build.code_debug=5
##############################################################
esp32s2.name=ESP32S2 Dev Module
esp32s2.vid.0=0x303a
esp32s2.pid.0=0x0002

4
cores/esp32/Esp.cpp
View file

@ -40,6 +40,10 @@ extern "C" {
#include "esp32s2/rom/spi_flash.h"
#include "soc/efuse_reg.h"
#define ESP_FLASH_IMAGE_BASE 0x1000
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#include "soc/efuse_reg.h"
#define ESP_FLASH_IMAGE_BASE 0x1000
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#define ESP_FLASH_IMAGE_BASE 0x0000 // Esp32c3 is located at 0x0000

12
cores/esp32/HardwareSerial.cpp
View file

@ -10,7 +10,7 @@
#ifndef SOC_RX0
#if CONFIG_IDF_TARGET_ESP32
#define SOC_RX0 3
#elif CONFIG_IDF_TARGET_ESP32S2
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define SOC_RX0 44
#elif CONFIG_IDF_TARGET_ESP32C3
#define SOC_RX0 20
@ -20,7 +20,7 @@
#ifndef SOC_TX0
#if CONFIG_IDF_TARGET_ESP32
#define SOC_TX0 1
#elif CONFIG_IDF_TARGET_ESP32S2
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define SOC_TX0 43
#elif CONFIG_IDF_TARGET_ESP32C3
#define SOC_TX0 21
@ -35,7 +35,7 @@ void serialEvent(void) {}
#ifndef RX1
#if CONFIG_IDF_TARGET_ESP32
#define RX1 9
#elif CONFIG_IDF_TARGET_ESP32S2
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define RX1 18
#elif CONFIG_IDF_TARGET_ESP32C3
#define RX1 18
@ -45,7 +45,7 @@ void serialEvent(void) {}
#ifndef TX1
#if CONFIG_IDF_TARGET_ESP32
#define TX1 10
#elif CONFIG_IDF_TARGET_ESP32S2
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define TX1 17
#elif CONFIG_IDF_TARGET_ESP32C3
#define TX1 19
@ -60,12 +60,16 @@ void serialEvent1(void) {}
#ifndef RX2
#if CONFIG_IDF_TARGET_ESP32
#define RX2 16
#else
#define RX2 -1
#endif
#endif
#ifndef TX2
#if CONFIG_IDF_TARGET_ESP32
#define TX2 17
#else
#define TX2 -1
#endif
#endif

4
cores/esp32/esp32-hal-adc.c
View file

@ -35,6 +35,10 @@ static uint8_t __analogVRefPin = 0;
#include "esp32s2/rom/ets_sys.h"
#include "soc/sens_reg.h"
#include "soc/rtc_io_reg.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/ets_sys.h"
#include "soc/sens_reg.h"
#include "soc/rtc_io_reg.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/ets_sys.h"
#else

3
cores/esp32/esp32-hal-cpu.c
View file

@ -33,6 +33,9 @@
#elif CONFIG_IDF_TARGET_ESP32S2
#include "freertos/xtensa_timer.h"
#include "esp32s2/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "freertos/xtensa_timer.h"
#include "esp32s3/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#else

6
cores/esp32/esp32-hal-i2c-slave.c
View file

@ -127,7 +127,7 @@ typedef enum {
static inline i2c_stretch_cause_t i2c_ll_stretch_cause(i2c_dev_t *hw)
{
#if CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
return hw->sr.stretch_cause;
#elif CONFIG_IDF_TARGET_ESP32S2
return hw->status_reg.stretch_cause;
@ -164,7 +164,7 @@ static inline void i2c_ll_stretch_clr(i2c_dev_t *hw)
static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
{
#if CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
return hw->sr.slave_addressed;
#else
return hw->status_reg.slave_addressed;
@ -173,7 +173,7 @@ static inline bool i2c_ll_slave_addressed(i2c_dev_t *hw)
static inline bool i2c_ll_slave_rw(i2c_dev_t *hw)//not exposed by hal_ll
{
#if CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
return hw->sr.slave_rw;
#else
return hw->status_reg.slave_rw;

2
cores/esp32/esp32-hal-matrix.c
View file

@ -21,6 +21,8 @@
#include "esp32/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/gpio.h"
#else

3
cores/esp32/esp32-hal-misc.c
View file

@ -41,6 +41,9 @@
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/rtc.h"
#include "driver/temp_sensor.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/rtc.h"
#include "driver/temp_sensor.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/rtc.h"
#include "driver/temp_sensor.h"

78
cores/esp32/esp32-hal-spi.c
View file

@ -37,6 +37,11 @@
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/gpio.h"
#include "esp_intr_alloc.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "soc/dport_reg.h"
#include "esp32s3/rom/ets_sys.h"
#include "esp32s3/rom/gpio.h"
#include "esp_intr_alloc.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/gpio.h"
@ -50,6 +55,8 @@
#include "esp_intr.h"
#endif
#ifndef CONFIG_IDF_TARGET_ESP32S3
struct spi_struct_t {
spi_dev_t * dev;
#if !CONFIG_DISABLE_HAL_LOCKS
@ -73,6 +80,21 @@ struct spi_struct_t {
#define SPI_INTR_SOURCE(u) ((u==0)?ETS_SPI1_INTR_SOURCE:((u==1)?ETS_SPI2_INTR_SOURCE:((u==2)?ETS_SPI3_INTR_SOURCE:0)))
#elif CONFIG_IDF_TARGET_ESP32S3
// ESP32S3
#define SPI_COUNT (2)
#define SPI_CLK_IDX(p) ((p==0)?SPICLK_OUT_IDX:((p==1)?FSPICLK_OUT_IDX:0))
#define SPI_MISO_IDX(p) ((p==0)?SPIQ_OUT_IDX:((p==1)?FSPIQ_OUT_IDX:0))
#define SPI_MOSI_IDX(p) ((p==0)?SPID_IN_IDX:((p==1)?FSPID_IN_IDX:0))
#define SPI_SPI_SS_IDX(n) ((n==0)?SPICS0_OUT_IDX:((n==1)?SPICS1_OUT_IDX:0))
#define SPI_HSPI_SS_IDX(n) ((n==0)?SPI3_CS0_OUT_IDX:((n==1)?SPI3_CS1_OUT_IDX:0))
#define SPI_FSPI_SS_IDX(n) ((n==0)?FSPICS0_OUT_IDX:((n==1)?FSPICS1_OUT_IDX:0))
#define SPI_SS_IDX(p, n) ((p==0)?SPI_SPI_SS_IDX(n):((p==1)?SPI_SPI_SS_IDX(n):0))
#define SPI_INTR_SOURCE(u) ((u==0)?ETS_SPI1_INTR_SOURCE:((u==1)?ETS_SPI2_INTR_SOURCE:0))
#elif CONFIG_IDF_TARGET_ESP32C3
// ESP32S2
#define SPI_COUNT (1)
@ -112,6 +134,9 @@ static spi_t _spi_bus_array[] = {
{(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 0},
{(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 1},
{(volatile spi_dev_t *)(DR_REG_SPI3_BASE), 2}
#elif CONFIG_IDF_TARGET_ESP32S3
{(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 0},
{(volatile spi_dev_t *)(DR_REG_SPI2_BASE), 1}
#else
{(volatile spi_dev_t *)(DR_REG_SPI0_BASE), 0},
{(volatile spi_dev_t *)(DR_REG_SPI1_BASE), 1},
@ -128,6 +153,9 @@ static spi_t _spi_bus_array[] = {
{(volatile spi_dev_t *)(DR_REG_SPI1_BASE), NULL, 0},
{(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 1},
{(volatile spi_dev_t *)(DR_REG_SPI3_BASE), NULL, 2}
#elif CONFIG_IDF_TARGET_ESP32S3
{(volatile spi_dev_t *)(DR_REG_SPI1_BASE), NULL, 0},
{(volatile spi_dev_t *)(DR_REG_SPI2_BASE), NULL, 1}
#elif CONFIG_IDF_TARGET_ESP32C3
{(volatile spi_dev_t *)(&GPSPI2), NULL, FSPI}
#else
@ -145,7 +173,7 @@ void spiAttachSCK(spi_t * spi, int8_t sck)
return;
}
if(sck < 0) {
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if(spi->num == FSPI) {
sck = 36;
} else {
@ -175,7 +203,7 @@ void spiAttachMISO(spi_t * spi, int8_t miso)
return;
}
if(miso < 0) {
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if(spi->num == FSPI) {
miso = 37;
} else {
@ -207,7 +235,7 @@ void spiAttachMOSI(spi_t * spi, int8_t mosi)
return;
}
if(mosi < 0) {
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if(spi->num == FSPI) {
mosi = 35;
} else {
@ -237,7 +265,7 @@ void spiDetachSCK(spi_t * spi, int8_t sck)
return;
}
if(sck < 0) {
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if(spi->num == FSPI) {
sck = 36;
} else {
@ -267,7 +295,7 @@ void spiDetachMISO(spi_t * spi, int8_t miso)
return;
}
if(miso < 0) {
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if(spi->num == FSPI) {
miso = 37;
} else {
@ -297,7 +325,7 @@ void spiDetachMOSI(spi_t * spi, int8_t mosi)
return;
}
if(mosi < 0) {
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if(spi->num == FSPI) {
mosi = 35;
} else {
@ -331,7 +359,7 @@ void spiAttachSS(spi_t * spi, uint8_t cs_num, int8_t ss)
}
if(ss < 0) {
cs_num = 0;
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if(spi->num == FSPI) {
ss = 34;
} else {
@ -362,7 +390,7 @@ void spiDetachSS(spi_t * spi, int8_t ss)
return;
}
if(ss < 0) {
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if(spi->num == FSPI) {
ss = 34;
} else {
@ -392,7 +420,7 @@ void spiEnableSSPins(spi_t * spi, uint8_t cs_mask)
return;
}
SPI_MUTEX_LOCK();
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.val &= ~(cs_mask & SPI_CS_MASK_ALL);
#else
spi->dev->pin.val &= ~(cs_mask & SPI_CS_MASK_ALL);
@ -406,7 +434,7 @@ void spiDisableSSPins(spi_t * spi, uint8_t cs_mask)
return;
}
SPI_MUTEX_LOCK();
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.val |= (cs_mask & SPI_CS_MASK_ALL);
#else
spi->dev->pin.val |= (cs_mask & SPI_CS_MASK_ALL);
@ -442,7 +470,7 @@ void spiSSSet(spi_t * spi)
return;
}
SPI_MUTEX_LOCK();
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.cs_keep_active = 1;
#else
spi->dev->pin.cs_keep_active = 1;
@ -456,7 +484,7 @@ void spiSSClear(spi_t * spi)
return;
}
SPI_MUTEX_LOCK();
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.cs_keep_active = 0;
#else
spi->dev->pin.cs_keep_active = 0;
@ -487,7 +515,7 @@ uint8_t spiGetDataMode(spi_t * spi)
if(!spi) {
return 0;
}
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
bool idleEdge = spi->dev->misc.ck_idle_edge;
#else
bool idleEdge = spi->dev->pin.ck_idle_edge;
@ -513,7 +541,7 @@ void spiSetDataMode(spi_t * spi, uint8_t dataMode)
SPI_MUTEX_LOCK();
switch (dataMode) {
case SPI_MODE1:
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.ck_idle_edge = 0;
#else
spi->dev->pin.ck_idle_edge = 0;
@ -521,7 +549,7 @@ void spiSetDataMode(spi_t * spi, uint8_t dataMode)
spi->dev->user.ck_out_edge = 1;
break;
case SPI_MODE2:
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.ck_idle_edge = 1;
#else
spi->dev->pin.ck_idle_edge = 1;
@ -529,7 +557,7 @@ void spiSetDataMode(spi_t * spi, uint8_t dataMode)
spi->dev->user.ck_out_edge = 1;
break;
case SPI_MODE3:
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.ck_idle_edge = 1;
#else
spi->dev->pin.ck_idle_edge = 1;
@ -538,7 +566,7 @@ void spiSetDataMode(spi_t * spi, uint8_t dataMode)
break;
case SPI_MODE0:
default:
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.ck_idle_edge = 0;
#else
spi->dev->pin.ck_idle_edge = 0;
@ -591,7 +619,7 @@ static void spiInitBus(spi_t * spi)
spi->dev->slave.trans_done = 0;
#endif
spi->dev->slave.val = 0;
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.val = 0;
#else
spi->dev->pin.val = 0;
@ -641,7 +669,7 @@ spi_t * spiStartBus(uint8_t spi_num, uint32_t clockDiv, uint8_t dataMode, uint8_
}
#endif
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if(spi_num == FSPI) {
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_CLK_EN);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_RST);
@ -704,7 +732,7 @@ void spiWaitReady(spi_t * spi)
while(spi->dev->cmd.usr);
}
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#define usr_mosi_dbitlen usr_mosi_bit_len
#define usr_miso_dbitlen usr_miso_bit_len
#elif CONFIG_IDF_TARGET_ESP32C3
@ -1012,7 +1040,7 @@ void spiTransaction(spi_t * spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bi
spi->dev->clock.val = clockDiv;
switch (dataMode) {
case SPI_MODE1:
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.ck_idle_edge = 0;
#else
spi->dev->pin.ck_idle_edge = 0;
@ -1020,7 +1048,7 @@ void spiTransaction(spi_t * spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bi
spi->dev->user.ck_out_edge = 1;
break;
case SPI_MODE2:
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.ck_idle_edge = 1;
#else
spi->dev->pin.ck_idle_edge = 1;
@ -1028,7 +1056,7 @@ void spiTransaction(spi_t * spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bi
spi->dev->user.ck_out_edge = 1;
break;
case SPI_MODE3:
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.ck_idle_edge = 1;
#else
spi->dev->pin.ck_idle_edge = 1;
@ -1037,7 +1065,7 @@ void spiTransaction(spi_t * spi, uint32_t clockDiv, uint8_t dataMode, uint8_t bi
break;
case SPI_MODE0:
default:
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
spi->dev->misc.ck_idle_edge = 0;
#else
spi->dev->pin.ck_idle_edge = 0;
@ -1475,4 +1503,4 @@ uint32_t spiFrequencyToClockDiv(uint32_t freq)
}
return bestReg.value;
}
#endif /* ifndef CONFIG_IDF_TARGET_ESP32S3 */

6
cores/esp32/esp32-hal-tinyusb.c
View file

@ -34,9 +34,15 @@
#include "esp32-hal.h"
#include "esp32-hal-tinyusb.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/usb/usb_persist.h"
#include "esp32s2/rom/usb/usb_dc.h"
#include "esp32s2/rom/usb/chip_usb_dw_wrapper.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/usb/usb_persist.h"
#include "esp32s3/rom/usb/usb_dc.h"
#include "esp32s3/rom/usb/chip_usb_dw_wrapper.h"
#endif
typedef enum{
TINYUSB_USBDEV_0,

2
cores/esp32/esp32-hal-tinyusb.h
View file

@ -15,7 +15,6 @@
#include "esp32-hal.h"
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_TINYUSB_ENABLED
#ifdef __cplusplus
@ -105,4 +104,3 @@ uint8_t tinyusb_get_free_out_endpoint(void);
#endif
#endif /* CONFIG_TINYUSB_ENABLED */
#endif /* CONFIG_IDF_TARGET_ESP32S2 */

4
cores/esp32/esp32-hal-touch.c
View file

@ -32,6 +32,10 @@
#include "esp32s2/rom/ets_sys.h"
#include "esp_intr_alloc.h"
#include "soc/periph_defs.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/ets_sys.h"
#include "esp_intr_alloc.h"
#include "soc/periph_defs.h"
#else
#error Target CONFIG_IDF_TARGET is not supported
#endif

7
cores/esp32/esp32-hal-uart.c
View file

@ -541,6 +541,7 @@ void log_print_buf(const uint8_t *b, size_t len){
*/
unsigned long uartBaudrateDetect(uart_t *uart, bool flg)
{
#ifndef CONFIG_IDF_TARGET_ESP32S3
if(uart == NULL) {
return 0;
}
@ -558,6 +559,9 @@ unsigned long uartBaudrateDetect(uart_t *uart, bool flg)
UART_MUTEX_UNLOCK();
return ret;
#else
return 0;
#endif
}
@ -602,7 +606,7 @@ void uartStartDetectBaudrate(uart_t *uart) {
//hw->rx_filt.glitch_filt_en = 1;
//hw->conf0.autobaud_en = 0;
//hw->conf0.autobaud_en = 1;
#elif CONFIG_IDF_TARGET_ESP32S3
#else
hw->auto_baud.glitch_filt = 0x08;
hw->auto_baud.en = 0;
@ -639,6 +643,7 @@ uartDetectBaudrate(uart_t *uart)
#ifdef CONFIG_IDF_TARGET_ESP32C3
//hw->conf0.autobaud_en = 0;
#elif CONFIG_IDF_TARGET_ESP32S3
#else
hw->auto_baud.en = 0;
#endif

2
libraries/SPI/src/SPI.cpp
View file

@ -50,7 +50,7 @@ void SPIClass::begin(int8_t sck, int8_t miso, int8_t mosi, int8_t ss)
}
if(sck == -1 && miso == -1 && mosi == -1 && ss == -1) {
#if CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
_sck = (_spi_num == FSPI) ? SCK : -1;
_miso = (_spi_num == FSPI) ? MISO : -1;
_mosi = (_spi_num == FSPI) ? MOSI : -1;

21
platform.txt
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2
tools/platformio-build-esp32.py
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@ -303,7 +303,7 @@ env.Append(
"UNITY_INCLUDE_CONFIG_H",
"WITH_POSIX",
"_GNU_SOURCE",
("IDF_VER", '\\"v4.4-beta1-308-gf3e0c8bc41\\"'),
("IDF_VER", '\\"v4.4-rc1\\"'),
"ESP_PLATFORM",
"_POSIX_READER_WRITER_LOCKS",
"ARDUINO_ARCH_ESP32",

2
tools/platformio-build-esp32c3.py
View file

@ -293,7 +293,7 @@ env.Append(
"UNITY_INCLUDE_CONFIG_H",
"WITH_POSIX",
"_GNU_SOURCE",
("IDF_VER", '\\"v4.4-beta1-308-gf3e0c8bc41\\"'),
("IDF_VER", '\\"v4.4-rc1\\"'),
"ESP_PLATFORM",
"_POSIX_READER_WRITER_LOCKS",
"ARDUINO_ARCH_ESP32",

2
tools/platformio-build-esp32s2.py
View file

@ -290,7 +290,7 @@ env.Append(
"UNITY_INCLUDE_CONFIG_H",
"WITH_POSIX",
"_GNU_SOURCE",
("IDF_VER", '\\"v4.4-beta1-308-gf3e0c8bc41\\"'),
("IDF_VER", '\\"v4.4-rc1\\"'),
"ESP_PLATFORM",
"_POSIX_READER_WRITER_LOCKS",
"ARDUINO_ARCH_ESP32",

380
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4
tools/sdk/esp32/include/config/sdkconfig.h
View file

@ -227,7 +227,7 @@
#define CONFIG_ESP_EVENT_POST_FROM_IRAM_ISR 1
#define CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS 1
#define CONFIG_ESP_HTTP_CLIENT_ENABLE_DIGEST_AUTH 1
#define CONFIG_HTTPD_MAX_REQ_HDR_LEN 512
#define CONFIG_HTTPD_MAX_REQ_HDR_LEN 1024
#define CONFIG_HTTPD_MAX_URI_LEN 512
#define CONFIG_HTTPD_ERR_RESP_NO_DELAY 1
#define CONFIG_HTTPD_PURGE_BUF_LEN 32
@ -551,7 +551,9 @@
#define CONFIG_GC2145_SUPPORT 1
#define CONFIG_GC032A_SUPPORT 1
#define CONFIG_GC0308_SUPPORT 1
#define CONFIG_BF3005_SUPPORT 1
#define CONFIG_SCCB_HARDWARE_I2C_PORT1 1
#define CONFIG_SCCB_CLK_FREQ 100000
#define CONFIG_GC_SENSOR_SUBSAMPLE_MODE 1
#define CONFIG_CAMERA_CORE0 1
#define CONFIG_CAMERA_DMA_BUFFER_SIZE_MAX 32768

3
tools/sdk/esp32/include/esp32-camera/driver/include/sensor.h
View file

@ -26,6 +26,7 @@ typedef enum {
GC2145_PID = 0x2145,
GC032A_PID = 0x232a,
GC0308_PID = 0x9b,
BF3005_PID = 0x30,
} camera_pid_t;
typedef enum {
@ -38,6 +39,7 @@ typedef enum {
CAMERA_GC2145,
CAMERA_GC032A,
CAMERA_GC0308,
CAMERA_BF3005,
CAMERA_MODEL_MAX,
CAMERA_NONE,
} camera_model_t;
@ -52,6 +54,7 @@ typedef enum {
GC2145_SCCB_ADDR = 0x3C,// 0x78 >> 1
GC032A_SCCB_ADDR = 0x21,// 0x42 >> 1
GC0308_SCCB_ADDR = 0x21,// 0x42 >> 1
BF3005_SCCB_ADDR = 0x6E,
} camera_sccb_addr_t;
typedef enum {

2
tools/sdk/esp32/ld/sections.ld
View file

@ -1,6 +1,6 @@
/* Automatically generated file; DO NOT EDIT */
/* Espressif IoT Development Framework Linker Script */
/* Generated from: /home/runner/work/esp32-arduino-lib-builder/esp32-arduino-lib-builder/esp-idf/components/esp_system/ld/esp32/sections.ld.in */
/* Generated from: /Users/ficeto/Desktop/ESP32/ESP32S2/esp-idf-public/components/esp_system/ld/esp32/sections.ld.in */
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD

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