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fix(clk_src): Fix error as APLL is not yet supported for P4

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Lucas Saavedra Vaz 2024-12-16 10:48:50 -03:00
parent 1ef1e7dbac
commit c688f3090f
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GPG key ID: 9CAE85DC84A38188
1 changed files with 2 additions and 11 deletions
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13
cores/esp32/esp32-hal-cpu.c
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@ -259,18 +259,10 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
if (apb_change_callbacks) { if (apb_change_callbacks) {
triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb); triggerApbChangeCallback(APB_AFTER_CHANGE, capb, apb);
} }
// clang-format off #if defined(SOC_CLK_APLL_SUPPORTED) && !defined(CONFIG_IDF_TARGET_ESP32P4) // APLL not yet supported in ESP32-P4
#ifdef SOC_CLK_APLL_SUPPORTED
log_d( log_d(
"%s: %u / %u = %u Mhz, APB: %u Hz", "%s: %u / %u = %u Mhz, APB: %u Hz",
(conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" (conf.source == SOC_CPU_CLK_SRC_PLL) ? "PLL" : ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL" : ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL" : "8M")),
: ((conf.source == SOC_CPU_CLK_SRC_APLL) ? "APLL"
: ((conf.source == SOC_CPU_CLK_SRC_XTAL) ? "XTAL"
#ifdef CONFIG_IDF_TARGET_ESP32P4
: "17.5M")),
#else
: "8M")),
#endif
conf.source_freq_mhz, conf.div, conf.freq_mhz, apb conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
); );
#else #else
@ -279,7 +271,6 @@ bool setCpuFrequencyMhz(uint32_t cpu_freq_mhz) {
conf.source_freq_mhz, conf.div, conf.freq_mhz, apb conf.source_freq_mhz, conf.div, conf.freq_mhz, apb
); );
#endif #endif
// clang-format on
return true; return true;
} }