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fix(psram): Add support for ESP32-C5 PSRAM

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me-no-dev 2025-01-27 14:06:54 +02:00
parent 9fbcb345b7
commit f45cd7bf33
3 changed files with 10 additions and 0 deletions
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5
boards.txt
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@ -210,6 +210,11 @@ esp32c5.menu.JTAGAdapter.bridge=ESP USB Bridge
esp32c5.menu.JTAGAdapter.bridge.build.openocdscript=esp32c5-bridge.cfg
esp32c5.menu.JTAGAdapter.bridge.build.copy_jtag_files=1
esp32c5.menu.PSRAM.disabled=Disabled
esp32c5.menu.PSRAM.disabled.build.defines=
esp32c5.menu.PSRAM.enabled=Enabled
esp32c5.menu.PSRAM.enabled.build.defines=-DBOARD_HAS_PSRAM
esp32c5.menu.CDCOnBoot.default=Disabled
esp32c5.menu.CDCOnBoot.default.build.cdc_on_boot=0
esp32c5.menu.CDCOnBoot.cdc=Enabled

3
cores/esp32/chip-debug-report.cpp
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@ -67,6 +67,9 @@ static void printPkgVersion(void) {
#elif CONFIG_IDF_TARGET_ESP32P4
uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS_2_REG, EFUSE_PKG_VERSION);
chip_report_printf("%lu", pkg_ver);
#elif CONFIG_IDF_TARGET_ESP32C5
uint32_t pkg_ver = REG_GET_FIELD(EFUSE_RD_MAC_SYS2_REG, EFUSE_PKG_VERSION);
chip_report_printf("%lu", pkg_ver);
#else
chip_report_printf("Unknown");
#endif

2
cores/esp32/esp32-hal-psram.c
View file

@ -29,6 +29,8 @@
#include "esp32s3/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C5
#include "esp32c5/rom/cache.h"
#else
#error Target CONFIG_IDF_TARGET is not supported
#endif