ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-H2 ESP32 H-Series 1 32-bit RISC-V MCU & IEEE 802.15.4 & Bluetooth 5 (LE) Copyright 2022 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. RV32IMC r0p0 little false false 4 false 32 32 0x00000000 0xFFFFFFFF AES AES (Advanced Encryption Standard) Accelerator AES 0x6003A000 0x0 0xBC registers AES 48 KEY_0 Key material key_0 configure register 0x0 0x20 KEY_0 This bits stores key_0 that is a part of key material. 0 32 read-write KEY_1 Key material key_1 configure register 0x4 0x20 KEY_1 This bits stores key_1 that is a part of key material. 0 32 read-write KEY_2 Key material key_2 configure register 0x8 0x20 KEY_2 This bits stores key_2 that is a part of key material. 0 32 read-write KEY_3 Key material key_3 configure register 0xC 0x20 KEY_3 This bits stores key_3 that is a part of key material. 0 32 read-write KEY_4 Key material key_4 configure register 0x10 0x20 KEY_4 This bits stores key_4 that is a part of key material. 0 32 read-write KEY_5 Key material key_5 configure register 0x14 0x20 KEY_5 This bits stores key_5 that is a part of key material. 0 32 read-write KEY_6 Key material key_6 configure register 0x18 0x20 KEY_6 This bits stores key_6 that is a part of key material. 0 32 read-write KEY_7 Key material key_7 configure register 0x1C 0x20 KEY_7 This bits stores key_7 that is a part of key material. 0 32 read-write TEXT_IN_0 source text material text_in_0 configure register 0x20 0x20 TEXT_IN_0 This bits stores text_in_0 that is a part of source text material. 0 32 read-write TEXT_IN_1 source text material text_in_1 configure register 0x24 0x20 TEXT_IN_1 This bits stores text_in_1 that is a part of source text material. 0 32 read-write TEXT_IN_2 source text material text_in_2 configure register 0x28 0x20 TEXT_IN_2 This bits stores text_in_2 that is a part of source text material. 0 32 read-write TEXT_IN_3 source text material text_in_3 configure register 0x2C 0x20 TEXT_IN_3 This bits stores text_in_3 that is a part of source text material. 0 32 read-write TEXT_OUT_0 result text material text_out_0 configure register 0x30 0x20 TEXT_OUT_0 This bits stores text_out_0 that is a part of result text material. 0 32 read-write TEXT_OUT_1 result text material text_out_1 configure register 0x34 0x20 TEXT_OUT_1 This bits stores text_out_1 that is a part of result text material. 0 32 read-write TEXT_OUT_2 result text material text_out_2 configure register 0x38 0x20 TEXT_OUT_2 This bits stores text_out_2 that is a part of result text material. 0 32 read-write TEXT_OUT_3 result text material text_out_3 configure register 0x3C 0x20 TEXT_OUT_3 This bits stores text_out_3 that is a part of result text material. 0 32 read-write MODE AES Mode register 0x40 0x20 MODE This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256. 0 3 read-write ENDIAN AES Endian configure register 0x44 0x20 ENDIAN endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian 0 6 read-write TRIGGER AES trigger register 0x48 0x20 TRIGGER Set this bit to start AES calculation. 0 1 write-only STATE AES state register 0x4C 0x20 STATE Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done. 0 2 read-only 16 0x1 IV_MEM[%s] The memory that stores initialization vector 0x50 0x8 16 0x1 H_MEM[%s] The memory that stores GCM hash subkey 0x60 0x8 16 0x1 J0_MEM[%s] The memory that stores J0 0x70 0x8 16 0x1 T0_MEM[%s] The memory that stores T0 0x80 0x8 DMA_ENABLE DMA-AES working mode register 0x90 0x20 DMA_ENABLE 1'b0: typical AES working mode, 1'b1: DMA-AES working mode. 0 1 read-write BLOCK_MODE AES cipher block mode register 0x94 0x20 BLOCK_MODE Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved. 0 3 read-write BLOCK_NUM AES block number register 0x98 0x20 BLOCK_NUM Those bits stores the number of Plaintext/ciphertext block. 0 32 read-write INC_SEL Standard incrementing function configure register 0x9C 0x20 INC_SEL This bit decides the standard incrementing function. 0: INC32. 1: INC128. 0 1 read-write AAD_BLOCK_NUM Additional Authential Data block number register 0xA0 0x20 AAD_BLOCK_NUM Those bits stores the number of AAD block. 0 32 read-write REMAINDER_BIT_NUM AES remainder bit number register 0xA4 0x20 REMAINDER_BIT_NUM Those bits stores the number of remainder bit. 0 7 read-write CONTINUE AES continue register 0xA8 0x20 CONTINUE Set this bit to continue GCM operation. 0 1 write-only INT_CLEAR AES Interrupt clear register 0xAC 0x20 INT_CLEAR Set this bit to clear the AES interrupt. 0 1 write-only INT_ENA AES Interrupt enable register 0xB0 0x20 INT_ENA Set this bit to enable interrupt that occurs when DMA-AES calculation is done. 0 1 read-write DATE AES version control register 0xB4 0x20 0x20191210 DATE This bits stores the version information of AES. 0 30 read-write DMA_EXIT AES-DMA exit config 0xB8 0x20 DMA_EXIT Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer. 0 1 write-only APB_SARADC Successive Approximation Register Analog to Digital Converter APB_SARADC 0x60040000 0x0 0x70 registers APB_ADC 43 CTRL digital saradc configure register 0x0 0x20 0x40038240 SARADC_START_FORCE select software enable saradc sample 0 1 read-write SARADC_START software enable saradc sample 1 1 read-write SARADC_SAR_CLK_GATED SAR clock gated 6 1 read-write SARADC_SAR_CLK_DIV SAR clock divider 7 8 read-write SARADC_SAR_PATT_LEN 0 ~ 15 means length 1 ~ 16 15 3 read-write SARADC_SAR_PATT_P_CLEAR clear the pointer of pattern table for DIG ADC1 CTRL 23 1 read-write SARADC_XPD_SAR_FORCE force option to xpd sar blocks 27 2 read-write SARADC2_PWDET_DRV enable saradc2 power detect driven func. 29 1 read-write SARADC_WAIT_ARB_CYCLE wait arbit signal stable after sar_done 30 2 read-write CTRL2 digital saradc configure register 0x4 0x20 0x0000A1FE SARADC_MEAS_NUM_LIMIT enable max meas num 0 1 read-write SARADC_MAX_MEAS_NUM max conversion number 1 8 read-write SARADC_SAR1_INV 1: data to DIG ADC1 CTRL is inverted, otherwise not 9 1 read-write SARADC_SAR2_INV 1: data to DIG ADC2 CTRL is inverted, otherwise not 10 1 read-write SARADC_TIMER_TARGET to set saradc timer target 12 12 read-write SARADC_TIMER_EN to enable saradc timer trigger 24 1 read-write FILTER_CTRL1 digital saradc configure register 0x8 0x20 APB_SARADC_FILTER_FACTOR1 Factor of saradc filter1 26 3 read-write APB_SARADC_FILTER_FACTOR0 Factor of saradc filter0 29 3 read-write FSM_WAIT digital saradc configure register 0xC 0x20 0x00FF0808 SARADC_XPD_WAIT saradc_xpd_wait 0 8 read-write SARADC_RSTB_WAIT saradc_rstb_wait 8 8 read-write SARADC_STANDBY_WAIT saradc_standby_wait 16 8 read-write SAR1_STATUS digital saradc configure register 0x10 0x20 0x20000000 SARADC_SAR1_STATUS saradc1 status about data and channel 0 32 read-only SAR2_STATUS digital saradc configure register 0x14 0x20 0x20000000 SARADC_SAR2_STATUS saradc2 status about data and channel 0 32 read-only SAR_PATT_TAB1 digital saradc configure register 0x18 0x20 0x00FFFFFF SARADC_SAR_PATT_TAB1 item 0 ~ 3 for pattern table 1 (each item one byte) 0 24 read-write SAR_PATT_TAB2 digital saradc configure register 0x1C 0x20 0x00FFFFFF SARADC_SAR_PATT_TAB2 Item 4 ~ 7 for pattern table 1 (each item one byte) 0 24 read-write ONETIME_SAMPLE digital saradc configure register 0x20 0x20 0x1A000000 SARADC_ONETIME_ATTEN configure onetime atten 23 2 read-write SARADC_ONETIME_CHANNEL configure onetime channel 25 4 read-write SARADC_ONETIME_START trigger adc onetime sample 29 1 read-write SARADC2_ONETIME_SAMPLE enable adc2 onetime sample 30 1 read-write SARADC1_ONETIME_SAMPLE enable adc1 onetime sample 31 1 read-write ARB_CTRL digital saradc configure register 0x24 0x20 0x00000900 ADC_ARB_APB_FORCE adc2 arbiter force to enableapb controller 2 1 read-write ADC_ARB_RTC_FORCE adc2 arbiter force to enable rtc controller 3 1 read-write ADC_ARB_WIFI_FORCE adc2 arbiter force to enable wifi controller 4 1 read-write ADC_ARB_GRANT_FORCE adc2 arbiter force grant 5 1 read-write ADC_ARB_APB_PRIORITY Set adc2 arbiterapb priority 6 2 read-write ADC_ARB_RTC_PRIORITY Set adc2 arbiter rtc priority 8 2 read-write ADC_ARB_WIFI_PRIORITY Set adc2 arbiter wifi priority 10 2 read-write ADC_ARB_FIX_PRIORITY adc2 arbiter uses fixed priority 12 1 read-write FILTER_CTRL0 digital saradc configure register 0x28 0x20 0x03740000 APB_SARADC_FILTER_CHANNEL1 configure filter1 to adc channel 18 4 read-write APB_SARADC_FILTER_CHANNEL0 configure filter0 to adc channel 22 4 read-write APB_SARADC_FILTER_RESET enable apb_adc1_filter 31 1 read-write SAR1DATA_STATUS digital saradc configure register 0x2C 0x20 APB_SARADC1_DATA saradc1 data 0 17 read-only SAR2DATA_STATUS digital saradc configure register 0x30 0x20 APB_SARADC2_DATA saradc2 data 0 17 read-only THRES0_CTRL digital saradc configure register 0x34 0x20 0x0003FFED APB_SARADC_THRES0_CHANNEL configure thres0 to adc channel 0 4 read-write APB_SARADC_THRES0_HIGH saradc thres0 monitor thres 5 13 read-write APB_SARADC_THRES0_LOW saradc thres0 monitor thres 18 13 read-write THRES1_CTRL digital saradc configure register 0x38 0x20 0x0003FFED APB_SARADC_THRES1_CHANNEL configure thres1 to adc channel 0 4 read-write APB_SARADC_THRES1_HIGH saradc thres1 monitor thres 5 13 read-write APB_SARADC_THRES1_LOW saradc thres1 monitor thres 18 13 read-write THRES_CTRL digital saradc configure register 0x3C 0x20 APB_SARADC_THRES_ALL_EN enable thres to all channel 27 1 read-write APB_SARADC_THRES1_EN enable thres1 30 1 read-write APB_SARADC_THRES0_EN enable thres0 31 1 read-write INT_ENA digital saradc int register 0x40 0x20 APB_SARADC_TSENS_INT_ENA tsens low interrupt enable 25 1 read-write APB_SARADC_THRES1_LOW_INT_ENA saradc thres1 low interrupt enable 26 1 read-write APB_SARADC_THRES0_LOW_INT_ENA saradc thres0 low interrupt enable 27 1 read-write APB_SARADC_THRES1_HIGH_INT_ENA saradc thres1 high interrupt enable 28 1 read-write APB_SARADC_THRES0_HIGH_INT_ENA saradc thres0 high interrupt enable 29 1 read-write APB_SARADC2_DONE_INT_ENA saradc2 done interrupt enable 30 1 read-write APB_SARADC1_DONE_INT_ENA saradc1 done interrupt enable 31 1 read-write INT_RAW digital saradc int register 0x44 0x20 APB_SARADC_TSENS_INT_RAW saradc tsens interrupt raw 25 1 read-only APB_SARADC_THRES1_LOW_INT_RAW saradc thres1 low interrupt raw 26 1 read-only APB_SARADC_THRES0_LOW_INT_RAW saradc thres0 low interrupt raw 27 1 read-only APB_SARADC_THRES1_HIGH_INT_RAW saradc thres1 high interrupt raw 28 1 read-only APB_SARADC_THRES0_HIGH_INT_RAW saradc thres0 high interrupt raw 29 1 read-only APB_SARADC2_DONE_INT_RAW saradc2 done interrupt raw 30 1 read-only APB_SARADC1_DONE_INT_RAW saradc1 done interrupt raw 31 1 read-only INT_ST digital saradc int register 0x48 0x20 APB_SARADC_TSENS_INT_ST saradc tsens interrupt state 25 1 read-only APB_SARADC_THRES1_LOW_INT_ST saradc thres1 low interrupt state 26 1 read-only APB_SARADC_THRES0_LOW_INT_ST saradc thres0 low interrupt state 27 1 read-only APB_SARADC_THRES1_HIGH_INT_ST saradc thres1 high interrupt state 28 1 read-only APB_SARADC_THRES0_HIGH_INT_ST saradc thres0 high interrupt state 29 1 read-only APB_SARADC2_DONE_INT_ST saradc2 done interrupt state 30 1 read-only APB_SARADC1_DONE_INT_ST saradc1 done interrupt state 31 1 read-only INT_CLR digital saradc int register 0x4C 0x20 APB_SARADC_TSENS_INT_CLR saradc tsens interrupt clear 25 1 write-only APB_SARADC_THRES1_LOW_INT_CLR saradc thres1 low interrupt clear 26 1 write-only APB_SARADC_THRES0_LOW_INT_CLR saradc thres0 low interrupt clear 27 1 write-only APB_SARADC_THRES1_HIGH_INT_CLR saradc thres1 high interrupt clear 28 1 write-only APB_SARADC_THRES0_HIGH_INT_CLR saradc thres0 high interrupt clear 29 1 write-only APB_SARADC2_DONE_INT_CLR saradc2 done interrupt clear 30 1 write-only APB_SARADC1_DONE_INT_CLR saradc1 done interrupt clear 31 1 write-only DMA_CONF digital saradc configure register 0x50 0x20 0x000000FF APB_ADC_EOF_NUM the dma_in_suc_eof gen when sample cnt = spi_eof_num 0 16 read-write APB_ADC_RESET_FSM reset_apb_adc_state 30 1 read-write APB_ADC_TRANS enable apb_adc use spi_dma 31 1 read-write CLKM_CONF digital saradc configure register 0x54 0x20 0x00000004 CLKM_DIV_NUM Integral I2S clock divider value 0 8 read-write CLKM_DIV_B Fractional clock divider numerator value 8 6 read-write CLKM_DIV_A Fractional clock divider denominator value 14 6 read-write CLK_EN reg clk en 20 1 read-write CLK_SEL Set this bit to enable clk_apll 21 2 read-write APB_TSENS_CTRL digital tsens configure register 0x58 0x20 0x00018080 TSENS_OUT temperature sensor data out 0 8 read-only TSENS_IN_INV invert temperature sensor data 13 1 read-write TSENS_CLK_DIV temperature sensor clock divider 14 8 read-write TSENS_PU temperature sensor power up 22 1 read-write TSENS_CTRL2 digital tsens configure register 0x5C 0x20 0x00004002 TSENS_XPD_WAIT the time that power up tsens need wait 0 12 read-write TSENS_XPD_FORCE force power up tsens 12 2 read-write TSENS_CLK_INV inv tsens clk 14 1 read-write TSENS_CLK_SEL tsens clk select 15 1 read-write CALI digital saradc configure register 0x60 0x20 0x00008000 APB_SARADC_CALI_CFG saradc cali factor 0 17 read-write APB_TSENS_WAKE digital tsens configure register 0x64 0x20 0x0000FF00 WAKEUP_TH_LOW reg_wakeup_th_low 0 8 read-write WAKEUP_TH_HIGH reg_wakeup_th_high 8 8 read-write WAKEUP_OVER_UPPER_TH reg_wakeup_over_upper_th 16 1 read-only WAKEUP_MODE reg_wakeup_mode 17 1 read-write WAKEUP_EN reg_wakeup_en 18 1 read-write APB_TSENS_SAMPLE digital tsens configure register 0x68 0x20 0x00000014 TSENS_SAMPLE_RATE HW sample rate 0 16 read-write TSENS_SAMPLE_EN HW sample en 16 1 read-write CTRL_DATE version 0x3FC 0x20 0x02206240 DATE version 0 32 read-write ASSIST_DEBUG Debug Assist ASSIST_DEBUG 0x600CE000 0x0 0x80 registers C0RE_0_INTR_ENA core0 monitor enable configuration register 0x0 0x20 CORE_0_AREA_DRAM0_0_RD_ENA Core0 dram0 area0 read monitor enable 0 1 read-write CORE_0_AREA_DRAM0_0_WR_ENA Core0 dram0 area0 write monitor enable 1 1 read-write CORE_0_AREA_DRAM0_1_RD_ENA Core0 dram0 area1 read monitor enable 2 1 read-write CORE_0_AREA_DRAM0_1_WR_ENA Core0 dram0 area1 write monitor enable 3 1 read-write CORE_0_AREA_PIF_0_RD_ENA Core0 PIF area0 read monitor enable 4 1 read-write CORE_0_AREA_PIF_0_WR_ENA Core0 PIF area0 write monitor enable 5 1 read-write CORE_0_AREA_PIF_1_RD_ENA Core0 PIF area1 read monitor enable 6 1 read-write CORE_0_AREA_PIF_1_WR_ENA Core0 PIF area1 write monitor enable 7 1 read-write CORE_0_SP_SPILL_MIN_ENA Core0 stackpoint underflow monitor enable 8 1 read-write CORE_0_SP_SPILL_MAX_ENA Core0 stackpoint overflow monitor enable 9 1 read-write CORE_0_IRAM0_EXCEPTION_MONITOR_ENA IBUS busy monitor enable 10 1 read-write CORE_0_DRAM0_EXCEPTION_MONITOR_ENA DBUS busy monitor enbale 11 1 read-write CORE_0_INTR_RAW core0 monitor interrupt status register 0x4 0x20 CORE_0_AREA_DRAM0_0_RD_RAW Core0 dram0 area0 read monitor interrupt status 0 1 read-only CORE_0_AREA_DRAM0_0_WR_RAW Core0 dram0 area0 write monitor interrupt status 1 1 read-only CORE_0_AREA_DRAM0_1_RD_RAW Core0 dram0 area1 read monitor interrupt status 2 1 read-only CORE_0_AREA_DRAM0_1_WR_RAW Core0 dram0 area1 write monitor interrupt status 3 1 read-only CORE_0_AREA_PIF_0_RD_RAW Core0 PIF area0 read monitor interrupt status 4 1 read-only CORE_0_AREA_PIF_0_WR_RAW Core0 PIF area0 write monitor interrupt status 5 1 read-only CORE_0_AREA_PIF_1_RD_RAW Core0 PIF area1 read monitor interrupt status 6 1 read-only CORE_0_AREA_PIF_1_WR_RAW Core0 PIF area1 write monitor interrupt status 7 1 read-only CORE_0_SP_SPILL_MIN_RAW Core0 stackpoint underflow monitor interrupt status 8 1 read-only CORE_0_SP_SPILL_MAX_RAW Core0 stackpoint overflow monitor interrupt status 9 1 read-only CORE_0_IRAM0_EXCEPTION_MONITOR_RAW IBUS busy monitor interrupt status 10 1 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_RAW DBUS busy monitor initerrupt status 11 1 read-only CORE_0_INTR_RLS core0 monitor interrupt enable register 0x8 0x20 CORE_0_AREA_DRAM0_0_RD_RLS Core0 dram0 area0 read monitor interrupt enable 0 1 read-write CORE_0_AREA_DRAM0_0_WR_RLS Core0 dram0 area0 write monitor interrupt enable 1 1 read-write CORE_0_AREA_DRAM0_1_RD_RLS Core0 dram0 area1 read monitor interrupt enable 2 1 read-write CORE_0_AREA_DRAM0_1_WR_RLS Core0 dram0 area1 write monitor interrupt enable 3 1 read-write CORE_0_AREA_PIF_0_RD_RLS Core0 PIF area0 read monitor interrupt enable 4 1 read-write CORE_0_AREA_PIF_0_WR_RLS Core0 PIF area0 write monitor interrupt enable 5 1 read-write CORE_0_AREA_PIF_1_RD_RLS Core0 PIF area1 read monitor interrupt enable 6 1 read-write CORE_0_AREA_PIF_1_WR_RLS Core0 PIF area1 write monitor interrupt enable 7 1 read-write CORE_0_SP_SPILL_MIN_RLS Core0 stackpoint underflow monitor interrupt enable 8 1 read-write CORE_0_SP_SPILL_MAX_RLS Core0 stackpoint overflow monitor interrupt enable 9 1 read-write CORE_0_IRAM0_EXCEPTION_MONITOR_RLS IBUS busy monitor interrupt enable 10 1 read-write CORE_0_DRAM0_EXCEPTION_MONITOR_RLS DBUS busy monitor interrupt enbale 11 1 read-write CORE_0_INTR_CLR core0 monitor interrupt clr register 0xC 0x20 CORE_0_AREA_DRAM0_0_RD_CLR Core0 dram0 area0 read monitor interrupt clr 0 1 write-only CORE_0_AREA_DRAM0_0_WR_CLR Core0 dram0 area0 write monitor interrupt clr 1 1 write-only CORE_0_AREA_DRAM0_1_RD_CLR Core0 dram0 area1 read monitor interrupt clr 2 1 write-only CORE_0_AREA_DRAM0_1_WR_CLR Core0 dram0 area1 write monitor interrupt clr 3 1 write-only CORE_0_AREA_PIF_0_RD_CLR Core0 PIF area0 read monitor interrupt clr 4 1 write-only CORE_0_AREA_PIF_0_WR_CLR Core0 PIF area0 write monitor interrupt clr 5 1 write-only CORE_0_AREA_PIF_1_RD_CLR Core0 PIF area1 read monitor interrupt clr 6 1 write-only CORE_0_AREA_PIF_1_WR_CLR Core0 PIF area1 write monitor interrupt clr 7 1 write-only CORE_0_SP_SPILL_MIN_CLR Core0 stackpoint underflow monitor interrupt clr 8 1 write-only CORE_0_SP_SPILL_MAX_CLR Core0 stackpoint overflow monitor interrupt clr 9 1 write-only CORE_0_IRAM0_EXCEPTION_MONITOR_CLR IBUS busy monitor interrupt clr 10 1 write-only CORE_0_DRAM0_EXCEPTION_MONITOR_CLR DBUS busy monitor interrupt clr 11 1 write-only CORE_0_AREA_DRAM0_0_MIN core0 dram0 region0 addr configuration register 0x10 0x20 0xFFFFFFFF CORE_0_AREA_DRAM0_0_MIN Core0 dram0 region0 start addr 0 32 read-write CORE_0_AREA_DRAM0_0_MAX core0 dram0 region0 addr configuration register 0x14 0x20 CORE_0_AREA_DRAM0_0_MAX Core0 dram0 region0 end addr 0 32 read-write CORE_0_AREA_DRAM0_1_MIN core0 dram0 region1 addr configuration register 0x18 0x20 0xFFFFFFFF CORE_0_AREA_DRAM0_1_MIN Core0 dram0 region1 start addr 0 32 read-write CORE_0_AREA_DRAM0_1_MAX core0 dram0 region1 addr configuration register 0x1C 0x20 CORE_0_AREA_DRAM0_1_MAX Core0 dram0 region1 end addr 0 32 read-write CORE_0_AREA_PIF_0_MIN core0 PIF region0 addr configuration register 0x20 0x20 0xFFFFFFFF CORE_0_AREA_PIF_0_MIN Core0 PIF region0 start addr 0 32 read-write CORE_0_AREA_PIF_0_MAX core0 PIF region0 addr configuration register 0x24 0x20 CORE_0_AREA_PIF_0_MAX Core0 PIF region0 end addr 0 32 read-write CORE_0_AREA_PIF_1_MIN core0 PIF region1 addr configuration register 0x28 0x20 0xFFFFFFFF CORE_0_AREA_PIF_1_MIN Core0 PIF region1 start addr 0 32 read-write CORE_0_AREA_PIF_1_MAX core0 PIF region1 addr configuration register 0x2C 0x20 CORE_0_AREA_PIF_1_MAX Core0 PIF region1 end addr 0 32 read-write CORE_0_AREA_PC core0 area pc status register 0x30 0x20 CORE_0_AREA_PC the stackpointer when first touch region monitor interrupt 0 32 read-only CORE_0_AREA_SP core0 area sp status register 0x34 0x20 CORE_0_AREA_SP the PC when first touch region monitor interrupt 0 32 read-only CORE_0_SP_MIN stack min value 0x38 0x20 CORE_0_SP_MIN core0 sp region configuration regsiter 0 32 read-write CORE_0_SP_MAX stack max value 0x3C 0x20 0xFFFFFFFF CORE_0_SP_MAX core0 sp pc status register 0 32 read-write CORE_0_SP_PC stack monitor pc status register 0x40 0x20 CORE_0_SP_PC This regsiter stores the PC when trigger stack monitor. 0 32 read-only CORE_0_RCD_EN record enable configuration register 0x44 0x20 CORE_0_RCD_RECORDEN Set 1 to enable record PC 0 1 read-write CORE_0_RCD_PDEBUGEN Set 1 to enable cpu pdebug function, must set this bit can get cpu PC 1 1 read-write CORE_0_RCD_PDEBUGPC record status regsiter 0x48 0x20 CORE_0_RCD_PDEBUGPC recorded PC 0 32 read-only CORE_0_RCD_PDEBUGSP record status regsiter 0x4C 0x20 CORE_0_RCD_PDEBUGSP recorded sp 0 32 read-only CORE_0_IRAM0_EXCEPTION_MONITOR_0 exception monitor status register0 0x50 0x20 CORE_0_IRAM0_RECORDING_ADDR_0 reg_core_0_iram0_recording_addr_0 0 24 read-only CORE_0_IRAM0_RECORDING_WR_0 reg_core_0_iram0_recording_wr_0 24 1 read-only CORE_0_IRAM0_RECORDING_LOADSTORE_0 reg_core_0_iram0_recording_loadstore_0 25 1 read-only CORE_0_IRAM0_EXCEPTION_MONITOR_1 exception monitor status register1 0x54 0x20 CORE_0_IRAM0_RECORDING_ADDR_1 reg_core_0_iram0_recording_addr_1 0 24 read-only CORE_0_IRAM0_RECORDING_WR_1 reg_core_0_iram0_recording_wr_1 24 1 read-only CORE_0_IRAM0_RECORDING_LOADSTORE_1 reg_core_0_iram0_recording_loadstore_1 25 1 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_0 exception monitor status register2 0x58 0x20 CORE_0_DRAM0_RECORDING_ADDR_0 reg_core_0_dram0_recording_addr_0 0 24 read-only CORE_0_DRAM0_RECORDING_WR_0 reg_core_0_dram0_recording_wr_0 24 1 read-only CORE_0_DRAM0_RECORDING_BYTEEN_0 reg_core_0_dram0_recording_byteen_0 25 4 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_1 exception monitor status register3 0x5C 0x20 CORE_0_DRAM0_RECORDING_PC_0 reg_core_0_dram0_recording_pc_0 0 32 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_2 exception monitor status register4 0x60 0x20 CORE_0_DRAM0_RECORDING_ADDR_1 reg_core_0_dram0_recording_addr_1 0 24 read-only CORE_0_DRAM0_RECORDING_WR_1 reg_core_0_dram0_recording_wr_1 24 1 read-only CORE_0_DRAM0_RECORDING_BYTEEN_1 reg_core_0_dram0_recording_byteen_1 25 4 read-only CORE_0_DRAM0_EXCEPTION_MONITOR_3 exception monitor status register5 0x64 0x20 CORE_0_DRAM0_RECORDING_PC_1 reg_core_0_dram0_recording_pc_1 0 32 read-only CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 exception monitor status register6 0x68 0x20 CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 reg_core_x_iram0_dram0_limit_cycle_0 0 20 read-write CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 exception monitor status register7 0x6C 0x20 CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 reg_core_x_iram0_dram0_limit_cycle_1 0 20 read-write C0RE_0_LASTPC_BEFORE_EXCEPTION cpu status register 0x70 0x20 CORE_0_LASTPC_BEFORE_EXC cpu's lastpc before exception 0 32 read-only C0RE_0_DEBUG_MODE cpu status register 0x74 0x20 CORE_0_DEBUG_MODE cpu debug mode status, 1 means cpu enter debug mode. 0 1 read-only CORE_0_DEBUG_MODULE_ACTIVE cpu debug_module active status 1 1 read-only CLOCK_GATE clock register 0x78 0x20 0x00000001 CLK_EN Set 1 force on the clock gate 0 1 read-write DATE version register 0x3FC 0x20 0x02109130 ASSIST_DEBUG_DATE version register 0 28 read-write GDMA DMA (Direct Memory Access) Controller DMA 0x6003F000 0x0 0x1A4 registers DMA_CH0 44 DMA_CH1 45 3 0x10 IN_INT_RAW_CH%s Raw status interrupt of channel 0 0x0 0x20 IN_DONE_CH_INT_RAW The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 read-only IN_SUC_EOF_CH_INT_RAW The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 read-only IN_ERR_EOF_CH_INT_RAW The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. 2 1 read-only IN_DSCR_ERR_CH_INT_RAW The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. 3 1 read-only IN_DSCR_EMPTY_CH_INT_RAW The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. 4 1 read-only INFIFO_OVF_CH_INT_RAW This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 5 1 read-only INFIFO_UDF_CH_INT_RAW This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 6 1 read-only 3 0x10 IN_INT_ST_CH%s Masked interrupt of channel 0 0x4 0x20 IN_DONE_CH_INT_ST The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only IN_SUC_EOF_CH_INT_ST The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only IN_ERR_EOF_CH_INT_ST The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only IN_DSCR_ERR_CH_INT_ST The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-only IN_DSCR_EMPTY_CH_INT_ST The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 read-only INFIFO_OVF_CH_INT_ST The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 5 1 read-only INFIFO_UDF_CH_INT_ST The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 6 1 read-only 3 0x10 IN_INT_ENA_CH%s Interrupt enable bits of channel 0 0x8 0x20 IN_DONE_CH_INT_ENA The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write IN_SUC_EOF_CH_INT_ENA The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write IN_ERR_EOF_CH_INT_ENA The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write IN_DSCR_ERR_CH_INT_ENA The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 3 1 read-write IN_DSCR_EMPTY_CH_INT_ENA The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 read-write INFIFO_OVF_CH_INT_ENA The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 5 1 read-write INFIFO_UDF_CH_INT_ENA The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 6 1 read-write 3 0x10 IN_INT_CLR_CH%s Interrupt clear bits of channel 0 0xC 0x20 IN_DONE_CH_INT_CLR Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only IN_SUC_EOF_CH_INT_CLR Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only IN_ERR_EOF_CH_INT_CLR Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only IN_DSCR_ERR_CH_INT_CLR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 3 1 write-only IN_DSCR_EMPTY_CH_INT_CLR Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 4 1 write-only INFIFO_OVF_CH_INT_CLR Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 5 1 write-only INFIFO_UDF_CH_INT_CLR Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 6 1 write-only 3 0x10 OUT_INT_RAW_CH%s Raw status interrupt of channel 0 0x30 0x20 OUT_DONE_CH_INT_RAW The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 0 1 read-only OUT_EOF_CH_INT_RAW The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 1 1 read-only OUT_DSCR_ERR_CH_INT_RAW The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. 2 1 read-only OUT_TOTAL_EOF_CH_INT_RAW The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 3 1 read-only OUTFIFO_OVF_CH_INT_RAW This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 4 1 read-only OUTFIFO_UDF_CH_INT_RAW This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 5 1 read-only 3 0x10 OUT_INT_ST_CH%s Masked interrupt of channel 0 0x34 0x20 OUT_DONE_CH_INT_ST The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 0 1 read-only OUT_EOF_CH_INT_ST The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 1 1 read-only OUT_DSCR_ERR_CH_INT_ST The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-only OUT_TOTAL_EOF_CH_INT_ST The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-only OUTFIFO_OVF_CH_INT_ST The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-only OUTFIFO_UDF_CH_INT_ST The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 read-only 3 0x10 OUT_INT_ENA_CH%s Interrupt enable bits of channel 0 0x38 0x20 OUT_DONE_CH_INT_ENA The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 0 1 read-write OUT_EOF_CH_INT_ENA The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 1 1 read-write OUT_DSCR_ERR_CH_INT_ENA The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 2 1 read-write OUT_TOTAL_EOF_CH_INT_ENA The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 read-write OUTFIFO_OVF_CH_INT_ENA The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 read-write OUTFIFO_UDF_CH_INT_ENA The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 read-write 3 0x10 OUT_INT_CLR_CH%s Interrupt clear bits of channel 0 0x3C 0x20 OUT_DONE_CH_INT_CLR Set this bit to clear the OUT_DONE_CH_INT interrupt. 0 1 write-only OUT_EOF_CH_INT_CLR Set this bit to clear the OUT_EOF_CH_INT interrupt. 1 1 write-only OUT_DSCR_ERR_CH_INT_CLR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 2 1 write-only OUT_TOTAL_EOF_CH_INT_CLR Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 3 1 write-only OUTFIFO_OVF_CH_INT_CLR Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 4 1 write-only OUTFIFO_UDF_CH_INT_CLR Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 5 1 write-only AHB_TEST reserved 0x60 0x20 AHB_TESTMODE reserved 0 3 read-write AHB_TESTADDR reserved 4 2 read-write MISC_CONF MISC register 0x64 0x20 AHBM_RST_INTER Set this bit then clear this bit to reset the internal ahb FSM. 0 1 read-write ARB_PRI_DIS Set this bit to disable priority arbitration function. 2 1 read-write CLK_EN 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. 3 1 read-write DATE Version control register 0x68 0x20 0x02202250 DATE register version. 0 32 read-write 3 0xC0 IN_CONF0_CH%s Configure 0 register of Rx channel 0 0x70 0x20 IN_RST_CH This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write IN_LOOP_TEST_CH reserved 1 1 read-write INDSCR_BURST_EN_CH Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write IN_DATA_BURST_EN_CH Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write MEM_TRANS_EN_CH Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 read-write IN_ETM_EN_CH Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task. 5 1 read-write 3 0xC0 IN_CONF1_CH%s Configure 1 register of Rx channel 0 0x74 0x20 IN_CHECK_OWNER_CH Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write 3 0xC0 INFIFO_STATUS_CH%s Receive FIFO status of Rx channel 0 0x78 0x20 0x07800003 INFIFO_FULL_CH L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only INFIFO_EMPTY_CH L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only INFIFO_CNT_CH The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 2 6 read-only IN_REMAIN_UNDER_1B_CH reserved 23 1 read-only IN_REMAIN_UNDER_2B_CH reserved 24 1 read-only IN_REMAIN_UNDER_3B_CH reserved 25 1 read-only IN_REMAIN_UNDER_4B_CH reserved 26 1 read-only IN_BUF_HUNGRY_CH reserved 27 1 read-only 3 0xC0 IN_POP_CH%s Pop control register of Rx channel 0 0x7C 0x20 0x00000800 INFIFO_RDATA_CH This register stores the data popping from DMA FIFO. 0 12 read-only INFIFO_POP_CH Set this bit to pop data from DMA FIFO. 12 1 write-only 3 0xC0 IN_LINK_CH%s Link descriptor configure and control register of Rx channel 0 0x80 0x20 0x01100000 INLINK_ADDR_CH This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write INLINK_AUTO_RET_CH Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data. 20 1 read-write INLINK_STOP_CH Set this bit to stop dealing with the inlink descriptors. 21 1 write-only INLINK_START_CH Set this bit to start dealing with the inlink descriptors. 22 1 write-only INLINK_RESTART_CH Set this bit to mount a new inlink descriptor. 23 1 write-only INLINK_PARK_CH 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 read-only 3 0xC0 IN_STATE_CH%s Receive status of Rx channel 0 0x84 0x20 INLINK_DSCR_ADDR_CH This register stores the current inlink descriptor's address. 0 18 read-only IN_DSCR_STATE_CH reserved 18 2 read-only IN_STATE_CH reserved 20 3 read-only 3 0xC0 IN_SUC_EOF_DES_ADDR_CH%s Inlink descriptor address when EOF occurs of Rx channel 0 0x88 0x20 IN_SUC_EOF_DES_ADDR_CH This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only 3 0xC0 IN_ERR_EOF_DES_ADDR_CH%s Inlink descriptor address when errors occur of Rx channel 0 0x8C 0x20 IN_ERR_EOF_DES_ADDR_CH This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 read-only 3 0xC0 IN_DSCR_CH%s Current inlink descriptor address of Rx channel 0 0x90 0x20 INLINK_DSCR_CH The address of the current inlink descriptor x. 0 32 read-only 3 0xC0 IN_DSCR_BF0_CH%s The last inlink descriptor address of Rx channel 0 0x94 0x20 INLINK_DSCR_BF0_CH The address of the last inlink descriptor x-1. 0 32 read-only 3 0xC0 IN_DSCR_BF1_CH%s The second-to-last inlink descriptor address of Rx channel 0 0x98 0x20 INLINK_DSCR_BF1_CH The address of the second-to-last inlink descriptor x-2. 0 32 read-only 3 0xC0 IN_PRI_CH%s Priority register of Rx channel 0 0x9C 0x20 RX_PRI_CH The priority of Rx channel 0. The larger of the value the higher of the priority. 0 4 read-write 3 0xC0 IN_PERI_SEL_CH%s Peripheral selection of Rx channel 0 0xA0 0x20 0x0000003F PERI_IN_SEL_CH This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy 0 6 read-write 3 0xC0 OUT_CONF1_CH%s Configure 1 register of Tx channel 0 0xD4 0x20 OUT_CHECK_OWNER_CH Set this bit to enable checking the owner attribute of the link descriptor. 12 1 read-write 3 0xC0 OUTFIFO_STATUS_CH%s Transmit FIFO status of Tx channel 0 0xD8 0x20 0x07800002 OUTFIFO_FULL_CH L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only OUTFIFO_EMPTY_CH L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only OUTFIFO_CNT_CH The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 2 6 read-only OUT_REMAIN_UNDER_1B_CH reserved 23 1 read-only OUT_REMAIN_UNDER_2B_CH reserved 24 1 read-only OUT_REMAIN_UNDER_3B_CH reserved 25 1 read-only OUT_REMAIN_UNDER_4B_CH reserved 26 1 read-only 3 0xC0 OUT_PUSH_CH%s Push control register of Rx channel 0 0xDC 0x20 OUTFIFO_WDATA_CH This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write OUTFIFO_PUSH_CH Set this bit to push data into DMA FIFO. 9 1 write-only 3 0xC0 OUT_LINK_CH%s Link descriptor configure and control register of Tx channel 0 0xE0 0x20 0x00800000 OUTLINK_ADDR_CH This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write OUTLINK_STOP_CH Set this bit to stop dealing with the outlink descriptors. 20 1 write-only OUTLINK_START_CH Set this bit to start dealing with the outlink descriptors. 21 1 write-only OUTLINK_RESTART_CH Set this bit to restart a new outlink from the last address. 22 1 write-only OUTLINK_PARK_CH 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 read-only 3 0xC0 OUT_STATE_CH%s Transmit status of Tx channel 0 0xE4 0x20 OUTLINK_DSCR_ADDR_CH This register stores the current outlink descriptor's address. 0 18 read-only OUT_DSCR_STATE_CH reserved 18 2 read-only OUT_STATE_CH reserved 20 3 read-only 3 0xC0 OUT_EOF_DES_ADDR_CH%s Outlink descriptor address when EOF occurs of Tx channel 0 0xE8 0x20 OUT_EOF_DES_ADDR_CH This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 read-only 3 0xC0 OUT_EOF_BFR_DES_ADDR_CH%s The last outlink descriptor address when EOF occurs of Tx channel 0 0xEC 0x20 OUT_EOF_BFR_DES_ADDR_CH This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 read-only 3 0xC0 OUT_DSCR_CH%s Current inlink descriptor address of Tx channel 0 0xF0 0x20 OUTLINK_DSCR_CH The address of the current outlink descriptor y. 0 32 read-only 3 0xC0 OUT_DSCR_BF0_CH%s The last inlink descriptor address of Tx channel 0 0xF4 0x20 OUTLINK_DSCR_BF0_CH The address of the last outlink descriptor y-1. 0 32 read-only 3 0xC0 OUT_DSCR_BF1_CH%s The second-to-last inlink descriptor address of Tx channel 0 0xF8 0x20 OUTLINK_DSCR_BF1_CH The address of the second-to-last inlink descriptor x-2. 0 32 read-only 3 0xC0 OUT_PRI_CH%s Priority register of Tx channel 0. 0xFC 0x20 TX_PRI_CH The priority of Tx channel 0. The larger of the value the higher of the priority. 0 4 read-write 3 0xC0 OUT_PERI_SEL_CH%s Peripheral selection of Tx channel 0 0x100 0x20 0x0000003F PERI_OUT_SEL_CH This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy 0 6 read-write 2 0xC0 OUT_CONF0_CH%s Configure 0 register of Tx channel 1 0x190 0x20 0x00000008 OUT_RST_CH This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. 0 1 read-write OUT_LOOP_TEST_CH reserved 1 1 read-write OUT_AUTO_WRBACK_CH Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write OUT_EOF_MODE_CH EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write OUTDSCR_BURST_EN_CH Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. 4 1 read-write OUT_DATA_BURST_EN_CH Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. 5 1 read-write OUT_ETM_EN_CH Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task. 6 1 read-write DS Digital Signature DS 0x6008C000 0x0 0xA5C registers 512 0x1 Y_MEM[%s] memory that stores Y 0x0 0x8 512 0x1 M_MEM[%s] memory that stores M 0x200 0x8 512 0x1 RB_MEM[%s] memory that stores Rb 0x400 0x8 48 0x1 BOX_MEM[%s] memory that stores BOX 0x600 0x8 16 0x1 IV_MEM[%s] memory that stores IV 0x630 0x8 512 0x1 X_MEM[%s] memory that stores X 0x800 0x8 512 0x1 Z_MEM[%s] memory that stores Z 0xA00 0x8 SET_START DS start control register 0xE00 0x20 SET_START set this bit to start DS operation. 0 1 write-only SET_CONTINUE DS continue control register 0xE04 0x20 SET_CONTINUE set this bit to continue DS operation. 0 1 write-only SET_FINISH DS finish control register 0xE08 0x20 SET_FINISH Set this bit to finish DS process. 0 1 write-only QUERY_BUSY DS query busy register 0xE0C 0x20 QUERY_BUSY digital signature state. 1'b0: idle, 1'b1: busy 0 1 read-only QUERY_KEY_WRONG DS query key-wrong counter register 0xE10 0x20 QUERY_KEY_WRONG digital signature key wrong counter 0 4 read-only QUERY_CHECK DS query check result register 0xE14 0x20 MD_ERROR MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail 0 1 read-only PADDING_BAD padding checkout result. 1'b0: a good padding, 1'b1: a bad padding 1 1 read-only DATE DS version control register 0xE20 0x20 0x20200618 DATE ds version information 0 30 read-write ECC ECC (ECC Hardware Accelerator) ECC 0x60039000 0x0 0x78 registers MULT_INT_RAW ECC interrupt raw register, valid in level. 0xC 0x20 CALC_DONE_INT_RAW The raw interrupt status bit for the ecc_calc_done_int interrupt 0 1 read-only MULT_INT_ST ECC interrupt status register. 0x10 0x20 CALC_DONE_INT_ST The masked interrupt status bit for the ecc_calc_done_int interrupt 0 1 read-only MULT_INT_ENA ECC interrupt enable register. 0x14 0x20 CALC_DONE_INT_ENA The interrupt enable bit for the ecc_calc_done_int interrupt 0 1 read-write MULT_INT_CLR ECC interrupt clear register. 0x18 0x20 CALC_DONE_INT_CLR Set this bit to clear the ecc_calc_done_int interrupt 0 1 write-only MULT_CONF ECC configure register 0x1C 0x20 0x80000000 START Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. 0 1 read-write RESET Write 1 to reset ECC Accelerator. 1 1 write-only KEY_LENGTH The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256. 2 1 read-write MOD_BASE The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve) 3 1 read-write WORK_MODE The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division. 4 4 read-write SECURITY_MODE Reserved 8 1 read-write VERIFICATION_RESULT The verification result bit of ECC Accelerator, only valid when calculation is done. 29 1 read-only CLK_EN Write 1 to force on register clock gate. 30 1 read-write MEM_CLOCK_GATE_FORCE_ON ECC memory clock gate force on register 31 1 read-write MULT_DATE Version control register 0xFC 0x20 0x02207180 DATE ECC mult version control register 0 28 read-write 32 0x1 K_MEM[%s] The memory that stores k. 0x100 0x8 32 0x1 PX_MEM[%s] The memory that stores Px. 0x120 0x8 32 0x1 PY_MEM[%s] The memory that stores Py. 0x140 0x8 EFUSE eFuse Controller EFUSE 0x6001A000 0x0 0x1D0 registers EFUSE 24 PGM_DATA0 Register 0 that stores data to be programmed. 0x0 0x20 PGM_DATA_0 Configures the 0th 32-bit data to be programmed. 0 32 read-write PGM_DATA1 Register 1 that stores data to be programmed. 0x4 0x20 PGM_DATA_1 Configures the 1st 32-bit data to be programmed. 0 32 read-write PGM_DATA2 Register 2 that stores data to be programmed. 0x8 0x20 PGM_DATA_2 Configures the 2nd 32-bit data to be programmed. 0 32 read-write PGM_DATA3 Register 3 that stores data to be programmed. 0xC 0x20 PGM_DATA_3 Configures the 3rd 32-bit data to be programmed. 0 32 read-write PGM_DATA4 Register 4 that stores data to be programmed. 0x10 0x20 PGM_DATA_4 Configures the 4th 32-bit data to be programmed. 0 32 read-write PGM_DATA5 Register 5 that stores data to be programmed. 0x14 0x20 PGM_DATA_5 Configures the 5th 32-bit data to be programmed. 0 32 read-write PGM_DATA6 Register 6 that stores data to be programmed. 0x18 0x20 PGM_DATA_6 Configures the 6th 32-bit data to be programmed. 0 32 read-write PGM_DATA7 Register 7 that stores data to be programmed. 0x1C 0x20 PGM_DATA_7 Configures the 7th 32-bit data to be programmed. 0 32 read-write PGM_CHECK_VALUE0 Register 0 that stores the RS code to be programmed. 0x20 0x20 PGM_RS_DATA_0 Configures the 0th 32-bit RS code to be programmed. 0 32 read-write PGM_CHECK_VALUE1 Register 1 that stores the RS code to be programmed. 0x24 0x20 PGM_RS_DATA_1 Configures the 1st 32-bit RS code to be programmed. 0 32 read-write PGM_CHECK_VALUE2 Register 2 that stores the RS code to be programmed. 0x28 0x20 PGM_RS_DATA_2 Configures the 2nd 32-bit RS code to be programmed. 0 32 read-write RD_WR_DIS BLOCK0 data register 0. 0x2C 0x20 WR_DIS Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled. 0 32 read-only RD_REPEAT_DATA0 BLOCK0 data register 1. 0x30 0x20 RD_DIS Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled. 0 7 read-only RPT4_RESERVED0_4 Reserved. 7 1 read-only DIS_ICACHE Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. 8 1 read-only DIS_USB_JTAG Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled. 9 1 read-only POWERGLITCH_EN Represents whether power glitch function is enabled. 1: enabled. 0: disabled. 10 1 read-only DIS_USB_SERIAL_JTAG Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. 11 1 read-only DIS_FORCE_DOWNLOAD Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled. 12 1 read-only SPI_DOWNLOAD_MSPI_DIS Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled. 13 1 read-only DIS_CAN Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. 14 1 read-only JTAG_SEL_ENABLE Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled. 15 1 read-only SOFT_DIS_JTAG Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled. 16 3 read-only DIS_PAD_JTAG Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled. 19 1 read-only DIS_DOWNLOAD_MANUAL_ENCRYPT Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled. 20 1 read-only USB_DREFH Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. 21 2 read-only USB_DREFL Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. 23 2 read-only USB_EXCHG_PINS Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. 25 1 read-only VDD_SPI_AS_GPIO Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned. 26 1 read-only RPT4_RESERVED0_2 Reserved. 27 2 read-only RPT4_RESERVED0_1 Reserved. 29 1 read-only RPT4_RESERVED0_0 Reserved. 30 2 read-only RD_REPEAT_DATA1 BLOCK0 data register 2. 0x34 0x20 RPT4_RESERVED1_1 Reserved. 0 16 read-only WDT_DELAY_SEL Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected. 16 2 read-only SPI_BOOT_CRYPT_CNT Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled. 18 3 read-only SECURE_BOOT_KEY_REVOKE0 Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled. 21 1 read-only SECURE_BOOT_KEY_REVOKE1 Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled. 22 1 read-only SECURE_BOOT_KEY_REVOKE2 Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled. 23 1 read-only KEY_PURPOSE_0 Represents the purpose of Key0. 24 4 read-only KEY_PURPOSE_1 Represents the purpose of Key1. 28 4 read-only RD_REPEAT_DATA2 BLOCK0 data register 3. 0x38 0x20 0x000C0000 KEY_PURPOSE_2 Represents the purpose of Key2. 0 4 read-only KEY_PURPOSE_3 Represents the purpose of Key3. 4 4 read-only KEY_PURPOSE_4 Represents the purpose of Key4. 8 4 read-only KEY_PURPOSE_5 Represents the purpose of Key5. 12 4 read-only SEC_DPA_LEVEL Represents the spa secure level by configuring the clock random divide mode. 16 2 read-only ECDSA_FORCE_USE_HARDWARE_K Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used. 18 1 read-only CRYPT_DPA_ENABLE Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. 19 1 read-only SECURE_BOOT_EN Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. 20 1 read-only SECURE_BOOT_AGGRESSIVE_REVOKE Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled. 21 1 read-only RPT4_RESERVED2_0 Reserved. 22 6 read-only FLASH_TPUW Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value. 28 4 read-only RD_REPEAT_DATA3 BLOCK0 data register 4. 0x3C 0x20 DIS_DOWNLOAD_MODE Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. 0 1 read-only DIS_DIRECT_BOOT Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. 1 1 read-only DIS_USB_PRINT Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. 2 1 read-only RPT4_RESERVED3_5 Reserved. 3 1 read-only DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled. 4 1 read-only ENABLE_SECURITY_DOWNLOAD Represents whether security download is enabled or disabled. 1: enabled. 0: disabled. 5 1 read-only UART_PRINT_CONTROL Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing. 6 2 read-only FORCE_SEND_RESUME Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced. 8 1 read-only SECURE_VERSION Represents the version used by ESP-IDF anti-rollback feature. 9 16 read-only SECURE_BOOT_DISABLE_FAST_WAKE Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled. 25 1 read-only HYS_EN_PAD0 Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. 26 6 read-only RD_REPEAT_DATA4 BLOCK0 data register 5. 0x40 0x20 HYS_EN_PAD1 Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled. 0 22 read-only RPT4_RESERVED4_1 Reserved. 22 2 read-only RPT4_RESERVED4_0 Reserved. 24 8 read-only RD_MAC_SYS_0 BLOCK1 data register $n. 0x44 0x20 MAC_0 Stores the low 32 bits of MAC address. 0 32 read-only RD_MAC_SYS_1 BLOCK1 data register $n. 0x48 0x20 MAC_1 Stores the high 16 bits of MAC address. 0 16 read-only MAC_EXT Stores the extended bits of MAC address. 16 16 read-only RD_MAC_SYS_2 BLOCK1 data register $n. 0x4C 0x20 MAC_RESERVED_1 Reserved. 0 14 read-only MAC_RESERVED_0 Reserved. 14 18 read-only RD_MAC_SYS_3 BLOCK1 data register $n. 0x50 0x20 MAC_RESERVED_2 Reserved. 0 18 read-only SYS_DATA_PART0_0 Stores the first 14 bits of the zeroth part of system data. 18 14 read-only RD_MAC_SYS_4 BLOCK1 data register $n. 0x54 0x20 SYS_DATA_PART0_1 Stores the first 32 bits of the zeroth part of system data. 0 32 read-only RD_MAC_SYS_5 BLOCK1 data register $n. 0x58 0x20 SYS_DATA_PART0_2 Stores the second 32 bits of the zeroth part of system data. 0 32 read-only RD_SYS_PART1_DATA0 Register $n of BLOCK2 (system). 0x5C 0x20 SYS_DATA_PART1_0 Stores the zeroth 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA1 Register $n of BLOCK2 (system). 0x60 0x20 SYS_DATA_PART1_1 Stores the first 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA2 Register $n of BLOCK2 (system). 0x64 0x20 SYS_DATA_PART1_2 Stores the second 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA3 Register $n of BLOCK2 (system). 0x68 0x20 SYS_DATA_PART1_3 Stores the third 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA4 Register $n of BLOCK2 (system). 0x6C 0x20 SYS_DATA_PART1_4 Stores the fourth 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA5 Register $n of BLOCK2 (system). 0x70 0x20 SYS_DATA_PART1_5 Stores the fifth 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA6 Register $n of BLOCK2 (system). 0x74 0x20 SYS_DATA_PART1_6 Stores the sixth 32 bits of the first part of system data. 0 32 read-only RD_SYS_PART1_DATA7 Register $n of BLOCK2 (system). 0x78 0x20 SYS_DATA_PART1_7 Stores the seventh 32 bits of the first part of system data. 0 32 read-only RD_USR_DATA0 Register $n of BLOCK3 (user). 0x7C 0x20 USR_DATA0 Stores the zeroth 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA1 Register $n of BLOCK3 (user). 0x80 0x20 USR_DATA1 Stores the first 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA2 Register $n of BLOCK3 (user). 0x84 0x20 USR_DATA2 Stores the second 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA3 Register $n of BLOCK3 (user). 0x88 0x20 USR_DATA3 Stores the third 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA4 Register $n of BLOCK3 (user). 0x8C 0x20 USR_DATA4 Stores the fourth 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA5 Register $n of BLOCK3 (user). 0x90 0x20 USR_DATA5 Stores the fifth 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA6 Register $n of BLOCK3 (user). 0x94 0x20 USR_DATA6 Stores the sixth 32 bits of BLOCK3 (user). 0 32 read-only RD_USR_DATA7 Register $n of BLOCK3 (user). 0x98 0x20 USR_DATA7 Stores the seventh 32 bits of BLOCK3 (user). 0 32 read-only RD_KEY0_DATA0 Register $n of BLOCK4 (KEY0). 0x9C 0x20 KEY0_DATA0 Stores the zeroth 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA1 Register $n of BLOCK4 (KEY0). 0xA0 0x20 KEY0_DATA1 Stores the first 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA2 Register $n of BLOCK4 (KEY0). 0xA4 0x20 KEY0_DATA2 Stores the second 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA3 Register $n of BLOCK4 (KEY0). 0xA8 0x20 KEY0_DATA3 Stores the third 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA4 Register $n of BLOCK4 (KEY0). 0xAC 0x20 KEY0_DATA4 Stores the fourth 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA5 Register $n of BLOCK4 (KEY0). 0xB0 0x20 KEY0_DATA5 Stores the fifth 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA6 Register $n of BLOCK4 (KEY0). 0xB4 0x20 KEY0_DATA6 Stores the sixth 32 bits of KEY0. 0 32 read-only RD_KEY0_DATA7 Register $n of BLOCK4 (KEY0). 0xB8 0x20 KEY0_DATA7 Stores the seventh 32 bits of KEY0. 0 32 read-only RD_KEY1_DATA0 Register $n of BLOCK5 (KEY1). 0xBC 0x20 KEY1_DATA0 Stores the zeroth 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA1 Register $n of BLOCK5 (KEY1). 0xC0 0x20 KEY1_DATA1 Stores the first 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA2 Register $n of BLOCK5 (KEY1). 0xC4 0x20 KEY1_DATA2 Stores the second 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA3 Register $n of BLOCK5 (KEY1). 0xC8 0x20 KEY1_DATA3 Stores the third 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA4 Register $n of BLOCK5 (KEY1). 0xCC 0x20 KEY1_DATA4 Stores the fourth 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA5 Register $n of BLOCK5 (KEY1). 0xD0 0x20 KEY1_DATA5 Stores the fifth 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA6 Register $n of BLOCK5 (KEY1). 0xD4 0x20 KEY1_DATA6 Stores the sixth 32 bits of KEY1. 0 32 read-only RD_KEY1_DATA7 Register $n of BLOCK5 (KEY1). 0xD8 0x20 KEY1_DATA7 Stores the seventh 32 bits of KEY1. 0 32 read-only RD_KEY2_DATA0 Register $n of BLOCK6 (KEY2). 0xDC 0x20 KEY2_DATA0 Stores the zeroth 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA1 Register $n of BLOCK6 (KEY2). 0xE0 0x20 KEY2_DATA1 Stores the first 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA2 Register $n of BLOCK6 (KEY2). 0xE4 0x20 KEY2_DATA2 Stores the second 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA3 Register $n of BLOCK6 (KEY2). 0xE8 0x20 KEY2_DATA3 Stores the third 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA4 Register $n of BLOCK6 (KEY2). 0xEC 0x20 KEY2_DATA4 Stores the fourth 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA5 Register $n of BLOCK6 (KEY2). 0xF0 0x20 KEY2_DATA5 Stores the fifth 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA6 Register $n of BLOCK6 (KEY2). 0xF4 0x20 KEY2_DATA6 Stores the sixth 32 bits of KEY2. 0 32 read-only RD_KEY2_DATA7 Register $n of BLOCK6 (KEY2). 0xF8 0x20 KEY2_DATA7 Stores the seventh 32 bits of KEY2. 0 32 read-only RD_KEY3_DATA0 Register $n of BLOCK7 (KEY3). 0xFC 0x20 KEY3_DATA0 Stores the zeroth 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA1 Register $n of BLOCK7 (KEY3). 0x100 0x20 KEY3_DATA1 Stores the first 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA2 Register $n of BLOCK7 (KEY3). 0x104 0x20 KEY3_DATA2 Stores the second 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA3 Register $n of BLOCK7 (KEY3). 0x108 0x20 KEY3_DATA3 Stores the third 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA4 Register $n of BLOCK7 (KEY3). 0x10C 0x20 KEY3_DATA4 Stores the fourth 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA5 Register $n of BLOCK7 (KEY3). 0x110 0x20 KEY3_DATA5 Stores the fifth 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA6 Register $n of BLOCK7 (KEY3). 0x114 0x20 KEY3_DATA6 Stores the sixth 32 bits of KEY3. 0 32 read-only RD_KEY3_DATA7 Register $n of BLOCK7 (KEY3). 0x118 0x20 KEY3_DATA7 Stores the seventh 32 bits of KEY3. 0 32 read-only RD_KEY4_DATA0 Register $n of BLOCK8 (KEY4). 0x11C 0x20 KEY4_DATA0 Stores the zeroth 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA1 Register $n of BLOCK8 (KEY4). 0x120 0x20 KEY4_DATA1 Stores the first 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA2 Register $n of BLOCK8 (KEY4). 0x124 0x20 KEY4_DATA2 Stores the second 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA3 Register $n of BLOCK8 (KEY4). 0x128 0x20 KEY4_DATA3 Stores the third 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA4 Register $n of BLOCK8 (KEY4). 0x12C 0x20 KEY4_DATA4 Stores the fourth 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA5 Register $n of BLOCK8 (KEY4). 0x130 0x20 KEY4_DATA5 Stores the fifth 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA6 Register $n of BLOCK8 (KEY4). 0x134 0x20 KEY4_DATA6 Stores the sixth 32 bits of KEY4. 0 32 read-only RD_KEY4_DATA7 Register $n of BLOCK8 (KEY4). 0x138 0x20 KEY4_DATA7 Stores the seventh 32 bits of KEY4. 0 32 read-only RD_KEY5_DATA0 Register $n of BLOCK9 (KEY5). 0x13C 0x20 KEY5_DATA0 Stores the zeroth 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA1 Register $n of BLOCK9 (KEY5). 0x140 0x20 KEY5_DATA1 Stores the first 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA2 Register $n of BLOCK9 (KEY5). 0x144 0x20 KEY5_DATA2 Stores the second 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA3 Register $n of BLOCK9 (KEY5). 0x148 0x20 KEY5_DATA3 Stores the third 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA4 Register $n of BLOCK9 (KEY5). 0x14C 0x20 KEY5_DATA4 Stores the fourth 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA5 Register $n of BLOCK9 (KEY5). 0x150 0x20 KEY5_DATA5 Stores the fifth 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA6 Register $n of BLOCK9 (KEY5). 0x154 0x20 KEY5_DATA6 Stores the sixth 32 bits of KEY5. 0 32 read-only RD_KEY5_DATA7 Register $n of BLOCK9 (KEY5). 0x158 0x20 KEY5_DATA7 Stores the seventh 32 bits of KEY5. 0 32 read-only RD_SYS_PART2_DATA0 Register $n of BLOCK10 (system). 0x15C 0x20 SYS_DATA_PART2_0 Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA1 Register $n of BLOCK9 (KEY5). 0x160 0x20 SYS_DATA_PART2_1 Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA2 Register $n of BLOCK10 (system). 0x164 0x20 SYS_DATA_PART2_2 Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA3 Register $n of BLOCK10 (system). 0x168 0x20 SYS_DATA_PART2_3 Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA4 Register $n of BLOCK10 (system). 0x16C 0x20 SYS_DATA_PART2_4 Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA5 Register $n of BLOCK10 (system). 0x170 0x20 SYS_DATA_PART2_5 Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA6 Register $n of BLOCK10 (system). 0x174 0x20 SYS_DATA_PART2_6 Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only RD_SYS_PART2_DATA7 Register $n of BLOCK10 (system). 0x178 0x20 SYS_DATA_PART2_7 Stores the 0th 32 bits of the 2nd part of system data. 0 32 read-only RD_REPEAT_ERR0 Programming error record register 0 of BLOCK0. 0x17C 0x20 RD_DIS_ERR Indicates a programming error of RD_DIS. 0 7 read-only RPT4_RESERVED0_ERR_4 Reserved. 7 1 read-only DIS_ICACHE_ERR Indicates a programming error of DIS_ICACHE. 8 1 read-only DIS_USB_JTAG_ERR Indicates a programming error of DIS_USB_JTAG. 9 1 read-only POWERGLITCH_EN_ERR Indicates a programming error of POWERGLITCH_EN. 10 1 read-only DIS_USB_SERIAL_JTAG_ERR Indicates a programming error of DIS_USB_DEVICE. 11 1 read-only DIS_FORCE_DOWNLOAD_ERR Indicates a programming error of DIS_FORCE_DOWNLOAD. 12 1 read-only SPI_DOWNLOAD_MSPI_DIS_ERR Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. 13 1 read-only DIS_TWAI_ERR Indicates a programming error of DIS_CAN. 14 1 read-only JTAG_SEL_ENABLE_ERR Indicates a programming error of JTAG_SEL_ENABLE. 15 1 read-only SOFT_DIS_JTAG_ERR Indicates a programming error of SOFT_DIS_JTAG. 16 3 read-only DIS_PAD_JTAG_ERR Indicates a programming error of DIS_PAD_JTAG. 19 1 read-only DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. 20 1 read-only USB_DREFH_ERR Indicates a programming error of USB_DREFH. 21 2 read-only USB_DREFL_ERR Indicates a programming error of USB_DREFL. 23 2 read-only USB_EXCHG_PINS_ERR Indicates a programming error of USB_EXCHG_PINS. 25 1 read-only VDD_SPI_AS_GPIO_ERR Indicates a programming error of VDD_SPI_AS_GPIO. 26 1 read-only RPT4_RESERVED0_ERR_2 Reserved. 27 2 read-only RPT4_RESERVED0_ERR_1 Reserved. 29 1 read-only RPT4_RESERVED0_ERR_0 Reserved. 30 2 read-only RD_REPEAT_ERR1 Programming error record register 1 of BLOCK0. 0x180 0x20 RPT4_RESERVED1_ERR_0 Reserved. 0 16 read-only WDT_DELAY_SEL_ERR Indicates a programming error of WDT_DELAY_SEL. 16 2 read-only SPI_BOOT_CRYPT_CNT_ERR Indicates a programming error of SPI_BOOT_CRYPT_CNT. 18 3 read-only SECURE_BOOT_KEY_REVOKE0_ERR Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. 21 1 read-only SECURE_BOOT_KEY_REVOKE1_ERR Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. 22 1 read-only SECURE_BOOT_KEY_REVOKE2_ERR Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. 23 1 read-only KEY_PURPOSE_0_ERR Indicates a programming error of KEY_PURPOSE_0. 24 4 read-only KEY_PURPOSE_1_ERR Indicates a programming error of KEY_PURPOSE_1. 28 4 read-only RD_REPEAT_ERR2 Programming error record register 2 of BLOCK0. 0x184 0x20 KEY_PURPOSE_2_ERR Indicates a programming error of KEY_PURPOSE_2. 0 4 read-only KEY_PURPOSE_3_ERR Indicates a programming error of KEY_PURPOSE_3. 4 4 read-only KEY_PURPOSE_4_ERR Indicates a programming error of KEY_PURPOSE_4. 8 4 read-only KEY_PURPOSE_5_ERR Indicates a programming error of KEY_PURPOSE_5. 12 4 read-only SEC_DPA_LEVEL_ERR Indicates a programming error of SEC_DPA_LEVEL. 16 2 read-only RPT4_RESERVED2_ERR_1 Reserved. 18 1 read-only CRYPT_DPA_ENABLE_ERR Indicates a programming error of CRYPT_DPA_ENABLE. 19 1 read-only SECURE_BOOT_EN_ERR Indicates a programming error of SECURE_BOOT_EN. 20 1 read-only SECURE_BOOT_AGGRESSIVE_REVOKE_ERR Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. 21 1 read-only RPT4_RESERVED2_ERR_0 Reserved. 22 6 read-only FLASH_TPUW_ERR Indicates a programming error of FLASH_TPUW. 28 4 read-only RD_REPEAT_ERR3 Programming error record register 3 of BLOCK0. 0x188 0x20 DIS_DOWNLOAD_MODE_ERR Indicates a programming error of DIS_DOWNLOAD_MODE. 0 1 read-only DIS_DIRECT_BOOT_ERR Indicates a programming error of DIS_DIRECT_BOOT. 1 1 read-only USB_PRINT_ERR Indicates a programming error of UART_PRINT_CHANNEL. 2 1 read-only RPT4_RESERVED3_ERR_5 Reserved. 3 1 read-only DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. 4 1 read-only ENABLE_SECURITY_DOWNLOAD_ERR Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. 5 1 read-only UART_PRINT_CONTROL_ERR Indicates a programming error of UART_PRINT_CONTROL. 6 2 read-only FORCE_SEND_RESUME_ERR Indicates a programming error of FORCE_SEND_RESUME. 8 1 read-only SECURE_VERSION_ERR Indicates a programming error of SECURE VERSION. 9 16 read-only SECURE_BOOT_DISABLE_FAST_WAKE_ERR Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. 25 1 read-only HYS_EN_PAD0_ERR Indicates a programming error of HYS_EN_PAD0. 26 6 read-only RD_REPEAT_ERR4 Programming error record register 4 of BLOCK0. 0x18C 0x20 HYS_EN_PAD1_ERR Indicates a programming error of HYS_EN_PAD1. 0 22 read-only RPT4_RESERVED4_ERR_1 Reserved. 22 2 read-only RPT4_RESERVED4_ERR_0 Reserved. 24 8 read-only RD_RS_ERR0 Programming error record register 0 of BLOCK1-10. 0x1C0 0x20 MAC_SPI_8M_ERR_NUM The value of this signal means the number of error bytes. 0 3 read-only MAC_SPI_8M_FAIL 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 3 1 read-only SYS_PART1_NUM The value of this signal means the number of error bytes. 4 3 read-only SYS_PART1_FAIL 0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 7 1 read-only USR_DATA_ERR_NUM The value of this signal means the number of error bytes. 8 3 read-only USR_DATA_FAIL 0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 11 1 read-only KEY0_ERR_NUM The value of this signal means the number of error bytes. 12 3 read-only KEY0_FAIL 0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6. 15 1 read-only KEY1_ERR_NUM The value of this signal means the number of error bytes. 16 3 read-only KEY1_FAIL 0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6. 19 1 read-only KEY2_ERR_NUM The value of this signal means the number of error bytes. 20 3 read-only KEY2_FAIL 0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6. 23 1 read-only KEY3_ERR_NUM The value of this signal means the number of error bytes. 24 3 read-only KEY3_FAIL 0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6. 27 1 read-only KEY4_ERR_NUM The value of this signal means the number of error bytes. 28 3 read-only KEY4_FAIL 0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6. 31 1 read-only RD_RS_ERR1 Programming error record register 1 of BLOCK1-10. 0x1C4 0x20 KEY5_ERR_NUM The value of this signal means the number of error bytes. 0 3 read-only KEY5_FAIL 0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6. 3 1 read-only SYS_PART2_ERR_NUM The value of this signal means the number of error bytes. 4 3 read-only SYS_PART2_FAIL 0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6. 7 1 read-only CLK eFuse clcok configuration register. 0x1C8 0x20 0x00000002 MEM_FORCE_PD Set this bit to force eFuse SRAM into power-saving mode. 0 1 read-write MEM_CLK_FORCE_ON Set this bit and force to activate clock signal of eFuse SRAM. 1 1 read-write MEM_FORCE_PU Set this bit to force eFuse SRAM into working mode. 2 1 read-write EN Set this bit to force enable eFuse register configuration clock signal. 16 1 read-write CONF eFuse operation mode configuraiton register 0x1CC 0x20 OP_CODE 0x5A5A: programming operation command 0x5AA5: read operation command. 0 16 read-write CFG_ECDSA_BLK Configures which block to use for ECDSA key output. 16 4 read-write STATUS eFuse status register. 0x1D0 0x20 STATE Indicates the state of the eFuse state machine. 0 4 read-only OTP_LOAD_SW The value of OTP_LOAD_SW. 4 1 read-only OTP_VDDQ_C_SYNC2 The value of OTP_VDDQ_C_SYNC2. 5 1 read-only OTP_STROBE_SW The value of OTP_STROBE_SW. 6 1 read-only OTP_CSB_SW The value of OTP_CSB_SW. 7 1 read-only OTP_PGENB_SW The value of OTP_PGENB_SW. 8 1 read-only OTP_VDDQ_IS_SW The value of OTP_VDDQ_IS_SW. 9 1 read-only BLK0_VALID_BIT_CNT Indicates the number of block valid bit. 10 10 read-only CUR_ECDSA_BLK Indicates which block is used for ECDSA key output. 20 4 read-only CMD eFuse command register. 0x1D4 0x20 READ_CMD Set this bit to send read command. 0 1 read-write PGM_CMD Set this bit to send programming command. 1 1 read-write BLK_NUM The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively. 2 4 read-write INT_RAW eFuse raw interrupt register. 0x1D8 0x20 READ_DONE_INT_RAW The raw bit signal for read_done interrupt. 0 1 read-only PGM_DONE_INT_RAW The raw bit signal for pgm_done interrupt. 1 1 read-only INT_ST eFuse interrupt status register. 0x1DC 0x20 READ_DONE_INT_ST The status signal for read_done interrupt. 0 1 read-only PGM_DONE_INT_ST The status signal for pgm_done interrupt. 1 1 read-only INT_ENA eFuse interrupt enable register. 0x1E0 0x20 READ_DONE_INT_ENA The enable signal for read_done interrupt. 0 1 read-write PGM_DONE_INT_ENA The enable signal for pgm_done interrupt. 1 1 read-write INT_CLR eFuse interrupt clear register. 0x1E4 0x20 READ_DONE_INT_CLR The clear signal for read_done interrupt. 0 1 write-only PGM_DONE_INT_CLR The clear signal for pgm_done interrupt. 1 1 write-only DAC_CONF Controls the eFuse programming voltage. 0x1E8 0x20 0x0001FE17 DAC_CLK_DIV Controls the division factor of the rising clock of the programming voltage. 0 8 read-write DAC_CLK_PAD_SEL Don't care. 8 1 read-write DAC_NUM Controls the rising period of the programming voltage. 9 8 read-write OE_CLR Reduces the power supply of the programming voltage. 17 1 read-write RD_TIM_CONF Configures read timing parameters. 0x1EC 0x20 0x0F010201 THR_A Configures the read hold time. 0 8 read-write TRD Configures the read time. 8 8 read-write TSUR_A Configures the read setup time. 16 8 read-write READ_INIT_NUM Configures the waiting time of reading eFuse memory. 24 8 read-write WR_TIM_CONF1 Configurarion register 1 of eFuse programming timing parameters. 0x1F0 0x20 0x01266701 TSUP_A Configures the programming setup time. 0 8 read-write PWR_ON_NUM Configures the power up time for VDDQ. 8 16 read-write THP_A Configures the programming hold time. 24 8 read-write WR_TIM_CONF2 Configurarion register 2 of eFuse programming timing parameters. 0x1F4 0x20 0x00A00140 PWR_OFF_NUM Configures the power outage time for VDDQ. 0 16 read-write TPGM Configures the active programming time. 16 16 read-write WR_TIM_CONF0_RS_BYPASS Configurarion register0 of eFuse programming time parameters and rs bypass operation. 0x1F8 0x20 0x00002000 BYPASS_RS_CORRECTION Set this bit to bypass reed solomon correction step. 0 1 read-write BYPASS_RS_BLK_NUM Configures block number of programming twice operation. 1 11 read-write UPDATE Set this bit to update multi-bit register signals. 12 1 write-only TPGM_INACTIVE Configures the inactive programming time. 13 8 read-write DATE eFuse version register. 0x1FC 0x20 0x02208120 DATE Stores eFuse version. 0 28 read-write GPIO General Purpose Input/Output GPIO 0x60004000 0x0 0x2A8 registers GPIO 16 GPIO_NMI 17 BT_SELECT GPIO bit select register 0x0 0x20 BT_SEL GPIO bit select register 0 32 read-write OUT GPIO output register for GPIO0-31 0x4 0x20 DATA_ORIG GPIO output register for GPIO0-31 0 32 read-write OUT_W1TS GPIO output set register for GPIO0-31 0x8 0x20 OUT_W1TS GPIO output set register for GPIO0-31 0 32 write-only OUT_W1TC GPIO output clear register for GPIO0-31 0xC 0x20 OUT_W1TC GPIO output clear register for GPIO0-31 0 32 write-only SDIO_SELECT GPIO sdio select register 0x1C 0x20 SDIO_SEL GPIO sdio select register 0 8 read-write ENABLE GPIO output enable register for GPIO0-31 0x20 0x20 DATA GPIO output enable register for GPIO0-31 0 32 read-write ENABLE_W1TS GPIO output enable set register for GPIO0-31 0x24 0x20 ENABLE_W1TS GPIO output enable set register for GPIO0-31 0 32 write-only ENABLE_W1TC GPIO output enable clear register for GPIO0-31 0x28 0x20 ENABLE_W1TC GPIO output enable clear register for GPIO0-31 0 32 write-only STRAP pad strapping register 0x38 0x20 STRAPPING pad strapping register 0 16 read-only IN GPIO input register for GPIO0-31 0x3C 0x20 DATA_NEXT GPIO input register for GPIO0-31 0 32 read-only STATUS GPIO interrupt status register for GPIO0-31 0x44 0x20 INTERRUPT GPIO interrupt status register for GPIO0-31 0 32 read-write STATUS_W1TS GPIO interrupt status set register for GPIO0-31 0x48 0x20 STATUS_W1TS GPIO interrupt status set register for GPIO0-31 0 32 write-only STATUS_W1TC GPIO interrupt status clear register for GPIO0-31 0x4C 0x20 STATUS_W1TC GPIO interrupt status clear register for GPIO0-31 0 32 write-only PCPU_INT GPIO PRO_CPU interrupt status register for GPIO0-31 0x5C 0x20 PROCPU_INT GPIO PRO_CPU interrupt status register for GPIO0-31 0 32 read-only PCPU_NMI_INT GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 0x60 0x20 PROCPU_NMI_INT GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 0 32 read-only CPUSDIO_INT GPIO CPUSDIO interrupt status register for GPIO0-31 0x64 0x20 SDIO_INT GPIO CPUSDIO interrupt status register for GPIO0-31 0 32 read-only 32 0x4 PIN%s GPIO pin configuration register 0x74 0x20 SYNC2_BYPASS set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 0 2 read-write PAD_DRIVER set this bit to select pad driver. 1:open-drain. 0:normal. 2 1 read-write SYNC1_BYPASS set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 3 2 read-write INT_TYPE set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level 7 3 read-write WAKEUP_ENABLE set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 10 1 read-write CONFIG reserved 11 2 read-write INT_ENA set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. 13 5 read-write STATUS_NEXT GPIO interrupt source register for GPIO0-31 0x14C 0x20 STATUS_INTERRUPT_NEXT GPIO interrupt source register for GPIO0-31 0 32 read-only FUNC0_IN_SEL_CFG GPIO input function configuration register 0x154 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC6_IN_SEL_CFG GPIO input function configuration register 0x16C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC7_IN_SEL_CFG GPIO input function configuration register 0x170 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC8_IN_SEL_CFG GPIO input function configuration register 0x174 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC9_IN_SEL_CFG GPIO input function configuration register 0x178 0x20 0x00000038 IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC10_IN_SEL_CFG GPIO input function configuration register 0x17C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC11_IN_SEL_CFG GPIO input function configuration register 0x180 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC12_IN_SEL_CFG GPIO input function configuration register 0x184 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC13_IN_SEL_CFG GPIO input function configuration register 0x188 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC14_IN_SEL_CFG GPIO input function configuration register 0x18C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC15_IN_SEL_CFG GPIO input function configuration register 0x190 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC16_IN_SEL_CFG GPIO input function configuration register 0x194 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC17_IN_SEL_CFG GPIO input function configuration register 0x198 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC19_IN_SEL_CFG GPIO input function configuration register 0x1A0 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC28_IN_SEL_CFG GPIO input function configuration register 0x1C4 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC29_IN_SEL_CFG GPIO input function configuration register 0x1C8 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC30_IN_SEL_CFG GPIO input function configuration register 0x1CC 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC31_IN_SEL_CFG GPIO input function configuration register 0x1D0 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC32_IN_SEL_CFG GPIO input function configuration register 0x1D4 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC33_IN_SEL_CFG GPIO input function configuration register 0x1D8 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC34_IN_SEL_CFG GPIO input function configuration register 0x1DC 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC35_IN_SEL_CFG GPIO input function configuration register 0x1E0 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC40_IN_SEL_CFG GPIO input function configuration register 0x1F4 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC41_IN_SEL_CFG GPIO input function configuration register 0x1F8 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC42_IN_SEL_CFG GPIO input function configuration register 0x1FC 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC45_IN_SEL_CFG GPIO input function configuration register 0x208 0x20 0x00000038 IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC46_IN_SEL_CFG GPIO input function configuration register 0x20C 0x20 0x00000038 IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC47_IN_SEL_CFG GPIO input function configuration register 0x210 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC48_IN_SEL_CFG GPIO input function configuration register 0x214 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC49_IN_SEL_CFG GPIO input function configuration register 0x218 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC50_IN_SEL_CFG GPIO input function configuration register 0x21C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC51_IN_SEL_CFG GPIO input function configuration register 0x220 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC52_IN_SEL_CFG GPIO input function configuration register 0x224 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC53_IN_SEL_CFG GPIO input function configuration register 0x228 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC54_IN_SEL_CFG GPIO input function configuration register 0x22C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC55_IN_SEL_CFG GPIO input function configuration register 0x230 0x20 0x00000038 IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC56_IN_SEL_CFG GPIO input function configuration register 0x234 0x20 0x00000038 IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC63_IN_SEL_CFG GPIO input function configuration register 0x250 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC64_IN_SEL_CFG GPIO input function configuration register 0x254 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC65_IN_SEL_CFG GPIO input function configuration register 0x258 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC66_IN_SEL_CFG GPIO input function configuration register 0x25C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC67_IN_SEL_CFG GPIO input function configuration register 0x260 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC68_IN_SEL_CFG GPIO input function configuration register 0x264 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC69_IN_SEL_CFG GPIO input function configuration register 0x268 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC70_IN_SEL_CFG GPIO input function configuration register 0x26C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC71_IN_SEL_CFG GPIO input function configuration register 0x270 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC72_IN_SEL_CFG GPIO input function configuration register 0x274 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC73_IN_SEL_CFG GPIO input function configuration register 0x278 0x20 0x00000038 IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC81_IN_SEL_CFG GPIO input function configuration register 0x298 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC82_IN_SEL_CFG GPIO input function configuration register 0x29C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC87_IN_SEL_CFG GPIO input function configuration register 0x2B0 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC88_IN_SEL_CFG GPIO input function configuration register 0x2B4 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC89_IN_SEL_CFG GPIO input function configuration register 0x2B8 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC90_IN_SEL_CFG GPIO input function configuration register 0x2BC 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC91_IN_SEL_CFG GPIO input function configuration register 0x2C0 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC92_IN_SEL_CFG GPIO input function configuration register 0x2C4 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC93_IN_SEL_CFG GPIO input function configuration register 0x2C8 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC94_IN_SEL_CFG GPIO input function configuration register 0x2CC 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC95_IN_SEL_CFG GPIO input function configuration register 0x2D0 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC97_IN_SEL_CFG GPIO input function configuration register 0x2D8 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC98_IN_SEL_CFG GPIO input function configuration register 0x2DC 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC99_IN_SEL_CFG GPIO input function configuration register 0x2E0 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC100_IN_SEL_CFG GPIO input function configuration register 0x2E4 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC101_IN_SEL_CFG GPIO input function configuration register 0x2E8 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC102_IN_SEL_CFG GPIO input function configuration register 0x2EC 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC103_IN_SEL_CFG GPIO input function configuration register 0x2F0 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC104_IN_SEL_CFG GPIO input function configuration register 0x2F4 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC105_IN_SEL_CFG GPIO input function configuration register 0x2F8 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC106_IN_SEL_CFG GPIO input function configuration register 0x2FC 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC107_IN_SEL_CFG GPIO input function configuration register 0x300 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC108_IN_SEL_CFG GPIO input function configuration register 0x304 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC109_IN_SEL_CFG GPIO input function configuration register 0x308 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC110_IN_SEL_CFG GPIO input function configuration register 0x30C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC111_IN_SEL_CFG GPIO input function configuration register 0x310 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC112_IN_SEL_CFG GPIO input function configuration register 0x314 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC113_IN_SEL_CFG GPIO input function configuration register 0x318 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC114_IN_SEL_CFG GPIO input function configuration register 0x31C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC115_IN_SEL_CFG GPIO input function configuration register 0x320 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC116_IN_SEL_CFG GPIO input function configuration register 0x324 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC117_IN_SEL_CFG GPIO input function configuration register 0x328 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC118_IN_SEL_CFG GPIO input function configuration register 0x32C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC119_IN_SEL_CFG GPIO input function configuration register 0x330 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC120_IN_SEL_CFG GPIO input function configuration register 0x334 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC121_IN_SEL_CFG GPIO input function configuration register 0x338 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC122_IN_SEL_CFG GPIO input function configuration register 0x33C 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC123_IN_SEL_CFG GPIO input function configuration register 0x340 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write FUNC124_IN_SEL_CFG GPIO input function configuration register 0x344 0x20 0x0000003C IN_SEL set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 6 read-write IN_INV_SEL set this bit to invert input signal. 1:invert. 0:not invert. 6 1 read-write SEL set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 7 1 read-write 32 0x4 FUNC%s_OUT_SEL_CFG GPIO output function select register 0x554 0x20 0x00000080 OUT_SEL The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n]. 0 8 read-write INV_SEL set this bit to invert output signal.1:invert.0:not invert. 8 1 read-write OEN_SEL set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. 9 1 read-write OEN_INV_SEL set this bit to invert output enable signal.1:invert.0:not invert. 10 1 read-write CLOCK_GATE GPIO clock gate register 0x62C 0x20 0x00000001 CLK_EN set this bit to enable GPIO clock gate 0 1 read-write DATE GPIO version register 0x6FC 0x20 0x02201120 DATE version register 0 28 read-write HMAC HMAC (Hash-based Message Authentication Code) Accelerator HMAC 0x6003E000 0x0 0xA4 registers SET_START Process control register 0. 0x40 0x20 SET_START Start hmac operation. 0 1 write-only SET_PARA_PURPOSE Configure purpose. 0x44 0x20 PURPOSE_SET Set hmac parameter purpose. 0 4 write-only SET_PARA_KEY Configure key. 0x48 0x20 KEY_SET Set hmac parameter key. 0 3 write-only SET_PARA_FINISH Finish initial configuration. 0x4C 0x20 SET_PARA_END Finish hmac configuration. 0 1 write-only SET_MESSAGE_ONE Process control register 1. 0x50 0x20 SET_TEXT_ONE Call SHA to calculate one message block. 0 1 write-only SET_MESSAGE_ING Process control register 2. 0x54 0x20 SET_TEXT_ING Continue typical hmac. 0 1 write-only SET_MESSAGE_END Process control register 3. 0x58 0x20 SET_TEXT_END Start hardware padding. 0 1 write-only SET_RESULT_FINISH Process control register 4. 0x5C 0x20 SET_RESULT_END After read result from upstream, then let hmac back to idle. 0 1 write-only SET_INVALIDATE_JTAG Invalidate register 0. 0x60 0x20 SET_INVALIDATE_JTAG Clear result from hmac downstream JTAG. 0 1 write-only SET_INVALIDATE_DS Invalidate register 1. 0x64 0x20 SET_INVALIDATE_DS Clear result from hmac downstream DS. 0 1 write-only QUERY_ERROR Error register. 0x68 0x20 QUREY_CHECK Hmac configuration state. 0: key are agree with purpose. 1: error 0 1 read-only QUERY_BUSY Busy register. 0x6C 0x20 BUSY_STATE Hmac state. 1'b0: idle. 1'b1: busy 0 1 read-only 64 0x1 WR_MESSAGE_MEM[%s] Message block memory. 0x80 0x8 32 0x1 RD_RESULT_MEM[%s] Result from upstream. 0xC0 0x8 SET_MESSAGE_PAD Process control register 5. 0xF0 0x20 SET_TEXT_PAD Start software padding. 0 1 write-only ONE_BLOCK Process control register 6. 0xF4 0x20 SET_ONE_BLOCK Don't have to do padding. 0 1 write-only SOFT_JTAG_CTRL Jtag register 0. 0xF8 0x20 SOFT_JTAG_CTRL Turn on JTAG verification. 0 1 write-only WR_JTAG Jtag register 1. 0xFC 0x20 WR_JTAG 32-bit of key to be compared. 0 32 write-only DATE Date register. 0x1FC 0x20 0x20200618 DATE Hmac date information/ hmac version information. 0 30 read-write I2C0 I2C (Inter-Integrated Circuit) Controller I2C 0x60013000 0x0 0x90 registers I2C 11 I2C_EXT0 29 SCL_LOW_PERIOD Configures the low level width of the SCL Clock 0x0 0x20 SCL_LOW_PERIOD This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles. 0 9 read-write CTR Transmission setting 0x4 0x20 0x00000208 SDA_FORCE_OUT 1: direct output, 0: open drain output. 0 1 read-write SCL_FORCE_OUT 1: direct output, 0: open drain output. 1 1 read-write SAMPLE_SCL_LEVEL This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level. 2 1 read-write RX_FULL_ACK_LEVEL This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. 3 1 read-write MS_MODE Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave. 4 1 read-write TRANS_START Set this bit to start sending the data in txfifo. 5 1 write-only TX_LSB_FIRST This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit. 6 1 read-write RX_LSB_FIRST This bit is used to control the storage mode for received data. 1: receive data from the least significant bit, 0: receive data from the most significant bit. 7 1 read-write CLK_EN Reserved 8 1 read-write ARBITRATION_EN This is the enable bit for arbitration_lost. 9 1 read-write FSM_RST This register is used to reset the scl FMS. 10 1 write-only CONF_UPGATE synchronization bit 11 1 write-only SLV_TX_AUTO_START_EN This is the enable bit for slave to send data automatically 12 1 read-write ADDR_10BIT_RW_CHECK_EN This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol 13 1 read-write ADDR_BROADCASTING_EN This is the enable bit to support the 7bit general call function. 14 1 read-write SR Describe I2C work status. 0x8 0x20 0x0000C000 RESP_REC The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. 0 1 read-only SLAVE_RW When in slave mode, 1: master reads from slave, 0: master writes to slave. 1 1 read-only ARB_LOST When the I2C controller loses control of SCL line, this register changes to 1. 3 1 read-only BUS_BUSY 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. 4 1 read-only SLAVE_ADDRESSED When configured as an I2C Slave, and the address sent by the master is equal to the address of the slave, then this bit will be of high level. 5 1 read-only RXFIFO_CNT This field represents the amount of data needed to be sent. 8 6 read-only STRETCH_CAUSE The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode. 14 2 read-only TXFIFO_CNT This field stores the amount of received data in RAM. 18 6 read-only SCL_MAIN_STATE_LAST This field indicates the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK 24 3 read-only SCL_STATE_LAST This field indicates the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop 28 3 read-only TO Setting time out control for receiving data. 0xC 0x20 0x00000010 TIME_OUT_VALUE This register is used to configure the timeout for receiving a data bit in APB clock cycles. 0 5 read-write TIME_OUT_EN This is the enable bit for time out control. 5 1 read-write SLAVE_ADDR Local slave address setting 0x10 0x20 SLAVE_ADDR When configured as an I2C Slave, this field is used to configure the slave address. 0 15 read-write ADDR_10BIT_EN This field is used to enable the slave 10-bit addressing mode in master mode. 31 1 read-write FIFO_ST FIFO status register. 0x14 0x20 RXFIFO_RADDR This is the offset address of the APB reading from rxfifo 0 5 read-only RXFIFO_WADDR This is the offset address of i2c module receiving data and writing to rxfifo. 5 5 read-only TXFIFO_RADDR This is the offset address of i2c module reading from txfifo. 10 5 read-only TXFIFO_WADDR This is the offset address of APB bus writing to txfifo. 15 5 read-only SLAVE_RW_POINT The received data in I2C slave mode. 22 8 read-only FIFO_CONF FIFO configuration register. 0x18 0x20 0x0000408B RXFIFO_WM_THRHD The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid. 0 5 read-write TXFIFO_WM_THRHD The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid. 5 5 read-write NONFIFO_EN Set this bit to enable APB nonfifo access. 10 1 read-write FIFO_ADDR_CFG_EN When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. 11 1 read-write RX_FIFO_RST Set this bit to reset rx-fifo. 12 1 read-write TX_FIFO_RST Set this bit to reset tx-fifo. 13 1 read-write FIFO_PRT_EN The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. 14 1 read-write DATA Rx FIFO read data. 0x1C 0x20 FIFO_RDATA The value of rx FIFO read data. 0 8 read-only INT_RAW Raw interrupt status 0x20 0x20 0x00000002 RXFIFO_WM_INT_RAW The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-only TXFIFO_WM_INT_RAW The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-only RXFIFO_OVF_INT_RAW The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-only END_DETECT_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 3 1 read-only BYTE_TRANS_DONE_INT_RAW The raw interrupt bit for the I2C_END_DETECT_INT interrupt. 4 1 read-only ARBITRATION_LOST_INT_RAW The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-only MST_TXFIFO_UDF_INT_RAW The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-only TRANS_COMPLETE_INT_RAW The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-only TIME_OUT_INT_RAW The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-only TRANS_START_INT_RAW The raw interrupt bit for the I2C_TRANS_START_INT interrupt. 9 1 read-only NACK_INT_RAW The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-only TXFIFO_OVF_INT_RAW The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-only RXFIFO_UDF_INT_RAW The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-only SCL_ST_TO_INT_RAW The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-only SCL_MAIN_ST_TO_INT_RAW The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-only DET_START_INT_RAW The raw interrupt bit for I2C_DET_START_INT interrupt. 15 1 read-only SLAVE_STRETCH_INT_RAW The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. 16 1 read-only GENERAL_CALL_INT_RAW The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. 17 1 read-only SLAVE_ADDR_UNMATCH_INT_RAW The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. 18 1 read-only INT_CLR Interrupt clear bits 0x24 0x20 RXFIFO_WM_INT_CLR Set this bit to clear I2C_RXFIFO_WM_INT interrupt. 0 1 write-only TXFIFO_WM_INT_CLR Set this bit to clear I2C_TXFIFO_WM_INT interrupt. 1 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. 2 1 write-only END_DETECT_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. 3 1 write-only BYTE_TRANS_DONE_INT_CLR Set this bit to clear the I2C_END_DETECT_INT interrupt. 4 1 write-only ARBITRATION_LOST_INT_CLR Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. 5 1 write-only MST_TXFIFO_UDF_INT_CLR Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. 6 1 write-only TRANS_COMPLETE_INT_CLR Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. 7 1 write-only TIME_OUT_INT_CLR Set this bit to clear the I2C_TIME_OUT_INT interrupt. 8 1 write-only TRANS_START_INT_CLR Set this bit to clear the I2C_TRANS_START_INT interrupt. 9 1 write-only NACK_INT_CLR Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. 10 1 write-only TXFIFO_OVF_INT_CLR Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. 11 1 write-only RXFIFO_UDF_INT_CLR Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. 12 1 write-only SCL_ST_TO_INT_CLR Set this bit to clear I2C_SCL_ST_TO_INT interrupt. 13 1 write-only SCL_MAIN_ST_TO_INT_CLR Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 write-only DET_START_INT_CLR Set this bit to clear I2C_DET_START_INT interrupt. 15 1 write-only SLAVE_STRETCH_INT_CLR Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. 16 1 write-only GENERAL_CALL_INT_CLR Set this bit to clear I2C_GENARAL_CALL_INT interrupt. 17 1 write-only SLAVE_ADDR_UNMATCH_INT_CLR Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. 18 1 write-only INT_ENA Interrupt enable bits 0x28 0x20 RXFIFO_WM_INT_ENA The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-write TXFIFO_WM_INT_ENA The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-write RXFIFO_OVF_INT_ENA The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-write END_DETECT_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 3 1 read-write BYTE_TRANS_DONE_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. 4 1 read-write ARBITRATION_LOST_INT_ENA The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-write MST_TXFIFO_UDF_INT_ENA The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-write TRANS_COMPLETE_INT_ENA The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-write TIME_OUT_INT_ENA The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-write TRANS_START_INT_ENA The interrupt enable bit for the I2C_TRANS_START_INT interrupt. 9 1 read-write NACK_INT_ENA The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-write TXFIFO_OVF_INT_ENA The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-write RXFIFO_UDF_INT_ENA The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-write SCL_ST_TO_INT_ENA The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-write SCL_MAIN_ST_TO_INT_ENA The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-write DET_START_INT_ENA The interrupt enable bit for I2C_DET_START_INT interrupt. 15 1 read-write SLAVE_STRETCH_INT_ENA The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. 16 1 read-write GENERAL_CALL_INT_ENA The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. 17 1 read-write SLAVE_ADDR_UNMATCH_INT_ENA The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. 18 1 read-write INT_STATUS Status of captured I2C communication events 0x2C 0x20 RXFIFO_WM_INT_ST The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. 0 1 read-only TXFIFO_WM_INT_ST The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. 1 1 read-only RXFIFO_OVF_INT_ST The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. 2 1 read-only END_DETECT_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 3 1 read-only BYTE_TRANS_DONE_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. 4 1 read-only ARBITRATION_LOST_INT_ST The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. 5 1 read-only MST_TXFIFO_UDF_INT_ST The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. 6 1 read-only TRANS_COMPLETE_INT_ST The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. 7 1 read-only TIME_OUT_INT_ST The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. 8 1 read-only TRANS_START_INT_ST The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. 9 1 read-only NACK_INT_ST The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. 10 1 read-only TXFIFO_OVF_INT_ST The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. 11 1 read-only RXFIFO_UDF_INT_ST The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. 12 1 read-only SCL_ST_TO_INT_ST The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. 13 1 read-only SCL_MAIN_ST_TO_INT_ST The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. 14 1 read-only DET_START_INT_ST The masked interrupt status bit for I2C_DET_START_INT interrupt. 15 1 read-only SLAVE_STRETCH_INT_ST The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. 16 1 read-only GENERAL_CALL_INT_ST The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. 17 1 read-only SLAVE_ADDR_UNMATCH_INT_ST The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. 18 1 read-only SDA_HOLD Configures the hold time after a negative SCL edge. 0x30 0x20 TIME This register is used to configure the time to hold the data after the negative edge of SCL, in I2C module clock cycles. 0 9 read-write SDA_SAMPLE Configures the sample time after a positive SCL edge. 0x34 0x20 TIME This register is used to configure for how long SDA is sampled, in I2C module clock cycles. 0 9 read-write SCL_HIGH_PERIOD Configures the high level width of SCL 0x38 0x20 SCL_HIGH_PERIOD This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles. 0 9 read-write SCL_WAIT_HIGH_PERIOD This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles. 9 7 read-write SCL_START_HOLD Configures the delay between the SDA and SCL negative edge for a start condition 0x40 0x20 0x00000008 TIME This register is used to configure the time between the negative edge of SDA and the negative edge of SCL for a START condition, in I2C module clock cycles. 0 9 read-write SCL_RSTART_SETUP Configures the delay between the positive edge of SCL and the negative edge of SDA 0x44 0x20 0x00000008 TIME This register is used to configure the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles. 0 9 read-write SCL_STOP_HOLD Configures the delay after the SCL clock edge for a stop condition 0x48 0x20 0x00000008 TIME This register is used to configure the delay after the STOP condition, in I2C module clock cycles. 0 9 read-write SCL_STOP_SETUP Configures the delay between the SDA and SCL positive edge for a stop condition 0x4C 0x20 0x00000008 TIME This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles. 0 9 read-write FILTER_CFG SCL and SDA filter configuration register 0x50 0x20 0x00000300 SCL_FILTER_THRES When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. 0 4 read-write SDA_FILTER_THRES When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse. 4 4 read-write SCL_FILTER_EN This is the filter enable bit for SCL. 8 1 read-write SDA_FILTER_EN This is the filter enable bit for SDA. 9 1 read-write CLK_CONF I2C CLK configuration register 0x54 0x20 0x00200000 SCLK_DIV_NUM the integral part of the fractional divisor for i2c module 0 8 read-write SCLK_DIV_A the numerator of the fractional part of the fractional divisor for i2c module 8 6 read-write SCLK_DIV_B the denominator of the fractional part of the fractional divisor for i2c module 14 6 read-write SCLK_SEL The clock selection for i2c module:0-XTAL,1-CLK_8MHz. 20 1 read-write SCLK_ACTIVE The clock switch for i2c module 21 1 read-write 8 0x4 0-7 COMD%s I2C command register %s 0x58 0x20 COMMAND0 This is the content of command 0. It consists of three parts: op_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END. Byte_num represents the number of bytes that need to be sent or received. ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more Information. 0 14 read-write COMMAND0_DONE When command 0 is done in I2C Master mode, this bit changes to high level. 31 1 read-write SCL_ST_TIME_OUT SCL status time out register 0x78 0x20 0x00000010 SCL_ST_TO_I2C The threshold value of SCL_FSM state unchanged period. It should be o more than 23 0 5 read-write SCL_MAIN_ST_TIME_OUT SCL main status time out register 0x7C 0x20 0x00000010 SCL_MAIN_ST_TO_I2C The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 0 5 read-write SCL_SP_CONF Power configuration register 0x80 0x20 SCL_RST_SLV_EN When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]. 0 1 read-write SCL_RST_SLV_NUM Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. 1 5 read-write SCL_PD_EN The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. 6 1 read-write SDA_PD_EN The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. 7 1 read-write SCL_STRETCH_CONF Set SCL stretch of I2C slave 0x84 0x20 STRETCH_PROTECT_NUM Configure the period of I2C slave stretching SCL line. 0 10 read-write SLAVE_SCL_STRETCH_EN The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause. 10 1 read-write SLAVE_SCL_STRETCH_CLR Set this bit to clear the I2C slave SCL stretch function. 11 1 write-only SLAVE_BYTE_ACK_CTL_EN The enable bit for slave to control ACK level function. 12 1 read-write SLAVE_BYTE_ACK_LVL Set the ACK level when slave controlling ACK level function enables. 13 1 read-write DATE Version register 0xF8 0x20 0x02201172 DATE This is the the version register. 0 32 read-write TXFIFO_START_ADDR I2C TXFIFO base address register 0x100 0x20 TXFIFO_START_ADDR This is the I2C txfifo first address. 0 32 read-only RXFIFO_START_ADDR I2C RXFIFO base address register 0x180 0x20 RXFIFO_START_ADDR This is the I2C rxfifo first address. 0 32 read-only I2S0 I2S (Inter-IC Sound) Controller I2S 0x6002D000 0x0 0x60 registers I2S1 20 INT_RAW I2S interrupt raw register, valid in level. 0xC 0x20 RX_DONE_INT_RAW The raw interrupt status bit for the i2s_rx_done_int interrupt 0 1 read-only TX_DONE_INT_RAW The raw interrupt status bit for the i2s_tx_done_int interrupt 1 1 read-only RX_HUNG_INT_RAW The raw interrupt status bit for the i2s_rx_hung_int interrupt 2 1 read-only TX_HUNG_INT_RAW The raw interrupt status bit for the i2s_tx_hung_int interrupt 3 1 read-only INT_ST I2S interrupt status register. 0x10 0x20 RX_DONE_INT_ST The masked interrupt status bit for the i2s_rx_done_int interrupt 0 1 read-only TX_DONE_INT_ST The masked interrupt status bit for the i2s_tx_done_int interrupt 1 1 read-only RX_HUNG_INT_ST The masked interrupt status bit for the i2s_rx_hung_int interrupt 2 1 read-only TX_HUNG_INT_ST The masked interrupt status bit for the i2s_tx_hung_int interrupt 3 1 read-only INT_ENA I2S interrupt enable register. 0x14 0x20 RX_DONE_INT_ENA The interrupt enable bit for the i2s_rx_done_int interrupt 0 1 read-write TX_DONE_INT_ENA The interrupt enable bit for the i2s_tx_done_int interrupt 1 1 read-write RX_HUNG_INT_ENA The interrupt enable bit for the i2s_rx_hung_int interrupt 2 1 read-write TX_HUNG_INT_ENA The interrupt enable bit for the i2s_tx_hung_int interrupt 3 1 read-write INT_CLR I2S interrupt clear register. 0x18 0x20 RX_DONE_INT_CLR Set this bit to clear the i2s_rx_done_int interrupt 0 1 write-only TX_DONE_INT_CLR Set this bit to clear the i2s_tx_done_int interrupt 1 1 write-only RX_HUNG_INT_CLR Set this bit to clear the i2s_rx_hung_int interrupt 2 1 write-only TX_HUNG_INT_CLR Set this bit to clear the i2s_tx_hung_int interrupt 3 1 write-only RX_CONF I2S RX configure register 0x20 0x20 0x00C0B600 RX_RESET Set this bit to reset receiver 0 1 write-only RX_FIFO_RESET Set this bit to reset Rx AFIFO 1 1 write-only RX_START Set this bit to start receiving data 2 1 read-write RX_SLAVE_MOD Set this bit to enable slave receiver mode 3 1 read-write RX_STOP_MODE 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. 4 2 read-write RX_MONO Set this bit to enable receiver in mono mode 6 1 read-write RX_BIG_ENDIAN I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write RX_UPDATE Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write RX_MONO_FST_VLD 1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode. 9 1 read-write RX_PCM_CONF I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write RX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for received data. 12 1 read-write RX_MSB_SHIFT Set this bit to enable receiver in Phillips standard mode 13 1 read-write RX_LEFT_ALIGN 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. 15 1 read-write RX_24_FILL_EN 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. 16 1 read-write RX_WS_IDLE_POL 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. 17 1 read-write RX_BIT_ORDER I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first. 18 1 read-write RX_TDM_EN 1: Enable I2S TDM Rx mode . 0: Disable. 19 1 read-write RX_PDM_EN 1: Enable I2S PDM Rx mode . 0: Disable. 20 1 read-write RX_BCK_DIV_NUM Bit clock configuration bits in receiver mode. 21 6 read-write TX_CONF I2S TX configure register 0x24 0x20 0x00C0F210 TX_RESET Set this bit to reset transmitter 0 1 write-only TX_FIFO_RESET Set this bit to reset Tx AFIFO 1 1 write-only TX_START Set this bit to start transmitting data 2 1 read-write TX_SLAVE_MOD Set this bit to enable slave transmitter mode 3 1 read-write TX_STOP_EN Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy 4 1 read-write TX_CHAN_EQUAL 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. 5 1 read-write TX_MONO Set this bit to enable transmitter in mono mode 6 1 read-write TX_BIG_ENDIAN I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 7 1 read-write TX_UPDATE Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. 8 1 read-write TX_MONO_FST_VLD 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode. 9 1 read-write TX_PCM_CONF I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 10 2 read-write TX_PCM_BYPASS Set this bit to bypass Compress/Decompress module for transmitted data. 12 1 read-write TX_MSB_SHIFT Set this bit to enable transmitter in Phillips standard mode 13 1 read-write TX_BCK_NO_DLY 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode. 14 1 read-write TX_LEFT_ALIGN 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. 15 1 read-write TX_24_FILL_EN 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode 16 1 read-write TX_WS_IDLE_POL 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. 17 1 read-write TX_BIT_ORDER I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first. 18 1 read-write TX_TDM_EN 1: Enable I2S TDM Tx mode . 0: Disable. 19 1 read-write TX_PDM_EN 1: Enable I2S PDM Tx mode . 0: Disable. 20 1 read-write TX_BCK_DIV_NUM Bit clock configuration bits in transmitter mode. 21 6 read-write TX_CHAN_MOD I2S transmitter channel mode configuration bits. 27 3 read-write SIG_LOOPBACK Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. 30 1 read-write RX_CONF1 I2S RX configure register 1 0x28 0x20 0x787BC000 RX_TDM_WS_WIDTH The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck 0 9 read-write RX_BITS_MOD Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. 14 5 read-write RX_HALF_SAMPLE_BITS I2S Rx half sample bits -1. 19 8 read-write RX_TDM_CHAN_BITS The Rx bit number for each channel minus 1in TDM mode. 27 5 read-write TX_CONF1 I2S TX configure register 1 0x2C 0x20 0x787BC000 TX_TDM_WS_WIDTH The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck 0 9 read-write TX_BITS_MOD Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode. 14 5 read-write TX_HALF_SAMPLE_BITS I2S Tx half sample bits -1. 19 8 read-write TX_TDM_CHAN_BITS The Tx bit number for each channel minus 1in TDM mode. 27 5 read-write RX_CLKM_CONF I2S RX clock configure register 0x30 0x20 0x00000002 RX_CLKM_DIV_NUM Integral I2S clock divider value 0 8 read-write RX_CLK_ACTIVE I2S Rx module clock enable signal. 26 1 read-write RX_CLK_SEL Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 27 2 read-write MCLK_SEL 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. 29 1 read-write TX_CLKM_CONF I2S TX clock configure register 0x34 0x20 0x00000002 TX_CLKM_DIV_NUM Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. 0 8 read-write TX_CLK_ACTIVE I2S Tx module clock enable signal. 26 1 read-write TX_CLK_SEL Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 27 2 read-write CLK_EN Set this bit to enable clk gate 29 1 read-write RX_CLKM_DIV_CONF I2S RX module clock divider configure register 0x38 0x20 0x00000200 RX_CLKM_DIV_Z For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). 0 9 read-write RX_CLKM_DIV_Y For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). 9 9 read-write RX_CLKM_DIV_X For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. 18 9 read-write RX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. 27 1 read-write TX_CLKM_DIV_CONF I2S TX module clock divider configure register 0x3C 0x20 0x00000200 TX_CLKM_DIV_Z For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). 0 9 read-write TX_CLKM_DIV_Y For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). 9 9 read-write TX_CLKM_DIV_X For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. 18 9 read-write TX_CLKM_DIV_YN1 For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. 27 1 read-write TX_PCM2PDM_CONF I2S TX PCM2PDM configuration register 0x40 0x20 0x004AA004 TX_PDM_HP_BYPASS I2S TX PDM bypass hp filter or not. The option has been removed. 0 1 read-write TX_PDM_SINC_OSR2 I2S TX PDM OSR2 value 1 4 read-write TX_PDM_PRESCALE I2S TX PDM prescale for sigmadelta 5 8 read-write TX_PDM_HP_IN_SHIFT I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 13 2 read-write TX_PDM_LP_IN_SHIFT I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 15 2 read-write TX_PDM_SINC_IN_SHIFT I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 17 2 read-write TX_PDM_SIGMADELTA_IN_SHIFT I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 19 2 read-write TX_PDM_SIGMADELTA_DITHER2 I2S TX PDM sigmadelta dither2 value 21 1 read-write TX_PDM_SIGMADELTA_DITHER I2S TX PDM sigmadelta dither value 22 1 read-write TX_PDM_DAC_2OUT_EN I2S TX PDM dac mode enable 23 1 read-write TX_PDM_DAC_MODE_EN I2S TX PDM dac 2channel enable 24 1 read-write PCM2PDM_CONV_EN I2S TX PDM Converter enable 25 1 read-write TX_PCM2PDM_CONF1 I2S TX PCM2PDM configuration register 0x44 0x20 0x03F783C0 TX_PDM_FP I2S TX PDM Fp 0 10 read-write TX_PDM_FS I2S TX PDM Fs 10 10 read-write TX_IIR_HP_MULT12_5 The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0]) 20 3 read-write TX_IIR_HP_MULT12_0 The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0]) 23 3 read-write RX_TDM_CTRL I2S TX TDM mode control register 0x50 0x20 0x0000FFFF RX_TDM_PDM_CHAN0_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel. 0 1 read-write RX_TDM_PDM_CHAN1_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel. 1 1 read-write RX_TDM_PDM_CHAN2_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel. 2 1 read-write RX_TDM_PDM_CHAN3_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel. 3 1 read-write RX_TDM_PDM_CHAN4_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel. 4 1 read-write RX_TDM_PDM_CHAN5_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel. 5 1 read-write RX_TDM_PDM_CHAN6_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel. 6 1 read-write RX_TDM_PDM_CHAN7_EN 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel. 7 1 read-write RX_TDM_CHAN8_EN 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel. 8 1 read-write RX_TDM_CHAN9_EN 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel. 9 1 read-write RX_TDM_CHAN10_EN 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel. 10 1 read-write RX_TDM_CHAN11_EN 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel. 11 1 read-write RX_TDM_CHAN12_EN 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel. 12 1 read-write RX_TDM_CHAN13_EN 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel. 13 1 read-write RX_TDM_CHAN14_EN 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel. 14 1 read-write RX_TDM_CHAN15_EN 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel. 15 1 read-write RX_TDM_TOT_CHAN_NUM The total channel number of I2S TX TDM mode. 16 4 read-write TX_TDM_CTRL I2S TX TDM mode control register 0x54 0x20 0x0000FFFF TX_TDM_CHAN0_EN 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel. 0 1 read-write TX_TDM_CHAN1_EN 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel. 1 1 read-write TX_TDM_CHAN2_EN 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel. 2 1 read-write TX_TDM_CHAN3_EN 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel. 3 1 read-write TX_TDM_CHAN4_EN 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel. 4 1 read-write TX_TDM_CHAN5_EN 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel. 5 1 read-write TX_TDM_CHAN6_EN 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel. 6 1 read-write TX_TDM_CHAN7_EN 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel. 7 1 read-write TX_TDM_CHAN8_EN 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel. 8 1 read-write TX_TDM_CHAN9_EN 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel. 9 1 read-write TX_TDM_CHAN10_EN 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel. 10 1 read-write TX_TDM_CHAN11_EN 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel. 11 1 read-write TX_TDM_CHAN12_EN 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel. 12 1 read-write TX_TDM_CHAN13_EN 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel. 13 1 read-write TX_TDM_CHAN14_EN 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel. 14 1 read-write TX_TDM_CHAN15_EN 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel. 15 1 read-write TX_TDM_TOT_CHAN_NUM The total channel number of I2S TX TDM mode. 16 4 read-write TX_TDM_SKIP_MSK_EN When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels. 20 1 read-write RX_TIMING I2S RX timing control register 0x58 0x20 RX_SD_IN_DM The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 2 read-write RX_WS_OUT_DM The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 16 2 read-write RX_BCK_OUT_DM The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 20 2 read-write RX_WS_IN_DM The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 24 2 read-write RX_BCK_IN_DM The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 28 2 read-write TX_TIMING I2S TX timing control register 0x5C 0x20 TX_SD_OUT_DM The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 0 2 read-write TX_SD1_OUT_DM The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 4 2 read-write TX_WS_OUT_DM The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 16 2 read-write TX_BCK_OUT_DM The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 20 2 read-write TX_WS_IN_DM The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 24 2 read-write TX_BCK_IN_DM The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used. 28 2 read-write LC_HUNG_CONF I2S HUNG configure register. 0x60 0x20 0x00000810 LC_FIFO_TIMEOUT the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value 0 8 read-write LC_FIFO_TIMEOUT_SHIFT The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift 8 3 read-write LC_FIFO_TIMEOUT_ENA The enable bit for FIFO timeout 11 1 read-write RXEOF_NUM I2S RX data number control register. 0x64 0x20 0x00000040 RX_EOF_NUM The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. 0 12 read-write CONF_SIGLE_DATA I2S signal data register 0x68 0x20 SINGLE_DATA The configured constant channel data to be sent out. 0 32 read-write STATE I2S TX status register 0x6C 0x20 0x00000001 TX_IDLE 1: i2s_tx is idle state. 0: i2s_tx is working. 0 1 read-only ETM_CONF I2S ETM configure register 0x70 0x20 0x00010040 ETM_TX_SEND_WORD_NUM I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. 0 10 read-write ETM_RX_RECEIVE_WORD_NUM I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. 10 10 read-write DATE Version control register 0x80 0x20 0x02208250 DATE I2S version control register 0 28 read-write IO_MUX Input/Output Multiplexer IO_MUX 0x60009000 0x0 0x7C registers PIN_CTRL Clock Output Configuration Register 0x0 0x20 0x00001DEF CLK_OUT1 If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals. 0 5 read-write CLK_OUT2 If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals. 5 5 read-write CLK_OUT3 If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals. 10 5 read-write 28 0x4 GPIO%s IO MUX Configure Register for pad GPIO0 0x4 0x20 0x00000800 MCU_OE Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. 0 1 read-write SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. 1 1 read-write MCU_WPD Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled. 2 1 read-write MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled. 3 1 read-write MCU_IE Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. 4 1 read-write MCU_DRV Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. 5 2 read-write FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled. 7 1 read-write FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled. 8 1 read-write FUN_IE Input enable of the pad. 1: input enabled. 0: input disabled. 9 1 read-write FUN_DRV Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA. 10 2 read-write MCU_SEL Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc. 12 3 read-write FILTER_EN Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. 15 1 read-write HYS_EN Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: Hysteresis disabled. 16 1 read-write HYS_SEL Select enabling signals of the pad from software and efuse hardware. 1: Select enabling siganl from slftware. 0: Select enabling signal from efuse hardware. 17 1 read-write MODEM_DIAG_EN GPIO MATRIX Configure Register for modem diag 0xBC 0x20 MODEM_DIAG_EN bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix 0 32 read-write DATE IO MUX Version Control Register 0xFC 0x20 0x02207270 REG_DATE Version control register 0 28 read-write LEDC LED Control PWM (Pulse Width Modulation) LEDC 0x60019000 0x0 0x154 registers LEDC 23 6 0x14 CH%s_CONF0 Configuration register 0 for channel %s 0x0 0x20 TIMER_SEL_CH This field is used to select one of timers for channel %s. 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3 0 2 read-write SIG_OUT_EN_CH Set this bit to enable signal output on channel %s. 2 1 read-write IDLE_LV_CH This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). 3 1 read-write PARA_UP_CH This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware. 4 1 write-only OVF_NUM_CH This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. 5 10 read-write OVF_CNT_EN_CH This bit is used to enable the ovf_cnt of channel %s. 15 1 read-write OVF_CNT_RESET_CH Set this bit to reset the ovf_cnt of channel %s. 16 1 write-only 6 0x14 CH%s_HPOINT High point register for channel %s 0x4 0x20 HPOINT_CH The output value changes to high when the selected timers has reached the value specified by this register. 0 20 read-write 6 0x14 CH%s_DUTY Initial duty cycle for channel %s 0x8 0x20 DUTY_CH This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. 0 25 read-write 6 0x14 CH%s_CONF1 Configuration register 1 for channel %s 0xC 0x20 DUTY_START_CH Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. 31 1 read-write 6 0x14 CH%s_DUTY_R Current duty cycle for channel %s 0x10 0x20 DUTY_CH_R This register stores the current duty of output signal on channel %s. 0 25 read-only 4 0x8 TIMER%s_CONF Timer %s configuration 0xA0 0x20 0x01000000 TIMER_DUTY_RES This register is used to control the range of the counter in timer %s. 0 5 read-write CLK_DIV_TIMER This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. 5 18 read-write TIMER_PAUSE This bit is used to suspend the counter in timer %s. 23 1 read-write TIMER_RST This bit is used to reset timer %s. The counter will show 0 after reset. 24 1 read-write TICK_SEL_TIMER This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1'h0: SLOW_CLK 1'h1: REF_TICK 25 1 read-write TIMER_PARA_UP Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. 26 1 write-only 4 0x8 TIMER%s_VALUE Timer %s current counter value 0xA4 0x20 TIMER_CNT This register stores the current counter value of timer %s. 0 20 read-only INT_RAW Raw interrupt status 0xC0 0x20 TIMER0_OVF_INT_RAW Triggered when the timer0 has reached its maximum counter value. 0 1 read-only TIMER1_OVF_INT_RAW Triggered when the timer1 has reached its maximum counter value. 1 1 read-only TIMER2_OVF_INT_RAW Triggered when the timer2 has reached its maximum counter value. 2 1 read-only TIMER3_OVF_INT_RAW Triggered when the timer3 has reached its maximum counter value. 3 1 read-only DUTY_CHNG_END_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. 4 1 read-only DUTY_CHNG_END_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. 5 1 read-only DUTY_CHNG_END_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. 6 1 read-only DUTY_CHNG_END_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. 7 1 read-only DUTY_CHNG_END_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. 8 1 read-only DUTY_CHNG_END_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. 9 1 read-only OVF_CNT_CH0_INT_RAW Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. 12 1 read-only OVF_CNT_CH1_INT_RAW Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. 13 1 read-only OVF_CNT_CH2_INT_RAW Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. 14 1 read-only OVF_CNT_CH3_INT_RAW Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. 15 1 read-only OVF_CNT_CH4_INT_RAW Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. 16 1 read-only OVF_CNT_CH5_INT_RAW Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. 17 1 read-only INT_ST Masked interrupt status 0xC4 0x20 TIMER0_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. 0 1 read-only TIMER1_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. 1 1 read-only TIMER2_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. 2 1 read-only TIMER3_OVF_INT_ST This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. 3 1 read-only DUTY_CHNG_END_CH0_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. 4 1 read-only DUTY_CHNG_END_CH1_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. 5 1 read-only DUTY_CHNG_END_CH2_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. 6 1 read-only DUTY_CHNG_END_CH3_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. 7 1 read-only DUTY_CHNG_END_CH4_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. 8 1 read-only DUTY_CHNG_END_CH5_INT_ST This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. 9 1 read-only OVF_CNT_CH0_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. 12 1 read-only OVF_CNT_CH1_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. 13 1 read-only OVF_CNT_CH2_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. 14 1 read-only OVF_CNT_CH3_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. 15 1 read-only OVF_CNT_CH4_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. 16 1 read-only OVF_CNT_CH5_INT_ST This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. 17 1 read-only INT_ENA Interrupt enable bits 0xC8 0x20 TIMER0_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. 0 1 read-write TIMER1_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. 1 1 read-write TIMER2_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. 2 1 read-write TIMER3_OVF_INT_ENA The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. 3 1 read-write DUTY_CHNG_END_CH0_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. 4 1 read-write DUTY_CHNG_END_CH1_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. 5 1 read-write DUTY_CHNG_END_CH2_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. 6 1 read-write DUTY_CHNG_END_CH3_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. 7 1 read-write DUTY_CHNG_END_CH4_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. 8 1 read-write DUTY_CHNG_END_CH5_INT_ENA The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. 9 1 read-write OVF_CNT_CH0_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. 12 1 read-write OVF_CNT_CH1_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. 13 1 read-write OVF_CNT_CH2_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. 14 1 read-write OVF_CNT_CH3_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. 15 1 read-write OVF_CNT_CH4_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. 16 1 read-write OVF_CNT_CH5_INT_ENA The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. 17 1 read-write INT_CLR Interrupt clear bits 0xCC 0x20 TIMER0_OVF_INT_CLR Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. 0 1 write-only TIMER1_OVF_INT_CLR Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. 1 1 write-only TIMER2_OVF_INT_CLR Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. 2 1 write-only TIMER3_OVF_INT_CLR Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. 3 1 write-only DUTY_CHNG_END_CH0_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. 4 1 write-only DUTY_CHNG_END_CH1_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. 5 1 write-only DUTY_CHNG_END_CH2_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. 6 1 write-only DUTY_CHNG_END_CH3_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. 7 1 write-only DUTY_CHNG_END_CH4_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. 8 1 write-only DUTY_CHNG_END_CH5_INT_CLR Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. 9 1 write-only OVF_CNT_CH0_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. 12 1 write-only OVF_CNT_CH1_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. 13 1 write-only OVF_CNT_CH2_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. 14 1 write-only OVF_CNT_CH3_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. 15 1 write-only OVF_CNT_CH4_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. 16 1 write-only OVF_CNT_CH5_INT_CLR Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. 17 1 write-only 6 0x10 CH%s_GAMMA_WR Ledc ch%s gamma ram write register. 0x100 0x20 CH_GAMMA_DUTY_INC Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase 0: Decrease. 0 1 read-write CH_GAMMA_DUTY_CYCLE Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s. 1 10 read-write CH_GAMMA_SCALE Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s. 11 10 read-write CH_GAMMA_DUTY_NUM Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed. 21 10 read-write 6 0x10 CH%s_GAMMA_WR_ADDR Ledc ch%s gamma ram write address register. 0x104 0x20 CH_GAMMA_WR_ADDR Ledc ch%s gamma ram write address. 0 4 read-write 6 0x10 CH%s_GAMMA_RD_ADDR Ledc ch%s gamma ram read address register. 0x108 0x20 CH_GAMMA_RD_ADDR Ledc ch%s gamma ram read address. 0 4 read-write 6 0x10 CH%s_GAMMA_RD_DATA Ledc ch%s gamma ram read data register. 0x10C 0x20 CH_GAMMA_RD_DATA Ledc ch%s gamma ram read data. 0 31 read-only 6 0x4 CH%s_GAMMA_CONF Ledc ch%s gamma config register. 0x180 0x20 CH_GAMMA_ENTRY_NUM Ledc ch%s gamma entry num. 0 5 read-write CH_GAMMA_PAUSE Ledc ch%s gamma pause, write 1 to pause. 5 1 write-only CH_GAMMA_RESUME Ledc ch%s gamma resume, write 1 to resume. 6 1 write-only EVT_TASK_EN0 Ledc event task enable bit register0. 0x1A0 0x20 EVT_DUTY_CHNG_END_CH0_EN Ledc ch0 duty change end event enable register, write 1 to enable this event. 0 1 read-write EVT_DUTY_CHNG_END_CH1_EN Ledc ch1 duty change end event enable register, write 1 to enable this event. 1 1 read-write EVT_DUTY_CHNG_END_CH2_EN Ledc ch2 duty change end event enable register, write 1 to enable this event. 2 1 read-write EVT_DUTY_CHNG_END_CH3_EN Ledc ch3 duty change end event enable register, write 1 to enable this event. 3 1 read-write EVT_DUTY_CHNG_END_CH4_EN Ledc ch4 duty change end event enable register, write 1 to enable this event. 4 1 read-write EVT_DUTY_CHNG_END_CH5_EN Ledc ch5 duty change end event enable register, write 1 to enable this event. 5 1 read-write EVT_OVF_CNT_PLS_CH0_EN Ledc ch0 overflow count pulse event enable register, write 1 to enable this event. 8 1 read-write EVT_OVF_CNT_PLS_CH1_EN Ledc ch1 overflow count pulse event enable register, write 1 to enable this event. 9 1 read-write EVT_OVF_CNT_PLS_CH2_EN Ledc ch2 overflow count pulse event enable register, write 1 to enable this event. 10 1 read-write EVT_OVF_CNT_PLS_CH3_EN Ledc ch3 overflow count pulse event enable register, write 1 to enable this event. 11 1 read-write EVT_OVF_CNT_PLS_CH4_EN Ledc ch4 overflow count pulse event enable register, write 1 to enable this event. 12 1 read-write EVT_OVF_CNT_PLS_CH5_EN Ledc ch5 overflow count pulse event enable register, write 1 to enable this event. 13 1 read-write EVT_TIME_OVF_TIMER0_EN Ledc timer0 overflow event enable register, write 1 to enable this event. 16 1 read-write EVT_TIME_OVF_TIMER1_EN Ledc timer1 overflow event enable register, write 1 to enable this event. 17 1 read-write EVT_TIME_OVF_TIMER2_EN Ledc timer2 overflow event enable register, write 1 to enable this event. 18 1 read-write EVT_TIME_OVF_TIMER3_EN Ledc timer3 overflow event enable register, write 1 to enable this event. 19 1 read-write EVT_TIME0_CMP_EN Ledc timer0 compare event enable register, write 1 to enable this event. 20 1 read-write EVT_TIME1_CMP_EN Ledc timer1 compare event enable register, write 1 to enable this event. 21 1 read-write EVT_TIME2_CMP_EN Ledc timer2 compare event enable register, write 1 to enable this event. 22 1 read-write EVT_TIME3_CMP_EN Ledc timer3 compare event enable register, write 1 to enable this event. 23 1 read-write TASK_DUTY_SCALE_UPDATE_CH0_EN Ledc ch0 duty scale update task enable register, write 1 to enable this task. 24 1 read-write TASK_DUTY_SCALE_UPDATE_CH1_EN Ledc ch1 duty scale update task enable register, write 1 to enable this task. 25 1 read-write TASK_DUTY_SCALE_UPDATE_CH2_EN Ledc ch2 duty scale update task enable register, write 1 to enable this task. 26 1 read-write TASK_DUTY_SCALE_UPDATE_CH3_EN Ledc ch3 duty scale update task enable register, write 1 to enable this task. 27 1 read-write TASK_DUTY_SCALE_UPDATE_CH4_EN Ledc ch4 duty scale update task enable register, write 1 to enable this task. 28 1 read-write TASK_DUTY_SCALE_UPDATE_CH5_EN Ledc ch5 duty scale update task enable register, write 1 to enable this task. 29 1 read-write EVT_TASK_EN1 Ledc event task enable bit register1. 0x1A4 0x20 TASK_TIMER0_RES_UPDATE_EN Ledc timer0 res update task enable register, write 1 to enable this task. 0 1 read-write TASK_TIMER1_RES_UPDATE_EN Ledc timer1 res update task enable register, write 1 to enable this task. 1 1 read-write TASK_TIMER2_RES_UPDATE_EN Ledc timer2 res update task enable register, write 1 to enable this task. 2 1 read-write TASK_TIMER3_RES_UPDATE_EN Ledc timer3 res update task enable register, write 1 to enable this task. 3 1 read-write TASK_TIMER0_CAP_EN Ledc timer0 capture task enable register, write 1 to enable this task. 4 1 read-write TASK_TIMER1_CAP_EN Ledc timer1 capture task enable register, write 1 to enable this task. 5 1 read-write TASK_TIMER2_CAP_EN Ledc timer2 capture task enable register, write 1 to enable this task. 6 1 read-write TASK_TIMER3_CAP_EN Ledc timer3 capture task enable register, write 1 to enable this task. 7 1 read-write TASK_SIG_OUT_DIS_CH0_EN Ledc ch0 signal out disable task enable register, write 1 to enable this task. 8 1 read-write TASK_SIG_OUT_DIS_CH1_EN Ledc ch1 signal out disable task enable register, write 1 to enable this task. 9 1 read-write TASK_SIG_OUT_DIS_CH2_EN Ledc ch2 signal out disable task enable register, write 1 to enable this task. 10 1 read-write TASK_SIG_OUT_DIS_CH3_EN Ledc ch3 signal out disable task enable register, write 1 to enable this task. 11 1 read-write TASK_SIG_OUT_DIS_CH4_EN Ledc ch4 signal out disable task enable register, write 1 to enable this task. 12 1 read-write TASK_SIG_OUT_DIS_CH5_EN Ledc ch5 signal out disable task enable register, write 1 to enable this task. 13 1 read-write TASK_OVF_CNT_RST_CH0_EN Ledc ch0 overflow count reset task enable register, write 1 to enable this task. 16 1 read-write TASK_OVF_CNT_RST_CH1_EN Ledc ch1 overflow count reset task enable register, write 1 to enable this task. 17 1 read-write TASK_OVF_CNT_RST_CH2_EN Ledc ch2 overflow count reset task enable register, write 1 to enable this task. 18 1 read-write TASK_OVF_CNT_RST_CH3_EN Ledc ch3 overflow count reset task enable register, write 1 to enable this task. 19 1 read-write TASK_OVF_CNT_RST_CH4_EN Ledc ch4 overflow count reset task enable register, write 1 to enable this task. 20 1 read-write TASK_OVF_CNT_RST_CH5_EN Ledc ch5 overflow count reset task enable register, write 1 to enable this task. 21 1 read-write TASK_TIMER0_RST_EN Ledc timer0 reset task enable register, write 1 to enable this task. 24 1 read-write TASK_TIMER1_RST_EN Ledc timer1 reset task enable register, write 1 to enable this task. 25 1 read-write TASK_TIMER2_RST_EN Ledc timer2 reset task enable register, write 1 to enable this task. 26 1 read-write TASK_TIMER3_RST_EN Ledc timer3 reset task enable register, write 1 to enable this task. 27 1 read-write TASK_TIMER0_PAUSE_RESUME_EN Ledc timer0 pause resume task enable register, write 1 to enable this task. 28 1 read-write TASK_TIMER1_PAUSE_RESUME_EN Ledc timer1 pause resume task enable register, write 1 to enable this task. 29 1 read-write TASK_TIMER2_PAUSE_RESUME_EN Ledc timer2 pause resume task enable register, write 1 to enable this task. 30 1 read-write TASK_TIMER3_PAUSE_RESUME_EN Ledc timer3 pause resume task enable register, write 1 to enable this task. 31 1 read-write EVT_TASK_EN2 Ledc event task enable bit register2. 0x1A8 0x20 TASK_GAMMA_RESTART_CH0_EN Ledc ch0 gamma restart task enable register, write 1 to enable this task. 0 1 read-write TASK_GAMMA_RESTART_CH1_EN Ledc ch1 gamma restart task enable register, write 1 to enable this task. 1 1 read-write TASK_GAMMA_RESTART_CH2_EN Ledc ch2 gamma restart task enable register, write 1 to enable this task. 2 1 read-write TASK_GAMMA_RESTART_CH3_EN Ledc ch3 gamma restart task enable register, write 1 to enable this task. 3 1 read-write TASK_GAMMA_RESTART_CH4_EN Ledc ch4 gamma restart task enable register, write 1 to enable this task. 4 1 read-write TASK_GAMMA_RESTART_CH5_EN Ledc ch5 gamma restart task enable register, write 1 to enable this task. 5 1 read-write TASK_GAMMA_PAUSE_CH0_EN Ledc ch0 gamma pause task enable register, write 1 to enable this task. 8 1 read-write TASK_GAMMA_PAUSE_CH1_EN Ledc ch1 gamma pause task enable register, write 1 to enable this task. 9 1 read-write TASK_GAMMA_PAUSE_CH2_EN Ledc ch2 gamma pause task enable register, write 1 to enable this task. 10 1 read-write TASK_GAMMA_PAUSE_CH3_EN Ledc ch3 gamma pause task enable register, write 1 to enable this task. 11 1 read-write TASK_GAMMA_PAUSE_CH4_EN Ledc ch4 gamma pause task enable register, write 1 to enable this task. 12 1 read-write TASK_GAMMA_PAUSE_CH5_EN Ledc ch5 gamma pause task enable register, write 1 to enable this task. 13 1 read-write TASK_GAMMA_RESUME_CH0_EN Ledc ch0 gamma resume task enable register, write 1 to enable this task. 16 1 read-write TASK_GAMMA_RESUME_CH1_EN Ledc ch1 gamma resume task enable register, write 1 to enable this task. 17 1 read-write TASK_GAMMA_RESUME_CH2_EN Ledc ch2 gamma resume task enable register, write 1 to enable this task. 18 1 read-write TASK_GAMMA_RESUME_CH3_EN Ledc ch3 gamma resume task enable register, write 1 to enable this task. 19 1 read-write TASK_GAMMA_RESUME_CH4_EN Ledc ch4 gamma resume task enable register, write 1 to enable this task. 20 1 read-write TASK_GAMMA_RESUME_CH5_EN Ledc ch5 gamma resume task enable register, write 1 to enable this task. 21 1 read-write 4 0x4 TIMER%s_CMP Ledc timer%s compare value register. 0x1B0 0x20 TIMER_CMP This register stores ledc timer%s compare value. 0 20 read-write 4 0x4 TIMER%s_CNT_CAP Ledc timer%s count value capture register. 0x1C0 0x20 TIMER_CNT_CAP This register stores ledc timer%s count value. 0 20 read-only CONF Global ledc configuration register 0x1F0 0x20 APB_CLK_SEL This bit is used to select clock source for the 4 timers . 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK 0 2 read-write GAMMA_RAM_CLK_EN_CH0 This bit is used to control clock. 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. 2 1 read-write GAMMA_RAM_CLK_EN_CH1 This bit is used to control clock. 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. 3 1 read-write GAMMA_RAM_CLK_EN_CH2 This bit is used to control clock. 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. 4 1 read-write GAMMA_RAM_CLK_EN_CH3 This bit is used to control clock. 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. 5 1 read-write GAMMA_RAM_CLK_EN_CH4 This bit is used to control clock. 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. 6 1 read-write GAMMA_RAM_CLK_EN_CH5 This bit is used to control clock. 1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram. 7 1 read-write CLK_EN This bit is used to control clock. 1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers. 31 1 read-write DATE Version control register 0x1FC 0x20 0x02111150 LEDC_DATE This is the version control register. 0 28 read-write PCNT Pulse Counter PCNT 0x60017000 0x0 0x68 registers 4 0xC U%s_CONF0 Configuration register 0 for unit %s 0x0 0x20 0x00003C10 FILTER_THRES_U This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled. 0 10 read-write FILTER_EN_U This is the enable bit for unit %s's input filter. 10 1 read-write THR_ZERO_EN_U This is the enable bit for unit %s's zero comparator. 11 1 read-write THR_H_LIM_EN_U This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt. 12 1 read-write THR_L_LIM_EN_U This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt. 13 1 read-write THR_THRES0_EN_U This is the enable bit for unit %s's thres0 comparator. 14 1 read-write THR_THRES1_EN_U This is the enable bit for unit %s's thres1 comparator. 15 1 read-write CH0_NEG_MODE_U This register sets the behavior when the signal input of channel 0 detects a negative edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter 16 2 read-write CH0_POS_MODE_U This register sets the behavior when the signal input of channel 0 detects a positive edge. 1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter 18 2 read-write CH0_HCTRL_MODE_U This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification 20 2 read-write CH0_LCTRL_MODE_U This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification 22 2 read-write CH1_NEG_MODE_U This register sets the behavior when the signal input of channel 1 detects a negative edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter 24 2 read-write CH1_POS_MODE_U This register sets the behavior when the signal input of channel 1 detects a positive edge. 1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter 26 2 read-write CH1_HCTRL_MODE_U This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification 28 2 read-write CH1_LCTRL_MODE_U This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low. 0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification 30 2 read-write 4 0xC U%s_CONF1 Configuration register 1 for unit %s 0x4 0x20 CNT_THRES0_U This register is used to configure the thres0 value for unit %s. 0 16 read-write CNT_THRES1_U This register is used to configure the thres1 value for unit %s. 16 16 read-write 4 0xC U%s_CONF2 Configuration register 2 for unit %s 0x8 0x20 CNT_H_LIM_U This register is used to configure the thr_h_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. 0 16 read-write CNT_L_LIM_U This register is used to configure the thr_l_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0. 16 16 read-write 4 0x4 U%s_CNT Counter value for unit %s 0x30 0x20 PULSE_CNT_U This register stores the current pulse count value for unit %s. 0 16 read-only INT_RAW Interrupt raw status register 0x40 0x20 CNT_THR_EVENT_U0_INT_RAW The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only CNT_THR_EVENT_U1_INT_RAW The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only CNT_THR_EVENT_U2_INT_RAW The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only CNT_THR_EVENT_U3_INT_RAW The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 read-only INT_ST Interrupt status register 0x44 0x20 CNT_THR_EVENT_U0_INT_ST The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-only CNT_THR_EVENT_U1_INT_ST The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-only CNT_THR_EVENT_U2_INT_ST The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-only CNT_THR_EVENT_U3_INT_ST The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 read-only INT_ENA Interrupt enable register 0x48 0x20 CNT_THR_EVENT_U0_INT_ENA The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 read-write CNT_THR_EVENT_U1_INT_ENA The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 read-write CNT_THR_EVENT_U2_INT_ENA The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 read-write CNT_THR_EVENT_U3_INT_ENA The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 read-write INT_CLR Interrupt clear register 0x4C 0x20 CNT_THR_EVENT_U0_INT_CLR Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. 0 1 write-only CNT_THR_EVENT_U1_INT_CLR Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. 1 1 write-only CNT_THR_EVENT_U2_INT_CLR Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. 2 1 write-only CNT_THR_EVENT_U3_INT_CLR Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. 3 1 write-only 4 0x4 U%s_STATUS PNCT UNIT%s status register 0x50 0x20 CNT_THR_ZERO_MODE_U The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive. 0 2 read-only CNT_THR_THRES1_LAT_U The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others 2 1 read-only CNT_THR_THRES0_LAT_U The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others 3 1 read-only CNT_THR_L_LIM_LAT_U The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others 4 1 read-only CNT_THR_H_LIM_LAT_U The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others 5 1 read-only CNT_THR_ZERO_LAT_U The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others 6 1 read-only CTRL Control register for all counters 0x60 0x20 0x00000001 PULSE_CNT_RST_U0 Set this bit to clear unit 0's counter. 0 1 read-write CNT_PAUSE_U0 Set this bit to freeze unit 0's counter. 1 1 read-write PULSE_CNT_RST_U1 Set this bit to clear unit 1's counter. 2 1 read-write CNT_PAUSE_U1 Set this bit to freeze unit 1's counter. 3 1 read-write PULSE_CNT_RST_U2 Set this bit to clear unit 2's counter. 4 1 read-write CNT_PAUSE_U2 Set this bit to freeze unit 2's counter. 5 1 read-write PULSE_CNT_RST_U3 Set this bit to clear unit 3's counter. 6 1 read-write CNT_PAUSE_U3 Set this bit to freeze unit 3's counter. 7 1 read-write CLK_EN The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application 16 1 read-write DATE PCNT version control register 0xFC 0x20 0x18072600 DATE This is the PCNT version control register. 0 32 read-write RMT Remote Control Peripheral RMT 0x60016000 0x0 0x78 registers RMT 28 4 0x4 TX_CH%sDATA The read and write data register for CHANNEL%s by apb fifo access. 0x0 0x20 CHDATA Read and write data for channel %s via APB FIFO. 0 32 read-only 2 0x4 TX_CH%sCONF0 Channel %s configure register 0 0x10 0x20 0x00710200 TX_START_CH0 Set this bit to start sending data on CHANNEL%s. 0 1 write-only MEM_RD_RST_CH0 Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. 1 1 write-only APB_MEM_RST_CH0 Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. 2 1 write-only TX_CONTI_MODE_CH0 Set this bit to restart transmission from the first data to the last data in CHANNEL%s. 3 1 read-write MEM_TX_WRAP_EN_CH0 This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size. 4 1 read-write IDLE_OUT_LV_CH0 This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. 5 1 read-write IDLE_OUT_EN_CH0 This is the output enable-control bit for CHANNEL%s in IDLE state. 6 1 read-write TX_STOP_CH0 Set this bit to stop the transmitter of CHANNEL%s sending data out. 7 1 read-write DIV_CNT_CH0 This register is used to configure the divider for clock of CHANNEL%s. 8 8 read-write MEM_SIZE_CH0 This register is used to configure the maximum size of memory allocated to CHANNEL%s. 16 3 read-write CARRIER_EFF_EN_CH0 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1. 20 1 read-write CARRIER_EN_CH0 This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. 21 1 read-write CARRIER_OUT_LV_CH0 This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level. 22 1 read-write AFIFO_RST_CH0 Reserved 23 1 write-only CONF_UPDATE_CH0 synchronization bit for CHANNEL%s 24 1 write-only 2 0x8 RX_CH%sCONF0 Channel %s configure register 0 0x18 0x20 0x30FFFF02 DIV_CNT_CH2 This register is used to configure the divider for clock of CHANNEL%s. 0 8 read-write IDLE_THRES_CH2 When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished. 8 15 read-write MEM_SIZE_CH2 This register is used to configure the maximum size of memory allocated to CHANNEL%s. 23 3 read-write CARRIER_EN_CH2 This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out. 28 1 read-write CARRIER_OUT_LV_CH2 This bit is used to configure the position of carrier wave for CHANNEL%s. 1'h0: add carrier wave on low level. 1'h1: add carrier wave on high level. 29 1 read-write 2 0x8 RX_CH%sCONF1 Channel %s configure register 1 0x1C 0x20 0x000001E8 RX_EN_CH2 Set this bit to enable receiver to receive data on CHANNEL%s. 0 1 read-write MEM_WR_RST_CH2 Set this bit to reset write ram address for CHANNEL%s by accessing receiver. 1 1 write-only APB_MEM_RST_CH2 Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. 2 1 write-only MEM_OWNER_CH2 This register marks the ownership of CHANNEL%s's ram block. 1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram. 3 1 read-write RX_FILTER_EN_CH2 This is the receive filter's enable bit for CHANNEL%s. 4 1 read-write RX_FILTER_THRES_CH2 Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). 5 8 read-write MEM_RX_WRAP_EN_CH2 This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size. 13 1 read-write AFIFO_RST_CH2 Reserved 14 1 write-only CONF_UPDATE_CH2 synchronization bit for CHANNEL%s 15 1 write-only 2 0x4 TX_CH%sSTATUS Channel %s status register 0x28 0x20 MEM_RADDR_EX_CH0 This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. 0 9 read-only STATE_CH0 This register records the FSM status of CHANNEL%s. 9 3 read-only APB_MEM_WADDR_CH0 This register records the memory address offset when writes RAM over APB bus. 12 9 read-only APB_MEM_RD_ERR_CH0 This status bit will be set if the offset address out of memory size when reading via APB bus. 21 1 read-only MEM_EMPTY_CH0 This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. 22 1 read-only APB_MEM_WR_ERR_CH0 This status bit will be set if the offset address out of memory size when writes via APB bus. 23 1 read-only APB_MEM_RADDR_CH0 This register records the memory address offset when reading RAM over APB bus. 24 8 read-only 2 0x4 RX_CH%sSTATUS Channel %s status register 0x30 0x20 MEM_WADDR_EX_CH2 This register records the memory address offset when receiver of CHANNEL%s is using the RAM. 0 9 read-only APB_MEM_RADDR_CH2 This register records the memory address offset when reads RAM over APB bus. 12 9 read-only STATE_CH2 This register records the FSM status of CHANNEL%s. 22 3 read-only MEM_OWNER_ERR_CH2 This status bit will be set when the ownership of memory block is wrong. 25 1 read-only MEM_FULL_CH2 This status bit will be set if the receiver receives more data than the memory size. 26 1 read-only APB_MEM_RD_ERR_CH2 This status bit will be set if the offset address out of memory size when reads via APB bus. 27 1 read-only INT_RAW Raw interrupt status 0x38 0x20 CH0_TX_END_INT_RAW The interrupt raw bit for CHANNEL0. Triggered when transmission done. 0 1 read-only CH1_TX_END_INT_RAW The interrupt raw bit for CHANNEL1. Triggered when transmission done. 1 1 read-only CH2_RX_END_INT_RAW The interrupt raw bit for CHANNEL2. Triggered when reception done. 2 1 read-only CH3_RX_END_INT_RAW The interrupt raw bit for CHANNEL3. Triggered when reception done. 3 1 read-only TX_CH0_ERR_INT_RAW The interrupt raw bit for CHANNEL4. Triggered when error occurs. 4 1 read-only TX_CH1_ERR_INT_RAW The interrupt raw bit for CHANNEL5. Triggered when error occurs. 5 1 read-only TX_CH2_ERR_INT_RAW The interrupt raw bit for CHANNEL6. Triggered when error occurs. 6 1 read-only TX_CH3_ERR_INT_RAW The interrupt raw bit for CHANNEL7. Triggered when error occurs. 7 1 read-only CH0_TX_THR_EVENT_INT_RAW The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. 8 1 read-only CH1_TX_THR_EVENT_INT_RAW The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. 9 1 read-only CH2_RX_THR_EVENT_INT_RAW The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. 10 1 read-only CH3_RX_THR_EVENT_INT_RAW The interrupt raw bit for CHANNEL3. Triggered when receiver receive more data than configured value. 11 1 read-only CH0_TX_LOOP_INT_RAW The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. 12 1 read-only CH1_TX_LOOP_INT_RAW The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. 13 1 read-only INT_ST Masked interrupt status 0x3C 0x20 CH0_TX_END_INT_ST The masked interrupt status bit for CH0_TX_END_INT. 0 1 read-only CH1_TX_END_INT_ST The masked interrupt status bit for CH1_TX_END_INT. 1 1 read-only CH2_RX_END_INT_ST The masked interrupt status bit for CH2_RX_END_INT. 2 1 read-only CH3_RX_END_INT_ST The masked interrupt status bit for CH3_RX_END_INT. 3 1 read-only RX_CH0_ERR_INT_ST The masked interrupt status bit for CH4_ERR_INT. 4 1 read-only RX_CH1_ERR_INT_ST The masked interrupt status bit for CH5_ERR_INT. 5 1 read-only RX_CH2_ERR_INT_ST The masked interrupt status bit for CH6_ERR_INT. 6 1 read-only RX_CH3_ERR_INT_ST The masked interrupt status bit for CH7_ERR_INT. 7 1 read-only CH0_TX_THR_EVENT_INT_ST The masked interrupt status bit for CH0_TX_THR_EVENT_INT. 8 1 read-only CH1_TX_THR_EVENT_INT_ST The masked interrupt status bit for CH1_TX_THR_EVENT_INT. 9 1 read-only CH2_RX_THR_EVENT_INT_ST The masked interrupt status bit for CH2_RX_THR_EVENT_INT. 10 1 read-only CH3_RX_THR_EVENT_INT_ST The masked interrupt status bit for CH3_RX_THR_EVENT_INT. 11 1 read-only CH0_TX_LOOP_INT_ST The masked interrupt status bit for CH0_TX_LOOP_INT. 12 1 read-only CH1_TX_LOOP_INT_ST The masked interrupt status bit for CH1_TX_LOOP_INT. 13 1 read-only INT_ENA Interrupt enable bits 0x40 0x20 CH0_TX_END_INT_ENA The interrupt enable bit for CH0_TX_END_INT. 0 1 read-write CH1_TX_END_INT_ENA The interrupt enable bit for CH1_TX_END_INT. 1 1 read-write CH2_RX_END_INT_ENA The interrupt enable bit for CH2_RX_END_INT. 2 1 read-write CH3_RX_END_INT_ENA The interrupt enable bit for CH3_RX_END_INT. 3 1 read-write CH0_ERR_INT_ENA The interrupt enable bit for CH4_ERR_INT. 4 1 read-write CH1_ERR_INT_ENA The interrupt enable bit for CH5_ERR_INT. 5 1 read-write CH2_ERR_INT_ENA The interrupt enable bit for CH6_ERR_INT. 6 1 read-write CH3_ERR_INT_ENA The interrupt enable bit for CH7_ERR_INT. 7 1 read-write CH0_TX_THR_EVENT_INT_ENA The interrupt enable bit for CH0_TX_THR_EVENT_INT. 8 1 read-write CH1_TX_THR_EVENT_INT_ENA The interrupt enable bit for CH1_TX_THR_EVENT_INT. 9 1 read-write CH2_RX_THR_EVENT_INT_ENA The interrupt enable bit for CH2_RX_THR_EVENT_INT. 10 1 read-write CH3_RX_THR_EVENT_INT_ENA The interrupt enable bit for CH3_RX_THR_EVENT_INT. 11 1 read-write CH0_TX_LOOP_INT_ENA The interrupt enable bit for CH0_TX_LOOP_INT. 12 1 read-write CH1_TX_LOOP_INT_ENA The interrupt enable bit for CH1_TX_LOOP_INT. 13 1 read-write INT_CLR Interrupt clear bits 0x44 0x20 CH0_TX_END_INT_CLR Set this bit to clear theCH0_TX_END_INT interrupt. 0 1 write-only CH1_TX_END_INT_CLR Set this bit to clear theCH1_TX_END_INT interrupt. 1 1 write-only CH2_RX_END_INT_CLR Set this bit to clear theCH2_RX_END_INT interrupt. 2 1 write-only CH3_RX_END_INT_CLR Set this bit to clear theCH3_RX_END_INT interrupt. 3 1 write-only RX_CH0_ERR_INT_CLR Set this bit to clear theCH4_ERR_INT interrupt. 4 1 write-only RX_CH1_ERR_INT_CLR Set this bit to clear theCH5_ERR_INT interrupt. 5 1 write-only RX_CH2_ERR_INT_CLR Set this bit to clear theCH6_ERR_INT interrupt. 6 1 write-only RX_CH3_ERR_INT_CLR Set this bit to clear theCH7_ERR_INT interrupt. 7 1 write-only CH0_TX_THR_EVENT_INT_CLR Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. 8 1 write-only CH1_TX_THR_EVENT_INT_CLR Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. 9 1 write-only CH2_RX_THR_EVENT_INT_CLR Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. 10 1 write-only CH3_RX_THR_EVENT_INT_CLR Set this bit to clear theCH3_RX_THR_EVENT_INT interrupt. 11 1 write-only CH0_TX_LOOP_INT_CLR Set this bit to clear theCH0_TX_LOOP_INT interrupt. 12 1 write-only CH1_TX_LOOP_INT_CLR Set this bit to clear theCH1_TX_LOOP_INT interrupt. 13 1 write-only 2 0x4 CH%sCARRIER_DUTY Channel %s duty cycle configuration register 0x48 0x20 0x00400040 CARRIER_LOW_CH0 This register is used to configure carrier wave 's low level clock period for CHANNEL%s. 0 16 read-write CARRIER_HIGH_CH0 This register is used to configure carrier wave 's high level clock period for CHANNEL%s. 16 16 read-write 2 0x4 CH%s_RX_CARRIER_RM Channel %s carrier remove register 0x50 0x20 CARRIER_LOW_THRES_CH2 The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. 0 16 read-write CARRIER_HIGH_THRES_CH2 The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. 16 16 read-write 2 0x4 CH%s_TX_LIM Channel %s Tx event configuration register 0x58 0x20 0x00000080 TX_LIM_CH0 This register is used to configure the maximum entries that CHANNEL%s can send out. 0 9 read-write TX_LOOP_NUM_CH0 This register is used to configure the maximum loop count when tx_conti_mode is valid. 9 10 read-write TX_LOOP_CNT_EN_CH0 This register is the enabled bit for loop count. 19 1 read-write LOOP_COUNT_RESET_CH0 This register is used to reset the loop count when tx_conti_mode is valid. 20 1 write-only LOOP_STOP_EN_CH0 This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. 21 1 read-write 2 0x4 CH%s_RX_LIM Channel %s Rx event configuration register 0x60 0x20 0x00000080 RMT_RX_LIM_CH2 This register is used to configure the maximum entries that CHANNEL%s can receive. 0 9 read-write SYS_CONF RMT apb configuration register 0x68 0x20 0x05000010 APB_FIFO_MASK 1'h1: access memory directly. 1'h0: access memory by FIFO. 0 1 read-write MEM_CLK_FORCE_ON Set this bit to enable the clock for RMT memory. 1 1 read-write RMT_MEM_FORCE_PD Set this bit to power down RMT memory. 2 1 read-write RMT_MEM_FORCE_PU 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode. 3 1 read-write RMT_SCLK_DIV_NUM the integral part of the fractional divisor 4 8 read-write RMT_SCLK_DIV_A the numerator of the fractional part of the fractional divisor 12 6 read-write RMT_SCLK_DIV_B the denominator of the fractional part of the fractional divisor 18 6 read-write RMT_SCLK_SEL choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL 24 2 read-write RMT_SCLK_ACTIVE rmt_sclk switch 26 1 read-write CLK_EN RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers 31 1 read-write TX_SIM RMT TX synchronous register 0x6C 0x20 CH0 Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. 0 1 read-write CH1 Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. 1 1 read-write EN This register is used to enable multiple of channels to start sending data synchronously. 2 1 read-write REF_CNT_RST RMT clock divider reset register 0x70 0x20 TX_REF_CNT_RST_CH0 This register is used to reset the clock divider of CHANNEL0. 0 1 write-only TX_REF_CNT_RST_CH1 This register is used to reset the clock divider of CHANNEL1. 1 1 write-only RX_REF_CNT_RST_CH2 This register is used to reset the clock divider of CHANNEL2. 2 1 write-only RX_REF_CNT_RST_CH3 This register is used to reset the clock divider of CHANNEL3. 3 1 write-only DATE RMT version register 0xCC 0x20 0x02108213 RMT_DATE This is the version register. 0 28 read-write RNG Hardware random number generator RNG 0x600260B0 0x0 0x4 registers DATA Random number data 0x0 0x20 RSA RSA (Rivest Shamir Adleman) Accelerator RSA 0x6003C000 0x0 0x74 registers RSA 47 16 0x1 M_MEM[%s] Represents M 0x0 0x8 16 0x1 Z_MEM[%s] Represents Z 0x200 0x8 16 0x1 Y_MEM[%s] Represents Y 0x400 0x8 16 0x1 X_MEM[%s] Represents X 0x600 0x8 M_PRIME Represents M’ 0x800 0x20 M_PRIME Represents M’ 0 32 read-write MODE Configures RSA length 0x804 0x20 MODE Configures the RSA length. 0 7 read-write QUERY_CLEAN RSA clean register 0x808 0x20 QUERY_CLEAN Represents whether or not the RSA memory completes initialization. 0: Not complete 1: Completed 0 1 read-only SET_START_MODEXP Starts modular exponentiation 0x80C 0x20 SET_START_MODEXP Configure whether or not to start the modular exponentiation. 0: No effect 1: Start 0 1 write-only SET_START_MODMULT Starts modular multiplication 0x810 0x20 SET_START_MODMULT Configure whether or not to start the modular multiplication. 0: No effect 1: Start 0 1 write-only SET_START_MULT Starts multiplication 0x814 0x20 SET_START_MULT Configure whether or not to start the multiplication. 0: No effect 1: Start 0 1 write-only QUERY_IDLE Represents the RSA status 0x818 0x20 QUERY_IDLE Represents the RSA status. 0: Busy 1: Idle 0 1 read-only INT_CLR Clears RSA interrupt 0x81C 0x20 CLEAR_INTERRUPT Write 1 to clear the RSA interrupt. 0 1 write-only CONSTANT_TIME Configures the constant_time option 0x820 0x20 0x00000001 CONSTANT_TIME Configures the constant_time option. 0: Acceleration 1: No acceleration (default) 0 1 read-write SEARCH_ENABLE Configures the search option 0x824 0x20 SEARCH_ENABLE Configure the search option. 0: No acceleration (default) 1: Acceleration This option should be used together with RSA_SEARCH_POS. 0 1 read-write SEARCH_POS Configures the search position 0x828 0x20 SEARCH_POS Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. 0 12 read-write INT_ENA Enables the RSA interrupt 0x82C 0x20 INT_ENA Write 1 to enable the RSA interrupt. 0 1 read-write DATE Version control register 0x830 0x20 0x20200618 DATE Version control register. 0 30 read-write SHA SHA (Secure Hash Algorithm) Accelerator SHA 0x6003B000 0x0 0xB0 registers SHA 49 MODE Initial configuration register. 0x0 0x20 MODE Sha mode. 0 3 read-write T_STRING SHA 512/t configuration register 0. 0x4 0x20 T_STRING Sha t_string (used if and only if mode == SHA_512/t). 0 32 read-write T_LENGTH SHA 512/t configuration register 1. 0x8 0x20 T_LENGTH Sha t_length (used if and only if mode == SHA_512/t). 0 6 read-write DMA_BLOCK_NUM DMA configuration register 0. 0xC 0x20 DMA_BLOCK_NUM Dma-sha block number. 0 6 read-write START Typical SHA configuration register 0. 0x10 0x20 START Reserved. 1 31 read-only CONTINUE Typical SHA configuration register 1. 0x14 0x20 CONTINUE Reserved. 1 31 read-only BUSY Busy register. 0x18 0x20 STATE Sha busy state. 1'b0: idle. 1'b1: busy. 0 1 read-only DMA_START DMA configuration register 1. 0x1C 0x20 DMA_START Start dma-sha. 0 1 write-only DMA_CONTINUE DMA configuration register 2. 0x20 0x20 DMA_CONTINUE Continue dma-sha. 0 1 write-only CLEAR_IRQ Interrupt clear register. 0x24 0x20 CLEAR_INTERRUPT Clear sha interrupt. 0 1 write-only IRQ_ENA Interrupt enable register. 0x28 0x20 INTERRUPT_ENA Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable. 0 1 read-write DATE Date register. 0x2C 0x20 0x20201229 DATE Sha date information/ sha version information. 0 30 read-write 64 0x1 H_MEM[%s] Sha H memory which contains intermediate hash or finial hash. 0x40 0x8 64 0x1 M_MEM[%s] Sha M memory which contains message. 0x80 0x8 SPI0 SPI (Serial Peripheral Interface) Controller SPI0 0x60003000 0x0 0x138 registers SPI_MEM_REJECT_CACHE 40 SPI_MEM_CMD SPI0 FSM status register 0x0 0x20 SPI_MEM_MST_ST The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state. 0 4 read-only SPI_MEM_SLV_ST The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. 4 4 read-only SPI_MEM_USR SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 18 1 read-only SPI_MEM_CTRL SPI0 control register. 0x8 0x20 0x802C200C SPI_MEM_WDUMMY_DQS_ALWAYS_OUT In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller. 0 1 read-only SPI_MEM_WDUMMY_ALWAYS_OUT In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller. 1 1 read-write SPI_MEM_FDUMMY_RIN In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase. 2 1 read-write SPI_MEM_FDUMMY_WOUT In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash. 3 1 read-write SPI_MEM_FDOUT_OCT Apply 8 signals during write-data phase 1:enable 0: disable 4 1 read-only SPI_MEM_FDIN_OCT Apply 8 signals during read-data phase 1:enable 0: disable 5 1 read-only SPI_MEM_FADDR_OCT Apply 8 signals during address phase 1:enable 0: disable 6 1 read-only SPI_MEM_FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable 8 1 read-write SPI_MEM_FCMD_OCT Apply 8 signals during command phase 1:enable 0: disable 9 1 read-only SPI_MEM_FASTRD_MODE This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. 13 1 read-write SPI_MEM_FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. 14 1 read-write SPI_MEM_Q_POL The bit is used to set MISO line polarity, 1: high 0, low 18 1 read-write SPI_MEM_D_POL The bit is used to set MOSI line polarity, 1: high 0, low 19 1 read-write SPI_MEM_FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. 20 1 read-write SPI_MEM_WP Write protect signal output when SPI is idle. 1: output high, 0: output low. 21 1 read-write SPI_MEM_FREAD_DIO In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. 23 1 read-write SPI_MEM_FREAD_QIO In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. 24 1 read-write SPI_MEM_DQS_IE_ALWAYS_ON When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. 30 1 read-only SPI_MEM_DATA_IE_ALWAYS_ON When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. 31 1 read-write SPI_MEM_CTRL1 SPI0 control1 register. 0xC 0x20 0x28E00000 SPI_MEM_CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. 0 2 read-write SPI_AR_SIZE0_1_SUPPORT_EN 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. 21 1 read-write SPI_AW_SIZE0_1_SUPPORT_EN 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. 22 1 read-write SPI_AXI_RDATA_BACK_FAST 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available. 23 1 read-only SPI_MEM_RRESP_ECC_ERR_EN 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG. 24 1 read-write SPI_MEM_AR_SPLICE_EN Set this bit to enable AXI Read Splice-transfer. 25 1 read-only SPI_MEM_AW_SPLICE_EN Set this bit to enable AXI Write Splice-transfer. 26 1 read-only SPI_MEM_RAM0_EN When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. 27 1 read-only SPI_MEM_DUAL_RAM_EN Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time. 28 1 read-only SPI_MEM_FAST_WRITE_EN Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2. 29 1 read-write SPI_MEM_RXFIFO_RST The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. 30 1 write-only SPI_MEM_TXFIFO_RST The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. 31 1 write-only SPI_MEM_CTRL2 SPI0 control2 register. 0x10 0x20 0x00002C21 SPI_MEM_CS_SETUP_TIME (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit. 0 5 read-write SPI_MEM_CS_HOLD_TIME SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit. 5 5 read-write SPI_MEM_ECC_CS_HOLD_TIME SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. 10 3 read-only SPI_MEM_ECC_SKIP_PAGE_CORNER 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash. 13 1 read-only SPI_MEM_ECC_16TO18_BYTE_EN Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. 14 1 read-only SPI_MEM_SPLIT_TRANS_EN Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not. 24 1 read-only SPI_MEM_CS_HOLD_DELAY These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. 25 6 read-write SPI_MEM_SYNC_RESET The spi0_mst_st and spi0_slv_st will be reset. 31 1 write-only SPI_MEM_CLOCK SPI clock division control register. 0x14 0x20 0x00030103 SPI_MEM_CLKCNT_L In the master mode it must be equal to spi_mem_clkcnt_N. 0 8 read-write SPI_MEM_CLKCNT_H In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). 8 8 read-write SPI_MEM_CLKCNT_N In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) 16 8 read-write SPI_MEM_CLK_EQU_SYSCLK 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock. 31 1 read-write SPI_MEM_USER SPI0 user register. 0x18 0x20 SPI_MEM_CS_HOLD spi cs keep low when spi is in done phase. 1: enable 0: disable. 6 1 read-write SPI_MEM_CS_SETUP spi cs is enable when spi is in prepare phase. 1: enable 0: disable. 7 1 read-write SPI_MEM_CK_OUT_EDGE The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. 9 1 read-write SPI_MEM_USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. 26 1 read-write SPI_MEM_USR_DUMMY This bit enable the dummy phase of an operation. 29 1 read-write SPI_MEM_USER1 SPI0 user1 register. 0x1C 0x20 0x5C000047 SPI_MEM_USR_DUMMY_CYCLELEN The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). 0 6 read-write SPI_MEM_USR_DBYTELEN SPI0 USR_CMD read or write data byte length -1 6 3 read-only SPI_MEM_USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). 26 6 read-write SPI_MEM_USER2 SPI0 user2 register. 0x20 0x20 0x70000000 SPI_MEM_USR_COMMAND_VALUE The value of command. 0 16 read-write SPI_MEM_USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1) 28 4 read-write SPI_MEM_RD_STATUS SPI0 read control register. 0x2C 0x20 SPI_MEM_WB_MODE Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. 16 8 read-write SPI_MEM_MISC SPI0 misc register 0x34 0x20 SPI_MEM_FSUB_PIN For SPI0, flash is connected to SUBPINs. 7 1 read-only SPI_MEM_SSUB_PIN For SPI0, sram is connected to SUBPINs. 8 1 read-only SPI_MEM_CK_IDLE_EDGE 1: SPI_CLK line is high when idle 0: spi clk line is low when idle 9 1 read-write SPI_MEM_CS_KEEP_ACTIVE SPI_CS line keep low when the bit is set. 10 1 read-write SPI_MEM_CACHE_FCTRL SPI0 bit mode control register. 0x3C 0x20 0xC0000000 SPI_MEM_AXI_REQ_EN For SPI0, AXI master access enable, 1: enable, 0:disable. 0 1 read-write SPI_MEM_CACHE_USR_ADDR_4BYTE For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. 1 1 read-write SPI_MEM_CACHE_FLASH_USR_CMD For SPI0, cache read flash for user define command, 1: enable, 0:disable. 2 1 read-write SPI_MEM_FDIN_DUAL For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 3 1 read-write SPI_MEM_FDOUT_DUAL For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 4 1 read-write SPI_MEM_FADDR_DUAL For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 5 1 read-write SPI_MEM_FDIN_QUAD For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 6 1 read-write SPI_MEM_FDOUT_QUAD For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 7 1 read-write SPI_MEM_FADDR_QUAD For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 8 1 read-write SPI_SAME_AW_AR_ADDR_CHK_EN Set this bit to check AXI read/write the same address region. 30 1 read-only SPI_CLOSE_AXI_INF_EN Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP. 31 1 read-write SPI_MEM_CACHE_SCTRL SPI0 external RAM control register 0x40 0x20 0x0055C070 SPI_MEM_CACHE_USR_SADDR_4BYTE For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable. 0 1 read-only SPI_MEM_USR_SRAM_DIO For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable 1 1 read-only SPI_MEM_USR_SRAM_QIO For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable 2 1 read-only SPI_MEM_USR_WR_SRAM_DUMMY For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations. 3 1 read-only SPI_MEM_USR_RD_SRAM_DUMMY For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations. 4 1 read-only SPI_MEM_CACHE_SRAM_USR_RCMD For SPI0, In the external RAM mode cache read external RAM for user define command. 5 1 read-only SPI_MEM_SRAM_RDUMMY_CYCLELEN For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1). 6 6 read-only SPI_MEM_SRAM_ADDR_BITLEN For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1). 14 6 read-only SPI_MEM_CACHE_SRAM_USR_WCMD For SPI0, In the external RAM mode cache write sram for user define command 20 1 read-only SPI_MEM_SRAM_OCT reserved 21 1 read-only SPI_MEM_SRAM_WDUMMY_CYCLELEN For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1). 22 6 read-only SPI_MEM_SRAM_CMD SPI0 external RAM mode control register 0x44 0x20 0xC0400000 SPI_MEM_SCLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. 0 2 read-only SPI_MEM_SWB_MODE Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. 2 8 read-only SPI_MEM_SDIN_DUAL For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. 10 1 read-only SPI_MEM_SDOUT_DUAL For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. 11 1 read-only SPI_MEM_SADDR_DUAL For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio. 12 1 read-only SPI_MEM_SDIN_QUAD For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. 14 1 read-only SPI_MEM_SDOUT_QUAD For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. 15 1 read-only SPI_MEM_SADDR_QUAD For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. 16 1 read-only SPI_MEM_SCMD_QUAD For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio. 17 1 read-only SPI_MEM_SDIN_OCT For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. 18 1 read-only SPI_MEM_SDOUT_OCT For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. 19 1 read-only SPI_MEM_SADDR_OCT For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. 20 1 read-only SPI_MEM_SCMD_OCT For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. 21 1 read-only SPI_MEM_SDUMMY_RIN In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. 22 1 read-write SPI_MEM_SDUMMY_WOUT In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller. 23 1 read-only SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller. 24 1 read-only SPI_SMEM_WDUMMY_ALWAYS_OUT In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller. 25 1 read-only SPI_SMEM_DQS_IE_ALWAYS_ON When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others. 30 1 read-only SPI_SMEM_DATA_IE_ALWAYS_ON When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others. 31 1 read-only SPI_MEM_SRAM_DRD_CMD SPI0 external RAM DDR read command control register 0x48 0x20 SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE For SPI0,When cache mode is enable it is the read command value of command phase for sram. 0 16 read-only SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1). 28 4 read-only SPI_MEM_SRAM_DWR_CMD SPI0 external RAM DDR write command control register 0x4C 0x20 SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE For SPI0,When cache mode is enable it is the write command value of command phase for sram. 0 16 read-only SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1). 28 4 read-only SPI_MEM_SRAM_CLK SPI0 external RAM clock control register 0x50 0x20 0x00030103 SPI_MEM_SCLKCNT_L For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. 0 8 read-only SPI_MEM_SCLKCNT_H For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). 8 8 read-only SPI_MEM_SCLKCNT_N For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) 16 8 read-only SPI_MEM_SCLK_EQU_SYSCLK For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock. 31 1 read-only SPI_MEM_FSM SPI0 FSM status register 0x54 0x20 0x00000200 SPI_MEM_LOCK_DELAY_TIME The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. 7 5 read-write SPI_MEM_INT_ENA SPI0 interrupt enable register 0xC0 0x20 SPI_MEM_SLV_ST_END_INT_ENA The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-write SPI_MEM_MST_ST_END_INT_ENA The enable bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-write SPI_MEM_ECC_ERR_INT_ENA The enable bit for SPI_MEM_ECC_ERR_INT interrupt. 5 1 read-only SPI_MEM_PMS_REJECT_INT_ENA The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. 6 1 read-write SPI_MEM_AXI_RADDR_ERR_INT_ENA The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 7 1 read-write SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 8 1 read-only SPI_MEM_AXI_WADDR_ERR_INT__ENA The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 9 1 read-only SPI_MEM_INT_CLR SPI0 interrupt clear register 0xC4 0x20 SPI_MEM_SLV_ST_END_INT_CLR The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 write-only SPI_MEM_MST_ST_END_INT_CLR The clear bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 write-only SPI_MEM_ECC_ERR_INT_CLR The clear bit for SPI_MEM_ECC_ERR_INT interrupt. 5 1 read-only SPI_MEM_PMS_REJECT_INT_CLR The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. 6 1 write-only SPI_MEM_AXI_RADDR_ERR_INT_CLR The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 7 1 write-only SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 8 1 read-only SPI_MEM_AXI_WADDR_ERR_INT_CLR The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 9 1 read-only SPI_MEM_INT_RAW SPI0 interrupt raw register 0xC8 0x20 SPI_MEM_SLV_ST_END_INT_RAW The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others 3 1 read-only SPI_MEM_MST_ST_END_INT_RAW The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others. 4 1 read-only SPI_MEM_ECC_ERR_INT_RAW The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered. 5 1 read-only SPI_MEM_PMS_REJECT_INT_RAW The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others. 6 1 read-only SPI_MEM_AXI_RADDR_ERR_INT_RAW The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others. 7 1 read-only SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others. 8 1 read-only SPI_MEM_AXI_WADDR_ERR_INT_RAW The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others. 9 1 read-only SPI_MEM_INT_ST SPI0 interrupt status register 0xCC 0x20 SPI_MEM_SLV_ST_END_INT_ST The status bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-only SPI_MEM_MST_ST_END_INT_ST The status bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-only SPI_MEM_ECC_ERR_INT_ST The status bit for SPI_MEM_ECC_ERR_INT interrupt. 5 1 read-only SPI_MEM_PMS_REJECT_INT_ST The status bit for SPI_MEM_PMS_REJECT_INT interrupt. 6 1 read-only SPI_MEM_AXI_RADDR_ERR_INT_ST The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 7 1 read-only SPI_MEM_AXI_WR_FLASH_ERR_INT_ST The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 8 1 read-only SPI_MEM_AXI_WADDR_ERR_INT_ST The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 9 1 read-only SPI_MEM_DDR SPI0 flash DDR mode control register 0xD4 0x20 0x00003020 SPI_FMEM_DDR_EN 1: in DDR mode, 0 in SDR mode 0 1 read-only SPI_FMEM_VAR_DUMMY Set the bit to enable variable dummy cycle in spi DDR mode. 1 1 read-only SPI_FMEM_DDR_RDAT_SWP Set the bit to reorder rx data of the word in spi DDR mode. 2 1 read-only SPI_FMEM_DDR_WDAT_SWP Set the bit to reorder tx data of the word in spi DDR mode. 3 1 read-only SPI_FMEM_DDR_CMD_DIS the bit is used to disable dual edge in command phase when DDR mode. 4 1 read-only SPI_FMEM_OUTMINBYTELEN It is the minimum output data length in the panda device. 5 7 read-only SPI_FMEM_TX_DDR_MSK_EN Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash. 12 1 read-only SPI_FMEM_RX_DDR_MSK_EN Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash. 13 1 read-only SPI_FMEM_USR_DDR_DQS_THD The delay number of data strobe which from memory based on SPI clock. 14 7 read-only SPI_FMEM_DDR_DQS_LOOP 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. 21 1 read-only SPI_FMEM_CLK_DIFF_EN Set this bit to enable the differential SPI_CLK#. 24 1 read-only SPI_FMEM_DQS_CA_IN Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. 26 1 read-only SPI_FMEM_HYPERBUS_DUMMY_2X Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. 27 1 read-only SPI_FMEM_CLK_DIFF_INV Set this bit to invert SPI_DIFF when accesses to flash. . 28 1 read-only SPI_FMEM_OCTA_RAM_ADDR Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. 29 1 read-only SPI_FMEM_HYPERBUS_CA Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. 30 1 read-only SPI_SMEM_DDR SPI0 external RAM DDR mode control register 0xD8 0x20 0x00003020 EN 1: in DDR mode, 0 in SDR mode 0 1 read-only SPI_SMEM_VAR_DUMMY Set the bit to enable variable dummy cycle in spi DDR mode. 1 1 read-only RDAT_SWP Set the bit to reorder rx data of the word in spi DDR mode. 2 1 read-only WDAT_SWP Set the bit to reorder tx data of the word in spi DDR mode. 3 1 read-only CMD_DIS the bit is used to disable dual edge in command phase when DDR mode. 4 1 read-only SPI_SMEM_OUTMINBYTELEN It is the minimum output data length in the DDR psram. 5 7 read-only SPI_SMEM_TX_DDR_MSK_EN Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM. 12 1 read-only SPI_SMEM_RX_DDR_MSK_EN Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM. 13 1 read-only SPI_SMEM_USR_DDR_DQS_THD The delay number of data strobe which from memory based on SPI clock. 14 7 read-only DQS_LOOP 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. 21 1 read-only SPI_SMEM_CLK_DIFF_EN Set this bit to enable the differential SPI_CLK#. 24 1 read-only SPI_SMEM_DQS_CA_IN Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. 26 1 read-only SPI_SMEM_HYPERBUS_DUMMY_2X Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. 27 1 read-only SPI_SMEM_CLK_DIFF_INV Set this bit to invert SPI_DIFF when accesses to external RAM. . 28 1 read-only SPI_SMEM_OCTA_RAM_ADDR Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. 29 1 read-only SPI_SMEM_HYPERBUS_CA Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. 30 1 read-only 4 0x4 SPI_FMEM_PMS%s_ATTR MSPI flash ACE section %s attribute register 0x100 0x20 0x00000003 SPI_FMEM_PMS_RD_ATTR 1: SPI1 flash ACE section %s read accessible. 0: Not allowed. 0 1 read-write SPI_FMEM_PMS_WR_ATTR 1: SPI1 flash ACE section %s write accessible. 0: Not allowed. 1 1 read-write SPI_FMEM_PMS_ECC SPI1 flash ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG. 2 1 read-write 4 0x4 SPI_FMEM_PMS%s_ADDR SPI1 flash ACE section %s start address register 0x110 0x20 S SPI1 flash ACE section %s start address value 0 26 read-write 4 0x4 SPI_FMEM_PMS%s_SIZE SPI1 flash ACE section %s start address register 0x120 0x20 0x00001000 SPI_FMEM_PMS_SIZE SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE) 0 14 read-write 4 0x4 SPI_SMEM_PMS%s_ATTR SPI1 flash ACE section %s start address register 0x130 0x20 0x00000003 SPI_SMEM_PMS_RD_ATTR 1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed. 0 1 read-write SPI_SMEM_PMS_WR_ATTR 1: SPI1 external RAM ACE section %s write accessible. 0: Not allowed. 1 1 read-write SPI_SMEM_PMS_ECC SPI1 external RAM ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG. 2 1 read-write 4 0x4 SPI_SMEM_PMS%s_ADDR SPI1 external RAM ACE section %s start address register 0x140 0x20 S SPI1 external RAM ACE section %s start address value 0 26 read-write 4 0x4 SPI_SMEM_PMS%s_SIZE SPI1 external RAM ACE section %s start address register 0x150 0x20 0x00001000 SPI_SMEM_PMS_SIZE SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE) 0 14 read-write SPI_MEM_PMS_REJECT SPI1 access reject register 0x164 0x20 SPI_MEM_REJECT_ADDR This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. 0 26 read-only SPI_MEM_PM_EN Set this bit to enable SPI0/1 transfer permission control function. 26 1 read-write SPI_MEM_PMS_LD 1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. 28 1 read-only SPI_MEM_PMS_ST 1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. 29 1 read-only SPI_MEM_PMS_MULTI_HIT 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. 30 1 read-only SPI_MEM_PMS_IVD 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. 31 1 read-only SPI_MEM_ECC_CTRL MSPI ECC control register 0x168 0x20 0x01005000 SPI_FMEM_ECC_ERR_INT_NUM Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. 11 6 read-only SPI_FMEM_ECC_ERR_INT_EN Set this bit to calculate the error times of MSPI ECC read when accesses to flash. 17 1 read-only SPI_FMEM_PAGE_SIZE Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. 18 2 read-write SPI_FMEM_ECC_ADDR_EN Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1. 20 1 read-only SPI_MEM_USR_ECC_ADDR_EN Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. 21 1 read-only SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information. 24 1 read-only SPI_MEM_ECC_ERR_BITS Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7) 25 7 read-only SPI_MEM_ECC_ERR_ADDR MSPI ECC error address register 0x16C 0x20 SPI_MEM_ECC_ERR_ADDR This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. 0 26 read-only SPI_MEM_ECC_ERR_CNT This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. 26 6 read-only SPI_MEM_AXI_ERR_ADDR SPI0 AXI request error address. 0x170 0x20 0xFC000000 SPI_MEM_AXI_ERR_ADDR This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. 0 26 read-only SPI_MEM_ALL_FIFO_EMPTY The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others. 26 1 read-only SPI_RDATA_AFIFO_REMPTY 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. 27 1 read-only SPI_RADDR_AFIFO_REMPTY 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. 28 1 read-only SPI_WDATA_AFIFO_REMPTY 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. 29 1 read-only SPI_WBLEN_AFIFO_REMPTY 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. 30 1 read-only SPI_ALL_AXI_TRANS_AFIFO_EMPTY This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE. 31 1 read-only SPI_SMEM_ECC_CTRL MSPI ECC control register 0x174 0x20 0x00080000 SPI_SMEM_ECC_ERR_INT_EN Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. 17 1 read-only SPI_SMEM_PAGE_SIZE Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes. 18 2 read-only SPI_SMEM_ECC_ADDR_EN Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1. 20 1 read-only SPI_MEM_TIMING_CALI SPI0 flash timing calibration register 0x180 0x20 0x00000001 SPI_MEM_TIMING_CLK_ENA The bit is used to enable timing adjust clock for all reading operations. 0 1 read-write SPI_MEM_TIMING_CALI The bit is used to enable timing auto-calibration for all reading operations. 1 1 read-write SPI_MEM_EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 read-write SPI_MEM_DLL_TIMING_CALI Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. 5 1 read-only UPDATE Set this bit to update delay mode, delay num and extra dummy in MSPI. 6 1 write-only SPI_MEM_DIN_MODE MSPI flash input timing delay mode control register 0x184 0x20 SPI_MEM_DIN0_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 0 3 read-write SPI_MEM_DIN1_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 3 3 read-write SPI_MEM_DIN2_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 6 3 read-write SPI_MEM_DIN3_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 9 3 read-write SPI_MEM_DIN4_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk 12 3 read-write SPI_MEM_DIN5_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk 15 3 read-write SPI_MEM_DIN6_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk 18 3 read-write SPI_MEM_DIN7_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk 21 3 read-write SPI_MEM_DINS_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk 24 3 read-write SPI_MEM_DIN_NUM MSPI flash input timing delay number control register 0x188 0x20 SPI_MEM_DIN0_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 0 2 read-write SPI_MEM_DIN1_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 2 2 read-write SPI_MEM_DIN2_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 4 2 read-write SPI_MEM_DIN3_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 6 2 read-write SPI_MEM_DIN4_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 8 2 read-write SPI_MEM_DIN5_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 10 2 read-write SPI_MEM_DIN6_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 12 2 read-write SPI_MEM_DIN7_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 14 2 read-write SPI_MEM_DINS_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 16 2 read-write SPI_MEM_DOUT_MODE MSPI flash output timing adjustment control register 0x18C 0x20 SPI_MEM_DOUT0_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 0 1 read-write SPI_MEM_DOUT1_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 1 1 read-write SPI_MEM_DOUT2_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 2 1 read-write SPI_MEM_DOUT3_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 3 1 read-write SPI_MEM_DOUT4_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk 4 1 read-write SPI_MEM_DOUT5_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk 5 1 read-write SPI_MEM_DOUT6_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk 6 1 read-write SPI_MEM_DOUT7_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk 7 1 read-write SPI_MEM_DOUTS_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk 8 1 read-write SPI_SMEM_TIMING_CALI MSPI external RAM timing calibration register 0x190 0x20 0x00000001 SPI_SMEM_TIMING_CLK_ENA For sram, the bit is used to enable timing adjust clock for all reading operations. 0 1 read-only SPI_SMEM_TIMING_CALI For sram, the bit is used to enable timing auto-calibration for all reading operations. 1 1 read-only SPI_SMEM_EXTRA_DUMMY_CYCLELEN For sram, add extra dummy spi clock cycle length for spi clock calibration. 2 3 read-only SPI_SMEM_DLL_TIMING_CALI Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. 5 1 read-only SPI_SMEM_DIN_MODE MSPI external RAM input timing delay mode control register 0x194 0x20 SPI_SMEM_DIN0_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 0 3 read-only SPI_SMEM_DIN1_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 3 3 read-only SPI_SMEM_DIN2_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 6 3 read-only SPI_SMEM_DIN3_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 9 3 read-only SPI_SMEM_DIN4_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 12 3 read-only SPI_SMEM_DIN5_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 15 3 read-only SPI_SMEM_DIN6_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 18 3 read-only SPI_SMEM_DIN7_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 21 3 read-only SPI_SMEM_DINS_MODE the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 24 3 read-only SPI_SMEM_DIN_NUM MSPI external RAM input timing delay number control register 0x198 0x20 SPI_SMEM_DIN0_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 0 2 read-only SPI_SMEM_DIN1_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 2 2 read-only SPI_SMEM_DIN2_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 4 2 read-only SPI_SMEM_DIN3_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 6 2 read-only SPI_SMEM_DIN4_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 8 2 read-only SPI_SMEM_DIN5_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 10 2 read-only SPI_SMEM_DIN6_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 12 2 read-only SPI_SMEM_DIN7_NUM the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... 14 2 read-only SPI_SMEM_DINS_NUM the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge 16 2 read-only SPI_SMEM_DOUT_MODE MSPI external RAM output timing adjustment control register 0x19C 0x20 SPI_SMEM_DOUT0_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 0 1 read-only SPI_SMEM_DOUT1_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 1 1 read-only SPI_SMEM_DOUT2_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 2 1 read-only SPI_SMEM_DOUT3_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 3 1 read-only SPI_SMEM_DOUT4_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 4 1 read-only SPI_SMEM_DOUT5_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 5 1 read-only SPI_SMEM_DOUT6_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 6 1 read-only SPI_SMEM_DOUT7_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 7 1 read-only SPI_SMEM_DOUTS_MODE the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge 8 1 read-only SPI_SMEM_AC MSPI external RAM ECC and SPI CS timing control register 0x1A0 0x20 0x8000B084 SPI_SMEM_CS_SETUP For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable. 0 1 read-only SPI_SMEM_CS_HOLD For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. 1 1 read-only SPI_SMEM_CS_SETUP_TIME For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. 2 5 read-only SPI_SMEM_CS_HOLD_TIME For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. 7 5 read-only SPI_SMEM_ECC_CS_HOLD_TIME SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. 12 3 read-only SPI_SMEM_ECC_SKIP_PAGE_CORNER 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM. 15 1 read-only SPI_SMEM_ECC_16TO18_BYTE_EN Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. 16 1 read-only SPI_SMEM_CS_HOLD_DELAY These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. 25 6 read-only SPI_SMEM_SPLIT_TRANS_EN Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not. 31 1 read-only SPI_MEM_CLOCK_GATE SPI0 clock gate register 0x200 0x20 0x00000001 SPI_CLK_EN Register clock gate enable signal. 1: Enable. 0: Disable. 0 1 read-write SPI_MEM_XTS_PLAIN_BASE The base address of the memory that stores plaintext in Manual Encryption 0x300 0x20 SPI_XTS_PLAIN This field is only used to generate include file in c case. This field is useless. Please do not use this field. 0 32 read-write SPI_MEM_XTS_LINESIZE Manual Encryption Line-Size register 0x340 0x20 SPI_XTS_LINESIZE This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved. 0 2 read-write SPI_MEM_XTS_DESTINATION Manual Encryption destination register 0x344 0x20 SPI_XTS_DESTINATION This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. 0 1 read-write SPI_MEM_XTS_PHYSICAL_ADDRESS Manual Encryption physical address register 0x348 0x20 SPI_XTS_PHYSICAL_ADDRESS This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. 0 26 read-write SPI_MEM_XTS_TRIGGER Manual Encryption physical address register 0x34C 0x20 SPI_XTS_TRIGGER Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2. 0 1 write-only SPI_MEM_XTS_RELEASE Manual Encryption physical address register 0x350 0x20 SPI_XTS_RELEASE Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3. 0 1 write-only SPI_MEM_XTS_DESTROY Manual Encryption physical address register 0x354 0x20 SPI_XTS_DESTROY Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0. 0 1 write-only SPI_MEM_XTS_STATE Manual Encryption physical address register 0x358 0x20 SPI_XTS_STATE This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi. 0 2 read-only SPI_MEM_XTS_DATE Manual Encryption version register 0x35C 0x20 0x20201010 SPI_XTS_DATE This bits stores the last modified-time of manual encryption feature. 0 30 read-write SPI_MEM_MMU_ITEM_CONTENT MSPI-MMU item content register 0x37C 0x20 0x0000037C SPI_MMU_ITEM_CONTENT MSPI-MMU item content 0 32 read-write SPI_MEM_MMU_ITEM_INDEX MSPI-MMU item index register 0x380 0x20 SPI_MMU_ITEM_INDEX MSPI-MMU item index 0 32 read-write SPI_MEM_MMU_POWER_CTRL MSPI MMU power control register 0x384 0x20 0x13200004 SPI_MMU_MEM_FORCE_ON Set this bit to enable mmu-memory clock force on 0 1 read-write SPI_MMU_MEM_FORCE_PD Set this bit to force mmu-memory powerdown 1 1 read-write SPI_MMU_MEM_FORCE_PU Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc. 2 1 read-write SPI_MMU_PAGE_SIZE 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 3 2 read-write SPI_MEM_AUX_CTRL MMU PSRAM aux control register 16 14 read-only SPI_MEM_RDN_ENA ECO register enable bit 30 1 read-only SPI_MEM_RDN_RESULT MSPI module clock domain and AXI clock domain ECO register result register 31 1 read-only SPI_MEM_DPA_CTRL SPI memory cryption DPA register 0x388 0x20 0x0000000F SPI_CRYPT_SECURITY_LEVEL Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing) 0 3 read-write SPI_CRYPT_CALC_D_DPA_EN Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1. 3 1 read-write SPI_CRYPT_DPA_SELECT_REGISTER 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. 4 1 read-write SPI_MEM_REGISTERRND_ECO_HIGH MSPI ECO high register 0x3F0 0x20 0x0000037C SPI_MEM_REGISTERRND_ECO_HIGH ECO high register 0 32 read-only SPI_MEM_REGISTERRND_ECO_LOW MSPI ECO low register 0x3F4 0x20 0x0000037C SPI_MEM_REGISTERRND_ECO_LOW ECO low register 0 32 read-only SPI_MEM_DATE SPI0 version control register 0x3FC 0x20 0x02203030 SPI_MEM_DATE SPI0 register version. 0 28 read-write SPI1 SPI (Serial Peripheral Interface) Controller SPI1 0x60002000 0x0 0xAC registers SPI1 18 SPI_MEM_CMD SPI1 memory command register 0x0 0x20 SPI_MEM_MST_ST The current status of SPI1 master FSM. 0 4 read-only SPI_MEM_SLV_ST The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state. 4 4 read-only SPI_MEM_FLASH_PE In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable. 17 1 read-write SPI_MEM_USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 18 1 read-write SPI_MEM_FLASH_HPM Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. 19 1 read-write SPI_MEM_FLASH_RES This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. 20 1 read-write SPI_MEM_FLASH_DP Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 21 1 read-write SPI_MEM_FLASH_CE Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 22 1 read-write SPI_MEM_FLASH_BE Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 23 1 read-write SPI_MEM_FLASH_SE Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 24 1 read-write SPI_MEM_FLASH_PP Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. 25 1 read-write SPI_MEM_FLASH_WRSR Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 26 1 read-write SPI_MEM_FLASH_RDSR Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 27 1 read-write SPI_MEM_FLASH_RDID Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 28 1 read-write SPI_MEM_FLASH_WRDI Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 29 1 read-write SPI_MEM_FLASH_WREN Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 30 1 read-write SPI_MEM_FLASH_READ Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. 31 1 read-write SPI_MEM_ADDR SPI1 address register 0x4 0x20 SPI_MEM_USR_ADDR_VALUE In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer. 0 32 read-write SPI_MEM_CTRL SPI1 control register. 0x8 0x20 0x002CA00C SPI_MEM_FDUMMY_RIN In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. 2 1 read-write SPI_MEM_FDUMMY_WOUT In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller. 3 1 read-write SPI_MEM_FDOUT_OCT Apply 8 signals during write-data phase 1:enable 0: disable 4 1 read-only SPI_MEM_FDIN_OCT Apply 8 signals during read-data phase 1:enable 0: disable 5 1 read-only SPI_MEM_FADDR_OCT Apply 8 signals during address phase 1:enable 0: disable 6 1 read-only SPI_MEM_FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable 8 1 read-write SPI_MEM_FCMD_OCT Apply 8 signals during command phase 1:enable 0: disable 9 1 read-only SPI_MEM_FCS_CRC_EN For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. 10 1 read-only SPI_MEM_TX_CRC_EN For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable 11 1 read-only SPI_MEM_FASTRD_MODE This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. 13 1 read-write SPI_MEM_FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. 14 1 read-write SPI_MEM_RESANDRES The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. 15 1 read-write SPI_MEM_Q_POL The bit is used to set MISO line polarity, 1: high 0, low 18 1 read-write SPI_MEM_D_POL The bit is used to set MOSI line polarity, 1: high 0, low 19 1 read-write SPI_MEM_FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. 20 1 read-write SPI_MEM_WP Write protect signal output when SPI is idle. 1: output high, 0: output low. 21 1 read-write SPI_MEM_WRSR_2B two bytes data will be written to status register when it is set. 1: enable 0: disable. 22 1 read-write SPI_MEM_FREAD_DIO In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. 23 1 read-write SPI_MEM_FREAD_QIO In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. 24 1 read-write SPI_MEM_CTRL1 SPI1 control1 register. 0xC 0x20 0x00000FFC SPI_MEM_CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. 0 2 read-write SPI_MEM_CS_HOLD_DLY_RES After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles. 2 10 read-write SPI_MEM_CTRL2 SPI1 control2 register. 0x10 0x20 SPI_MEM_SYNC_RESET The FSM will be reset. 31 1 write-only SPI_MEM_CLOCK SPI1 clock division control register. 0x14 0x20 0x00030103 SPI_MEM_CLKCNT_L In the master mode it must be equal to spi_mem_clkcnt_N. 0 8 read-write SPI_MEM_CLKCNT_H In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). 8 8 read-write SPI_MEM_CLKCNT_N In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) 16 8 read-write SPI_MEM_CLK_EQU_SYSCLK reserved 31 1 read-write SPI_MEM_USER SPI1 user register. 0x18 0x20 0x80000000 SPI_MEM_CK_OUT_EDGE the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. 9 1 read-write SPI_MEM_FWRITE_DUAL In the write operations read-data phase apply 2 signals 12 1 read-write SPI_MEM_FWRITE_QUAD In the write operations read-data phase apply 4 signals 13 1 read-write SPI_MEM_FWRITE_DIO In the write operations address phase and read-data phase apply 2 signals. 14 1 read-write SPI_MEM_FWRITE_QIO In the write operations address phase and read-data phase apply 4 signals. 15 1 read-write SPI_MEM_USR_MISO_HIGHPART read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. 24 1 read-only SPI_MEM_USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable. 25 1 read-only SPI_MEM_USR_DUMMY_IDLE SPI clock is disable in dummy phase when the bit is enable. 26 1 read-write SPI_MEM_USR_MOSI This bit enable the write-data phase of an operation. 27 1 read-write SPI_MEM_USR_MISO This bit enable the read-data phase of an operation. 28 1 read-write SPI_MEM_USR_DUMMY This bit enable the dummy phase of an operation. 29 1 read-write SPI_MEM_USR_ADDR This bit enable the address phase of an operation. 30 1 read-write SPI_MEM_USR_COMMAND This bit enable the command phase of an operation. 31 1 read-write SPI_MEM_USER1 SPI1 user1 register. 0x1C 0x20 0x5C000007 SPI_MEM_USR_DUMMY_CYCLELEN The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). 0 6 read-write SPI_MEM_USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). 26 6 read-write SPI_MEM_USER2 SPI1 user2 register. 0x20 0x20 0x70000000 SPI_MEM_USR_COMMAND_VALUE The value of command. 0 16 read-write SPI_MEM_USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1) 28 4 read-write SPI_MEM_MOSI_DLEN SPI1 send data bit length control register. 0x24 0x20 SPI_MEM_USR_MOSI_DBITLEN The length in bits of write-data. The register value shall be (bit_num-1). 0 10 read-write SPI_MEM_MISO_DLEN SPI1 receive data bit length control register. 0x28 0x20 SPI_MEM_USR_MISO_DBITLEN The length in bits of read-data. The register value shall be (bit_num-1). 0 10 read-write SPI_MEM_RD_STATUS SPI1 status register. 0x2C 0x20 SPI_MEM_STATUS The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. 0 16 read-write SPI_MEM_WB_MODE Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. 16 8 read-write SPI_MEM_MISC SPI1 misc register 0x34 0x20 0x00000002 SPI_MEM_CS0_DIS SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on. 0 1 read-write SPI_MEM_CS1_DIS SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on. 1 1 read-write SPI_MEM_CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle 9 1 read-write SPI_MEM_CS_KEEP_ACTIVE spi cs line keep low when the bit is set. 10 1 read-write SPI_MEM_TX_CRC SPI1 TX CRC data register. 0x38 0x20 0xFFFFFFFF DATA For SPI1, the value of crc32. 0 32 read-only SPI_MEM_CACHE_FCTRL SPI1 bit mode control register. 0x3C 0x20 SPI_MEM_CACHE_USR_ADDR_4BYTE For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. 1 1 read-write SPI_MEM_FDIN_DUAL For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 3 1 read-write SPI_MEM_FDOUT_DUAL For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 4 1 read-write SPI_MEM_FADDR_DUAL For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio. 5 1 read-write SPI_MEM_FDIN_QUAD For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 6 1 read-write SPI_MEM_FDOUT_QUAD For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 7 1 read-write SPI_MEM_FADDR_QUAD For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio. 8 1 read-write SPI_MEM_W0 SPI1 memory data buffer0 0x58 0x20 SPI_MEM_BUF0 data buffer 0 32 read-write SPI_MEM_W1 SPI1 memory data buffer1 0x5C 0x20 SPI_MEM_BUF1 data buffer 0 32 read-write SPI_MEM_W2 SPI1 memory data buffer2 0x60 0x20 SPI_MEM_BUF2 data buffer 0 32 read-write SPI_MEM_W3 SPI1 memory data buffer3 0x64 0x20 SPI_MEM_BUF3 data buffer 0 32 read-write SPI_MEM_W4 SPI1 memory data buffer4 0x68 0x20 SPI_MEM_BUF4 data buffer 0 32 read-write SPI_MEM_W5 SPI1 memory data buffer5 0x6C 0x20 SPI_MEM_BUF5 data buffer 0 32 read-write SPI_MEM_W6 SPI1 memory data buffer6 0x70 0x20 SPI_MEM_BUF6 data buffer 0 32 read-write SPI_MEM_W7 SPI1 memory data buffer7 0x74 0x20 SPI_MEM_BUF7 data buffer 0 32 read-write SPI_MEM_W8 SPI1 memory data buffer8 0x78 0x20 SPI_MEM_BUF8 data buffer 0 32 read-write SPI_MEM_W9 SPI1 memory data buffer9 0x7C 0x20 SPI_MEM_BUF9 data buffer 0 32 read-write SPI_MEM_W10 SPI1 memory data buffer10 0x80 0x20 SPI_MEM_BUF10 data buffer 0 32 read-write SPI_MEM_W11 SPI1 memory data buffer11 0x84 0x20 SPI_MEM_BUF11 data buffer 0 32 read-write SPI_MEM_W12 SPI1 memory data buffer12 0x88 0x20 SPI_MEM_BUF12 data buffer 0 32 read-write SPI_MEM_W13 SPI1 memory data buffer13 0x8C 0x20 SPI_MEM_BUF13 data buffer 0 32 read-write SPI_MEM_W14 SPI1 memory data buffer14 0x90 0x20 SPI_MEM_BUF14 data buffer 0 32 read-write SPI_MEM_W15 SPI1 memory data buffer15 0x94 0x20 SPI_MEM_BUF15 data buffer 0 32 read-write SPI_MEM_FLASH_WAITI_CTRL SPI1 wait idle control register 0x98 0x20 0x00050001 SPI_MEM_WAITI_EN 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported. 0 1 read-write SPI_MEM_WAITI_DUMMY The dummy phase enable when wait flash idle (RDSR) 1 1 read-write SPI_MEM_WAITI_ADDR_EN 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer. 2 1 read-write SPI_MEM_WAITI_ADDR_CYCLELEN When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared. 3 2 read-write SPI_MEM_WAITI_CMD_2B 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8. 9 1 read-write SPI_MEM_WAITI_DUMMY_CYCLELEN The dummy cycle length when wait flash idle(RDSR). 10 6 read-write SPI_MEM_WAITI_CMD The command value to wait flash idle(RDSR). 16 16 read-write SPI_MEM_FLASH_SUS_CTRL SPI1 flash suspend control register 0x9C 0x20 0x08002000 SPI_MEM_FLASH_PER program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 0 1 read-write SPI_MEM_FLASH_PES program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. 1 1 read-write SPI_MEM_FLASH_PER_WAIT_EN 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent. 2 1 read-write SPI_MEM_FLASH_PES_WAIT_EN 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent. 3 1 read-write SPI_MEM_PES_PER_EN Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done. 4 1 read-write SPI_MEM_FLASH_PES_EN Set this bit to enable Auto-suspending function. 5 1 read-write SPI_MEM_PESR_END_MSK The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]. 6 16 read-write SPI_FMEM_RD_SUS_2B 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit 22 1 read-write SPI_MEM_PER_END_EN 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0. 23 1 read-write SPI_MEM_PES_END_EN 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0. 24 1 read-write SPI_MEM_SUS_TIMEOUT_CNT When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass. 25 7 read-write SPI_MEM_FLASH_SUS_CMD SPI1 flash suspend command register 0xA0 0x20 0x00057575 SPI_MEM_FLASH_PES_COMMAND Program/Erase suspend command. 0 16 read-write SPI_MEM_WAIT_PESR_COMMAND Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. 16 16 read-write SPI_MEM_SUS_STATUS SPI1 flash suspend status register 0xA4 0x20 0x7A7A0000 SPI_MEM_FLASH_SUS The status of flash suspend, only used in SPI1. 0 1 read-write SPI_MEM_WAIT_PESR_CMD_2B 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit. 1 1 read-write SPI_MEM_FLASH_HPM_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent. 2 1 read-write SPI_MEM_FLASH_RES_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent. 3 1 read-write SPI_MEM_FLASH_DP_DLY_128 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent. 4 1 read-write SPI_MEM_FLASH_PER_DLY_128 Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent. 5 1 read-write SPI_MEM_FLASH_PES_DLY_128 Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent. 6 1 read-write SPI_MEM_SPI0_LOCK_EN 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it. 7 1 read-write SPI_MEM_FLASH_PESR_CMD_2B 1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8. 15 1 read-write SPI_MEM_FLASH_PER_COMMAND Program/Erase resume command. 16 16 read-write SPI_MEM_INT_ENA SPI1 interrupt enable register 0xC0 0x20 SPI_MEM_PER_END_INT_ENA The enable bit for SPI_MEM_PER_END_INT interrupt. 0 1 read-write SPI_MEM_PES_END_INT_ENA The enable bit for SPI_MEM_PES_END_INT interrupt. 1 1 read-write SPI_MEM_WPE_END_INT_ENA The enable bit for SPI_MEM_WPE_END_INT interrupt. 2 1 read-write SPI_MEM_SLV_ST_END_INT_ENA The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-write SPI_MEM_MST_ST_END_INT_ENA The enable bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-write SPI_MEM_BROWN_OUT_INT_ENA The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. 10 1 read-write SPI_MEM_INT_CLR SPI1 interrupt clear register 0xC4 0x20 SPI_MEM_PER_END_INT_CLR The clear bit for SPI_MEM_PER_END_INT interrupt. 0 1 write-only SPI_MEM_PES_END_INT_CLR The clear bit for SPI_MEM_PES_END_INT interrupt. 1 1 write-only SPI_MEM_WPE_END_INT_CLR The clear bit for SPI_MEM_WPE_END_INT interrupt. 2 1 write-only SPI_MEM_SLV_ST_END_INT_CLR The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 write-only SPI_MEM_MST_ST_END_INT_CLR The clear bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 write-only SPI_MEM_BROWN_OUT_INT_CLR The status bit for SPI_MEM_BROWN_OUT_INT interrupt. 10 1 write-only SPI_MEM_INT_RAW SPI1 interrupt raw register 0xC8 0x20 SPI_MEM_PER_END_INT_RAW The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others. 0 1 read-only SPI_MEM_PES_END_INT_RAW The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others. 1 1 read-only SPI_MEM_WPE_END_INT_RAW The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. 2 1 read-only SPI_MEM_SLV_ST_END_INT_RAW The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others 3 1 read-only SPI_MEM_MST_ST_END_INT_RAW The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. 4 1 read-only SPI_MEM_BROWN_OUT_INT_RAW The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others. 10 1 read-only SPI_MEM_INT_ST SPI1 interrupt status register 0xCC 0x20 SPI_MEM_PER_END_INT_ST The status bit for SPI_MEM_PER_END_INT interrupt. 0 1 read-only SPI_MEM_PES_END_INT_ST The status bit for SPI_MEM_PES_END_INT interrupt. 1 1 read-only SPI_MEM_WPE_END_INT_ST The status bit for SPI_MEM_WPE_END_INT interrupt. 2 1 read-only SPI_MEM_SLV_ST_END_INT_ST The status bit for SPI_MEM_SLV_ST_END_INT interrupt. 3 1 read-only SPI_MEM_MST_ST_END_INT_ST The status bit for SPI_MEM_MST_ST_END_INT interrupt. 4 1 read-only SPI_MEM_BROWN_OUT_INT_ST The status bit for SPI_MEM_BROWN_OUT_INT interrupt. 10 1 read-only SPI_MEM_DDR SPI1 DDR control register 0xD4 0x20 0x00000020 SPI_FMEM_DDR_EN 1: in ddr mode, 0 in sdr mode 0 1 read-only SPI_FMEM_VAR_DUMMY Set the bit to enable variable dummy cycle in spi ddr mode. 1 1 read-only SPI_FMEM_DDR_RDAT_SWP Set the bit to reorder rx data of the word in spi ddr mode. 2 1 read-only SPI_FMEM_DDR_WDAT_SWP Set the bit to reorder tx data of the word in spi ddr mode. 3 1 read-only SPI_FMEM_DDR_CMD_DIS the bit is used to disable dual edge in command phase when ddr mode. 4 1 read-only SPI_FMEM_OUTMINBYTELEN It is the minimum output data length in the panda device. 5 7 read-only SPI_FMEM_USR_DDR_DQS_THD The delay number of data strobe which from memory based on SPI clock. 14 7 read-only SPI_FMEM_DDR_DQS_LOOP 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS. 21 1 read-only SPI_FMEM_CLK_DIFF_EN Set this bit to enable the differential SPI_CLK#. 24 1 read-only SPI_FMEM_DQS_CA_IN Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. 26 1 read-only SPI_FMEM_HYPERBUS_DUMMY_2X Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. 27 1 read-only SPI_FMEM_CLK_DIFF_INV Set this bit to invert SPI_DIFF when accesses to flash. . 28 1 read-only SPI_FMEM_OCTA_RAM_ADDR Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. 29 1 read-only SPI_FMEM_HYPERBUS_CA Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. 30 1 read-only SPI_MEM_TIMING_CALI SPI1 timing control register 0x180 0x20 SPI_MEM_TIMING_CALI The bit is used to enable timing auto-calibration for all reading operations. 1 1 read-write SPI_MEM_EXTRA_DUMMY_CYCLELEN add extra dummy spi clock cycle length for spi clock calibration. 2 3 read-write SPI_MEM_CLOCK_GATE SPI1 clk_gate register 0x200 0x20 0x00000001 SPI_MEM_CLK_EN Register clock gate enable signal. 1: Enable. 0: Disable. 0 1 read-write SPI_MEM_DATE Version control register 0x3FC 0x20 0x02202160 SPI_MEM_DATE Version control register 0 28 read-write SPI2 SPI (Serial Peripheral Interface) Controller SPI2 0x60024000 0x0 0x98 registers SPI2 19 SPI_CMD Command control register 0x0 0x20 SPI_CONF_BITLEN Define the APB cycles of SPI_CONF state. Can be configured in CONF state. 0 18 read-write SPI_UPDATE Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode. 23 1 write-only SPI_USR User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf. 24 1 read-write SPI_ADDR Address value register 0x4 0x20 SPI_USR_ADDR_VALUE Address to slave. Can be configured in CONF state. 0 32 read-write SPI_CTRL SPI control register 0x8 0x20 0x003C0000 SPI_DUMMY_OUT 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state. 3 1 read-write SPI_FADDR_DUAL Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 5 1 read-write SPI_FADDR_QUAD Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 6 1 read-write SPI_FADDR_OCT Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state. 7 1 read-only SPI_FCMD_DUAL Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 8 1 read-write SPI_FCMD_QUAD Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 9 1 read-write SPI_FCMD_OCT Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state. 10 1 read-only SPI_FREAD_DUAL In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state. 14 1 read-write SPI_FREAD_QUAD In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state. 15 1 read-write SPI_FREAD_OCT In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state. 16 1 read-only SPI_Q_POL The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state. 18 1 read-write SPI_D_POL The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state. 19 1 read-write SPI_HOLD_POL SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. 20 1 read-write SPI_WP_POL Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state. 21 1 read-write SPI_RD_BIT_ORDER In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state. 23 2 read-write SPI_WR_BIT_ORDER In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state. 25 2 read-write SPI_CLOCK SPI clock control register 0xC 0x20 0x80003043 SPI_CLKCNT_L In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. 0 6 read-write SPI_CLKCNT_H In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. 6 6 read-write SPI_CLKCNT_N In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. 12 6 read-write SPI_CLKDIV_PRE In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. 18 4 read-write SPI_CLK_EQU_SYSCLK In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state. 31 1 read-write SPI_USER SPI USER control register 0x10 0x20 0x800000C0 SPI_DOUTDIN Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state. 0 1 read-write SPI_QPI_MODE Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state. 3 1 read-write SPI_OPI_MODE Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state. 4 1 read-only SPI_TSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. 5 1 read-write SPI_CS_HOLD spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state. 6 1 read-write SPI_CS_SETUP spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state. 7 1 read-write SPI_RSCK_I_EDGE In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. 8 1 read-write SPI_CK_OUT_EDGE the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. 9 1 read-write SPI_FWRITE_DUAL In the write operations read-data phase apply 2 signals. Can be configured in CONF state. 12 1 read-write SPI_FWRITE_QUAD In the write operations read-data phase apply 4 signals. Can be configured in CONF state. 13 1 read-write SPI_FWRITE_OCT In the write operations read-data phase apply 8 signals. Can be configured in CONF state. 14 1 read-only SPI_USR_CONF_NXT 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state. 15 1 read-write SPI_SIO Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state. 17 1 read-write SPI_USR_MISO_HIGHPART read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. 24 1 read-write SPI_USR_MOSI_HIGHPART write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state. 25 1 read-write SPI_USR_DUMMY_IDLE spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. 26 1 read-write SPI_USR_MOSI This bit enable the write-data phase of an operation. Can be configured in CONF state. 27 1 read-write SPI_USR_MISO This bit enable the read-data phase of an operation. Can be configured in CONF state. 28 1 read-write SPI_USR_DUMMY This bit enable the dummy phase of an operation. Can be configured in CONF state. 29 1 read-write SPI_USR_ADDR This bit enable the address phase of an operation. Can be configured in CONF state. 30 1 read-write SPI_USR_COMMAND This bit enable the command phase of an operation. Can be configured in CONF state. 31 1 read-write SPI_USER1 SPI USER control register 1 0x14 0x20 0xB8410007 SPI_USR_DUMMY_CYCLELEN The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. 0 8 read-write SPI_MST_WFULL_ERR_END_EN 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 16 1 read-write SPI_CS_SETUP_TIME (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. 17 5 read-write SPI_CS_HOLD_TIME delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. 22 5 read-write SPI_USR_ADDR_BITLEN The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. 27 5 read-write SPI_USER2 SPI USER control register 2 0x18 0x20 0x78000000 SPI_USR_COMMAND_VALUE The value of command. Can be configured in CONF state. 0 16 read-write SPI_MST_REMPTY_ERR_END_EN 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 27 1 read-write SPI_USR_COMMAND_BITLEN The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. 28 4 read-write SPI_MS_DLEN SPI data bit length control register 0x1C 0x20 SPI_MS_DATA_BITLEN The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. 0 18 read-write SPI_MISC SPI misc register 0x20 0x20 0x0000003E SPI_CS0_DIS SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state. 0 1 read-write SPI_CS1_DIS SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state. 1 1 read-write SPI_CS2_DIS SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state. 2 1 read-write SPI_CS3_DIS SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state. 3 1 read-write SPI_CS4_DIS SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state. 4 1 read-write SPI_CS5_DIS SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state. 5 1 read-write SPI_CK_DIS 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. 6 1 read-write SPI_MASTER_CS_POL In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. 7 6 read-write SPI_CLK_DATA_DTR_EN 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. 16 1 read-only SPI_DATA_DTR_EN 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state. 17 1 read-only SPI_ADDR_DTR_EN 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state. 18 1 read-only SPI_CMD_DTR_EN 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state. 19 1 read-only SPI_SLAVE_CS_POL spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state. 23 1 read-write SPI_DQS_IDLE_EDGE The default value of spi_dqs. Can be configured in CONF state. 24 1 read-only SPI_CK_IDLE_EDGE 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state. 29 1 read-write SPI_CS_KEEP_ACTIVE spi cs line keep low when the bit is set. Can be configured in CONF state. 30 1 read-write SPI_QUAD_DIN_PIN_SWAP 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state. 31 1 read-write SPI_DIN_MODE SPI input delay mode configuration 0x24 0x20 SPI_DIN0_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 0 2 read-write SPI_DIN1_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 2 2 read-write SPI_DIN2_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 4 2 read-write SPI_DIN3_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 6 2 read-write SPI_DIN4_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state. 8 2 read-only SPI_DIN5_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state. 10 2 read-only SPI_DIN6_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state. 12 2 read-only SPI_DIN7_MODE the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state. 14 2 read-only SPI_TIMING_HCLK_ACTIVE 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state. 16 1 read-write SPI_DIN_NUM SPI input delay number configuration 0x28 0x20 SPI_DIN0_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 0 2 read-write SPI_DIN1_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 2 2 read-write SPI_DIN2_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 4 2 read-write SPI_DIN3_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 6 2 read-write SPI_DIN4_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 8 2 read-only SPI_DIN5_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 10 2 read-only SPI_DIN6_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 12 2 read-only SPI_DIN7_NUM the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. 14 2 read-only SPI_DOUT_MODE SPI output delay mode configuration 0x2C 0x20 SPI_DOUT0_MODE The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 0 1 read-write SPI_DOUT1_MODE The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 1 1 read-write SPI_DOUT2_MODE The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 2 1 read-write SPI_DOUT3_MODE The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 3 1 read-write SPI_DOUT4_MODE The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 4 1 read-only SPI_DOUT5_MODE The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 5 1 read-only SPI_DOUT6_MODE The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 6 1 read-only SPI_DOUT7_MODE The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 7 1 read-only SPI_D_DQS_MODE The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state. 8 1 read-only SPI_DMA_CONF SPI DMA control register 0x30 0x20 0x00000003 SPI_DMA_OUTFIFO_EMPTY Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. 0 1 read-only SPI_DMA_INFIFO_FULL Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. 1 1 read-only SPI_DMA_SLV_SEG_TRANS_EN Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. 18 1 read-write SPI_SLV_RX_SEG_TRANS_CLR_EN 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. 19 1 read-write SPI_SLV_TX_SEG_TRANS_CLR_EN 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. 20 1 read-write SPI_RX_EOF_EN 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. 21 1 read-write SPI_DMA_RX_ENA Set this bit to enable SPI DMA controlled receive data mode. 27 1 read-write SPI_DMA_TX_ENA Set this bit to enable SPI DMA controlled send data mode. 28 1 read-write SPI_RX_AFIFO_RST Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. 29 1 write-only SPI_BUF_AFIFO_RST Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. 30 1 write-only SPI_DMA_AFIFO_RST Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. 31 1 write-only SPI_DMA_INT_ENA SPI interrupt enable register 0x34 0x20 SPI_DMA_INFIFO_FULL_ERR_INT_ENA The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 read-write SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 read-write SPI_SLV_EX_QPI_INT_ENA The enable bit for SPI slave Ex_QPI interrupt. 2 1 read-write SPI_SLV_EN_QPI_INT_ENA The enable bit for SPI slave En_QPI interrupt. 3 1 read-write SPI_SLV_CMD7_INT_ENA The enable bit for SPI slave CMD7 interrupt. 4 1 read-write SPI_SLV_CMD8_INT_ENA The enable bit for SPI slave CMD8 interrupt. 5 1 read-write SPI_SLV_CMD9_INT_ENA The enable bit for SPI slave CMD9 interrupt. 6 1 read-write SPI_SLV_CMDA_INT_ENA The enable bit for SPI slave CMDA interrupt. 7 1 read-write SPI_SLV_RD_DMA_DONE_INT_ENA The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 read-write SPI_SLV_WR_DMA_DONE_INT_ENA The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 read-write SPI_SLV_RD_BUF_DONE_INT_ENA The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 read-write SPI_SLV_WR_BUF_DONE_INT_ENA The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 read-write SPI_TRANS_DONE_INT_ENA The enable bit for SPI_TRANS_DONE_INT interrupt. 12 1 read-write SPI_DMA_SEG_TRANS_DONE_INT_ENA The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 read-write SPI_SEG_MAGIC_ERR_INT_ENA The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 read-write SPI_SLV_BUF_ADDR_ERR_INT_ENA The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 read-write SPI_SLV_CMD_ERR_INT_ENA The enable bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 read-write SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 read-write SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 read-write SPI_APP2_INT_ENA The enable bit for SPI_APP2_INT interrupt. 19 1 read-write SPI_APP1_INT_ENA The enable bit for SPI_APP1_INT interrupt. 20 1 read-write SPI_DMA_INT_CLR SPI interrupt clear register 0x38 0x20 SPI_DMA_INFIFO_FULL_ERR_INT_CLR The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 write-only SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 write-only SPI_SLV_EX_QPI_INT_CLR The clear bit for SPI slave Ex_QPI interrupt. 2 1 write-only SPI_SLV_EN_QPI_INT_CLR The clear bit for SPI slave En_QPI interrupt. 3 1 write-only SPI_SLV_CMD7_INT_CLR The clear bit for SPI slave CMD7 interrupt. 4 1 write-only SPI_SLV_CMD8_INT_CLR The clear bit for SPI slave CMD8 interrupt. 5 1 write-only SPI_SLV_CMD9_INT_CLR The clear bit for SPI slave CMD9 interrupt. 6 1 write-only SPI_SLV_CMDA_INT_CLR The clear bit for SPI slave CMDA interrupt. 7 1 write-only SPI_SLV_RD_DMA_DONE_INT_CLR The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 write-only SPI_SLV_WR_DMA_DONE_INT_CLR The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 write-only SPI_SLV_RD_BUF_DONE_INT_CLR The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 write-only SPI_SLV_WR_BUF_DONE_INT_CLR The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 write-only SPI_TRANS_DONE_INT_CLR The clear bit for SPI_TRANS_DONE_INT interrupt. 12 1 write-only SPI_DMA_SEG_TRANS_DONE_INT_CLR The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 write-only SPI_SEG_MAGIC_ERR_INT_CLR The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 write-only SPI_SLV_BUF_ADDR_ERR_INT_CLR The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 write-only SPI_SLV_CMD_ERR_INT_CLR The clear bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 write-only SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 write-only SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 write-only SPI_APP2_INT_CLR The clear bit for SPI_APP2_INT interrupt. 19 1 write-only SPI_APP1_INT_CLR The clear bit for SPI_APP1_INT interrupt. 20 1 write-only SPI_DMA_INT_RAW SPI interrupt raw register 0x3C 0x20 SPI_DMA_INFIFO_FULL_ERR_INT_RAW 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. 0 1 read-only SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. 1 1 read-only SPI_SLV_EX_QPI_INT_RAW The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others. 2 1 read-only SPI_SLV_EN_QPI_INT_RAW The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others. 3 1 read-only SPI_SLV_CMD7_INT_RAW The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others. 4 1 read-only SPI_SLV_CMD8_INT_RAW The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others. 5 1 read-only SPI_SLV_CMD9_INT_RAW The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others. 6 1 read-only SPI_SLV_CMDA_INT_RAW The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others. 7 1 read-only SPI_SLV_RD_DMA_DONE_INT_RAW The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others. 8 1 read-only SPI_SLV_WR_DMA_DONE_INT_RAW The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others. 9 1 read-only SPI_SLV_RD_BUF_DONE_INT_RAW The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others. 10 1 read-only SPI_SLV_WR_BUF_DONE_INT_RAW The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others. 11 1 read-only SPI_TRANS_DONE_INT_RAW The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others. 12 1 read-only SPI_DMA_SEG_TRANS_DONE_INT_RAW The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. 13 1 read-only SPI_SEG_MAGIC_ERR_INT_RAW The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others. 14 1 read-only SPI_SLV_BUF_ADDR_ERR_INT_RAW The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others. 15 1 read-only SPI_SLV_CMD_ERR_INT_RAW The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others. 16 1 read-only SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. 17 1 read-only SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others. 18 1 read-only SPI_APP2_INT_RAW The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. 19 1 read-only SPI_APP1_INT_RAW The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. 20 1 read-only SPI_DMA_INT_ST SPI interrupt status register 0x40 0x20 SPI_DMA_INFIFO_FULL_ERR_INT_ST The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 read-only SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 read-only SPI_SLV_EX_QPI_INT_ST The status bit for SPI slave Ex_QPI interrupt. 2 1 read-only SPI_SLV_EN_QPI_INT_ST The status bit for SPI slave En_QPI interrupt. 3 1 read-only SPI_SLV_CMD7_INT_ST The status bit for SPI slave CMD7 interrupt. 4 1 read-only SPI_SLV_CMD8_INT_ST The status bit for SPI slave CMD8 interrupt. 5 1 read-only SPI_SLV_CMD9_INT_ST The status bit for SPI slave CMD9 interrupt. 6 1 read-only SPI_SLV_CMDA_INT_ST The status bit for SPI slave CMDA interrupt. 7 1 read-only SPI_SLV_RD_DMA_DONE_INT_ST The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 read-only SPI_SLV_WR_DMA_DONE_INT_ST The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 read-only SPI_SLV_RD_BUF_DONE_INT_ST The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 read-only SPI_SLV_WR_BUF_DONE_INT_ST The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 read-only SPI_TRANS_DONE_INT_ST The status bit for SPI_TRANS_DONE_INT interrupt. 12 1 read-only SPI_DMA_SEG_TRANS_DONE_INT_ST The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 read-only SPI_SEG_MAGIC_ERR_INT_ST The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 read-only SPI_SLV_BUF_ADDR_ERR_INT_ST The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 read-only SPI_SLV_CMD_ERR_INT_ST The status bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 read-only SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 read-only SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 read-only SPI_APP2_INT_ST The status bit for SPI_APP2_INT interrupt. 19 1 read-only SPI_APP1_INT_ST The status bit for SPI_APP1_INT interrupt. 20 1 read-only SPI_DMA_INT_SET SPI interrupt software set register 0x44 0x20 SPI_DMA_INFIFO_FULL_ERR_INT_SET The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. 0 1 write-only SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. 1 1 write-only SPI_SLV_EX_QPI_INT_SET The software set bit for SPI slave Ex_QPI interrupt. 2 1 write-only SPI_SLV_EN_QPI_INT_SET The software set bit for SPI slave En_QPI interrupt. 3 1 write-only SPI_SLV_CMD7_INT_SET The software set bit for SPI slave CMD7 interrupt. 4 1 write-only SPI_SLV_CMD8_INT_SET The software set bit for SPI slave CMD8 interrupt. 5 1 write-only SPI_SLV_CMD9_INT_SET The software set bit for SPI slave CMD9 interrupt. 6 1 write-only SPI_SLV_CMDA_INT_SET The software set bit for SPI slave CMDA interrupt. 7 1 write-only SPI_SLV_RD_DMA_DONE_INT_SET The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 8 1 write-only SPI_SLV_WR_DMA_DONE_INT_SET The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 9 1 write-only SPI_SLV_RD_BUF_DONE_INT_SET The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 10 1 write-only SPI_SLV_WR_BUF_DONE_INT_SET The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 11 1 write-only SPI_TRANS_DONE_INT_SET The software set bit for SPI_TRANS_DONE_INT interrupt. 12 1 write-only SPI_DMA_SEG_TRANS_DONE_INT_SET The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 13 1 write-only SPI_SEG_MAGIC_ERR_INT_SET The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. 14 1 write-only SPI_SLV_BUF_ADDR_ERR_INT_SET The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 15 1 write-only SPI_SLV_CMD_ERR_INT_SET The software set bit for SPI_SLV_CMD_ERR_INT interrupt. 16 1 write-only SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 17 1 write-only SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 18 1 write-only SPI_APP2_INT_SET The software set bit for SPI_APP2_INT interrupt. 19 1 write-only SPI_APP1_INT_SET The software set bit for SPI_APP1_INT interrupt. 20 1 write-only SPI_W0 SPI CPU-controlled buffer0 0x98 0x20 SPI_BUF0 data buffer 0 32 read-write SPI_W1 SPI CPU-controlled buffer1 0x9C 0x20 SPI_BUF1 data buffer 0 32 read-write SPI_W2 SPI CPU-controlled buffer2 0xA0 0x20 SPI_BUF2 data buffer 0 32 read-write SPI_W3 SPI CPU-controlled buffer3 0xA4 0x20 SPI_BUF3 data buffer 0 32 read-write SPI_W4 SPI CPU-controlled buffer4 0xA8 0x20 SPI_BUF4 data buffer 0 32 read-write SPI_W5 SPI CPU-controlled buffer5 0xAC 0x20 SPI_BUF5 data buffer 0 32 read-write SPI_W6 SPI CPU-controlled buffer6 0xB0 0x20 SPI_BUF6 data buffer 0 32 read-write SPI_W7 SPI CPU-controlled buffer7 0xB4 0x20 SPI_BUF7 data buffer 0 32 read-write SPI_W8 SPI CPU-controlled buffer8 0xB8 0x20 SPI_BUF8 data buffer 0 32 read-write SPI_W9 SPI CPU-controlled buffer9 0xBC 0x20 SPI_BUF9 data buffer 0 32 read-write SPI_W10 SPI CPU-controlled buffer10 0xC0 0x20 SPI_BUF10 data buffer 0 32 read-write SPI_W11 SPI CPU-controlled buffer11 0xC4 0x20 SPI_BUF11 data buffer 0 32 read-write SPI_W12 SPI CPU-controlled buffer12 0xC8 0x20 SPI_BUF12 data buffer 0 32 read-write SPI_W13 SPI CPU-controlled buffer13 0xCC 0x20 SPI_BUF13 data buffer 0 32 read-write SPI_W14 SPI CPU-controlled buffer14 0xD0 0x20 SPI_BUF14 data buffer 0 32 read-write SPI_W15 SPI CPU-controlled buffer15 0xD4 0x20 SPI_BUF15 data buffer 0 32 read-write SPI_SLAVE SPI slave control register 0xE0 0x20 0x02800000 SPI_CLK_MODE SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state. 0 2 read-write SPI_CLK_MODE_13 {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]. 2 1 read-write SPI_RSCK_DATA_OUT It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge 3 1 read-write SPI_SLV_RDDMA_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others 8 1 read-write SPI_SLV_WRDMA_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others 9 1 read-write SPI_SLV_RDBUF_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others 10 1 read-write SPI_SLV_WRBUF_BITLEN_EN 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others 11 1 read-write SPI_DMA_SEG_MAGIC_VALUE The magic value of BM table in master DMA seg-trans. 22 4 read-write MODE Set SPI work mode. 1: slave mode 0: master mode. 26 1 read-write SPI_SOFT_RESET Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state. 27 1 write-only SPI_USR_CONF 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode. 28 1 read-write SPI_MST_FD_WAIT_DMA_TX_DATA In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer. 29 1 read-write SPI_SLAVE1 SPI slave control register 1 0xE4 0x20 SPI_SLV_DATA_BITLEN The transferred data bit length in SPI slave FD and HD mode. 0 18 read-write SPI_SLV_LAST_COMMAND In the slave mode it is the value of command. 18 8 read-write SPI_SLV_LAST_ADDR In the slave mode it is the value of address. 26 6 read-write SPI_CLK_GATE SPI module clock and register clock control 0xE8 0x20 SPI_CLK_EN Set this bit to enable clk gate 0 1 read-write SPI_MST_CLK_ACTIVE Set this bit to power on the SPI module clock. 1 1 read-write SPI_MST_CLK_SEL This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK. 2 1 read-write SPI_DATE Version control 0xF0 0x20 0x02201300 SPI_DATE SPI register version. 0 28 read-write SPI3 SPI (Serial Peripheral Interface) Controller 0x60025000 SPI4 SPI (Serial Peripheral Interface) Controller 0x60037000 SYSTIMER System Timer SYSTIMER 0x60023000 0x0 0x90 registers SYSTIMER_TARGET0_EDGE 37 SYSTIMER_TARGET1_EDGE 38 SYSTIMER_TARGET2_EDGE 39 CONF Configure system timer clock 0x0 0x20 0x46000000 SYSTIMER_CLK_FO systimer clock force on 0 1 read-write ETM_EN enable systimer's etm task and event 1 1 read-write TARGET2_WORK_EN target2 work enable 22 1 read-write TARGET1_WORK_EN target1 work enable 23 1 read-write TARGET0_WORK_EN target0 work enable 24 1 read-write TIMER_UNIT1_CORE1_STALL_EN If timer unit1 is stalled when core1 stalled 25 1 read-write TIMER_UNIT1_CORE0_STALL_EN If timer unit1 is stalled when core0 stalled 26 1 read-write TIMER_UNIT0_CORE1_STALL_EN If timer unit0 is stalled when core1 stalled 27 1 read-write TIMER_UNIT0_CORE0_STALL_EN If timer unit0 is stalled when core0 stalled 28 1 read-write TIMER_UNIT1_WORK_EN timer unit1 work enable 29 1 read-write TIMER_UNIT0_WORK_EN timer unit0 work enable 30 1 read-write CLK_EN register file clk gating 31 1 read-write UNIT0_OP system timer unit0 value update register 0x4 0x20 TIMER_UNIT0_VALUE_VALID timer value is sync and valid 29 1 read-only TIMER_UNIT0_UPDATE update timer_unit0 30 1 write-only UNIT1_OP system timer unit1 value update register 0x8 0x20 TIMER_UNIT1_VALUE_VALID timer value is sync and valid 29 1 read-only TIMER_UNIT1_UPDATE update timer unit1 30 1 write-only UNIT0_LOAD_HI system timer unit0 value high load register 0xC 0x20 TIMER_UNIT0_LOAD_HI timer unit0 load high 20 bits 0 20 read-write UNIT0_LOAD_LO system timer unit0 value low load register 0x10 0x20 TIMER_UNIT0_LOAD_LO timer unit0 load low 32 bits 0 32 read-write UNIT1_LOAD_HI system timer unit1 value high load register 0x14 0x20 TIMER_UNIT1_LOAD_HI timer unit1 load high 20 bits 0 20 read-write UNIT1_LOAD_LO system timer unit1 value low load register 0x18 0x20 TIMER_UNIT1_LOAD_LO timer unit1 load low 32 bits 0 32 read-write TARGET0_HI system timer comp0 value high register 0x1C 0x20 TIMER_TARGET0_HI timer taget0 high 20 bits 0 20 read-write TARGET0_LO system timer comp0 value low register 0x20 0x20 TIMER_TARGET0_LO timer taget0 low 32 bits 0 32 read-write TARGET1_HI system timer comp1 value high register 0x24 0x20 TIMER_TARGET1_HI timer taget1 high 20 bits 0 20 read-write TARGET1_LO system timer comp1 value low register 0x28 0x20 TIMER_TARGET1_LO timer taget1 low 32 bits 0 32 read-write TARGET2_HI system timer comp2 value high register 0x2C 0x20 TIMER_TARGET2_HI timer taget2 high 20 bits 0 20 read-write TARGET2_LO system timer comp2 value low register 0x30 0x20 TIMER_TARGET2_LO timer taget2 low 32 bits 0 32 read-write TARGET0_CONF system timer comp0 target mode register 0x34 0x20 TARGET0_PERIOD target0 period 0 26 read-write TARGET0_PERIOD_MODE Set target0 to period mode 30 1 read-write TARGET0_TIMER_UNIT_SEL select which unit to compare 31 1 read-write TARGET1_CONF system timer comp1 target mode register 0x38 0x20 TARGET1_PERIOD target1 period 0 26 read-write TARGET1_PERIOD_MODE Set target1 to period mode 30 1 read-write TARGET1_TIMER_UNIT_SEL select which unit to compare 31 1 read-write TARGET2_CONF system timer comp2 target mode register 0x3C 0x20 TARGET2_PERIOD target2 period 0 26 read-write TARGET2_PERIOD_MODE Set target2 to period mode 30 1 read-write TARGET2_TIMER_UNIT_SEL select which unit to compare 31 1 read-write UNIT0_VALUE_HI system timer unit0 value high register 0x40 0x20 TIMER_UNIT0_VALUE_HI timer read value high 20bits 0 20 read-only UNIT0_VALUE_LO system timer unit0 value low register 0x44 0x20 TIMER_UNIT0_VALUE_LO timer read value low 32bits 0 32 read-only UNIT1_VALUE_HI system timer unit1 value high register 0x48 0x20 TIMER_UNIT1_VALUE_HI timer read value high 20bits 0 20 read-only UNIT1_VALUE_LO system timer unit1 value low register 0x4C 0x20 TIMER_UNIT1_VALUE_LO timer read value low 32bits 0 32 read-only COMP0_LOAD system timer comp0 conf sync register 0x50 0x20 TIMER_COMP0_LOAD timer comp0 sync enable signal 0 1 write-only COMP1_LOAD system timer comp1 conf sync register 0x54 0x20 TIMER_COMP1_LOAD timer comp1 sync enable signal 0 1 write-only COMP2_LOAD system timer comp2 conf sync register 0x58 0x20 TIMER_COMP2_LOAD timer comp2 sync enable signal 0 1 write-only UNIT0_LOAD system timer unit0 conf sync register 0x5C 0x20 TIMER_UNIT0_LOAD timer unit0 sync enable signal 0 1 write-only UNIT1_LOAD system timer unit1 conf sync register 0x60 0x20 TIMER_UNIT1_LOAD timer unit1 sync enable signal 0 1 write-only INT_ENA systimer interrupt enable register 0x64 0x20 TARGET0_INT_ENA interupt0 enable 0 1 read-write TARGET1_INT_ENA interupt1 enable 1 1 read-write TARGET2_INT_ENA interupt2 enable 2 1 read-write INT_RAW systimer interrupt raw register 0x68 0x20 TARGET0_INT_RAW interupt0 raw 0 1 read-only TARGET1_INT_RAW interupt1 raw 1 1 read-only TARGET2_INT_RAW interupt2 raw 2 1 read-only INT_CLR systimer interrupt clear register 0x6C 0x20 TARGET0_INT_CLR interupt0 clear 0 1 write-only TARGET1_INT_CLR interupt1 clear 1 1 write-only TARGET2_INT_CLR interupt2 clear 2 1 write-only INT_ST systimer interrupt status register 0x70 0x20 TARGET0_INT_ST interupt0 status 0 1 read-only TARGET1_INT_ST interupt1 status 1 1 read-only TARGET2_INT_ST interupt2 status 2 1 read-only REAL_TARGET0_LO system timer comp0 actual target value low register 0x74 0x20 TARGET0_LO_RO actual target value value low 32bits 0 32 read-only REAL_TARGET0_HI system timer comp0 actual target value high register 0x78 0x20 TARGET0_HI_RO actual target value value high 20bits 0 20 read-only REAL_TARGET1_LO system timer comp1 actual target value low register 0x7C 0x20 TARGET1_LO_RO actual target value value low 32bits 0 32 read-only REAL_TARGET1_HI system timer comp1 actual target value high register 0x80 0x20 TARGET1_HI_RO actual target value value high 20bits 0 20 read-only REAL_TARGET2_LO system timer comp2 actual target value low register 0x84 0x20 TARGET2_LO_RO actual target value value low 32bits 0 32 read-only REAL_TARGET2_HI system timer comp2 actual target value high register 0x88 0x20 TARGET2_HI_RO actual target value value high 20bits 0 20 read-only DATE system timer version control register 0xFC 0x20 0x02201073 DATE systimer register version 0 32 read-write TEE Peripheral TEE TEE 0x60098000 0x0 0x88 registers M0_MODE_CTRL Tee mode control register 0x0 0x20 M0_MODE M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M1_MODE_CTRL Tee mode control register 0x4 0x20 0x00000003 M1_MODE M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M2_MODE_CTRL Tee mode control register 0x8 0x20 M2_MODE M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M3_MODE_CTRL Tee mode control register 0xC 0x20 0x00000003 M3_MODE M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M4_MODE_CTRL Tee mode control register 0x10 0x20 0x00000003 M4_MODE M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M5_MODE_CTRL Tee mode control register 0x14 0x20 0x00000003 M5_MODE M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M6_MODE_CTRL Tee mode control register 0x18 0x20 0x00000003 M6_MODE M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M7_MODE_CTRL Tee mode control register 0x1C 0x20 0x00000003 M7_MODE M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M8_MODE_CTRL Tee mode control register 0x20 0x20 0x00000003 M8_MODE M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M9_MODE_CTRL Tee mode control register 0x24 0x20 0x00000003 M9_MODE M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M10_MODE_CTRL Tee mode control register 0x28 0x20 0x00000003 M10_MODE M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M11_MODE_CTRL Tee mode control register 0x2C 0x20 0x00000003 M11_MODE M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M12_MODE_CTRL Tee mode control register 0x30 0x20 0x00000003 M12_MODE M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M13_MODE_CTRL Tee mode control register 0x34 0x20 0x00000003 M13_MODE M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M14_MODE_CTRL Tee mode control register 0x38 0x20 0x00000003 M14_MODE M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M15_MODE_CTRL Tee mode control register 0x3C 0x20 0x00000003 M15_MODE M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M16_MODE_CTRL Tee mode control register 0x40 0x20 0x00000003 M16_MODE M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M17_MODE_CTRL Tee mode control register 0x44 0x20 0x00000003 M17_MODE M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M18_MODE_CTRL Tee mode control register 0x48 0x20 0x00000003 M18_MODE M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M19_MODE_CTRL Tee mode control register 0x4C 0x20 0x00000003 M19_MODE M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M20_MODE_CTRL Tee mode control register 0x50 0x20 0x00000003 M20_MODE M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M21_MODE_CTRL Tee mode control register 0x54 0x20 0x00000003 M21_MODE M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M22_MODE_CTRL Tee mode control register 0x58 0x20 0x00000003 M22_MODE M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M23_MODE_CTRL Tee mode control register 0x5C 0x20 0x00000003 M23_MODE M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M24_MODE_CTRL Tee mode control register 0x60 0x20 0x00000003 M24_MODE M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M25_MODE_CTRL Tee mode control register 0x64 0x20 0x00000003 M25_MODE M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M26_MODE_CTRL Tee mode control register 0x68 0x20 0x00000003 M26_MODE M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M27_MODE_CTRL Tee mode control register 0x6C 0x20 0x00000003 M27_MODE M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M28_MODE_CTRL Tee mode control register 0x70 0x20 0x00000003 M28_MODE M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M29_MODE_CTRL Tee mode control register 0x74 0x20 0x00000003 M29_MODE M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M30_MODE_CTRL Tee mode control register 0x78 0x20 0x00000003 M30_MODE M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write M31_MODE_CTRL Tee mode control register 0x7C 0x20 0x00000003 M31_MODE M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode 0 2 read-write CLOCK_GATE Clock gating register 0x80 0x20 0x00000001 CLK_EN reg_clk_en 0 1 read-write DATE Version register 0xFFC 0x20 0x02205282 DATE reg_tee_date 0 28 read-write TIMG0 Timer Group TIMG 0x6001F000 0x0 0x68 registers TG0_T0_LEVEL 32 TG0_WDT_LEVEL 33 T0CONFIG Timer %s configuration register 0x0 0x20 0x60002000 T_USE_XTAL 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group. 9 1 read-write T_ALARM_EN When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs. 10 1 read-write T_DIVCNT_RST When set, Timer %s 's clock divider counter will be reset. 12 1 write-only T_DIVIDER Timer %s clock (T%s_clk) prescaler value. 13 16 read-write T_AUTORELOAD When set, timer %s auto-reload at alarm is enabled. 29 1 read-write T_INCREASE When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement. 30 1 read-write T_EN When set, the timer %s time-base counter is enabled. 31 1 read-write T0LO Timer %s current value, low 32 bits 0x4 0x20 T_LO After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here. 0 32 read-only T0HI Timer %s current value, high 22 bits 0x8 0x20 T_HI After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter of timer %s can be read here. 0 22 read-only T0UPDATE Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG 0xC 0x20 T_UPDATE After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched. 31 1 read-write T0ALARMLO Timer %s alarm value, low 32 bits 0x10 0x20 T_ALARM_LO Timer %s alarm trigger time-base counter value, low 32 bits. 0 32 read-write T0ALARMHI Timer %s alarm value, high bits 0x14 0x20 T_ALARM_HI Timer %s alarm trigger time-base counter value, high 22 bits. 0 22 read-write T0LOADLO Timer %s reload value, low 32 bits 0x18 0x20 T_LOAD_LO Low 32 bits of the value that a reload will load onto timer %s time-base Counter. 0 32 read-write T0LOADHI Timer %s reload value, high 22 bits 0x1C 0x20 T_LOAD_HI High 22 bits of the value that a reload will load onto timer %s time-base counter. 0 22 read-write T0LOAD Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG 0x20 0x20 T_LOAD Write any value to trigger a timer %s time-base counter reload. 0 32 write-only WDTCONFIG0 Watchdog timer configuration register 0x48 0x20 0x0004C000 WDT_APPCPU_RESET_EN WDT reset CPU enable. 12 1 read-write WDT_PROCPU_RESET_EN WDT reset CPU enable. 13 1 read-write WDT_FLASHBOOT_MOD_EN When set, Flash boot protection is enabled. 14 1 read-write WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. 15 3 read-write WDT_CPU_RESET_LENGTH CPU reset signal length selection. 0: 100 ns, 1: 200 ns, 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. 18 3 read-write WDT_USE_XTAL choose WDT clock:0-apb_clk, 1-xtal_clk. 21 1 read-write WDT_CONF_UPDATE_EN update the WDT configuration registers 22 1 write-only WDT_STG3 Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 23 2 read-write WDT_STG2 Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 25 2 read-write WDT_STG1 Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 27 2 read-write WDT_STG0 Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system. 29 2 read-write WDT_EN When set, MWDT is enabled. 31 1 read-write WDTCONFIG1 Watchdog timer prescaler register 0x4C 0x20 0x00010000 WDT_DIVCNT_RST When set, WDT 's clock divider counter will be reset. 0 1 write-only WDT_CLK_PRESCALE MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE. 16 16 read-write WDTCONFIG2 Watchdog timer stage 0 timeout value 0x50 0x20 0x018CBA80 WDT_STG0_HOLD Stage 0 timeout value, in MWDT clock cycles. 0 32 read-write WDTCONFIG3 Watchdog timer stage 1 timeout value 0x54 0x20 0x07FFFFFF WDT_STG1_HOLD Stage 1 timeout value, in MWDT clock cycles. 0 32 read-write WDTCONFIG4 Watchdog timer stage 2 timeout value 0x58 0x20 0x000FFFFF WDT_STG2_HOLD Stage 2 timeout value, in MWDT clock cycles. 0 32 read-write WDTCONFIG5 Watchdog timer stage 3 timeout value 0x5C 0x20 0x000FFFFF WDT_STG3_HOLD Stage 3 timeout value, in MWDT clock cycles. 0 32 read-write WDTFEED Write to feed the watchdog timer 0x60 0x20 WDT_FEED Write any value to feed the MWDT. (WO) 0 32 write-only WDTWPROTECT Watchdog write protect register 0x64 0x20 0x50D83AA1 WDT_WKEY If the register contains a different value than its reset value, write protection is enabled. 0 32 read-write RTCCALICFG RTC calibration configure register 0x68 0x20 0x00011000 RTC_CALI_START_CYCLING 0: one-shot frequency calculation,1: periodic frequency calculation, 12 1 read-write RTC_CALI_CLK_SEL 0:rtc slow clock. 1:clk_8m, 2:xtal_32k. 13 2 read-write RTC_CALI_RDY indicate one-shot frequency calculation is done. 15 1 read-only RTC_CALI_MAX Configure the time to calculate RTC slow clock's frequency. 16 15 read-write RTC_CALI_START Set this bit to start one-shot frequency calculation. 31 1 read-write RTCCALICFG1 RTC calibration configure1 register 0x6C 0x20 RTC_CALI_CYCLING_DATA_VLD indicate periodic frequency calculation is done. 0 1 read-only RTC_CALI_VALUE When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency. 7 25 read-only INT_ENA_TIMERS Interrupt enable bits 0x70 0x20 T0_INT_ENA The interrupt enable bit for the TIMG_T0_INT interrupt. 0 1 read-write WDT_INT_ENA The interrupt enable bit for the TIMG_WDT_INT interrupt. 1 1 read-write INT_RAW_TIMERS Raw interrupt status 0x74 0x20 T0_INT_RAW The raw interrupt status bit for the TIMG_T0_INT interrupt. 0 1 read-only WDT_INT_RAW The raw interrupt status bit for the TIMG_WDT_INT interrupt. 1 1 read-only INT_ST_TIMERS Masked interrupt status 0x78 0x20 T0_INT_ST The masked interrupt status bit for the TIMG_T0_INT interrupt. 0 1 read-only WDT_INT_ST The masked interrupt status bit for the TIMG_WDT_INT interrupt. 1 1 read-only INT_CLR_TIMERS Interrupt clear bits 0x7C 0x20 T0_INT_CLR Set this bit to clear the TIMG_T0_INT interrupt. 0 1 write-only WDT_INT_CLR Set this bit to clear the TIMG_WDT_INT interrupt. 1 1 write-only RTCCALICFG2 Timer group calibration register 0x80 0x20 0xFFFFFF98 RTC_CALI_TIMEOUT RTC calibration timeout indicator 0 1 read-only RTC_CALI_TIMEOUT_RST_CNT Cycles that release calibration timeout reset 3 4 read-write RTC_CALI_TIMEOUT_THRES Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered. 7 25 read-write NTIMERS_DATE Timer version control register 0xF8 0x20 0x02206072 NTIMGS_DATE Timer version control register 0 28 read-write REGCLK Timer group clock gate register 0xFC 0x20 0x70000000 ETM_EN enable timer's etm task and event 28 1 read-write WDT_CLK_IS_ACTIVE enable WDT's clock 29 1 read-write TIMER_CLK_IS_ACTIVE enable Timer 30's clock 30 1 read-write CLK_EN Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software. 31 1 read-write TIMG1 Timer Group 0x60020000 TG1_T0_LEVEL 34 TG1_WDT_LEVEL 35 TWAI Two-Wire Automotive Interface TWAI 0x6002B000 0x0 0x80 registers TWAI 25 MODE TWAI mode register. 0x0 0x20 0x00000001 RESET_MODE 1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode. 0 1 read-write LISTEN_ONLY_MODE 1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal. 1 1 read-write SELF_TEST_MODE 1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission. 2 1 read-write ACCEPTANCE_FILTER_MODE 1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active). 3 1 read-write CMD TWAI command register. 0x4 0x20 TX_REQUEST 1: present, a message shall be transmitted. 0: absent 0 1 write-only ABORT_TX 1: present, if not already in progress, a pending transmission request is cancelled. 0: absent 1 1 write-only RELEASE_BUFFER 1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action 2 1 write-only CLEAR_DATA_OVERRUN 1: clear, the data overrun status bit is cleared. 0: no action. 3 1 write-only SELF_RX_REQUEST 1: present, a message shall be transmitted and received simultaneously. 0: absent. 4 1 write-only STATUS TWAI status register. 0x8 0x20 RECEIVE_BUFFER 1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available 0 1 read-only OVERRUN 1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given 1 1 read-only TRANSMIT_BUFFER 1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted 2 1 read-only TRANSMISSION_COMPLETE 1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed 3 1 read-only RECEIVE 1: receive, the TWAI controller is receiving a message. 0: idle 4 1 read-only TRANSMIT 1: transmit, the TWAI controller is transmitting a message. 0: idle 5 1 read-only ERR 1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit 6 1 read-only NODE_BUS_OFF 1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities 7 1 read-only MISS 1: current message is destroyed because of FIFO overflow. 8 1 read-only INTERRUPT Interrupt signals' register. 0xC 0x20 RECEIVE_INT_ST 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset 0 1 read-only TRANSMIT_INT_ST 1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset 1 1 read-only ERR_WARNING_INT_ST 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset 2 1 read-only DATA_OVERRUN_INT_ST 1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset 3 1 read-only ERR_PASSIVE_INT_ST 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset 5 1 read-only ARBITRATION_LOST_INT_ST 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset 6 1 read-only BUS_ERR_INT_ST 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset 7 1 read-only IDLE_INT_ST 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset 8 1 read-only INTERRUPT_ENABLE Interrupt enable register. 0x10 0x20 EXT_RECEIVE_INT_ENA 1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable 0 1 read-write EXT_TRANSMIT_INT_ENA 1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable 1 1 read-write EXT_ERR_WARNING_INT_ENA 1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable 2 1 read-write EXT_DATA_OVERRUN_INT_ENA 1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable 3 1 read-write ERR_PASSIVE_INT_ENA 1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable 5 1 read-write ARBITRATION_LOST_INT_ENA 1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable 6 1 read-write BUS_ERR_INT_ENA 1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable 7 1 read-write IDLE_INT_ENA 1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable 8 1 read-only BUS_TIMING_0 Bit timing configuration register 0. 0x18 0x20 BAUD_PRESC The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. 0 14 read-write SYNC_JUMP_WIDTH The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. 14 2 read-write BUS_TIMING_1 Bit timing configuration register 1. 0x1C 0x20 TIME_SEGMENT1 The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. 0 4 read-write TIME_SEGMENT2 The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. 4 3 read-write TIME_SAMPLING 1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode. 7 1 read-write ARB_LOST_CAP TWAI arbiter lost capture register. 0x2C 0x20 ARBITRATION_LOST_CAPTURE This register contains information about the bit position of losing arbitration. 0 5 read-only ERR_CODE_CAP TWAI error info capture register. 0x30 0x20 ERR_CAPTURE_CODE_SEGMENT This register contains information about the location of errors on the bus. 0 5 read-only ERR_CAPTURE_CODE_DIRECTION 1: RX, error occurred during reception. 0: TX, error occurred during transmission. 5 1 read-only ERR_CAPTURE_CODE_TYPE 00: bit error. 01: form error. 10:stuff error. 11:other type of error. 6 2 read-only ERR_WARNING_LIMIT TWAI error threshold configuration register. 0x34 0x20 0x00000060 ERR_WARNING_LIMIT The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. 0 8 read-write RX_ERR_CNT Rx error counter register. 0x38 0x20 RX_ERR_CNT The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. 0 8 read-write TX_ERR_CNT Tx error counter register. 0x3C 0x20 TX_ERR_CNT The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. 0 8 read-write DATA_0 Data register 0. 0x40 0x20 DATA_0 In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0. 0 8 read-write DATA_1 Data register 1. 0x44 0x20 DATA_1 In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1. 0 8 read-write DATA_2 Data register 2. 0x48 0x20 DATA_2 In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2. 0 8 read-write DATA_3 Data register 3. 0x4C 0x20 DATA_3 In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3. 0 8 read-write DATA_4 Data register 4. 0x50 0x20 DATA_4 In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4. 0 8 read-write DATA_5 Data register 5. 0x54 0x20 DATA_5 In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5. 0 8 read-write DATA_6 Data register 6. 0x58 0x20 DATA_6 In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6. 0 8 read-write DATA_7 Data register 7. 0x5C 0x20 DATA_7 In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7. 0 8 read-write DATA_8 Data register 8. 0x60 0x20 DATA_8 In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8. 0 8 read-write DATA_9 Data register 9. 0x64 0x20 DATA_9 In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9. 0 8 read-write DATA_10 Data register 10. 0x68 0x20 DATA_10 In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10. 0 8 read-write DATA_11 Data register 11. 0x6C 0x20 DATA_11 In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11. 0 8 read-write DATA_12 Data register 12. 0x70 0x20 DATA_12 In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12. 0 8 read-write RX_MESSAGE_COUNTER Received message counter register. 0x74 0x20 RX_MESSAGE_COUNTER Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. 0 7 read-only CLOCK_DIVIDER Clock divider register. 0x7C 0x20 CD These bits are used to define the frequency at the external CLKOUT pin. 0 8 read-write CLOCK_OFF 1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode. 8 1 read-write SW_STANDBY_CFG Software configure standby pin directly. 0x80 0x20 0x00000002 SW_STANDBY_EN Enable standby pin. 0 1 read-write SW_STANDBY_CLR Clear standby pin. 1 1 read-write HW_CFG Hardware configure standby pin. 0x84 0x20 HW_STANDBY_EN Enable function that hardware control standby pin. 0 1 read-write HW_STANDBY_CNT Configure standby counter. 0x88 0x20 0x00000001 STANDBY_WAIT_CNT Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. 0 32 read-write IDLE_INTR_CNT Configure idle interrupt counter. 0x8C 0x20 0x00000001 IDLE_INTR_CNT Configure the number of cycles before triggering idle interrupt. 0 32 read-write ECO_CFG ECO configuration register. 0x90 0x20 0x00000002 RDN_ENA Enable eco module. 0 1 read-write RDN_RESULT Output of eco module. 1 1 read-only UART0 UART (Universal Asynchronous Receiver-Transmitter) Controller UART 0x60000000 0x0 0x98 registers UART0 21 FIFO FIFO data register 0x0 0x20 RXFIFO_RD_BYTE UART 0 accesses FIFO via this register. 0 8 read-only INT_RAW Raw interrupt status 0x4 0x20 0x00000002 RXFIFO_FULL_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. 0 1 read-only TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . 1 1 read-only PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error in the data. 2 1 read-only FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error . 3 1 read-only RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. 4 1 read-only DSR_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. 5 1 read-only CTS_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. 6 1 read-only BRK_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. 7 1 read-only RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. 8 1 read-only SW_XON_INT_RAW This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. 9 1 read-only SW_XOFF_INT_RAW This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. 10 1 read-only GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. 11 1 read-only TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. 12 1 read-only TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. 13 1 read-only TX_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. 14 1 read-only RS485_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. 15 1 read-only RS485_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. 16 1 read-only RS485_CLASH_INT_RAW This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. 17 1 read-only AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. 18 1 read-only WAKEUP_INT_RAW This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. 19 1 read-only INT_ST Masked interrupt status 0x8 0x20 RXFIFO_FULL_INT_ST This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. 0 1 read-only TXFIFO_EMPTY_INT_ST This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. 1 1 read-only PARITY_ERR_INT_ST This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. 2 1 read-only FRM_ERR_INT_ST This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. 3 1 read-only RXFIFO_OVF_INT_ST This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. 4 1 read-only DSR_CHG_INT_ST This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. 5 1 read-only CTS_CHG_INT_ST This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. 6 1 read-only BRK_DET_INT_ST This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. 7 1 read-only RXFIFO_TOUT_INT_ST This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. 8 1 read-only SW_XON_INT_ST This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. 9 1 read-only SW_XOFF_INT_ST This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. 10 1 read-only GLITCH_DET_INT_ST This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. 11 1 read-only TX_BRK_DONE_INT_ST This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. 12 1 read-only TX_BRK_IDLE_DONE_INT_ST This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. 13 1 read-only TX_DONE_INT_ST This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. 14 1 read-only RS485_PARITY_ERR_INT_ST This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. 15 1 read-only RS485_FRM_ERR_INT_ST This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. 16 1 read-only RS485_CLASH_INT_ST This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. 17 1 read-only AT_CMD_CHAR_DET_INT_ST This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. 18 1 read-only WAKEUP_INT_ST This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. 19 1 read-only INT_ENA Interrupt enable bits 0xC 0x20 RXFIFO_FULL_INT_ENA This is the enable bit for rxfifo_full_int_st register. 0 1 read-write TXFIFO_EMPTY_INT_ENA This is the enable bit for txfifo_empty_int_st register. 1 1 read-write PARITY_ERR_INT_ENA This is the enable bit for parity_err_int_st register. 2 1 read-write FRM_ERR_INT_ENA This is the enable bit for frm_err_int_st register. 3 1 read-write RXFIFO_OVF_INT_ENA This is the enable bit for rxfifo_ovf_int_st register. 4 1 read-write DSR_CHG_INT_ENA This is the enable bit for dsr_chg_int_st register. 5 1 read-write CTS_CHG_INT_ENA This is the enable bit for cts_chg_int_st register. 6 1 read-write BRK_DET_INT_ENA This is the enable bit for brk_det_int_st register. 7 1 read-write RXFIFO_TOUT_INT_ENA This is the enable bit for rxfifo_tout_int_st register. 8 1 read-write SW_XON_INT_ENA This is the enable bit for sw_xon_int_st register. 9 1 read-write SW_XOFF_INT_ENA This is the enable bit for sw_xoff_int_st register. 10 1 read-write GLITCH_DET_INT_ENA This is the enable bit for glitch_det_int_st register. 11 1 read-write TX_BRK_DONE_INT_ENA This is the enable bit for tx_brk_done_int_st register. 12 1 read-write TX_BRK_IDLE_DONE_INT_ENA This is the enable bit for tx_brk_idle_done_int_st register. 13 1 read-write TX_DONE_INT_ENA This is the enable bit for tx_done_int_st register. 14 1 read-write RS485_PARITY_ERR_INT_ENA This is the enable bit for rs485_parity_err_int_st register. 15 1 read-write RS485_FRM_ERR_INT_ENA This is the enable bit for rs485_parity_err_int_st register. 16 1 read-write RS485_CLASH_INT_ENA This is the enable bit for rs485_clash_int_st register. 17 1 read-write AT_CMD_CHAR_DET_INT_ENA This is the enable bit for at_cmd_char_det_int_st register. 18 1 read-write WAKEUP_INT_ENA This is the enable bit for uart_wakeup_int_st register. 19 1 read-write INT_CLR Interrupt clear bits 0x10 0x20 RXFIFO_FULL_INT_CLR Set this bit to clear the rxfifo_full_int_raw interrupt. 0 1 write-only TXFIFO_EMPTY_INT_CLR Set this bit to clear txfifo_empty_int_raw interrupt. 1 1 write-only PARITY_ERR_INT_CLR Set this bit to clear parity_err_int_raw interrupt. 2 1 write-only FRM_ERR_INT_CLR Set this bit to clear frm_err_int_raw interrupt. 3 1 write-only RXFIFO_OVF_INT_CLR Set this bit to clear rxfifo_ovf_int_raw interrupt. 4 1 write-only DSR_CHG_INT_CLR Set this bit to clear the dsr_chg_int_raw interrupt. 5 1 write-only CTS_CHG_INT_CLR Set this bit to clear the cts_chg_int_raw interrupt. 6 1 write-only BRK_DET_INT_CLR Set this bit to clear the brk_det_int_raw interrupt. 7 1 write-only RXFIFO_TOUT_INT_CLR Set this bit to clear the rxfifo_tout_int_raw interrupt. 8 1 write-only SW_XON_INT_CLR Set this bit to clear the sw_xon_int_raw interrupt. 9 1 write-only SW_XOFF_INT_CLR Set this bit to clear the sw_xoff_int_raw interrupt. 10 1 write-only GLITCH_DET_INT_CLR Set this bit to clear the glitch_det_int_raw interrupt. 11 1 write-only TX_BRK_DONE_INT_CLR Set this bit to clear the tx_brk_done_int_raw interrupt.. 12 1 write-only TX_BRK_IDLE_DONE_INT_CLR Set this bit to clear the tx_brk_idle_done_int_raw interrupt. 13 1 write-only TX_DONE_INT_CLR Set this bit to clear the tx_done_int_raw interrupt. 14 1 write-only RS485_PARITY_ERR_INT_CLR Set this bit to clear the rs485_parity_err_int_raw interrupt. 15 1 write-only RS485_FRM_ERR_INT_CLR Set this bit to clear the rs485_frm_err_int_raw interrupt. 16 1 write-only RS485_CLASH_INT_CLR Set this bit to clear the rs485_clash_int_raw interrupt. 17 1 write-only AT_CMD_CHAR_DET_INT_CLR Set this bit to clear the at_cmd_char_det_int_raw interrupt. 18 1 write-only WAKEUP_INT_CLR Set this bit to clear the uart_wakeup_int_raw interrupt. 19 1 write-only CLKDIV_SYNC Clock divider configuration 0x14 0x20 0x000002B6 CLKDIV The integral part of the frequency divider factor. 0 12 read-write CLKDIV_FRAG The decimal part of the frequency divider factor. 20 4 read-write RX_FILT Rx Filter configuration 0x18 0x20 0x00000008 GLITCH_FILT when input pulse width is lower than this value the pulse is ignored. 0 8 read-write GLITCH_FILT_EN Set this bit to enable Rx signal filter. 8 1 read-write STATUS UART status register 0x1C 0x20 0xE000C000 RXFIFO_CNT Stores the byte number of valid data in Rx-FIFO. 0 8 read-only DSRN The register represent the level value of the internal uart dsr signal. 13 1 read-only CTSN This register represent the level value of the internal uart cts signal. 14 1 read-only RXD This register represent the level value of the internal uart rxd signal. 15 1 read-only TXFIFO_CNT Stores the byte number of data in Tx-FIFO. 16 8 read-only DTRN This bit represents the level of the internal uart dtr signal. 29 1 read-only RTSN This bit represents the level of the internal uart rts signal. 30 1 read-only TXD This bit represents the level of the internal uart txd signal. 31 1 read-only CONF0_SYNC a 0x20 0x20 0x0010001C PARITY This register is used to configure the parity check mode. 0 1 read-write PARITY_EN Set this bit to enable uart parity check. 1 1 read-write BIT_NUM This register is used to set the length of data. 2 2 read-write STOP_BIT_NUM This register is used to set the length of stop bit. 4 2 read-write TXD_BRK Set this bit to enbale transmitter to send NULL when the process of sending data is done. 6 1 read-write IRDA_DPLX Set this bit to enable IrDA loopback mode. 7 1 read-write IRDA_TX_EN This is the start enable bit for IrDA transmitter. 8 1 read-write IRDA_WCTL 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0. 9 1 read-write IRDA_TX_INV Set this bit to invert the level of IrDA transmitter. 10 1 read-write IRDA_RX_INV Set this bit to invert the level of IrDA receiver. 11 1 read-write LOOPBACK Set this bit to enable uart loopback test mode. 12 1 read-write TX_FLOW_EN Set this bit to enable flow control function for transmitter. 13 1 read-write IRDA_EN Set this bit to enable IrDA protocol. 14 1 read-write RXD_INV Set this bit to inverse the level value of uart rxd signal. 15 1 read-write TXD_INV Set this bit to inverse the level value of uart txd signal. 16 1 read-write DIS_RX_DAT_OVF Disable UART Rx data overflow detect. 17 1 read-write ERR_WR_MASK 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong. 18 1 read-write AUTOBAUD_EN This is the enable bit for detecting baudrate. 19 1 read-write MEM_CLK_EN UART memory clock gate enable signal. 20 1 read-write SW_RTS This register is used to configure the software rts signal which is used in software flow control. 21 1 read-write RXFIFO_RST Set this bit to reset the uart receive-FIFO. 22 1 read-write TXFIFO_RST Set this bit to reset the uart transmit-FIFO. 23 1 read-write CONF1 Configuration register 1 0x24 0x20 0x00006060 RXFIFO_FULL_THRHD It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. 0 8 read-write TXFIFO_EMPTY_THRHD It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. 8 8 read-write CTS_INV Set this bit to inverse the level value of uart cts signal. 16 1 read-write DSR_INV Set this bit to inverse the level value of uart dsr signal. 17 1 read-write RTS_INV Set this bit to inverse the level value of uart rts signal. 18 1 read-write DTR_INV Set this bit to inverse the level value of uart dtr signal. 19 1 read-write SW_DTR This register is used to configure the software dtr signal which is used in software flow control. 20 1 read-write CLK_EN 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. 21 1 read-write HWFC_CONF_SYNC Hardware flow-control configuration 0x2C 0x20 RX_FLOW_THRHD This register is used to configure the maximum amount of data that can be received when hardware flow control works. 0 8 read-write RX_FLOW_EN This is the flow enable bit for UART receiver. 8 1 read-write SLEEP_CONF0 UART sleep configure register 0 0x30 0x20 WK_CHAR1 This register restores the specified wake up char1 to wake up 0 8 read-write WK_CHAR2 This register restores the specified wake up char2 to wake up 8 8 read-write WK_CHAR3 This register restores the specified wake up char3 to wake up 16 8 read-write WK_CHAR4 This register restores the specified wake up char4 to wake up 24 8 read-write SLEEP_CONF1 UART sleep configure register 1 0x34 0x20 WK_CHAR0 This register restores the specified char0 to wake up 0 8 read-write SLEEP_CONF2 UART sleep configure register 2 0x38 0x20 0x001404F0 ACTIVE_THRESHOLD The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. 0 10 read-write RX_WAKE_UP_THRHD In wake up mode 1 this field is used to set the received data number threshold to wake up chip. 10 8 read-write WK_CHAR_NUM This register is used to select number of wake up char. 18 3 read-write WK_CHAR_MASK This register is used to mask wake up char. 21 5 read-write WK_MODE_SEL This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than 26 2 read-write SWFC_CONF0_SYNC Software flow-control character configuration 0x3C 0x20 0x00001311 XON_CHAR This register stores the Xon flow control char. 0 8 read-write XOFF_CHAR This register stores the Xoff flow control char. 8 8 read-write XON_XOFF_STILL_SEND In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled. 16 1 read-write SW_FLOW_CON_EN Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. 17 1 read-write XONOFF_DEL Set this bit to remove flow control char from the received data. 18 1 read-write FORCE_XON Set this bit to enable the transmitter to go on sending data. 19 1 read-write FORCE_XOFF Set this bit to stop the transmitter from sending data. 20 1 read-write SEND_XON Set this bit to send Xon char. It is cleared by hardware automatically. 21 1 read-write SEND_XOFF Set this bit to send Xoff char. It is cleared by hardware automatically. 22 1 read-write SWFC_CONF1 Software flow-control character configuration 0x40 0x20 0x0000E000 XON_THRESHOLD When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. 0 8 read-write XOFF_THRESHOLD When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. 8 8 read-write TXBRK_CONF_SYNC Tx Break character configuration 0x44 0x20 0x0000000A TX_BRK_NUM This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. 0 8 read-write IDLE_CONF_SYNC Frame-end idle configuration 0x48 0x20 0x00040100 RX_IDLE_THRHD It will produce frame end signal when receiver takes more time to receive one byte data than this register value. 0 10 read-write TX_IDLE_NUM This register is used to configure the duration time between transfers. 10 10 read-write RS485_CONF_SYNC RS485 mode configuration 0x4C 0x20 RS485_EN Set this bit to choose the rs485 mode. 0 1 read-write DL0_EN Set this bit to delay the stop bit by 1 bit. 1 1 read-write DL1_EN Set this bit to delay the stop bit by 1 bit. 2 1 read-write RS485TX_RX_EN Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. 3 1 read-write RS485RXBY_TX_EN 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy. 4 1 read-write RS485_RX_DLY_NUM This register is used to delay the receiver's internal data signal. 5 1 read-write RS485_TX_DLY_NUM This register is used to delay the transmitter's internal data signal. 6 4 read-write AT_CMD_PRECNT_SYNC Pre-sequence timing configuration 0x50 0x20 0x00000901 PRE_IDLE_NUM This register is used to configure the idle duration time before the first at_cmd is received by receiver. 0 16 read-write AT_CMD_POSTCNT_SYNC Post-sequence timing configuration 0x54 0x20 0x00000901 POST_IDLE_NUM This register is used to configure the duration time between the last at_cmd and the next data. 0 16 read-write AT_CMD_GAPTOUT_SYNC Timeout configuration 0x58 0x20 0x0000000B RX_GAP_TOUT This register is used to configure the duration time between the at_cmd chars. 0 16 read-write AT_CMD_CHAR_SYNC AT escape sequence detection configuration 0x5C 0x20 0x0000032B AT_CMD_CHAR This register is used to configure the content of at_cmd char. 0 8 read-write CHAR_NUM This register is used to configure the num of continuous at_cmd chars received by receiver. 8 8 read-write MEM_CONF UART memory power configuration 0x60 0x20 MEM_FORCE_PD Set this bit to force power down UART memory. 25 1 read-write MEM_FORCE_PU Set this bit to force power up UART memory. 26 1 read-write TOUT_CONF_SYNC UART threshold and allocation configuration 0x64 0x20 0x00000028 RX_TOUT_EN This is the enble bit for uart receiver's timeout function. 0 1 read-write RX_TOUT_FLOW_DIS Set this bit to stop accumulating idle_cnt when hardware flow control works. 1 1 read-write RX_TOUT_THRHD This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. 2 10 read-write MEM_TX_STATUS Tx-SRAM write and read offset address. 0x68 0x20 TX_SRAM_WADDR This register stores the offset write address in Tx-SRAM. 0 8 read-only TX_SRAM_RADDR This register stores the offset read address in Tx-SRAM. 9 8 read-only MEM_RX_STATUS Rx-SRAM write and read offset address. 0x6C 0x20 0x00010080 RX_SRAM_RADDR This register stores the offset read address in RX-SRAM. 0 8 read-only RX_SRAM_WADDR This register stores the offset write address in Rx-SRAM. 9 8 read-only FSM_STATUS UART transmit and receive status. 0x70 0x20 ST_URX_OUT This is the status register of receiver. 0 4 read-only ST_UTX_OUT This is the status register of transmitter. 4 4 read-only POSPULSE Autobaud high pulse register 0x74 0x20 0x00000FFF POSEDGE_MIN_CNT This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. 0 12 read-only NEGPULSE Autobaud low pulse register 0x78 0x20 0x00000FFF NEGEDGE_MIN_CNT This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. 0 12 read-only LOWPULSE Autobaud minimum low pulse duration register 0x7C 0x20 0x00000FFF MIN_CNT This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. 0 12 read-only HIGHPULSE Autobaud minimum high pulse duration register 0x80 0x20 0x00000FFF MIN_CNT This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. 0 12 read-only RXD_CNT Autobaud edge change count register 0x84 0x20 RXD_EDGE_CNT This register stores the count of rxd edge change. It is used in baud rate-detect process. 0 10 read-only CLK_CONF UART core clock configuration 0x88 0x20 0x03000000 TX_SCLK_EN Set this bit to enable UART Tx clock. 24 1 read-write RX_SCLK_EN Set this bit to enable UART Rx clock. 25 1 read-write TX_RST_CORE Write 1 then write 0 to this bit to reset UART Tx. 26 1 read-write RX_RST_CORE Write 1 then write 0 to this bit to reset UART Rx. 27 1 read-write DATE UART Version register 0x8C 0x20 0x02207250 DATE This is the version register. 0 32 read-write AFIFO_STATUS UART AFIFO Status 0x90 0x20 0x0000000A TX_AFIFO_FULL Full signal of APB TX AFIFO. 0 1 read-only TX_AFIFO_EMPTY Empty signal of APB TX AFIFO. 1 1 read-only RX_AFIFO_FULL Full signal of APB RX AFIFO. 2 1 read-only RX_AFIFO_EMPTY Empty signal of APB RX AFIFO. 3 1 read-only REG_UPDATE UART Registers Configuration Update register 0x98 0x20 REG_UPDATE Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. 0 1 read-write ID UART ID register 0x9C 0x20 0x00000500 ID This register is used to configure the uart_id. 0 32 read-write UART1 UART (Universal Asynchronous Receiver-Transmitter) Controller 0x60010000 UART1 22 UHCI0 Universal Host Controller Interface UHCI 0x60014000 0x0 0x84 registers UHCI0 15 CONF0 a 0x0 0x20 0x000006E0 TX_RST Write 1 then write 0 to this bit to reset decode state machine. 0 1 read-write RX_RST Write 1 then write 0 to this bit to reset encode state machine. 1 1 read-write UART0_CE Set this bit to link up HCI and UART0. 2 1 read-write UART1_CE Set this bit to link up HCI and UART1. 3 1 read-write SEPER_EN Set this bit to separate the data frame using a special char. 5 1 read-write HEAD_EN Set this bit to encode the data packet with a formatting header. 6 1 read-write CRC_REC_EN Set this bit to enable UHCI to receive the 16 bit CRC. 7 1 read-write UART_IDLE_EOF_EN If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. 8 1 read-write LEN_EOF_EN If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. 9 1 read-write ENCODE_CRC_EN Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. 10 1 read-write CLK_EN 1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers. 11 1 read-write UART_RX_BRK_EOF_EN If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. 12 1 read-write INT_RAW a 0x4 0x20 RX_START_INT_RAW a 0 1 read-only TX_START_INT_RAW a 1 1 read-only RX_HUNG_INT_RAW a 2 1 read-only TX_HUNG_INT_RAW a 3 1 read-only SEND_S_REG_Q_INT_RAW a 4 1 read-only SEND_A_REG_Q_INT_RAW a 5 1 read-only OUT_EOF_INT_RAW This is the interrupt raw bit. Triggered when there are some errors in EOF in the 6 1 read-only APP_CTRL0_INT_RAW Soft control int raw bit. 7 1 read-write APP_CTRL1_INT_RAW Soft control int raw bit. 8 1 read-write INT_ST a 0x8 0x20 RX_START_INT_ST a 0 1 read-only TX_START_INT_ST a 1 1 read-only RX_HUNG_INT_ST a 2 1 read-only TX_HUNG_INT_ST a 3 1 read-only SEND_S_REG_Q_INT_ST a 4 1 read-only SEND_A_REG_Q_INT_ST a 5 1 read-only OUTLINK_EOF_ERR_INT_ST a 6 1 read-only APP_CTRL0_INT_ST a 7 1 read-only APP_CTRL1_INT_ST a 8 1 read-only INT_ENA a 0xC 0x20 RX_START_INT_ENA a 0 1 read-write TX_START_INT_ENA a 1 1 read-write RX_HUNG_INT_ENA a 2 1 read-write TX_HUNG_INT_ENA a 3 1 read-write SEND_S_REG_Q_INT_ENA a 4 1 read-write SEND_A_REG_Q_INT_ENA a 5 1 read-write OUTLINK_EOF_ERR_INT_ENA a 6 1 read-write APP_CTRL0_INT_ENA a 7 1 read-write APP_CTRL1_INT_ENA a 8 1 read-write INT_CLR a 0x10 0x20 RX_START_INT_CLR a 0 1 write-only TX_START_INT_CLR a 1 1 write-only RX_HUNG_INT_CLR a 2 1 write-only TX_HUNG_INT_CLR a 3 1 write-only SEND_S_REG_Q_INT_CLR a 4 1 write-only SEND_A_REG_Q_INT_CLR a 5 1 write-only OUTLINK_EOF_ERR_INT_CLR a 6 1 write-only APP_CTRL0_INT_CLR a 7 1 write-only APP_CTRL1_INT_CLR a 8 1 write-only CONF1 a 0x14 0x20 0x00000033 CHECK_SUM_EN a 0 1 read-write CHECK_SEQ_EN a 1 1 read-write CRC_DISABLE a 2 1 read-write SAVE_HEAD a 3 1 read-write TX_CHECK_SUM_RE a 4 1 read-write TX_ACK_NUM_RE a 5 1 read-write WAIT_SW_START a 7 1 read-write SW_START a 8 1 write-only STATE0 a 0x18 0x20 RX_ERR_CAUSE a 0 3 read-only DECODE_STATE a 3 3 read-only STATE1 a 0x1C 0x20 ENCODE_STATE a 0 3 read-only ESCAPE_CONF a 0x20 0x20 0x00000033 TX_C0_ESC_EN a 0 1 read-write TX_DB_ESC_EN a 1 1 read-write TX_11_ESC_EN a 2 1 read-write TX_13_ESC_EN a 3 1 read-write RX_C0_ESC_EN a 4 1 read-write RX_DB_ESC_EN a 5 1 read-write RX_11_ESC_EN a 6 1 read-write RX_13_ESC_EN a 7 1 read-write HUNG_CONF a 0x24 0x20 0x00810810 TXFIFO_TIMEOUT a 0 8 read-write TXFIFO_TIMEOUT_SHIFT a 8 3 read-write TXFIFO_TIMEOUT_ENA a 11 1 read-write RXFIFO_TIMEOUT a 12 8 read-write RXFIFO_TIMEOUT_SHIFT a 20 3 read-write RXFIFO_TIMEOUT_ENA a 23 1 read-write ACK_NUM a 0x28 0x20 ACK_NUM a 0 3 read-write LOAD a 3 1 write-only RX_HEAD a 0x2C 0x20 RX_HEAD a 0 32 read-only QUICK_SENT a 0x30 0x20 SINGLE_SEND_NUM a 0 3 read-write SINGLE_SEND_EN a 3 1 write-only ALWAYS_SEND_NUM a 4 3 read-write ALWAYS_SEND_EN a 7 1 read-write REG_Q0_WORD0 a 0x34 0x20 SEND_Q0_WORD0 a 0 32 read-write REG_Q0_WORD1 a 0x38 0x20 SEND_Q0_WORD1 a 0 32 read-write REG_Q1_WORD0 a 0x3C 0x20 SEND_Q1_WORD0 a 0 32 read-write REG_Q1_WORD1 a 0x40 0x20 SEND_Q1_WORD1 a 0 32 read-write REG_Q2_WORD0 a 0x44 0x20 SEND_Q2_WORD0 a 0 32 read-write REG_Q2_WORD1 a 0x48 0x20 SEND_Q2_WORD1 a 0 32 read-write REG_Q3_WORD0 a 0x4C 0x20 SEND_Q3_WORD0 a 0 32 read-write REG_Q3_WORD1 a 0x50 0x20 SEND_Q3_WORD1 a 0 32 read-write REG_Q4_WORD0 a 0x54 0x20 SEND_Q4_WORD0 a 0 32 read-write REG_Q4_WORD1 a 0x58 0x20 SEND_Q4_WORD1 a 0 32 read-write REG_Q5_WORD0 a 0x5C 0x20 SEND_Q5_WORD0 a 0 32 read-write REG_Q5_WORD1 a 0x60 0x20 SEND_Q5_WORD1 a 0 32 read-write REG_Q6_WORD0 a 0x64 0x20 SEND_Q6_WORD0 a 0 32 read-write REG_Q6_WORD1 a 0x68 0x20 SEND_Q6_WORD1 a 0 32 read-write ESC_CONF0 a 0x6C 0x20 0x00DCDBC0 SEPER_CHAR a 0 8 read-write SEPER_ESC_CHAR0 a 8 8 read-write SEPER_ESC_CHAR1 a 16 8 read-write ESC_CONF1 a 0x70 0x20 0x00DDDBDB ESC_SEQ0 a 0 8 read-write ESC_SEQ0_CHAR0 a 8 8 read-write ESC_SEQ0_CHAR1 a 16 8 read-write ESC_CONF2 a 0x74 0x20 0x00DEDB11 ESC_SEQ1 a 0 8 read-write ESC_SEQ1_CHAR0 a 8 8 read-write ESC_SEQ1_CHAR1 a 16 8 read-write ESC_CONF3 a 0x78 0x20 0x00DFDB13 ESC_SEQ2 a 0 8 read-write ESC_SEQ2_CHAR0 a 8 8 read-write ESC_SEQ2_CHAR1 a 16 8 read-write PKT_THRES a 0x7C 0x20 0x00000080 PKT_THRS a 0 13 read-write DATE a 0x80 0x20 0x02201100 DATE a 0 32 read-write UHCI1 Universal Host Controller Interface 0x6000C000 USB_DEVICE Full-speed USB Serial/JTAG Controller USB_DEVICE 0x60043000 0x0 0x70 registers USB 26 EP1 FIFO access for the CDC-ACM data IN and OUT endpoints. 0x0 0x20 USB_SERIAL_JTAG_RDWR_BYTE Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO. 0 8 read-write EP1_CONF Configuration and control registers for the CDC-ACM FIFOs. 0x4 0x20 0x00000002 USB_SERIAL_JTAG_WR_DONE Set this bit to indicate writing byte data to UART Tx FIFO is done. 0 1 write-only USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host. 1 1 read-only USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL 1'b1: Indicate there is data in UART Rx FIFO. 2 1 read-only INT_RAW Interrupt raw status register. 0x8 0x20 0x00000008 USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. 0 1 read-only USB_SERIAL_JTAG_SOF_INT_RAW The raw interrupt bit turns to high level when SOF frame is received. 1 1 read-only USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. 2 1 read-only USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. 3 1 read-only USB_SERIAL_JTAG_PID_ERR_INT_RAW The raw interrupt bit turns to high level when pid error is detected. 4 1 read-only USB_SERIAL_JTAG_CRC5_ERR_INT_RAW The raw interrupt bit turns to high level when CRC5 error is detected. 5 1 read-only USB_SERIAL_JTAG_CRC16_ERR_INT_RAW The raw interrupt bit turns to high level when CRC16 error is detected. 6 1 read-only USB_SERIAL_JTAG_STUFF_ERR_INT_RAW The raw interrupt bit turns to high level when stuff error is detected. 7 1 read-only USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. 8 1 read-only USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW The raw interrupt bit turns to high level when usb bus reset is detected. 9 1 read-only USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. 10 1 read-only USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. 11 1 read-only USB_SERIAL_JTAG_RTS_CHG_INT_RAW The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. 12 1 read-only USB_SERIAL_JTAG_DTR_CHG_INT_RAW The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. 13 1 read-only USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW The raw interrupt bit turns to high level when level of GET LINE CODING request is received. 14 1 read-only USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW The raw interrupt bit turns to high level when level of SET LINE CODING request is received. 15 1 read-only INT_ST Interrupt status register. 0xC 0x20 USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 read-only USB_SERIAL_JTAG_SOF_INT_ST The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. 1 1 read-only USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 read-only USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 read-only USB_SERIAL_JTAG_PID_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. 4 1 read-only USB_SERIAL_JTAG_CRC5_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 read-only USB_SERIAL_JTAG_CRC16_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 read-only USB_SERIAL_JTAG_STUFF_ERR_INT_ST The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 read-only USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. 8 1 read-only USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 read-only USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 read-only USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 read-only USB_SERIAL_JTAG_RTS_CHG_INT_ST The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. 12 1 read-only USB_SERIAL_JTAG_DTR_CHG_INT_ST The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. 13 1 read-only USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. 14 1 read-only USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. 15 1 read-only INT_ENA Interrupt enable status register. 0x10 0x20 USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 read-write USB_SERIAL_JTAG_SOF_INT_ENA The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. 1 1 read-write USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 read-write USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 read-write USB_SERIAL_JTAG_PID_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. 4 1 read-write USB_SERIAL_JTAG_CRC5_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 read-write USB_SERIAL_JTAG_CRC16_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 read-write USB_SERIAL_JTAG_STUFF_ERR_INT_ENA The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 read-write USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. 8 1 read-write USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 read-write USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 read-write USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 read-write USB_SERIAL_JTAG_RTS_CHG_INT_ENA The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. 12 1 read-write USB_SERIAL_JTAG_DTR_CHG_INT_ENA The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. 13 1 read-write USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. 14 1 read-write USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. 15 1 read-write INT_CLR Interrupt clear status register. 0x14 0x20 USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. 0 1 write-only USB_SERIAL_JTAG_SOF_INT_CLR Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. 1 1 write-only USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. 2 1 write-only USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. 3 1 write-only USB_SERIAL_JTAG_PID_ERR_INT_CLR Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. 4 1 write-only USB_SERIAL_JTAG_CRC5_ERR_INT_CLR Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. 5 1 write-only USB_SERIAL_JTAG_CRC16_ERR_INT_CLR Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. 6 1 write-only USB_SERIAL_JTAG_STUFF_ERR_INT_CLR Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. 7 1 write-only USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. 8 1 write-only USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. 9 1 write-only USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. 10 1 write-only USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. 11 1 write-only USB_SERIAL_JTAG_RTS_CHG_INT_CLR Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. 12 1 write-only USB_SERIAL_JTAG_DTR_CHG_INT_CLR Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. 13 1 write-only USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. 14 1 write-only USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. 15 1 write-only CONF0 PHY hardware configuration. 0x18 0x20 0x00004200 USB_SERIAL_JTAG_PHY_SEL Select internal/external PHY 0 1 read-write USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE Enable software control USB D+ D- exchange 1 1 read-write USB_SERIAL_JTAG_EXCHG_PINS USB D+ D- exchange 2 1 read-write USB_SERIAL_JTAG_VREFH Control single-end input high threshold,1.76V to 2V, step 80mV 3 2 read-write USB_SERIAL_JTAG_VREFL Control single-end input low threshold,0.8V to 1.04V, step 80mV 5 2 read-write USB_SERIAL_JTAG_VREF_OVERRIDE Enable software control input threshold 7 1 read-write USB_SERIAL_JTAG_PAD_PULL_OVERRIDE Enable software control USB D+ D- pullup pulldown 8 1 read-write USB_SERIAL_JTAG_DP_PULLUP Control USB D+ pull up. 9 1 read-write USB_SERIAL_JTAG_DP_PULLDOWN Control USB D+ pull down. 10 1 read-write USB_SERIAL_JTAG_DM_PULLUP Control USB D- pull up. 11 1 read-write USB_SERIAL_JTAG_DM_PULLDOWN Control USB D- pull down. 12 1 read-write USB_SERIAL_JTAG_PULLUP_VALUE Control pull up value. 13 1 read-write USB_SERIAL_JTAG_USB_PAD_ENABLE Enable USB pad function. 14 1 read-write USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix. 15 1 read-write TEST Registers used for debugging the PHY. 0x1C 0x20 0x00000030 USB_SERIAL_JTAG_TEST_ENABLE Enable test of the USB pad 0 1 read-write USB_SERIAL_JTAG_TEST_USB_OE USB pad oen in test 1 1 read-write USB_SERIAL_JTAG_TEST_TX_DP USB D+ tx value in test 2 1 read-write USB_SERIAL_JTAG_TEST_TX_DM USB D- tx value in test 3 1 read-write USB_SERIAL_JTAG_TEST_RX_RCV USB RCV value in test 4 1 read-only USB_SERIAL_JTAG_TEST_RX_DP USB D+ rx value in test 5 1 read-only USB_SERIAL_JTAG_TEST_RX_DM USB D- rx value in test 6 1 read-only JFIFO_ST JTAG FIFO status and control registers. 0x20 0x20 0x00000044 USB_SERIAL_JTAG_IN_FIFO_CNT JTAT in fifo counter. 0 2 read-only USB_SERIAL_JTAG_IN_FIFO_EMPTY 1: JTAG in fifo is empty. 2 1 read-only USB_SERIAL_JTAG_IN_FIFO_FULL 1: JTAG in fifo is full. 3 1 read-only USB_SERIAL_JTAG_OUT_FIFO_CNT JTAT out fifo counter. 4 2 read-only USB_SERIAL_JTAG_OUT_FIFO_EMPTY 1: JTAG out fifo is empty. 6 1 read-only USB_SERIAL_JTAG_OUT_FIFO_FULL 1: JTAG out fifo is full. 7 1 read-only USB_SERIAL_JTAG_IN_FIFO_RESET Write 1 to reset JTAG in fifo. 8 1 read-write USB_SERIAL_JTAG_OUT_FIFO_RESET Write 1 to reset JTAG out fifo. 9 1 read-write FRAM_NUM Last received SOF frame index register. 0x24 0x20 USB_SERIAL_JTAG_SOF_FRAME_INDEX Frame index of received SOF frame. 0 11 read-only IN_EP0_ST Control IN endpoint status information. 0x28 0x20 0x00000001 USB_SERIAL_JTAG_IN_EP0_STATE State of IN Endpoint 0. 0 2 read-only USB_SERIAL_JTAG_IN_EP0_WR_ADDR Write data address of IN endpoint 0. 2 7 read-only USB_SERIAL_JTAG_IN_EP0_RD_ADDR Read data address of IN endpoint 0. 9 7 read-only IN_EP1_ST CDC-ACM IN endpoint status information. 0x2C 0x20 0x00000001 USB_SERIAL_JTAG_IN_EP1_STATE State of IN Endpoint 1. 0 2 read-only USB_SERIAL_JTAG_IN_EP1_WR_ADDR Write data address of IN endpoint 1. 2 7 read-only USB_SERIAL_JTAG_IN_EP1_RD_ADDR Read data address of IN endpoint 1. 9 7 read-only IN_EP2_ST CDC-ACM interrupt IN endpoint status information. 0x30 0x20 0x00000001 USB_SERIAL_JTAG_IN_EP2_STATE State of IN Endpoint 2. 0 2 read-only USB_SERIAL_JTAG_IN_EP2_WR_ADDR Write data address of IN endpoint 2. 2 7 read-only USB_SERIAL_JTAG_IN_EP2_RD_ADDR Read data address of IN endpoint 2. 9 7 read-only IN_EP3_ST JTAG IN endpoint status information. 0x34 0x20 0x00000001 USB_SERIAL_JTAG_IN_EP3_STATE State of IN Endpoint 3. 0 2 read-only USB_SERIAL_JTAG_IN_EP3_WR_ADDR Write data address of IN endpoint 3. 2 7 read-only USB_SERIAL_JTAG_IN_EP3_RD_ADDR Read data address of IN endpoint 3. 9 7 read-only OUT_EP0_ST Control OUT endpoint status information. 0x38 0x20 USB_SERIAL_JTAG_OUT_EP0_STATE State of OUT Endpoint 0. 0 2 read-only USB_SERIAL_JTAG_OUT_EP0_WR_ADDR Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. 2 7 read-only USB_SERIAL_JTAG_OUT_EP0_RD_ADDR Read data address of OUT endpoint 0. 9 7 read-only OUT_EP1_ST CDC-ACM OUT endpoint status information. 0x3C 0x20 USB_SERIAL_JTAG_OUT_EP1_STATE State of OUT Endpoint 1. 0 2 read-only USB_SERIAL_JTAG_OUT_EP1_WR_ADDR Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. 2 7 read-only USB_SERIAL_JTAG_OUT_EP1_RD_ADDR Read data address of OUT endpoint 1. 9 7 read-only USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT Data count in OUT endpoint 1 when one packet is received. 16 7 read-only OUT_EP2_ST JTAG OUT endpoint status information. 0x40 0x20 USB_SERIAL_JTAG_OUT_EP2_STATE State of OUT Endpoint 2. 0 2 read-only USB_SERIAL_JTAG_OUT_EP2_WR_ADDR Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. 2 7 read-only USB_SERIAL_JTAG_OUT_EP2_RD_ADDR Read data address of OUT endpoint 2. 9 7 read-only MISC_CONF Clock enable control 0x44 0x20 USB_SERIAL_JTAG_CLK_EN 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers. 0 1 read-write MEM_CONF Memory power control 0x48 0x20 0x00000002 USB_SERIAL_JTAG_USB_MEM_PD 1: power down usb memory. 0 1 read-write USB_SERIAL_JTAG_USB_MEM_CLK_EN 1: Force clock on for usb memory. 1 1 read-write CHIP_RST CDC-ACM chip reset control. 0x4C 0x20 USB_SERIAL_JTAG_RTS 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. 0 1 read-only USB_SERIAL_JTAG_DTR 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. 1 1 read-only USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS Set this bit to disable chip reset from usb serial channel to reset chip. 2 1 read-write SET_LINE_CODE_W0 W0 of SET_LINE_CODING command. 0x50 0x20 USB_SERIAL_JTAG_DW_DTE_RATE The value of dwDTERate set by host through SET_LINE_CODING command. 0 32 read-only SET_LINE_CODE_W1 W1 of SET_LINE_CODING command. 0x54 0x20 USB_SERIAL_JTAG_BCHAR_FORMAT The value of bCharFormat set by host through SET_LINE_CODING command. 0 8 read-only USB_SERIAL_JTAG_BPARITY_TYPE The value of bParityTpye set by host through SET_LINE_CODING command. 8 8 read-only USB_SERIAL_JTAG_BDATA_BITS The value of bDataBits set by host through SET_LINE_CODING command. 16 8 read-only GET_LINE_CODE_W0 W0 of GET_LINE_CODING command. 0x58 0x20 USB_SERIAL_JTAG_GET_DW_DTE_RATE The value of dwDTERate set by software which is requested by GET_LINE_CODING command. 0 32 read-write GET_LINE_CODE_W1 W1 of GET_LINE_CODING command. 0x5C 0x20 USB_SERIAL_JTAG_GET_BDATA_BITS The value of bCharFormat set by software which is requested by GET_LINE_CODING command. 0 8 read-write USB_SERIAL_JTAG_GET_BPARITY_TYPE The value of bParityTpye set by software which is requested by GET_LINE_CODING command. 8 8 read-write USB_SERIAL_JTAG_GET_BCHAR_FORMAT The value of bDataBits set by software which is requested by GET_LINE_CODING command. 16 8 read-write CONFIG_UPDATE Configuration registers' value update 0x60 0x20 USB_SERIAL_JTAG_CONFIG_UPDATE Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. 0 1 write-only SER_AFIFO_CONFIG Serial AFIFO configure register 0x64 0x20 0x00000010 USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR Write 1 to reset CDC_ACM IN async FIFO write clock domain. 0 1 read-write USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD Write 1 to reset CDC_ACM IN async FIFO read clock domain. 1 1 read-write USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR Write 1 to reset CDC_ACM OUT async FIFO write clock domain. 2 1 read-write USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD Write 1 to reset CDC_ACM OUT async FIFO read clock domain. 3 1 read-write USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY CDC_ACM OUTOUT async FIFO empty signal in read clock domain. 4 1 read-only USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL CDC_ACM OUT IN async FIFO empty signal in write clock domain. 5 1 read-only BUS_RESET_ST USB Bus reset status register 0x68 0x20 0x00000001 USB_SERIAL_JTAG_USB_BUS_RESET_ST USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released. 0 1 read-only DATE Date register 0x80 0x20 0x02109220 USB_SERIAL_JTAG_DATE register version. 0 32 read-write