The chip supports 133MHz and the other Pico core already defaults to
the higher speed, so make 133 the default.
It can still be changed through the menus and will stay at 125 unless
pre-existing users change it so they will see no difference.
To remove compiler warning the valid core macro was modified to only check
that the core passed in was < # of total cores. Unfortunately there are
parts of the FreeRTOS code where the passed in core # is -1. The upstream
catches this and returns FALSE, but my hacked version returned TRUE. This
caused interesting memory corruption errors and crashes when the
current task block[-1] was updated.
Undo the change and fix the 1 spot where a warning happens instead.
Undo the forced compiler -O0 for port.c, it was only masking the fault.
Use low power WFE when idle.
Set PORT.C to built `-O0` always because it seems to occasinally end
up with interrupts disabled in task code, causing the SYSTICK never to
fire and killing task switching.
No need for dynamic exceptions. We don't move the execbase.
Adds code to define which pins are used, moving them from the defaults, which are the same as the only three analogue input pins, and adding comments to explain how to change them.
The original didn't give any clues about which pins were used, which isn't ideal for a beginner - it was necessary to look at the code for the library, to work that out.
The new code redundantly defines a pWS pin number (as pBCLK+1), which isn't used in the example, but is meant as a reminder to the person using it, of how to wire up WS.
Using all the work from @hfellner and others, add FreeRTOS
SMP support.
Allow idling cores through the FreeRTOS FIFO queue to
allow for file system and EEPROM support.
Make delay a weak function so FreeRTOS can override.
Add cycle count support under FreeRTOS using a PIO SM.
Use a task-based approach for handling the USB periodic work
instead of the IRQ-based one in the main core.
Set 8 prio levels so it fits in 3 bits nicely (0..7).
I receive mails weekly asking how to use `SoftwareSerial` on this core.
Avoid the issue by including a simple wrapper class around `SerialPIO`
which gives the proper class name and constructor parameters.
Note that inverted mode is not supported.
Adjust the 1/2 bit time to match the number of extra cycles in the actual
PIO loop.
Throw out the entire start bit, which results in sampling the data at the
midpoint and not the starting time of a bit (which was causing random
failures on read data).
Tested at 300bps all the way to 2,000,000bps using a loopback connection.
Fixes#360
* Avoid "chunkiness" of UART FIFO availability
The UART FIFO will generate an IRQ to transfer data into the SerialUART
FIFOs either every 4 received bytes, or every 4 idle byte times. This
causes the ::available count to report "0" until either of those two
cases happen, causing a potentially delay in data becoming available to
the app.
Change the code to pull data from the HW FIFO on a read/available/peek.
Use a non-blocking mutex and IRQ disabling to safely empty the FIFO from
user space. The mutex added to the IRQ is non-blocking and will be
a single CAS the vast majority of the time, so it should not impact the
Serial performance.
Fixes#464 and others where `setPollingMode()` was needed as a workaround.
Make sure we have all mutexes locked before we disable the port and free
the queue to avoid evil cases.
Only init the mutexes once, on object creation.
In polled mode, don't bother acquiring/releasing the fifo mutex.
When begin() is called on an already running port, call end() to clean
up the old data/etc. before making a new queue/config. This avoids a
memory leak and potential write-after-free case.
The PIO and state machine were hard wired, so this caused problems if they were not free. The approach used by the Servo library has been adopted so a free PIO and SM are searched.
The DMA_IRQ_0 was grabbed exclusively, but this conflicts with SPI DMA use. The interrupt is now shared, but has been allocated the highest possible priority.
Since the PDM PIO use is receive only, the PIO state machine RX FIFO's can be joined to reduce DMA interrupt load.
GDB for non-Linux systems was built w/o expat which caused odd behavior
under Windows and other systems (i.e. breakpoints not working, etc.)
New toolchain manually builds cross-compiled libexpat and ensures it is
used, fixing the issue.
Windows OpenOCD binaries now come from manually built and tested copies
(using a real Windows system).
Fixes#478Fixes#457Fixes#456
and probably others...
Fixes#472
Instead of using interrupts, explicitly call the IRQ handler dueing Serial
read/peek/available calls.
Add to keywords.txt for syntax hilighting.
Add poll calls in the SerialUART::write-like calls (write,
flush, etc.)
Really remove division from IRQ routines/
