e25d382732
Using pico-sdk develop branch, add in support for CYW43-based WiFi/BT/BLE boards on the RP2350 such as the SparkFun Thing Plus RP2350 or the Pimoroni Pico Plus 2W. Fixes #2608 Rolls in dynamic SPI divider #2600 * Support LED digitalWrite on RP2350+CYW Also move "special GPIO" to 64 since the Pimoroni Pico 2W uses the RP2350B with 48 GPIOs. * Enable CYW43_PIN_WL_DYNAMIC in IDE and P.IO Allows calling `cyw43_set_pins_wl(cyw43_pin_array);` to redefine the CYW43 hookup in the variant initialization.
485 lines
13 KiB
C++
485 lines
13 KiB
C++
/*
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RP2040 utility class
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Copyright (c) 2021 Earle F. Philhower, III <earlephilhower@yahoo.com>
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <hardware/clocks.h>
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#include <hardware/irq.h>
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#include <hardware/pio.h>
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#include <pico/unique_id.h>
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#ifdef PICO_RP2350
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#include <hardware/regs/powman.h>
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#else
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#include <hardware/regs/vreg_and_chip_reset.h>
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#endif
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#include <hardware/exception.h>
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#include <hardware/watchdog.h>
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#include <hardware/structs/rosc.h>
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#include <hardware/structs/systick.h>
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#include <pico/multicore.h>
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#include <hardware/dma.h>
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#include <pico/rand.h>
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#include <pico/util/queue.h>
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#include <pico/bootrom.h>
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#include "CoreMutex.h"
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#include "PIOProgram.h"
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#include "ccount.pio.h"
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#include <malloc.h>
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#include "_freertos.h"
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extern "C" volatile bool __otherCoreIdled;
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class _MFIFO {
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public:
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_MFIFO() { /* noop */ };
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~_MFIFO() { /* noop */ };
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void begin(int cores) {
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constexpr int FIFOCNT = 8;
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if (cores == 1) {
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_multicore = false;
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return;
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}
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mutex_init(&_idleMutex);
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queue_init(&_queue[0], sizeof(uint32_t), FIFOCNT);
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queue_init(&_queue[1], sizeof(uint32_t), FIFOCNT);
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_multicore = true;
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}
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void registerCore() {
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if (!__isFreeRTOS) {
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multicore_fifo_clear_irq();
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#ifdef PICO_RP2350
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irq_set_exclusive_handler(SIO_IRQ_FIFO, _irq);
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irq_set_enabled(SIO_IRQ_FIFO, true);
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#else
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irq_set_exclusive_handler(SIO_IRQ_PROC0 + get_core_num(), _irq);
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irq_set_enabled(SIO_IRQ_PROC0 + get_core_num(), true);
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#endif
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}
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// FreeRTOS port.c will handle the IRQ hooking
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}
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void push(uint32_t val) {
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while (!push_nb(val)) { /* noop */ }
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}
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bool push_nb(uint32_t val) {
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// Push to the other FIFO
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return queue_try_add(&_queue[get_core_num() ^ 1], &val);
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}
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uint32_t pop() {
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uint32_t ret;
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while (!pop_nb(&ret)) { /* noop */ }
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return ret;
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}
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bool pop_nb(uint32_t *val) {
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// Pop from my own FIFO
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return queue_try_remove(&_queue[get_core_num()], val);
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}
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int available() {
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return queue_get_level(&_queue[get_core_num()]);
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}
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void idleOtherCore() {
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if (!_multicore) {
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return;
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}
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if (__isFreeRTOS) {
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__freertos_idle_other_core();
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} else {
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mutex_enter_blocking(&_idleMutex);
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__otherCoreIdled = false;
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multicore_fifo_push_blocking(_GOTOSLEEP);
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while (!__otherCoreIdled) { /* noop */ }
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}
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}
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void resumeOtherCore() {
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if (!_multicore) {
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return;
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}
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mutex_exit(&_idleMutex);
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__otherCoreIdled = false;
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if (__isFreeRTOS) {
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__freertos_resume_other_core();
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}
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// Other core will exit busy-loop and return to operation
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// once __otherCoreIdled == false.
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}
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void clear() {
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uint32_t val;
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while (queue_try_remove(&_queue[0], &val)) {
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tight_loop_contents();
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}
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while (queue_try_remove(&_queue[1], &val)) {
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tight_loop_contents();
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}
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}
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private:
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static void __no_inline_not_in_flash_func(_irq)() {
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if (!__isFreeRTOS) {
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multicore_fifo_clear_irq();
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noInterrupts(); // We need total control, can't run anything
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while (multicore_fifo_rvalid()) {
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if (_GOTOSLEEP == multicore_fifo_pop_blocking()) {
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__otherCoreIdled = true;
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while (__otherCoreIdled) { /* noop */ }
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break;
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}
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}
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interrupts();
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}
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}
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bool _multicore = false;
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mutex_t _idleMutex;
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queue_t _queue[2];
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static constexpr uint32_t _GOTOSLEEP = 0xC0DED02E;
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};
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class RP2040;
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extern RP2040 rp2040;
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extern "C" void main1();
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extern "C" char __StackLimit;
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extern "C" char __bss_end__;
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extern "C" void setup1() __attribute__((weak));
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extern "C" void loop1() __attribute__((weak));
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extern "C" bool core1_separate_stack;
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extern "C" uint32_t* core1_separate_stack_address;
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class RP2040 {
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public:
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RP2040() { /* noop */ }
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~RP2040() { /* noop */ }
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void begin() {
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_epoch = 0;
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#if !defined(__riscv)
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if (!__isFreeRTOS) {
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// Enable SYSTICK exception
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exception_set_exclusive_handler(SYSTICK_EXCEPTION, _SystickHandler);
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systick_hw->csr = 0x7;
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systick_hw->rvr = 0x00FFFFFF;
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} else {
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#endif
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int off = 0;
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_ccountPgm = new PIOProgram(&ccount_program);
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_ccountPgm->prepare(&_pio, &_sm, &off);
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ccount_program_init(_pio, _sm, off);
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pio_sm_set_enabled(_pio, _sm, true);
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#if !defined(__riscv)
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}
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#endif
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}
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// Convert from microseconds to PIO clock cycles
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static int usToPIOCycles(int us) {
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// Parenthesis needed to guarantee order of operations to avoid 32bit overflow
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return (us * (clock_get_hz(clk_sys) / 1'000'000));
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}
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// Get current clock frequency
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static int f_cpu() {
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return clock_get_hz(clk_sys);
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}
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// Get current CPU core number
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static int cpuid() {
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return sio_hw->cpuid;
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}
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// Get CPU cycle count. Needs to do magic to extens 24b HW to something longer
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volatile uint64_t _epoch = 0;
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inline uint32_t getCycleCount() {
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#if !defined(__riscv)
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if (!__isFreeRTOS) {
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uint32_t epoch;
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uint32_t ctr;
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do {
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epoch = (uint32_t)_epoch;
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ctr = systick_hw->cvr;
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} while (epoch != (uint32_t)_epoch);
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return epoch + (1 << 24) - ctr; /* CTR counts down from 1<<24-1 */
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} else {
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#endif
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return ccount_read(_pio, _sm);
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#if !defined(__riscv)
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}
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#endif
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}
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inline uint64_t getCycleCount64() {
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#if !defined(__riscv)
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if (!__isFreeRTOS) {
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uint64_t epoch;
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uint64_t ctr;
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do {
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epoch = _epoch;
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ctr = systick_hw->cvr;
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} while (epoch != _epoch);
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return epoch + (1LL << 24) - ctr;
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} else {
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#endif
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return ccount_read(_pio, _sm);
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#if !defined(__riscv)
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}
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#endif
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}
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inline int getFreeHeap() {
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return getTotalHeap() - getUsedHeap();
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}
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inline int getUsedHeap() {
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struct mallinfo m = mallinfo();
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return m.uordblks;
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}
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inline int getTotalHeap() {
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return &__StackLimit - &__bss_end__;
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}
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inline int getFreePSRAMHeap() {
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return getTotalPSRAMHeap() - getUsedPSRAMHeap();
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}
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inline int getUsedPSRAMHeap() {
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#if defined(RP2350_PSRAM_CS)
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extern size_t __psram_total_used();
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return __psram_total_used();
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#else
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return 0;
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#endif
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}
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inline int getTotalPSRAMHeap() {
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#if defined(RP2350_PSRAM_CS)
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extern size_t __psram_total_space();
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return __psram_total_space();
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#else
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return 0;
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#endif
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}
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inline uint32_t getStackPointer() {
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uint32_t *sp;
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#if defined(__riscv)
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asm volatile("mv %0, sp" : "=r"(sp));
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#else
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asm volatile("mov %0, sp" : "=r"(sp));
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#endif
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return (uint32_t)sp;
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}
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inline int getFreeStack() {
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const unsigned int sp = getStackPointer();
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uint32_t ref = 0x20040000;
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if (setup1 || loop1) {
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if (core1_separate_stack) {
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ref = cpuid() ? (unsigned int)core1_separate_stack_address : 0x20040000;
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} else {
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ref = cpuid() ? 0x20040000 : 0x20041000;
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}
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}
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return sp - ref;
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}
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inline size_t getPSRAMSize() {
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#if defined(RP2350_PSRAM_CS)
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extern size_t __psram_size;
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return __psram_size;
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#else
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return 0;
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#endif
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}
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void idleOtherCore() {
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fifo.idleOtherCore();
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}
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void resumeOtherCore() {
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fifo.resumeOtherCore();
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}
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void restartCore1() {
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multicore_reset_core1();
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fifo.clear();
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multicore_launch_core1(main1);
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}
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void reboot() {
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watchdog_reboot(0, 0, 10);
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while (1) {
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continue;
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}
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}
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inline void restart() {
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reboot();
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}
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inline void rebootToBootloader() {
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reset_usb_boot(0, 0);
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while (1) {
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continue;
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}
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}
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#ifdef PICO_RP2040
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static void enableDoubleResetBootloader();
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#endif
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void wdt_begin(uint32_t delay_ms) {
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watchdog_enable(delay_ms, 1);
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}
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void wdt_reset() {
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watchdog_update();
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}
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enum resetReason_t {UNKNOWN_RESET, PWRON_RESET, RUN_PIN_RESET, SOFT_RESET, WDT_RESET, DEBUG_RESET, GLITCH_RESET, BROWNOUT_RESET};
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resetReason_t getResetReason(void) {
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io_rw_32 *WD_reason_reg = (io_rw_32 *)(WATCHDOG_BASE + WATCHDOG_REASON_OFFSET);
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if (watchdog_caused_reboot() && watchdog_enable_caused_reboot()) { // watchdog timer
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return WDT_RESET;
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}
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if (*WD_reason_reg & WATCHDOG_REASON_TIMER_BITS) { // soft reset() or reboot()
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return SOFT_RESET;
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}
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#ifdef PICO_RP2350
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// **** RP2350 is untested ****
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io_rw_32 *rrp = (io_rw_32 *)(POWMAN_BASE + POWMAN_CHIP_RESET_OFFSET);
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if (*rrp & POWMAN_CHIP_RESET_HAD_POR_BITS) { // POR: power-on reset (brownout is separately detected on RP2350)
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return PWRON_RESET;
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}
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if (*rrp & POWMAN_CHIP_RESET_HAD_RUN_LOW_BITS) { // RUN pin
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return RUN_PIN_RESET;
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}
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if ((*rrp & POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_BITS) || (*rrp & POWMAN_CHIP_RESET_HAD_RESCUE_BITS) || (*rrp & POWMAN_CHIP_RESET_HAD_HZD_SYS_RESET_REQ_BITS)) { // DEBUG port
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return DEBUG_RESET;
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}
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if (*rrp & POWMAN_CHIP_RESET_HAD_GLITCH_DETECT_BITS) { // power supply glitch
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return GLITCH_RESET;
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}
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if (*rrp & POWMAN_CHIP_RESET_HAD_BOR_BITS) { // power supply brownout reset
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return BROWNOUT_RESET;
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}
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#else
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io_rw_32 *rrp = (io_rw_32 *)(VREG_AND_CHIP_RESET_BASE + VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET);
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if (*rrp & VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS) { // POR: power-on reset or brown-out detection
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return PWRON_RESET;
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}
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if (*rrp & VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS) { // RUN pin
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return RUN_PIN_RESET;
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}
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if (*rrp & VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS) { // DEBUG port
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return DEBUG_RESET; // **** untested **** debug reset may just cause a rebootToBootloader()
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}
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#endif
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return UNKNOWN_RESET;
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}
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const char *getChipID() {
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static char id[2 * PICO_UNIQUE_BOARD_ID_SIZE_BYTES + 1] = { 0 };
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if (!id[0]) {
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pico_get_unique_board_id_string(id, sizeof(id));
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}
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return id;
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}
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#pragma GCC push_options
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#pragma GCC optimize ("Os")
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void *memcpyDMA(void *dest, const void *src, size_t n) {
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// Allocate a DMA channel on 1st call, reuse it every call after
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if (memcpyDMAChannel < 1) {
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memcpyDMAChannel = dma_claim_unused_channel(true);
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dma_channel_config c = dma_channel_get_default_config(memcpyDMAChannel);
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channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
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channel_config_set_read_increment(&c, true);
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channel_config_set_write_increment(&c, true);
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channel_config_set_irq_quiet(&c, true);
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dma_channel_set_config(memcpyDMAChannel, &c, false);
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}
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// If there's any misalignment or too small, use regular memcpy which can handle it
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if ((n < 64) || (((uint32_t)dest) | ((uint32_t)src) | n) & 3) {
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return memcpy(dest, src, n);
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}
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int words = n / 4;
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dma_channel_set_read_addr(memcpyDMAChannel, src, false);
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dma_channel_set_write_addr(memcpyDMAChannel, dest, false);
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dma_channel_set_trans_count(memcpyDMAChannel, words, false);
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dma_channel_start(memcpyDMAChannel);
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while (dma_channel_is_busy(memcpyDMAChannel)) {
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/* busy wait dma */
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}
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return dest;
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}
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#pragma GCC pop_options
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// Multicore comms FIFO
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_MFIFO fifo;
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uint32_t hwrand32() {
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return get_rand_32();
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}
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bool isPicoW() {
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#if !defined(PICO_CYW43_SUPPORTED)
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return false;
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#else
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extern bool __isPicoW;
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return __isPicoW;
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#endif
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}
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private:
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static void _SystickHandler() {
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rp2040._epoch += 1LL << 24;
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}
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PIO _pio;
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int _sm;
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PIOProgram *_ccountPgm;
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int memcpyDMAChannel = -1;
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};
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