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bump-tinyu
| Author | SHA1 | Date | |
|---|---|---|---|
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76eef14b81 |
11 changed files with 81 additions and 693 deletions
174
boards.txt
174
boards.txt
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@ -48,25 +48,21 @@ CH32V00x_EVT.menu.upload_method.swdMethod=WCH-SWD
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CH32V00x_EVT.menu.upload_method.swdMethod.upload.protocol=
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CH32V00x_EVT.menu.upload_method.swdMethod.upload.options=
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CH32V00x_EVT.menu.upload_method.swdMethod.upload.tool=WCH_linkE
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CH32V00x_EVT.menu.upload_method.ispMethod=WCH-ISP
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CH32V00x_EVT.menu.upload_method.ispMethod.upload.protocol=
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CH32V00x_EVT.menu.upload_method.ispMethod.upload.options=
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CH32V00x_EVT.menu.upload_method.ispMethod.upload.tool=wchisp
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# Clock Select
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CH32V00x_EVT.menu.clock.48MHz_HSI=48MHz Internal
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CH32V00x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000 -DF_CPU=48000000
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CH32V00x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000
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CH32V00x_EVT.menu.clock.24MHz_HSI=24MHz Internal
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CH32V00x_EVT.menu.clock.24MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSI=24000000 -DF_CPU=24000000
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CH32V00x_EVT.menu.clock.24MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSI=24000000
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CH32V00x_EVT.menu.clock.8MHz_HSI=8MHz Internal
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CH32V00x_EVT.menu.clock.8MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSI=8000000 -DF_CPU=8000000
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CH32V00x_EVT.menu.clock.8MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSI=8000000
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CH32V00x_EVT.menu.clock.48MHz_HSE=48MHz External
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CH32V00x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000 -DF_CPU=48000000
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CH32V00x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000
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CH32V00x_EVT.menu.clock.24MHz_HSE=24MHz External
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CH32V00x_EVT.menu.clock.24MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSE=24000000 -DF_CPU=24000000
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CH32V00x_EVT.menu.clock.24MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSE=24000000
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CH32V00x_EVT.menu.clock.8MHz_HSE=8MHz External
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CH32V00x_EVT.menu.clock.8MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSE=8000000 -DF_CPU=8000000
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CH32V00x_EVT.menu.clock.8MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSE=8000000
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# Optimizations
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@ -152,25 +148,21 @@ CH32VM00X_EVT.menu.upload_method.swdMethod=WCH-SWD
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CH32VM00X_EVT.menu.upload_method.swdMethod.upload.protocol=
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CH32VM00X_EVT.menu.upload_method.swdMethod.upload.options=
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CH32VM00X_EVT.menu.upload_method.swdMethod.upload.tool=WCH_linkE
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CH32VM00X_EVT.menu.upload_method.ispMethod=WCH-ISP
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CH32VM00X_EVT.menu.upload_method.ispMethod.upload.protocol=
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CH32VM00X_EVT.menu.upload_method.ispMethod.upload.options=
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CH32VM00X_EVT.menu.upload_method.ispMethod.upload.tool=wchisp
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# Clock Select
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CH32VM00X_EVT.menu.clock.48MHz_HSI=48MHz Internal
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CH32VM00X_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000 -DF_CPU=48000000
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CH32VM00X_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000
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CH32VM00X_EVT.menu.clock.24MHz_HSI=24MHz Internal
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CH32VM00X_EVT.menu.clock.24MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSI=24000000 -DF_CPU=24000000
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CH32VM00X_EVT.menu.clock.24MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSI=24000000
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CH32VM00X_EVT.menu.clock.8MHz_HSI=8MHz Internal
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CH32VM00X_EVT.menu.clock.8MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSI=8000000 -DF_CPU=8000000
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CH32VM00X_EVT.menu.clock.8MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSI=8000000
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CH32VM00X_EVT.menu.clock.48MHz_HSE=48MHz External
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CH32VM00X_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000 -DF_CPU=48000000
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CH32VM00X_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000
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CH32VM00X_EVT.menu.clock.24MHz_HSE=24MHz External
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CH32VM00X_EVT.menu.clock.24MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSE=24000000 -DF_CPU=24000000
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CH32VM00X_EVT.menu.clock.24MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSE=24000000
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CH32VM00X_EVT.menu.clock.8MHz_HSE=8MHz External
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CH32VM00X_EVT.menu.clock.8MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSE=8000000 -DF_CPU=8000000
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CH32VM00X_EVT.menu.clock.8MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSE=8000000
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# Optimizations
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@ -256,23 +248,19 @@ CH32X035_EVT.menu.upload_method.swdMethod=WCH-SWD
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CH32X035_EVT.menu.upload_method.swdMethod.upload.protocol=
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CH32X035_EVT.menu.upload_method.swdMethod.upload.options=
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CH32X035_EVT.menu.upload_method.swdMethod.upload.tool=WCH_linkE
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CH32X035_EVT.menu.upload_method.ispMethod=WCH-ISP
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CH32X035_EVT.menu.upload_method.ispMethod.upload.protocol=
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CH32X035_EVT.menu.upload_method.ispMethod.upload.options=
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CH32X035_EVT.menu.upload_method.ispMethod.upload.tool=wchisp
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# Clock Select
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CH32X035_EVT.menu.clock.48MHz_HSI=48MHz Internal
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CH32X035_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000 -DF_CPU=48000000
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CH32X035_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000
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CH32X035_EVT.menu.clock.24MHz_HSI=24MHz Internal
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CH32X035_EVT.menu.clock.24MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSI=24000000 -DF_CPU=24000000
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CH32X035_EVT.menu.clock.24MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_24MHz_HSI=24000000
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CH32X035_EVT.menu.clock.16MHz_HSI=16MHz Internal
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CH32X035_EVT.menu.clock.16MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_16MHz_HSI=16000000 -DF_CPU=16000000
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CH32X035_EVT.menu.clock.16MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_16MHz_HSI=16000000
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CH32X035_EVT.menu.clock.12MHz_HSI=12MHz Internal
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CH32X035_EVT.menu.clock.12MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_12MHz_HSI=12000000 -DF_CPU=12000000
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CH32X035_EVT.menu.clock.12MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_12MHz_HSI=12000000
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CH32X035_EVT.menu.clock.8MHz_HSI=8MHz Internal
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CH32X035_EVT.menu.clock.8MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSI=8000000 -DF_CPU=8000000
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CH32X035_EVT.menu.clock.8MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSI=8000000
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# Optimizations
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@ -358,29 +346,25 @@ CH32V10x_EVT.menu.upload_method.swdMethod=WCH-SWD
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CH32V10x_EVT.menu.upload_method.swdMethod.upload.protocol=
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CH32V10x_EVT.menu.upload_method.swdMethod.upload.options=
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CH32V10x_EVT.menu.upload_method.swdMethod.upload.tool=WCH_linkE
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CH32V10x_EVT.menu.upload_method.ispMethod=WCH-ISP
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CH32V10x_EVT.menu.upload_method.ispMethod.upload.protocol=
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CH32V10x_EVT.menu.upload_method.ispMethod.upload.options=
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CH32V10x_EVT.menu.upload_method.ispMethod.upload.tool=wchisp
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# Clock Select
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CH32V10x_EVT.menu.clock.72MHz_HSI=72MHz Internal
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CH32V10x_EVT.menu.clock.72MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSI=72000000 -DF_CPU=72000000
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CH32V10x_EVT.menu.clock.72MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSI=72000000
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CH32V10x_EVT.menu.clock.56MHz_HSI=56MHz Internal
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CH32V10x_EVT.menu.clock.56MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSI=56000000 -DF_CPU=56000000
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CH32V10x_EVT.menu.clock.56MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSI=56000000
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CH32V10x_EVT.menu.clock.48MHz_HSI=48MHz Internal
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CH32V10x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000 -DF_CPU=48000000
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CH32V10x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000
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CH32V10x_EVT.menu.clock.8MHz_HSI=8MHz Internal
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CH32V10x_EVT.menu.clock.8MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSI=8000000 -DF_CPU=8000000
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CH32V10x_EVT.menu.clock.8MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSI=8000000
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CH32V10x_EVT.menu.clock.72MHz_HSE=72MHz External
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CH32V10x_EVT.menu.clock.72MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSE=72000000 -DF_CPU=72000000
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CH32V10x_EVT.menu.clock.72MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSE=72000000
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CH32V10x_EVT.menu.clock.56MHz_HSE=56MHz External
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CH32V10x_EVT.menu.clock.56MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSE=56000000 -DF_CPU=56000000
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CH32V10x_EVT.menu.clock.56MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSE=56000000
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CH32V10x_EVT.menu.clock.48MHz_HSE=48MHz External
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CH32V10x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000 -DF_CPU=48000000
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CH32V10x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000
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CH32V10x_EVT.menu.clock.8MHz_HSE=8MHz External
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CH32V10x_EVT.menu.clock.8MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSE=8000000 -DF_CPU=8000000
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CH32V10x_EVT.menu.clock.8MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_8MHz_HSE=8000000
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# Optimizations
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@ -476,22 +460,6 @@ CH32V20x_EVT.menu.pnum.CH32V203G8.build.math_lib_gcc=-lm
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CH32V20x_EVT.menu.pnum.CH32V203G8.build.IQ_math_RV32=
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CH32V20x_EVT.menu.pnum.CH32V203G8.build.ch_extra_lib=-lprintf
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#CH32V203G6 EVT Board
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CH32V20x_EVT.menu.pnum.CH32V203G6=CH32V203G6 EVT
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CH32V20x_EVT.menu.pnum.CH32V203G6.node=NODE_V203G6
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CH32V20x_EVT.menu.pnum.CH32V203G6.upload.maximum_size=32768
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CH32V20x_EVT.menu.pnum.CH32V203G6.upload.maximum_data_size=10240
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.mcu=QingKe-V4B
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.board=CH32V203G6
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.series=CH32V20x
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.variant=CH32V20x/CH32V203G6
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.chip=CH32V203
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.march=rv32imacxw
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.mabi=ilp32
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.math_lib_gcc=-lm
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.IQ_math_RV32=
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CH32V20x_EVT.menu.pnum.CH32V203G6.build.ch_extra_lib=-lprintf
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#CH32V203C8 Board
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CH32V20x_EVT.menu.pnum.CH32V203C8=CH32V203C8
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CH32V20x_EVT.menu.pnum.CH32V203C8.node=NODE_V203C8
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@ -512,7 +480,7 @@ CH32V20x_EVT.menu.pnum.CH32V203C8.build.ch_extra_lib=-lprintf
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CH32V20x_EVT.menu.pnum.CH32V203C6=CH32V203C6
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CH32V20x_EVT.menu.pnum.CH32V203C6.node=NODE_V203C6
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CH32V20x_EVT.menu.pnum.CH32V203C6.upload.maximum_size=32768
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CH32V20x_EVT.menu.pnum.CH32V203C6.upload.maximum_data_size=10240
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CH32V20x_EVT.menu.pnum.CH32V203C6.upload.maximum_data_size=20480
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CH32V20x_EVT.menu.pnum.CH32V203C6.build.mcu=QingKe-V4B
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CH32V20x_EVT.menu.pnum.CH32V203C6.build.board=CH32V203C6
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CH32V20x_EVT.menu.pnum.CH32V203C6.build.series=CH32V20x
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@ -538,41 +506,37 @@ CH32V20x_EVT.menu.upload_method.swdMethod=WCH-SWD
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CH32V20x_EVT.menu.upload_method.swdMethod.upload.protocol=
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CH32V20x_EVT.menu.upload_method.swdMethod.upload.options=
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CH32V20x_EVT.menu.upload_method.swdMethod.upload.tool=WCH_linkE
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CH32V20x_EVT.menu.upload_method.ispMethod=WCH-ISP
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CH32V20x_EVT.menu.upload_method.ispMethod.upload.protocol=
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CH32V20x_EVT.menu.upload_method.ispMethod.upload.options=
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CH32V20x_EVT.menu.upload_method.ispMethod.upload.tool=wchisp
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# Clock Select
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CH32V20x_EVT.menu.clock.144MHz_HSI=144MHz Internal
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CH32V20x_EVT.menu.clock.144MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_144MHz_HSI=144000000 -DF_CPU=144000000
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CH32V20x_EVT.menu.clock.144MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_144MHz_HSI=144000000
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CH32V20x_EVT.menu.clock.120MHz_HSI=120MHz Internal
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CH32V20x_EVT.menu.clock.120MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_120MHz_HSI=120000000 -DF_CPU=120000000
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CH32V20x_EVT.menu.clock.120MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_120MHz_HSI=120000000
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||||
CH32V20x_EVT.menu.clock.96MHz_HSI=96MHz Internal
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||||
CH32V20x_EVT.menu.clock.96MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSI=96000000 -DF_CPU=96000000
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||||
CH32V20x_EVT.menu.clock.96MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSI=96000000
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||||
CH32V20x_EVT.menu.clock.72MHz_HSI=72MHz Internal
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||||
CH32V20x_EVT.menu.clock.72MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSI=72000000 -DF_CPU=72000000
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||||
CH32V20x_EVT.menu.clock.72MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSI=72000000
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||||
CH32V20x_EVT.menu.clock.56MHz_HSI=56MHz Internal
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||||
CH32V20x_EVT.menu.clock.56MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSI=56000000 -DF_CPU=56000000
|
||||
CH32V20x_EVT.menu.clock.56MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSI=56000000
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||||
CH32V20x_EVT.menu.clock.48MHz_HSI=48MHz Internal
|
||||
CH32V20x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000 -DF_CPU=48000000
|
||||
CH32V20x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000
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||||
CH32V20x_EVT.menu.clock.HSI=HSI Internal
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||||
CH32V20x_EVT.menu.clock.HSI.build.flags.clock=-DSYSCLK_FREQ_HSI=HSI_VALUE -DF_CPU=HSI_VALUE
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||||
CH32V20x_EVT.menu.clock.HSI.build.flags.clock=-DSYSCLK_FREQ_HSI=HSI_VALUE
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||||
CH32V20x_EVT.menu.clock.144MHz_HSE=144MHz External
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||||
CH32V20x_EVT.menu.clock.144MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_144MHz_HSE=144000000 -DF_CPU=144000000
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||||
CH32V20x_EVT.menu.clock.144MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_144MHz_HSE=144000000
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||||
CH32V20x_EVT.menu.clock.120MHz_HSE=120MHz External
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||||
CH32V20x_EVT.menu.clock.120MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_120MHz_HSE=120000000 -DF_CPU=120000000
|
||||
CH32V20x_EVT.menu.clock.120MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_120MHz_HSE=120000000
|
||||
CH32V20x_EVT.menu.clock.96MHz_HSE=96MHz External
|
||||
CH32V20x_EVT.menu.clock.96MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSE=96000000 -DF_CPU=96000000
|
||||
CH32V20x_EVT.menu.clock.96MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSE=96000000
|
||||
CH32V20x_EVT.menu.clock.72MHz_HSE=72MHz External
|
||||
CH32V20x_EVT.menu.clock.72MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSE=72000000 -DF_CPU=72000000
|
||||
CH32V20x_EVT.menu.clock.72MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSE=72000000
|
||||
CH32V20x_EVT.menu.clock.56MHz_HSE=56MHz External
|
||||
CH32V20x_EVT.menu.clock.56MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSE=56000000 -DF_CPU=56000000
|
||||
CH32V20x_EVT.menu.clock.56MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSE=56000000
|
||||
CH32V20x_EVT.menu.clock.48MHz_HSE=48MHz External
|
||||
CH32V20x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000 -DF_CPU=48000000
|
||||
CH32V20x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000
|
||||
CH32V20x_EVT.menu.clock.HSE=HSE External
|
||||
CH32V20x_EVT.menu.clock.HSE.build.flags.clock=-DSYSCLK_FREQ_HSE=HSE_VALUE -DF_CPU=HSE_VALUE
|
||||
CH32V20x_EVT.menu.clock.HSE.build.flags.clock=-DSYSCLK_FREQ_HSE=HSE_VALUE
|
||||
|
||||
|
||||
# Optimizations
|
||||
|
|
@ -666,41 +630,37 @@ CH32V30x_EVT.menu.upload_method.swdMethod=WCH-SWD
|
|||
CH32V30x_EVT.menu.upload_method.swdMethod.upload.protocol=
|
||||
CH32V30x_EVT.menu.upload_method.swdMethod.upload.options=
|
||||
CH32V30x_EVT.menu.upload_method.swdMethod.upload.tool=WCH_linkE
|
||||
CH32V30x_EVT.menu.upload_method.ispMethod=WCH-ISP
|
||||
CH32V30x_EVT.menu.upload_method.ispMethod.upload.protocol=
|
||||
CH32V30x_EVT.menu.upload_method.ispMethod.upload.options=
|
||||
CH32V30x_EVT.menu.upload_method.ispMethod.upload.tool=wchisp
|
||||
|
||||
|
||||
# Clock Select
|
||||
CH32V30x_EVT.menu.clock.144MHz_HSI=144MHz Internal
|
||||
CH32V30x_EVT.menu.clock.144MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_144MHz_HSI=144000000 -DF_CPU=144000000
|
||||
CH32V30x_EVT.menu.clock.144MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_144MHz_HSI=144000000
|
||||
CH32V30x_EVT.menu.clock.120MHz_HSI=120MHz Internal
|
||||
CH32V30x_EVT.menu.clock.120MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_120MHz_HSI=120000000 -DF_CPU=120000000
|
||||
CH32V30x_EVT.menu.clock.120MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_120MHz_HSI=120000000
|
||||
CH32V30x_EVT.menu.clock.96MHz_HSI=96MHz Internal
|
||||
CH32V30x_EVT.menu.clock.96MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSI=96000000 -DF_CPU=96000000
|
||||
CH32V30x_EVT.menu.clock.96MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSI=96000000
|
||||
CH32V30x_EVT.menu.clock.72MHz_HSI=72MHz Internal
|
||||
CH32V30x_EVT.menu.clock.72MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSI=72000000 -DF_CPU=72000000
|
||||
CH32V30x_EVT.menu.clock.72MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSI=72000000
|
||||
CH32V30x_EVT.menu.clock.56MHz_HSI=56MHz Internal
|
||||
CH32V30x_EVT.menu.clock.56MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSI=56000000 -DF_CPU=56000000
|
||||
CH32V30x_EVT.menu.clock.56MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSI=56000000
|
||||
CH32V30x_EVT.menu.clock.48MHz_HSI=48MHz Internal
|
||||
CH32V30x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000 -DF_CPU=48000000
|
||||
CH32V30x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000
|
||||
CH32V30x_EVT.menu.clock.HSI=HSI Internal
|
||||
CH32V30x_EVT.menu.clock.HSI.build.flags.clock=-DSYSCLK_FREQ_HSI=HSI_VALUE -DF_CPU=HSI_VALUE
|
||||
CH32V30x_EVT.menu.clock.HSI.build.flags.clock=-DSYSCLK_FREQ_HSI=HSI_VALUE
|
||||
CH32V30x_EVT.menu.clock.144MHz_HSE=144MHz External
|
||||
CH32V30x_EVT.menu.clock.144MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_144MHz_HSE=144000000 -DF_CPU=144000000
|
||||
CH32V30x_EVT.menu.clock.144MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_144MHz_HSE=144000000
|
||||
CH32V30x_EVT.menu.clock.120MHz_HSE=120MHz External
|
||||
CH32V30x_EVT.menu.clock.120MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_120MHz_HSE=120000000 -DF_CPU=120000000
|
||||
CH32V30x_EVT.menu.clock.120MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_120MHz_HSE=120000000
|
||||
CH32V30x_EVT.menu.clock.96MHz_HSE=96MHz External
|
||||
CH32V30x_EVT.menu.clock.96MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSE=96000000 -DF_CPU=96000000
|
||||
CH32V30x_EVT.menu.clock.96MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSE=96000000
|
||||
CH32V30x_EVT.menu.clock.72MHz_HSE=72MHz External
|
||||
CH32V30x_EVT.menu.clock.72MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSE=72000000 -DF_CPU=72000000
|
||||
CH32V30x_EVT.menu.clock.72MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSE=72000000
|
||||
CH32V30x_EVT.menu.clock.56MHz_HSE=56MHz External
|
||||
CH32V30x_EVT.menu.clock.56MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSE=56000000 -DF_CPU=56000000
|
||||
CH32V30x_EVT.menu.clock.56MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSE=56000000
|
||||
CH32V30x_EVT.menu.clock.48MHz_HSE=48MHz External
|
||||
CH32V30x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000 -DF_CPU=48000000
|
||||
CH32V30x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000
|
||||
CH32V30x_EVT.menu.clock.HSE=HSE External
|
||||
CH32V30x_EVT.menu.clock.HSE.build.flags.clock=-DSYSCLK_FREQ_HSE=HSE_VALUE -DF_CPU=HSE_VALUE
|
||||
CH32V30x_EVT.menu.clock.HSE.build.flags.clock=-DSYSCLK_FREQ_HSE=HSE_VALUE
|
||||
|
||||
|
||||
# Optimizations
|
||||
|
|
@ -786,35 +746,31 @@ CH32L10x_EVT.menu.upload_method.swdMethod=WCH-SWD
|
|||
CH32L10x_EVT.menu.upload_method.swdMethod.upload.protocol=
|
||||
CH32L10x_EVT.menu.upload_method.swdMethod.upload.options=
|
||||
CH32L10x_EVT.menu.upload_method.swdMethod.upload.tool=WCH_linkE
|
||||
CH32L10x_EVT.menu.upload_method.ispMethod=WCH-ISP
|
||||
CH32L10x_EVT.menu.upload_method.ispMethod.upload.protocol=
|
||||
CH32L10x_EVT.menu.upload_method.ispMethod.upload.options=
|
||||
CH32L10x_EVT.menu.upload_method.ispMethod.upload.tool=wchisp
|
||||
|
||||
|
||||
# Clock Select
|
||||
CH32L10x_EVT.menu.clock.96MHz_HSI=96MHz Internal
|
||||
CH32L10x_EVT.menu.clock.96MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSI=96000000 -DF_CPU=96000000
|
||||
CH32L10x_EVT.menu.clock.96MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSI=96000000
|
||||
CH32L10x_EVT.menu.clock.72MHz_HSI=72MHz Internal
|
||||
CH32L10x_EVT.menu.clock.72MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSI=72000000 -DF_CPU=72000000
|
||||
CH32L10x_EVT.menu.clock.72MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSI=72000000
|
||||
CH32L10x_EVT.menu.clock.56MHz_HSI=56MHz Internal
|
||||
CH32L10x_EVT.menu.clock.56MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSI=56000000 -DF_CPU=56000000
|
||||
CH32L10x_EVT.menu.clock.56MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSI=56000000
|
||||
CH32L10x_EVT.menu.clock.48MHz_HSI=48MHz Internal
|
||||
CH32L10x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000 -DF_CPU=48000000
|
||||
CH32L10x_EVT.menu.clock.48MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSI=48000000
|
||||
CH32L10x_EVT.menu.clock.HSI=HSI Internal
|
||||
CH32L10x_EVT.menu.clock.HSI.build.flags.clock=-DSYSCLK_FREQ_HSI=HSI_VALUE -DF_CPU=HSI_VALUE
|
||||
CH32L10x_EVT.menu.clock.HSI.build.flags.clock=-DSYSCLK_FREQ_HSI=HSI_VALUE
|
||||
CH32L10x_EVT.menu.clock.HSI_LP=HSI_LP Internal
|
||||
CH32L10x_EVT.menu.clock.HSI_LP.build.flags.clock=-DSYSCLK_FREQ_HSI_LP=HSI_LP_VALUE -DF_CPU=HSI_LP_VALUE
|
||||
CH32L10x_EVT.menu.clock.HSI_LP.build.flags.clock=-DSYSCLK_FREQ_HSI_LP=HSI_LP_VALUE
|
||||
CH32L10x_EVT.menu.clock.96MHz_HSE=96MHz External
|
||||
CH32L10x_EVT.menu.clock.96MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSE=96000000 -DF_CPU=96000000
|
||||
CH32L10x_EVT.menu.clock.96MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_96MHz_HSE=96000000
|
||||
CH32L10x_EVT.menu.clock.72MHz_HSE=72MHz External
|
||||
CH32L10x_EVT.menu.clock.72MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSE=72000000 -DF_CPU=72000000
|
||||
CH32L10x_EVT.menu.clock.72MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_72MHz_HSE=72000000
|
||||
CH32L10x_EVT.menu.clock.56MHz_HSE=56MHz External
|
||||
CH32L10x_EVT.menu.clock.56MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSE=56000000 -DF_CPU=56000000
|
||||
CH32L10x_EVT.menu.clock.56MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_56MHz_HSE=56000000
|
||||
CH32L10x_EVT.menu.clock.48MHz_HSE=48MHz External
|
||||
CH32L10x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000 -DF_CPU=48000000
|
||||
CH32L10x_EVT.menu.clock.48MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_48MHz_HSE=48000000
|
||||
CH32L10x_EVT.menu.clock.HSE=HSE External
|
||||
CH32L10x_EVT.menu.clock.HSE.build.flags.clock=-DSYSCLK_FREQ_HSE=HSE_VALUE -DF_CPU=HSE_VALUE
|
||||
CH32L10x_EVT.menu.clock.HSE.build.flags.clock=-DSYSCLK_FREQ_HSE=HSE_VALUE
|
||||
|
||||
|
||||
# Optimizations
|
||||
|
|
|
|||
|
|
@ -11,21 +11,15 @@ int main( void )
|
|||
{
|
||||
pre_init( );
|
||||
#if defined(USE_TINYUSB)
|
||||
if (TinyUSB_Device_Init) {
|
||||
TinyUSB_Device_Init(0);
|
||||
}
|
||||
TinyUSB_Device_Init(0);
|
||||
#endif
|
||||
setup( );
|
||||
|
||||
do {
|
||||
loop( );
|
||||
#if defined(USE_TINYUSB)
|
||||
if (TinyUSB_Device_Task) {
|
||||
TinyUSB_Device_Task();
|
||||
}
|
||||
if (TinyUSB_Device_FlushCDC) {
|
||||
TinyUSB_Device_FlushCDC();
|
||||
}
|
||||
TinyUSB_Device_Task();
|
||||
TinyUSB_Device_FlushCDC();
|
||||
#endif
|
||||
} while (1);
|
||||
|
||||
|
|
|
|||
11
platform.txt
11
platform.txt
|
|
@ -65,7 +65,7 @@ build.variant_h=
|
|||
|
||||
# These can be overridden in platform.local.txt
|
||||
compiler.c.extra_flags=
|
||||
compiler.c.elf.extra_flags=-Wl,--defsym=__FLASH_SIZE={upload.maximum_size} -Wl,--defsym=__RAM_SIZE={upload.maximum_data_size}
|
||||
compiler.c.elf.extra_flags=
|
||||
compiler.cpp.extra_flags=
|
||||
compiler.cpp.std=gnu++14
|
||||
compiler.S.extra_flags=
|
||||
|
|
@ -169,17 +169,10 @@ tools.WCH_linkE.upload.params.quiet=
|
|||
tools.WCH_linkE.upload.config={runtime.tools.openocd.path}/bin/wch-riscv.cfg
|
||||
tools.WCH_linkE.upload.pattern="{path}{cmd}" -f "{upload.config}" -c init -c halt -c "program {{build.path}/{build.project_name}.elf} verify; wlink_reset_resume; exit;"
|
||||
|
||||
|
||||
#tools.WCH_linkE.upload.pattern="{path}{cmd}" -f {upload.config} -c init -c halt -c "program {{build.path}/{build.project_name}.elf}; verify_image {{build.path}/{build.project_name}.elf}; wlink_reset_resume; exit;"
|
||||
|
||||
|
||||
## WCH-ISP
|
||||
tools.wchisp.path={runtime.tools.wchisp.path}/
|
||||
tools.wchisp.cmd=wchisp
|
||||
tools.wchisp.upload.params.verbose=
|
||||
tools.wchisp.upload.params.quiet=
|
||||
tools.wchisp.upload.pattern="{path}{cmd}" {upload.verbose} flash "{build.path}/{build.project_name}.elf"
|
||||
|
||||
|
||||
# Debugger configuration (general options)
|
||||
# ----------------------------------------
|
||||
# EXPERIMENTAL feature:
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
__flash_size = DEFINED(__FLASH_SIZE) ? __FLASH_SIZE : 64K;
__ram_size = DEFINED(__RAM_SIZE) ? __RAM_SIZE : 20K;
__stack_size = DEFINED(__STACK_SIZE) ? __STACK_SIZE : 2048;
ENTRY( _start )
PROVIDE( _stack_size = __stack_size );
MEMORY
{
/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
/*
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
*/
/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
/**/
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = __flash_size
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = __ram_size
/* CH32V20x_D8 - CH32V203RB
CH32V20x_D8W - CH32V208x
FLASH + RAM supports the following configuration
FLASH-128K + RAM-64K
FLASH-144K + RAM-48K
FLASH-160K + RAM-32K
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
*/
}
SECTIONS
{
.init :
{
_sinit = .;
. = ALIGN(4);
KEEP(*(SORT_NONE(.init)))
. = ALIGN(4);
_einit = .;
} >FLASH AT>FLASH
.vector :
{
*(.vector);
. = ALIGN(64);
} >FLASH AT>FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
*(.rodata*)
*(.gnu.linkonce.t.*)
. = ALIGN(4);
} >FLASH AT>FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4);
} >FLASH AT>FLASH
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH AT>FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH AT>FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH AT>FLASH
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH AT>FLASH
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >FLASH AT>FLASH
.dalign :
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
} >RAM AT>FLASH
.dlalign :
{
. = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
.data :
{
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(4);
PROVIDE( _edata = .);
} >RAM AT>FLASH
.bss :
{
. = ALIGN(4);
PROVIDE( _sbss = .);
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss*)
*(.gnu.linkonce.b.*)
*(COMMON*)
. = ALIGN(4);
PROVIDE( _ebss = .);
} >RAM AT>FLASH
PROVIDE( _end = _ebss);
PROVIDE( end = . );
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
{
PROVIDE( _heap_end = . );
. = ALIGN(4);
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
} >RAM
}
|
||||
ENTRY( _start )
__stack_size = 2048;
PROVIDE( _stack_size = __stack_size );
MEMORY
{
/* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203K6-CH32V203C6 */
/*
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K
*/
/* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */
/**/
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
/* CH32V20x_D8 - CH32V203RB
CH32V20x_D8W - CH32V208x
FLASH + RAM supports the following configuration
FLASH-128K + RAM-64K
FLASH-144K + RAM-48K
FLASH-160K + RAM-32K
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
*/
}
SECTIONS
{
.init :
{
_sinit = .;
. = ALIGN(4);
KEEP(*(SORT_NONE(.init)))
. = ALIGN(4);
_einit = .;
} >FLASH AT>FLASH
.vector :
{
*(.vector);
. = ALIGN(64);
} >FLASH AT>FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
*(.rodata*)
*(.gnu.linkonce.t.*)
. = ALIGN(4);
} >FLASH AT>FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4);
} >FLASH AT>FLASH
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH AT>FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH AT>FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH AT>FLASH
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH AT>FLASH
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >FLASH AT>FLASH
.dalign :
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
} >RAM AT>FLASH
.dlalign :
{
. = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
.data :
{
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(4);
PROVIDE( _edata = .);
} >RAM AT>FLASH
.bss :
{
. = ALIGN(4);
PROVIDE( _sbss = .);
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss*)
*(.gnu.linkonce.b.*)
*(COMMON*)
. = ALIGN(4);
PROVIDE( _ebss = .);
} >RAM AT>FLASH
PROVIDE( _end = _ebss);
PROVIDE( end = . );
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
{
PROVIDE( _heap_end = . );
. = ALIGN(4);
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
} >RAM
}
|
||||
30
tools/makeboards.py
Normal file → Executable file
30
tools/makeboards.py
Normal file → Executable file
|
|
@ -77,9 +77,8 @@ board_list = {
|
|||
'pnums': {
|
||||
'CH32V203RB': {'name': 'CH32V203RB EVT', 'maximum_size': 131072, 'maximum_data_size': 65536, 'mcu': 'QingKe-V4C', 'chip': 'CH32V203'},
|
||||
'CH32V203G8': {'name': 'CH32V203G8 EVT', 'maximum_size': 65536, 'maximum_data_size': 20480, 'mcu': 'QingKe-V4B', 'chip': 'CH32V203'},
|
||||
'CH32V203G6': {'name': 'CH32V203G6 EVT', 'maximum_size': 32768, 'maximum_data_size': 10240, 'mcu': 'QingKe-V4B', 'chip': 'CH32V203'},
|
||||
'CH32V203C8': {'name': 'CH32V203C8', 'maximum_size': 65536, 'maximum_data_size': 20480, 'mcu': 'QingKe-V4B', 'chip': 'CH32V203'},
|
||||
'CH32V203C6': {'name': 'CH32V203C6', 'maximum_size': 32768, 'maximum_data_size': 10240, 'mcu': 'QingKe-V4B', 'chip': 'CH32V203'},
|
||||
'CH32V203C6': {'name': 'CH32V203C6', 'maximum_size': 32768, 'maximum_data_size': 20480, 'mcu': 'QingKe-V4B', 'chip': 'CH32V203'},
|
||||
}
|
||||
},
|
||||
'CH32V30x': {
|
||||
|
|
@ -181,19 +180,10 @@ def build_upload(series, values):
|
|||
print("# Upload menu")
|
||||
name = values["name"]
|
||||
menu = f'{name}.menu.upload_method'
|
||||
|
||||
menu_swd = f'{menu}.swdMethod'
|
||||
print(f'{menu_swd}=WCH-SWD')
|
||||
print(f'{menu_swd}.upload.protocol=')
|
||||
print(f'{menu_swd}.upload.options=')
|
||||
print(f'{menu_swd}.upload.tool=WCH_linkE')
|
||||
|
||||
menu_isp = f'{menu}.ispMethod'
|
||||
print(f'{menu_isp}=WCH-ISP')
|
||||
print(f'{menu_isp}.upload.protocol=')
|
||||
print(f'{menu_isp}.upload.options=')
|
||||
print(f'{menu_isp}.upload.tool=wchisp')
|
||||
|
||||
print(f'{menu}.swdMethod=WCH-SWD')
|
||||
print(f'{menu}.swdMethod.upload.protocol=')
|
||||
print(f'{menu}.swdMethod.upload.options=')
|
||||
print(f'{menu}.swdMethod.upload.tool=WCH_linkE')
|
||||
print()
|
||||
|
||||
|
||||
|
|
@ -238,20 +228,20 @@ def build_clock(series, values):
|
|||
for hsi in values['hsi']:
|
||||
if hsi == 0:
|
||||
print(f'{menu}.HSI=HSI Internal')
|
||||
print(f'{menu}.HSI.build.flags.clock=-DSYSCLK_FREQ_HSI=HSI_VALUE -DF_CPU=HSI_VALUE')
|
||||
print(f'{menu}.HSI.build.flags.clock=-DSYSCLK_FREQ_HSI=HSI_VALUE')
|
||||
elif hsi == 'HSI_LP':
|
||||
print(f'{menu}.HSI_LP=HSI_LP Internal')
|
||||
print(f'{menu}.HSI_LP.build.flags.clock=-DSYSCLK_FREQ_HSI_LP=HSI_LP_VALUE -DF_CPU=HSI_LP_VALUE')
|
||||
print(f'{menu}.HSI_LP.build.flags.clock=-DSYSCLK_FREQ_HSI_LP=HSI_LP_VALUE')
|
||||
else:
|
||||
print(f'{menu}.{hsi}MHz_HSI={hsi}MHz Internal')
|
||||
print(f'{menu}.{hsi}MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_{hsi}MHz_HSI={hsi}000000 -DF_CPU={hsi}000000')
|
||||
print(f'{menu}.{hsi}MHz_HSI.build.flags.clock=-DSYSCLK_FREQ_{hsi}MHz_HSI={hsi}000000')
|
||||
for hse in values['hse']:
|
||||
if hse == 0:
|
||||
print(f'{menu}.HSE=HSE External')
|
||||
print(f'{menu}.HSE.build.flags.clock=-DSYSCLK_FREQ_HSE=HSE_VALUE -DF_CPU=HSE_VALUE')
|
||||
print(f'{menu}.HSE.build.flags.clock=-DSYSCLK_FREQ_HSE=HSE_VALUE')
|
||||
else:
|
||||
print(f'{menu}.{hse}MHz_HSE={hse}MHz External')
|
||||
print(f'{menu}.{hse}MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_{hse}MHz_HSE={hse}000000 -DF_CPU={hse}000000')
|
||||
print(f'{menu}.{hse}MHz_HSE.build.flags.clock=-DSYSCLK_FREQ_{hse}MHz_HSE={hse}000000')
|
||||
print()
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,30 +0,0 @@
|
|||
# v3.21 implemented semantic changes regarding $<TARGET_OBJECTS:...>
|
||||
# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects
|
||||
cmake_minimum_required(VERSION 3.21)
|
||||
|
||||
add_library(variant INTERFACE)
|
||||
add_library(variant_usage INTERFACE)
|
||||
|
||||
target_include_directories(variant_usage INTERFACE
|
||||
.
|
||||
)
|
||||
|
||||
|
||||
target_link_libraries(variant_usage INTERFACE
|
||||
base_config
|
||||
)
|
||||
|
||||
target_link_libraries(variant INTERFACE variant_usage)
|
||||
|
||||
|
||||
|
||||
add_library(variant_bin STATIC EXCLUDE_FROM_ALL
|
||||
PeripheralPins.c
|
||||
variant_CH32V203G6.cpp
|
||||
)
|
||||
target_link_libraries(variant_bin PUBLIC variant_usage)
|
||||
|
||||
target_link_libraries(variant INTERFACE
|
||||
variant_bin
|
||||
)
|
||||
|
||||
|
|
@ -1,215 +0,0 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by WCH under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include "Arduino.h"
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
/* =====
|
||||
* Notes:
|
||||
* - The pins mentioned Px_y_ALTz are alternative possibilities which use other
|
||||
* HW peripheral instances. You can use them the same way as any other "normal"
|
||||
* pin (i.e. analogWrite(PA7_ALT1, 128);).
|
||||
*
|
||||
* - Commented lines are alternative possibilities which are not used per default.
|
||||
* If you change them, you will have to know what you do
|
||||
* =====
|
||||
*/
|
||||
|
||||
//*** ADC ***
|
||||
#ifdef ADC_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_ADC[] = {
|
||||
{PA_0, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 0)}, // ADC1_IN0
|
||||
{PA_0_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 0)}, // ADC2_IN0
|
||||
{PA_1, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 1)}, // ADC1_IN1
|
||||
{PA_1_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 1)}, // ADC2_IN1
|
||||
{PA_2, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 2)}, // ADC1_IN2
|
||||
{PA_2_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 2)}, // ADC2_IN2
|
||||
{PA_3, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 3)}, // ADC1_IN3
|
||||
{PA_3_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 3)}, // ADC2_IN3
|
||||
{PA_4, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 4)}, // ADC1_IN4
|
||||
{PA_4_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 4)}, // ADC2_IN4
|
||||
{PA_5, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 5)}, // ADC1_IN5
|
||||
{PA_5_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 5)}, // ADC2_IN5
|
||||
{PA_6, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 6)}, // ADC1_IN6
|
||||
{PA_6_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 6)}, // ADC2_IN6
|
||||
{PA_7, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 7)}, // ADC1_IN7
|
||||
{PA_7_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 7)}, // ADC2_IN7
|
||||
{PB_0, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 8)}, // ADC1_IN8
|
||||
{PB_0_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 8)}, // ADC2_IN8
|
||||
{PB_1, ADC1, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 9)}, // ADC1_IN9
|
||||
{PB_1_ALT1, ADC2, CH_PIN_DATA_EXT(CH_MODE_INPUT, CH_CNF_INPUT_ANALOG, 0, AFIO_NONE, 9)}, // ADC2_IN9
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
//*** No DAC ***
|
||||
|
||||
|
||||
|
||||
//*** I2C ***
|
||||
#ifdef I2C_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_I2C_SDA[] = {
|
||||
{PB_7, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_NONE)},
|
||||
{PB_9, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_Remap_I2C1_ENABLE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef I2C_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_I2C_SCL[] = {
|
||||
{PB_6, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_NONE)},
|
||||
{PB_8, I2C1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFOD, NOPULL, AFIO_Remap_I2C1_ENABLE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
//*** TIM ***
|
||||
#ifdef TIM_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_TIM[] = {
|
||||
{PA_0, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 1)}, // TIM2_CH1
|
||||
{PA_1, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 2)}, // TIM2_CH2
|
||||
{PA_2, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 3)}, // TIM2_CH3
|
||||
{PA_3, TIM2, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM2_DISABLE, 4)}, // TIM2_CH4
|
||||
|
||||
{PA_6, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 1)}, // TIM3_CH1
|
||||
{PA_7, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 2)}, // TIM3_CH2
|
||||
{PB_0, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 3)}, // TIM3_CH3
|
||||
{PB_1, TIM3, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM3_DISABLE, 4)}, // TIM3_CH4
|
||||
|
||||
{PB_6, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 1)}, // TIM4_CH1
|
||||
{PB_7, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 2)}, // TIM4_CH2
|
||||
{PB_8, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 3)}, // TIM4_CH3
|
||||
{PB_9, TIM4, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM4_DISABLE, 4)}, // TIM4_CH4
|
||||
|
||||
{PA_8, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1
|
||||
{PA_9, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2
|
||||
{PA_10, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3
|
||||
{PA_11, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 4)}, // TIM1_CH4
|
||||
|
||||
{PB_13, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 1)}, // TIM1_CH1N
|
||||
{PB_14, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 2)}, // TIM1_CH2N
|
||||
{PA_15, TIM1, CH_PIN_DATA_EXT(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, NOPULL, AFIO_Remap_TIM1_DISABLE, 3)}, // TIM1_CH3N
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
//*** UART ***
|
||||
#ifdef UART_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_UART_TX[] = {
|
||||
{PA_9, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{PB_6, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_Remap_USART1_ENABLE)},
|
||||
{PA_2, USART2, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{PB_10,USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{PC_10,USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_FullRemap_USART3_ENABLE)},
|
||||
{PB_0, UART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{PA_5, UART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_FullRemap_USART4_ENABLE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef UART_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_UART_RX[] = {
|
||||
{PA_10, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
|
||||
{PB_7, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_Remap_USART1_ENABLE)},
|
||||
{PA_3, USART2, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
|
||||
{PB_11, USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
|
||||
{PC_11, USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_FullRemap_USART3_ENABLE)},
|
||||
{PB_1, UART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
|
||||
{PB_5, UART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_FullRemap_USART4_ENABLE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef UART_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_UART_RTS[] = {
|
||||
{PA_12, USART1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{PA_1, USART2, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{PB_14, USART3, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{PB_4, UART4, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef UART_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_UART_CTS[] = {
|
||||
{PA_11, USART1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
|
||||
{PA_0, USART2, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
|
||||
{PB_13, USART3, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
|
||||
{PB_3, UART4, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_PUPD, PULLUP, AFIO_NONE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
//*** SPI ***
|
||||
#ifdef SPI_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PA_7, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef SPI_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_SPI_MISO[] = {
|
||||
{PA_6, SPI1, CH_PIN_DATA(CH_MODE_INPUT, CH_CNF_INPUT_FLOAT, 0, AFIO_NONE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef SPI_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PA_5, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef SPI_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PA_4, SPI1, CH_PIN_DATA(CH_MODE_OUTPUT_50MHz, CH_CNF_OUTPUT_AFPP, 0, AFIO_NONE)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
//*** CAN ***
|
||||
#ifdef CAN_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_CAN_RD[] = {
|
||||
{PA_11, CAN1, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)},
|
||||
{PB_8, CAN1, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_CAN1_2)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CAN_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_CAN_TD[] = {
|
||||
{PA_12, CAN1, CH_PIN_DATA(CH_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE)},
|
||||
{PB_9, CAN1, CH_PIN_DATA(CH_MODE_AF_PP, GPIO_NOPULL, AFIO_CAN1_2)},
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
//*** No ETHERNET ***
|
||||
|
||||
|
||||
|
||||
//*** USB ***
|
||||
#ifdef USB_MODULE_ENABLED
|
||||
WEAK const PinMap PinMap_USB[] = {
|
||||
{PA_11, USB, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DM
|
||||
{PA_12, USB, CH_PIN_DATA(CH_MODE_INPUT, GPIO_NOPULL, AFIO_NONE)}, // USB_DP
|
||||
{NC, NP, 0}
|
||||
};
|
||||
#endif
|
||||
|
||||
//*** No SD ***
|
||||
|
||||
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
/* Alternate pin name */
|
||||
PA_0_ALT1 = PA_0 | ALT1,
|
||||
PA_1_ALT1 = PA_1 | ALT1,
|
||||
PA_2_ALT1 = PA_2 | ALT1,
|
||||
PA_3_ALT1 = PA_3 | ALT1,
|
||||
PA_4_ALT1 = PA_4 | ALT1,
|
||||
PA_5_ALT1 = PA_5 | ALT1,
|
||||
PA_6_ALT1 = PA_6 | ALT1,
|
||||
PA_7_ALT1 = PA_7 | ALT1,
|
||||
PA_8_ALT1 = PA_8 | ALT1,
|
||||
PA_9_ALT1 = PA_9 | ALT1,
|
||||
PA_10_ALT1 = PA_10 | ALT1,
|
||||
PA_11_ALT1 = PA_11 | ALT1,
|
||||
PA_15_ALT1 = PA_15 | ALT1,
|
||||
PB_0_ALT1 = PB_0 | ALT1,
|
||||
PB_0_ALT2 = PB_0 | ALT2,
|
||||
PB_1_ALT1 = PB_1 | ALT1,
|
||||
PB_1_ALT2 = PB_1 | ALT2,
|
||||
PB_3_ALT1 = PB_3 | ALT1,
|
||||
PB_10_ALT1 = PB_10 | ALT1,
|
||||
PB_11_ALT1 = PB_11 | ALT1,
|
||||
|
||||
/* SYS_WKUP */
|
||||
#ifdef PWR_WAKEUP_PIN1
|
||||
SYS_WKUP1 = PA_0,
|
||||
#endif
|
||||
#ifdef PWR_WAKEUP_PIN2
|
||||
SYS_WKUP2 = NC,
|
||||
#endif
|
||||
#ifdef PWR_WAKEUP_PIN3
|
||||
SYS_WKUP3 = NC,
|
||||
#endif
|
||||
#ifdef PWR_WAKEUP_PIN4
|
||||
SYS_WKUP4 = NC,
|
||||
#endif
|
||||
#ifdef PWR_WAKEUP_PIN5
|
||||
SYS_WKUP5 = NC,
|
||||
#endif
|
||||
#ifdef PWR_WAKEUP_PIN6
|
||||
SYS_WKUP6 = NC,
|
||||
#endif
|
||||
#ifdef PWR_WAKEUP_PIN7
|
||||
SYS_WKUP7 = NC,
|
||||
#endif
|
||||
#ifdef PWR_WAKEUP_PIN8
|
||||
SYS_WKUP8 = NC,
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifdef USBCON
|
||||
USB_DM = PA_11,
|
||||
USB_DP = PA_12,
|
||||
#endif
|
||||
|
|
@ -1,12 +0,0 @@
|
|||
# This file help to add generic board entry.
|
||||
|
||||
|
||||
|
||||
# CH32V203G6
|
||||
CH32V20x_EVT.menu.pnum.CH32V203G6=CH32V203G6 EVT
|
||||
CH32V20x_EVT.menu.pnum.CH32V203G6.upload.maximum_size=32768
|
||||
CH32V20x_EVT.menu.pnum.CH32V203G6.upload.maximum_data_size=10240
|
||||
CH32V20x_EVT.menu.pnum.CH32V203G6.build.board=CH32V203G6
|
||||
CH32V20x_EVT.menu.pnum.CH32V203G6.build.product_line=CH32V203x6
|
||||
CH32V20x_EVT.menu.pnum.CH32V203G6.build.variant=CH32V20x/CH32V203G6
|
||||
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/**
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by WCH under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#include "pins_arduino.h"
|
||||
|
||||
|
||||
|
||||
|
||||
// Digital PinName array
|
||||
const PinName digitalPin[] = {
|
||||
PA_0, // D0/A0
|
||||
PA_1, // D1/A1
|
||||
PA_2, // D2/A2
|
||||
PA_3, // D3/A3
|
||||
PA_4, // D4/A4
|
||||
PA_5, // D5/A5
|
||||
PA_6, // D6/A6
|
||||
PA_7, // D7/A7
|
||||
PA_8, // D8
|
||||
PA_9, // D9
|
||||
PA_10, // D10
|
||||
PA_11, // D11
|
||||
PA_12, // D12
|
||||
PA_13, // D13
|
||||
PA_14, // D14
|
||||
PA_15, // D15
|
||||
PB_0, // D16/A8
|
||||
PB_1, // D17/A9
|
||||
PB_2, // D18
|
||||
PB_3, // D19
|
||||
PB_4, // D20
|
||||
PB_5, // D21
|
||||
PB_6, // D22
|
||||
PB_7, // D23
|
||||
PB_8, // D24
|
||||
};
|
||||
|
||||
// Analog (Ax) pin number array
|
||||
const uint32_t analogInputPin[] = {
|
||||
0, // A0, PA0
|
||||
1, // A1, PA1
|
||||
2, // A2, PA2
|
||||
3, // A3, PA3
|
||||
4, // A4, PA4
|
||||
5, // A5, PA5
|
||||
6, // A6, PA6
|
||||
7, // A7, PA7
|
||||
16, // A8, PB0
|
||||
17 // A9, PB1
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,172 +0,0 @@
|
|||
/*
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software component is licensed by WCH under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
/* ENABLE Peripherals */
|
||||
#define ADC_MODULE_ENABLED
|
||||
#define UART_MODULE_ENABLED
|
||||
#define SPI_MODULE_ENABLED
|
||||
#define I2C_MODULE_ENABLED
|
||||
#define TIM_MODULE_ENABLED
|
||||
|
||||
/* CH32V203G6 Pins */
|
||||
#define PA0 PIN_A0
|
||||
#define PA1 PIN_A1
|
||||
#define PA2 PIN_A2
|
||||
#define PA3 PIN_A3
|
||||
#define PA4 PIN_A4
|
||||
#define PA5 PIN_A5
|
||||
#define PA6 PIN_A6
|
||||
#define PA7 PIN_A7
|
||||
#define PA8 8
|
||||
#define PA9 9
|
||||
#define PA10 10
|
||||
#define PA11 11
|
||||
#define PA12 12
|
||||
#define PA13 13
|
||||
#define PA14 14
|
||||
#define PA15 15
|
||||
#define PB0 PIN_A8
|
||||
#define PB1 PIN_A9
|
||||
#define PB2 18
|
||||
#define PB3 19
|
||||
#define PB4 20
|
||||
#define PB5 21
|
||||
#define PB6 22
|
||||
#define PB7 23
|
||||
#define PB8 24
|
||||
|
||||
// Alternate pins number
|
||||
#define PA0_ALT1 (PA0 | ALT1)
|
||||
#define PA1_ALT1 (PA1 | ALT1)
|
||||
#define PA2_ALT1 (PA2 | ALT1)
|
||||
#define PA3_ALT1 (PA3 | ALT1)
|
||||
#define PA4_ALT1 (PA4 | ALT1)
|
||||
#define PA5_ALT1 (PA5 | ALT1)
|
||||
#define PA6_ALT1 (PA6 | ALT1)
|
||||
#define PA7_ALT1 (PA7 | ALT1)
|
||||
#define PA8_ALT1 (PA8 | ALT1)
|
||||
#define PA9_ALT1 (PA9 | ALT1)
|
||||
#define PA10_ALT1 (PA10 | ALT1)
|
||||
#define PA11_ALT1 (PA11 | ALT1)
|
||||
#define PA15_ALT1 (PA15 | ALT1)
|
||||
#define PB0_ALT1 (PB0 | ALT1)
|
||||
#define PB0_ALT2 (PB0 | ALT2)
|
||||
#define PB1_ALT1 (PB1 | ALT1)
|
||||
#define PB1_ALT2 (PB1 | ALT2)
|
||||
#define PB3_ALT1 (PB3 | ALT1)
|
||||
#define PB10_ALT1 (PB10 | ALT1)
|
||||
#define PB11_ALT1 (PB11 | ALT1)
|
||||
|
||||
#define NUM_DIGITAL_PINS 24
|
||||
#define NUM_ANALOG_INPUTS 10
|
||||
// #define ADC_CTLR_ADCAL
|
||||
#define ADC_RESOLUTION 12
|
||||
|
||||
|
||||
// On-board LED pin number
|
||||
#ifndef LED_BUILTIN
|
||||
#define LED_BUILTIN PNUM_NOT_DEFINED
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// On-board user button
|
||||
#ifndef USER_BTN
|
||||
#define USER_BTN PNUM_NOT_DEFINED
|
||||
#endif
|
||||
|
||||
// SPI definitions
|
||||
#ifndef PIN_SPI_SS
|
||||
#define PIN_SPI_SS PA4
|
||||
#endif
|
||||
#ifndef PIN_SPI_SS1
|
||||
#define PIN_SPI_SS1 PA15
|
||||
#endif
|
||||
#ifndef PIN_SPI_SS2
|
||||
#define PIN_SPI_SS2 PNUM_NOT_DEFINED
|
||||
#endif
|
||||
#ifndef PIN_SPI_SS3
|
||||
#define PIN_SPI_SS3 PNUM_NOT_DEFINED
|
||||
#endif
|
||||
|
||||
#ifndef PIN_SPI_MOSI
|
||||
#define PIN_SPI_MOSI PA7
|
||||
#endif
|
||||
#ifndef PIN_SPI_MISO
|
||||
#define PIN_SPI_MISO PA6
|
||||
#endif
|
||||
#ifndef PIN_SPI_SCK
|
||||
#define PIN_SPI_SCK PA5
|
||||
#endif
|
||||
|
||||
// I2C definitions
|
||||
#ifndef PIN_WIRE_SDA
|
||||
#define PIN_WIRE_SDA PB7
|
||||
#endif
|
||||
#ifndef PIN_WIRE_SCL
|
||||
#define PIN_WIRE_SCL PB6
|
||||
#endif
|
||||
|
||||
// Timer Definitions
|
||||
// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
|
||||
#ifndef TIMER_TONE
|
||||
#define TIMER_TONE TIM3
|
||||
#endif
|
||||
#ifndef TIMER_SERVO
|
||||
#define TIMER_SERVO TIM2
|
||||
#endif
|
||||
|
||||
|
||||
// UART Definitions
|
||||
#ifndef SERIAL_UART_INSTANCE
|
||||
#define SERIAL_UART_INSTANCE 1
|
||||
#endif
|
||||
// Default pin used for generic 'Serial' instance
|
||||
// Mandatory for Firmata
|
||||
#ifndef PIN_SERIAL_RX
|
||||
#define PIN_SERIAL_RX PA10
|
||||
#endif
|
||||
#ifndef PIN_SERIAL_TX
|
||||
#define PIN_SERIAL_TX PA9
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Arduino objects - C++ only
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
// These serial port names are intended to allow libraries and architecture-neutral
|
||||
// sketches to automatically default to the correct port name for a particular type
|
||||
// of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
|
||||
// the first hardware serial port whose RX/TX pins are not dedicated to another use.
|
||||
//
|
||||
// SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
|
||||
//
|
||||
// SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
|
||||
//
|
||||
// SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
|
||||
//
|
||||
// SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
|
||||
//
|
||||
// SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
|
||||
// pins are NOT connected to anything by default.
|
||||
#ifndef SERIAL_PORT_MONITOR
|
||||
#define SERIAL_PORT_MONITOR Serial
|
||||
#endif
|
||||
#ifndef SERIAL_PORT_HARDWARE
|
||||
#define SERIAL_PORT_HARDWARE Serial
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in a new issue