diff --git a/_drafts/2022-12-20-draft.md b/_drafts/2022-12-20-draft.md index e41a34c08..3f2993662 100644 --- a/_drafts/2022-12-20-draft.md +++ b/_drafts/2022-12-20-draft.md @@ -62,7 +62,7 @@ text - [site](url). ## RISC-V: The background, the benefits, and the future -[![RISC-V: The background, the benefits, and the future](../assets/20221220/20221220-name.jpg)](https://www.eeworldonline.com/risc-v-background-benefits-and-future-faq/) +[![RISC-V: The background, the benefits, and the future](../assets/20221220/20221220r5.jpg)](https://www.eeworldonline.com/risc-v-background-benefits-and-future-faq/) US developers conceived the revolutionary instruction set architecture (ISA) known as RISC-V in 2010. Grounded in reduced instruction set computer (RISC) principles, it’s a common, open-source, and completely free ISA that can be used to develop software and hardware. These attributes are just part of what makes the architecture unique and attractive to developers and manufacturers.