3 commits

Author	SHA1	Message	Date
eightycc	1f3307ef72	Fix arm register unload area size.	2025-05-17 10:57:41 -07:00
eightycc	739b24212c	Fix crashing bug in PR #10325 for RISC-V builds.	2025-05-10 15:56:21 -07:00
Scott Shawcroft	2bec0562eb	Factor out register saves ... This fixes RISC-V ESP32 because it ignored registers on that architecture.	2025-05-08 16:12:10 -07:00