add help message to Kconfig for ulp

such that fsm and riscv ulps are no longer mutually exclusive at compile time

.gitlab/ci/common.yml

@@ -39,7 +39,7 @@ variables:
   GIT_FETCH_EXTRA_FLAGS: "--no-recurse-submodules --prune --prune-tags"
   # we're using .cache folder for caches
   GIT_CLEAN_FLAGS: -ffdx -e .cache/
-  LATEST_GIT_TAG: v5.3
+  LATEST_GIT_TAG: v5.3.1
 
   SUBMODULE_FETCH_TOOL: "tools/ci/ci_fetch_submodule.py"
   # by default we will fetch all submodules

components/bootloader_support/src/flash_encryption/flash_encrypt.c

@@ -16,11 +16,15 @@
 #include "esp_log.h"
 #include "hal/wdt_hal.h"
 
-#if SOC_KEY_MANAGER_SUPPORTED
-#include "hal/key_mgr_hal.h"
-#include "hal/mspi_timing_tuning_ll.h"
+#if SOC_KEY_MANAGER_FE_KEY_DEPLOY || CONFIG_IDF_TARGET_ESP32C5
+#if CONFIG_IDF_TARGET_ESP32C5
 #include "soc/keymng_reg.h"
-#endif
+#include "soc/pcr_reg.h"
+#else /* CONFIG_IDF_TARGET_ESP32C5 */
+#include "hal/key_mgr_ll.h"
+#include "hal/mspi_timing_tuning_ll.h"
+#endif /* !CONFIG_IDF_TARGET_ESP32C5 */
+#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
 
 #ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
 #include "soc/sensitive_reg.h"
@@ -217,18 +221,25 @@ static esp_err_t check_and_generate_encryption_keys(void)
         ESP_LOGI(TAG, "Using pre-loaded flash encryption key in efuse");
     }
 
-#if SOC_KEY_MANAGER_SUPPORTED
-#if CONFIG_IDF_TARGET_ESP32C5 && SOC_KEY_MANAGER_SUPPORTED
-    // TODO: [ESP32C5] IDF-8622 find a more proper place for these codes
-    REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+#if SOC_KEY_MANAGER_FE_KEY_DEPLOY || CONFIG_IDF_TARGET_ESP32C5
+#if CONFIG_IDF_TARGET_ESP32C5
+    REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 2);
     REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
     REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
-#endif
+#else /* CONFIG_IDF_TARGET_ESP32C5 */
+    // Enable and reset key manager
+    // To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
+    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
+    key_mgr_ll_enable_bus_clock(true);
+    key_mgr_ll_enable_peripheral_clock(true);
+    key_mgr_ll_reset_register();
+    while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
+    };
     // Force Key Manager to use eFuse key for XTS-AES operation
-    key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
+    key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
     _mspi_timing_ll_reset_mspi();
-#endif
-
+#endif /* !CONFIG_IDF_TARGET_ESP32C5 */
+#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
     return ESP_OK;
 }
 

components/esp_common/include/esp_idf_version.h

@@ -15,7 +15,7 @@ extern "C" {
 /** Minor version number (x.X.x) */
 #define ESP_IDF_VERSION_MINOR   3
 /** Patch version number (x.x.X) */
-#define ESP_IDF_VERSION_PATCH   0
+#define ESP_IDF_VERSION_PATCH   1
 
 /**
  * Macro to convert IDF version number into an integer

components/esp_hw_support/sleep_modes.c

@@ -168,7 +168,11 @@
 
 #if SOC_PM_SUPPORT_TOP_PD
 // IDF console uses 8 bits data mode without parity, so each char occupy 8(data)+1(start)+1(stop)=10bits
+#ifdef CONFIG_ESP_CONSOLE_UART_NONE
+#define UART_FLUSH_US_PER_CHAR              (0)
+#else
 #define UART_FLUSH_US_PER_CHAR              (10*1000*1000 / CONFIG_ESP_CONSOLE_UART_BAUDRATE)
+#endif
 #define CONCATENATE_HELPER(x, y)            (x##y)
 #define CONCATENATE(x, y)                   CONCATENATE_HELPER(x, y)
 #define CONSOLE_UART_DEV                    (&CONCATENATE(UART, CONFIG_ESP_CONSOLE_UART_NUM))

components/esp_lcd/rgb/esp_lcd_panel_rgb.c

@@ -154,7 +154,7 @@ static esp_err_t lcd_rgb_panel_alloc_frame_buffers(const esp_lcd_rgb_panel_confi
     if (rgb_panel->num_fbs > 0) {
         // fb_in_psram is only an option, if there's no PSRAM on board, we fallback to alloc from SRAM
         if (rgb_panel_config->flags.fb_in_psram) {
-#if CONFIG_SPIRAM_USE_MALLOC || CONFIG_SPIRAM_USE_CAPS_ALLOC
+#if CONFIG_SPIRAM
             if (esp_psram_is_initialized()) {
                 fb_in_psram = true;
             }

components/esp_psram/esp_psram.c

@@ -447,6 +447,15 @@ size_t esp_psram_get_size(void)
     return (size_t)available_size;
 }
 
+uint8_t* esp_psram_get_address(void)
+{
+    if (!s_psram_ctx.is_initialised) {
+        return NULL;
+    }
+
+    return s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start;
+}
+
 uint8_t esp_psram_io_get_cs_io(void)
 {
     return esp_psram_impl_get_cs_io();

components/esp_psram/include/esp_psram.h

@@ -41,6 +41,13 @@ bool esp_psram_is_initialized(void);
  */
 size_t esp_psram_get_size(void);
 
+/**
+ * @brief Get the memory mapped address of the attached PSRAM chip
+ *
+ * @return Pointer to the start of PSRAM memory, or NULL if PSRAM isn't successfully initialized
+ */
+uint8_t* esp_psram_get_address(void);
+
 #ifdef __cplusplus
 }
 #endif

components/esp_system/port/cpu_start.c

@@ -71,8 +71,8 @@
 #include "soc/hp_sys_clkrst_reg.h"
 #endif
 
-#if SOC_KEY_MANAGER_SUPPORTED
-#include "hal/key_mgr_hal.h"
+#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY
+#include "hal/key_mgr_ll.h"
 #endif
 
 #include "esp_private/rtc_clk.h"
@@ -309,13 +309,22 @@ static void start_other_core(void)
     }
 #endif
 
-#if SOC_KEY_MANAGER_SUPPORTED
     // The following operation makes the Key Manager to use eFuse key for ECDSA and XTS-AES operation by default
     // This is to keep the default behavior same as the other chips
     // If the Key Manager configuration is already locked then following operation does not have any effect
-    key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
-    key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
+#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY
+    // Enable key manager clock
+    // Using ll APIs which do not require critical section
+    _key_mgr_ll_enable_bus_clock(true);
+    _key_mgr_ll_enable_peripheral_clock(true);
+#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
+    key_mgr_ll_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
 #endif
+#if SOC_KEY_MANAGER_FE_KEY_DEPLOY
+    key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
+#endif
+#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY */
+
     ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
 
     bool cpus_up = false;

components/hal/ecdsa_hal.c

@@ -9,7 +9,11 @@
 #include "hal/ecdsa_hal.h"
 #include "hal/efuse_hal.h"
 
-#ifdef SOC_KEY_MANAGER_SUPPORTED
+#if CONFIG_IDF_TARGET_ESP32C5
+#include "soc/keymng_reg.h"
+#endif
+
+#ifdef SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
 #include "hal/key_mgr_hal.h"
 #endif
 
@@ -19,16 +23,21 @@
 static void configure_ecdsa_periph(ecdsa_hal_config_t *conf)
 {
 
-
     if (conf->use_km_key == 0) {
         efuse_hal_set_ecdsa_key(conf->efuse_key_blk);
-#if SOC_KEY_MANAGER_SUPPORTED
-        key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
+
+#if CONFIG_IDF_TARGET_ESP32C5
+        REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY, 1);
+#endif
+
+#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
+        // Force Key Manager to use eFuse key for XTS-AES operation
+        key_mgr_ll_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
 #endif
     }
 #if SOC_KEY_MANAGER_SUPPORTED
     else {
-        key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_OWN_KEY);
+        key_mgr_ll_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_OWN_KEY);
     }
 #endif
 

components/hal/esp32p4/include/hal/key_mgr_ll.h

@@ -10,9 +10,7 @@
  ******************************************************************************/
 
 #pragma once
-#include "soc/soc_caps.h"
 
-#if SOC_KEY_MANAGER_SUPPORTED
 #include <stdint.h>
 #include <stdbool.h>
 #include <string.h>
@@ -21,7 +19,6 @@
 #include "hal/key_mgr_types.h"
 #include "soc/keymng_reg.h"
 #include "soc/hp_sys_clkrst_struct.h"
-#include "soc/soc_caps.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -29,29 +26,32 @@ extern "C" {
 
 /**
  * @brief Enable the bus clock for Key Manager peripheral
- *
+ * Note: Please use key_mgr_ll_enable_bus_clock which requires the critical section
+ *       and do not use _key_mgr_ll_enable_bus_clock
  * @param true to enable, false to disable
  */
-static inline void key_mgr_ll_enable_bus_clock(bool enable)
+static inline void _key_mgr_ll_enable_bus_clock(bool enable)
 {
     HP_SYS_CLKRST.soc_clk_ctrl1.reg_key_manager_sys_clk_en = enable;
 }
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
-#define key_mgr_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; key_mgr_ll_enable_bus_clock(__VA_ARGS__)
+#define key_mgr_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_enable_bus_clock(__VA_ARGS__)
 
 /**
  * @brief Enable the peripheral clock for Key Manager
  *
+ * Note: Please use key_mgr_ll_enable_peripheral_clock which requires the critical section
+ *       and do not use _key_mgr_ll_enable_peripheral_clock
  * @param true to enable, false to disable
  */
-static inline void key_mgr_ll_enable_peripheral_clock(bool enable)
+static inline void _key_mgr_ll_enable_peripheral_clock(bool enable)
 {
     HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_km_clk_en = enable;
 }
 
-#define key_mgr_ll_enable_peripheral_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; key_mgr_ll_enable_bus_clock(__VA_ARGS__)
+#define key_mgr_ll_enable_peripheral_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_enable_peripheral_clock(__VA_ARGS__)
 
 /**
  * @brief Reset the Key Manager peripheral */
@@ -345,4 +345,3 @@ static inline uint32_t key_mgr_ll_get_date_info(void)
 #ifdef __cplusplus
 }
 #endif
-#endif

components/hal/esp32s2/include/hal/rtc_io_ll.h

@@ -68,6 +68,12 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
     } else if (func == RTCIO_LL_FUNC_DIGITAL) {
         CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
+        // If any other rtcio is set to rtc mux, then return early to leave the clock on.
+        for (int n = 0; n < SOC_RTCIO_PIN_COUNT; n++) {
+            if (GET_PERI_REG_MASK(rtc_io_desc[n].reg, rtc_io_desc[n].mux) != 0) {
+                return;
+            }
+        }
         SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
     }
 }

components/hal/esp32s3/include/hal/rtc_io_ll.h

@@ -75,6 +75,12 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
     } else if (func == RTCIO_LL_FUNC_DIGITAL) {
         CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
+        // If any other rtcio is set to rtc mux, then return early to leave the clock on.
+        for (int n = 0; n < SOC_RTCIO_PIN_COUNT; n++) {
+            if (GET_PERI_REG_MASK(rtc_io_desc[n].reg, rtc_io_desc[n].mux) != 0) {
+                return;
+            }
+        }
         SENS.sar_peri_clk_gate_conf.iomux_clk_en = 0;
         // USB Serial JTAG pad re-enable won't be done here (it requires both DM and DP pins not in rtc function)
         // Instead, USB_SERIAL_JTAG_USB_PAD_ENABLE needs to be guaranteed to be set in usb_serial_jtag driver

components/hal/include/hal/key_mgr_types.h

@@ -5,9 +5,6 @@
  */
 #pragma once
 
-#include "soc/soc_caps.h"
-
-#if SOC_KEY_MANAGER_SUPPORTED
 #include <stdbool.h>
 #include <stddef.h>
 #include <stdint.h>
@@ -24,7 +21,7 @@ extern "C" {
  */
 typedef enum {
     ESP_KEY_MGR_STATE_IDLE = 0, /* Key Manager is idle */
-    ESP_KEY_MGR_STATE_LOAD = 1,     /* Key Manager is ready to recieve input */
+    ESP_KEY_MGR_STATE_LOAD = 1,     /* Key Manager is ready to receive input */
     ESP_KEY_MGR_STATE_GAIN = 2,     /* Key Manager is ready to provide output */
     ESP_KEY_MGR_STATE_BUSY = 3,      /* Key Manager is busy */
 } esp_key_mgr_state_t;
@@ -114,5 +111,3 @@ typedef struct WORD_ALIGNED_ATTR PACKED_ATTR {
 #ifdef __cplusplus
 }
 #endif
-
-#endif

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1483,6 +1483,14 @@ config SOC_EFUSE_ECDSA_KEY
     bool
     default y
 
+config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
+    bool
+    default y
+
+config SOC_KEY_MANAGER_FE_KEY_DEPLOY
+    bool
+    default y
+
 config SOC_SECURE_BOOT_V2_RSA
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -582,6 +582,9 @@
 #define SOC_EFUSE_DIS_DOWNLOAD_MSPI 1
 #define SOC_EFUSE_ECDSA_KEY 1
 
+/*-------------------------- Key Manager CAPS----------------------------*/
+#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY    1 /*!< Key manager responsible to deploy ECDSA key */
+#define SOC_KEY_MANAGER_FE_KEY_DEPLOY       1 /*!< Key manager responsible to deploy Flash Encryption key */
 /*-------------------------- Secure Boot CAPS----------------------------*/
 #define SOC_SECURE_BOOT_V2_RSA              1
 #define SOC_SECURE_BOOT_V2_ECC              1
@@ -595,7 +598,6 @@
 #define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1
 #define SOC_FLASH_ENCRYPTION_XTS_AES_128    1
 #define SOC_FLASH_ENCRYPTION_XTS_AES_256    1
-
 /*-------------------------- MEMPROT CAPS ------------------------------------*/
 
 /*-------------------------- UART CAPS ---------------------------------------*/

components/ulp/CMakeLists.txt

@@ -41,7 +41,9 @@ if(CONFIG_ULP_COPROC_TYPE_FSM OR CONFIG_ULP_COPROC_TYPE_RISCV)
             "ulp_fsm/ulp.c"
             "ulp_fsm/ulp_macro.c")
 
-    elseif(CONFIG_ULP_COPROC_TYPE_RISCV)
+    endif()
+
+    if(CONFIG_ULP_COPROC_TYPE_RISCV)
         list(APPEND srcs
             "ulp_riscv/ulp_riscv.c"
             "ulp_riscv/ulp_riscv_lock.c"

components/ulp/Kconfig

@@ -8,23 +8,21 @@ menu "Ultra Low Power (ULP) Co-processor"
             Enable this feature if you plan to use the ULP Co-processor.
             Once this option is enabled, further ULP co-processor configuration will appear in the menu.
 
-    choice ULP_COPROC_TYPE
-        prompt "ULP Co-processor type"
-        depends on ULP_COPROC_ENABLED
-        default ULP_COPROC_TYPE_RISCV if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3)
+    config ULP_COPROC_TYPE_FSM
+        bool "Enable ULP FSM (Finite State Machine)"
+        depends on (SOC_ULP_FSM_SUPPORTED && ULP_COPROC_ENABLED)
         help
-            Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V.
-
-        config ULP_COPROC_TYPE_FSM
-            bool "ULP FSM (Finite State Machine)"
-            depends on SOC_ULP_FSM_SUPPORTED
-        config ULP_COPROC_TYPE_RISCV
-            bool "ULP RISC-V"
-            depends on SOC_RISCV_COPROC_SUPPORTED
-        config ULP_COPROC_TYPE_LP_CORE
-            bool "LP core RISC-V"
-            depends on SOC_LP_CORE_SUPPORTED
-    endchoice
+            Note: On devices with both ULP FSM and ULP RISC-V, both ULPs can be enabled simultaneously at compile-time, 
+            but may not be used simultaneously at run-time. 
+    config ULP_COPROC_TYPE_RISCV
+        bool "Enable ULP RISC-V"
+        depends on (SOC_RISCV_COPROC_SUPPORTED && ULP_COPROC_ENABLED)
+        help
+            Note: On devices with both ULP FSM and ULP RISC-V, both ULPs can be enabled simultaneously at compile-time, 
+            but may not be used simultaneously at run-time. 
+    config ULP_COPROC_TYPE_LP_CORE
+        bool "Enable LP core RISC-V"
+        depends on (SOC_LP_CORE_SUPPORTED && ULP_COPROC_ENABLED)
 
     config ULP_COPROC_RESERVE_MEM
         int

tools/cmake/version.cmake

@@ -1,5 +1,5 @@
 set(IDF_VERSION_MAJOR 5)
 set(IDF_VERSION_MINOR 3)
-set(IDF_VERSION_PATCH 0)
+set(IDF_VERSION_PATCH 1)
 
 set(ENV{IDF_VERSION} "${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}.${IDF_VERSION_PATCH}")