add help message to Kconfig for ulp

such that fsm and riscv ulps are no longer mutually exclusive at compile time

.gitmodules

@@ -89,7 +89,7 @@
 
 [submodule "components/bt/host/nimble/nimble"]
 	path = components/bt/host/nimble/nimble
-	url = ../../espressif/esp-nimble.git
+	url = ../../adafruit/esp-nimble.git
 
 [submodule "components/esp_wifi/lib"]
 	path = components/esp_wifi/lib

components/bt/host/nimble/nimble

@@ -1 +1 @@
-Subproject commit a2acac3e14bb7810783ac5089ccf8229a2dd2f70
+Subproject commit 81492a09c52ed308143779b7d1d20751276c008a

components/esp_hw_support/sleep_modes.c

@@ -147,7 +147,11 @@
 
 #if SOC_PM_SUPPORT_TOP_PD
 // IDF console uses 8 bits data mode without parity, so each char occupy 8(data)+1(start)+1(stop)=10bits
+#ifdef CONFIG_ESP_CONSOLE_UART_NONE
+#define UART_FLUSH_US_PER_CHAR              (0)
+#else
 #define UART_FLUSH_US_PER_CHAR              (10*1000*1000 / CONFIG_ESP_CONSOLE_UART_BAUDRATE)
+#endif
 #define CONCATENATE_HELPER(x, y)            (x##y)
 #define CONCATENATE(x, y)                   CONCATENATE_HELPER(x, y)
 #define CONSOLE_UART_DEV                    (&CONCATENATE(UART, CONFIG_ESP_CONSOLE_UART_NUM))

components/esp_lcd/src/esp_lcd_panel_rgb.c

@@ -142,7 +142,7 @@ static esp_err_t lcd_rgb_panel_alloc_frame_buffers(const esp_lcd_rgb_panel_confi
     if (rgb_panel->num_fbs > 0) {
         // fb_in_psram is only an option, if there's no PSRAM on board, we fallback to alloc from SRAM
         if (rgb_panel_config->flags.fb_in_psram) {
-#if CONFIG_SPIRAM_USE_MALLOC || CONFIG_SPIRAM_USE_CAPS_ALLOC
+#if CONFIG_SPIRAM
             if (esp_psram_is_initialized()) {
                 fb_in_psram = true;
             }
@@ -178,9 +178,11 @@ static esp_err_t lcd_rgb_panel_alloc_frame_buffers(const esp_lcd_rgb_panel_confi
     return ESP_OK;
 }
 
-static esp_err_t lcd_rgb_panel_destory(esp_rgb_panel_t *rgb_panel)
+static esp_err_t lcd_rgb_panel_destroy(esp_rgb_panel_t *rgb_panel)
 {
-    lcd_ll_enable_clock(rgb_panel->hal.dev, false);
+    if (rgb_panel->hal.dev) {
+        lcd_ll_enable_clock(rgb_panel->hal.dev, false);
+    }
     if (rgb_panel->panel_id >= 0) {
         PERIPH_RCC_RELEASE_ATOMIC(lcd_periph_signals.panels[rgb_panel->panel_id].module, ref_count) {
             if (ref_count == 0) {
@@ -361,7 +363,7 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf
 
 err:
     if (rgb_panel) {
-        lcd_rgb_panel_destory(rgb_panel);
+        lcd_rgb_panel_destroy(rgb_panel);
     }
     return ret;
 }
@@ -498,7 +500,7 @@ static esp_err_t rgb_panel_del(esp_lcd_panel_t *panel)
 {
     esp_rgb_panel_t *rgb_panel = __containerof(panel, esp_rgb_panel_t, base);
     int panel_id = rgb_panel->panel_id;
-    ESP_RETURN_ON_ERROR(lcd_rgb_panel_destory(rgb_panel), TAG, "destroy rgb panel(%d) failed", panel_id);
+    ESP_RETURN_ON_ERROR(lcd_rgb_panel_destroy(rgb_panel), TAG, "destroy rgb panel(%d) failed", panel_id);
     ESP_LOGD(TAG, "del rgb panel(%d)", panel_id);
     return ESP_OK;
 }

components/esp_psram/esp_psram.c

@@ -381,6 +381,15 @@ size_t esp_psram_get_size(void)
     return (size_t)available_size;
 }
 
+uint8_t* esp_psram_get_address(void)
+{
+    if (!s_psram_ctx.is_initialised) {
+        return NULL;
+    }
+
+    return s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start;
+}
+
 uint8_t esp_psram_io_get_cs_io(void)
 {
     return esp_psram_impl_get_cs_io();

components/esp_psram/include/esp_psram.h

@@ -41,6 +41,13 @@ bool esp_psram_is_initialized(void);
  */
 size_t esp_psram_get_size(void);
 
+/**
+ * @brief Get the memory mapped address of the attached PSRAM chip
+ *
+ * @return Pointer to the start of PSRAM memory, or NULL if PSRAM isn't successfully initialized
+ */
+uint8_t* esp_psram_get_address(void);
+
 #ifdef __cplusplus
 }
 #endif

components/esp_system/port/soc/esp32/Kconfig.system

@@ -66,4 +66,4 @@ config ESP32_DISABLE_BASIC_ROM_CONSOLE
 config ESP32_ECO3_CACHE_LOCK_FIX
     bool
     default y
-    depends on !FREERTOS_UNICORE && SPIRAM
+    depends on !FREERTOS_UNICORE

components/hal/esp32s2/include/hal/rtc_io_ll.h

@@ -68,6 +68,12 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
     } else if (func == RTCIO_LL_FUNC_DIGITAL) {
         CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
+        // If any other rtcio is set to rtc mux, then return early to leave the clock on.
+        for (int n = 0; n < SOC_RTCIO_PIN_COUNT; n++) {
+            if (GET_PERI_REG_MASK(rtc_io_desc[n].reg, rtc_io_desc[n].mux) != 0) {
+                return;
+            }
+        }
         SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
     }
 }

components/hal/esp32s3/include/hal/rtc_io_ll.h

@@ -74,6 +74,12 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
     } else if (func == RTCIO_LL_FUNC_DIGITAL) {
         CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
+        // If any other rtcio is set to rtc mux, then return early to leave the clock on.
+        for (int n = 0; n < SOC_RTCIO_PIN_COUNT; n++) {
+            if (GET_PERI_REG_MASK(rtc_io_desc[n].reg, rtc_io_desc[n].mux) != 0) {
+                return;
+            }
+        }
         SENS.sar_peri_clk_gate_conf.iomux_clk_en = 0;
         // USB Serial JTAG pad re-enable won't be done here (it requires both DM and DP pins not in rtc function)
         // Instead, USB_SERIAL_JTAG_USB_PAD_ENABLE needs to be guaranteed to be set in usb_serial_jtag driver

components/ulp/CMakeLists.txt

@@ -42,7 +42,9 @@ if(CONFIG_ULP_COPROC_TYPE_FSM OR CONFIG_ULP_COPROC_TYPE_RISCV)
             "ulp_fsm/ulp.c"
             "ulp_fsm/ulp_macro.c")
 
-    elseif(CONFIG_ULP_COPROC_TYPE_RISCV)
+    endif()
+
+    if(CONFIG_ULP_COPROC_TYPE_RISCV)
         list(APPEND srcs
             "ulp_riscv/ulp_riscv.c"
             "ulp_riscv/ulp_riscv_lock.c"

components/ulp/Kconfig

@@ -8,23 +8,21 @@ menu "Ultra Low Power (ULP) Co-processor"
             Enable this feature if you plan to use the ULP Co-processor.
             Once this option is enabled, further ULP co-processor configuration will appear in the menu.
 
-    choice ULP_COPROC_TYPE
-        prompt "ULP Co-processor type"
-        depends on ULP_COPROC_ENABLED
-        default ULP_COPROC_TYPE_RISCV if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3)
+    config ULP_COPROC_TYPE_FSM
+        bool "Enable ULP FSM (Finite State Machine)"
+        depends on (SOC_ULP_FSM_SUPPORTED && ULP_COPROC_ENABLED)
         help
-            Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V.
-
-        config ULP_COPROC_TYPE_FSM
-            bool "ULP FSM (Finite State Machine)"
-            depends on SOC_ULP_FSM_SUPPORTED
-        config ULP_COPROC_TYPE_RISCV
-            bool "ULP RISC-V"
-            depends on SOC_RISCV_COPROC_SUPPORTED
-        config ULP_COPROC_TYPE_LP_CORE
-            bool "LP core RISC-V"
-            depends on SOC_LP_CORE_SUPPORTED
-    endchoice
+            Note: On devices with both ULP FSM and ULP RISC-V, both ULPs can be enabled simultaneously at compile-time, 
+            but may not be used simultaneously at run-time. 
+    config ULP_COPROC_TYPE_RISCV
+        bool "Enable ULP RISC-V"
+        depends on (SOC_RISCV_COPROC_SUPPORTED && ULP_COPROC_ENABLED)
+        help
+            Note: On devices with both ULP FSM and ULP RISC-V, both ULPs can be enabled simultaneously at compile-time, 
+            but may not be used simultaneously at run-time. 
+    config ULP_COPROC_TYPE_LP_CORE
+        bool "Enable LP core RISC-V"
+        depends on (SOC_LP_CORE_SUPPORTED && ULP_COPROC_ENABLED)
 
     config ULP_COPROC_RESERVE_MEM
         int