add help message to Kconfig for ulp

such that fsm and riscv ulps are no longer mutually exclusive at compile time

.gitlab/ci/common.yml

@@ -39,7 +39,7 @@ variables:
   GIT_FETCH_EXTRA_FLAGS: "--no-recurse-submodules --prune --prune-tags"
   # we're using .cache folder for caches
   GIT_CLEAN_FLAGS: -ffdx -e .cache/
-  LATEST_GIT_TAG: v5.3.1
+  LATEST_GIT_TAG: v5.3.2
 
   SUBMODULE_FETCH_TOOL: "tools/ci/ci_fetch_submodule.py"
   # by default we will fetch all submodules

components/esp_common/include/esp_idf_version.h

@@ -15,7 +15,7 @@ extern "C" {
 /** Minor version number (x.X.x) */
 #define ESP_IDF_VERSION_MINOR   3
 /** Patch version number (x.x.X) */
-#define ESP_IDF_VERSION_PATCH   1
+#define ESP_IDF_VERSION_PATCH   2
 
 /**
  * Macro to convert IDF version number into an integer

components/esp_hw_support/sleep_modes.c

@@ -168,7 +168,11 @@
 
 #if SOC_PM_SUPPORT_TOP_PD
 // IDF console uses 8 bits data mode without parity, so each char occupy 8(data)+1(start)+1(stop)=10bits
+#ifdef CONFIG_ESP_CONSOLE_UART_NONE
+#define UART_FLUSH_US_PER_CHAR              (0)
+#else
 #define UART_FLUSH_US_PER_CHAR              (10*1000*1000 / CONFIG_ESP_CONSOLE_UART_BAUDRATE)
+#endif
 #define CONCATENATE_HELPER(x, y)            (x##y)
 #define CONCATENATE(x, y)                   CONCATENATE_HELPER(x, y)
 #define CONSOLE_UART_DEV                    (&CONCATENATE(UART, CONFIG_ESP_CONSOLE_UART_NUM))

components/esp_psram/esp_psram.c

@@ -448,6 +448,15 @@ size_t esp_psram_get_size(void)
     return (size_t)available_size;
 }
 
+uint8_t* esp_psram_get_address(void)
+{
+    if (!s_psram_ctx.is_initialised) {
+        return NULL;
+    }
+
+    return s_psram_ctx.mapped_regions[PSRAM_MEM_8BIT_ALIGNED].vaddr_start;
+}
+
 uint8_t esp_psram_io_get_cs_io(void)
 {
     return esp_psram_impl_get_cs_io();

components/esp_psram/include/esp_psram.h

@@ -41,6 +41,13 @@ bool esp_psram_is_initialized(void);
  */
 size_t esp_psram_get_size(void);
 
+/**
+ * @brief Get the memory mapped address of the attached PSRAM chip
+ *
+ * @return Pointer to the start of PSRAM memory, or NULL if PSRAM isn't successfully initialized
+ */
+uint8_t* esp_psram_get_address(void);
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s2/include/hal/rtc_io_ll.h

@@ -68,6 +68,12 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
     } else if (func == RTCIO_LL_FUNC_DIGITAL) {
         CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
+        // If any other rtcio is set to rtc mux, then return early to leave the clock on.
+        for (int n = 0; n < SOC_RTCIO_PIN_COUNT; n++) {
+            if (GET_PERI_REG_MASK(rtc_io_desc[n].reg, rtc_io_desc[n].mux) != 0) {
+                return;
+            }
+        }
         SENS.sar_io_mux_conf.iomux_clk_gate_en = 0;
     }
 }

components/hal/esp32s3/include/hal/rtc_io_ll.h

@@ -75,6 +75,12 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         rtcio_ll_iomux_func_sel(rtcio_num, RTCIO_LL_PIN_FUNC);
     } else if (func == RTCIO_LL_FUNC_DIGITAL) {
         CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, (rtc_io_desc[rtcio_num].mux));
+        // If any other rtcio is set to rtc mux, then return early to leave the clock on.
+        for (int n = 0; n < SOC_RTCIO_PIN_COUNT; n++) {
+            if (GET_PERI_REG_MASK(rtc_io_desc[n].reg, rtc_io_desc[n].mux) != 0) {
+                return;
+            }
+        }
         SENS.sar_peri_clk_gate_conf.iomux_clk_en = 0;
         // USB Serial JTAG pad re-enable won't be done here (it requires both DM and DP pins not in rtc function)
         // Instead, USB_SERIAL_JTAG_USB_PAD_ENABLE needs to be guaranteed to be set in usb_serial_jtag driver

components/ulp/CMakeLists.txt

@@ -41,7 +41,9 @@ if(CONFIG_ULP_COPROC_TYPE_FSM OR CONFIG_ULP_COPROC_TYPE_RISCV)
             "ulp_fsm/ulp.c"
             "ulp_fsm/ulp_macro.c")
 
-    elseif(CONFIG_ULP_COPROC_TYPE_RISCV)
+    endif()
+
+    if(CONFIG_ULP_COPROC_TYPE_RISCV)
         list(APPEND srcs
             "ulp_riscv/ulp_riscv.c"
             "ulp_riscv/ulp_riscv_lock.c"

components/ulp/Kconfig

@@ -8,23 +8,21 @@ menu "Ultra Low Power (ULP) Co-processor"
             Enable this feature if you plan to use the ULP Co-processor.
             Once this option is enabled, further ULP co-processor configuration will appear in the menu.
 
-    choice ULP_COPROC_TYPE
-        prompt "ULP Co-processor type"
-        depends on ULP_COPROC_ENABLED
-        default ULP_COPROC_TYPE_RISCV if (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3)
+    config ULP_COPROC_TYPE_FSM
+        bool "Enable ULP FSM (Finite State Machine)"
+        depends on (SOC_ULP_FSM_SUPPORTED && ULP_COPROC_ENABLED)
         help
-            Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V.
-
-        config ULP_COPROC_TYPE_FSM
-            bool "ULP FSM (Finite State Machine)"
-            depends on SOC_ULP_FSM_SUPPORTED
-        config ULP_COPROC_TYPE_RISCV
-            bool "ULP RISC-V"
-            depends on SOC_RISCV_COPROC_SUPPORTED
-        config ULP_COPROC_TYPE_LP_CORE
-            bool "LP core RISC-V"
-            depends on SOC_LP_CORE_SUPPORTED
-    endchoice
+            Note: On devices with both ULP FSM and ULP RISC-V, both ULPs can be enabled simultaneously at compile-time, 
+            but may not be used simultaneously at run-time. 
+    config ULP_COPROC_TYPE_RISCV
+        bool "Enable ULP RISC-V"
+        depends on (SOC_RISCV_COPROC_SUPPORTED && ULP_COPROC_ENABLED)
+        help
+            Note: On devices with both ULP FSM and ULP RISC-V, both ULPs can be enabled simultaneously at compile-time, 
+            but may not be used simultaneously at run-time. 
+    config ULP_COPROC_TYPE_LP_CORE
+        bool "Enable LP core RISC-V"
+        depends on (SOC_LP_CORE_SUPPORTED && ULP_COPROC_ENABLED)
 
     config ULP_COPROC_RESERVE_MEM
         int

examples/wifi/power_save/pytest_wifi_power_save.py

@@ -1,6 +1,5 @@
-# SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: Apache-2.0
-
 import logging
 
 import pexpect
@@ -9,7 +8,7 @@ from common_test_methods import get_env_config_variable
 from pytest_embedded import Dut
 
 bad_event_str = [
-    'bcn_timout',
+    'bcn_timeout',
     'm f probe req l',
     'abort() was called',
     'Guru Meditation Error',
@@ -31,7 +30,7 @@ def _run_test(dut: Dut) -> None:
         pass
 
     try:
-        dut.expect(r'got ip: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=20)
+        dut.expect(r'got ip: (\d+\.\d+\.\d+\.\d+)[^\d]', timeout=30)
         log_after_got_ip = dut.expect(pexpect.TIMEOUT, timeout=10).decode()
         if any(s in log_after_got_ip for s in bad_event_str):
             logging.info('Abnormal connection log:')

tools/cmake/version.cmake

@@ -1,5 +1,5 @@
 set(IDF_VERSION_MAJOR 5)
 set(IDF_VERSION_MINOR 3)
-set(IDF_VERSION_PATCH 1)
+set(IDF_VERSION_PATCH 2)
 
 set(ENV{IDF_VERSION} "${IDF_VERSION_MAJOR}.${IDF_VERSION_MINOR}.${IDF_VERSION_PATCH}")