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esp-idf/components/esp32s3
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Angus Gratton 420aef1ffe Updates for riscv support 
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00
..
include Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
ld esp32s3/bootloader: extend IRAM usage to 0x6000 2020-10-09 17:50:17 +08:00
cache_err_int.c
clk.c Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
CMakeLists.txt Updates for riscv support 2020-11-13 07:49:11 +11:00
component.mk
crosscore_int.c
dport_access.c
esp_crypto_lock.c Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
hw_random.c components: remove some unneeded headers from source files 2020-10-22 19:37:10 +08:00
Kconfig Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
linker.lf
Makefile.projbuild
memprot.c esp32s3: sync memprot header from esp32s2, fixing compilation error 2020-10-08 22:20:39 +02:00
README.md
spiram.c support flash instr and rodata copy to SPIRAM 2020-09-22 15:15:03 +08:00
spiram_psram.c Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
spiram_psram.h psram: support psram for esp32s3 2020-09-22 15:15:03 +08:00
system_api_esp32s3.c components: remove some unneeded headers from source files 2020-10-22 19:37:10 +08:00

README.md

ESP32-S3 component

This directory contains support for the upcoming ESP32-S3 SoC. This code is still work in progress and not intended for public use.

Please follow announcements on espressif.com and esp32.com to be informed about the ESP32-S3 SoC.

This note will be removed once the ESP32-S3 initial support is ready.