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Add SPI ETH Multicast and ESP32-S2 I2C patches

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This commit is contained in:
me-no-dev 2023-11-27 17:28:51 +02:00
parent e86b30a9a6
commit 8dce212b36
3 changed files with 128 additions and 0 deletions
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17
patches/esp32s2_i2c_ll_master_init.diff Normal file
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@ -0,0 +1,17 @@
diff --git a/components/hal/esp32s2/include/hal/i2c_ll.h b/components/hal/esp32s2/include/hal/i2c_ll.h
index f9a66b61d6..2f669b68c0 100644
--- a/components/hal/esp32s2/include/hal/i2c_ll.h
+++ b/components/hal/esp32s2/include/hal/i2c_ll.h
@@ -653,10 +653,12 @@ static inline void i2c_ll_enable_controller_clock(i2c_dev_t *hw, bool en)
static inline void i2c_ll_master_init(i2c_dev_t *hw)
{
typeof(hw->ctr) ctrl_reg;
+ uint32_t ref_always_on = hw->ctr.ref_always_on;
ctrl_reg.val = 0;
ctrl_reg.ms_mode = 1;
ctrl_reg.sda_force_out = 1;
ctrl_reg.scl_force_out = 1;
+ ctrl_reg.ref_always_on = ref_always_on;
hw->ctr.val = ctrl_reg.val;
}

109
patches/eth_multicast.diff Normal file
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@ -0,0 +1,109 @@
diff --git a/components/esp_eth/src/esp_eth_mac_esp.c b/components/esp_eth/src/esp_eth_mac_esp.c
index 7704d9ac48cbe572aefcacd24bfcf6097a9a0562..d59e1e33b4ab3d8a9bde7527ec8f68175bf5dc1e 100644
--- a/components/esp_eth/src/esp_eth_mac_esp.c
+++ b/components/esp_eth/src/esp_eth_mac_esp.c
@@ -634,7 +634,6 @@ esp_eth_mac_t *esp_eth_mac_new_esp32(const eth_esp32_emac_config_t *esp32_config
emac->smi_mdio_gpio_num = esp32_config->smi_mdio_gpio_num;
emac->flow_control_high_water_mark = FLOW_CONTROL_HIGH_WATER_MARK;
emac->flow_control_low_water_mark = FLOW_CONTROL_LOW_WATER_MARK;
- emac->use_apll = false;
emac->parent.set_mediator = emac_esp32_set_mediator;
emac->parent.init = emac_esp32_init;
emac->parent.deinit = emac_esp32_deinit;
diff --git a/components/esp_eth/src/esp_eth_mac_ksz8851snl.c b/components/esp_eth/src/esp_eth_mac_ksz8851snl.c
index 10ab357fc4c68141361e5038af1856fa769fe168..473195a83b236236a604f26f5ce1765eed2c1d91 100644
--- a/components/esp_eth/src/esp_eth_mac_ksz8851snl.c
+++ b/components/esp_eth/src/esp_eth_mac_ksz8851snl.c
@@ -298,7 +298,7 @@ static esp_err_t init_set_defaults(emac_ksz8851snl_t *emac)
ESP_GOTO_ON_ERROR(ksz8851_set_bits(emac, KSZ8851_RXDTTR, RXDTTR_INIT_VALUE), err, TAG, "RXDTTR write failed");
ESP_GOTO_ON_ERROR(ksz8851_set_bits(emac, KSZ8851_RXDBCTR, RXDBCTR_INIT_VALUE), err, TAG, "RXDBCTR write failed");
ESP_GOTO_ON_ERROR(ksz8851_set_bits(emac, KSZ8851_RXCR1,
- RXCR1_RXUDPFCC | RXCR1_RXTCPFCC | RXCR1_RXIPFCC | RXCR1_RXPAFMA | RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME), err, TAG, "RXCR1 write failed");
+ RXCR1_RXUDPFCC | RXCR1_RXTCPFCC | RXCR1_RXIPFCC | RXCR1_RXPAFMA | RXCR1_RXFCE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXMAFMA | RXCR1_RXAE), err, TAG, "RXCR1 write failed");
ESP_GOTO_ON_ERROR(ksz8851_set_bits(emac, KSZ8851_RXCR2,
(4 << RXCR2_SRDBL_SHIFT) | RXCR2_IUFFP | RXCR2_RXIUFCEZ | RXCR2_UDPLFE | RXCR2_RXICMPFCC), err, TAG, "RXCR2 write failed");
ESP_GOTO_ON_ERROR(ksz8851_set_bits(emac, KSZ8851_RXQCR, RXQCR_RXFCTE | RXQCR_ADRFE), err, TAG, "RXQCR write failed");
@@ -650,13 +650,13 @@ static esp_err_t emac_ksz8851_set_promiscuous(esp_eth_mac_t *mac, bool enable)
if (enable) {
// NOTE(v.chistyakov): set promiscuous mode
ESP_LOGD(TAG, "setting promiscuous mode");
- rxcr1 |= RXCR1_RXINVF | RXCR1_RXAE;
+ rxcr1 |= RXCR1_RXAE | RXCR1_RXINVF;
rxcr1 &= ~(RXCR1_RXPAFMA | RXCR1_RXMAFMA);
} else {
// NOTE(v.chistyakov): set hash perfect (default)
- ESP_LOGD(TAG, "setting hash perfect mode");
- rxcr1 |= RXCR1_RXPAFMA;
- rxcr1 &= ~(RXCR1_RXINVF | RXCR1_RXAE | RXCR1_RXMAFMA);
+ ESP_LOGD(TAG, "setting perfect with multicast passed");
+ rxcr1 |= RXCR1_RXAE| RXCR1_RXPAFMA | RXCR1_RXMAFMA;
+ rxcr1 &= ~RXCR1_RXINVF;
}
ESP_GOTO_ON_ERROR(ksz8851_write_reg(emac, KSZ8851_RXCR1, rxcr1), err, TAG, "RXCR1 write failed");
err:
diff --git a/components/esp_eth/src/esp_eth_phy_802_3.c b/components/esp_eth/src/esp_eth_phy_802_3.c
index 51a10fd551820bda41db581a3f65d63f63306972..785a0c0feb7725e5f9ce7174220d4df37cb14b45 100644
--- a/components/esp_eth/src/esp_eth_phy_802_3.c
+++ b/components/esp_eth/src/esp_eth_phy_802_3.c
@@ -302,16 +302,18 @@ esp_err_t esp_eth_phy_802_3_detect_phy_addr(esp_eth_mediator_t *eth, int *detect
}
int addr_try = 0;
uint32_t reg_value = 0;
- for (; addr_try < 16; addr_try++) {
- eth->phy_reg_read(eth, addr_try, ETH_PHY_IDR1_REG_ADDR, &reg_value);
- if (reg_value != 0xFFFF && reg_value != 0x00) {
- *detected_addr = addr_try;
- break;
+ for (int i = 0; i < 3; i++){
+ for (addr_try = 0; addr_try < 32; addr_try++) {
+ eth->phy_reg_read(eth, addr_try, ETH_PHY_IDR1_REG_ADDR, &reg_value);
+ if (reg_value != 0xFFFF && reg_value != 0x00) {
+ *detected_addr = addr_try;
+ break;
+ }
+ }
+ if (addr_try < 32) {
+ ESP_LOGD(TAG, "Found PHY address: %d", addr_try);
+ return ESP_OK;
}
- }
- if (addr_try < 16) {
- ESP_LOGD(TAG, "Found PHY address: %d", addr_try);
- return ESP_OK;
}
ESP_LOGE(TAG, "No PHY device detected");
return ESP_ERR_NOT_FOUND;
diff --git a/components/esp_eth/src/esp_eth_phy_dm9051.c b/components/esp_eth/src/esp_eth_phy_dm9051.c
index d8f9bad9fc8a4da396f65c47f283335bf5448b2f..6db49f8fad0adacf78c52e78525b856bfb53b643 100644
--- a/components/esp_eth/src/esp_eth_phy_dm9051.c
+++ b/components/esp_eth/src/esp_eth_phy_dm9051.c
@@ -95,7 +95,7 @@ static esp_err_t dm9051_update_link_duplex_speed(phy_dm9051_t *dm9051)
eth_duplex_t duplex = ETH_DUPLEX_HALF;
uint32_t peer_pause_ability = false;
bmsr_reg_t bmsr;
- dscsr_reg_t dscsr;
+ bmcr_reg_t bmcr;
anlpar_reg_t anlpar;
// BMSR is a latch low register
// after power up, the first latched value must be 0, which means down
@@ -108,17 +108,9 @@ static esp_err_t dm9051_update_link_duplex_speed(phy_dm9051_t *dm9051)
if (dm9051->phy_802_3.link_status != link) {
/* when link up, read negotiation result */
if (link == ETH_LINK_UP) {
- ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_DSCSR_REG_ADDR, &(dscsr.val)), err, TAG, "read DSCSR failed");
- if (dscsr.fdx100 || dscsr.hdx100) {
- speed = ETH_SPEED_100M;
- } else {
- speed = ETH_SPEED_10M;
- }
- if (dscsr.fdx100 || dscsr.fdx10) {
- duplex = ETH_DUPLEX_FULL;
- } else {
- duplex = ETH_DUPLEX_HALF;
- }
+ ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
+ speed = bmcr.speed_select == 1 ? ETH_SPEED_100M : ETH_SPEED_10M;
+ duplex = bmcr.duplex_mode == 1 ? ETH_DUPLEX_FULL : ETH_DUPLEX_HALF;
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
/* if we're in duplex mode, and peer has the flow control ability */

2
tools/install-esp-idf.sh
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@ -38,6 +38,8 @@ if [ ! -x $idf_was_installed ] || [ ! -x $commit_predefined ]; then
# Temporarily patch the ETH driver to support custom SPI
cd $IDF_PATH
patch -p1 -N -i ../patches/spi_eth.diff
patch -p1 -N -i ../patches/eth_multicast.diff
patch -p1 -N -i ../patches/esp32s2_i2c_ll_master_init.diff
cd -
fi