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nrfx 0.8.0 release

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Głąbek, Andrzej 2017-12-20 14:09:26 +01:00
parent bd4c9a1099
commit b7cfe970b4
104 changed files with 152737 additions and 4073 deletions
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25
CHANGELOG.md
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@ -1,10 +1,27 @@
# Changelog
All notable changes to this project will be documented in this file.
All notable changes to this project are documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
## [0.8.0] - 2017-12-20
### Added
- Added XIP support in the QSPI driver.
- Implemented Errata 132 in the CLOCK driver.
- Added function for checking if a TIMER instance is enabled.
- Added extended SPIM support.
## [Unreleased]
### Changed
- Updated MDK to 8.15.0. Introduced Segger Embedded Studio startup files.
- Updated drivers: COMP, PWM, QDEC, SAADC, SPIS, TIMER, TWI, TWIS.
- Changed the type used for transfer lengths to 'size_t' in drivers: SPI, SPIM, SPIS, TWI, TWIM, TWIS, UART, UARTE. Introduced checking of EasyDMA transfers limits.
- Updated HALs: COMP, NVMC, UART, UARTE, USBD.
- Updated template files and documentation of configuration options.
### Fixed
- Fixed TWI and TWIM drivers so that they now support GPIOs from all ports.
- Fixed definitions related to compare channels in the TIMER HAL.
### Removed
- Removed the possibility of passing NULL instead of configuration to get default settings during drivers initialization.
- Removed support for UART1 and PRS box #5.
## [0.7.0] - 2017-10-20
### Added

29
LICENSE Normal file
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@ -0,0 +1,29 @@
BSD 3-Clause License
Copyright (c) 2017, Nordic Semiconductor ASA
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

4
README.md
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@ -35,7 +35,3 @@ nrfx documentation is availabe in the `doc\html` folder of the release package.
You can also generate documentation yourself from the source code. To do it, install doxygen
and run one of the scripts: `generate_html_doc.bat` or `generate_html_doc.sh`. Generated
documentation will be stored in the `doc\html` directory. Use `index.html` to open it.
## Licence
nrfx is licensed under the BSD 3-clause License. License text can be found in every source file.

51
doc/config_dox/nrfx_prs_dox_config.h
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@ -51,13 +51,60 @@
*/
#define NRFX_PRS_BOX_4_ENABLED
/** @brief Enables box 5 in the module.
/** @brief Enables logging in the module.
*
* Set to 1 to activate.
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_PRS_BOX_5_ENABLED
#define NRFX_PRS_CONFIG_LOG_ENABLED
/** @brief Default Severity level
*
* Following options are available:
* - 0 - Off
* - 1 - Error
* - 2 - Warning
* - 3 - Info
* - 4 - Debug
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_PRS_CONFIG_LOG_LEVEL
/** @brief ANSI escape code prefix.
*
* Following options are available:
* - 0 - Default
* - 1 - Black
* - 2 - Red
* - 3 - Green
* - 4 - Yellow
* - 5 - Blue
* - 6 - Magenta
* - 7 - Cyan
* - 8 - White
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_PRS_CONFIG_INFO_COLOR
/** @brief ANSI escape code prefix.
*
* Following options are available:
* - 0 - Default
* - 1 - Black
* - 2 - Red
* - 3 - Green
* - 4 - Yellow
* - 5 - Blue
* - 6 - Magenta
* - 7 - Cyan
* - 8 - White
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_PRS_CONFIG_DEBUG_COLOR
/** @} */

7
doc/config_dox/nrfx_qspi_dox_config.h
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@ -20,6 +20,13 @@
*/
#define NRFX_QSPI_CONFIG_SCK_DELAY
/** @brief Address offset in the external memory for Execute in Place operation.
*
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_QSPI_CONFIG_XIP_OFFSET
/** @brief Number of data lines and opcode used for reading.
*
* Following options are available:

11
doc/config_dox/nrfx_spi_dox_config.h
View file

@ -35,6 +35,17 @@
*/
#define NRFX_SPI2_ENABLED
/** @brief MISO pin pull configuration.
*
* Following options are available:
* - 0 - NRF_GPIO_PIN_NOPULL
* - 1 - NRF_GPIO_PIN_PULLDOWN
* - 3 - NRF_GPIO_PIN_PULLUP
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_SPI_MISO_PULL_CFG
/** @brief Interrupt priority
*
* Following options are available:

27
doc/config_dox/nrfx_spim_dox_config.h
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@ -35,6 +35,33 @@
*/
#define NRFX_SPIM2_ENABLED
/** @brief Enable SPIM3 instance
*
* Set to 1 to activate.
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_SPIM3_ENABLED
/** @brief Enable extended SPIM features
*
* Set to 1 to activate.
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_SPIM_EXTENDED_ENABLED
/** @brief MISO pin pull configuration.
*
* Following options are available:
* - 0 - NRF_GPIO_PIN_NOPULL
* - 1 - NRF_GPIO_PIN_PULLDOWN
* - 3 - NRF_GPIO_PIN_PULLUP
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_SPIM_MISO_PULL_CFG
/** @brief Interrupt priority
*
* Following options are available:

26
doc/config_dox/nrfx_uart_dox_config.h
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@ -18,13 +18,6 @@
*/
#define NRFX_UART0_ENABLED
/** @brief Enable UART1 instance
*
*
* @note This is an NRF_CONFIG macro.
*/
#define NRFX_UART1_ENABLED
/** @brief Hardware Flow Control
*
* Following options are available:
@ -52,18 +45,19 @@
* - 643072 - 2400 baud
* - 1290240 - 4800 baud
* - 2576384 - 9600 baud
* - 3862528 - 14400 baud
* - 3866624 - 14400 baud
* - 5152768 - 19200 baud
* - 7716864 - 28800 baud
* - 10289152 - 38400 baud
* - 15400960 - 57600 baud
* - 7729152 - 28800 baud
* - 8388608 - 31250 baud
* - 10309632 - 38400 baud
* - 15007744 - 56000 baud
* - 15462400 - 57600 baud
* - 20615168 - 76800 baud
* - 30801920 - 115200 baud (nRF52 family only)
* - 30924800 - 115200 baud (nRF51 family only)
* - 61865984 - 230400 baud
* - 30924800 - 115200 baud
* - 61845504 - 230400 baud
* - 67108864 - 250000 baud
* - 121634816 - 460800 baud
* - 251658240 - 921600 baud
* - 123695104 - 460800 baud
* - 247386112 - 921600 baud
* - 268435456 - 1000000 baud
*
* @note This is an NRF_CONFIG macro.

5
doc/config_dox/nrfx_uarte_dox_config.h
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@ -55,11 +55,12 @@
* - 3862528 - 14400 baud
* - 5152768 - 19200 baud
* - 7716864 - 28800 baud
* - 8388608 - 31250 baud
* - 10289152 - 38400 baud
* - 15007744 - 56000 baud
* - 15400960 - 57600 baud
* - 20615168 - 76800 baud
* - 30801920 - 115200 baud (nRF52 family only)
* - 30924800 - 115200 baud (nRF51 family only)
* - 30801920 - 115200 baud
* - 61865984 - 230400 baud
* - 67108864 - 250000 baud
* - 121634816 - 460800 baud

2
doc/drv_supp_matrix.dox
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@ -12,7 +12,7 @@ Driver | nRF51 Series | nRF52810 | nRF52832 | nRF52840 |
@ref nrf_gpio |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
@ref nrf_gpiote |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
@ref nrf_i2s |@tagRedCross |@tagRedCross |@tagGreenTick |@tagGreenTick |
@ref nrf_lpcomp |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
@ref nrf_lpcomp |@tagGreenTick |@tagRedCross |@tagGreenTick |@tagGreenTick |
@ref nrf_nvmc |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |
@ref nrf_pdm |@tagRedCross |@tagGreenTick |@tagGreenTick |@tagGreenTick |
@ref nrf_power |@tagGreenTick |@tagGreenTick |@tagGreenTick |@tagGreenTick |

0
doc/generate_html_doc.sh Normal file → Executable file
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3
doc/main_page.dox
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@ -75,8 +75,9 @@ Refer to the "driver configuration" section in the API reference for a given
driver for more information regarding configuration options available for it.
@section nrfx_additional_reqs Additional requirements
Nordic SoCs are based on ARM® Cortex™-M series processors. Before you can
start developing with nrfx, you must add the CMSIS header files to include
start developing with @em nrfx, you must add the CMSIS header files to include
paths during the compilation process. Download these files from the following
website:

2
doc/nrfx.doxyfile
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@ -33,7 +33,7 @@ PROJECT_NAME = "nrfx"
# This could be handy for archiving the generated documentation or
# if some version control system is used.
PROJECT_NUMBER = "0.7"
PROJECT_NUMBER = "0.8"
### EDIT THIS ###
# Using the PROJECT_BRIEF tag one can provide an optional one line description

2
drivers/include/nrfx_adc.h
View file

@ -159,7 +159,7 @@ typedef void (*nrfx_adc_event_handler_t)(nrfx_adc_evt_t const * p_event);
* If a valid event handler is provided, the driver is initialized in non-blocking mode.
* If event_handler is NULL, the driver works in blocking mode.
*
* @param[in] p_config Driver configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Event handler provided by the user.
*
* @retval NRFX_SUCCESS If initialization was successful.

19
drivers/include/nrfx_comp.h
View file

@ -89,7 +89,9 @@ typedef struct
nrf_comp_th_t threshold; /**< Structure holding THDOWN and THUP values needed by the COMP_TH register. */
nrf_comp_sp_mode_t speed_mode; /**< Speed and power mode. */
nrf_comp_hyst_t hyst; /**< Comparator hysteresis.*/
#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__)
nrf_isource_t isource; /**< Current source selected on analog input. */
#endif
nrf_comp_input_t input; /**< Input to be monitored. */
uint8_t interrupt_priority; /**< Interrupt priority. */
} nrfx_comp_config_t;
@ -102,6 +104,7 @@ typedef struct
}
/** @brief COMP driver default configuration including the COMP HAL configuration. */
#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__)
#define NRFX_COMP_DEFAULT_CONFIG(_input) \
{ \
.reference = (nrf_comp_ref_t)NRFX_COMP_CONFIG_REF, \
@ -113,6 +116,18 @@ typedef struct
.input = (nrf_comp_input_t)_input, \
.interrupt_priority = NRFX_COMP_CONFIG_IRQ_PRIORITY \
}
#else
#define NRFX_COMP_DEFAULT_CONFIG(_input) \
{ \
.reference = (nrf_comp_ref_t)NRFX_COMP_CONFIG_REF, \
.main_mode = (nrf_comp_main_mode_t)NRFX_COMP_CONFIG_MAIN_MODE, \
.threshold = NRFX_COMP_CONFIG_TH, \
.speed_mode = (nrf_comp_sp_mode_t)NRFX_COMP_CONFIG_SPEED_MODE, \
.hyst = (nrf_comp_hyst_t)NRFX_COMP_CONFIG_HYST, \
.input = (nrf_comp_input_t)_input, \
.interrupt_priority = NRFX_COMP_CONFIG_IRQ_PRIORITY \
}
#endif
/**
* @brief Function for initializing the COMP driver.
@ -120,9 +135,7 @@ typedef struct
* This function initializes the COMP driver, but does not enable the peripheral or any interrupts.
* To start the driver, call the function @ref nrfx_comp_start() after initialization.
*
* If no configuration structure is provided, the driver is initialized with the default settings.
*
* @param[in] p_config Initial configuration. If NULL, the default configuration is used.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Handler function.
*
* @retval NRFX_ERROR_INVALID_PARAM If the configuration is invalid.

1
drivers/include/nrfx_i2s.h
View file

@ -151,7 +151,6 @@ typedef void (* nrfx_i2s_data_handler_t)(uint32_t const * p_data_received,
* @brief Function for initializing the I2S driver.
*
* @param[in] p_config Pointer to the structure with initial configuration.
* If NULL, the default configuration is used.
* @param[in] handler Data handler provided by the user. Must not be NULL.
*
* @retval NRFX_SUCCESS If initialization was successful.

2
drivers/include/nrfx_lpcomp.h
View file

@ -88,7 +88,7 @@ typedef struct
*
* If no configuration structure is provided, the driver is initialized with the default settings.
*
* @param[in] p_config Initial configuration. If NULL, the default configuration is used.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Handler function.
*
* @retval NRFX_ERROR_INVALID_PARAM If the configuration is invalid.

4
drivers/include/nrfx_pdm.h
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@ -117,12 +117,12 @@ typedef void (*nrfx_pdm_event_handler_t)(nrfx_pdm_evt_t const * const p_evt);
/**
* @brief Function for initializing the PDM interface.
*
* @param[in] p_config Pointer to a configuration structure. Cannot be NULL.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Event handler provided by the user. Cannot be NULL.
*
* @retval NRFX_SUCCESS If initialization was successful.
* @retval NRFX_ERROR_INVALID_STATE If the driver is already initialized.
* @retval NRFX_ERROR_INVALID_PARAM If invalid parameters were specified.
* @retval NRFX_ERROR_INVALID_PARAM If specified event handler is NULL.
*/
nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config,
nrfx_pdm_event_handler_t event_handler);

3
drivers/include/nrfx_power.h
View file

@ -217,8 +217,7 @@ nrfx_power_usb_event_handler_t nrfx_power_usb_handler_get(void);
*
* Enabled power module driver would process all the interrupts from power system.
*
* @param[in] p_config Driver configuration. Can be NULL - the default configuration
* from @em sdk_config.h file would be used then.
* @param[in] p_config Pointer to the structure with initial configuration.
*
* @retval NRFX_SUCCESS Successfully initialized.
* @retval NRFX_ERROR_ALREADY_INITIALIZED Module was already initialized.

2
drivers/include/nrfx_qdec.h
View file

@ -107,7 +107,7 @@ typedef void (*nrfx_qdec_event_handler_t)(nrfx_qdec_event_t event);
/**@brief Function for initializing QDEC.
*
* @param[in] p_config Pointer to configuration parameters.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Event handler function.
*
* @retval NRFX_SUCCESS If initialization was successful.

6
drivers/include/nrfx_qspi.h
View file

@ -51,6 +51,7 @@ extern "C" {
*/
typedef struct
{
uint32_t xip_offset; /**< Address offset into the external memory for Execute in Place operation. */
nrf_qspi_pins_t pins; /**< Pins configuration structure. */
nrf_qspi_prot_conf_t prot_if; /**< Protocol layer interface configuration structure. */
nrf_qspi_phy_conf_t phy_if; /**< Physical layer interface configuration structure. */
@ -62,6 +63,7 @@ typedef struct
*/
#define NRFX_QSPI_DEFAULT_CONFIG \
{ \
.xip_offset = NRFX_QSPI_CONFIG_XIP_OFFSET, \
.pins = { \
.sck_pin = NRFX_QSPI_PIN_SCK, \
.csn_pin = NRFX_QSPI_PIN_CSN, \
@ -82,7 +84,7 @@ typedef struct
.sck_delay = (uint8_t)NRFX_QSPI_CONFIG_SCK_DELAY, \
.spi_mode = (nrf_qspi_spi_mode_t)NRFX_QSPI_CONFIG_MODE, \
.dpmen = false \
} \
}, \
}
/**
@ -115,7 +117,7 @@ typedef void (*nrfx_qspi_handler_t)(nrfx_qspi_evt_t event, void * p_context);
/**
* @brief Function for initializing the QSPI driver instance.
*
* @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] handler Event handler provided by the user. If NULL, transfers
* will be performed in blocking mode.
* @param[in] p_context Pointer to context. Use in interrupt handler.

4
drivers/include/nrfx_rng.h
View file

@ -77,13 +77,13 @@ typedef void (* nrfx_rng_evt_handler_t)(uint8_t rng_data);
/**
* @brief Function for initializing the nrfx_rng module.
*
* @param[in] p_config Initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] handler Event handler provided by the user. Handler is required
* to work with the module. NULL value is not supported.
*
* @retval NRFX_SUCCESS Driver was successfully initialized.
* @retval NRFX_ERROR_ALREADY_INITIALIZED Driver was already initialized.
* @retval NRFX_ERROR_INVALID_PARAM Handler value or p_config is NULL.
* @retval NRFX_ERROR_INVALID_PARAM Handler value is NULL.
*/
nrfx_err_t nrfx_rng_init(nrfx_rng_config_t const * p_config, nrfx_rng_evt_handler_t handler);

2
drivers/include/nrfx_rtc.h
View file

@ -121,7 +121,7 @@ typedef void (*nrfx_rtc_handler_t)(nrfx_rtc_int_type_t int_type);
* After initialization, the instance is in power off state.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] handler User's event handler.
*
* @retval NRFX_SUCCESS If successfully initialized.

2
drivers/include/nrfx_saadc.h
View file

@ -168,7 +168,7 @@ typedef void (* nrfx_saadc_event_handler_t)(nrfx_saadc_evt_t const * p_event);
/**
* @brief Function for initializing the SAADC.
*
* @param[in] p_config Pointer to a configuration structure. If NULL, the default one is used.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Event handler provided by the user.
*
* @retval NRFX_SUCCESS If initialization was successful.

29
drivers/include/nrfx_spi.h
View file

@ -167,9 +167,9 @@ typedef struct
typedef struct
{
uint8_t const * p_tx_buffer; ///< Pointer to TX buffer.
uint32_t tx_length; ///< TX buffer length.
size_t tx_length; ///< TX buffer length.
uint8_t * p_rx_buffer; ///< Pointer to RX buffer.
uint32_t rx_length; ///< RX buffer length.
size_t rx_length; ///< RX buffer length.
}nrfx_spi_xfer_desc_t;
/**
@ -230,7 +230,7 @@ typedef void (* nrfx_spi_evt_handler_t)(nrfx_spi_evt_t const * p_event,
* This function configures and enables the specified peripheral.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
*
* @param handler Event handler provided by the user. If NULL, transfers
* will be performed in blocking mode.
@ -263,31 +263,10 @@ void nrfx_spi_uninit(nrfx_spi_t const * const p_instance);
* Otherwise, the transfer is performed in blocking mode, which means that this function
* returns when the transfer is finished.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_tx_buffer Pointer to the transmit buffer. Can be NULL
* if there is nothing to send.
* @param tx_buffer_length Length of the transmit buffer.
* @param[in] p_rx_buffer Pointer to the receive buffer. Can be NULL
* if there is nothing to receive.
* @param rx_buffer_length Length of the receive buffer.
*
* @retval NRFX_SUCCESS If the operation was successful.
* @retval NRFX_ERROR_BUSY If a previously started transfer has not finished yet.
*/
nrfx_err_t nrfx_spi_transfer(nrfx_spi_t const * const p_instance,
uint8_t const * p_tx_buffer,
uint32_t tx_buffer_length,
uint8_t * p_rx_buffer,
uint32_t rx_buffer_length);
/**
* @brief Function for starting the SPI data transfer with additional option flags.
*
* Currently, no additional flags available.
*
* @param p_instance Pointer to the driver instance structure.
* @param p_xfer_desc Pointer to the transfer descriptor.
* @param flags Transfer options (0 for default settings).
* Currently, no additional flags are available.
*
* @retval NRFX_SUCCESS If the procedure was successful.
* @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.

186
drivers/include/nrfx_spim.h
View file

@ -64,6 +64,9 @@ enum {
#endif
#if NRFX_CHECK(NRFX_SPIM2_ENABLED)
NRFX_SPIM2_INST_IDX,
#endif
#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
NRFX_SPIM3_INST_IDX,
#endif
NRFX_SPIM_ENABLED_COUNT
};
@ -84,40 +87,6 @@ enum {
*/
#define NRFX_SPIM_PIN_NOT_USED 0xFF
/**
* @brief SPIM data rates.
*/
typedef enum
{
NRFX_SPIM_FREQ_125K = NRF_SPIM_FREQ_125K, ///< 125 kbps.
NRFX_SPIM_FREQ_250K = NRF_SPIM_FREQ_250K, ///< 250 kbps.
NRFX_SPIM_FREQ_500K = NRF_SPIM_FREQ_500K, ///< 500 kbps.
NRFX_SPIM_FREQ_1M = NRF_SPIM_FREQ_1M, ///< 1 Mbps.
NRFX_SPIM_FREQ_2M = NRF_SPIM_FREQ_2M, ///< 2 Mbps.
NRFX_SPIM_FREQ_4M = NRF_SPIM_FREQ_4M, ///< 4 Mbps.
NRFX_SPIM_FREQ_8M = NRF_SPIM_FREQ_8M ///< 8 Mbps.
} nrfx_spim_frequency_t;
/**
* @brief SPIM modes.
*/
typedef enum
{
NRFX_SPIM_MODE_0 = NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
NRFX_SPIM_MODE_1 = NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
NRFX_SPIM_MODE_2 = NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock.
NRFX_SPIM_MODE_3 = NRF_SPIM_MODE_3 ///< SCK active low, sample on trailing edge of clock.
} nrfx_spim_mode_t;
/**
* @brief SPIM bit orders.
*/
typedef enum
{
NRFX_SPIM_BIT_ORDER_MSB_FIRST = NRF_SPIM_BIT_ORDER_MSB_FIRST, ///< Most significant bit shifted out first.
NRFX_SPIM_BIT_ORDER_LSB_FIRST = NRF_SPIM_BIT_ORDER_LSB_FIRST ///< Least significant bit shifted out first.
} nrfx_spim_bit_order_t;
/**
* @brief SPIM master driver instance configuration structure.
*/
@ -125,40 +94,67 @@ typedef struct
{
uint8_t sck_pin; ///< SCK pin number.
uint8_t mosi_pin; ///< MOSI pin number (optional).
/**< Set to @ref NRFX_SPI_PIN_NOT_USED
/**< Set to @ref NRFX_SPIM_PIN_NOT_USED
* if this signal is not needed. */
uint8_t miso_pin; ///< MISO pin number (optional).
/**< Set to @ref NRFX_SPI_PIN_NOT_USED
/**< Set to @ref NRFX_SPIM_PIN_NOT_USED
* if this signal is not needed. */
uint8_t ss_pin; ///< Slave Select pin number (optional).
/**< Set to @ref NRFX_SPI_PIN_NOT_USED
* if this signal is not needed. The driver
* supports only active low for this signal.
* If the signal should be active high,
* it must be controlled externally. */
/**< Set to @ref NRFX_SPIM_PIN_NOT_USED
* if this signal is not needed. */
bool ss_active_high; ///< Polarity of the Slave Select pin during transmission.
uint8_t irq_priority; ///< Interrupt priority.
uint8_t orc; ///< Over-run character.
/**< This character is used when all bytes from the TX buffer are sent,
but the transfer continues due to RX. */
nrfx_spim_frequency_t frequency; ///< SPI frequency.
nrfx_spim_mode_t mode; ///< SPI mode.
nrfx_spim_bit_order_t bit_order; ///< SPI bit order.
nrf_spim_frequency_t frequency; ///< SPI frequency.
nrf_spim_mode_t mode; ///< SPI mode.
nrf_spim_bit_order_t bit_order; ///< SPI bit order.
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__)
uint8_t dcx_pin; ///< D/CX pin number (optional).
uint8_t rx_delay; ///< Sample delay for input serial data on MISO.
/**< The value specifies the delay, in number of 64 MHz clock cycles
* (15.625 ns), from the the sampling edge of SCK (leading edge for
* CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until
* the input serial data is sampled.*/
bool use_hw_ss; ///< Indication to use software or hardware controlled Slave Select pin.
uint8_t ss_duration; ///< Slave Select duration before and after transmission.
/**< Minimum duration between the edge of CSN and the edge of SCK and minimum
* duration of CSN must stay inactive between transactions.
* The value is specified in number of 64 MHz clock cycles (15.625 ns).
* Supported only for hardware controlled Slave Select.*/
#endif
} nrfx_spim_config_t;
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__)
/**
* @brief SPIM master instance extended default configuration.
*/
#define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \
.dcx_pin = NRFX_SPIM_PIN_NOT_USED, \
.rx_delay = 0x00, \
.ss_duration = 0x00, \
.use_hw_ss = false,
#else
#define NRFX_SPIM_DEFAULT_EXTENDED_CONFIG
#endif
/**
* @brief SPIM master instance default configuration.
*/
#define NRFX_SPIM_DEFAULT_CONFIG \
{ \
.sck_pin = NRFX_SPIM_PIN_NOT_USED, \
.mosi_pin = NRFX_SPIM_PIN_NOT_USED, \
.miso_pin = NRFX_SPIM_PIN_NOT_USED, \
.ss_pin = NRFX_SPIM_PIN_NOT_USED, \
.irq_priority = NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY, \
.orc = 0xFF, \
.frequency = NRFX_SPIM_FREQ_4M, \
.mode = NRFX_SPIM_MODE_0, \
.bit_order = NRFX_SPIM_BIT_ORDER_MSB_FIRST, \
#define NRFX_SPIM_DEFAULT_CONFIG \
{ \
.sck_pin = NRFX_SPIM_PIN_NOT_USED, \
.mosi_pin = NRFX_SPIM_PIN_NOT_USED, \
.miso_pin = NRFX_SPIM_PIN_NOT_USED, \
.ss_pin = NRFX_SPIM_PIN_NOT_USED, \
.ss_active_high = false, \
.irq_priority = NRFX_SPIM_DEFAULT_CONFIG_IRQ_PRIORITY, \
.orc = 0xFF, \
.frequency = NRF_SPIM_FREQ_4M, \
.mode = NRF_SPIM_MODE_0, \
.bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST, \
NRFX_SPIM_DEFAULT_EXTENDED_CONFIG \
}
#define NRFX_SPIM_FLAG_TX_POSTINC (1UL << 0) /**< TX buffer address incremented after transfer. */
@ -173,9 +169,9 @@ typedef struct
typedef struct
{
uint8_t const * p_tx_buffer; ///< Pointer to TX buffer.
uint8_t tx_length; ///< TX buffer length.
size_t tx_length; ///< TX buffer length.
uint8_t * p_rx_buffer; ///< Pointer to RX buffer.
uint8_t rx_length; ///< RX buffer length.
size_t rx_length; ///< RX buffer length.
} nrfx_spim_xfer_desc_t;
/**
@ -236,7 +232,7 @@ typedef void (* nrfx_spim_evt_handler_t)(nrfx_spim_evt_t const * p_event,
* This function configures and enables the specified peripheral.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Pointer to the structure with the initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
*
* @param handler Event handler provided by the user. If NULL, transfers
* will be performed in blocking mode.
@ -248,6 +244,8 @@ typedef void (* nrfx_spim_evt_handler_t)(nrfx_spim_evt_t const * p_event,
* instance ID is already in use. This is
* possible only if @ref nrfx_prs module
* is enabled.
* @retval NRFX_ERROR_NOT_SUPPORTED If requested configuration is not supported
* by the SPIM instance.
*/
nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
nrfx_spim_config_t const * p_config,
@ -264,41 +262,7 @@ void nrfx_spim_uninit(nrfx_spim_t const * const p_instance);
/**
* @brief Function for starting the SPI data transfer.
*
* If an event handler was provided in the @ref nrfx_spim_init call, this function
* returns immediately and the handler is called when the transfer is done.
* Otherwise, the transfer is performed in blocking mode, which means that this function
* returns when the transfer is finished.
*
* @note Peripherals using EasyDMA (including SPIM) require the transfer buffers
* to be placed in the Data RAM region. If this condition is not met,
* this function will fail with the error code NRFX_ERROR_INVALID_ADDR.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_tx_buffer Pointer to the transmit buffer. Can be NULL
* if there is nothing to send.
* @param tx_buffer_length Length of the transmit buffer.
* @param[in] p_rx_buffer Pointer to the receive buffer. Can be NULL
* if there is nothing to receive.
* @param rx_buffer_length Length of the receive buffer.
*
* @retval NRFX_SUCCESS If the operation was successful.
* @retval NRFX_ERROR_BUSY If a previously started transfer has not finished
* yet.
* @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data
* RAM region.
*/
nrfx_err_t nrfx_spim_transfer(nrfx_spim_t const * const p_instance,
uint8_t const * p_tx_buffer,
uint8_t tx_buffer_length,
uint8_t * p_rx_buffer,
uint8_t rx_buffer_length);
/**
* @brief Function for starting the SPI data transfer with additional options.
*
* @note This function is intended to be used only in non-blocking mode.
*
* Additional options are provided using the flags parameter:
* Additional options are provided using the @c flags parameter:
*
* - @ref NRFX_SPIM_FLAG_TX_POSTINC and @ref NRFX_SPIM_FLAG_RX_POSTINC<span></span>:
* Post-incrementation of buffer addresses. Supported only by SPIM.
@ -341,6 +305,41 @@ nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance,
nrfx_spim_xfer_desc_t const * p_xfer_desc,
uint32_t flags);
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for starting the SPI data transfer with DCX control.
*
* See @ref nrfx_spim_xfer for description of additional options of transfer
* provided by the @c flags parameter.
*
* @note Peripherals that use EasyDMA (including SPIM) require the transfer buffers
* to be placed in the Data RAM region. If this condition is not met,
* this function will fail with the error code NRFX_ERROR_INVALID_ADDR.
*
* @param p_instance Pointer to the driver instance structure.
* @param p_xfer_desc Pointer to the transfer descriptor.
* @param flags Transfer options (0 for default settings).
* @param cmd_length Length of the command bytes preceding the data
* bytes. The DCX line will be low during transmission
* of command bytes and high during transmission of data bytes.
* Maximum value available for dividing the transmitted bytes
* into command bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1.
* The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the
* @c cmd_length parameter causes all transmitted bytes
* to be marked as command bytes.
*
* @retval NRFX_SUCCESS If the procedure was successful.
* @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
* @retval NRFX_ERROR_NOT_SUPPORTED If the provided parameters are not supported.
* @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data
* RAM region.
*/
nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance,
nrfx_spim_xfer_desc_t const * p_xfer_desc,
uint32_t flags,
uint8_t cmd_length);
#endif
/**
* @brief Function for returning the address of a SPIM start task.
*
@ -376,6 +375,7 @@ void nrfx_spim_abort(nrfx_spim_t const * p_instance);
void nrfx_spim_0_irq_handler(void);
void nrfx_spim_1_irq_handler(void);
void nrfx_spim_2_irq_handler(void);
void nrfx_spim_3_irq_handler(void);
/** @} */

12
drivers/include/nrfx_spis.h
View file

@ -85,8 +85,8 @@ typedef enum
typedef struct
{
nrfx_spis_event_type_t evt_type; //!< Type of event.
uint32_t rx_amount; //!< Number of bytes received in last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events.
uint32_t tx_amount; //!< Number of bytes transmitted in last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events.
size_t rx_amount; //!< Number of bytes received in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events.
size_t tx_amount; //!< Number of bytes transmitted in the last transaction. This parameter is only valid for @ref NRFX_SPIS_XFER_DONE events.
} nrfx_spis_event_t;
/** @brief SPI slave driver instance data structure. */
@ -166,8 +166,7 @@ typedef void (*nrfx_spis_event_handler_t)(nrfx_spis_event_t event);
* to detect falling edges on CSN pin.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Pointer to the structure with the initial configuration.
* If NULL, the default configuration will be used.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Function to be called by the SPI slave driver upon event.
*
* @retval NRFX_SUCCESS If the initialization was successful.
@ -221,13 +220,14 @@ void nrfx_spis_uninit(nrfx_spis_t const * const p_instance);
* @retval NRFX_ERROR_INVALID_STATE If the operation failed because the SPI slave device is in an incorrect state.
* @retval NRFX_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data
* RAM region.
* @retval NRFX_ERROR_INVALID_LENGTH If provided lengths exceed the EasyDMA limits for the peripheral.
* @retval NRFX_ERROR_INTERNAL If the operation failed because of an internal error.
*/
nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance,
uint8_t const * p_tx_buffer,
uint8_t tx_buffer_length,
size_t tx_buffer_length,
uint8_t * p_rx_buffer,
uint8_t rx_buffer_length);
size_t rx_buffer_length);
void nrfx_spis_0_irq_handler(void);

11
drivers/include/nrfx_timer.h
View file

@ -125,7 +125,7 @@ typedef void (* nrfx_timer_event_handler_t)(nrf_timer_event_t event_type,
* @brief Function for initializing the timer.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Initial configuration. Must not be NULL.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] timer_event_handler Event handler provided by the user.
* Must not be NULL.
*
@ -161,6 +161,15 @@ void nrfx_timer_enable(nrfx_timer_t const * const p_instance);
*/
void nrfx_timer_disable(nrfx_timer_t const * const p_instance);
/**
* @brief Function for checking the timer state.
*
* @param[in] p_instance Pointer to the driver instance structure.
*
* @return True if timer is enabled, false otherwise.
*/
bool nrfx_timer_is_enabled(nrfx_timer_t const * const p_instance);
/**
* @brief Function for pausing the timer.
*

12
drivers/include/nrfx_twi.h
View file

@ -129,8 +129,8 @@ typedef struct
{
nrfx_twi_xfer_type_t type; ///< Type of transfer.
uint8_t address; ///< Slave address.
uint32_t primary_length; ///< Number of bytes transferred.
uint32_t secondary_length; ///< Number of bytes transferred.
size_t primary_length; ///< Number of bytes transferred.
size_t secondary_length; ///< Number of bytes transferred.
uint8_t * p_primary_buf; ///< Pointer to transferred data.
uint8_t * p_secondary_buf; ///< Pointer to transferred data.
} nrfx_twi_xfer_desc_t;
@ -195,7 +195,7 @@ typedef void (* nrfx_twi_evt_handler_t)(nrfx_twi_evt_t const * p_event,
* @brief Function for initializing the TWI driver instance.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled.
* @param[in] p_context Context passed to event handler.
*
@ -255,7 +255,7 @@ void nrfx_twi_disable(nrfx_twi_t const * p_instance);
nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance,
uint8_t address,
uint8_t const * p_data,
uint32_t length,
size_t length,
bool no_stop);
/**
@ -279,7 +279,7 @@ nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance,
nrfx_err_t nrfx_twi_rx(nrfx_twi_t const * p_instance,
uint8_t address,
uint8_t * p_data,
uint32_t length);
size_t length);
/**
* @brief Function for preparing a TWI transfer.
@ -333,7 +333,7 @@ bool nrfx_twi_is_busy(nrfx_twi_t const * p_instance);
*
* @return Data count.
*/
uint32_t nrfx_twi_data_count_get(nrfx_twi_t const * const p_instance);
size_t nrfx_twi_data_count_get(nrfx_twi_t const * const p_instance);
/**
* @brief Function for returning the address of a STOPPED TWI event.

20
drivers/include/nrfx_twim.h
View file

@ -133,8 +133,8 @@ typedef struct
{
nrfx_twim_xfer_type_t type; ///< Type of transfer.
uint8_t address; ///< Slave address.
uint8_t primary_length; ///< Number of bytes transferred.
uint8_t secondary_length; ///< Number of bytes transferred.
size_t primary_length; ///< Number of bytes transferred.
size_t secondary_length; ///< Number of bytes transferred.
uint8_t * p_primary_buf; ///< Pointer to transferred data.
uint8_t * p_secondary_buf; ///< Pointer to transferred data.
} nrfx_twim_xfer_desc_t;
@ -199,7 +199,7 @@ typedef void (* nrfx_twim_evt_handler_t)(nrfx_twim_evt_t const * p_event,
* @brief Function for initializing the TWI driver instance.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Event handler provided by the user. If NULL, blocking mode is enabled.
* @param[in] p_context Context passed to event handler.
*
@ -249,7 +249,10 @@ void nrfx_twim_disable(nrfx_twim_t const * p_instance);
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] address Address of a specific slave device (only 7 LSB).
* @param[in] p_data Pointer to a transmit buffer.
* @param[in] length Number of bytes to send.
* @param[in] length Number of bytes to send. Maximum possible length is
* dependent on the used SoC (see the MAXCNT register
* description in the Product Specification). The driver
* checks it with assertion.
* @param[in] no_stop If set, the stop condition is not generated on the bus
* after the transfer has completed successfully (allowing
* for a repeated start in the next transfer).
@ -264,7 +267,7 @@ void nrfx_twim_disable(nrfx_twim_t const * p_instance);
nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance,
uint8_t address,
uint8_t const * p_data,
uint8_t length,
size_t length,
bool no_stop);
/**
@ -276,7 +279,10 @@ nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance,
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] address Address of a specific slave device (only 7 LSB).
* @param[in] p_data Pointer to a receive buffer.
* @param[in] length Number of bytes to be received.
* @param[in] length Number of bytes to be received. Maximum possible length
* is dependent on the used SoC (see the MAXCNT register
* description in the Product Specification). The driver
* checks it with assertion.
*
* @retval NRFX_SUCCESS If the procedure was successful.
* @retval NRFX_ERROR_BUSY If the driver is not ready for a new transfer.
@ -287,7 +293,7 @@ nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance,
nrfx_err_t nrfx_twim_rx(nrfx_twim_t const * p_instance,
uint8_t address,
uint8_t * p_data,
uint8_t length);
size_t length);
/**
* @brief Function for preparing a TWI transfer.

2
drivers/include/nrfx_twis.h
View file

@ -171,7 +171,7 @@ typedef struct
* @attention @em p_instance has to be global object.
* It would be used by interrupts so make it sure that object
* would not be destroyed when function is leaving.
* @param[in] p_config Initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Event handler provided by the user.
*
* @retval NRFX_SUCCESS If initialization was successful.

10
drivers/include/nrfx_uart.h
View file

@ -58,9 +58,6 @@ typedef struct
enum {
#if NRFX_CHECK(NRFX_UART0_ENABLED)
NRFX_UART0_INST_IDX,
#endif
#if NRFX_CHECK(NRFX_UART1_ENABLED)
NRFX_UART1_INST_IDX,
#endif
NRFX_UART_ENABLED_COUNT
};
@ -163,7 +160,7 @@ typedef void (*nrfx_uart_event_handler_t)(nrfx_uart_event_t const * p_event,
* This function configures and enables UART. After this function GPIO pins are controlled by UART.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Event handler provided by the user. If not provided driver works in
* blocking mode.
*
@ -226,7 +223,7 @@ __STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_insta
*/
nrfx_err_t nrfx_uart_tx(nrfx_uart_t const * p_instance,
uint8_t const * p_data,
uint32_t length);
size_t length);
/**
* @brief Function for checking if UART is currently transmitting.
@ -275,7 +272,7 @@ void nrfx_uart_tx_abort(nrfx_uart_t const * p_instance);
*/
nrfx_err_t nrfx_uart_rx(nrfx_uart_t const * p_instance,
uint8_t * p_data,
uint32_t length);
size_t length);
@ -348,7 +345,6 @@ __STATIC_INLINE uint32_t nrfx_uart_event_address_get(nrfx_uart_t const * p_insta
void nrfx_uart_0_irq_handler(void);
void nrfx_uart_1_irq_handler(void);
/** @} */

16
drivers/include/nrfx_uarte.h
View file

@ -163,7 +163,7 @@ typedef void (*nrfx_uarte_event_handler_t)(nrfx_uarte_event_t const * p_event,
* This function configures and enables UARTE. After this function GPIO pins are controlled by UARTE.
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_config Initial configuration.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] event_handler Event handler provided by the user. If not provided driver works in
* blocking mode.
*
@ -221,7 +221,10 @@ __STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_ins
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_data Pointer to data.
* @param[in] length Number of bytes to send.
* @param[in] length Number of bytes to send. Maximum possible length is
* dependent on the used SoC (see the MAXCNT register
* description in the Product Specification). The driver
* checks it with assertion.
*
* @retval NRFX_SUCCESS If initialization was successful.
* @retval NRFX_ERROR_BUSY If driver is already transferring.
@ -231,7 +234,7 @@ __STATIC_INLINE uint32_t nrfx_uarte_event_address_get(nrfx_uarte_t const * p_ins
*/
nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance,
uint8_t const * p_data,
uint8_t length);
size_t length);
/**
* @brief Function for checking if UARTE is currently transmitting.
@ -272,7 +275,10 @@ void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance);
*
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_data Pointer to data.
* @param[in] length Number of bytes to receive.
* @param[in] length Number of bytes to receive. Maximum possible length is
* dependent on the used SoC (see the MAXCNT register
* description in the Product Specification). The driver
* checks it with assertion.
*
* @retval NRFX_SUCCESS If initialization was successful.
* @retval NRFX_ERROR_BUSY If the driver is already receiving
@ -285,7 +291,7 @@ void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance);
*/
nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance,
uint8_t * p_data,
uint8_t length);
size_t length);

2
drivers/include/nrfx_wdt.h
View file

@ -69,7 +69,7 @@ typedef nrf_wdt_rr_register_t nrfx_wdt_channel_id;
/**
* @brief This function initializes watchdog.
*
* @param[in] p_config Initial configuration. Default configuration used if NULL.
* @param[in] p_config Pointer to the structure with initial configuration.
* @param[in] wdt_event_handler specifies event handler provided by user.
*
* @note Function asserts if wdt_event_handler is NULL.

13
drivers/nrfx_common.h
View file

@ -117,6 +117,19 @@ extern "C" {
*/
#define NRFX_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b))
/**@brief Macro for checking if given lengths of EasyDMA transfers do not exceed
* the limit of the specified peripheral.
*
* @param peripheral Peripheral to check the lengths against.
* @param length1 First length to be checked.
* @param length2 Second length to be checked (pass 0 if not needed).
*
* @return
*/
#define NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, length1, length2) \
(((length1) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE))) && \
((length2) < (1U << NRFX_CONCAT_2(peripheral, _EASYDMA_MAXCNT_SIZE))))
/**
* @brief IRQ handler type.

6
drivers/src/nrfx_adc.c
View file

@ -52,11 +52,11 @@ typedef struct
} adc_cb_t;
static adc_cb_t m_cb;
static const nrfx_adc_config_t m_default_config = NRFX_ADC_DEFAULT_CONFIG;
nrfx_err_t nrfx_adc_init(nrfx_adc_config_t const * p_config,
nrfx_adc_event_handler_t event_handler)
{
NRFX_ASSERT(p_config);
nrfx_err_t err_code;
if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
@ -71,10 +71,6 @@ nrfx_err_t nrfx_adc_init(nrfx_adc_config_t const * p_config,
nrf_adc_event_clear(NRF_ADC_EVENT_END);
if (event_handler)
{
if (!p_config)
{
p_config = (nrfx_adc_config_t *)&m_default_config;
}
NRFX_IRQ_PRIORITY_SET(ADC_IRQn, p_config->interrupt_priority);
NRFX_IRQ_ENABLE(ADC_IRQn);
}

50
drivers/src/nrfx_clock.c
View file

@ -88,6 +88,51 @@ static nrfx_clock_cb_t m_clock_cb;
bool nrfx_clock_irq_enabled;
#endif
#ifdef NRF52832_XXAA
// ANOMALY 132 - LFCLK needs to avoid frame from 66us to 138us after LFCLK stop. This solution
// applies delay of 138us before starting LFCLK.
#define ANOMALY_132_REQ_DELAY_US 138UL
// nRF52832 is clocked with 64MHz.
#define ANOMALY_132_NRF52832_FREQ_MHZ 64UL
// Convert time to cycles.
#define ANOMALY_132_DELAY_CYCLES (ANOMALY_132_REQ_DELAY_US * ANOMALY_132_NRF52832_FREQ_MHZ)
/**
* @brief Function for applying delay of 138us before starting LFCLK.
*/
static void nrfx_clock_anomaly_132(void)
{
uint32_t cyccnt_inital;
uint32_t core_debug;
uint32_t dwt_ctrl;
// Preserve DEMCR register to do not influence into its configuration. Enable the trace and
// debug blocks. It is required to read and write data to DWT block.
core_debug = CoreDebug->DEMCR;
CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk;
// Preserve CTRL register in DWT block to do not influence into its configuration. Make sure
// that cycle counter is enabled.
dwt_ctrl = DWT->CTRL;
DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk;
// Store start value of cycle counter.
cyccnt_inital = DWT->CYCCNT;
// Delay required time.
while ((DWT->CYCCNT - cyccnt_inital) < ANOMALY_132_DELAY_CYCLES)
{}
// Restore preserved registers.
DWT->CTRL = dwt_ctrl;
CoreDebug->DEMCR = core_debug;
}
#endif // NRF52832_XXAA
nrfx_err_t nrfx_clock_init(nrfx_clock_event_handler_t event_handler)
{
nrfx_err_t err_code = NRFX_SUCCESS;
@ -155,6 +200,11 @@ void nrfx_clock_lfclk_start(void)
NRFX_ASSERT(m_clock_cb.module_initialized);
nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED);
nrf_clock_int_enable(NRF_CLOCK_INT_LF_STARTED_MASK);
#ifdef NRF52832_XXAA
nrfx_clock_anomaly_132();
#endif
nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTART);
}

10
drivers/src/nrfx_comp.c
View file

@ -50,8 +50,6 @@
static nrfx_comp_event_handler_t m_comp_event_handler = NULL;
static nrfx_drv_state_t m_state = NRFX_DRV_STATE_UNINITIALIZED;
static nrfx_comp_config_t const m_default_config = NRFX_COMP_DEFAULT_CONFIG(NRF_COMP_INPUT_0);
static void comp_execute_handler(nrf_comp_event_t event, uint32_t event_mask)
{
if (nrf_comp_event_check(event) && nrf_comp_int_enable_check(event_mask))
@ -75,6 +73,7 @@ void nrfx_comp_irq_handler(void)
nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config,
nrfx_comp_event_handler_t event_handler)
{
NRFX_ASSERT(p_config);
nrfx_err_t err_code;
if (m_state != NRFX_DRV_STATE_UNINITIALIZED)
@ -86,11 +85,6 @@ nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config,
return err_code;
}
if (p_config == NULL)
{
p_config = &m_default_config;
}
if (event_handler)
{
m_comp_event_handler = event_handler;
@ -136,7 +130,9 @@ nrfx_err_t nrfx_comp_init(nrfx_comp_config_t const * p_config,
nrf_comp_main_mode_set(p_config->main_mode);
nrf_comp_speed_mode_set(p_config->speed_mode);
nrf_comp_hysteresis_set(p_config->hyst);
#if defined (COMP_ISOURCE_ISOURCE_Msk)
nrf_comp_isource_set(p_config->isource);
#endif
nrf_comp_shorts_disable(NRFX_COMP_SHORT_STOP_AFTER_CROSS_EVT |
NRFX_COMP_SHORT_STOP_AFTER_UP_EVT |
NRFX_COMP_SHORT_STOP_AFTER_DOWN_EVT);

10
drivers/src/nrfx_i2s.c
View file

@ -62,10 +62,6 @@ typedef struct
} i2s_control_block_t;
static i2s_control_block_t m_cb;
static nrfx_i2s_config_t const m_default_config = NRFX_I2S_DEFAULT_CONFIG;
static void configure_pins(nrfx_i2s_config_t const * p_config)
{
uint32_t mck_pin, sdout_pin, sdin_pin;
@ -127,6 +123,7 @@ static void configure_pins(nrfx_i2s_config_t const * p_config)
nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config,
nrfx_i2s_data_handler_t handler)
{
NRFX_ASSERT(p_config);
NRFX_ASSERT(handler);
nrfx_err_t err_code;
@ -140,11 +137,6 @@ nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config,
return err_code;
}
if (p_config == NULL)
{
p_config = &m_default_config;
}
if (!nrf_i2s_configure(NRF_I2S, p_config->mode,
p_config->format,
p_config->alignment,

4
drivers/src/nrfx_pdm.c
View file

@ -170,6 +170,7 @@ void nrfx_pdm_irq_handler(void)
nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config,
nrfx_pdm_event_handler_t event_handler)
{
NRFX_ASSERT(p_config);
nrfx_err_t err_code;
if (m_cb.drv_state != NRFX_DRV_STATE_UNINITIALIZED)
@ -180,7 +181,7 @@ nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config,
NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
}
if ((p_config == NULL) || (event_handler == NULL))
if (event_handler == NULL)
{
err_code = NRFX_ERROR_INVALID_PARAM;
NRFX_LOG_WARNING("Function: %s, error code: %s.",
@ -188,6 +189,7 @@ nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config,
NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
}
if (p_config->gain_l > NRF_PDM_GAIN_MAXIMUM ||
p_config->gain_r > NRF_PDM_GAIN_MAXIMUM)
{

23
drivers/src/nrfx_power.c
View file

@ -48,21 +48,6 @@ extern bool nrfx_clock_irq_enabled;
* @{
*/
/**
* @brief Default configuration
*
* The structure with default configuration data.
* This structure would be used if configuration pointer given
* to the @ref nrfx_power_init is set to NULL.
*/
static const nrfx_power_config_t m_drv_power_config_default =
{
.dcdcen = NRFX_POWER_CONFIG_DEFAULT_DCDCEN,
#if NRF_POWER_HAS_VDDH || defined(__NRFX_DOXYGEN__)
.dcdcenhv = NRFX_POWER_CONFIG_DEFAULT_DCDCENHV,
#endif
};
/**
* This variable is used to check whether common POWER_CLOCK common interrupt
* should be disabled or not if @ref nrfx_clock tries to disable the interrupt.
@ -111,18 +96,16 @@ nrfx_power_usb_event_handler_t nrfx_power_usb_handler_get(void)
nrfx_err_t nrfx_power_init(nrfx_power_config_t const * p_config)
{
nrfx_power_config_t const * p_used_config;
NRFX_ASSERT(p_config);
if (m_initialized)
{
return NRFX_ERROR_ALREADY_INITIALIZED;
}
p_used_config = (p_config != NULL) ?
p_config : (&m_drv_power_config_default);
#if NRF_POWER_HAS_VDDH
nrf_power_dcdcen_vddh_set(p_used_config->dcdcenhv);
nrf_power_dcdcen_vddh_set(p_config->dcdcenhv);
#endif
nrf_power_dcdcen_set(p_used_config->dcdcen);
nrf_power_dcdcen_set(p_config->dcdcen);
nrfx_power_clock_irq_init();

20
drivers/src/nrfx_pwm.c
View file

@ -300,10 +300,10 @@ uint32_t nrfx_pwm_simple_playback(nrfx_pwm_t const * const p_instance,
NRFX_LOG_INFO("Function: %s, sequence length: %d.",
__func__,
p_sequence->length * sizeof(p_sequence->values));
p_sequence->length);
NRFX_LOG_DEBUG("Sequence data:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_sequence->values.p_raw,
p_sequence->length * sizeof(p_sequence->values));
p_sequence->length * sizeof(uint16_t));
return start_playback(p_instance, p_cb, flags,
odd ? NRF_PWM_TASK_SEQSTART1 : NRF_PWM_TASK_SEQSTART0);
}
@ -341,17 +341,17 @@ uint32_t nrfx_pwm_complex_playback(nrfx_pwm_t const * const p_instance,
nrf_pwm_shorts_set(p_instance->p_registers, shorts_mask);
NRFX_LOG_INFO("Function: %s, sequence 0 length: %d.",
__func__,
p_sequence_0->length * sizeof(p_sequence_0->values));
__func__,
p_sequence_0->length);
NRFX_LOG_INFO("Function: %s, sequence 1 length: %d.",
__func__,
p_sequence_1->length * sizeof(p_sequence_1->values));
__func__,
p_sequence_1->length);
NRFX_LOG_DEBUG("Sequence 0 data:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_sequence_0->values.p_raw,
p_sequence_0->length * sizeof(p_sequence_0->values));
NRFX_LOG_HEXDUMP_DEBUG(p_sequence_0->values.p_raw,
p_sequence_0->length * sizeof(uint16_t));
NRFX_LOG_DEBUG("Sequence 1 data:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_sequence_1->values.p_raw,
p_sequence_1->length * sizeof(p_sequence_1->values));
NRFX_LOG_HEXDUMP_DEBUG(p_sequence_1->values.p_raw,
p_sequence_1->length * sizeof(uint16_t));
return start_playback(p_instance, p_cb, flags, NRF_PWM_TASK_SEQSTART0);
}

11
drivers/src/nrfx_qdec.c
View file

@ -91,6 +91,7 @@ void nrfx_qdec_irq_handler(void)
nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config,
nrfx_qdec_event_handler_t event_handler)
{
NRFX_ASSERT(p_config);
nrfx_err_t err_code;
if (m_state != NRFX_DRV_STATE_UNINITIALIZED)
@ -102,12 +103,6 @@ nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config,
return err_code;
}
if (p_config == NULL)
{
static nrfx_qdec_config_t const default_config = NRFX_QDEC_DEFAULT_CONFIG;
p_config = &default_config;
}
if (event_handler)
{
m_qdec_event_handler = event_handler;
@ -199,9 +194,9 @@ void nrfx_qdec_accumulators_read(int16_t * p_acc, int16_t * p_accdbl)
*p_accdbl = (int16_t)nrf_qdec_accdblread_get();
NRFX_LOG_DEBUG("Accumulators data, ACC register:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_acc, sizeof(p_acc));
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_acc, sizeof(p_acc[0]));
NRFX_LOG_DEBUG("Accumulators data, ACCDBL register:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_accdbl, sizeof(p_accdbl));
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_accdbl, sizeof(p_accdbl[0]));
}
#endif // NRFX_CHECK(NRFX_QDEC_ENABLED)

2
drivers/src/nrfx_qspi.c
View file

@ -110,6 +110,7 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config,
nrfx_qspi_handler_t handler,
void * p_context)
{
NRFX_ASSERT(p_config);
if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
{
return NRFX_ERROR_INVALID_STATE;
@ -120,6 +121,7 @@ nrfx_err_t nrfx_qspi_init(nrfx_qspi_config_t const * p_config,
return NRFX_ERROR_INVALID_PARAM;
}
nrf_qspi_xip_offset_set(NRF_QSPI, p_config->xip_offset);
nrf_qspi_ifconfig0_set(NRF_QSPI, &p_config->prot_if);
nrf_qspi_ifconfig1_set(NRF_QSPI, &p_config->phy_if);

4
drivers/src/nrfx_rng.c
View file

@ -50,15 +50,17 @@ static nrfx_rng_evt_handler_t m_rng_hndl;
nrfx_err_t nrfx_rng_init(nrfx_rng_config_t const * p_config, nrfx_rng_evt_handler_t handler)
{
NRFX_ASSERT(p_config);
if (m_rng_state != NRFX_DRV_STATE_UNINITIALIZED)
{
return NRFX_ERROR_ALREADY_INITIALIZED;
}
if ((handler == NULL) || (p_config == NULL))
if (handler == NULL)
{
return NRFX_ERROR_INVALID_PARAM;
}
m_rng_hndl = handler;
if (p_config->error_correction)

2
drivers/src/nrfx_rtc.c
View file

@ -69,7 +69,7 @@ nrfx_err_t nrfx_rtc_init(nrfx_rtc_t const * const p_instance,
nrfx_rtc_config_t const * p_config,
nrfx_rtc_handler_t handler)
{
NRFX_ASSERT(p_config != NULL);
NRFX_ASSERT(p_config);
nrfx_err_t err_code;

17
drivers/src/nrfx_saadc.c
View file

@ -45,11 +45,6 @@
(event == NRF_SAADC_EVENT_STOPPED ? "NRF_SAADC_EVENT_STOPPED" : \
"UNKNOWN EVENT"))))))
#define EVT_TO_STR_LIMIT(event) \
(event == NRF_SAADC_LIMIT_LOW ? "NRF_SAADC_LIMIT_LOW" : \
(event == NRF_SAADC_LIMIT_HIGH ? "NRF_SAADC_LIMIT_HIGH" : \
"UNKNOWN EVENT"))
typedef enum
{
@ -65,8 +60,6 @@ typedef struct
nrf_saadc_input_t pseln;
} nrf_saadc_psel_buffer;
static const nrfx_saadc_config_t m_default_config = NRFX_SAADC_DEFAULT_CONFIG;
/** @brief SAADC control block.*/
typedef struct
{
@ -196,9 +189,9 @@ void nrfx_saadc_irq_handler(void)
evt.type = NRFX_SAADC_EVT_LIMIT;
evt.data.limit.channel = LIMIT_EVENT_TO_CHANNEL(event);
evt.data.limit.limit_type = LIMIT_EVENT_TO_LIMIT_TYPE(event);
NRFX_LOG_DEBUG("Event limit, channel: %d, limit type: %s.",
NRFX_LOG_DEBUG("Event limit, channel: %d, limit type: %d.",
evt.data.limit.channel,
EVT_TO_STR_LIMIT(evt.data.limit.limit_type));
evt.data.limit.limit_type);
m_cb.event_handler(&evt);
}
}
@ -209,6 +202,7 @@ void nrfx_saadc_irq_handler(void)
nrfx_err_t nrfx_saadc_init(nrfx_saadc_config_t const * p_config,
nrfx_saadc_event_handler_t event_handler)
{
NRFX_ASSERT(p_config);
nrfx_err_t err_code;
if (m_cb.state != NRFX_DRV_STATE_UNINITIALIZED)
@ -228,11 +222,6 @@ nrfx_err_t nrfx_saadc_init(nrfx_saadc_config_t const * p_config,
return err_code;
}
if (p_config == NULL)
{
p_config = &m_default_config;
}
m_cb.event_handler = event_handler;
nrf_saadc_resolution_set(p_config->resolution);
nrf_saadc_oversample_set(p_config->oversample);

23
drivers/src/nrfx_spi.c
View file

@ -58,7 +58,7 @@ typedef struct
// are not concurrently used in IRQ handlers and main line code]
uint8_t ss_pin;
uint8_t orc;
uint32_t bytes_transferred;
size_t bytes_transferred;
bool abort;
} spi_control_block_t;
@ -145,7 +145,7 @@ nrfx_err_t nrfx_spi_init(nrfx_spi_t const * const p_instance,
if (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED)
{
miso_pin = p_config->miso_pin;
nrf_gpio_cfg_input(miso_pin, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(miso_pin, (nrf_gpio_pin_pull_t)NRFX_SPI_MISO_PULL_CFG);
}
else
{
@ -254,9 +254,8 @@ static bool transfer_byte(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb)
// NOTE - we've already used 'p_cb->bytes_transferred + 1' bytes from our
// buffers, because we take advantage of double buffering of TXD
// register (so in effect one byte is still being transmitted now);
// see how the transfer is started in the 'nrfx_spi_transfer'
// function.
uint32_t bytes_used = p_cb->bytes_transferred + 1;
// see how the transfer is started in the 'spi_xfer' function.
size_t bytes_used = p_cb->bytes_transferred + 1;
if (p_cb->abort)
{
@ -385,20 +384,6 @@ nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * const p_instance,
return err_code;
}
nrfx_err_t nrfx_spi_transfer(nrfx_spi_t const * const p_instance,
uint8_t const * p_tx_buffer,
uint32_t tx_buffer_length,
uint8_t * p_rx_buffer,
uint32_t rx_buffer_length)
{
nrfx_spi_xfer_desc_t xfer_desc;
xfer_desc.p_tx_buffer = p_tx_buffer;
xfer_desc.p_rx_buffer = p_rx_buffer;
xfer_desc.tx_length = tx_buffer_length;
xfer_desc.rx_length = rx_buffer_length;
return nrfx_spi_xfer(p_instance, &xfer_desc, 0);
}
void nrfx_spi_abort(nrfx_spi_t const * p_instance)
{
spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];

191
drivers/src/nrfx_spim.c
View file

@ -34,8 +34,12 @@
#if NRFX_CHECK(NRFX_SPIM_ENABLED)
#if !(NRFX_CHECK(NRFX_SPIM0_ENABLED) || NRFX_CHECK(NRFX_SPIM1_ENABLED) || \
NRFX_CHECK(NRFX_SPIM2_ENABLED))
#error "No enabled SPI instances. Check <nrfx_config.h>."
NRFX_CHECK(NRFX_SPIM2_ENABLED) || NRFX_CHECK(NRFX_SPIM3_ENABLED))
#error "No enabled SPIM instances. Check <nrfx_config.h>."
#endif
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) && !NRFX_CHECK(NRFX_SPIM3_ENABLED)
#error "Extended options are available only in SPIM3 on the nRF52840 SoC."
#endif
#include <nrfx_spim.h>
@ -45,6 +49,41 @@
#define NRFX_LOG_MODULE SPIM
#include <nrfx_log.h>
#define SPIMX_LENGTH_VALIDATE(peripheral, drv_inst_idx, rx_len, tx_len) \
(((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \
NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, rx_len, tx_len))
#if NRFX_CHECK(NRFX_SPIM0_ENABLED)
#define SPIM0_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM0, __VA_ARGS__)
#else
#define SPIM0_LENGTH_VALIDATE(...) 0
#endif
#if NRFX_CHECK(NRFX_SPIM1_ENABLED)
#define SPIM1_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM1, __VA_ARGS__)
#else
#define SPIM1_LENGTH_VALIDATE(...) 0
#endif
#if NRFX_CHECK(NRFX_SPIM2_ENABLED)
#define SPIM2_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM2, __VA_ARGS__)
#else
#define SPIM2_LENGTH_VALIDATE(...) 0
#endif
#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
#define SPIM3_LENGTH_VALIDATE(...) SPIMX_LENGTH_VALIDATE(SPIM3, __VA_ARGS__)
#else
#define SPIM3_LENGTH_VALIDATE(...) 0
#endif
#define SPIM_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) \
(SPIM0_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
SPIM1_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
SPIM2_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
SPIM3_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len))
// Control block - driver instance local data.
typedef struct
{
@ -54,20 +93,23 @@ typedef struct
nrfx_drv_state_t state;
volatile bool transfer_in_progress;
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
bool use_hw_ss;
#endif
// [no need for 'volatile' attribute for the following members, as they
// are not concurrently used in IRQ handlers and main line code]
bool ss_active_high;
uint8_t ss_pin;
uint8_t orc;
uint8_t bytes_transferred;
#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
uint8_t tx_length;
uint8_t rx_length;
size_t tx_length;
size_t rx_length;
#endif
} spim_control_block_t;
static spim_control_block_t m_cb[NRFX_SPIM_ENABLED_COUNT];
nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
nrfx_spim_config_t const * p_config,
nrfx_spim_evt_handler_t handler,
@ -86,6 +128,26 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
return err_code;
}
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
// Currently, only SPIM3 in nRF52840 supports the extended features. Other instances must be checked.
if ((p_instance->drv_inst_idx != NRFX_SPIM3_INST_IDX) &&
((p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED) ||
(p_config->frequency == NRF_SPIM_FREQ_16M) ||
(p_config->frequency == NRF_SPIM_FREQ_32M) ||
(p_config->rx_delay != 0x00) ||
(p_config->use_hw_ss)))
{
err_code = NRFX_ERROR_NOT_SUPPORTED;
NRFX_LOG_WARNING("Function: %s, error code: %s.",
__func__,
NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
}
#endif
NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
#if NRFX_CHECK(NRFX_PRS_ENABLED)
static nrfx_irq_handler_t const irq_handlers[NRFX_SPIM_ENABLED_COUNT] = {
#if NRFX_CHECK(NRFX_SPIM0_ENABLED)
@ -97,6 +159,9 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
#if NRFX_CHECK(NRFX_SPIM2_ENABLED)
nrfx_spim_2_irq_handler,
#endif
#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
nrfx_spim_3_irq_handler,
#endif
};
if (nrfx_prs_acquire(p_instance->p_reg,
irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS)
@ -119,7 +184,7 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
// 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1);
// according to the reference manual guidelines this pin and its input
// buffer must always be connected for the SPI to work.
if (p_config->mode <= NRFX_SPIM_MODE_1)
if (p_config->mode <= NRF_SPIM_MODE_1)
{
nrf_gpio_pin_clear(p_config->sck_pin);
}
@ -148,7 +213,7 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
if (p_config->miso_pin != NRFX_SPIM_PIN_NOT_USED)
{
miso_pin = p_config->miso_pin;
nrf_gpio_cfg_input(miso_pin, NRF_GPIO_PIN_NOPULL);
nrf_gpio_cfg_input(miso_pin, (nrf_gpio_pin_pull_t)NRFX_SPIM_MISO_PULL_CFG);
}
else
{
@ -157,12 +222,44 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * const p_instance,
// - Slave Select (optional) - output with initial value 1 (inactive).
if (p_config->ss_pin != NRFX_SPIM_PIN_NOT_USED)
{
nrf_gpio_pin_set(p_config->ss_pin);
if (p_config->ss_active_high)
{
nrf_gpio_pin_clear(p_config->ss_pin);
}
else
{
nrf_gpio_pin_set(p_config->ss_pin);
}
nrf_gpio_cfg_output(p_config->ss_pin);
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
if (p_config->use_hw_ss)
{
m_cb[p_instance->drv_inst_idx].use_hw_ss = p_config->use_hw_ss;
nrf_spim_csn_configure(p_spim,
p_config->ss_pin,
(p_config->ss_active_high == true ?
NRF_SPIM_CSN_POL_HIGH : NRF_SPIM_CSN_POL_LOW),
p_config->ss_duration);
}
#endif
m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin;
m_cb[p_instance->drv_inst_idx].ss_active_high = p_config->ss_active_high;
}
m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin;
NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
// - DCX (optional) - output.
if (p_config->dcx_pin != NRFX_SPIM_PIN_NOT_USED)
{
nrf_gpio_pin_set(p_config->dcx_pin);
nrf_gpio_cfg_output(p_config->dcx_pin);
nrf_spim_dcx_pin_set(p_spim, p_config->dcx_pin);
}
// Change rx delay
nrf_spim_iftiming_set(p_spim, p_config->rx_delay);
#endif
nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin);
nrf_spim_frequency_set(p_spim,
(nrf_spim_frequency_t)p_config->frequency);
@ -226,26 +323,36 @@ void nrfx_spim_uninit(nrfx_spim_t const * const p_instance)
p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
}
nrfx_err_t nrfx_spim_transfer(nrfx_spim_t const * const p_instance,
uint8_t const * p_tx_buffer,
uint8_t tx_buffer_length,
uint8_t * p_rx_buffer,
uint8_t rx_buffer_length)
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
nrfx_err_t nrfx_spim_xfer_dcx(nrfx_spim_t const * const p_instance,
nrfx_spim_xfer_desc_t const * p_xfer_desc,
uint32_t flags,
uint8_t cmd_length)
{
nrfx_spim_xfer_desc_t xfer_desc;
xfer_desc.p_tx_buffer = p_tx_buffer;
xfer_desc.p_rx_buffer = p_rx_buffer;
xfer_desc.tx_length = tx_buffer_length;
xfer_desc.rx_length = rx_buffer_length;
return nrfx_spim_xfer(p_instance, &xfer_desc, 0);
ASSERT(cmd_length <= NRF_SPIM_DCX_CNT_ALL_CMD)
nrf_spim_dcx_cnt_set((NRF_SPIM_Type *)p_instance->p_reg, cmd_length);
return nrfx_spim_xfer(p_instance, p_xfer_desc, 0);
}
#endif
static void finish_transfer(spim_control_block_t * p_cb)
{
// If Slave Select signal is used, this is the time to deactivate it.
if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
{
nrf_gpio_pin_set(p_cb->ss_pin);
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
if (!p_cb->use_hw_ss)
#endif
{
if (p_cb->ss_active_high)
{
nrf_gpio_pin_clear(p_cb->ss_pin);
}
else
{
nrf_gpio_pin_set(p_cb->ss_pin);
}
}
}
// By clearing this flag before calling the handler we allow subsequent
@ -341,7 +448,19 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim,
while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)){}
if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
{
nrf_gpio_pin_set(p_cb->ss_pin);
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
if (!p_cb->use_hw_ss)
#endif
{
if (p_cb->ss_active_high)
{
nrf_gpio_pin_clear(p_cb->ss_pin);
}
else
{
nrf_gpio_pin_set(p_cb->ss_pin);
}
}
}
}
else
@ -361,6 +480,9 @@ nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance,
NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
NRFX_ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0);
NRFX_ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0);
NRFX_ASSERT(SPIM_LENGTH_VALIDATE(p_instance->drv_inst_idx,
p_xfer_desc->rx_length,
p_xfer_desc->tx_length));
nrfx_err_t err_code = NRFX_SUCCESS;
@ -385,7 +507,19 @@ nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * const p_instance,
if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
{
nrf_gpio_pin_clear(p_cb->ss_pin);
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
if (!p_cb->use_hw_ss)
#endif
{
if (p_cb->ss_active_high)
{
nrf_gpio_pin_set(p_cb->ss_pin);
}
else
{
nrf_gpio_pin_clear(p_cb->ss_pin);
}
}
}
return spim_xfer(p_instance->p_reg, p_cb, p_xfer_desc, flags);
@ -470,4 +604,11 @@ void nrfx_spim_2_irq_handler(void)
}
#endif
#if NRFX_CHECK(NRFX_SPIM3_ENABLED)
void nrfx_spim_3_irq_handler(void)
{
irq_handler(NRF_SPIM3, &m_cb[NRFX_SPIM3_INST_IDX]);
}
#endif
#endif // NRFX_CHECK(NRFX_SPIM_ENABLED)

50
drivers/src/nrfx_spis.c
View file

@ -44,11 +44,45 @@
#define NRFX_LOG_MODULE SPIS
#include <nrfx_log.h>
#if defined(NRF51) && !defined(SPIS1_EASYDMA_MAXCNT_SIZE)
/* MDK comes with SPIS0 definition of maximum transmission length but nRF51 Series is equipped
* with SPIS1 only. It is a simple workaround and will be removed in the next release of the MDK.
*/
#define SPIS1_EASYDMA_MAXCNT_SIZE SPIS0_EASYDMA_MAXCNT_SIZE
#endif
#define EVT_TO_STR(event) \
(event == NRF_SPIS_EVENT_ACQUIRED ? "NRF_SPIS_EVENT_ACQUIRED" : \
(event == NRF_SPIS_EVENT_END ? "NRF_SPIS_EVENT_END" : \
"UNKNOWN ERROR"))
#define SPISX_LENGTH_VALIDATE(peripheral, drv_inst_idx, rx_len, tx_len) \
(((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \
NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, rx_len, tx_len))
#if NRFX_CHECK(NRFX_SPIS0_ENABLED)
#define SPIS0_LENGTH_VALIDATE(...) SPISX_LENGTH_VALIDATE(SPIS0, __VA_ARGS__)
#else
#define SPIS0_LENGTH_VALIDATE(...) 0
#endif
#if NRFX_CHECK(NRFX_SPIS1_ENABLED)
#define SPIS1_LENGTH_VALIDATE(...) SPISX_LENGTH_VALIDATE(SPIS1, __VA_ARGS__)
#else
#define SPIS1_LENGTH_VALIDATE(...) 0
#endif
#if NRFX_CHECK(NRFX_SPIS2_ENABLED)
#define SPIS2_LENGTH_VALIDATE(...) SPISX_LENGTH_VALIDATE(SPIS2, __VA_ARGS__)
#else
#define SPIS2_LENGTH_VALIDATE(...) 0
#endif
#define SPIS_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) \
(SPIS0_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
SPIS1_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len) || \
SPIS2_LENGTH_VALIDATE(drv_inst_idx, rx_len, tx_len))
#if NRFX_CHECK(NRFX_SPIS_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
#include <nrfx_gpiote.h>
@ -308,8 +342,8 @@ static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis,
event.tx_amount = nrf_spis_tx_amount_get(p_spis);
NRFX_LOG_INFO("Transfer rx_len:%d.", event.rx_amount);
NRFX_LOG_DEBUG("Rx data:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_cb->rx_buffer,
event.rx_amount * sizeof(p_cb->rx_buffer));
NRFX_LOG_HEXDUMP_DEBUG((uint8_t const *)p_cb->rx_buffer,
event.rx_amount * sizeof(p_cb->rx_buffer[0]));
NRFX_ASSERT(p_cb->handler != NULL);
p_cb->handler(event);
break;
@ -334,12 +368,11 @@ static void spis_state_change(NRF_SPIS_Type * p_spis,
spis_state_entry_action_execute(p_spis, p_cb);
}
nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance,
uint8_t const * p_tx_buffer,
uint8_t tx_buffer_length,
size_t tx_buffer_length,
uint8_t * p_rx_buffer,
uint8_t rx_buffer_length)
size_t rx_buffer_length)
{
spis_cb_t * p_cb = &m_cb[p_instance->drv_inst_idx];
nrfx_err_t err_code;
@ -349,6 +382,13 @@ nrfx_err_t nrfx_spis_buffers_set(nrfx_spis_t const * const p_instance,
return NRFX_ERROR_NULL;
}
if (!SPIS_LENGTH_VALIDATE(p_instance->drv_inst_idx,
rx_buffer_length,
tx_buffer_length))
{
return NRFX_ERROR_INVALID_LENGTH;
}
// EasyDMA requires that transfer buffers are placed in Data RAM region;
// signal error if they are not.
if ((p_tx_buffer != NULL && !nrfx_is_in_ram(p_tx_buffer)) ||

9
drivers/src/nrfx_timer.c
View file

@ -156,6 +156,12 @@ void nrfx_timer_disable(nrfx_timer_t const * const p_instance)
NRFX_LOG_INFO("Disabled instance: %d.", p_instance->instance_id);
}
bool nrfx_timer_is_enabled(nrfx_timer_t const * const p_instance)
{
NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED);
return (m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_POWERED_ON);
}
void nrfx_timer_resume(nrfx_timer_t const * const p_instance)
{
NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_POWERED_ON);
@ -187,7 +193,7 @@ void nrfx_timer_increment(nrfx_timer_t const * const p_instance)
uint32_t nrfx_timer_capture(nrfx_timer_t const * const p_instance,
nrf_timer_cc_channel_t cc_channel)
{
NRFX_ASSERT(m_cb[p_instance->instance_id].state == NRFX_DRV_STATE_POWERED_ON);
NRFX_ASSERT(m_cb[p_instance->instance_id].state != NRFX_DRV_STATE_UNINITIALIZED);
NRFX_ASSERT(cc_channel < p_instance->cc_channel_count);
nrf_timer_task_trigger(p_instance->p_reg,
@ -204,6 +210,7 @@ void nrfx_timer_compare(nrfx_timer_t const * const p_instance,
if (enable_int)
{
nrf_timer_event_clear(p_instance->p_reg, nrf_timer_compare_event_get(cc_channel));
nrf_timer_int_enable(p_instance->p_reg, timer_int);
}
else

84
drivers/src/nrfx_twi.c
View file

@ -38,6 +38,7 @@
#endif
#include <nrfx_twi.h>
#include <hal/nrf_gpio.h>
#include "prs/nrfx_prs.h"
#define NRFX_LOG_MODULE TWI
@ -65,53 +66,32 @@
(type == NRFX_TWI_XFER_TXTX ? "XFER_TXTX" : \
"UNKNOWN TRANSFER TYPE"))))
#define SCL_PIN_INIT_CONF \
( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos))
#define SDA_PIN_INIT_CONF SCL_PIN_INIT_CONF
#define SDA_PIN_UNINIT_CONF \
( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos))
#define SCL_PIN_UNINIT_CONF SDA_PIN_UNINIT_CONF
#define SCL_PIN_INIT_CONF_CLR \
( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos))
#define SDA_PIN_INIT_CONF_CLR SCL_PIN_INIT_CONF_CLR
#define TWI_PIN_INIT(_pin) nrf_gpio_cfg((_pin), \
NRF_GPIO_PIN_DIR_INPUT, \
NRF_GPIO_PIN_INPUT_CONNECT, \
NRF_GPIO_PIN_PULLUP, \
NRF_GPIO_PIN_S0D1, \
NRF_GPIO_PIN_NOSENSE)
#define HW_TIMEOUT 10000
// Control block - driver instance local data.
typedef struct
{
nrfx_twi_evt_handler_t handler;
void * p_context;
volatile uint32_t int_mask;
nrfx_twi_xfer_desc_t xfer_desc;
uint32_t flags;
uint8_t * p_curr_buf;
uint8_t curr_length;
bool curr_no_stop;
nrfx_drv_state_t state;
bool error;
volatile bool busy;
bool repeated;
uint8_t bytes_transferred;
bool hold_bus_uninit;
nrfx_twi_evt_handler_t handler;
void * p_context;
volatile uint32_t int_mask;
nrfx_twi_xfer_desc_t xfer_desc;
uint32_t flags;
uint8_t * p_curr_buf;
uint8_t curr_length;
bool curr_no_stop;
nrfx_drv_state_t state;
bool error;
volatile bool busy;
bool repeated;
uint8_t bytes_transferred;
bool hold_bus_uninit;
} twi_control_block_t;
static twi_control_block_t m_cb[NRFX_TWI_ENABLED_COUNT];
@ -190,8 +170,8 @@ nrfx_err_t nrfx_twi_init(nrfx_twi_t const * p_instance,
master when the system is in OFF mode, and when the TWI master is
disabled, these pins must be configured in the GPIO peripheral.
*/
NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_INIT_CONF;
NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_INIT_CONF;
TWI_PIN_INIT(p_config->scl);
TWI_PIN_INIT(p_config->sda);
NRF_TWI_Type * p_twi = p_instance->p_twi;
nrf_twi_pins_set(p_twi, p_config->scl, p_config->sda);
@ -229,8 +209,8 @@ void nrfx_twi_uninit(nrfx_twi_t const * p_instance)
if (!p_cb->hold_bus_uninit)
{
NRF_GPIO->PIN_CNF[p_instance->p_twi->PSELSCL] = SCL_PIN_UNINIT_CONF;
NRF_GPIO->PIN_CNF[p_instance->p_twi->PSELSDA] = SDA_PIN_UNINIT_CONF;
nrf_gpio_cfg_default(p_instance->p_twi->PSELSCL);
nrf_gpio_cfg_default(p_instance->p_twi->PSELSDA);
}
p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
@ -603,11 +583,11 @@ nrfx_err_t nrfx_twi_xfer(nrfx_twi_t const * p_instance,
p_xfer_desc->primary_length,
p_xfer_desc->secondary_length);
NRFX_LOG_DEBUG("Primary buffer data:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_xfer_desc->p_primary_buf,
p_xfer_desc->primary_length * sizeof(p_xfer_desc->p_primary_buf));
NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_primary_buf,
p_xfer_desc->primary_length * sizeof(p_xfer_desc->p_primary_buf[0]));
NRFX_LOG_DEBUG("Secondary buffer data:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_xfer_desc->p_secondary_buf,
p_xfer_desc->secondary_length * sizeof(p_xfer_desc->p_secondary_buf));
NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_secondary_buf,
p_xfer_desc->secondary_length * sizeof(p_xfer_desc->p_secondary_buf[0]));
err_code = twi_xfer(p_cb, (NRF_TWI_Type *)p_instance->p_twi, p_xfer_desc, flags);
NRFX_LOG_WARNING("Function: %s, error code: %s.",
@ -619,7 +599,7 @@ nrfx_err_t nrfx_twi_xfer(nrfx_twi_t const * p_instance,
nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance,
uint8_t address,
uint8_t const * p_data,
uint32_t length,
size_t length,
bool no_stop)
{
nrfx_twi_xfer_desc_t xfer = NRFX_TWI_XFER_DESC_TX(address, (uint8_t*)p_data, length);
@ -630,13 +610,13 @@ nrfx_err_t nrfx_twi_tx(nrfx_twi_t const * p_instance,
nrfx_err_t nrfx_twi_rx(nrfx_twi_t const * p_instance,
uint8_t address,
uint8_t * p_data,
uint32_t length)
size_t length)
{
nrfx_twi_xfer_desc_t xfer = NRFX_TWI_XFER_DESC_RX(address, p_data, length);
return nrfx_twi_xfer(p_instance, &xfer, 0);
}
uint32_t nrfx_twi_data_count_get(nrfx_twi_t const * const p_instance)
size_t nrfx_twi_data_count_get(nrfx_twi_t const * const p_instance)
{
return m_cb[p_instance->drv_inst_idx].bytes_transferred;
}

77
drivers/src/nrfx_twim.c
View file

@ -38,6 +38,7 @@
#endif
#include <nrfx_twim.h>
#include <hal/nrf_gpio.h>
#include "prs/nrfx_prs.h"
#define NRFX_LOG_MODULE TWIM
@ -66,35 +67,32 @@
(type == NRFX_TWIM_XFER_TXTX ? "XFER_TXTX" : \
"UNKNOWN TRANSFER TYPE"))))
#define TWIM_PIN_INIT(_pin) nrf_gpio_cfg((_pin), \
NRF_GPIO_PIN_DIR_INPUT, \
NRF_GPIO_PIN_INPUT_CONNECT, \
NRF_GPIO_PIN_PULLUP, \
NRF_GPIO_PIN_S0D1, \
NRF_GPIO_PIN_NOSENSE)
#define SCL_PIN_INIT_CONF \
( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos))
#define TWIMX_LENGTH_VALIDATE(peripheral, drv_inst_idx, len1, len2) \
(((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \
NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, len1, len2))
#define SDA_PIN_INIT_CONF SCL_PIN_INIT_CONF
#if NRFX_CHECK(NRFX_TWIM0_ENABLED)
#define TWIM0_LENGTH_VALIDATE(...) TWIMX_LENGTH_VALIDATE(TWIM0, __VA_ARGS__)
#else
#define TWIM0_LENGTH_VALIDATE(...) 0
#endif
#define SDA_PIN_UNINIT_CONF \
( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos))
#if NRFX_CHECK(NRFX_TWIM1_ENABLED)
#define TWIM1_LENGTH_VALIDATE(...) TWIMX_LENGTH_VALIDATE(TWIM1, __VA_ARGS__)
#else
#define TWIM1_LENGTH_VALIDATE(...) 0
#endif
#define SCL_PIN_UNINIT_CONF SDA_PIN_UNINIT_CONF
#define SCL_PIN_INIT_CONF_CLR \
( (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \
| (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \
| (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \
| (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos))
#define SDA_PIN_INIT_CONF_CLR SCL_PIN_INIT_CONF_CLR
#define HW_TIMEOUT 10000
#define TWIM_LENGTH_VALIDATE(drv_inst_idx, len1, len2) \
(TWIM0_LENGTH_VALIDATE(drv_inst_idx, len1, len2) || \
TWIM1_LENGTH_VALIDATE(drv_inst_idx, len1, len2))
// Control block - driver instance local data.
typedef struct
@ -105,7 +103,7 @@ typedef struct
nrfx_twim_xfer_desc_t xfer_desc;
uint32_t flags;
uint8_t * p_curr_buf;
uint8_t curr_length;
size_t curr_length;
bool curr_no_stop;
nrfx_drv_state_t state;
bool error;
@ -190,8 +188,8 @@ nrfx_err_t nrfx_twim_init(nrfx_twim_t const * p_instance,
master when the system is in OFF mode, and when the TWI master is
disabled, these pins must be configured in the GPIO peripheral.
*/
NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_INIT_CONF;
NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_INIT_CONF;
TWIM_PIN_INIT(p_config->scl);
TWIM_PIN_INIT(p_config->sda);
NRF_TWIM_Type * p_twim = p_instance->p_twim;
nrf_twim_pins_set(p_twim, p_config->scl, p_config->sda);
@ -229,8 +227,8 @@ void nrfx_twim_uninit(nrfx_twim_t const * p_instance)
if (!p_cb->hold_bus_uninit)
{
NRF_GPIO->PIN_CNF[p_instance->p_twim->PSEL.SCL] = SCL_PIN_UNINIT_CONF;
NRF_GPIO->PIN_CNF[p_instance->p_twim->PSEL.SDA] = SDA_PIN_UNINIT_CONF;
nrf_gpio_cfg_default(p_instance->p_twim->PSEL.SCL);
nrf_gpio_cfg_default(p_instance->p_twim->PSEL.SDA);
}
p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
@ -460,6 +458,9 @@ nrfx_err_t nrfx_twim_xfer(nrfx_twim_t const * p_instance,
nrfx_twim_xfer_desc_t const * p_xfer_desc,
uint32_t flags)
{
NRFX_ASSERT(TWIM_LENGTH_VALIDATE(p_instance->drv_inst_idx,
p_xfer_desc->primary_length,
p_xfer_desc->secondary_length));
nrfx_err_t err_code = NRFX_SUCCESS;
twim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
@ -473,11 +474,11 @@ nrfx_err_t nrfx_twim_xfer(nrfx_twim_t const * p_instance,
p_xfer_desc->primary_length,
p_xfer_desc->secondary_length);
NRFX_LOG_DEBUG("Primary buffer data:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_xfer_desc->p_primary_buf,
p_xfer_desc->primary_length * sizeof(p_xfer_desc->p_primary_buf));
NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_primary_buf,
p_xfer_desc->primary_length * sizeof(p_xfer_desc->p_primary_buf[0]));
NRFX_LOG_DEBUG("Secondary buffer data:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t *)p_xfer_desc->p_secondary_buf,
p_xfer_desc->secondary_length * sizeof(p_xfer_desc->p_secondary_buf));
NRFX_LOG_HEXDUMP_DEBUG(p_xfer_desc->p_secondary_buf,
p_xfer_desc->secondary_length * sizeof(p_xfer_desc->p_secondary_buf[0]));
err_code = twim_xfer(p_cb, (NRF_TWIM_Type *)p_instance->p_twim, p_xfer_desc, flags);
NRFX_LOG_WARNING("Function: %s, error code: %s.",
@ -489,7 +490,7 @@ nrfx_err_t nrfx_twim_xfer(nrfx_twim_t const * p_instance,
nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance,
uint8_t address,
uint8_t const * p_data,
uint8_t length,
size_t length,
bool no_stop)
{
nrfx_twim_xfer_desc_t xfer = NRFX_TWIM_XFER_DESC_TX(address, (uint8_t*)p_data, length);
@ -500,7 +501,7 @@ nrfx_err_t nrfx_twim_tx(nrfx_twim_t const * p_instance,
nrfx_err_t nrfx_twim_rx(nrfx_twim_t const * p_instance,
uint8_t address,
uint8_t * p_data,
uint8_t length)
size_t length)
{
nrfx_twim_xfer_desc_t xfer = NRFX_TWIM_XFER_DESC_RX(address, p_data, length);
return nrfx_twim_xfer(p_instance, &xfer, 0);
@ -573,9 +574,9 @@ static void twim_irq_handler(NRF_TWIM_Type * p_twim, twim_control_block_t * p_cb
{
event.xfer_desc.primary_length = (p_cb->xfer_desc.type == NRFX_TWIM_XFER_RX) ?
(uint8_t)nrf_twim_rxd_amount_get(p_twim) : (uint8_t)nrf_twim_txd_amount_get(p_twim);
nrf_twim_rxd_amount_get(p_twim) : nrf_twim_txd_amount_get(p_twim);
event.xfer_desc.secondary_length = (p_cb->xfer_desc.type == NRFX_TWIM_XFER_TXRX) ?
(uint8_t)nrf_twim_rxd_amount_get(p_twim) : (uint8_t)nrf_twim_txd_amount_get(p_twim);
nrf_twim_rxd_amount_get(p_twim) : nrf_twim_txd_amount_get(p_twim);
}
nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);

24
drivers/src/nrfx_twis.c
View file

@ -323,8 +323,8 @@ static void nrfx_twis_state_machine(NRF_TWIS_Type * p_reg,
else
{
nrfx_twis_process_error(p_cb,
NRFX_TWIS_EVT_GENERAL_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
NRFX_TWIS_EVT_GENERAL_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
ev = 0;
}
break;
@ -341,8 +341,8 @@ static void nrfx_twis_state_machine(NRF_TWIS_Type * p_reg,
else
{
nrfx_twis_process_error(p_cb,
NRFX_TWIS_EVT_READ_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
NRFX_TWIS_EVT_READ_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
substate = NRFX_TWIS_SUBSTATE_IDLE;
ev = 0;
}
@ -354,10 +354,10 @@ static void nrfx_twis_state_machine(NRF_TWIS_Type * p_reg,
{
evdata.type = NRFX_TWIS_EVT_READ_DONE;
evdata.data.tx_amount = nrf_twis_tx_amount_get(p_reg);
NRFX_LOG_INFO("Transfer rx_len:%d", evdata.data.tx_amount);
NRFX_LOG_INFO("Transfer tx_len:%d", evdata.data.tx_amount);
NRFX_LOG_DEBUG("Tx data:");
NRFX_LOG_HEXDUMP_DEBUG((uint8_t const *)p_reg->TXD.PTR,
evdata.data.tx_amount);
evdata.data.tx_amount * sizeof(uint8_t));
call_event_handler(p_cb, &evdata);
/* Go to idle and repeat the state machine if READ or WRITE events detected.
* This time READ or WRITE would be started */
@ -367,8 +367,8 @@ static void nrfx_twis_state_machine(NRF_TWIS_Type * p_reg,
else
{
nrfx_twis_process_error(p_cb,
NRFX_TWIS_EVT_READ_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
NRFX_TWIS_EVT_READ_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
substate = NRFX_TWIS_SUBSTATE_IDLE;
ev = 0;
}
@ -386,8 +386,8 @@ static void nrfx_twis_state_machine(NRF_TWIS_Type * p_reg,
else
{
nrfx_twis_process_error(p_cb,
NRFX_TWIS_EVT_WRITE_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
NRFX_TWIS_EVT_WRITE_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
substate = NRFX_TWIS_SUBSTATE_IDLE;
ev = 0;
}
@ -408,8 +408,8 @@ static void nrfx_twis_state_machine(NRF_TWIS_Type * p_reg,
else
{
nrfx_twis_process_error(p_cb,
NRFX_TWIS_EVT_WRITE_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
NRFX_TWIS_EVT_WRITE_ERROR,
nrf_twis_error_source_get_and_clear(p_reg));
substate = NRFX_TWIS_SUBSTATE_IDLE;
ev = 0;
}

36
drivers/src/nrfx_uart.c
View file

@ -33,7 +33,7 @@
#if NRFX_CHECK(NRFX_UART_ENABLED)
#if !(NRFX_CHECK(NRFX_UART0_ENABLED) || NRFX_CHECK(NRFX_UART1_ENABLED))
#if !NRFX_CHECK(NRFX_UART0_ENABLED)
#error "No enabled UART instances. Check <nrfx_config.h>."
#endif
@ -58,11 +58,11 @@ typedef struct
uint8_t const * p_tx_buffer;
uint8_t * p_rx_buffer;
uint8_t * p_rx_secondary_buffer;
uint32_t tx_buffer_length;
uint32_t rx_buffer_length;
uint32_t rx_secondary_buffer_length;
volatile uint32_t tx_counter;
volatile uint32_t rx_counter;
size_t tx_buffer_length;
size_t rx_buffer_length;
size_t rx_secondary_buffer_length;
volatile size_t tx_counter;
volatile size_t rx_counter;
volatile bool tx_abort;
bool rx_enabled;
nrfx_drv_state_t state;
@ -176,9 +176,6 @@ nrfx_err_t nrfx_uart_init(nrfx_uart_t const * p_instance,
#if NRFX_CHECK(NRFX_UART0_ENABLED)
nrfx_uart_0_irq_handler,
#endif
#if NRFX_CHECK(NRFX_UART1_ENABLED)
nrfx_uart_1_irq_handler,
#endif
};
if (nrfx_prs_acquire(p_instance->p_reg,
irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS)
@ -265,7 +262,7 @@ static bool tx_blocking(NRF_UART_Type * p_uart, uart_control_block_t * p_cb)
nrfx_err_t nrfx_uart_tx(nrfx_uart_t const * p_instance,
uint8_t const * p_data,
uint32_t length)
size_t length)
{
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED);
@ -348,7 +345,7 @@ static void rx_byte(NRF_UART_Type * p_uart, uart_control_block_t * p_cb)
nrfx_err_t nrfx_uart_rx(nrfx_uart_t const * p_instance,
uint8_t * p_data,
uint32_t length)
size_t length)
{
uart_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
@ -492,7 +489,7 @@ uint32_t nrfx_uart_errorsrc_get(nrfx_uart_t const * p_instance)
}
static void rx_done_event(uart_control_block_t * p_cb,
uint32_t bytes,
size_t bytes,
uint8_t * p_data)
{
nrfx_uart_event_t event;
@ -505,7 +502,7 @@ static void rx_done_event(uart_control_block_t * p_cb,
}
static void tx_done_event(uart_control_block_t * p_cb,
uint8_t bytes)
size_t bytes)
{
nrfx_uart_event_t event;
@ -561,7 +558,7 @@ static void uart_irq_handler(NRF_UART_Type * p_uart,
event.data.error.rxtx.bytes = p_cb->rx_buffer_length;
event.data.error.rxtx.p_data = p_cb->p_rx_buffer;
//abort transfer
// Abort transfer.
p_cb->rx_buffer_length = 0;
p_cb->rx_secondary_buffer_length = 0;
@ -576,9 +573,9 @@ static void uart_irq_handler(NRF_UART_Type * p_uart,
if (p_cb->rx_secondary_buffer_length)
{
uint8_t * p_data = p_cb->p_rx_buffer;
uint32_t rx_counter = p_cb->rx_counter;
size_t rx_counter = p_cb->rx_counter;
//Switch to secondary buffer.
// Switch to secondary buffer.
p_cb->rx_buffer_length = p_cb->rx_secondary_buffer_length;
p_cb->p_rx_buffer = p_cb->p_rx_secondary_buffer;
p_cb->rx_secondary_buffer_length = 0;
@ -640,11 +637,4 @@ void nrfx_uart_0_irq_handler(void)
}
#endif
#if NRFX_CHECK(NRFX_UART1_ENABLED)
void nrfx_uart_1_irq_handler(void)
{
uart_irq_handler(NRF_UART1, &m_cb[NRFX_UART1_INST_IDX]);
}
#endif
#endif // NRFX_CHECK(NRFX_UART_ENABLED)

42
drivers/src/nrfx_uarte.c
View file

@ -48,6 +48,26 @@
(event == NRF_UARTE_EVENT_ERROR ? "NRF_UARTE_EVENT_ERROR" : \
"UNKNOWN EVENT")
#define UARTEX_LENGTH_VALIDATE(peripheral, drv_inst_idx, len1, len2) \
(((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \
NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, len1, len2))
#if NRFX_CHECK(NRFX_UARTE0_ENABLED)
#define UARTE0_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE0, __VA_ARGS__)
#else
#define UARTE0_LENGTH_VALIDATE(...) 0
#endif
#if NRFX_CHECK(NRFX_UARTE1_ENABLED)
#define UARTE1_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE1, __VA_ARGS__)
#else
#define UARTE1_LENGTH_VALIDATE(...) 0
#endif
#define UARTE_LENGTH_VALIDATE(drv_inst_idx, length) \
(UARTE0_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \
UARTE1_LENGTH_VALIDATE(drv_inst_idx, length, 0))
typedef struct
{
@ -56,9 +76,9 @@ typedef struct
uint8_t const * p_tx_buffer;
uint8_t * p_rx_buffer;
uint8_t * p_rx_secondary_buffer;
uint8_t tx_buffer_length;
uint8_t rx_buffer_length;
uint8_t rx_secondary_buffer_length;
size_t tx_buffer_length;
size_t rx_buffer_length;
size_t rx_secondary_buffer_length;
nrfx_drv_state_t state;
} uarte_control_block_t;
static uarte_control_block_t m_cb[NRFX_UARTE_ENABLED_COUNT];
@ -234,12 +254,13 @@ void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance)
nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance,
uint8_t const * p_data,
uint8_t length)
size_t length)
{
uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED);
NRFX_ASSERT(p_data);
NRFX_ASSERT(length > 0);
NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length));
nrfx_err_t err_code;
@ -306,13 +327,14 @@ bool nrfx_uarte_tx_in_progress(nrfx_uarte_t const * p_instance)
nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance,
uint8_t * p_data,
uint8_t length)
size_t length)
{
uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED);
NRFX_ASSERT(p_data);
NRFX_ASSERT(length > 0);
NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length));
nrfx_err_t err_code;
@ -424,7 +446,7 @@ uint32_t nrfx_uarte_errorsrc_get(nrfx_uarte_t const * p_instance)
}
static void rx_done_event(uarte_control_block_t * p_cb,
uint8_t bytes,
size_t bytes,
uint8_t * p_data)
{
nrfx_uarte_event_t event;
@ -437,7 +459,7 @@ static void rx_done_event(uarte_control_block_t * p_cb,
}
static void tx_done_event(uarte_control_block_t * p_cb,
uint8_t bytes)
size_t bytes)
{
nrfx_uarte_event_t event;
@ -484,7 +506,7 @@ static void uarte_irq_handler(NRF_UARTE_Type * p_uarte,
event.data.error.rxtx.bytes = nrf_uarte_rx_amount_get(p_uarte);
event.data.error.rxtx.p_data = p_cb->p_rx_buffer;
//abort transfer
// Abort transfer.
p_cb->rx_buffer_length = 0;
p_cb->rx_secondary_buffer_length = 0;
@ -493,9 +515,9 @@ static void uarte_irq_handler(NRF_UARTE_Type * p_uarte,
else if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDRX))
{
nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDRX);
uint8_t amount = nrf_uarte_rx_amount_get(p_uarte);
size_t amount = nrf_uarte_rx_amount_get(p_uarte);
// If the transfer was stopped before completion, amount of transfered bytes
// will not be equal to the buffer length. Interrupted trunsfer is ignored.
// will not be equal to the buffer length. Interrupted transfer is ignored.
if (amount == p_cb->rx_buffer_length)
{
if (p_cb->rx_secondary_buffer_length)

8
drivers/src/nrfx_wdt.c
View file

@ -47,8 +47,6 @@ static nrfx_drv_state_t m_state;
/**@brief WDT alloc table. */
static uint32_t m_alloc_index;
static const nrfx_wdt_config_t m_default_config = NRFX_WDT_DEAFULT_CONFIG;
/**@brief WDT interrupt handler. */
void nrfx_wdt_irq_handler(void)
{
@ -63,6 +61,7 @@ void nrfx_wdt_irq_handler(void)
nrfx_err_t nrfx_wdt_init(nrfx_wdt_config_t const * p_config,
nrfx_wdt_event_handler_t wdt_event_handler)
{
NRFX_ASSERT(p_config);
NRFX_ASSERT(wdt_event_handler != NULL);
nrfx_err_t err_code;
m_wdt_event_handler = wdt_event_handler;
@ -80,11 +79,6 @@ nrfx_err_t nrfx_wdt_init(nrfx_wdt_config_t const * p_config,
return err_code;
}
if (p_config == NULL)
{
p_config = &m_default_config;
}
nrf_wdt_behaviour_set(p_config->behaviour);
nrf_wdt_reload_value_set((p_config->reload_value * 32768) / 1000);

7
drivers/src/prs/nrfx_prs.c
View file

@ -71,9 +71,6 @@ PRS_BOX_DEFINE(3)
#if defined(NRFX_PRS_BOX_4_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED)
PRS_BOX_DEFINE(4)
#endif
#if defined(NRFX_PRS_BOX_5_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_5_ENABLED)
PRS_BOX_DEFINE(5)
#endif
static prs_box_t * prs_box_get(void const * p_base_addr)
@ -101,10 +98,6 @@ static prs_box_t * prs_box_get(void const * p_base_addr)
#if defined(NRFX_PRS_BOX_4_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_4_ENABLED)
if (IS_PRS_BOX(4, p_base_addr)) { return &m_prs_box_4; }
else
#endif
#if defined(NRFX_PRS_BOX_5_ADDR) && NRFX_CHECK(NRFX_PRS_BOX_5_ENABLED)
if (IS_PRS_BOX(5, p_base_addr)) { return &m_prs_box_5; }
else
#endif
{
return NULL;

3
drivers/src/prs/nrfx_prs.h
View file

@ -78,8 +78,6 @@ extern "C" {
#define NRFX_PRS_BOX_3_ADDR NRF_COMP
// UARTE0, UART0
#define NRFX_PRS_BOX_4_ADDR NRF_UARTE0
// UARTE1, UART1
#define NRFX_PRS_BOX_5_ADDR NRF_UARTE1
#else
#error "Unknown device."
#endif
@ -123,7 +121,6 @@ void nrfx_prs_box_1_irq_handler(void);
void nrfx_prs_box_2_irq_handler(void);
void nrfx_prs_box_3_irq_handler(void);
void nrfx_prs_box_4_irq_handler(void);
void nrfx_prs_box_5_irq_handler(void);
/** @} */

13
hal/nrf_comp.h
View file

@ -58,8 +58,11 @@ typedef enum
NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */
NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */
NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */
#ifdef COMP_PSEL_PSEL_AnalogInput7
NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7 /*!< AIN7 selected as analog input. */
#if defined (COMP_PSEL_PSEL_AnalogInput7) || defined (__NRFX_DOXYGEN__)
NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7, /*!< AIN7 selected as analog input. */
#endif
#if defined (COMP_PSEL_PSEL_VddDiv2) || defined (__NRFX_DOXYGEN__)
NRF_COMP_VDD_DIV2 = COMP_PSEL_PSEL_VddDiv2, /*!< VDD/2 selected as analog input. */
#endif
}nrf_comp_input_t;
@ -126,6 +129,7 @@ typedef enum
NRF_COMP_HYST_50mV = COMP_HYST_HYST_Hyst50mV /*!< Comparator hysteresis enabled. */
}nrf_comp_hyst_t;
#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__)
/**
* @brief COMP current source selection on analog input.
*/
@ -136,6 +140,7 @@ typedef enum
NRF_COMP_ISOURCE_Ien5uA = COMP_ISOURCE_ISOURCE_Ien5mA, /*!< Current source enabled (+/- 5 uA). */
NRF_COMP_ISOURCE_Ien10uA = COMP_ISOURCE_ISOURCE_Ien10mA /*!< Current source enabled (+/- 10 uA). */
}nrf_isource_t;
#endif
/**
* @enum nrf_comp_task_t
@ -242,12 +247,14 @@ __STATIC_INLINE void nrf_comp_speed_mode_set(nrf_comp_sp_mode_t speed_mode);
__STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst);
#if defined (COMP_ISOURCE_ISOURCE_Msk) || defined (__NRFX_DOXYGEN__)
/**
* @brief Function for setting the current source on the analog input.
*
* @param[in] isource COMP current source selection on analog input.
*/
__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource);
#endif
/**
@ -411,10 +418,12 @@ __STATIC_INLINE void nrf_comp_hysteresis_set(nrf_comp_hyst_t hyst)
NRF_COMP->HYST = (hyst << COMP_HYST_HYST_Pos) & COMP_HYST_HYST_Msk;
}
#if defined (COMP_ISOURCE_ISOURCE_Msk)
__STATIC_INLINE void nrf_comp_isource_set(nrf_isource_t isource)
{
NRF_COMP->ISOURCE = (isource << COMP_ISOURCE_ISOURCE_Pos) & COMP_ISOURCE_ISOURCE_Msk;
}
#endif
__STATIC_INLINE void nrf_comp_input_select(nrf_comp_input_t input)
{

61
hal/nrf_nvmc.c
View file

@ -36,25 +36,25 @@
#include <nrfx.h>
#include <nrf_nvmc.h>
static inline void wait_for_flash_ready(void)
{
while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {;}
}
void nrf_nvmc_page_erase(uint32_t address)
{
// Enable erase.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
__ISB();
__DSB();
// Erase the page
NRF_NVMC->ERASEPAGE = address;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
wait_for_flash_ready();
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
__ISB();
__DSB();
}
@ -67,41 +67,36 @@ void nrf_nvmc_write_byte(uint32_t address, uint8_t value)
// Enable write.
NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
__ISB();
__DSB();
*(uint32_t*)address32 = value32;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
wait_for_flash_ready();
NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
{
}
__ISB();
__DSB();
}
void nrf_nvmc_write_word(uint32_t address, uint32_t value)
{
// Enable write.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
}
__ISB();
__DSB();
*(uint32_t*)address = value;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
}
wait_for_flash_ready();
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
__ISB();
__DSB();
}
void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes)
{
uint32_t i;
for (i=0;i<num_bytes;i++)
for (i = 0; i < num_bytes; i++)
{
nrf_nvmc_write_byte(address + i,src[i]);
}
@ -113,21 +108,17 @@ void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_w
// Enable write.
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
__ISB();
__DSB();
for (i=0;i<num_words;i++)
for (i = 0; i < num_words; i++)
{
((uint32_t*)address)[i] = src[i];
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
wait_for_flash_ready();
}
NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
{
}
__ISB();
__DSB();
}

15
hal/nrf_qspi.h
View file

@ -358,6 +358,15 @@ __STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg);
__STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_pins_t * p_pins);
/**
* @brief Function for setting the QSPI XIPOFFSET register.
*
* @param[in] p_reg Pointer to the peripheral register structure.
* @param[in] xip_offset Address offset in the external memory for Execute in Place operation.
*/
__STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
uint32_t xip_offset);
/**
* @brief Function for setting the QSPI IFCONFIG0 register.
*
@ -557,6 +566,12 @@ __STATIC_INLINE void nrf_qspi_pins_set(NRF_QSPI_Type * p_reg, const nrf_qspi_pin
p_reg->PSEL.IO3 = NRF_QSPI_PIN_VAL(p_pins->io3_pin);
}
__STATIC_INLINE void nrf_qspi_xip_offset_set(NRF_QSPI_Type * p_reg,
uint32_t xip_offset)
{
p_reg->XIPOFFSET = xip_offset;
}
__STATIC_INLINE void nrf_qspi_ifconfig0_set(NRF_QSPI_Type * p_reg,
const nrf_qspi_prot_conf_t * p_config)
{

215
hal/nrf_spim.h
View file

@ -52,6 +52,22 @@ extern "C" {
*/
#define NRF_SPIM_PIN_NOT_CONNECTED 0xFFFFFFFF
#if defined(SPIM_DCXCNT_DCXCNT_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief This value specified in the DCX line configuration causes this line
* to be set low during whole transmission (all transmitted bytes are
* marked as command bytes). Any lower value causes the DCX line to be
* switched from low to high after this number of bytes is transmitted
* (all remaining bytes are marked as data bytes).
*/
#define NRF_SPIM_DCX_CNT_ALL_CMD 0xF
#endif
#define NRF_SPIM_HW_CSN_PRESENT \
(NRFX_CHECK(SPIM0_FEATURE_HARDWARE_CSN_PRESENT) || \
NRFX_CHECK(SPIM1_FEATURE_HARDWARE_CSN_PRESENT) || \
NRFX_CHECK(SPIM2_FEATURE_HARDWARE_CSN_PRESENT) || \
NRFX_CHECK(SPIM3_FEATURE_HARDWARE_CSN_PRESENT))
/**
* @brief SPIM tasks.
@ -111,15 +127,21 @@ typedef enum
*/
typedef enum
{
NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125, ///< 125 kbps.
NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500, ///< 500 kbps.
NRF_SPIM_FREQ_1M = SPIM_FREQUENCY_FREQUENCY_M1, ///< 1 Mbps.
NRF_SPIM_FREQ_2M = SPIM_FREQUENCY_FREQUENCY_M2, ///< 2 Mbps.
NRF_SPIM_FREQ_4M = SPIM_FREQUENCY_FREQUENCY_M4, ///< 4 Mbps.
// [conversion to 'int' needed to prevent compilers from complaining
// that the provided value (0x80000000UL) is out of range of "int"]
NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
NRF_SPIM_FREQ_8M = (int)SPIM_FREQUENCY_FREQUENCY_M8, ///< 8 Mbps.
#if defined(SPIM_FREQUENCY_FREQUENCY_M16) || defined(__NRFX_DOXYGEN__)
NRF_SPIM_FREQ_16M = SPIM_FREQUENCY_FREQUENCY_M16, ///< 16 Mbps.
#endif
#if defined(SPIM_FREQUENCY_FREQUENCY_M32) || defined(__NRFX_DOXYGEN__)
NRF_SPIM_FREQ_32M = SPIM_FREQUENCY_FREQUENCY_M32 ///< 32 Mbps.
#endif
} nrf_spim_frequency_t;
/**
@ -142,6 +164,16 @@ typedef enum
NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst ///< Least significant bit shifted out first.
} nrf_spim_bit_order_t;
#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief SPI CSN pin polarity.
*/
typedef enum
{
NRF_SPIM_CSN_POL_LOW = SPIM_CSNPOL_CSNPOL_LOW, ///< Active low (idle state high).
NRF_SPIM_CSN_POL_HIGH = SPIM_CSNPOL_CSNPOL_HIGH ///< Active high (idle state low).
} nrf_spim_csn_pol_t;
#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for activating a specific SPIM task.
@ -270,19 +302,114 @@ __STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_reg);
* value instead of its pin number.
*
* @param[in] p_reg Pointer to the peripheral registers structure.
* @param[in] sck_pin SCK pin number.
* @param[in] mosi_pin MOSI pin number.
* @param[in] miso_pin MISO pin number.
* @param[in] sck_pin SCK pin number.
* @param[in] mosi_pin MOSI pin number.
* @param[in] miso_pin MISO pin number.
*/
__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
uint32_t sck_pin,
uint32_t mosi_pin,
uint32_t miso_pin);
#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for configuring the SPIM hardware CSN pin.
*
* If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_reg Pointer to the peripheral registers structure.
* @param[in] pin CSN pin number.
* @param[in] polarity CSN pin polarity.
* @param[in] duration Minimum duration between the edge of CSN and the edge of SCK
* and minimum duration of CSN must stay unselected between transactions.
* The value is specified in number of 64 MHz clock cycles (15.625 ns).
*/
__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
uint32_t pin,
nrf_spim_csn_pol_t polarity,
uint32_t duration);
#endif // (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
#if defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for configuring the SPIM DCX pin.
*
* If this signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
* value instead of its pin number.
*
* @param[in] p_reg Pointer to the peripheral registers structure.
* @param[in] dcx_pin DCX pin number.
*/
__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
uint32_t dcx_pin);
/**
* @brief Function for configuring the number of command bytes.
*
* Maximum value available for dividing the transmitted bytes into command
* bytes and data bytes is @ref NRF_SPIM_DCX_CNT_ALL_CMD - 1.
* The @ref NRF_SPIM_DCX_CNT_ALL_CMD value passed as the @c count parameter
* causes all transmitted bytes to be marked as command bytes.
*
* @param[in] p_reg Pointer to the peripheral registers structure.
* @param[in] count Number of command bytes preceding the data bytes.
*/
__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
uint32_t count);
#endif // defined(SPIM_PSELDCX_CONNECT_Msk) || defined(__NRFX_DOXYGEN__)
#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for configuring the extended SPIM interface.
* @param p_reg Pointer to the peripheral registers structure.
* @param rxdelay Sample delay for input serial data on MISO,
* specified in 64 MHz clock cycles (15.625 ns) from the sampling edge of SCK.
*/
__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
uint32_t rxdelay);
#endif // defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk) || defined(__NRFX_DOXYGEN__)
#if defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for clearing stall status for RX EasyDMA RAM accesses.
*
* @param p_reg Pointer to the peripheral registers structure.
*/
__STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg);
/**
* @brief Function for getting stall status for RX EasyDMA RAM accesses.
*
* @param p_reg Pointer to the peripheral registers structure.
*
* @return Stall status of RX EasyDMA RAM accesses.
*/
__STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg);
#endif // defined(SPIM_STALLSTAT_RX_Msk) || defined(__NRFX_DOXYGEN__)
#if defined(SPIM_STALLSTAT_TX_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for clearing stall status for TX EasyDMA RAM accesses.
*
* @param p_reg Pointer to the peripheral registers structure.
*/
__STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg);
/**
* @brief Function for getting stall status for TX EasyDMA RAM accesses.
*
* @param p_reg Pointer to the peripheral registers structure.
*
* @return Stall status of TX EasyDMA RAM accesses.
*/
__STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg);
#endif // defined(SPIM_STALLSTAT_TX_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for setting the SPI master data rate.
*
* @param[in] p_reg Pointer to the peripheral registers structure.
* @param[in] p_reg Pointer to the peripheral registers structure.
* @param[in] frequency SPI frequency.
*/
__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
@ -297,7 +424,7 @@ __STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
*/
__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length);
size_t length);
/**
* @brief Function for setting the receive buffer.
@ -308,7 +435,7 @@ __STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
*/
__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
uint8_t * p_buffer,
uint8_t length);
size_t length);
/**
* @brief Function for setting the SPI configuration.
@ -450,6 +577,64 @@ __STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
p_reg->PSEL.MISO = miso_pin;
}
#if (NRF_SPIM_HW_CSN_PRESENT)
__STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
uint32_t pin,
nrf_spim_csn_pol_t polarity,
uint32_t duration)
{
p_reg->PSEL.CSN = pin;
p_reg->CSNPOL = polarity;
p_reg->IFTIMING.CSNDUR = duration;
}
#endif // defined(NRF_SPIM_HW_CSN_PRESENT)
#if defined(SPIM_PSELDCX_CONNECT_Msk)
__STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
uint32_t dcx_pin)
{
p_reg->PSELDCX = dcx_pin;
}
__STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
uint32_t dcx_cnt)
{
p_reg->DCXCNT = dcx_cnt;
}
#endif // defined(SPIM_PSELDCX_CONNECT_Msk)
#if defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk)
__STATIC_INLINE void nrf_spim_iftiming_set(NRF_SPIM_Type * p_reg,
uint32_t rxdelay)
{
p_reg->IFTIMING.RXDELAY = rxdelay;
}
#endif // defined(SPIM_IFTIMING_RXDELAY_RXDELAY_Msk)
#if defined(SPIM_STALLSTAT_RX_Msk)
__STATIC_INLINE void nrf_spim_stallstat_rx_clear(NRF_SPIM_Type * p_reg)
{
p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_RX_Msk);
}
__STATIC_INLINE bool nrf_spim_stallstat_rx_get(NRF_SPIM_Type * p_reg)
{
return (p_reg->STALLSTAT & SPIM_STALLSTAT_RX_Msk) != 0;
}
#endif // defined(SPIM_STALLSTAT_RX_Msk)
#if defined(SPIM_STALLSTAT_TX_Msk)
__STATIC_INLINE void nrf_spim_stallstat_tx_clear(NRF_SPIM_Type * p_reg)
{
p_reg->STALLSTAT &= ~(SPIM_STALLSTAT_TX_Msk);
}
__STATIC_INLINE bool nrf_spim_stallstat_tx_get(NRF_SPIM_Type * p_reg)
{
return (p_reg->STALLSTAT & SPIM_STALLSTAT_TX_Msk) != 0;
}
#endif // defined(SPIM_STALLSTAT_TX_Msk)
__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
nrf_spim_frequency_t frequency)
{
@ -458,7 +643,7 @@ __STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_reg,
__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length)
size_t length)
{
p_reg->TXD.PTR = (uint32_t)p_buffer;
p_reg->TXD.MAXCNT = length;
@ -466,7 +651,7 @@ __STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_reg,
__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_reg,
uint8_t * p_buffer,
uint8_t length)
size_t length)
{
p_reg->RXD.PTR = (uint32_t)p_buffer;
p_reg->RXD.MAXCNT = length;

45
hal/nrf_spis.h
View file

@ -291,7 +291,7 @@ __STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
*/
__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length);
size_t length);
/**
* @brief Function for setting the receive buffer.
@ -302,7 +302,7 @@ __STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
*/
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t * p_buffer,
uint8_t length);
size_t length);
/**
* @brief Function for getting the number of bytes transmitted
@ -312,7 +312,7 @@ __STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
*
* @returns Number of bytes transmitted.
*/
__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg);
__STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg);
/**
* @brief Function for getting the number of bytes received
@ -322,7 +322,7 @@ __STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg);
*
* @returns Number of bytes received.
*/
__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg);
__STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg);
/**
* @brief Function for setting the SPI configuration.
@ -449,36 +449,61 @@ __STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
uint32_t miso_pin,
uint32_t csn_pin)
{
#if defined (NRF51)
p_reg->PSELSCK = sck_pin;
p_reg->PSELMOSI = mosi_pin;
p_reg->PSELMISO = miso_pin;
p_reg->PSELCSN = csn_pin;
#else
p_reg->PSEL.SCK = sck_pin;
p_reg->PSEL.MOSI = mosi_pin;
p_reg->PSEL.MISO = miso_pin;
p_reg->PSEL.CSN = csn_pin;
#endif
}
__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length)
size_t length)
{
#if defined (NRF51)
p_reg->TXDPTR = (uint32_t)p_buffer;
p_reg->MAXTX = length;
#else
p_reg->TXD.PTR = (uint32_t)p_buffer;
p_reg->TXD.MAXCNT = length;
#endif
}
__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t * p_buffer,
uint8_t length)
size_t length)
{
#if defined (NRF51)
p_reg->RXDPTR = (uint32_t)p_buffer;
p_reg->MAXRX = length;
#else
p_reg->RXD.PTR = (uint32_t)p_buffer;
p_reg->RXD.MAXCNT = length;
#endif
}
__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg)
__STATIC_INLINE size_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_reg)
{
return (uint8_t) p_reg->AMOUNTTX;
#if defined (NRF51)
return p_reg->AMOUNTTX;
#else
return p_reg->TXD.AMOUNT;
#endif
}
__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)
__STATIC_INLINE size_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_reg)
{
return (uint8_t) p_reg->AMOUNTRX;
#if defined (NRF51)
return p_reg->AMOUNTRX;
#else
return p_reg->RXD.AMOUNT;
#endif
}
__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_reg,

24
hal/nrf_timer.h
View file

@ -101,8 +101,10 @@ typedef enum
NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1.
NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2.
NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3.
#if (TIMER_COUNT > 3) || defined(__NRFX_DOXYGEN__)
#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4.
#endif
#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5.
#endif
/*lint -restore*/
@ -118,8 +120,10 @@ typedef enum
NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1.
NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2.
NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3.
#if (TIMER_COUNT > 3) || defined(__NRFX_DOXYGEN__)
#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4.
#endif
#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5.
#endif
/*lint -restore*/
@ -134,16 +138,20 @@ typedef enum
NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk, ///< Shortcut for stopping the timer based on compare 1.
NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk, ///< Shortcut for stopping the timer based on compare 2.
NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk, ///< Shortcut for stopping the timer based on compare 3.
#if (TIMER_COUNT > 3) || defined(__NRFX_DOXYGEN__)
#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk, ///< Shortcut for stopping the timer based on compare 4.
#endif
#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk, ///< Shortcut for stopping the timer based on compare 5.
#endif
NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0.
NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1.
NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2.
NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3.
#if (TIMER_COUNT > 3) || defined(__NRFX_DOXYGEN__)
#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4.
#endif
#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5.
#endif
} nrf_timer_short_mask_t;
@ -197,8 +205,10 @@ typedef enum
NRF_TIMER_CC_CHANNEL1, ///< Timer capture/compare channel 1.
NRF_TIMER_CC_CHANNEL2, ///< Timer capture/compare channel 2.
NRF_TIMER_CC_CHANNEL3, ///< Timer capture/compare channel 3.
#if (TIMER_COUNT > 3) || defined(__NRFX_DOXYGEN__)
#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_CC_CHANNEL4, ///< Timer capture/compare channel 4.
#endif
#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_CC_CHANNEL5, ///< Timer capture/compare channel 5.
#endif
} nrf_timer_cc_channel_t;
@ -212,8 +222,10 @@ typedef enum
NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1.
NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2.
NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3.
#if (TIMER_COUNT > 3) || defined(__NRFX_DOXYGEN__)
#if defined(TIMER_INTENSET_COMPARE4_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4.
#endif
#if defined(TIMER_INTENSET_COMPARE5_Msk) || defined(__NRFX_DOXYGEN__)
NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5.
#endif
} nrf_timer_int_mask_t;

16
hal/nrf_twim.h
View file

@ -297,7 +297,7 @@ __STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
*/
__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length);
size_t length);
/**
* @brief Function for setting the receive buffer.
@ -308,14 +308,14 @@ __STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
*/
__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
uint8_t * p_buffer,
uint8_t length);
size_t length);
__STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
uint32_t shorts_mask);
__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg);
__STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg);
__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg);
__STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg);
/**
* @brief Function for enabling the TX list feature.
@ -453,7 +453,7 @@ __STATIC_INLINE void nrf_twim_address_set(NRF_TWIM_Type * p_reg,
__STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length)
size_t length)
{
p_reg->TXD.PTR = (uint32_t)p_buffer;
p_reg->TXD.MAXCNT = length;
@ -461,7 +461,7 @@ __STATIC_INLINE void nrf_twim_tx_buffer_set(NRF_TWIM_Type * p_reg,
__STATIC_INLINE void nrf_twim_rx_buffer_set(NRF_TWIM_Type * p_reg,
uint8_t * p_buffer,
uint8_t length)
size_t length)
{
p_reg->RXD.PTR = (uint32_t)p_buffer;
p_reg->RXD.MAXCNT = length;
@ -473,12 +473,12 @@ __STATIC_INLINE void nrf_twim_shorts_set(NRF_TWIM_Type * p_reg,
p_reg->SHORTS = shorts_mask;
}
__STATIC_INLINE uint32_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg)
__STATIC_INLINE size_t nrf_twim_txd_amount_get(NRF_TWIM_Type * p_reg)
{
return p_reg->TXD.AMOUNT;
}
__STATIC_INLINE uint32_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg)
__STATIC_INLINE size_t nrf_twim_rxd_amount_get(NRF_TWIM_Type * p_reg)
{
return p_reg->RXD.AMOUNT;
}

56
hal/nrf_uart.h
View file

@ -38,9 +38,6 @@
extern "C" {
#endif
//Temporary defining legacy UART for instance 1
#define NRF_UART1 (NRF_UART_Type *)NRF_UARTE1
/**
* @defgroup nrf_uart_hal UART HAL
* @{
@ -103,41 +100,24 @@ typedef enum
*/
typedef enum
{
#ifdef UARTE_PRESENT
NRF_UART_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
NRF_UART_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
NRF_UART_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
NRF_UART_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
NRF_UART_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
NRF_UART_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
NRF_UART_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
NRF_UART_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
NRF_UART_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
NRF_UART_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
NRF_UART_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
NRF_UART_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
NRF_UART_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
NRF_UART_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
NRF_UART_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
NRF_UART_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
#else
NRF_UART_BAUDRATE_1200 = UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
NRF_UART_BAUDRATE_2400 = UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
NRF_UART_BAUDRATE_4800 = UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
NRF_UART_BAUDRATE_9600 = UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
NRF_UART_BAUDRATE_14400 = UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
NRF_UART_BAUDRATE_19200 = UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
NRF_UART_BAUDRATE_28800 = UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
NRF_UART_BAUDRATE_38400 = UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
NRF_UART_BAUDRATE_57600 = UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
NRF_UART_BAUDRATE_76800 = UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
NRF_UART_BAUDRATE_115200 = UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
NRF_UART_BAUDRATE_230400 = UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
NRF_UART_BAUDRATE_250000 = UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
NRF_UART_BAUDRATE_460800 = UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
NRF_UART_BAUDRATE_921600 = UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
NRF_UART_BAUDRATE_1000000 = UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
#endif
NRF_UART_BAUDRATE_1200 = UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
NRF_UART_BAUDRATE_2400 = UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
NRF_UART_BAUDRATE_4800 = UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
NRF_UART_BAUDRATE_9600 = UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
NRF_UART_BAUDRATE_14400 = UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
NRF_UART_BAUDRATE_19200 = UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
NRF_UART_BAUDRATE_28800 = UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
NRF_UART_BAUDRATE_31250 = UART_BAUDRATE_BAUDRATE_Baud31250, /**< 31250 baud. */
NRF_UART_BAUDRATE_38400 = UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
NRF_UART_BAUDRATE_56000 = UART_BAUDRATE_BAUDRATE_Baud56000, /**< 56000 baud. */
NRF_UART_BAUDRATE_57600 = UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
NRF_UART_BAUDRATE_76800 = UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
NRF_UART_BAUDRATE_115200 = UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
NRF_UART_BAUDRATE_230400 = UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
NRF_UART_BAUDRATE_250000 = UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
NRF_UART_BAUDRATE_460800 = UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
NRF_UART_BAUDRATE_921600 = UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
NRF_UART_BAUDRATE_1000000 = UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
} nrf_uart_baudrate_t;
/**

42
hal/nrf_uarte.h
View file

@ -114,22 +114,24 @@ typedef enum
*/
typedef enum
{
NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud.
NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud.
NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud.
NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M, ///< 1000000 baud.
} nrf_uarte_baudrate_t;
/**
@ -369,7 +371,7 @@ __STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_
*/
__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length);
size_t length);
/**
* @brief Function for getting number of bytes transmitted in the last transaction.
@ -389,7 +391,7 @@ __STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg);
*/
__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t * p_buffer,
uint8_t length);
size_t length);
/**
* @brief Function for getting number of bytes received in the last transaction.
@ -530,7 +532,7 @@ __STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_
__STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t const * p_buffer,
uint8_t length)
size_t length)
{
p_reg->TXD.PTR = (uint32_t)p_buffer;
p_reg->TXD.MAXCNT = length;
@ -543,7 +545,7 @@ __STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type * p_reg)
__STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
uint8_t * p_buffer,
uint8_t length)
size_t length)
{
p_reg->RXD.PTR = (uint32_t)p_buffer;
p_reg->RXD.MAXCNT = length;

18
hal/nrf_usbd.h
View file

@ -1219,6 +1219,10 @@ void nrf_usbd_dpdmvalue_set(nrf_usbd_dpdmvalue_t val)
void nrf_usbd_dtoggle_set(uint8_t ep, nrf_usbd_dtoggle_t op)
{
ASSERT(NRF_USBD_EP_VALIDATE(ep));
ASSERT(!NRF_USBD_EPISO_CHECK(ep));
NRF_USBD->DTOGGLE = ep | (NRF_USBD_DTOGGLE_NOP << USBD_DTOGGLE_VALUE_Pos);
__DSB();
NRF_USBD->DTOGGLE = ep | (op << USBD_DTOGGLE_VALUE_Pos);
__ISB();
__DSB();
@ -1228,7 +1232,7 @@ nrf_usbd_dtoggle_t nrf_usbd_dtoggle_get(uint8_t ep)
{
uint32_t retval;
/* Select the endpoint to read */
nrf_usbd_dtoggle_set(ep, NRF_USBD_DTOGGLE_NOP);
NRF_USBD->DTOGGLE = ep | (NRF_USBD_DTOGGLE_NOP << USBD_DTOGGLE_VALUE_Pos);
retval = ((NRF_USBD->DTOGGLE) & USBD_DTOGGLE_VALUE_Msk) >> USBD_DTOGGLE_VALUE_Pos;
return (nrf_usbd_dtoggle_t)retval;
}
@ -1240,11 +1244,11 @@ bool nrf_usbd_ep_enable_check(uint8_t ep)
if (NRF_USBD_EPIN_CHECK(ep))
{
return 0 != (NRF_USBD->EPINEN & (1UL<<epnr));
return 0 != (NRF_USBD->EPINEN & (1UL << epnr));
}
else
{
return 0 != (NRF_USBD->EPOUTEN & (1UL<<epnr));
return 0 != (NRF_USBD->EPOUTEN & (1UL << epnr));
}
}
@ -1255,11 +1259,11 @@ void nrf_usbd_ep_enable(uint8_t ep)
if (NRF_USBD_EPIN_CHECK(ep))
{
NRF_USBD->EPINEN |= 1UL<<epnr;
NRF_USBD->EPINEN |= 1UL << epnr;
}
else
{
NRF_USBD->EPOUTEN |= 1UL<<epnr;
NRF_USBD->EPOUTEN |= 1UL << epnr;
}
__ISB();
__DSB();
@ -1272,11 +1276,11 @@ void nrf_usbd_ep_disable(uint8_t ep)
if (NRF_USBD_EPIN_CHECK(ep))
{
NRF_USBD->EPINEN &= ~(1UL<<epnr);
NRF_USBD->EPINEN &= ~(1UL << epnr);
}
else
{
NRF_USBD->EPOUTEN &= ~(1UL<<epnr);
NRF_USBD->EPOUTEN &= ~(1UL << epnr);
}
__ISB();
__DSB();

21
mdk/nRFxxx.h Normal file
View file

@ -0,0 +1,21 @@
/*****************************************************************************
* SEGGER Microcontroller GmbH & Co. KG *
* Solutions for real time microcontroller applications *
*****************************************************************************
* *
* (c) 2017 SEGGER Microcontroller GmbH & Co. KG *
* *
* Internet: www.segger.com Support: support@segger.com *
* *
*****************************************************************************/
#ifndef __nRFxxx_h
#define __nRFxxx_h
#if defined(NRF51) || defined(NRF52) || defined(NRF52832_XXAB) || defined(NRF52840_XXAA) || defined(NRF52810_XXAA)
#include "nrf.h"
#endif
#endif

2
mdk/nrf.h
View file

@ -35,7 +35,7 @@ POSSIBILITY OF SUCH DAMAGE.
/* MDK version */
#define MDK_MAJOR_VERSION 8
#define MDK_MINOR_VERSION 14
#define MDK_MINOR_VERSION 15
#define MDK_MICRO_VERSION 0
/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */

2
mdk/nrf51.h
View file

@ -6,7 +6,7 @@
* nrf51 from Nordic Semiconductor.
*
* @version V522
* @date 12. May 2017
* @date 3. October 2017
*
* @note Generated with SVDConv V2.81d
* from CMSIS SVD File 'nrf51.svd' Version 522,

20969
mdk/nrf51.svd Normal file
View file

File diff suppressed because it is too large Load diff

8
mdk/nrf51422_peripherals.h
View file

@ -34,6 +34,12 @@ POSSIBILITY OF SUCH DAMAGE.
#define _NRF51422_PERIPHERALS_H
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
@ -115,6 +121,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS0_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2

12
mdk/nrf51801_peripherals.h
View file

@ -34,6 +34,12 @@ POSSIBILITY OF SUCH DAMAGE.
#define _NRF51801_PERIPHERALS_H
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
@ -111,14 +117,12 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPI_PRESENT
#define SPI_COUNT 2
/* Serial Peripheral Interface Master with DMA */
#define SPIM_PRESENT
#define SPIM_COUNT 1
/* Serial Peripheral Interface Slave with DMA */
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS0_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2

8
mdk/nrf51802_peripherals.h
View file

@ -34,6 +34,12 @@ POSSIBILITY OF SUCH DAMAGE.
#define _NRF51802_PERIPHERALS_H
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
@ -115,6 +121,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS0_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2

8
mdk/nrf51822_peripherals.h
View file

@ -34,6 +34,12 @@ POSSIBILITY OF SUCH DAMAGE.
#define _NRF51822_PERIPHERALS_H
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
@ -115,6 +121,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS0_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2

8
mdk/nrf51824_peripherals.h
View file

@ -34,6 +34,12 @@ POSSIBILITY OF SUCH DAMAGE.
#define _NRF51824_PERIPHERALS_H
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAMON_REGISTERS_PRESENT
/* Software Interrupts */
#define SWI_PRESENT
#define SWI_COUNT 6
@ -115,6 +121,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS0_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2

9
mdk/nrf51_common.ld
View file

@ -132,7 +132,7 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
@ -158,4 +158,11 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Check if text sections + data exceeds FLASH limit */
DataInitFlashUsed = __bss_start__ - __data_start__;
CodeFlashUsed = __etext - ORIGIN(FLASH);
TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed;
ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data")
}

2
mdk/nrf52.h
View file

@ -6,7 +6,7 @@
* nrf52 from Nordic Semiconductor.
*
* @version V1
* @date 12. May 2017
* @date 3. October 2017
*
* @note Generated with SVDConv V2.81d
* from CMSIS SVD File 'nrf52.svd' Version 1,

42684
mdk/nrf52.svd Normal file
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File diff suppressed because it is too large Load diff

11
mdk/nrf52810.h
View file

@ -6,7 +6,7 @@
* nrf52810 from Nordic Semiconductor.
*
* @version V1
* @date 12. May 2017
* @date 3. October 2017
*
* @note Generated with SVDConv V2.81d
* from CMSIS SVD File 'nrf52810.svd' Version 1,
@ -495,8 +495,6 @@ typedef struct { /*!< CLOCK Structure
__IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */
__I uint32_t RESERVED6[7];
__IO uint32_t CTIV; /*!< Calibration timer interval */
__I uint32_t RESERVED7[8];
__IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */
} NRF_CLOCK_Type;
@ -1254,13 +1252,12 @@ typedef struct { /*!< COMP Structure
__I uint32_t RESERVED4[63];
__IO uint32_t ENABLE; /*!< COMP enable */
__IO uint32_t PSEL; /*!< Pin select */
__IO uint32_t REFSEL; /*!< Reference source select */
__IO uint32_t REFSEL; /*!< Reference source select for single-ended mode */
__IO uint32_t EXTREFSEL; /*!< External reference select */
__I uint32_t RESERVED5[8];
__IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */
__IO uint32_t MODE; /*!< Mode configuration */
__IO uint32_t HYST; /*!< Comparator hysteresis enable */
__IO uint32_t ISOURCE; /*!< Current source select on analog input */
} NRF_COMP_Type;
@ -1391,7 +1388,7 @@ typedef struct { /*!< PDM Structure
/**
* @brief Non Volatile Memory Controller (NVMC)
* @brief Non-volatile memory controller (NVMC)
*/
typedef struct { /*!< NVMC Structure */
@ -1401,9 +1398,9 @@ typedef struct { /*!< NVMC Structure
__IO uint32_t CONFIG; /*!< Configuration register */
union {
__IO uint32_t ERASEPAGE; /*!< Register for erasing a page in code area */
__IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in code area.
Equivalent to ERASEPAGE. */
__IO uint32_t ERASEPAGE; /*!< Register for erasing a page in code area */
};
__IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */
__IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in code area.

31678
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1382
mdk/nrf52810_bitfields.h
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25
mdk/nrf52810_peripherals.h
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@ -34,6 +34,13 @@ POSSIBILITY OF SUCH DAMAGE.
#define _NRF52810_PERIPHERALS_H
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
/* Systick timer */
#define SYSTICK_PRESENT
#define SYSTICK_COUNT 1
@ -58,6 +65,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 8
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
@ -127,22 +136,32 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM0_EASYDMA_MAXCNT_SIZE 10
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 1
#define SPIS0_EASYDMA_MAXCNT_SIZE 10
/* Two Wire Interface Master with DMA */
#define TWIM_PRESENT
#define TWIM_COUNT 1
#define TWIM0_EASYDMA_MAXCNT_SIZE 10
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 1
#define TWIS0_EASYDMA_MAXCNT_SIZE 10
/* Universal Asynchronous Receiver-Transmitter with DMA */
#define UARTE_PRESENT
#define UARTE_COUNT 1
#define UARTE0_EASYDMA_MAXCNT_SIZE 10
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
@ -151,6 +170,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_EASYDMA_MAXCNT_SIZE 15
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
@ -170,9 +191,13 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM0_CH_NUM 4
#define PWM0_EASYDMA_MAXCNT_SIZE 15
/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1
#define PDM_EASYDMA_MAXCNT_SIZE 15
#endif // _NRF52810_PERIPHERALS_H

37
mdk/nrf52832_peripherals.h
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@ -34,6 +34,13 @@ POSSIBILITY OF SUCH DAMAGE.
#define _NRF52832_PERIPHERALS_H
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#define POWER_FEATURE_RAM_REGISTERS_COUNT 8
/* Floating Point Unit */
#define FPU_PRESENT
#define FPU_COUNT 1
@ -66,6 +73,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 8
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
@ -84,6 +93,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define NFCT_PRESENT
#define NFCT_COUNT 1
#define NFCT_EASYDMA_MAXCNT_SIZE 9
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
@ -156,10 +167,18 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM0_EASYDMA_MAXCNT_SIZE 8
#define SPIM1_EASYDMA_MAXCNT_SIZE 8
#define SPIM2_EASYDMA_MAXCNT_SIZE 8
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 3
#define SPIS0_EASYDMA_MAXCNT_SIZE 8
#define SPIS1_EASYDMA_MAXCNT_SIZE 8
#define SPIS2_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
@ -168,10 +187,16 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_PRESENT
#define TWIM_COUNT 2
#define TWIM0_EASYDMA_MAXCNT_SIZE 8
#define TWIM1_EASYDMA_MAXCNT_SIZE 8
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 2
#define TWIS0_EASYDMA_MAXCNT_SIZE 8
#define TWIS1_EASYDMA_MAXCNT_SIZE 8
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
@ -180,6 +205,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PRESENT
#define UARTE_COUNT 1
#define UARTE0_EASYDMA_MAXCNT_SIZE 8
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
@ -188,6 +215,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_EASYDMA_MAXCNT_SIZE 15
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
@ -217,13 +246,21 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM1_CH_NUM 4
#define PWM2_CH_NUM 4
#define PWM0_EASYDMA_MAXCNT_SIZE 15
#define PWM1_EASYDMA_MAXCNT_SIZE 15
#define PWM2_EASYDMA_MAXCNT_SIZE 15
/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1
#define PDM_EASYDMA_MAXCNT_SIZE 15
/* Inter-IC Sound Interface */
#define I2S_PRESENT
#define I2S_COUNT 1
#define I2S_EASYDMA_MAXCNT_SIZE 14
#endif // _NRF52832_PERIPHERALS_H

60
mdk/nrf52840.h
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@ -6,7 +6,7 @@
* nrf52840 from Nordic Semiconductor.
*
* @version V1
* @date 12. May 2017
* @date 3. October 2017
*
* @note Generated with SVDConv V2.81d
* from CMSIS SVD File 'nrf52840.svd' Version 1,
@ -616,8 +616,8 @@ typedef struct { /*!< UICR Structure
or GPIO */
__IO uint32_t DEBUGCTRL; /*!< Processor debug control */
__I uint32_t RESERVED2[59];
__IO uint32_t EXTSUPPLY; /*!< Enable external circuitry to be supplied from VDD pin. Applicable
in high voltage mode only. */
__IO uint32_t DCDCDRIVE0; /*!< Set drive level for REG0 DCDC mode. Using high drive will slightly
reduce DCDC efficiency. */
__IO uint32_t REGOUT0; /*!< GPIO reference voltage / external output supply voltage in high
voltage mode */
} NRF_UICR_Type;
@ -694,26 +694,31 @@ typedef struct { /*!< CLOCK Structure
__I uint32_t RESERVED1;
__IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */
__IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */
__I uint32_t RESERVED2[124];
__I uint32_t RESERVED2[5];
__IO uint32_t EVENTS_CTSTARTED; /*!< Calibration timer has been started and is ready to process new
tasks */
__IO uint32_t EVENTS_CTSTOPPED; /*!< Calibration timer has been stopped and is ready to process new
tasks */
__I uint32_t RESERVED3[117];
__IO uint32_t INTENSET; /*!< Enable interrupt */
__IO uint32_t INTENCLR; /*!< Disable interrupt */
__I uint32_t RESERVED3[63];
__I uint32_t RESERVED4[63];
__I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */
__I uint32_t HFCLKSTAT; /*!< HFCLK status */
__I uint32_t RESERVED4;
__I uint32_t RESERVED5;
__I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */
__I uint32_t LFCLKSTAT; /*!< LFCLK status */
__I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
__I uint32_t RESERVED5[62];
__I uint32_t RESERVED6[62];
__IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */
__I uint32_t RESERVED6[3];
__I uint32_t RESERVED7[3];
__IO uint32_t HFXODEBOUNCE; /*!< HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART
task. */
__I uint32_t RESERVED7[3];
__I uint32_t RESERVED8[3];
__IO uint32_t CTIV; /*!< Calibration timer interval */
__I uint32_t RESERVED8[8];
__I uint32_t RESERVED9[8];
__IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */
__I uint32_t RESERVED9[21];
__I uint32_t RESERVED10[21];
__IO uint32_t LFRCMODE; /*!< LFRC mode configuration */
} NRF_CLOCK_Type;
@ -975,7 +980,10 @@ typedef struct { /*!< SPIM Structure
__IO uint32_t CONFIG; /*!< Configuration register */
__I uint32_t RESERVED14[2];
SPIM_IFTIMING_Type IFTIMING; /*!< Unspecified */
__I uint32_t RESERVED15[22];
__IO uint32_t CSNPOL; /*!< Polarity of CSN output */
__IO uint32_t PSELDCX; /*!< Pin select for DCX signal */
__IO uint32_t DCXCNT; /*!< DCX configuration */
__I uint32_t RESERVED15[19];
__IO uint32_t ORC; /*!< Byte transmitted after TXD.MAXCNT bytes have been transmitted
in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
} NRF_SPIM_Type;
@ -1393,14 +1401,12 @@ typedef struct { /*!< TIMER Structure
__I uint32_t RESERVED3[64];
__IO uint32_t INTENSET; /*!< Enable interrupt */
__IO uint32_t INTENCLR; /*!< Disable interrupt */
__I uint32_t RESERVED4[61];
__I uint32_t STATUS; /*!< Timer status */
__I uint32_t RESERVED5[64];
__I uint32_t RESERVED4[126];
__IO uint32_t MODE; /*!< Timer mode selection */
__IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */
__I uint32_t RESERVED6;
__I uint32_t RESERVED5;
__IO uint32_t PRESCALER; /*!< Timer prescaler register */
__I uint32_t RESERVED7[11];
__I uint32_t RESERVED6[11];
__IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */
} NRF_TIMER_Type;
@ -1709,13 +1715,12 @@ typedef struct { /*!< COMP Structure
__I uint32_t RESERVED4[63];
__IO uint32_t ENABLE; /*!< COMP enable */
__IO uint32_t PSEL; /*!< Pin select */
__IO uint32_t REFSEL; /*!< Reference source select */
__IO uint32_t REFSEL; /*!< Reference source select for single-ended mode */
__IO uint32_t EXTREFSEL; /*!< External reference select */
__I uint32_t RESERVED5[8];
__IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */
__IO uint32_t MODE; /*!< Mode configuration */
__IO uint32_t HYST; /*!< Comparator hysteresis enable */
__IO uint32_t ISOURCE; /*!< Current source select on analog input */
} NRF_COMP_Type;
@ -1891,21 +1896,23 @@ typedef struct { /*!< PDM Structure
typedef struct { /*!< NVMC Structure */
__I uint32_t RESERVED0[256];
__I uint32_t READY; /*!< Ready flag */
__I uint32_t RESERVED1[64];
__I uint32_t RESERVED1;
__I uint32_t READYNEXT; /*!< Ready flag */
__I uint32_t RESERVED2[62];
__IO uint32_t CONFIG; /*!< Configuration register */
union {
__IO uint32_t ERASEPAGE; /*!< Register for erasing a page in code area */
__IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in code area.
Equivalent to ERASEPAGE. */
__IO uint32_t ERASEPAGE; /*!< Register for erasing a page in code area */
};
__IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */
__IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in code area.
Equivalent to ERASEPAGE. */
__IO uint32_t ERASEUICR; /*!< Register for erasing user information configuration registers */
__I uint32_t RESERVED2[10];
__I uint32_t RESERVED3[10];
__IO uint32_t ICACHECNF; /*!< I-code cache configuration register. */
__I uint32_t RESERVED3;
__I uint32_t RESERVED4;
__IO uint32_t IHIT; /*!< I-code cache hit counter. */
__IO uint32_t IMISS; /*!< I-code cache miss counter. */
} NRF_NVMC_Type;
@ -2138,8 +2145,7 @@ typedef struct { /*!< USBD Structure
__IO uint32_t ISOSPLIT; /*!< Controls the split of ISO buffers */
__I uint32_t FRAMECNTR; /*!< Returns the current value of the start of frame counter */
__I uint32_t RESERVED9[2];
__IO uint32_t LOWPOWER; /*!< First silicon only: Controls USBD peripheral low-power mode
during USB suspend */
__IO uint32_t LOWPOWER; /*!< Controls USBD peripheral low-power mode during USB suspend */
__IO uint32_t ISOINCONFIG; /*!< Controls the response of the ISO IN endpoint to an IN token
when no data is ready to be sent */
__I uint32_t RESERVED10[51];
@ -2231,12 +2237,12 @@ typedef struct { /*!< GPIO Structure
/**
* @brief ARM CryptoCell register interface (CRYPTOCELL)
* @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL)
*/
typedef struct { /*!< CRYPTOCELL Structure */
__I uint32_t RESERVED0[320];
__IO uint32_t ENABLE; /*!< Control power and clock for ARM CryptoCell subsystem */
__IO uint32_t ENABLE; /*!< Control power and clock for CRYPTOCELL subsystem */
} NRF_CRYPTOCELL_Type;

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225
mdk/nrf52840_bitfields.h
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@ -318,6 +318,20 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: CLOCK_INTENSET */
/* Description: Enable interrupt */
/* Bit 11 : Write '1' to Enable interrupt for CTSTOPPED event */
#define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
#define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
#define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */
/* Bit 10 : Write '1' to Enable interrupt for CTSTARTED event */
#define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
#define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
#define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */
/* Bit 4 : Write '1' to Enable interrupt for CTTO event */
#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
@ -349,6 +363,20 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: CLOCK_INTENCLR */
/* Description: Disable interrupt */
/* Bit 11 : Write '1' to Disable interrupt for CTSTOPPED event */
#define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */
#define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */
#define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */
/* Bit 10 : Write '1' to Disable interrupt for CTSTARTED event */
#define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */
#define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */
#define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
#define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */
#define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */
/* Bit 4 : Write '1' to Disable interrupt for CTTO event */
#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
@ -665,7 +693,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
/* Register: COMP_REFSEL */
/* Description: Reference source select */
/* Description: Reference source select for single-ended mode */
/* Bits 2..0 : Reference select */
#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
@ -679,11 +707,17 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: COMP_EXTREFSEL */
/* Description: External reference select */
/* Bit 0 : External analog reference select */
/* Bits 2..0 : External analog reference select */
#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */
#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */
/* Register: COMP_TH */
/* Description: Threshold configuration for hysteresis unit */
@ -699,18 +733,18 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: COMP_MODE */
/* Description: Mode configuration */
/* Bit 8 : Main operation mode */
/* Bit 8 : Main operation modes */
#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
/* Bits 1..0 : Speed and power mode */
/* Bits 1..0 : Speed and power modes */
#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
#define COMP_MODE_SP_High (2UL) /*!< High speed mode */
#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
/* Register: COMP_HYST */
/* Description: Comparator hysteresis enable */
@ -721,29 +755,18 @@ POSSIBILITY OF SUCH DAMAGE.
#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
/* Register: COMP_ISOURCE */
/* Description: Current source select on analog input */
/* Bits 1..0 : Comparator hysteresis */
#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
/* Peripheral: CRYPTOCELL */
/* Description: ARM CryptoCell register interface */
/* Description: ARM TrustZone CryptoCell register interface */
/* Register: CRYPTOCELL_ENABLE */
/* Description: Control power and clock for ARM CryptoCell subsystem */
/* Description: Control power and clock for CRYPTOCELL subsystem */
/* Bit 0 : Enable or disable the CryptoCell subsystem */
/* Bit 0 : Enable or disable the CRYPTOCELL subsystem */
#define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
#define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CryptoCell subsystem disabled */
#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CryptoCell subsystem enabled */
#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */
#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */
/* Peripheral: ECB */
@ -2082,8 +2105,8 @@ POSSIBILITY OF SUCH DAMAGE.
/* Bit 0 : Comparator hysteresis enable */
#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
#define LPCOMP_HYST_HYST_Disabled (0UL) /*!< Comparator hysteresis disabled */
#define LPCOMP_HYST_HYST_Enabled (1UL) /*!< Comparator hysteresis enabled */
/* Peripheral: MWU */
@ -4074,6 +4097,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
/* Register: NVMC_READYNEXT */
/* Description: Ready flag */
/* Bit 0 : NVMC can accept a new write operation */
#define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */
#define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */
#define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */
#define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */
/* Register: NVMC_CONFIG */
/* Description: Configuration register */
@ -4084,13 +4116,6 @@ POSSIBILITY OF SUCH DAMAGE.
#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */
#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
/* Register: NVMC_ERASEPAGE */
/* Description: Register for erasing a page in code area */
/* Bits 31..0 : Register for starting erase of a page in code area */
#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
/* Register: NVMC_ERASEPCR1 */
/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */
@ -4098,6 +4123,13 @@ POSSIBILITY OF SUCH DAMAGE.
#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
/* Register: NVMC_ERASEPAGE */
/* Description: Register for erasing a page in code area */
/* Bits 31..0 : Register for starting erase of a page in code area */
#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
/* Register: NVMC_ERASEALL */
/* Description: Register for erasing all non-volatile user memory */
@ -7993,9 +8025,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
@ -9297,7 +9329,6 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */
#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */
#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s (TX Only - RX supports both) */
@ -11083,6 +11114,39 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */
#define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */
/* Register: SPIM_CSNPOL */
/* Description: Polarity of CSN output */
/* Bit 0 : Polarity of CSN output */
#define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */
#define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */
#define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */
#define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */
/* Register: SPIM_PSELDCX */
/* Description: Pin select for DCX signal */
/* Bit 31 : Connection */
#define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
#define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
#define SPIM_PSELDCX_CONNECT_Connected (0UL) /*!< Connect */
#define SPIM_PSELDCX_CONNECT_Disconnected (1UL) /*!< Disconnect */
/* Bit 5 : Port number */
#define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */
#define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */
/* Bits 4..0 : Pin number */
#define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */
#define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */
/* Register: SPIM_DCXCNT */
/* Description: DCX configuration */
/* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */
#define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */
#define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */
/* Register: SPIM_ORC */
/* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */
@ -11266,16 +11330,16 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: SPIS_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */
/* Bits 7..0 : Maximum number of bytes in receive buffer */
/* Bits 15..0 : Maximum number of bytes in receive buffer */
#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIS_RXD_AMOUNT */
/* Description: Number of bytes received in last granted transaction */
/* Bits 7..0 : Number of bytes received in the last granted transaction */
/* Bits 15..0 : Number of bytes received in the last granted transaction */
#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIS_TXD_PTR */
/* Description: TXD data pointer */
@ -11287,16 +11351,16 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: SPIS_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */
/* Bits 7..0 : Maximum number of bytes in transmit buffer */
/* Bits 15..0 : Maximum number of bytes in transmit buffer */
#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: SPIS_TXD_AMOUNT */
/* Description: Number of bytes transmitted in last granted transaction */
/* Bits 7..0 : Number of bytes transmitted in last granted transaction */
/* Bits 15..0 : Number of bytes transmitted in last granted transaction */
#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: SPIS_CONFIG */
/* Description: Configuration register */
@ -11652,15 +11716,6 @@ POSSIBILITY OF SUCH DAMAGE.
#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
/* Register: TIMER_STATUS */
/* Description: Timer status */
/* Bit 0 : Timer status */
#define TIMER_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
#define TIMER_STATUS_STATUS_Msk (0x1UL << TIMER_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
#define TIMER_STATUS_STATUS_Stopped (0UL) /*!< Timer is stopped */
#define TIMER_STATUS_STATUS_Started (1UL) /*!< Timer is started */
/* Register: TIMER_MODE */
/* Description: Timer mode selection */
@ -12170,16 +12225,16 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIM_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */
/* Bits 7..0 : Maximum number of bytes in receive buffer */
/* Bits 15..0 : Maximum number of bytes in receive buffer */
#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIM_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIM_RXD_LIST */
/* Description: EasyDMA list type */
@ -12200,16 +12255,16 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIM_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */
/* Bits 7..0 : Maximum number of bytes in transmit buffer */
/* Bits 15..0 : Maximum number of bytes in transmit buffer */
#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIM_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIM_TXD_LIST */
/* Description: EasyDMA list type */
@ -12456,16 +12511,16 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIS_RXD_MAXCNT */
/* Description: Maximum number of bytes in RXD buffer */
/* Bits 7..0 : Maximum number of bytes in RXD buffer */
/* Bits 15..0 : Maximum number of bytes in RXD buffer */
#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIS_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last RXD transaction */
/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
/* Bits 15..0 : Number of bytes transferred in the last RXD transaction */
#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIS_TXD_PTR */
/* Description: TXD Data pointer */
@ -12477,16 +12532,16 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: TWIS_TXD_MAXCNT */
/* Description: Maximum number of bytes in TXD buffer */
/* Bits 7..0 : Maximum number of bytes in TXD buffer */
/* Bits 15..0 : Maximum number of bytes in TXD buffer */
#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: TWIS_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last TXD transaction */
/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
/* Bits 15..0 : Number of bytes transferred in the last TXD transaction */
#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: TWIS_ADDRESS */
/* Description: Description collection[0]: TWI slave address 0 */
@ -13171,16 +13226,16 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: UARTE_RXD_MAXCNT */
/* Description: Maximum number of bytes in receive buffer */
/* Bits 9..0 : Maximum number of bytes in receive buffer */
/* Bits 15..0 : Maximum number of bytes in receive buffer */
#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: UARTE_RXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 9..0 : Number of bytes transferred in the last transaction */
/* Bits 15..0 : Number of bytes transferred in the last transaction */
#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: UARTE_TXD_PTR */
/* Description: Data pointer */
@ -13192,16 +13247,16 @@ POSSIBILITY OF SUCH DAMAGE.
/* Register: UARTE_TXD_MAXCNT */
/* Description: Maximum number of bytes in transmit buffer */
/* Bits 9..0 : Maximum number of bytes in transmit buffer */
/* Bits 15..0 : Maximum number of bytes in transmit buffer */
#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
/* Register: UARTE_TXD_AMOUNT */
/* Description: Number of bytes transferred in the last transaction */
/* Bits 9..0 : Number of bytes transferred in the last transaction */
/* Bits 15..0 : Number of bytes transferred in the last transaction */
#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
/* Register: UARTE_CONFIG */
/* Description: Configuration of parity and hardware flow control */
@ -13299,14 +13354,14 @@ POSSIBILITY OF SUCH DAMAGE.
#define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */
#define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */
/* Register: UICR_EXTSUPPLY */
/* Description: Enable external circuitry to be supplied from VDD pin. Applicable in high voltage mode only. */
/* Register: UICR_DCDCDRIVE0 */
/* Description: Set drive level for REG0 DCDC mode. Using high drive will slightly reduce DCDC efficiency. */
/* Bit 0 : Enable external circuitry to be supplied from VDD pin (output of REG0 stage) */
#define UICR_EXTSUPPLY_EXTSUPPLY_Pos (0UL) /*!< Position of EXTSUPPLY field. */
#define UICR_EXTSUPPLY_EXTSUPPLY_Msk (0x1UL << UICR_EXTSUPPLY_EXTSUPPLY_Pos) /*!< Bit mask of EXTSUPPLY field. */
#define UICR_EXTSUPPLY_EXTSUPPLY_Disabled (0UL) /*!< No current can be drawn from the VDD pin */
#define UICR_EXTSUPPLY_EXTSUPPLY_Enabled (1UL) /*!< It is allowed to supply external circuitry from the VDD pin */
/* Bit 0 : Set drive level for REG0 DCDC mode. */
#define UICR_DCDCDRIVE0_DCDCDRIVE0_Pos (0UL) /*!< Position of DCDCDRIVE0 field. */
#define UICR_DCDCDRIVE0_DCDCDRIVE0_Msk (0x1UL << UICR_DCDCDRIVE0_DCDCDRIVE0_Pos) /*!< Bit mask of DCDCDRIVE0 field. */
#define UICR_DCDCDRIVE0_DCDCDRIVE0_Low (0UL) /*!< Low drive */
#define UICR_DCDCDRIVE0_DCDCDRIVE0_High (1UL) /*!< High drive */
/* Register: UICR_REGOUT0 */
/* Description: GPIO reference voltage / external output supply voltage in high voltage mode */
@ -14455,7 +14510,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */
/* Register: USBD_LOWPOWER */
/* Description: First silicon only: Controls USBD peripheral low-power mode during USB suspend */
/* Description: Controls USBD peripheral low-power mode during USB suspend */
/* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */
#define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */

46
mdk/nrf52840_peripherals.h
View file

@ -34,6 +34,15 @@ POSSIBILITY OF SUCH DAMAGE.
#define _NRF52840_PERIPHERALS_H
/* Power Peripheral */
#define POWER_PRESENT
#define POWER_COUNT 1
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
#define POWER_FEATURE_RAM_REGISTERS_COUNT 9
#define POWER_FEATURE_VDDH_PRESENT
/* Floating Point Unit */
#define FPU_PRESENT
#define FPU_COUNT 1
@ -66,6 +75,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PRESENT
#define RADIO_COUNT 1
#define RADIO_EASYDMA_MAXCNT_SIZE 8
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
@ -84,6 +95,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define NFCT_PRESENT
#define NFCT_COUNT 1
#define NFCT_EASYDMA_MAXCNT_SIZE 9
/* Peripheral to Peripheral Interconnect */
#define PPI_PRESENT
#define PPI_COUNT 1
@ -158,10 +171,19 @@ POSSIBILITY OF SUCH DAMAGE.
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
#define SPIM1_EASYDMA_MAXCNT_SIZE 16
#define SPIM2_EASYDMA_MAXCNT_SIZE 16
#define SPIM3_EASYDMA_MAXCNT_SIZE 16
/* Serial Peripheral Interface Slave with DMA*/
#define SPIS_PRESENT
#define SPIS_COUNT 3
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
#define SPIS1_EASYDMA_MAXCNT_SIZE 16
#define SPIS2_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Master */
#define TWI_PRESENT
#define TWI_COUNT 2
@ -170,10 +192,16 @@ POSSIBILITY OF SUCH DAMAGE.
#define TWIM_PRESENT
#define TWIM_COUNT 2
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
#define TWIM1_EASYDMA_MAXCNT_SIZE 16
/* Two Wire Interface Slave with DMA */
#define TWIS_PRESENT
#define TWIS_COUNT 2
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
#define TWIS1_EASYDMA_MAXCNT_SIZE 16
/* Universal Asynchronous Receiver-Transmitter */
#define UART_PRESENT
#define UART_COUNT 1
@ -182,6 +210,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define UARTE_PRESENT
#define UARTE_COUNT 2
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
#define UARTE1_EASYDMA_MAXCNT_SIZE 16
/* Quadrature Decoder */
#define QDEC_PRESENT
#define QDEC_COUNT 1
@ -190,6 +221,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define SAADC_PRESENT
#define SAADC_COUNT 1
#define SAADC_EASYDMA_MAXCNT_SIZE 15
/* GPIO Tasks and Events */
#define GPIOTE_PRESENT
#define GPIOTE_COUNT 1
@ -220,18 +253,29 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM2_CH_NUM 4
#define PWM3_CH_NUM 4
#define PWM0_EASYDMA_MAXCNT_SIZE 15
#define PWM1_EASYDMA_MAXCNT_SIZE 15
#define PWM2_EASYDMA_MAXCNT_SIZE 15
#define PWM3_EASYDMA_MAXCNT_SIZE 15
/* Pulse Density Modulator */
#define PDM_PRESENT
#define PDM_COUNT 1
#define PDM_EASYDMA_MAXCNT_SIZE 15
/* Inter-IC Sound Interface */
#define I2S_PRESENT
#define I2S_COUNT 1
#define I2S_EASYDMA_MAXCNT_SIZE 14
/* Universal Serial Bus Device */
#define USBD_PRESENT
#define USBD_COUNT 1
#define USBD_EASYDMA_MAXCNT_SIZE 7
/* ARM TrustZone Cryptocell 310 */
#define CRYPTOCELL_PRESENT
#define CRYPTOCELL_COUNT 1
@ -240,4 +284,6 @@ POSSIBILITY OF SUCH DAMAGE.
#define QSPI_PRESENT
#define QSPI_COUNT 1
#define QSPI_EASYDMA_MAXCNT_SIZE 20
#endif // _NRF52840_PERIPHERALS_H

7
mdk/nrf52_bitfields.h
View file

@ -1903,7 +1903,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
#define FICR_INFO_VARIANT_VARIANT_SPA0 (0x53504130UL) /*!< SPA0 */
#define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */
#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_PACKAGE */
@ -1915,6 +1915,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */
#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */
#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
/* Register: FICR_INFO_RAM */
@ -8146,9 +8147,9 @@ POSSIBILITY OF SUCH DAMAGE.
#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */
#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */

7
mdk/nrf52_common.ld
View file

@ -158,4 +158,11 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Check if text sections + data exceeds FLASH limit */
DataInitFlashUsed = __bss_start__ - __data_start__;
CodeFlashUsed = __etext - ORIGIN(FLASH);
TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed;
ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data")
}

6
mdk/nrf52_to_nrf52840.h
View file

@ -55,6 +55,12 @@ POSSIBILITY OF SUCH DAMAGE.
#define PSELSDA PSEL.SDA
/* LPCOMP */
/* The hysteresis control enumerated values has changed name for nRF52840 devices. */
#define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled
#define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled
/* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */
/* I2S */

9
mdk/nrf5x_common.ld
View file

@ -132,7 +132,7 @@ SECTIONS
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
@ -158,4 +158,11 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Check if text sections + data exceeds FLASH limit */
DataInitFlashUsed = __bss_start__ - __data_start__;
CodeFlashUsed = __etext - ORIGIN(FLASH);
TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed;
ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data")
}

148
mdk/ses_nRF_Startup.s Normal file
View file

@ -0,0 +1,148 @@
/*****************************************************************************
* SEGGER Microcontroller GmbH & Co. KG *
* Solutions for real time microcontroller applications *
*****************************************************************************
* *
* (c) 2017 SEGGER Microcontroller GmbH & Co. KG *
* *
* Internet: www.segger.com Support: support@segger.com *
* *
*****************************************************************************/
/*****************************************************************************
* Preprocessor Definitions *
* ------------------------ *
* NO_FPU_ENABLE *
* *
* If defined, FPU will not be enabled. *
* *
* NO_STACK_INIT *
* *
* If defined, the stack pointer will not be initialised. *
* *
* NO_SYSTEM_INIT *
* *
* If defined, the SystemInit() function will not be called. By default *
* SystemInit() is called after reset to enable the clocks and memories to *
* be initialised prior to any C startup initialisation. *
* *
* NO_VTOR_CONFIG *
* *
* If defined, the vector table offset register will not be configured. *
* *
* MEMORY_INIT *
* *
* If defined, the MemoryInit() function will be called. By default *
* MemoryInit() is called after SystemInit() to enable an external memory *
* controller. *
* *
* STACK_INIT_VAL *
* *
* If defined, specifies the initial stack pointer value. If undefined, *
* the stack pointer will be initialised to point to the end of the *
* RAM segment. *
* *
* VECTORS_IN_RAM *
* *
* If defined, the exception vectors will be copied from Flash to RAM. *
* *
*****************************************************************************/
.syntax unified
.global Reset_Handler
#ifdef INITIALIZE_USER_SECTIONS
.global InitializeUserMemorySections
#endif
.extern _vectors
.section .init, "ax"
.thumb_func
.equ VTOR_REG, 0xE000ED08
.equ FPU_CPACR_REG, 0xE000ED88
#ifndef STACK_INIT_VAL
#define STACK_INIT_VAL __RAM_segment_end__
#endif
Reset_Handler:
#ifndef NO_STACK_INIT
/* Initialise main stack */
ldr r0, =STACK_INIT_VAL
ldr r1, =0x7
bics r0, r1
mov sp, r0
#endif
#ifndef NO_SYSTEM_INIT
/* Initialise system */
ldr r0, =SystemInit
blx r0
#endif
#ifdef MEMORY_INIT
ldr r0, =MemoryInit
blx r0
#endif
#ifdef VECTORS_IN_RAM
/* Copy exception vectors into RAM */
ldr r0, =__vectors_start__
ldr r1, =__vectors_end__
ldr r2, =__vectors_ram_start__
1:
cmp r0, r1
beq 2f
ldr r3, [r0]
str r3, [r2]
adds r0, r0, #4
adds r2, r2, #4
b 1b
2:
#endif
#ifndef NO_VTOR_CONFIG
/* Configure vector table offset register */
ldr r0, =VTOR_REG
#ifdef VECTORS_IN_RAM
ldr r1, =_vectors_ram
#else
ldr r1, =_vectors
#endif
str r1, [r0]
#endif
#if (defined(__ARM_ARCH_FPV4_SP_D16__) || defined(__ARM_ARCH_FPV5_D16__)) && !defined(NO_FPU_ENABLE)
/* Enable FPU */
ldr r0, =FPU_CPACR_REG
ldr r1, [r0]
orr r1, r1, #(0xF << 20)
str r1, [r0]
dsb
isb
#endif
/* Jump to program start */
b _start
#ifdef INITIALIZE_USER_SECTIONS
.thumb_func
InitializeUserMemorySections:
ldr r0, =__start_nrf_sections
ldr r1, =__start_nrf_sections_run
ldr r2, =__end_nrf_sections_run
cmp r0, r1
beq 2f
subs r2, r2, r1
beq 2f
1:
ldrb r3, [r0]
adds r0, r0, #1
strb r3, [r1]
adds r1, r1, #1
subs r2, r2, #1
bne 1b
2:
bx lr
#endif

329
mdk/ses_nrf51_Vectors.s Normal file
View file

@ -0,0 +1,329 @@
/*****************************************************************************
* SEGGER Microcontroller GmbH & Co. KG *
* Solutions for real time microcontroller applications *
*****************************************************************************
* *
* (c) 2017 SEGGER Microcontroller GmbH & Co. KG *
* *
* Internet: www.segger.com Support: support@segger.com *
* *
*****************************************************************************/
/*****************************************************************************
* Preprocessor Definitions *
* ------------------------ *
* VECTORS_IN_RAM *
* *
* If defined, an area of RAM will large enough to store the vector table *
* will be reserved. *
* *
*****************************************************************************/
.syntax unified
.code 16
.section .init, "ax"
.align 0
/*****************************************************************************
* Default Exception Handlers *
*****************************************************************************/
.thumb_func
.weak NMI_Handler
NMI_Handler:
b .
.thumb_func
.weak HardFault_Handler
HardFault_Handler:
b .
.thumb_func
.weak SVC_Handler
SVC_Handler:
b .
.thumb_func
.weak PendSV_Handler
PendSV_Handler:
b .
.thumb_func
.weak SysTick_Handler
SysTick_Handler:
b .
.thumb_func
Dummy_Handler:
b .
#if defined(__OPTIMIZATION_SMALL)
.weak POWER_CLOCK_IRQHandler
.thumb_set POWER_CLOCK_IRQHandler,Dummy_Handler
.weak RADIO_IRQHandler
.thumb_set RADIO_IRQHandler,Dummy_Handler
.weak UART0_IRQHandler
.thumb_set UART0_IRQHandler,Dummy_Handler
.weak SPI0_TWI0_IRQHandler
.thumb_set SPI0_TWI0_IRQHandler,Dummy_Handler
.weak SPI1_TWI1_IRQHandler
.thumb_set SPI1_TWI1_IRQHandler,Dummy_Handler
.weak GPIOTE_IRQHandler
.thumb_set GPIOTE_IRQHandler,Dummy_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Dummy_Handler
.weak TIMER0_IRQHandler
.thumb_set TIMER0_IRQHandler,Dummy_Handler
.weak TIMER1_IRQHandler
.thumb_set TIMER1_IRQHandler,Dummy_Handler
.weak TIMER2_IRQHandler
.thumb_set TIMER2_IRQHandler,Dummy_Handler
.weak RTC0_IRQHandler
.thumb_set RTC0_IRQHandler,Dummy_Handler
.weak TEMP_IRQHandler
.thumb_set TEMP_IRQHandler,Dummy_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Dummy_Handler
.weak ECB_IRQHandler
.thumb_set ECB_IRQHandler,Dummy_Handler
.weak CCM_AAR_IRQHandler
.thumb_set CCM_AAR_IRQHandler,Dummy_Handler
.weak WDT_IRQHandler
.thumb_set WDT_IRQHandler,Dummy_Handler
.weak RTC1_IRQHandler
.thumb_set RTC1_IRQHandler,Dummy_Handler
.weak QDEC_IRQHandler
.thumb_set QDEC_IRQHandler,Dummy_Handler
.weak LPCOMP_IRQHandler
.thumb_set LPCOMP_IRQHandler,Dummy_Handler
.weak SWI0_IRQHandler
.thumb_set SWI0_IRQHandler,Dummy_Handler
.weak SWI1_IRQHandler
.thumb_set SWI1_IRQHandler,Dummy_Handler
.weak SWI2_IRQHandler
.thumb_set SWI2_IRQHandler,Dummy_Handler
.weak SWI3_IRQHandler
.thumb_set SWI3_IRQHandler,Dummy_Handler
.weak SWI4_IRQHandler
.thumb_set SWI4_IRQHandler,Dummy_Handler
.weak SWI5_IRQHandler
.thumb_set SWI5_IRQHandler,Dummy_Handler
#else
.thumb_func
.weak POWER_CLOCK_IRQHandler
POWER_CLOCK_IRQHandler:
b .
.thumb_func
.weak RADIO_IRQHandler
RADIO_IRQHandler:
b .
.thumb_func
.weak UART0_IRQHandler
UART0_IRQHandler:
b .
.thumb_func
.weak SPI0_TWI0_IRQHandler
SPI0_TWI0_IRQHandler:
b .
.thumb_func
.weak SPI1_TWI1_IRQHandler
SPI1_TWI1_IRQHandler:
b .
.thumb_func
.weak GPIOTE_IRQHandler
GPIOTE_IRQHandler:
b .
.thumb_func
.weak ADC_IRQHandler
ADC_IRQHandler:
b .
.thumb_func
.weak TIMER0_IRQHandler
TIMER0_IRQHandler:
b .
.thumb_func
.weak TIMER1_IRQHandler
TIMER1_IRQHandler:
b .
.thumb_func
.weak TIMER2_IRQHandler
TIMER2_IRQHandler:
b .
.thumb_func
.weak RTC0_IRQHandler
RTC0_IRQHandler:
b .
.thumb_func
.weak TEMP_IRQHandler
TEMP_IRQHandler:
b .
.thumb_func
.weak RNG_IRQHandler
RNG_IRQHandler:
b .
.thumb_func
.weak ECB_IRQHandler
ECB_IRQHandler:
b .
.thumb_func
.weak CCM_AAR_IRQHandler
CCM_AAR_IRQHandler:
b .
.thumb_func
.weak WDT_IRQHandler
WDT_IRQHandler:
b .
.thumb_func
.weak RTC1_IRQHandler
RTC1_IRQHandler:
b .
.thumb_func
.weak QDEC_IRQHandler
QDEC_IRQHandler:
b .
.thumb_func
.weak LPCOMP_IRQHandler
LPCOMP_IRQHandler:
b .
.thumb_func
.weak SWI0_IRQHandler
SWI0_IRQHandler:
b .
.thumb_func
.weak SWI1_IRQHandler
SWI1_IRQHandler:
b .
.thumb_func
.weak SWI2_IRQHandler
SWI2_IRQHandler:
b .
.thumb_func
.weak SWI3_IRQHandler
SWI3_IRQHandler:
b .
.thumb_func
.weak SWI4_IRQHandler
SWI4_IRQHandler:
b .
.thumb_func
.weak SWI5_IRQHandler
SWI5_IRQHandler:
b .
#endif
/*****************************************************************************
* Vector Table *
*****************************************************************************/
.section .vectors, "ax"
.align 0
.global _vectors
.extern __stack_end__
.extern Reset_Handler
_vectors:
.word __stack_end__
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SVC_Handler
.word 0 /* Reserved */
.word 0 /* Reserved */
.word PendSV_Handler
.word SysTick_Handler
.word POWER_CLOCK_IRQHandler
.word RADIO_IRQHandler
.word UART0_IRQHandler
.word SPI0_TWI0_IRQHandler
.word SPI1_TWI1_IRQHandler
.word Dummy_Handler /* Reserved */
.word GPIOTE_IRQHandler
.word ADC_IRQHandler
.word TIMER0_IRQHandler
.word TIMER1_IRQHandler
.word TIMER2_IRQHandler
.word RTC0_IRQHandler
.word TEMP_IRQHandler
.word RNG_IRQHandler
.word ECB_IRQHandler
.word CCM_AAR_IRQHandler
.word WDT_IRQHandler
.word RTC1_IRQHandler
.word QDEC_IRQHandler
.word LPCOMP_IRQHandler
.word SWI0_IRQHandler
.word SWI1_IRQHandler
.word SWI2_IRQHandler
.word SWI3_IRQHandler
.word SWI4_IRQHandler
.word SWI5_IRQHandler
_vectors_end:
#ifdef VECTORS_IN_RAM
.section .vectors_ram, "ax"
.align 0
.global _vectors_ram
_vectors_ram:
.space _vectors_end - _vectors, 0
#endif

369
mdk/ses_nrf52810_Vectors.s Normal file
View file

@ -0,0 +1,369 @@
/*****************************************************************************
* SEGGER Microcontroller GmbH & Co. KG *
* Solutions for real time microcontroller applications *
*****************************************************************************
* *
* (c) 2017 SEGGER Microcontroller GmbH & Co. KG *
* *
* Internet: www.segger.com Support: support@segger.com *
* *
*****************************************************************************/
/*****************************************************************************
* Preprocessor Definitions *
* ------------------------ *
* VECTORS_IN_RAM *
* *
* If defined, an area of RAM will large enough to store the vector table *
* will be reserved. *
* *
*****************************************************************************/
.syntax unified
.code 16
.section .init, "ax"
.align 0
/*****************************************************************************
* Default Exception Handlers *
*****************************************************************************/
.thumb_func
.weak NMI_Handler
NMI_Handler:
b .
.thumb_func
.weak HardFault_Handler
HardFault_Handler:
b .
.thumb_func
.weak MemoryManagement_Handler
MemoryManagement_Handler:
b .
.thumb_func
.weak BusFault_Handler
BusFault_Handler:
b .
.thumb_func
.weak UsageFault_Handler
UsageFault_Handler:
b .
.thumb_func
.weak SVC_Handler
SVC_Handler:
b .
.thumb_func
.weak DebugMon_Handler
DebugMon_Handler:
b .
.thumb_func
.weak PendSV_Handler
PendSV_Handler:
b .
.thumb_func
.weak SysTick_Handler
SysTick_Handler:
b .
.thumb_func
Dummy_Handler:
b .
#if defined(__OPTIMIZATION_SMALL)
.weak POWER_CLOCK_IRQHandler
.thumb_set POWER_CLOCK_IRQHandler,Dummy_Handler
.weak RADIO_IRQHandler
.thumb_set RADIO_IRQHandler,Dummy_Handler
.weak UARTE0_IRQHandler
.thumb_set UARTE0_IRQHandler,Dummy_Handler
.weak TWIM0_TWIS0_IRQHandler
.thumb_set TWIM0_TWIS0_IRQHandler,Dummy_Handler
.weak SPIM0_SPIS0_IRQHandler
.thumb_set SPIM0_SPIS0_IRQHandler,Dummy_Handler
.weak GPIOTE_IRQHandler
.thumb_set GPIOTE_IRQHandler,Dummy_Handler
.weak SAADC_IRQHandler
.thumb_set SAADC_IRQHandler,Dummy_Handler
.weak TIMER0_IRQHandler
.thumb_set TIMER0_IRQHandler,Dummy_Handler
.weak TIMER1_IRQHandler
.thumb_set TIMER1_IRQHandler,Dummy_Handler
.weak TIMER2_IRQHandler
.thumb_set TIMER2_IRQHandler,Dummy_Handler
.weak RTC0_IRQHandler
.thumb_set RTC0_IRQHandler,Dummy_Handler
.weak TEMP_IRQHandler
.thumb_set TEMP_IRQHandler,Dummy_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Dummy_Handler
.weak ECB_IRQHandler
.thumb_set ECB_IRQHandler,Dummy_Handler
.weak CCM_AAR_IRQHandler
.thumb_set CCM_AAR_IRQHandler,Dummy_Handler
.weak WDT_IRQHandler
.thumb_set WDT_IRQHandler,Dummy_Handler
.weak RTC1_IRQHandler
.thumb_set RTC1_IRQHandler,Dummy_Handler
.weak QDEC_IRQHandler
.thumb_set QDEC_IRQHandler,Dummy_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Dummy_Handler
.weak SWI0_EGU0_IRQHandler
.thumb_set SWI0_EGU0_IRQHandler,Dummy_Handler
.weak SWI1_EGU1_IRQHandler
.thumb_set SWI1_EGU1_IRQHandler,Dummy_Handler
.weak SWI2_IRQHandler
.thumb_set SWI2_IRQHandler,Dummy_Handler
.weak SWI3_IRQHandler
.thumb_set SWI3_IRQHandler,Dummy_Handler
.weak SWI4_IRQHandler
.thumb_set SWI4_IRQHandler,Dummy_Handler
.weak SWI5_IRQHandler
.thumb_set SWI5_IRQHandler,Dummy_Handler
.weak PWM0_IRQHandler
.thumb_set PWM0_IRQHandler,Dummy_Handler
.weak PDM_IRQHandler
.thumb_set PDM_IRQHandler,Dummy_Handler
#else
.thumb_func
.weak POWER_CLOCK_IRQHandler
POWER_CLOCK_IRQHandler:
b .
.thumb_func
.weak RADIO_IRQHandler
RADIO_IRQHandler:
b .
.thumb_func
.weak UARTE0_IRQHandler
UARTE0_IRQHandler:
b .
.thumb_func
.weak TWIM0_TWIS0_IRQHandler
TWIM0_TWIS0_IRQHandler:
b .
.thumb_func
.weak SPIM0_SPIS0_IRQHandler
SPIM0_SPIS0_IRQHandler:
b .
.thumb_func
.weak GPIOTE_IRQHandler
GPIOTE_IRQHandler:
b .
.thumb_func
.weak SAADC_IRQHandler
SAADC_IRQHandler:
b .
.thumb_func
.weak TIMER0_IRQHandler
TIMER0_IRQHandler:
b .
.thumb_func
.weak TIMER1_IRQHandler
TIMER1_IRQHandler:
b .
.thumb_func
.weak TIMER2_IRQHandler
TIMER2_IRQHandler:
b .
.thumb_func
.weak RTC0_IRQHandler
RTC0_IRQHandler:
b .
.thumb_func
.weak TEMP_IRQHandler
TEMP_IRQHandler:
b .
.thumb_func
.weak RNG_IRQHandler
RNG_IRQHandler:
b .
.thumb_func
.weak ECB_IRQHandler
ECB_IRQHandler:
b .
.thumb_func
.weak CCM_AAR_IRQHandler
CCM_AAR_IRQHandler:
b .
.thumb_func
.weak WDT_IRQHandler
WDT_IRQHandler:
b .
.thumb_func
.weak RTC1_IRQHandler
RTC1_IRQHandler:
b .
.thumb_func
.weak QDEC_IRQHandler
QDEC_IRQHandler:
b .
.thumb_func
.weak COMP_IRQHandler
COMP_IRQHandler:
b .
.thumb_func
.weak SWI0_EGU0_IRQHandler
SWI0_EGU0_IRQHandler:
b .
.thumb_func
.weak SWI1_EGU1_IRQHandler
SWI1_EGU1_IRQHandler:
b .
.thumb_func
.weak SWI2_IRQHandler
SWI2_IRQHandler:
b .
.thumb_func
.weak SWI3_IRQHandler
SWI3_IRQHandler:
b .
.thumb_func
.weak SWI4_IRQHandler
SWI4_IRQHandler:
b .
.thumb_func
.weak SWI5_IRQHandler
SWI5_IRQHandler:
b .
.thumb_func
.weak PWM0_IRQHandler
PWM0_IRQHandler:
b .
.thumb_func
.weak PDM_IRQHandler
PDM_IRQHandler:
b .
#endif
/*****************************************************************************
* Vector Table *
*****************************************************************************/
.section .vectors, "ax"
.align 0
.global _vectors
.extern __stack_end__
.extern Reset_Handler
_vectors:
.word __stack_end__
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemoryManagement_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SVC_Handler
.word DebugMon_Handler
.word 0 /* Reserved */
.word PendSV_Handler
.word SysTick_Handler
.word POWER_CLOCK_IRQHandler
.word RADIO_IRQHandler
.word UARTE0_IRQHandler
.word TWIM0_TWIS0_IRQHandler
.word SPIM0_SPIS0_IRQHandler
.word 0
.word GPIOTE_IRQHandler
.word SAADC_IRQHandler
.word TIMER0_IRQHandler
.word TIMER1_IRQHandler
.word TIMER2_IRQHandler
.word RTC0_IRQHandler
.word TEMP_IRQHandler
.word RNG_IRQHandler
.word ECB_IRQHandler
.word CCM_AAR_IRQHandler
.word WDT_IRQHandler
.word RTC1_IRQHandler
.word QDEC_IRQHandler
.word COMP_IRQHandler
.word SWI0_EGU0_IRQHandler
.word SWI1_EGU1_IRQHandler
.word SWI2_IRQHandler
.word SWI3_IRQHandler
.word SWI4_IRQHandler
.word SWI5_IRQHandler
.word 0
.word 0
.word PWM0_IRQHandler
.word PDM_IRQHandler
_vectors_end:
#ifdef VECTORS_IN_RAM
.section .vectors_ram, "ax"
.align 0
.global _vectors_ram
_vectors_ram:
.space _vectors_end - _vectors, 0
#endif

515
mdk/ses_nrf52840_Vectors.s Normal file
View file

@ -0,0 +1,515 @@
/*****************************************************************************
* SEGGER Microcontroller GmbH & Co. KG *
* Solutions for real time microcontroller applications *
*****************************************************************************
* *
* (c) 2017 SEGGER Microcontroller GmbH & Co. KG *
* *
* Internet: www.segger.com Support: support@segger.com *
* *
*****************************************************************************/
/*****************************************************************************
* Preprocessor Definitions *
* ------------------------ *
* VECTORS_IN_RAM *
* *
* If defined, an area of RAM will large enough to store the vector table *
* will be reserved. *
* *
*****************************************************************************/
.syntax unified
.code 16
.section .init, "ax"
.align 0
/*****************************************************************************
* Default Exception Handlers *
*****************************************************************************/
.thumb_func
.weak NMI_Handler
NMI_Handler:
b .
.thumb_func
.weak HardFault_Handler
HardFault_Handler:
b .
.thumb_func
.weak MemoryManagement_Handler
MemoryManagement_Handler:
b .
.thumb_func
.weak BusFault_Handler
BusFault_Handler:
b .
.thumb_func
.weak UsageFault_Handler
UsageFault_Handler:
b .
.thumb_func
.weak SVC_Handler
SVC_Handler:
b .
.thumb_func
.weak DebugMon_Handler
DebugMon_Handler:
b .
.thumb_func
.weak PendSV_Handler
PendSV_Handler:
b .
.thumb_func
.weak SysTick_Handler
SysTick_Handler:
b .
.thumb_func
Dummy_Handler:
b .
#if defined(__OPTIMIZATION_SMALL)
.weak POWER_CLOCK_IRQHandler
.thumb_set POWER_CLOCK_IRQHandler,Dummy_Handler
.weak RADIO_IRQHandler
.thumb_set RADIO_IRQHandler,Dummy_Handler
.weak UARTE0_UART0_IRQHandler
.thumb_set UARTE0_UART0_IRQHandler,Dummy_Handler
.weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
.thumb_set SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler,Dummy_Handler
.weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
.thumb_set SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler,Dummy_Handler
.weak NFCT_IRQHandler
.thumb_set NFCT_IRQHandler,Dummy_Handler
.weak GPIOTE_IRQHandler
.thumb_set GPIOTE_IRQHandler,Dummy_Handler
.weak SAADC_IRQHandler
.thumb_set SAADC_IRQHandler,Dummy_Handler
.weak TIMER0_IRQHandler
.thumb_set TIMER0_IRQHandler,Dummy_Handler
.weak TIMER1_IRQHandler
.thumb_set TIMER1_IRQHandler,Dummy_Handler
.weak TIMER2_IRQHandler
.thumb_set TIMER2_IRQHandler,Dummy_Handler
.weak RTC0_IRQHandler
.thumb_set RTC0_IRQHandler,Dummy_Handler
.weak TEMP_IRQHandler
.thumb_set TEMP_IRQHandler,Dummy_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Dummy_Handler
.weak ECB_IRQHandler
.thumb_set ECB_IRQHandler,Dummy_Handler
.weak CCM_AAR_IRQHandler
.thumb_set CCM_AAR_IRQHandler,Dummy_Handler
.weak WDT_IRQHandler
.thumb_set WDT_IRQHandler,Dummy_Handler
.weak RTC1_IRQHandler
.thumb_set RTC1_IRQHandler,Dummy_Handler
.weak QDEC_IRQHandler
.thumb_set QDEC_IRQHandler,Dummy_Handler
.weak COMP_LPCOMP_IRQHandler
.thumb_set COMP_LPCOMP_IRQHandler,Dummy_Handler
.weak SWI0_EGU0_IRQHandler
.thumb_set SWI0_EGU0_IRQHandler,Dummy_Handler
.weak SWI1_EGU1_IRQHandler
.thumb_set SWI1_EGU1_IRQHandler,Dummy_Handler
.weak SWI2_EGU2_IRQHandler
.thumb_set SWI2_EGU2_IRQHandler,Dummy_Handler
.weak SWI3_EGU3_IRQHandler
.thumb_set SWI3_EGU3_IRQHandler,Dummy_Handler
.weak SWI4_EGU4_IRQHandler
.thumb_set SWI4_EGU4_IRQHandler,Dummy_Handler
.weak SWI5_EGU5_IRQHandler
.thumb_set SWI5_EGU5_IRQHandler,Dummy_Handler
.weak TIMER3_IRQHandler
.thumb_set TIMER3_IRQHandler,Dummy_Handler
.weak TIMER4_IRQHandler
.thumb_set TIMER4_IRQHandler,Dummy_Handler
.weak PWM0_IRQHandler
.thumb_set PWM0_IRQHandler,Dummy_Handler
.weak PDM_IRQHandler
.thumb_set PDM_IRQHandler,Dummy_Handler
.weak MWU_IRQHandler
.thumb_set MWU_IRQHandler,Dummy_Handler
.weak PWM1_IRQHandler
.thumb_set PWM1_IRQHandler,Dummy_Handler
.weak PWM2_IRQHandler
.thumb_set PWM2_IRQHandler,Dummy_Handler
.weak SPIM2_SPIS2_SPI2_IRQHandler
.thumb_set SPIM2_SPIS2_SPI2_IRQHandler,Dummy_Handler
.weak RTC2_IRQHandler
.thumb_set RTC2_IRQHandler,Dummy_Handler
.weak I2S_IRQHandler
.thumb_set I2S_IRQHandler,Dummy_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Dummy_Handler
.weak USBD_IRQHandler
.thumb_set USBD_IRQHandler,Dummy_Handler
.weak UARTE1_IRQHandler
.thumb_set UARTE1_IRQHandler,Dummy_Handler
.weak QSPI_IRQHandler
.thumb_set QSPI_IRQHandler,Dummy_Handler
.weak CRYPTOCELL_IRQHandler
.thumb_set CRYPTOCELL_IRQHandler,Dummy_Handler
.weak SPIM3_IRQHandler
.thumb_set SPIM3_IRQHandler,Dummy_Handler
.weak PWM3_IRQHandler
.thumb_set PWM3_IRQHandler,Dummy_Handler
#else
.thumb_func
.weak POWER_CLOCK_IRQHandler
POWER_CLOCK_IRQHandler:
b .
.thumb_func
.weak RADIO_IRQHandler
RADIO_IRQHandler:
b .
.thumb_func
.weak UARTE0_UART0_IRQHandler
UARTE0_UART0_IRQHandler:
b .
.thumb_func
.weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler:
b .
.thumb_func
.weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler:
b .
.thumb_func
.weak NFCT_IRQHandler
NFCT_IRQHandler:
b .
.thumb_func
.weak GPIOTE_IRQHandler
GPIOTE_IRQHandler:
b .
.thumb_func
.weak SAADC_IRQHandler
SAADC_IRQHandler:
b .
.thumb_func
.weak TIMER0_IRQHandler
TIMER0_IRQHandler:
b .
.thumb_func
.weak TIMER1_IRQHandler
TIMER1_IRQHandler:
b .
.thumb_func
.weak TIMER2_IRQHandler
TIMER2_IRQHandler:
b .
.thumb_func
.weak RTC0_IRQHandler
RTC0_IRQHandler:
b .
.thumb_func
.weak TEMP_IRQHandler
TEMP_IRQHandler:
b .
.thumb_func
.weak RNG_IRQHandler
RNG_IRQHandler:
b .
.thumb_func
.weak ECB_IRQHandler
ECB_IRQHandler:
b .
.thumb_func
.weak CCM_AAR_IRQHandler
CCM_AAR_IRQHandler:
b .
.thumb_func
.weak WDT_IRQHandler
WDT_IRQHandler:
b .
.thumb_func
.weak RTC1_IRQHandler
RTC1_IRQHandler:
b .
.thumb_func
.weak QDEC_IRQHandler
QDEC_IRQHandler:
b .
.thumb_func
.weak COMP_LPCOMP_IRQHandler
COMP_LPCOMP_IRQHandler:
b .
.thumb_func
.weak SWI0_EGU0_IRQHandler
SWI0_EGU0_IRQHandler:
b .
.thumb_func
.weak SWI1_EGU1_IRQHandler
SWI1_EGU1_IRQHandler:
b .
.thumb_func
.weak SWI2_EGU2_IRQHandler
SWI2_EGU2_IRQHandler:
b .
.thumb_func
.weak SWI3_EGU3_IRQHandler
SWI3_EGU3_IRQHandler:
b .
.thumb_func
.weak SWI4_EGU4_IRQHandler
SWI4_EGU4_IRQHandler:
b .
.thumb_func
.weak SWI5_EGU5_IRQHandler
SWI5_EGU5_IRQHandler:
b .
.thumb_func
.weak TIMER3_IRQHandler
TIMER3_IRQHandler:
b .
.thumb_func
.weak TIMER4_IRQHandler
TIMER4_IRQHandler:
b .
.thumb_func
.weak PWM0_IRQHandler
PWM0_IRQHandler:
b .
.thumb_func
.weak PDM_IRQHandler
PDM_IRQHandler:
b .
.thumb_func
.weak MWU_IRQHandler
MWU_IRQHandler:
b .
.thumb_func
.weak PWM1_IRQHandler
PWM1_IRQHandler:
b .
.thumb_func
.weak PWM2_IRQHandler
PWM2_IRQHandler:
b .
.thumb_func
.weak SPIM2_SPIS2_SPI2_IRQHandler
SPIM2_SPIS2_SPI2_IRQHandler:
b .
.thumb_func
.weak RTC2_IRQHandler
RTC2_IRQHandler:
b .
.thumb_func
.weak I2S_IRQHandler
I2S_IRQHandler:
b .
.thumb_func
.weak FPU_IRQHandler
FPU_IRQHandler:
b .
.thumb_func
.weak USBD_IRQHandler
USBD_IRQHandler:
b .
.thumb_func
.weak UARTE1_IRQHandler
UARTE1_IRQHandler:
b .
.thumb_func
.weak QSPI_IRQHandler
QSPI_IRQHandler:
b .
.thumb_func
.weak CRYPTOCELL_IRQHandler
CRYPTOCELL_IRQHandler:
b .
.thumb_func
.weak SPIM3_IRQHandler
SPIM3_IRQHandler:
b .
.thumb_func
.weak PWM3_IRQHandler
PWM3_IRQHandler:
b .
#endif
/*****************************************************************************
* Vector Table *
*****************************************************************************/
.section .vectors, "ax"
.align 0
.global _vectors
.extern __stack_end__
.extern Reset_Handler
_vectors:
.word __stack_end__
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemoryManagement_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SVC_Handler
.word DebugMon_Handler
.word 0 /* Reserved */
.word PendSV_Handler
.word SysTick_Handler
.word POWER_CLOCK_IRQHandler
.word RADIO_IRQHandler
.word UARTE0_UART0_IRQHandler
.word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
.word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
.word NFCT_IRQHandler
.word GPIOTE_IRQHandler
.word SAADC_IRQHandler
.word TIMER0_IRQHandler
.word TIMER1_IRQHandler
.word TIMER2_IRQHandler
.word RTC0_IRQHandler
.word TEMP_IRQHandler
.word RNG_IRQHandler
.word ECB_IRQHandler
.word CCM_AAR_IRQHandler
.word WDT_IRQHandler
.word RTC1_IRQHandler
.word QDEC_IRQHandler
.word COMP_LPCOMP_IRQHandler
.word SWI0_EGU0_IRQHandler
.word SWI1_EGU1_IRQHandler
.word SWI2_EGU2_IRQHandler
.word SWI3_EGU3_IRQHandler
.word SWI4_EGU4_IRQHandler
.word SWI5_EGU5_IRQHandler
.word TIMER3_IRQHandler
.word TIMER4_IRQHandler
.word PWM0_IRQHandler
.word PDM_IRQHandler
.word Dummy_Handler /* Reserved */
.word Dummy_Handler /* Reserved */
.word MWU_IRQHandler
.word PWM1_IRQHandler
.word PWM2_IRQHandler
.word SPIM2_SPIS2_SPI2_IRQHandler
.word RTC2_IRQHandler
.word I2S_IRQHandler
.word FPU_IRQHandler
.word USBD_IRQHandler
.word UARTE1_IRQHandler
.word QSPI_IRQHandler
.word CRYPTOCELL_IRQHandler
.word Dummy_Handler /* Reserved */
.word Dummy_Handler /* Reserved */
.word PWM3_IRQHandler
.word Dummy_Handler /* Reserved */
.word SPIM3_IRQHandler
_vectors_end:
#ifdef VECTORS_IN_RAM
.section .vectors_ram, "ax"
.align 0
.global _vectors_ram
_vectors_ram:
.space _vectors_end - _vectors, 0
#endif

458
mdk/ses_nrf52_Vectors.s Normal file
View file

@ -0,0 +1,458 @@
/*****************************************************************************
* SEGGER Microcontroller GmbH & Co. KG *
* Solutions for real time microcontroller applications *
*****************************************************************************
* *
* (c) 2017 SEGGER Microcontroller GmbH & Co. KG *
* *
* Internet: www.segger.com Support: support@segger.com *
* *
*****************************************************************************/
/*****************************************************************************
* Preprocessor Definitions *
* ------------------------ *
* VECTORS_IN_RAM *
* *
* If defined, an area of RAM will large enough to store the vector table *
* will be reserved. *
* *
*****************************************************************************/
.syntax unified
.code 16
.section .init, "ax"
.align 0
/*****************************************************************************
* Default Exception Handlers *
*****************************************************************************/
.thumb_func
.weak NMI_Handler
NMI_Handler:
b .
.thumb_func
.weak HardFault_Handler
HardFault_Handler:
b .
.thumb_func
.weak MemoryManagement_Handler
MemoryManagement_Handler:
b .
.thumb_func
.weak BusFault_Handler
BusFault_Handler:
b .
.thumb_func
.weak UsageFault_Handler
UsageFault_Handler:
b .
.thumb_func
.weak SVC_Handler
SVC_Handler:
b .
.thumb_func
.weak DebugMon_Handler
DebugMon_Handler:
b .
.thumb_func
.weak PendSV_Handler
PendSV_Handler:
b .
.thumb_func
.weak SysTick_Handler
SysTick_Handler:
b .
.thumb_func
Dummy_Handler:
b .
#if defined(__OPTIMIZATION_SMALL)
.weak POWER_CLOCK_IRQHandler
.thumb_set POWER_CLOCK_IRQHandler,Dummy_Handler
.weak RADIO_IRQHandler
.thumb_set RADIO_IRQHandler,Dummy_Handler
.weak UARTE0_UART0_IRQHandler
.thumb_set UARTE0_UART0_IRQHandler,Dummy_Handler
.weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
.thumb_set SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler,Dummy_Handler
.weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
.thumb_set SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler,Dummy_Handler
.weak NFCT_IRQHandler
.thumb_set NFCT_IRQHandler,Dummy_Handler
.weak GPIOTE_IRQHandler
.thumb_set GPIOTE_IRQHandler,Dummy_Handler
.weak SAADC_IRQHandler
.thumb_set SAADC_IRQHandler,Dummy_Handler
.weak TIMER0_IRQHandler
.thumb_set TIMER0_IRQHandler,Dummy_Handler
.weak TIMER1_IRQHandler
.thumb_set TIMER1_IRQHandler,Dummy_Handler
.weak TIMER2_IRQHandler
.thumb_set TIMER2_IRQHandler,Dummy_Handler
.weak RTC0_IRQHandler
.thumb_set RTC0_IRQHandler,Dummy_Handler
.weak TEMP_IRQHandler
.thumb_set TEMP_IRQHandler,Dummy_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Dummy_Handler
.weak ECB_IRQHandler
.thumb_set ECB_IRQHandler,Dummy_Handler
.weak CCM_AAR_IRQHandler
.thumb_set CCM_AAR_IRQHandler,Dummy_Handler
.weak WDT_IRQHandler
.thumb_set WDT_IRQHandler,Dummy_Handler
.weak RTC1_IRQHandler
.thumb_set RTC1_IRQHandler,Dummy_Handler
.weak QDEC_IRQHandler
.thumb_set QDEC_IRQHandler,Dummy_Handler
.weak COMP_LPCOMP_IRQHandler
.thumb_set COMP_LPCOMP_IRQHandler,Dummy_Handler
.weak SWI0_EGU0_IRQHandler
.thumb_set SWI0_EGU0_IRQHandler,Dummy_Handler
.weak SWI1_EGU1_IRQHandler
.thumb_set SWI1_EGU1_IRQHandler,Dummy_Handler
.weak SWI2_EGU2_IRQHandler
.thumb_set SWI2_EGU2_IRQHandler,Dummy_Handler
.weak SWI3_EGU3_IRQHandler
.thumb_set SWI3_EGU3_IRQHandler,Dummy_Handler
.weak SWI4_EGU4_IRQHandler
.thumb_set SWI4_EGU4_IRQHandler,Dummy_Handler
.weak SWI5_EGU5_IRQHandler
.thumb_set SWI5_EGU5_IRQHandler,Dummy_Handler
.weak TIMER3_IRQHandler
.thumb_set TIMER3_IRQHandler,Dummy_Handler
.weak TIMER4_IRQHandler
.thumb_set TIMER4_IRQHandler,Dummy_Handler
.weak PWM0_IRQHandler
.thumb_set PWM0_IRQHandler,Dummy_Handler
.weak PDM_IRQHandler
.thumb_set PDM_IRQHandler,Dummy_Handler
.weak MWU_IRQHandler
.thumb_set MWU_IRQHandler,Dummy_Handler
.weak PWM1_IRQHandler
.thumb_set PWM1_IRQHandler,Dummy_Handler
.weak PWM2_IRQHandler
.thumb_set PWM2_IRQHandler,Dummy_Handler
.weak SPIM2_SPIS2_SPI2_IRQHandler
.thumb_set SPIM2_SPIS2_SPI2_IRQHandler,Dummy_Handler
.weak RTC2_IRQHandler
.thumb_set RTC2_IRQHandler,Dummy_Handler
.weak I2S_IRQHandler
.thumb_set I2S_IRQHandler,Dummy_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Dummy_Handler
#else
.thumb_func
.weak POWER_CLOCK_IRQHandler
POWER_CLOCK_IRQHandler:
b .
.thumb_func
.weak RADIO_IRQHandler
RADIO_IRQHandler:
b .
.thumb_func
.weak UARTE0_UART0_IRQHandler
UARTE0_UART0_IRQHandler:
b .
.thumb_func
.weak SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler:
b .
.thumb_func
.weak SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler:
b .
.thumb_func
.weak NFCT_IRQHandler
NFCT_IRQHandler:
b .
.thumb_func
.weak GPIOTE_IRQHandler
GPIOTE_IRQHandler:
b .
.thumb_func
.weak SAADC_IRQHandler
SAADC_IRQHandler:
b .
.thumb_func
.weak TIMER0_IRQHandler
TIMER0_IRQHandler:
b .
.thumb_func
.weak TIMER1_IRQHandler
TIMER1_IRQHandler:
b .
.thumb_func
.weak TIMER2_IRQHandler
TIMER2_IRQHandler:
b .
.thumb_func
.weak RTC0_IRQHandler
RTC0_IRQHandler:
b .
.thumb_func
.weak TEMP_IRQHandler
TEMP_IRQHandler:
b .
.thumb_func
.weak RNG_IRQHandler
RNG_IRQHandler:
b .
.thumb_func
.weak ECB_IRQHandler
ECB_IRQHandler:
b .
.thumb_func
.weak CCM_AAR_IRQHandler
CCM_AAR_IRQHandler:
b .
.thumb_func
.weak WDT_IRQHandler
WDT_IRQHandler:
b .
.thumb_func
.weak RTC1_IRQHandler
RTC1_IRQHandler:
b .
.thumb_func
.weak QDEC_IRQHandler
QDEC_IRQHandler:
b .
.thumb_func
.weak COMP_LPCOMP_IRQHandler
COMP_LPCOMP_IRQHandler:
b .
.thumb_func
.weak SWI0_EGU0_IRQHandler
SWI0_EGU0_IRQHandler:
b .
.thumb_func
.weak SWI1_EGU1_IRQHandler
SWI1_EGU1_IRQHandler:
b .
.thumb_func
.weak SWI2_EGU2_IRQHandler
SWI2_EGU2_IRQHandler:
b .
.thumb_func
.weak SWI3_EGU3_IRQHandler
SWI3_EGU3_IRQHandler:
b .
.thumb_func
.weak SWI4_EGU4_IRQHandler
SWI4_EGU4_IRQHandler:
b .
.thumb_func
.weak SWI5_EGU5_IRQHandler
SWI5_EGU5_IRQHandler:
b .
.thumb_func
.weak TIMER3_IRQHandler
TIMER3_IRQHandler:
b .
.thumb_func
.weak TIMER4_IRQHandler
TIMER4_IRQHandler:
b .
.thumb_func
.weak PWM0_IRQHandler
PWM0_IRQHandler:
b .
.thumb_func
.weak PDM_IRQHandler
PDM_IRQHandler:
b .
.thumb_func
.weak MWU_IRQHandler
MWU_IRQHandler:
b .
.thumb_func
.weak PWM1_IRQHandler
PWM1_IRQHandler:
b .
.thumb_func
.weak PWM2_IRQHandler
PWM2_IRQHandler:
b .
.thumb_func
.weak SPIM2_SPIS2_SPI2_IRQHandler
SPIM2_SPIS2_SPI2_IRQHandler:
b .
.thumb_func
.weak RTC2_IRQHandler
RTC2_IRQHandler:
b .
.thumb_func
.weak I2S_IRQHandler
I2S_IRQHandler:
b .
.thumb_func
.weak FPU_IRQHandler
FPU_IRQHandler:
b .
#endif
/*****************************************************************************
* Vector Table *
*****************************************************************************/
.section .vectors, "ax"
.align 0
.global _vectors
.extern __stack_end__
.extern Reset_Handler
_vectors:
.word __stack_end__
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemoryManagement_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SVC_Handler
.word DebugMon_Handler
.word 0 /* Reserved */
.word PendSV_Handler
.word SysTick_Handler
.word POWER_CLOCK_IRQHandler
.word RADIO_IRQHandler
.word UARTE0_UART0_IRQHandler
.word SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
.word SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
.word NFCT_IRQHandler
.word GPIOTE_IRQHandler
.word SAADC_IRQHandler
.word TIMER0_IRQHandler
.word TIMER1_IRQHandler
.word TIMER2_IRQHandler
.word RTC0_IRQHandler
.word TEMP_IRQHandler
.word RNG_IRQHandler
.word ECB_IRQHandler
.word CCM_AAR_IRQHandler
.word WDT_IRQHandler
.word RTC1_IRQHandler
.word QDEC_IRQHandler
.word COMP_LPCOMP_IRQHandler
.word SWI0_EGU0_IRQHandler
.word SWI1_EGU1_IRQHandler
.word SWI2_EGU2_IRQHandler
.word SWI3_EGU3_IRQHandler
.word SWI4_EGU4_IRQHandler
.word SWI5_EGU5_IRQHandler
.word TIMER3_IRQHandler
.word TIMER4_IRQHandler
.word PWM0_IRQHandler
.word PDM_IRQHandler
.word Dummy_Handler /* Reserved */
.word Dummy_Handler /* Reserved */
.word MWU_IRQHandler
.word PWM1_IRQHandler
.word PWM2_IRQHandler
.word SPIM2_SPIS2_SPI2_IRQHandler
.word RTC2_IRQHandler
.word I2S_IRQHandler
.word FPU_IRQHandler
_vectors_end:
#ifdef VECTORS_IN_RAM
.section .vectors_ram, "ax"
.align 0
.global _vectors_ram
_vectors_ram:
.space _vectors_end - _vectors, 0
#endif

5
soc/nrfx_irqs_nrf52840.h
View file

@ -178,12 +178,7 @@ extern "C" {
// USBD_IRQn
// UARTE1_IRQn
#if NRFX_CHECK(NRFX_PRS_ENABLED) && NRFX_CHECK(NRFX_PRS_BOX_5_ENABLED)
#define nrfx_prs_box_5_irq_handler UARTE1_IRQHandler
#else
#define nrfx_uarte_1_irq_handler UARTE1_IRQHandler
#define nrfx_uart_1_irq_handler UARTE1_IRQHandler
#endif
// QSPI_IRQn
#define nrfx_qspi_irq_handler QSPI_IRQHandler

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