From 00b2ef87444e4c57df0f6e7c517a5b1c52f8d7e6 Mon Sep 17 00:00:00 2001 From: Filip Kokosinski Date: Thu, 25 Apr 2024 13:18:46 +0200 Subject: [PATCH] dts: set the `riscv,isa` property for virt-based targets This commit makes the devicetrees of the targets that are based on the QEMU `virt` machine more consistent with the rest of the RISC-V targets in Zephyr by: * adding the `riscv,isa` property * adding a compatible string which uniquely identifies the `virt` core Signed-off-by: Filip Kokosinski --- boards/qemu/riscv32/qemu_riscv32.dts | 2 +- .../qemu_riscv32_qemu_virt_riscv32_smp.dts | 2 +- boards/qemu/riscv32e/qemu_riscv32e.dts | 2 +- boards/qemu/riscv64/qemu_riscv64.dts | 2 +- .../qemu_riscv64_qemu_virt_riscv64_smp.dts | 2 +- dts/bindings/cpu/qemu,riscv-virt.yaml | 9 ++++ dts/riscv/{virt.dtsi => qemu/virt-riscv.dtsi} | 16 +++---- dts/riscv/qemu/virt-riscv32.dtsi | 45 +++++++++++++++++++ dts/riscv/qemu/virt-riscv64.dtsi | 45 +++++++++++++++++++ 9 files changed, 112 insertions(+), 13 deletions(-) create mode 100644 dts/bindings/cpu/qemu,riscv-virt.yaml rename dts/riscv/{virt.dtsi => qemu/virt-riscv.dtsi} (91%) create mode 100644 dts/riscv/qemu/virt-riscv32.dtsi create mode 100644 dts/riscv/qemu/virt-riscv64.dtsi diff --git a/boards/qemu/riscv32/qemu_riscv32.dts b/boards/qemu/riscv32/qemu_riscv32.dts index 6c820813021..2c38ca1da1d 100644 --- a/boards/qemu/riscv32/qemu_riscv32.dts +++ b/boards/qemu/riscv32/qemu_riscv32.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include +#include / { chosen { diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts index 6c820813021..2c38ca1da1d 100644 --- a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts +++ b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.dts @@ -2,7 +2,7 @@ /dts-v1/; -#include +#include / { chosen { diff --git a/boards/qemu/riscv32e/qemu_riscv32e.dts b/boards/qemu/riscv32e/qemu_riscv32e.dts index 7596ee0d6eb..403d75cb742 100644 --- a/boards/qemu/riscv32e/qemu_riscv32e.dts +++ b/boards/qemu/riscv32e/qemu_riscv32e.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include +#include / { chosen { diff --git a/boards/qemu/riscv64/qemu_riscv64.dts b/boards/qemu/riscv64/qemu_riscv64.dts index fb96f6d3d38..673d4668019 100644 --- a/boards/qemu/riscv64/qemu_riscv64.dts +++ b/boards/qemu/riscv64/qemu_riscv64.dts @@ -3,7 +3,7 @@ /dts-v1/; -#include +#include / { chosen { diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts index fb96f6d3d38..673d4668019 100644 --- a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts +++ b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.dts @@ -3,7 +3,7 @@ /dts-v1/; -#include +#include / { chosen { diff --git a/dts/bindings/cpu/qemu,riscv-virt.yaml b/dts/bindings/cpu/qemu,riscv-virt.yaml new file mode 100644 index 00000000000..c4c5a8b174e --- /dev/null +++ b/dts/bindings/cpu/qemu,riscv-virt.yaml @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 + +description: QEMU RISC-V virt machine CPU node + +compatible: "qemu,riscv-virt" + +include: riscv,cpus.yaml diff --git a/dts/riscv/virt.dtsi b/dts/riscv/qemu/virt-riscv.dtsi similarity index 91% rename from dts/riscv/virt.dtsi rename to dts/riscv/qemu/virt-riscv.dtsi index 20873731c6e..8329a1ec62b 100644 --- a/dts/riscv/virt.dtsi +++ b/dts/riscv/qemu/virt-riscv.dtsi @@ -41,7 +41,7 @@ device_type = "cpu"; reg = < 0x00 >; status = "okay"; - compatible = "riscv"; + compatible = "qemu,riscv-virt", "riscv"; hlic0: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -55,7 +55,7 @@ device_type = "cpu"; reg = < 0x01 >; status = "okay"; - compatible = "riscv"; + compatible = "qemu,riscv-virt", "riscv"; hlic1: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -69,7 +69,7 @@ device_type = "cpu"; reg = < 0x02 >; status = "okay"; - compatible = "riscv"; + compatible = "qemu,riscv-virt", "riscv"; hlic2: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -83,7 +83,7 @@ device_type = "cpu"; reg = < 0x03 >; status = "okay"; - compatible = "riscv"; + compatible = "qemu,riscv-virt", "riscv"; hlic3: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -97,7 +97,7 @@ device_type = "cpu"; reg = < 0x04 >; status = "okay"; - compatible = "riscv"; + compatible = "qemu,riscv-virt", "riscv"; hlic4: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -111,7 +111,7 @@ device_type = "cpu"; reg = < 0x05 >; status = "okay"; - compatible = "riscv"; + compatible = "qemu,riscv-virt", "riscv"; hlic5: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -125,7 +125,7 @@ device_type = "cpu"; reg = < 0x06 >; status = "okay"; - compatible = "riscv"; + compatible = "qemu,riscv-virt", "riscv"; hlic6: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -139,7 +139,7 @@ device_type = "cpu"; reg = < 0x07 >; status = "okay"; - compatible = "riscv"; + compatible = "qemu,riscv-virt", "riscv"; hlic7: interrupt-controller { compatible = "riscv,cpu-intc"; diff --git a/dts/riscv/qemu/virt-riscv32.dtsi b/dts/riscv/qemu/virt-riscv32.dtsi new file mode 100644 index 00000000000..25d769d5183 --- /dev/null +++ b/dts/riscv/qemu/virt-riscv32.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + cpus { + cpu@0 { + riscv,isa = "rv32gc"; + }; + + cpu@1 { + riscv,isa = "rv32gc"; + }; + + cpu@2 { + riscv,isa = "rv32gc"; + }; + + cpu@3 { + riscv,isa = "rv32gc"; + }; + + cpu@4 { + riscv,isa = "rv32gc"; + }; + + cpu@5 { + riscv,isa = "rv32gc"; + }; + + cpu@6 { + riscv,isa = "rv32gc"; + }; + + cpu@7 { + riscv,isa = "rv32gc"; + }; + }; +}; diff --git a/dts/riscv/qemu/virt-riscv64.dtsi b/dts/riscv/qemu/virt-riscv64.dtsi new file mode 100644 index 00000000000..936f0a18815 --- /dev/null +++ b/dts/riscv/qemu/virt-riscv64.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + cpus { + cpu@0 { + riscv,isa = "rv64gc"; + }; + + cpu@1 { + riscv,isa = "rv64gc"; + }; + + cpu@2 { + riscv,isa = "rv64gc"; + }; + + cpu@3 { + riscv,isa = "rv64gc"; + }; + + cpu@4 { + riscv,isa = "rv64gc"; + }; + + cpu@5 { + riscv,isa = "rv64gc"; + }; + + cpu@6 { + riscv,isa = "rv64gc"; + }; + + cpu@7 { + riscv,isa = "rv64gc"; + }; + }; +};