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drivers: nxp_s32_netc_psi_vsi: update to RTD 2.0.0

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Config to enable VLAN promiscuous and untagged.

Config to enable SI message interrupt.

Fix the build warning.

Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
This commit is contained in:
Ha Duong Quang 2024-08-08 14:25:10 +07:00 committed by Henrik Brix Andersen
parent 3bff3168f5
commit 0135e7433b
4 changed files with 34 additions and 29 deletions
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4
drivers/ethernet/eth_nxp_s32_netc_priv.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2022-2023 NXP
* Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -99,7 +99,7 @@
#define _CONCAT3(a, b, c) DT_CAT3(a, b, c)
struct nxp_s32_eth_msix {
void (*handler)(uint8_t chan, const uint32_t *buf, uint8_t buf_size);
void (*handler)(uint8_t chan, const uint32 *buf, uint8_t buf_size);
struct mbox_dt_spec mbox_spec;
};

22
drivers/ethernet/eth_nxp_s32_netc_psi.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2022-2023 NXP
* Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -259,7 +259,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(nxp_s32_netc_psi) == 1, "Only one PSI enabl
#define INIT_VSIS(n) DT_INST_NODE_HAS_PROP(n, vsis)
#define NETC_PSI_INSTANCE_DEFINE(n) \
void nxp_s32_eth_psi##n##_rx_event(uint8_t chan, const uint32_t *buf, uint8_t buf_size) \
void nxp_s32_eth_psi##n##_rx_event(uint8_t chan, const uint32 *buf, uint8_t buf_size) \
{ \
ARG_UNUSED(chan); \
ARG_UNUSED(buf); \
@ -281,8 +281,8 @@ static void nxp_s32_eth##n##_rx_callback(const uint8_t unused, const uint8_t rin
} \
} \
\
static Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
static Netc_Eth_Ip_MACFilterHashTableEntryType \
static __nocache Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
static __nocache Netc_Eth_Ip_MACFilterHashTableEntryType \
nxp_s32_eth##n##_mac_filter_hash_table[CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE]; \
\
NETC_TX_RING(n, 0, NETC_MIN_RING_LEN, NETC_MIN_RING_BUF_SIZE); \
@ -359,27 +359,31 @@ static const Netc_Eth_Ip_EnetcGeneralConfigType nxp_s32_eth##n##_enetc_general_c
NETC_VSI_RX_MSG_BUF_ARRAY, (,), n)), \
(EMPTY)) \
}, \
.maskMACVLANPromiscuousEnable = (uint16)0x3U, \
.maskVLANAllowUntaggedEnable = (uint32)0x30000U, \
}; \
\
static const Netc_Eth_Ip_StationInterfaceConfigType nxp_s32_eth##n##_si_cfg = { \
.NumberOfRxBDR = 1, \
.NumberOfTxBDR = 2, \
.txMruMailboxAddr = NULL, \
.rxMruMailboxAddr = (uint32_t *)MRU_MBOX_ADDR(DT_DRV_INST(n), rx), \
.rxMruMailboxAddr = (uint32 *)MRU_MBOX_ADDR(DT_DRV_INST(n), rx), \
.siMsgMruMailboxAddr = COND_CODE_1(INIT_VSIS(n), \
((uint32_t *)MRU_MBOX_ADDR(DT_DRV_INST(n), vsi_msg)), (NULL)), \
((uint32 *)MRU_MBOX_ADDR(DT_DRV_INST(n), vsi_msg)), (NULL)), \
.EnableSIMsgInterrupt = true, \
.RxInterrupts = (uint32_t)true, \
.TxInterrupts = (uint32_t)false, \
.MACFilterTableMaxNumOfEntries = CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE, \
}; \
\
static uint8_t nxp_s32_eth##n##_switch_vlandr2dei_cfg[NETC_ETHSWT_NUMBER_OF_DR]; \
static uint8_t nxp_s32_eth##n##_switch_vlandr2dei_cfg[NETC_ETHSWT_IP_NUMBER_OF_DR]; \
static Netc_EthSwt_Ip_PortIngressType nxp_s32_eth##n##_switch_port_ingress_cfg; \
static Netc_EthSwt_Ip_PortEgressType nxp_s32_eth##n##_switch_port_egress_cfg = { \
.vlanDrToDei = &nxp_s32_eth##n##_switch_vlandr2dei_cfg, \
}; \
static Netc_EthSwt_Ip_PortType nxp_s32_eth##n##_switch_ports_cfg[NETC_ETHSWT_NUMBER_OF_PORTS] = {\
LISTIFY(NETC_ETHSWT_NUMBER_OF_PORTS, NETC_SWITCH_PORT_CFG, (,), n) \
static Netc_EthSwt_Ip_PortType \
nxp_s32_eth##n##_switch_ports_cfg[NETC_ETHSWT_IP_NUMBER_OF_PORTS] = { \
LISTIFY(NETC_ETHSWT_IP_NUMBER_OF_PORTS, NETC_SWITCH_PORT_CFG, (,), n) \
}; \
\
static const Netc_EthSwt_Ip_ConfigType nxp_s32_eth##n##_switch_cfg = { \

13
drivers/ethernet/eth_nxp_s32_netc_vsi.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2022-2023 NXP
* Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -82,7 +82,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(nxp_s32_netc_vsi) == 1, "Only one VSI enabl
#define NETC_VSI_INSTANCE_DEFINE(n) \
NETC_GENERATE_MAC_ADDRESS(n) \
\
void nxp_s32_eth_vsi##n##_rx_event(uint8_t chan, const uint32_t *buf, uint8_t buf_size) \
void nxp_s32_eth_vsi##n##_rx_event(uint8_t chan, const uint32 *buf, uint8_t buf_size) \
{ \
Netc_Eth_Ip_MSIX_Rx(NETC_SI_NXP_S32_HW_INSTANCE(n)); \
} \
@ -98,10 +98,10 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(nxp_s32_netc_vsi) == 1, "Only one VSI enabl
} \
} \
\
static Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
Netc_Eth_Ip_VsiToPsiMsgType nxp_s32_eth##n##_vsi2psi_msg \
static __nocache Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
__nocache Netc_Eth_Ip_VsiToPsiMsgType nxp_s32_eth##n##_vsi2psi_msg \
__aligned(FEATURE_NETC_ETH_VSI_MSG_ALIGNMENT); \
static Netc_Eth_Ip_MACFilterHashTableEntryType \
static __nocache Netc_Eth_Ip_MACFilterHashTableEntryType \
nxp_s32_eth##n##_mac_filter_hash_table[CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE]; \
\
NETC_RX_RING(n, TX_RING_IDX, CONFIG_ETH_NXP_S32_RX_RING_LEN, \
@ -137,7 +137,8 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(nxp_s32_netc_vsi) == 1, "Only one VSI enabl
.NumberOfRxBDR = 1, \
.NumberOfTxBDR = 1, \
.txMruMailboxAddr = NULL, \
.rxMruMailboxAddr = (uint32_t *)MRU_MBOX_ADDR(DT_DRV_INST(n), rx), \
.rxMruMailboxAddr = (uint32 *)MRU_MBOX_ADDR(DT_DRV_INST(n), rx), \
.EnableSIMsgInterrupt = true, \
.RxInterrupts = (uint32_t)true, \
.TxInterrupts = (uint32_t)false, \
.MACFilterTableMaxNumOfEntries = CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE, \

24
drivers/mbox/mbox_nxp_s32_mru.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2022-2023 NXP
* Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -80,9 +80,9 @@ static int nxp_s32_mru_send(const struct device *dev, uint32_t channel,
tx_cfg.NumTxMB = MRU_MAX_MBOX_PER_CHAN;
tx_cfg.LastTxMBIndex = MRU_MAX_MBOX_PER_CHAN - 1;
tx_cfg.MBAddList = (volatile uint32 * const *)tx_mbox_addr;
tx_cfg.ChMBSTATAdd = &cfg->base->CHXCONFIG[channel].CH_MBSTAT;
tx_cfg.ChMBSTATAdd = (volatile uint32 *)&cfg->base->CHXCONFIG[channel].CH_MBSTAT;
status = Mru_Ip_Transmit(&tx_cfg, (const uint32_t *)msg->data);
status = Mru_Ip_Transmit(&tx_cfg, (const uint32 *)msg->data);
return (status == MRU_IP_STATUS_SUCCESS ? 0 : -EBUSY);
}
@ -208,11 +208,11 @@ static const struct mbox_driver_api nxp_s32_mru_driver_api = {
}
#define MRU_CH_RX_CFG(i, n) \
static volatile const uint32_t * const \
static volatile const uint32 * const \
nxp_s32_mru_##n##_ch_##i##_rx_mbox_addr[MRU_MAX_MBOX_PER_CHAN] = { \
(uint32_t *const)MRU_MBOX_ADDR(n, i, 0), \
(uint32 *const)MRU_MBOX_ADDR(n, i, 0), \
}; \
static uint32_t nxp_s32_mru_##n##_ch_##i##_buf[MRU_MAX_MBOX_PER_CHAN]; \
static uint32 nxp_s32_mru_##n##_ch_##i##_buf[MRU_MAX_MBOX_PER_CHAN]; \
static const Mru_Ip_ReceiveChannelType nxp_s32_mru_##n##_ch_##i##_rx_cfg = { \
.ChannelId = i, \
.ChannelIndex = i, \
@ -235,18 +235,18 @@ static const struct mbox_driver_api nxp_s32_mru_driver_api = {
#define MRU_CH_CFG(i, n) \
{ \
.ChCFG0Add = &MRU_BASE(n)->CHXCONFIG[i].CH_CFG0, \
.ChCFG0Add = (volatile uint32 *)&MRU_BASE(n)->CHXCONFIG[i].CH_CFG0, \
.ChCFG0 = RTU_MRU_CH_CFG0_IE(0) | RTU_MRU_CH_CFG0_MBE0(0), \
.ChCFG1Add = &MRU_BASE(n)->CHXCONFIG[i].CH_CFG1, \
.ChCFG1Add = (volatile uint32 *)&MRU_BASE(n)->CHXCONFIG[i].CH_CFG1, \
.ChCFG1 = RTU_MRU_CH_CFG1_MBIC0(MRU_INT_GROUP(DT_INST_IRQN(n))), \
.ChMBSTATAdd = &MRU_BASE(n)->CHXCONFIG[i].CH_MBSTAT, \
.ChMBSTATAdd = (volatile uint32 *)&MRU_BASE(n)->CHXCONFIG[i].CH_MBSTAT, \
.NumMailbox = MRU_MAX_MBOX_PER_CHAN, \
.MBLinkReceiveChCfg = nxp_s32_mru_##n##_ch_##i##_rx_link_cfg \
}
/* Callback wrapper to adapt MRU's baremetal driver callback to Zephyr's mbox driver callback */
#define MRU_CALLBACK_WRAPPER_FUNC(n) \
void nxp_s32_mru_##n##_cb(uint8_t channel, const uint32_t *buf, uint8_t mbox_count) \
void nxp_s32_mru_##n##_cb(uint8_t channel, const uint32 *buf, uint8_t mbox_count) \
{ \
const struct device *dev = DEVICE_DT_INST_GET(n); \
struct nxp_s32_mru_data *data = dev->data; \
@ -283,8 +283,8 @@ static const struct mbox_driver_api nxp_s32_mru_driver_api = {
.ChannelCfg = COND_CODE_0(MRU_RX_CHANNELS(n), \
(NULL), (nxp_s32_mru_##n##_ch_cfg)), \
.NOTIFYAdd = { \
&MRU_BASE(n)->NOTIFY[0], \
&MRU_BASE(n)->NOTIFY[1] \
(const volatile uint32 *)&MRU_BASE(n)->NOTIFY[0], \
(const volatile uint32 *)&MRU_BASE(n)->NOTIFY[1] \
}, \
}, \
.irq_group = MRU_INT_GROUP(DT_INST_IRQN(n)), \