boards: nxp: imx8m/n/p, imx93/5, fix ram dts node name

For Zephyr Cortex-A Core supports on NXP boards imx8mm, imx8mn, imx8mp,
imx93 and imx95, currently use DDR DRAM memory as Zephyr memory, so
change RAM dts nodes name to be "dram" in order to reduce confusion.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This commit is contained in:
Jiafei Pan 2024-11-25 11:51:55 +08:00 committed by Benjamin Cabé
parent 7f97d001d5
commit 06227ba879
9 changed files with 26 additions and 18 deletions

View file

@ -16,7 +16,8 @@
chosen { chosen {
zephyr,console = &uart4; zephyr,console = &uart4;
zephyr,shell-uart = &uart4; zephyr,shell-uart = &uart4;
zephyr,sram = &sram0; /* sram node actually locates at DDR DRAM */
zephyr,sram = &dram;
}; };
cpus { cpus {
@ -31,7 +32,7 @@
}; };
}; };
sram0: memory@93c00000 { dram: memory@93c00000 {
reg = <0x93c00000 DT_SIZE_M(1)>; reg = <0x93c00000 DT_SIZE_M(1)>;
}; };
}; };

View file

@ -16,7 +16,8 @@
chosen { chosen {
zephyr,console = &uart4; zephyr,console = &uart4;
zephyr,shell-uart = &uart4; zephyr,shell-uart = &uart4;
zephyr,sram = &sram0; /* sram node actually locates at DDR DRAM */
zephyr,sram = &dram;
}; };
cpus { cpus {
@ -33,7 +34,7 @@
method = "smc"; method = "smc";
}; };
sram0: memory@93c00000 { dram: memory@93c00000 {
reg = <0x93c00000 DT_SIZE_M(1)>; reg = <0x93c00000 DT_SIZE_M(1)>;
}; };
}; };

View file

@ -16,7 +16,8 @@
chosen { chosen {
zephyr,console = &uart4; zephyr,console = &uart4;
zephyr,shell-uart = &uart4; zephyr,shell-uart = &uart4;
zephyr,sram = &sram0; /* sram node actually locates at DDR DRAM */
zephyr,sram = &dram;
}; };
cpus { cpus {
@ -31,7 +32,7 @@
}; };
}; };
sram0: memory@93c00000 { dram: memory@93c00000 {
reg = <0x93c00000 DT_SIZE_M(1)>; reg = <0x93c00000 DT_SIZE_M(1)>;
}; };
}; };

View file

@ -16,7 +16,8 @@
chosen { chosen {
zephyr,console = &uart4; zephyr,console = &uart4;
zephyr,shell-uart = &uart4; zephyr,shell-uart = &uart4;
zephyr,sram = &sram0; /* sram node actually locates at DDR DRAM */
zephyr,sram = &dram;
}; };
cpus { cpus {
@ -33,7 +34,7 @@
method = "smc"; method = "smc";
}; };
sram0: memory@93c00000 { dram: memory@93c00000 {
reg = <0x93c00000 DT_SIZE_M(1)>; reg = <0x93c00000 DT_SIZE_M(1)>;
}; };
}; };

View file

@ -16,7 +16,8 @@
chosen { chosen {
zephyr,console = &uart4; zephyr,console = &uart4;
zephyr,shell-uart = &uart4; zephyr,shell-uart = &uart4;
zephyr,sram = &sram0; /* sram node actually locates at DDR DRAM */
zephyr,sram = &dram;
}; };
cpus { cpus {
@ -31,7 +32,7 @@
}; };
}; };
sram0: memory@c0000000 { dram: memory@c0000000 {
reg = <0xc0000000 DT_SIZE_M(1)>; reg = <0xc0000000 DT_SIZE_M(1)>;
}; };

View file

@ -16,7 +16,8 @@
chosen { chosen {
zephyr,console = &uart4; zephyr,console = &uart4;
zephyr,shell-uart = &uart4; zephyr,shell-uart = &uart4;
zephyr,sram = &sram0; /* sram node actually locates at DDR DRAM */
zephyr,sram = &dram;
}; };
cpus { cpus {
@ -33,7 +34,7 @@
method = "smc"; method = "smc";
}; };
sram0: memory@c0000000 { dram: memory@c0000000 {
reg = <0xc0000000 DT_SIZE_M(1)>; reg = <0xc0000000 DT_SIZE_M(1)>;
}; };

View file

@ -16,7 +16,8 @@
chosen { chosen {
zephyr,console = &lpuart2; zephyr,console = &lpuart2;
zephyr,shell-uart = &lpuart2; zephyr,shell-uart = &lpuart2;
zephyr,sram = &sram0; /* sram node actually locates at DDR DRAM */
zephyr,sram = &dram;
zephyr,canbus = &flexcan2; zephyr,canbus = &flexcan2;
}; };
@ -26,7 +27,7 @@
}; };
}; };
sram0: memory@d0000000 { dram: memory@d0000000 {
reg = <0xd0000000 DT_SIZE_M(1)>; reg = <0xd0000000 DT_SIZE_M(1)>;
}; };

View file

@ -16,7 +16,8 @@
chosen { chosen {
zephyr,console = &lpuart1; zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1; zephyr,shell-uart = &lpuart1;
zephyr,sram = &sram0; /* sram node actually locates at DDR DRAM */
zephyr,sram = &dram;
}; };
cpus { cpus {
@ -41,7 +42,7 @@
}; };
}; };
sram0: memory@d0000000 { dram: memory@d0000000 {
reg = <0xd0000000 DT_SIZE_M(1)>; reg = <0xd0000000 DT_SIZE_M(1)>;
}; };
}; };

View file

@ -16,7 +16,7 @@
chosen { chosen {
zephyr,console = &lpuart1; zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1; zephyr,shell-uart = &lpuart1;
zephyr,sram = &sram0; zephyr,sram = &dram;
}; };
psci { psci {
@ -24,7 +24,7 @@
method = "smc"; method = "smc";
}; };
sram0: memory@d0000000 { dram: memory@d0000000 {
reg = <0xd0000000 DT_SIZE_M(1)>; reg = <0xd0000000 DT_SIZE_M(1)>;
}; };
}; };