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dts: arm: st: add reset control for display peripheral

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add reset control registers information (on RCC_BUS_RSTR LTDCRST bit)
for display peripheral reset.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
This commit is contained in:
Fabrice DJIATSA 2024-08-16 14:35:50 +02:00 committed by Anas Nashif
parent af57912af5
commit 07cdebaf8e
11 changed files with 15 additions and 2 deletions
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1
dts/arm/st/f4/stm32f429.dtsi
View file

@ -25,6 +25,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
resets = <&rctl STM32_RESET(APB2, 26U)>;
status = "disabled";
};

1
dts/arm/st/f7/stm32f746.dtsi
View file

@ -17,6 +17,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_err";
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
resets = <&rctl STM32_RESET(APB2, 26U)>;
status = "disabled";
};
};

1
dts/arm/st/f7/stm32f767.dtsi
View file

@ -18,6 +18,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_err";
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
resets = <&rctl STM32_RESET(APB2, 26U)>;
status = "disabled";
};
};

1
dts/arm/st/h7/stm32h723.dtsi
View file

@ -88,6 +88,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};

1
dts/arm/st/h7/stm32h743.dtsi
View file

@ -49,6 +49,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};

1
dts/arm/st/h7/stm32h745.dtsi
View file

@ -42,6 +42,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};

1
dts/arm/st/h7/stm32h750.dtsi
View file

@ -49,6 +49,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};

1
dts/arm/st/h7/stm32h7a3.dtsi
View file

@ -52,6 +52,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
resets = <&rctl STM32_RESET(APB3, 4U)>;
status = "disabled";
};

3
dts/arm/st/l4/stm32l4r9.dtsi
View file

@ -17,7 +17,8 @@
reg = <0x40016800 0x200>;
interrupts = <91 0>, <92 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x40000000>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x04000000>;
resets = <&rctl STM32_RESET(APB2, 26U)>;
status = "disabled";
};
};

1
dts/arm/st/mp1/stm32mp157.dtsi
View file

@ -395,6 +395,7 @@
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000001>;
resets = <&rctl STM32_RESET(APB4, 26U)>;
status = "disabled";
};
};

5
dts/bindings/display/st,stm32-ltdc.yaml
View file

@ -6,7 +6,7 @@ description: STM32 LCD-TFT display controller
compatible: "st,stm32-ltdc"
include: [lcd-controller.yaml, pinctrl-device.yaml]
include: [lcd-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
properties:
disp-on-gpios:
@ -30,6 +30,9 @@ properties:
clocks:
required: true
resets:
required: true
interrupts:
required: true