adafruit-mirror/zephyr
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions 9

drivers: serial: gd32: use clock control API

Browse source 
Use the clock control API to enable the UART clock.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2022-09-03 19:06:32 +02:00 committed by Carles Cufí
parent 22e64fddfd
commit 0aadc2dd44
8 changed files with 37 additions and 36 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
drivers/serial/usart_gd32.c
View file

@ -6,12 +6,14 @@
#define DT_DRV_COMPAT gd_gd32_usart
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/gd32.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/drivers/uart.h>
#include <gd32_usart.h>
#include <gd32_rcu.h>
/* Unify GD32 HAL USART status register name to USART_STAT */
#ifndef USART_STAT
@ -20,7 +22,7 @@
struct gd32_usart_config {
uint32_t reg;
uint32_t rcu_periph_clock;
uint16_t clkid;
struct reset_dt_spec reset;
const struct pinctrl_dev_config *pcfg;
uint32_t parity;
@ -82,7 +84,8 @@ static int usart_gd32_init(const struct device *dev)
return -ENOTSUP;
}
rcu_periph_clock_enable(cfg->rcu_periph_clock);
(void)clock_control_on(GD32_CLOCK_CONTROLLER,
(clock_control_subsys_t *)&cfg->clkid);
(void)reset_line_toggle_dt(&cfg->reset);
@ -321,7 +324,7 @@ static const struct uart_driver_api usart_gd32_driver_api = {
}; \
static const struct gd32_usart_config usart_gd32_config_##n = { \
.reg = DT_INST_REG_ADDR(n), \
.rcu_periph_clock = DT_INST_PROP(n, rcu_periph_clock), \
.clkid = DT_INST_CLOCKS_CELL(n, id), \
.reset = RESET_DT_SPEC_INST_GET(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE), \

10
dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi
View file

@ -64,7 +64,7 @@
compatible = "gd,gd32-usart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
rcu-periph-clock = <0x60e>;
clocks = <&cctl GD32_CLOCK_USART0>;
resets = <&rctl GD32_RESET_USART0>;
status = "disabled";
};
@ -73,7 +73,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
rcu-periph-clock = <0x711>;
clocks = <&cctl GD32_CLOCK_USART1>;
resets = <&rctl GD32_RESET_USART1>;
status = "disabled";
};
@ -82,7 +82,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
rcu-periph-clock = <0x712>;
clocks = <&cctl GD32_CLOCK_USART2>;
resets = <&rctl GD32_RESET_USART2>;
status = "disabled";
};
@ -91,7 +91,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004c00 0x400>;
interrupts = <52 0>;
rcu-periph-clock = <0x713>;
clocks = <&cctl GD32_CLOCK_UART3>;
resets = <&rctl GD32_RESET_UART3>;
status = "disabled";
};
@ -100,7 +100,7 @@
compatible = "gd,gd32-usart";
reg = <0x40005000 0x400>;
interrupts = <53 0>;
rcu-periph-clock = <0x714>;
clocks = <&cctl GD32_CLOCK_UART4>;
resets = <&rctl GD32_RESET_UART4>;
status = "disabled";
};

12
dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi
View file

@ -71,7 +71,7 @@
compatible = "gd,gd32-usart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
rcu-periph-clock = <0x60e>;
clocks = <&cctl GD32_CLOCK_USART0>;
resets = <&rctl GD32_RESET_USART0>;
status = "disabled";
};
@ -80,7 +80,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
rcu-periph-clock = <0x711>;
clocks = <&cctl GD32_CLOCK_USART1>;
resets = <&rctl GD32_RESET_USART1>;
status = "disabled";
};
@ -89,7 +89,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
rcu-periph-clock = <0x712>;
clocks = <&cctl GD32_CLOCK_USART2>;
resets = <&rctl GD32_RESET_USART2>;
status = "disabled";
};
@ -98,7 +98,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004c00 0x400>;
interrupts = <52 0>;
rcu-periph-clock = <0x713>;
clocks = <&cctl GD32_CLOCK_UART3>;
resets = <&rctl GD32_RESET_UART3>;
status = "disabled";
};
@ -107,7 +107,7 @@
compatible = "gd,gd32-usart";
reg = <0x40005000 0x400>;
interrupts = <53 0>;
rcu-periph-clock = <0x714>;
clocks = <&cctl GD32_CLOCK_UART4>;
resets = <&rctl GD32_RESET_UART4>;
status = "disabled";
};
@ -117,7 +117,7 @@
reg = <0x40017000 0x400>;
interrupts = <84 0>, <86 0>;
interrupt-names = "global", "wkup";
rcu-periph-clock = <0x61c>;
clocks = <&cctl GD32_CLOCK_USART5>;
resets = <&rctl GD32_RESET_USART5>;
status = "disabled";
};

4
dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi
View file

@ -62,7 +62,7 @@
compatible = "gd,gd32-usart";
reg = <0x40013800 0x400>;
interrupts = <27 0>;
rcu-periph-clock = <0x060e>;
clocks = <&cctl GD32_CLOCK_USART0>;
resets = <&rctl GD32_RESET_USART0>;
status = "disabled";
};
@ -71,7 +71,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004400 0x400>;
interrupts = <28 0>;
rcu-periph-clock = <0x0711>;
clocks = <&cctl GD32_CLOCK_USART1>;
resets = <&rctl GD32_RESET_USART1>;
status = "disabled";
};

10
dts/arm/gigadevice/gd32f403/gd32f403.dtsi
View file

@ -70,7 +70,7 @@
compatible = "gd,gd32-usart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
rcu-periph-clock = <0x60e>;
clocks = <&cctl GD32_CLOCK_USART0>;
resets = <&rctl GD32_RESET_USART0>;
status = "disabled";
};
@ -79,7 +79,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
rcu-periph-clock = <0x712>;
clocks = <&cctl GD32_CLOCK_USART1>;
resets = <&rctl GD32_RESET_USART1>;
status = "disabled";
};
@ -88,7 +88,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
rcu-periph-clock = <0x713>;
clocks = <&cctl GD32_CLOCK_USART2>;
resets = <&rctl GD32_RESET_USART2>;
status = "disabled";
};
@ -97,7 +97,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004c00 0x400>;
interrupts = <52 0>;
rcu-periph-clock = <0x714>;
clocks = <&cctl GD32_CLOCK_UART3>;
resets = <&rctl GD32_RESET_UART3>;
status = "disabled";
};
@ -106,7 +106,7 @@
compatible = "gd,gd32-usart";
reg = <0x40005000 0x400>;
interrupts = <53 0>;
rcu-periph-clock = <0x715>;
clocks = <&cctl GD32_CLOCK_UART4>;
resets = <&rctl GD32_RESET_UART4>;
status = "disabled";
};

16
dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
View file

@ -70,7 +70,7 @@
compatible = "gd,gd32-usart";
reg = <0x40011000 0x400>;
interrupts = <37 0>;
rcu-periph-clock = <0x1104>;
clocks = <&cctl GD32_CLOCK_USART0>;
resets = <&rctl GD32_RESET_USART0>;
status = "disabled";
};
@ -79,7 +79,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
rcu-periph-clock = <0x1011>;
clocks = <&cctl GD32_CLOCK_USART1>;
resets = <&rctl GD32_RESET_USART1>;
status = "disabled";
};
@ -88,7 +88,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
rcu-periph-clock = <0x1012>;
clocks = <&cctl GD32_CLOCK_USART2>;
resets = <&rctl GD32_RESET_USART2>;
status = "disabled";
};
@ -97,7 +97,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004c00 0x400>;
interrupts = <52 0>;
rcu-periph-clock = <0x1013>;
clocks = <&cctl GD32_CLOCK_UART3>;
resets = <&rctl GD32_RESET_UART3>;
status = "disabled";
};
@ -106,7 +106,7 @@
compatible = "gd,gd32-usart";
reg = <0x40005000 0x400>;
interrupts = <52 0>;
rcu-periph-clock = <0x1014>;
clocks = <&cctl GD32_CLOCK_UART4>;
resets = <&rctl GD32_RESET_UART4>;
status = "disabled";
};
@ -115,7 +115,7 @@
compatible = "gd,gd32-usart";
reg = <0x40011400 0x400>;
interrupts = <71 0>;
rcu-periph-clock = <0x1105>;
clocks = <&cctl GD32_CLOCK_USART5>;
resets = <&rctl GD32_RESET_USART5>;
status = "disabled";
};
@ -124,7 +124,7 @@
compatible = "gd,gd32-usart";
reg = <0x40007800 0x400>;
interrupts = <82 0>;
rcu-periph-clock = <0x101e>;
clocks = <&cctl GD32_CLOCK_UART6>;
resets = <&rctl GD32_RESET_UART6>;
status = "disabled";
};
@ -133,7 +133,7 @@
compatible = "gd,gd32-usart";
reg = <0x40007c00 0x400>;
interrupts = <83 0>;
rcu-periph-clock = <0x101f>;
clocks = <&cctl GD32_CLOCK_UART7>;
resets = <&rctl GD32_RESET_UART7>;
status = "disabled";
};

4
dts/bindings/serial/gd,gd32-usart.yaml
View file

@ -17,7 +17,5 @@ properties:
resets:
required: true
rcu-periph-clock:
type: int
description: Reset Control Unit Peripheral Clock ID
clocks:
required: true

6
dts/riscv/gigadevice/gd32vf103.dtsi
View file

@ -91,7 +91,7 @@
compatible = "gd,gd32-usart";
reg = <0x40013800 0x400>;
interrupts = <56 0>;
rcu-periph-clock = <0x60e>;
clocks = <&cctl GD32_CLOCK_USART0>;
resets = <&rctl GD32_RESET_USART0>;
status = "disabled";
};
@ -100,7 +100,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004400 0x400>;
interrupts = <57 0>;
rcu-periph-clock = <0x711>;
clocks = <&cctl GD32_CLOCK_USART1>;
resets = <&rctl GD32_RESET_USART1>;
status = "disabled";
};
@ -109,7 +109,7 @@
compatible = "gd,gd32-usart";
reg = <0x40004800 0x400>;
interrupts = <58 0>;
rcu-periph-clock = <0x712>;
clocks = <&cctl GD32_CLOCK_USART2>;
resets = <&rctl GD32_RESET_USART2>;
status = "disabled";
};