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drivers: ethernet: lan865x: remove internal PHY specific initialization

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Remove internal PHY initialization part as the phy_microchip_t1s.c
driver will do the internal PHY initialization.

Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
This commit is contained in:
Parthiban Veerasooran 2024-12-16 15:54:46 +05:30 committed by Benjamin Cabé
parent 25edf1b46e
commit 0b87a5469c
4 changed files with 14 additions and 199 deletions
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176
drivers/ethernet/eth_lan865x.c
View file

@ -160,145 +160,6 @@ static int lan865x_check_spi(const struct device *dev)
return ret;
}
/* Implementation of pseudo code from AN1760 */
static uint8_t lan865x_read_indirect_reg(const struct device *dev, uint8_t addr, uint8_t mask)
{
struct lan865x_data *ctx = dev->data;
uint32_t val;
oa_tc6_reg_write(ctx->tc6, 0x000400D8, addr);
oa_tc6_reg_write(ctx->tc6, 0x000400DA, 0x02);
oa_tc6_reg_read(ctx->tc6, 0x000400D9, &val);
return (uint8_t)val & mask;
}
/*
* Values in the below table for LAN865x rev. B0 and B1 (with place
* holders for cfgparamX.
*/
static oa_mem_map_t lan865x_conf[] = {
{.mms = 0x1, .address = 0x00, .value = 0x0000},
{.mms = 0x4, .address = 0xD0, .value = 0x3F31},
{.mms = 0x4, .address = 0xE0, .value = 0xC000},
{.mms = 0x4, .address = 0x84, .value = 0x0000}, /* cfgparam1 */
{.mms = 0x4, .address = 0x8A, .value = 0x0000}, /* cfgparam2 */
{.mms = 0x4, .address = 0xE9, .value = 0x9E50},
{.mms = 0x4, .address = 0xF5, .value = 0x1CF8},
{.mms = 0x4, .address = 0xF4, .value = 0xC020},
{.mms = 0x4, .address = 0xF8, .value = 0xB900},
{.mms = 0x4, .address = 0xF9, .value = 0x4E53},
{.mms = 0x4, .address = 0x91, .value = 0x9660},
{.mms = 0x4, .address = 0x77, .value = 0x0028},
{.mms = 0x4, .address = 0x43, .value = 0x00FF},
{.mms = 0x4, .address = 0x44, .value = 0xFFFF},
{.mms = 0x4, .address = 0x45, .value = 0x0000},
{.mms = 0x4, .address = 0x53, .value = 0x00FF},
{.mms = 0x4, .address = 0x54, .value = 0xFFFF},
{.mms = 0x4, .address = 0x55, .value = 0x0000},
{.mms = 0x4, .address = 0x40, .value = 0x0002},
{.mms = 0x4, .address = 0x50, .value = 0x0002},
{.mms = 0x4, .address = 0xAD, .value = 0x0000}, /* cfgparam3 */
{.mms = 0x4, .address = 0xAE, .value = 0x0000}, /* cfgparam4 */
{.mms = 0x4, .address = 0xAF, .value = 0x0000}, /* cfgparam5 */
{.mms = 0x4, .address = 0xB0, .value = 0x0103},
{.mms = 0x4, .address = 0xB1, .value = 0x0910},
{.mms = 0x4, .address = 0xB2, .value = 0x1D26},
{.mms = 0x4, .address = 0xB3, .value = 0x002A},
{.mms = 0x4, .address = 0xB4, .value = 0x0103},
{.mms = 0x4, .address = 0xB5, .value = 0x070D},
{.mms = 0x4, .address = 0xB6, .value = 0x1720},
{.mms = 0x4, .address = 0xB7, .value = 0x0027},
{.mms = 0x4, .address = 0xB8, .value = 0x0509},
{.mms = 0x4, .address = 0xB9, .value = 0x0E13},
{.mms = 0x4, .address = 0xBA, .value = 0x1C25},
{.mms = 0x4, .address = 0xBB, .value = 0x002B},
{.mms = 0x4, .address = 0x0C, .value = 0x0100},
{.mms = 0x4, .address = 0x81, .value = 0x00E0},
};
/* Based on AN1760 DS60001760G pseudo code */
static int lan865x_init_chip(const struct device *dev, uint8_t silicon_rev)
{
uint16_t cfgparam1, cfgparam2, cfgparam3, cfgparam4, cfgparam5;
uint8_t i, size = ARRAY_SIZE(lan865x_conf);
struct lan865x_data *ctx = dev->data;
int8_t offset1 = 0, offset2 = 0;
uint8_t value1, value2;
/* Enable protected control RW */
oa_tc6_set_protected_ctrl(ctx->tc6, true);
value1 = lan865x_read_indirect_reg(dev, 0x04, 0x1F);
if ((value1 & 0x10) != 0) { /* Convert uint8_t to int8_t */
offset1 = (int8_t)((uint8_t)value1 - 0x20);
} else {
offset1 = (int8_t)value1;
}
value2 = lan865x_read_indirect_reg(dev, 0x08, 0x1F);
if ((value2 & 0x10) != 0) { /* Convert uint8_t to int8_t */
offset2 = (int8_t)((uint8_t)value2 - 0x20);
} else {
offset2 = (int8_t)value2;
}
cfgparam1 = (uint16_t)(((9 + offset1) & 0x3F) << 10) |
(uint16_t)(((14 + offset1) & 0x3F) << 4) | 0x03;
cfgparam2 = (uint16_t)(((40 + offset2) & 0x3F) << 10);
cfgparam3 = (uint16_t)(((5 + offset1) & 0x3F) << 8) | (uint16_t)((9 + offset1) & 0x3F);
cfgparam4 = (uint16_t)(((9 + offset1) & 0x3F) << 8) | (uint16_t)((14 + offset1) & 0x3F);
cfgparam5 = (uint16_t)(((17 + offset1) & 0x3F) << 8) | (uint16_t)((22 + offset1) & 0x3F);
lan865x_update_dev_cfg_array(lan865x_conf, size, MMS_REG(0x4, 0x84), cfgparam1);
lan865x_update_dev_cfg_array(lan865x_conf, size, MMS_REG(0x4, 0x8A), cfgparam2);
lan865x_update_dev_cfg_array(lan865x_conf, size, MMS_REG(0x4, 0xAD), cfgparam3);
lan865x_update_dev_cfg_array(lan865x_conf, size, MMS_REG(0x4, 0xAE), cfgparam4);
lan865x_update_dev_cfg_array(lan865x_conf, size, MMS_REG(0x4, 0xAF), cfgparam5);
if (silicon_rev == 1) {
/* For silicon rev 1 (B0): (bit [3..0] from 0x0A0084 */
lan865x_update_dev_cfg_array(lan865x_conf, size, MMS_REG(0x4, 0xD0), 0x5F21);
}
/* Write LAN865x config with correct order */
for (i = 0; i < size; i++) {
oa_tc6_reg_write(ctx->tc6, MMS_REG(lan865x_conf[i].mms, lan865x_conf[i].address),
(uint32_t)lan865x_conf[i].value);
}
return 0;
}
/* Implementation of pseudo code from AN1760 - END */
static int lan865x_config_plca(const struct device *dev, uint8_t node_id, uint8_t node_cnt,
uint8_t burst_cnt, uint8_t burst_timer)
{
struct lan865x_data *ctx = dev->data;
uint32_t val;
/* Collision Detection */
oa_tc6_reg_write(ctx->tc6, 0x00040087, 0x0083u); /* COL_DET_CTRL0 */
/* T1S Phy Node ID and Max Node Count */
if (node_id == 0) {
val = (uint32_t)node_cnt << 8;
} else {
val = (uint32_t)node_id;
}
oa_tc6_reg_write(ctx->tc6, 0x0004CA02, val); /* PLCA_CONTROL_1_REGISTER */
/* PLCA Burst Count and Burst Timer */
val = ((uint32_t)burst_cnt << 8) | burst_timer;
oa_tc6_reg_write(ctx->tc6, 0x0004CA05, val); /* PLCA_BURST_MODE_REGISTER */
/* Enable PLCA */
oa_tc6_reg_write(ctx->tc6, 0x0004CA01, BIT(15)); /* PLCA_CONTROL_0_REGISTER */
return 0;
}
static void lan865x_write_macaddress(const struct device *dev)
{
struct lan865x_data *ctx = dev->data;
@ -342,26 +203,22 @@ static int lan865x_set_specific_multicast_addr(const struct device *dev)
return oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_NCFGR, LAN865x_MAC_NCFGR_MTIHEN);
}
static int lan865x_default_config(const struct device *dev, uint8_t silicon_rev)
static int lan865x_default_config(const struct device *dev)
{
const struct lan865x_config *cfg = dev->config;
struct lan865x_data *ctx = dev->data;
int ret;
/* Enable protected control RW */
oa_tc6_set_protected_ctrl(ctx->tc6, true);
ret = oa_tc6_reg_write(ctx->tc6, LAN865X_FIXUP_REG, LAN865X_FIXUP_VALUE);
if (ret) {
return ret;
}
lan865x_write_macaddress(dev);
lan865x_set_specific_multicast_addr(dev);
ret = lan865x_init_chip(dev, silicon_rev);
if (ret < 0) {
return ret;
}
if (cfg->plca->enable) {
ret = lan865x_config_plca(dev, cfg->plca->node_id, cfg->plca->node_count,
cfg->plca->burst_count, cfg->plca->burst_timer);
if (ret < 0) {
return ret;
}
}
return 0;
}
@ -420,7 +277,7 @@ static void lan865x_int_thread(const struct device *dev)
oa_tc6_reg_read(tc6, OA_STATUS0, &sts);
if (sts & OA_STATUS0_RESETC) {
oa_tc6_reg_write(tc6, OA_STATUS0, sts);
lan865x_default_config(dev, ctx->silicon_rev);
lan865x_default_config(dev);
oa_tc6_reg_read(tc6, OA_CONFIG0, &val);
val |= OA_CONFIG0_SYNC | OA_CONFIG0_RFA_ZARFE;
oa_tc6_reg_write(tc6, OA_CONFIG0, val);
@ -554,22 +411,11 @@ static const struct ethernet_api lan865x_api_func = {
};
#define LAN865X_DEFINE(inst) \
static struct lan865x_config_plca lan865x_config_plca_##inst = { \
.node_id = DT_INST_PROP(inst, plca_node_id), \
.node_count = DT_INST_PROP(inst, plca_node_count), \
.burst_count = DT_INST_PROP(inst, plca_burst_count), \
.burst_timer = DT_INST_PROP(inst, plca_burst_timer), \
.to_timer = DT_INST_PROP(inst, plca_to_timer), \
.enable = DT_INST_PROP(inst, plca_enable), \
}; \
\
static const struct lan865x_config lan865x_config_##inst = { \
.spi = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8), 0), \
.interrupt = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \
.reset = GPIO_DT_SPEC_INST_GET(inst, rst_gpios), \
.timeout = CONFIG_ETH_LAN865X_TIMEOUT, \
.plca = &lan865x_config_plca_##inst, \
}; \
\
struct oa_tc6 oa_tc6_##inst = { \
.cps = 64, .protected = 0, .spi = &lan865x_config_##inst.spi}; \

13
drivers/ethernet/eth_lan865x_priv.h
View file

@ -34,6 +34,9 @@
#define LAN865x_MAC_SAB1 MMS_REG(0x1, 0x022)
#define LAN865x_MAC_SAB2 MMS_REG(0x1, 0x024)
#define LAN865x_MAC_SAT2 MMS_REG(0x1, 0x025)
/* LAN8650/1 configuration fixup from AN1760 */
#define LAN865X_FIXUP_REG MMS_REG(0x1, 0x077)
#define LAN865X_FIXUP_VALUE 0x0028
#define LAN865x_MAC_TXRX_ON 1
#define LAN865x_MAC_TXRX_OFF 0
@ -81,14 +84,4 @@ struct lan865x_data {
k_tid_t tid_int;
};
static inline void lan865x_update_dev_cfg_array(oa_mem_map_t *cfg, uint8_t size,
uint32_t addr, uint16_t val)
{
for (uint8_t i = 0; i < size; i++) {
if (cfg[i].address == addr) {
cfg[i].value = val;
}
}
}
#endif /* ETH_LAN865X_PRIV_H__ */

6
drivers/ethernet/oa_tc6.h
View file

@ -112,12 +112,6 @@ struct oa_tc6 {
struct net_buf *concat_buf;
};
typedef struct {
uint8_t mms;
uint8_t address;
uint16_t value;
} oa_mem_map_t;
/**
* @brief Calculate parity bit from data
*

18
dts/bindings/ethernet/microchip,lan865x.yaml
View file

@ -15,24 +15,6 @@ properties:
rx-cut-through-mode:
type: boolean
description: Enable RX cut through mode
plca-enable:
type: boolean
description: Enable or disable PLCA support
plca-node-id:
type: int
description: Specify the PLCA node ID number
plca-node-count:
type: int
description: Specify the PLCA node count
plca-burst-count:
type: int
description: Specify the PLCA burst count
plca-burst-timer:
type: int
description: Specify the PLCA burst timer value
plca-to-timer:
type: int
description: Specify the PLCA to timer value
int-gpios:
type: phandle-array
required: true