From 0db19661e6eea922f549202a057b96b38e600ace Mon Sep 17 00:00:00 2001
From: Conor Paxton <conor.paxton@microchip.com>
Date: Tue, 21 Jun 2022 08:55:03 +0100
Subject: [PATCH] dts: riscv: introduce PolarFire SoC GPIO interface

Add support for the Microchip PolarFire SoC GPIO interface

Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
---
 dts/bindings/gpio/microchip,mpfs-gpio.yaml | 22 ++++++++++++
 dts/riscv/mpfs-icicle.dtsi                 | 42 ++++++++++++++++++++++
 2 files changed, 64 insertions(+)
 create mode 100644 dts/bindings/gpio/microchip,mpfs-gpio.yaml

diff --git a/dts/bindings/gpio/microchip,mpfs-gpio.yaml b/dts/bindings/gpio/microchip,mpfs-gpio.yaml
new file mode 100644
index 00000000000..6509e608e66
--- /dev/null
+++ b/dts/bindings/gpio/microchip,mpfs-gpio.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2022 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip PolarFire SoC GPIO node
+
+compatible: "microchip,mpfs-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: false
+
+    "#gpio-cells":
+      const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/riscv/mpfs-icicle.dtsi b/dts/riscv/mpfs-icicle.dtsi
index d3ddca0ca5b..356165d91f3 100644
--- a/dts/riscv/mpfs-icicle.dtsi
+++ b/dts/riscv/mpfs-icicle.dtsi
@@ -4,6 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <skeleton.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <1>;
@@ -92,5 +95,44 @@
 			status = "disabled";
 			clock-frequency = <150000000>;
 		};
+
+		gpio0: gpio@20120000 {
+			compatible = "microchip,mpfs-gpio";
+			reg = <0x20120000 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <51 1>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+			status = "disabled";
+		};
+
+		gpio1: gpio@20121000 {
+			compatible = "microchip,mpfs-gpio";
+			reg = <0x20121000 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <52 1>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+			status = "disabled";
+		};
+
+		gpio2: gpio@20122000 {
+			compatible = "microchip,mpfs-gpio";
+			reg = <0x20122000 0x1000>;
+			interrupt-parent = <&plic>;
+			interrupts = <53 1>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+			status = "disabled";
+		};
 	};
 };