boards: riscv: Add initial support for OpenTitan Earl Grey

This board is confirmed to build and run simple applications in
RTL simulation as described in the included board documentation.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>

boards/riscv/opentitan_earlgrey/Kconfig.board

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+# Copyright (c) 2023 by Rivos Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_OPENTITAN_EARLGREY
+	bool "OpenTitan Earl Grey Target"
+	depends on SOC_RISCV_OPENTITAN

boards/riscv/opentitan_earlgrey/Kconfig.defconfig

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+# Copyright (c) 2023 by Rivos Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_OPENTITAN_EARLGREY
+
+config BOARD
+	default "opentitan_earlgrey"
+
+endif # BOARD_OPENTITAN_EARLGREY

boards/riscv/opentitan_earlgrey/doc/index.rst

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+.. _opentitan_earlgrey:
+
+OpenTitan Earl Grey
+###################
+
+Overview
+********
+
+The OpenTitan Earl Grey chip is a low-power secure microcontroller that is
+designed for several use cases requiring hardware security. The `OpenTitan
+Github`_ page contains HDL code, utilities, and documentation relevant to the
+chip.
+
+Hardware
+********
+
+- RV32IMCB RISC-V "Ibex" core
+- 128kB main SRAM
+- Fixed-frequency and AON timers
+- 32 x GPIO
+- 4 x UART
+- 3 x I2C
+- 2 x SPI
+- Various security peripherals
+
+Detailed specification is on the `OpenTitan Earl Grey Chip Datasheet`_.
+
+Supported Features
+==================
+
+The ``opentitan_earlgrey`` board configuration is designed and tested to run on
+the Earl Grey chip simulated in Verilator, a cycle-accurate HDL simulation tool.
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| Timer     | on-chip    | RISC-V Machine Timer                |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling                 |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on Zephyr porting.
+
+Programming and Debugging
+*************************
+
+First, build and install Verilator as described in the `OpenTitan Verilator
+Setup`_ guide .
+
+Building and Flashing
+=====================
+
+Here is an example for building the :ref:`hello_world` application. The
+following steps were tested on OpenTitan master branch @ 6a3c2e98.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: opentitan_earlgrey
+   :goals: build
+
+The OpenTitan Vchip_sim_tb tool can take the Zephyr .elf as input and place it
+in simulated flash. The OpenTitan test ROM will then run in simulation, read
+the manifest header from simulated flash, and begin executing Zephyr from the
+entry point.
+
+.. code-block:: console
+
+   $OT_HOME/bazel-bin/hw/build.verilator_real/sim-verilator/Vchip_sim_tb --verbose-mem-load \
+   -r $OT_HOME/bazel-out/k8-fastbuild-ST-2cc462681f62/bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.39.scr.vmem \
+   --meminit=otp,$OT_HOME/bazel-out/k8-fastbuild/bin/hw/ip/otp_ctrl/data/img_rma.24.vmem \
+   --meminit=flash,$ZEPHYR_PATH/build/zephyr/zephyr.elf
+
+UART output:
+
+.. code-block:: console
+
+   I00000 test_rom.c:135] Version: earlgrey_silver_release_v5-9599-g6a3c2e988, Build Date: 2023-01-17 16:02:09
+   I00001 test_rom.c:237] Test ROM complete, jumping to flash (addr: 20000384)!
+   *** Booting Zephyr OS build zephyr-v3.2.0-3494-gf0729b494b98 ***
+   Hello World! opentitan_earlgrey
+
+References
+**********
+
+.. target-notes::
+
+.. _OpenTitan Earl Grey Chip Datasheet: https://docs.opentitan.org/hw/top_earlgrey/doc/
+
+.. _OpenTitan GitHub: https://github.com/lowRISC/opentitan
+
+.. _OpenTitan Verilator Setup: https://docs.opentitan.org/doc/getting_started/setup_verilator/

boards/riscv/opentitan_earlgrey/opentitan_earlgrey.dts

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+/*
+ * Copyright (c) 2023 by Rivos Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <lowrisc/opentitan_earlgrey.dtsi>
+
+/ {
+	model = "OpenTitan Earlgrey";
+	compatible = "lowrisc,opentitan-earlgrey";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &ram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	clock-frequency = <125000>;
+	current-speed = <7200>;
+};
+
+&mtimer {
+	status = "okay";
+};

boards/riscv/opentitan_earlgrey/opentitan_earlgrey.yaml

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+identifier: opentitan_earlgrey
+name: OpenTitan Earl Grey
+type: mcu
+arch: riscv32
+toolchain:
+  - zephyr
+ram: 128
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/riscv/opentitan_earlgrey/opentitan_earlgrey_defconfig

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+# Copyright (c) 2023 by Rivos Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_RISCV_OPENTITAN=y
+CONFIG_SOC_RISCV_OPENTITAN=y
+CONFIG_BOARD_OPENTITAN_EARLGREY=y
+CONFIG_XIP=y
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_BUILD_OUTPUT_BIN=n

dts/riscv/lowrisc/opentitan_earlgrey.dtsi

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+/*
+ * Copyright (c) 2023 by Rivos Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	#address-cells = <0x01>;
+	#size-cells = <0x01>;
+	compatible = "lowrisc,opentitan-earlgrey";
+
+	cpus {
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		timebase-frequency = <10000000>;
+
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0x00>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32imc";
+
+			hlic: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		compatible = "simple-bus";
+		ranges;
+
+		flash0: flash@20000000 {
+			reg = <0x20000000 0x100000>;
+			compatible = "soc-nv-flash";
+		};
+
+		ram0: memory@10000000 {
+			device_type = "memory";
+			reg = <0x10000000 0x10000>;
+		};
+
+		mtimer: timer@40100000 {
+			compatible = "lowrisc,machine-timer";
+			reg = <0x40100000 0x200>;
+			interrupts = <7 0>;
+			interrupt-parent = <&hlic>;
+			status = "disabled";
+		};
+
+		plic: interrupt-controller@48000000 {
+			compatible = "sifive,plic-1.0.0";
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts-extended = <&hlic 11>;
+			reg = <0x48000000 0x00002000
+			       0x48002000 0x001fe000
+			       0x48000000 0x03e00000>;
+			reg-names = "prio", "irq_en", "reg";
+			riscv,max-priority = <7>;
+			riscv,ndev = <184>;
+		};
+
+		uart0: serial@40000000{
+			reg = <0x40000000 0x1000>;
+			compatible = "lowrisc,opentitan-uart";
+			status = "disabled";
+		};
+	};
+};
+