Microchip: MEC172X DTS files reorganization

MEC172X series SoCs share most IP but the -LJ series expands the PWM and
ADC channels available as well as defines extra pinctrl pins.
Separating these better to be able to simplify their inclusion and
driver code.  Any board based on either the -SZ or -LJ package can just
include the mec172x<sz/lj> dtsi files for their specific package.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>

dts/arm/microchip/mec1727nsz.dtsi

@@ -11,14 +11,53 @@
 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
 
-#include "mec172xnsz.dtsi"
 #include "mec172x/mec172x-vw-routing.dtsi"
 #include "mec172x/mec172xnsz-pinctrl.dtsi"
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4";
+			reg = <0>;
+			cpu-power-states = <&idle &suspend_to_ram>;
+		};
+
+		power-states {
+			idle: idle {
+				compatible = "zephyr,power-state";
+				power-state-name = "suspend-to-idle";
+				min-residency-us = <1000000>;
+			};
+
+			suspend_to_ram: suspend_to_ram {
+				compatible = "zephyr,power-state";
+				power-state-name = "suspend-to-ram";
+				min-residency-us = <2000000>;
+			};
+		};
+	};
+
+	flash0: flash@c0000 {
+		reg = <0x000C0000 0x58000>;
+	};
+
 	flash1: flash@60000000 {
 		reg = <0x60000000 0x80000>;
 	};
+
+	sram0: memory@118000 {
+		compatible = "mmio-sram";
+		reg = <0x00118000 0x10000>;
+	};
+
+	soc {
+		#include "mec172x_common.dtsi"
+	};
+
 };
 
 &spi0 {

dts/arm/microchip/mec172x/mec172xnlj-pinctrl.dtsi

@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
+#include "mec172xnsz-pinctrl.dtsi"
 
 &pinctrl {
 

dts/arm/microchip/mec172xnlj.dtsi

@@ -4,11 +4,68 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "mec172xnsz.dtsi"
+#include <arm/armv7-m.dtsi>
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
+#include <freq.h>
+#include <mem.h>
+
+#include "mec172x/mec172x-vw-routing.dtsi"
 
 / {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4";
+			reg = <0>;
+			cpu-power-states = <&idle &suspend_to_ram>;
+		};
+
+		power-states {
+			idle: idle {
+				compatible = "zephyr,power-state";
+				power-state-name = "suspend-to-idle";
+				min-residency-us = <1000000>;
+			};
+
+			suspend_to_ram: suspend_to_ram {
+				compatible = "zephyr,power-state";
+				power-state-name = "suspend-to-ram";
+				min-residency-us = <2000000>;
+			};
+		};
+	};
+
+	flash0: flash@c0000 {
+		reg = <0x000C0000 0x58000>;
+	};
+
+	sram0: memory@118000 {
+		compatible = "mmio-sram";
+		reg = <0x00118000 0x10000>;
+	};
 
 	soc {
+		#include "mec172x_common.dtsi"
+
+		eeprom: eeprom@40002c00 {
+			compatible = "microchip,xec-eeprom";
+			reg = <0x40002c00 0x400>;
+			interrupts = <155 2>;
+			size = <8192>;
+			girqs = <18 13>;
+			pcrs = <4 14>;
+			status = "disabled";
+		};
+
 		pwm9: pwm@40005890 {
 			compatible = "microchip,xec-pwm";
 			reg = <0x40005890 0x20>;
@@ -32,6 +89,14 @@
 			status = "disabled";
 			#pwm-cells = <3>;
 		};
+
 	};
 };
 
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
+
+&systick {
+	status = "disabled";
+};