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drivers: clock control: stm32F412 has PLL48MHz

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Add the configuration of the PLL Q divider of main PLL
and I2S_Q of the PLLI2S toset the PLL48MHz clock which feeds
 the USB, SDMMC, RNG through the RCC_DCKCFGR2 register.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2024-11-26 15:36:07 +01:00 committed by Benjamin Cabé
parent 3651725316
commit 15bdefecc0
4 changed files with 44 additions and 0 deletions
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22
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -214,6 +214,13 @@ int enabled_clock(uint32_t src_clk)
}
break;
#endif /* STM32_SRC_PLL_R */
#if defined(STM32_SRC_PLLI2S_Q)
case STM32_SRC_PLLI2S_Q:
if (!IS_ENABLED(STM32_PLLI2S_Q_ENABLED)) {
r = -ENOTSUP;
}
break;
#endif /* STM32_SRC_PLLI2S_Q */
#if defined(STM32_SRC_PLLI2S_R)
case STM32_SRC_PLLI2S_R:
if (!IS_ENABLED(STM32_PLLI2S_R_ENABLED)) {
@ -425,6 +432,14 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
STM32_PLL_R_DIVISOR);
break;
#endif
#if defined(STM32_SRC_PLLI2S_Q) & STM32_PLLI2S_ENABLED
case STM32_SRC_PLLI2S_Q:
*rate = get_pll_div_frequency(get_pllsrc_frequency(),
STM32_PLLI2S_M_DIVISOR,
STM32_PLLI2S_N_MULTIPLIER,
STM32_PLLI2S_Q_DIVISOR);
break;
#endif /* STM32_SRC_PLLI2S_Q */
#if defined(STM32_SRC_PLLI2S_R) & STM32_PLLI2S_ENABLED
case STM32_SRC_PLLI2S_R:
*rate = get_pll_div_frequency(get_pllsrc_frequency(),
@ -433,6 +448,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
STM32_PLLI2S_R_DIVISOR);
break;
#endif /* STM32_SRC_PLLI2S_R */
/* PLLSAI1x not supported yet */
/* PLLSAI2x not supported yet */
#if defined(STM32_SRC_LSE)
@ -465,6 +481,12 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
*rate = STM32_HSI48_FREQ;
break;
#endif /* STM32_HSI48_ENABLED */
#if defined(STM32_CK48_ENABLED)
case STM32_SRC_CK48:
*rate = STM32_CK48_FREQ;
break;
#endif /* STM32_CK48_ENABLED */
default:
return -ENOTSUP;
}

3
drivers/clock_control/clock_stm32_ll_common.h
View file

@ -36,6 +36,9 @@
#endif /* RCC_PLLI2SCFGR_PLLI2SM */
#define plli2sm(v) z_plli2s_m(v)
#define z_plli2s_q(v) LL_RCC_PLLI2SQ_DIV_ ## v
#define plli2sq(v) z_plli2s_q(v)
#define z_plli2s_r(v) LL_RCC_PLLI2SR_DIV_ ## v
#define plli2sr(v) z_plli2s_r(v)

16
drivers/clock_control/clock_stm32f2_f4_f7.c
View file

@ -64,6 +64,14 @@ void config_pll_sysclock(void)
STM32_PLL_N_MULTIPLIER,
pllp(STM32_PLL_P_DIVISOR));
#if STM32_PLL_Q_ENABLED
/* There is a Q divider on the PLL to configure the PLL48CK */
LL_RCC_PLL_ConfigDomain_48M(get_pll_source(),
pllm(STM32_PLL_M_DIVISOR),
STM32_PLL_N_MULTIPLIER,
pllq(STM32_PLL_Q_DIVISOR));
#endif /* STM32_PLLI2S_Q_ENABLED */
#if defined(CONFIG_SOC_SERIES_STM32F7X)
/* Assuming we stay on Power Scale default value: Power Scale 1 */
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 180000000) {
@ -108,6 +116,14 @@ void config_plli2s(void)
plli2sm(STM32_PLLI2S_M_DIVISOR),
STM32_PLLI2S_N_MULTIPLIER,
plli2sr(STM32_PLLI2S_R_DIVISOR));
#if STM32_PLLI2S_Q_ENABLED
/* There is a Q divider on the PLLI2S to configure the PLL48CK */
LL_RCC_PLLI2S_ConfigDomain_48M(get_pll_source(),
plli2sm(STM32_PLLI2S_M_DIVISOR),
STM32_PLLI2S_N_MULTIPLIER,
plli2sq(STM32_PLLI2S_Q_DIVISOR));
#endif /* STM32_PLLI2S_Q_ENABLED */
}
#endif /* STM32_PLLI2S_ENABLED */

3
include/zephyr/drivers/clock_control/stm32_clock_control.h
View file

@ -27,6 +27,7 @@
#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32F4X)
#include <zephyr/dt-bindings/clock/stm32f4_clock.h>
#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32F7X)
#include <zephyr/dt-bindings/clock/stm32f7_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
@ -183,6 +184,8 @@
#define STM32_PLLI2S_ENABLED 1
#define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m)
#define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n)
#define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q)
#define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1)
#define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r)
#define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
#endif