driver: spi: MAX32 add RTIO support plus refactor
Implements the SPIO RTIO API. Refactors internal transcive fucntios to work with both existing SPI API and RTIO functions. When SPI_RTIO is enabled the spi_transcieve call translates the request into an RTIO transaction placed in the queue that device will execute. Include the latest refacor changes of RTIO. Signed-off-by: Dimitrije Lilic <dimitrije.lilic@orioninc.com>
This commit is contained in:
Dimitrije Lilic
Henrik Brix Andersen
parent
e78811bcd6
commit
15ec1f2016
2 changed files with 198 additions and 7 deletions
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@ -23,4 +23,28 @@ config SPI_MAX32_DMA
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help
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Enable DMA support for MAX32 MCU SPI driver.
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config SPI_MAX32_RTIO
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bool "MAX32 SPI RTIO Support"
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default y if SPI_RTIO
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depends on !SPI_ASYNC
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select SPI_MAX32_INTERRUPT
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if SPI_MAX32_RTIO
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config SPI_MAX32_RTIO_SQ_SIZE
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int "Number of available submission queue entries"
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default 8 # Sensible default that covers most common spi transactions
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help
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When RTIO is used with SPI, each driver holds a context with which blocking
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API calls use to perform SPI transactions. This queue needs to be as deep
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as the longest set of spi_buf_sets used, where normal SPI operations are
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used (equal length buffers). It may need to be slightly deeper where the
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spi buffer sets for transmit/receive are not always matched equally in
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length as these are transformed into normal transceives.
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config SPI_MAX32_RTIO_CQ_SIZE
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int "Number of available completion queue entries"
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default 8 # Sensible default that covers most common spi transactions
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endif # SPI_MAX32_RTIO
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endif # SPI_MAX32
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@ -17,6 +17,10 @@
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#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <zephyr/rtio/rtio.h>
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#include <zephyr/sys/__assert.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/spi/rtio.h>
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#include <wrap_max32_spi.h>
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@ -51,12 +55,18 @@ struct max32_spi_data {
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const struct device *dev;
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mxc_spi_req_t req;
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uint8_t dummy[2];
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#ifdef CONFIG_SPI_MAX32_DMA
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volatile uint8_t dma_stat;
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#endif /* CONFIG_SPI_MAX32_DMA */
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#ifdef CONFIG_SPI_ASYNC
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struct k_work async_work;
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#endif /* CONFIG_SPI_ASYNC */
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#ifdef CONFIG_SPI_RTIO
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struct spi_rtio *rtio_ctx;
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#endif
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};
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#ifdef CONFIG_SPI_MAX32_DMA
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@ -234,6 +244,10 @@ static int spi_max32_transceive(const struct device *dev)
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const struct max32_spi_config *cfg = dev->config;
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struct max32_spi_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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#ifdef CONFIG_SPI_RTIO
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struct spi_rtio *rtio_ctx = data->rtio_ctx;
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struct rtio_sqe *sqe = &rtio_ctx->txn_curr->sqe;
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#endif
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uint32_t len;
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uint8_t dfs_shift;
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@ -242,12 +256,48 @@ static int spi_max32_transceive(const struct device *dev)
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dfs_shift = spi_max32_get_dfs_shift(ctx);
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len = spi_context_max_continuous_chunk(ctx);
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#ifdef CONFIG_SPI_RTIO
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switch (sqe->op) {
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case RTIO_OP_RX:
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len = sqe->rx.buf_len;
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data->req.rxData = sqe->rx.buf;
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data->req.rxLen = sqe->rx.buf_len;
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data->req.txData = NULL;
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data->req.txLen = len >> dfs_shift;
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break;
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case RTIO_OP_TX:
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len = sqe->tx.buf_len;
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data->req.rxLen = 0;
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data->req.rxData = data->dummy;
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data->req.txData = (uint8_t *)sqe->tx.buf;
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data->req.txLen = len >> dfs_shift;
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break;
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case RTIO_OP_TINY_TX:
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len = sqe->tiny_tx.buf_len;
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data->req.txData = (uint8_t *)sqe->tiny_tx.buf;
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data->req.rxData = data->dummy;
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data->req.txLen = len >> dfs_shift;
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data->req.rxLen = 0;
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break;
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case RTIO_OP_TXRX:
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len = sqe->txrx.buf_len;
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data->req.txData = (uint8_t *)sqe->txrx.tx_buf;
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data->req.rxData = sqe->txrx.rx_buf;
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data->req.txLen = len >> dfs_shift;
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data->req.rxLen = len >> dfs_shift;
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break;
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default:
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break;
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}
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#else
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data->req.txLen = len >> dfs_shift;
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data->req.txData = (uint8_t *)ctx->tx_buf;
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data->req.rxLen = len >> dfs_shift;
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data->req.rxData = ctx->rx_buf;
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data->req.rxData = ctx->rx_buf;
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data->req.rxLen = len >> dfs_shift;
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if (!data->req.rxData) {
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/* Pass a dummy buffer to HAL if receive buffer is NULL, otherwise
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@ -256,6 +306,7 @@ static int spi_max32_transceive(const struct device *dev)
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data->req.rxData = data->dummy;
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data->req.rxLen = 0;
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}
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#endif
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data->req.spi = cfg->regs;
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data->req.ssIdx = ctx->config->slave;
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data->req.ssDeassert = 0;
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@ -296,10 +347,12 @@ static int transceive(const struct device *dev, const struct spi_config *config,
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bool async, spi_callback_t cb, void *userdata)
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{
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int ret = 0;
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const struct max32_spi_config *cfg = dev->config;
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struct max32_spi_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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#ifndef CONFIG_SPI_RTIO
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const struct max32_spi_config *cfg = dev->config;
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bool hw_cs_ctrl = true;
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#endif
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#ifndef CONFIG_SPI_MAX32_INTERRUPT
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if (async) {
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@ -309,6 +362,7 @@ static int transceive(const struct device *dev, const struct spi_config *config,
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spi_context_lock(ctx, async, cb, userdata, config);
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#ifndef CONFIG_SPI_RTIO
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ret = spi_configure(dev, config);
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if (ret != 0) {
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spi_context_release(ctx, ret);
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@ -363,9 +417,12 @@ static int transceive(const struct device *dev, const struct spi_config *config,
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cfg->regs->ctrl0 |= MXC_F_SPI_CTRL0_EN;
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}
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}
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#else
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struct spi_rtio *rtio_ctx = data->rtio_ctx;
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ret = spi_rtio_transceive(rtio_ctx, config, tx_bufs, rx_bufs);
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#endif
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spi_context_release(ctx, ret);
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return ret;
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}
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@ -565,6 +622,99 @@ unlock:
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}
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#endif /* CONFIG_SPI_MAX32_DMA */
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#ifdef CONFIG_SPI_RTIO
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static void spi_max32_iodev_complete(const struct device *dev, int status);
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static void spi_max32_iodev_start(const struct device *dev)
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{
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struct max32_spi_data *data = dev->data;
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struct spi_rtio *rtio_ctx = data->rtio_ctx;
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struct rtio_sqe *sqe = &rtio_ctx->txn_curr->sqe;
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int ret = 0;
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switch (sqe->op) {
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case RTIO_OP_RX:
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case RTIO_OP_TX:
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case RTIO_OP_TINY_TX:
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case RTIO_OP_TXRX:
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ret = spi_max32_transceive(dev);
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break;
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default:
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spi_max32_iodev_complete(dev, -EINVAL);
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break;
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}
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if (ret != 0) {
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spi_max32_iodev_complete(dev, -EIO);
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}
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}
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static inline void spi_max32_iodev_prepare_start(const struct device *dev)
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{
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struct max32_spi_data *data = dev->data;
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struct spi_rtio *rtio_ctx = data->rtio_ctx;
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struct spi_dt_spec *spi_dt_spec = rtio_ctx->txn_curr->sqe.iodev->data;
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struct spi_config *spi_config = &spi_dt_spec->config;
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struct max32_spi_config *cfg = (struct max32_spi_config *)dev->config;
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int ret;
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bool hw_cs_ctrl = true;
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ret = spi_configure(dev, spi_config);
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__ASSERT(!ret, "%d", ret);
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/* Check if CS GPIO exists */
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if (spi_cs_is_gpio(spi_config)) {
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hw_cs_ctrl = false;
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}
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MXC_SPI_HWSSControl(cfg->regs, hw_cs_ctrl);
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/* Assert the CS line if HW control disabled */
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if (!hw_cs_ctrl) {
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spi_context_cs_control(&data->ctx, true);
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} else {
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cfg->regs->ctrl0 = (cfg->regs->ctrl0 & ~MXC_F_SPI_CTRL0_START) |
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MXC_F_SPI_CTRL0_SS_CTRL;
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};
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}
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static void spi_max32_iodev_complete(const struct device *dev, int status)
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{
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struct max32_spi_data *data = dev->data;
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struct spi_rtio *rtio_ctx = data->rtio_ctx;
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if (!status && rtio_ctx->txn_curr->sqe.flags & RTIO_SQE_TRANSACTION) {
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rtio_ctx->txn_curr = rtio_txn_next(rtio_ctx->txn_curr);
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spi_max32_iodev_start(dev);
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} else {
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struct max32_spi_config *cfg = (struct max32_spi_config *)dev->config;
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bool hw_cs_ctrl = true;
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if (!hw_cs_ctrl) {
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spi_context_cs_control(&data->ctx, false);
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} else {
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cfg->regs->ctrl0 &= ~(MXC_F_SPI_CTRL0_START | MXC_F_SPI_CTRL0_SS_CTRL |
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MXC_F_SPI_CTRL0_EN);
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cfg->regs->ctrl0 |= MXC_F_SPI_CTRL0_EN;
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}
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if (spi_rtio_complete(rtio_ctx, status)) {
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spi_max32_iodev_prepare_start(dev);
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spi_max32_iodev_start(dev);
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}
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}
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}
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static void api_iodev_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
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{
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struct max32_spi_data *data = dev->data;
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struct spi_rtio *rtio_ctx = data->rtio_ctx;
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if (spi_rtio_submit(rtio_ctx, iodev_sqe)) {
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spi_max32_iodev_prepare_start(dev);
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spi_max32_iodev_start(dev);
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}
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}
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#endif
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static int api_transceive(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs)
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{
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@ -596,6 +746,13 @@ static void spi_max32_callback(mxc_spi_req_t *req, int error)
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const struct device *dev = data->dev;
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uint32_t len;
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#ifdef CONFIG_SPI_RTIO
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struct spi_rtio *rtio_ctx = data->rtio_ctx;
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if (rtio_ctx->txn_head != NULL) {
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spi_max32_iodev_complete(data->dev, 0);
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}
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#endif
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len = spi_context_max_continuous_chunk(ctx);
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spi_context_update_tx(ctx, 1, len);
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spi_context_update_rx(ctx, 1, len);
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@ -685,12 +842,12 @@ static int api_release(const struct device *dev, const struct spi_config *config
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{
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struct max32_spi_data *data = dev->data;
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#ifndef CONFIG_SPI_RTIO
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if (!spi_context_configured(&data->ctx, config)) {
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return -EINVAL;
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}
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#endif
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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@ -724,6 +881,10 @@ static int spi_max32_init(const struct device *dev)
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data->dev = dev;
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#ifdef CONFIG_SPI_RTIO
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spi_rtio_init(data->rtio_ctx, dev);
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#endif
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#ifdef CONFIG_SPI_MAX32_INTERRUPT
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cfg->irq_config_func(dev);
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#ifdef CONFIG_SPI_ASYNC
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@ -743,8 +904,8 @@ static const struct spi_driver_api spi_max32_api = {
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.transceive_async = api_transceive_async,
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#endif /* CONFIG_SPI_ASYNC */
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#ifdef CONFIG_SPI_RTIO
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.iodev_submit = spi_rtio_iodev_default_submit,
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#endif
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.iodev_submit = api_iodev_submit,
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#endif /* CONFIG_SPI_RTIO */
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.release = api_release,
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};
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@ -784,9 +945,14 @@ static const struct spi_driver_api spi_max32_api = {
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#define MAX32_SPI_DMA_INIT(n)
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#endif
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#define DEFINE_SPI_MAX32_RTIO(_num) SPI_RTIO_DEFINE(max32_spi_rtio_##_num, \
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CONFIG_SPI_MAX32_RTIO_SQ_SIZE, \
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CONFIG_SPI_MAX32_RTIO_CQ_SIZE)
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#define DEFINE_SPI_MAX32(_num) \
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PINCTRL_DT_INST_DEFINE(_num); \
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SPI_MAX32_IRQ_CONFIG_FUNC(_num) \
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COND_CODE_1(CONFIG_SPI_RTIO, (DEFINE_SPI_MAX32_RTIO(_num)), ()); \
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static const struct max32_spi_config max32_spi_config_##_num = { \
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.regs = (mxc_spi_regs_t *)DT_INST_REG_ADDR(_num), \
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.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num), \
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@ -797,7 +963,8 @@ static const struct spi_driver_api spi_max32_api = {
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static struct max32_spi_data max32_spi_data_##_num = { \
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SPI_CONTEXT_INIT_LOCK(max32_spi_data_##_num, ctx), \
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SPI_CONTEXT_INIT_SYNC(max32_spi_data_##_num, ctx), \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(_num), ctx)}; \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(_num), ctx) \
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IF_ENABLED(CONFIG_SPI_RTIO, (.rtio_ctx = &max32_spi_rtio_##_num))}; \
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DEVICE_DT_INST_DEFINE(_num, spi_max32_init, NULL, &max32_spi_data_##_num, \
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&max32_spi_config_##_num, PRE_KERNEL_2, CONFIG_SPI_INIT_PRIORITY, \
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&spi_max32_api);
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