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llext: flush dcache in the llext memory range

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On architectures that have separate data and instruction caches, such as
the Cortex-M7, it is required to flush the reloc changes to the actual RAM
storage before trying to execute any code from the newly loaded llext.

Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
This commit is contained in:
Luca Burelli 2023-12-01 18:43:40 +01:00 committed by Anas Nashif
parent e96b713caf
commit 1732177530
1 changed files with 10 additions and 0 deletions
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10
subsys/llext/llext.c
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@ -11,6 +11,7 @@
#include <zephyr/llext/loader.h> #include <zephyr/llext/loader.h>
#include <zephyr/llext/llext.h> #include <zephyr/llext/llext.h>
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#include <zephyr/cache.h>
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(llext, CONFIG_LLEXT_LOG_LEVEL); LOG_MODULE_REGISTER(llext, CONFIG_LLEXT_LOG_LEVEL);
@ -776,6 +777,15 @@ static int llext_link(struct llext_loader *ldr, struct llext *ext, bool do_local
} }
} }
#ifdef CONFIG_CACHE_MANAGEMENT
/* Make sure changes to ext sections are flushed to RAM */
for (i = 0; i < LLEXT_MEM_COUNT; ++i) {
if (ext->mem[i]) {
arch_dcache_flush_range(ext->mem[i], ext->mem_size[i]);
}
}
#endif
return 0; return 0;
} }