drivers: adc: esp32: dma enable
adc dma mode operation on ESP32S3 and ESP32C3 Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
This commit is contained in:
Marcio Ribeiro
Carles Cufí
parent
bb770c5965
commit
19d8ade5fa
2 changed files with 411 additions and 1 deletions
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@ -8,3 +8,15 @@ config ADC_ESP32
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depends on DT_HAS_ESPRESSIF_ESP32_ADC_ENABLED
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help
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Enable the driver implementation for the ESP32 ADC
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if ADC_ESP32
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config ADC_ESP32_DMA
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bool "ESP32 ADC DMA Support"
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default n
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depends on DT_HAS_ESPRESSIF_ESP32_GDMA_ENABLED
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help
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Enable the ADC DMA mode for ADC instances
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that enable dma channels in their device tree node.
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endif
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@ -9,12 +9,25 @@
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#include <errno.h>
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#include <hal/adc_hal.h>
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#include <hal/adc_types.h>
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#include <soc/adc_periph.h>
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#include <esp_adc_cal.h>
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#include <esp_clk_tree.h>
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#include <esp_private/periph_ctrl.h>
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#include <esp_private/sar_periph_ctrl.h>
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#include <esp_private/adc_share_hw_ctrl.h>
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#if defined(CONFIG_ADC_ESP32_DMA)
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#if !SOC_GDMA_SUPPORTED
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#error "SoCs without GDMA peripheral are not supported!"
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#endif
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#include <zephyr/drivers/dma.h>
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#include <zephyr/drivers/dma/dma_esp32.h>
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#endif
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL);
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@ -43,9 +56,16 @@ LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL);
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/* Default internal reference voltage */
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#define ADC_ESP32_DEFAULT_VREF_INTERNAL (1100)
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#define ADC_DMA_BUFFER_SIZE DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED
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struct adc_esp32_conf {
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adc_unit_t unit;
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uint8_t channel_count;
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#if defined(CONFIG_ADC_ESP32_DMA)
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const struct device *gpio_port;
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const struct device *dma_dev;
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uint8_t dma_channel;
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#endif /* defined(CONFIG_ADC_ESP32_DMA) */
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};
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struct adc_esp32_data {
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@ -54,8 +74,12 @@ struct adc_esp32_data {
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esp_adc_cal_characteristics_t chars[SOC_ADC_MAX_CHANNEL_NUM];
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uint16_t meas_ref_internal;
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uint16_t *buffer;
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uint16_t *buffer_repeat;
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bool calibrate;
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#if defined(CONFIG_ADC_ESP32_DMA)
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adc_hal_dma_ctx_t adc_hal_dma_ctx;
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uint8_t *dma_buffer;
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struct k_sem dma_conv_wait_lock;
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#endif /* defined(CONFIG_ADC_ESP32_DMA) */
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};
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/* Convert zephyr,gain property to the ESP32 attenuation */
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@ -80,6 +104,7 @@ static inline int gain_to_atten(enum adc_gain gain, adc_atten_t *atten)
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return 0;
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}
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#if !defined(CONFIG_ADC_ESP32_DMA)
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/* Convert voltage by inverted attenuation to support zephyr gain values */
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static void atten_to_gain(adc_atten_t atten, uint32_t *val_mv)
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{
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@ -101,6 +126,7 @@ static void atten_to_gain(adc_atten_t atten, uint32_t *val_mv)
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break;
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}
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}
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#endif /* !defined(CONFIG_ADC_ESP32_DMA) */
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static bool adc_calibration_init(const struct device *dev)
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{
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@ -120,9 +146,229 @@ static bool adc_calibration_init(const struct device *dev)
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LOG_ERR("Invalid arg");
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break;
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}
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return false;
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}
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#if defined(CONFIG_ADC_ESP32_DMA)
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static void IRAM_ATTR adc_esp32_dma_conv_done(const struct device *dma_dev, void *user_data,
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uint32_t channel, int status)
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{
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ARG_UNUSED(dma_dev);
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ARG_UNUSED(status);
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const struct device *dev = user_data;
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struct adc_esp32_data *data = dev->data;
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k_sem_give(&data->dma_conv_wait_lock);
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}
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static int adc_esp32_dma_start(const struct device *dev, uint8_t *buf, size_t len)
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{
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const struct adc_esp32_conf *conf = dev->config;
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struct adc_esp32_data *data = dev->data;
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int err = 0;
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struct dma_config dma_cfg = {0};
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struct dma_status dma_status = {0};
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struct dma_block_config dma_blk = {0};
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err = dma_get_status(conf->dma_dev, conf->dma_channel, &dma_status);
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if (err) {
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LOG_ERR("Unable to get dma channel[%u] status (%d)",
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(unsigned int)conf->dma_channel, err);
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return -EINVAL;
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}
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if (dma_status.busy) {
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LOG_ERR("dma channel[%u] is busy!", (unsigned int)conf->dma_channel);
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return -EBUSY;
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}
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unsigned int key = irq_lock();
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dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
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dma_cfg.dma_callback = adc_esp32_dma_conv_done;
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dma_cfg.user_data = (void *)dev;
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dma_cfg.dma_slot = ESP_GDMA_TRIG_PERIPH_ADC0;
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dma_cfg.block_count = 1;
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dma_cfg.head_block = &dma_blk;
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dma_blk.block_size = len;
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dma_blk.dest_address = (uint32_t)buf;
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err = dma_config(conf->dma_dev, conf->dma_channel, &dma_cfg);
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if (err) {
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LOG_ERR("Error configuring dma (%d)", err);
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goto unlock;
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}
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err = dma_start(conf->dma_dev, conf->dma_channel);
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if (err) {
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LOG_ERR("Error starting dma (%d)", err);
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goto unlock;
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}
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unlock:
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irq_unlock(key);
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return err;
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}
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static int adc_esp32_dma_stop(const struct device *dev)
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{
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const struct adc_esp32_conf *conf = dev->config;
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unsigned int key = irq_lock();
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int err = 0;
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err = dma_stop(conf->dma_dev, conf->dma_channel);
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if (err) {
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LOG_ERR("Error stopping dma (%d)", err);
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}
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irq_unlock(key);
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return err;
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}
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static int adc_esp32_fill_digi_pattern(const struct device *dev, const struct adc_sequence *seq,
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void *pattern_config, uint32_t *pattern_len, uint32_t *unit_attenuation)
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{
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const struct adc_esp32_conf *conf = dev->config;
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struct adc_esp32_data *data = dev->data;
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adc_digi_pattern_config_t *adc_digi_pattern_config =
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(adc_digi_pattern_config_t *)pattern_config;
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const uint32_t unit_atten_uninit = 999;
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uint32_t channel_mask = 1, channels_copy = seq->channels;
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*pattern_len = 0;
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*unit_attenuation = unit_atten_uninit;
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for (uint8_t channel_id = 0; channel_id < conf->channel_count; channel_id++) {
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if (channels_copy & channel_mask) {
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if (*unit_attenuation == unit_atten_uninit) {
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*unit_attenuation = data->attenuation[channel_id];
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} else if (*unit_attenuation != data->attenuation[channel_id]) {
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LOG_ERR("Channel[%u] attenuation different of unit[%u] attenuation",
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(unsigned int)channel_id, (unsigned int)conf->unit);
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return -EINVAL;
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}
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adc_digi_pattern_config->atten = data->attenuation[channel_id];
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adc_digi_pattern_config->channel = channel_id;
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adc_digi_pattern_config->unit = conf->unit;
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adc_digi_pattern_config->bit_width = seq->resolution;
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adc_digi_pattern_config++;
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*pattern_len += 1;
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if (*pattern_len > SOC_ADC_PATT_LEN_MAX) {
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LOG_ERR("Max pattern len is %d", SOC_ADC_PATT_LEN_MAX);
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return -EINVAL;
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}
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channels_copy &= ~channel_mask;
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if (!channels_copy) {
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break;
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}
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}
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channel_mask <<= 1;
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}
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return 0;
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}
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static void adc_esp32_digi_start(const struct device *dev, void *pattern_config,
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uint32_t pattern_len, uint32_t number_of_samplings,
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uint32_t sample_freq_hz, uint32_t unit_attenuation)
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{
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const struct adc_esp32_conf *conf = dev->config;
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struct adc_esp32_data *data = dev->data;
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sar_periph_ctrl_adc_continuous_power_acquire();
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adc_lock_acquire(conf->unit);
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#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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adc_set_hw_calibration_code(conf->unit, unit_attenuation);
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#endif /* SOC_ADC_CALIBRATION_V1_SUPPORTED */
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#if SOC_ADC_ARBITER_SUPPORTED
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if (conf->unit == ADC_UNIT_2) {
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adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
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adc_hal_arbiter_config(&config);
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}
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#endif /* SOC_ADC_ARBITER_SUPPORTED */
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adc_hal_digi_ctrlr_cfg_t adc_hal_digi_ctrlr_cfg;
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soc_module_clk_t clk_src = ADC_DIGI_CLK_SRC_DEFAULT;
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uint32_t clk_src_freq_hz = 0;
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esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
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&clk_src_freq_hz);
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adc_hal_digi_ctrlr_cfg.conv_mode =
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(conf->unit == ADC_UNIT_1)?ADC_CONV_SINGLE_UNIT_1:ADC_CONV_SINGLE_UNIT_2;
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adc_hal_digi_ctrlr_cfg.clk_src = clk_src;
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adc_hal_digi_ctrlr_cfg.clk_src_freq_hz = clk_src_freq_hz;
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adc_hal_digi_ctrlr_cfg.sample_freq_hz = sample_freq_hz;
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adc_hal_digi_ctrlr_cfg.adc_pattern = (adc_digi_pattern_config_t *)pattern_config;
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adc_hal_digi_ctrlr_cfg.adc_pattern_len = pattern_len;
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uint32_t number_of_adc_digi_samples = number_of_samplings * pattern_len;
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adc_hal_dma_config_t adc_hal_dma_config = {
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.dev = (void *)GDMA_LL_GET_HW(0),
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.eof_desc_num = 1,
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.eof_step = 1,
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.dma_chan = conf->dma_channel,
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.eof_num = number_of_adc_digi_samples,
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};
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adc_hal_dma_ctx_config(&data->adc_hal_dma_ctx, &adc_hal_dma_config);
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adc_hal_set_controller(conf->unit, ADC_HAL_CONTINUOUS_READ_MODE);
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adc_hal_digi_init(&data->adc_hal_dma_ctx);
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adc_hal_digi_controller_config(&data->adc_hal_dma_ctx, &adc_hal_digi_ctrlr_cfg);
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adc_hal_digi_start(&data->adc_hal_dma_ctx, data->dma_buffer);
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}
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static void adc_esp32_digi_stop(const struct device *dev)
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{
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const struct adc_esp32_conf *conf = dev->config;
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struct adc_esp32_data *data = dev->data;
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adc_hal_digi_dis_intr(&data->adc_hal_dma_ctx, ADC_HAL_DMA_INTR_MASK);
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adc_hal_digi_clr_intr(&data->adc_hal_dma_ctx, ADC_HAL_DMA_INTR_MASK);
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adc_hal_digi_stop(&data->adc_hal_dma_ctx);
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adc_hal_digi_deinit(&data->adc_hal_dma_ctx);
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adc_lock_release(conf->unit);
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sar_periph_ctrl_adc_continuous_power_release();
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}
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static void adc_esp32_fill_seq_buffer(const void *seq_buffer, const void *dma_buffer,
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uint32_t number_of_samples)
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{
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uint16_t *sample = (uint16_t *)seq_buffer;
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adc_digi_output_data_t *digi_data = (adc_digi_output_data_t *)dma_buffer;
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for (uint32_t k = 0; k < number_of_samples; k++) {
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*sample++ = (uint16_t)(digi_data++)->type2.data;
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}
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}
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static int adc_esp32_wait_for_dma_conv_done(const struct device *dev)
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{
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struct adc_esp32_data *data = dev->data;
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int err = 0;
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err = k_sem_take(&data->dma_conv_wait_lock, K_FOREVER);
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if (err) {
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LOG_ERR("Error taking dma_conv_wait_lock (%d)", err);
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}
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return err;
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}
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#endif /* defined(CONFIG_ADC_ESP32_DMA) */
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static int adc_esp32_read(const struct device *dev, const struct adc_sequence *seq)
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{
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const struct adc_esp32_conf *conf = dev->config;
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@ -137,10 +383,12 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
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return -ENOMEM;
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}
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#if !defined(CONFIG_ADC_ESP32_DMA)
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if (seq->channels > BIT(channel_id)) {
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LOG_ERR("Multi-channel readings not supported");
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return -ENOTSUP;
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}
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#endif /* !defined(CONFIG_ADC_ESP32_DMA) */
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if (seq->options) {
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if (seq->options->extra_samplings) {
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@ -148,10 +396,12 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
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return -ENOTSUP;
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}
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#if !defined(CONFIG_ADC_ESP32_DMA)
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if (seq->options->interval_us) {
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LOG_ERR("Interval between samplings not supported");
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return -ENOTSUP;
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}
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#endif /* !defined(CONFIG_ADC_ESP32_DMA) */
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}
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if (INVALID_RESOLUTION(seq->resolution)) {
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@ -176,6 +426,7 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
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adc_set_data_width(conf->unit, WIDTH_MASK(data->resolution[channel_id]));
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#endif /* CONFIG_SOC_SERIES_ESP32C3 */
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#if !defined(CONFIG_ADC_ESP32_DMA)
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/* Read raw value */
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if (conf->unit == ADC_UNIT_1) {
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reading = adc1_get_raw(channel_id);
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@ -216,6 +467,74 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
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data->buffer = (uint16_t *) seq->buffer;
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data->buffer[0] = cal;
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#else /* !defined(CONFIG_ADC_ESP32_DMA) */
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int err = 0;
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uint32_t adc_pattern_len, unit_attenuation;
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adc_digi_pattern_config_t adc_digi_pattern_config[SOC_ADC_MAX_CHANNEL_NUM];
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err = adc_esp32_fill_digi_pattern(dev, seq, &adc_digi_pattern_config,
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&adc_pattern_len, &unit_attenuation);
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if (err || adc_pattern_len == 0) {
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return -EINVAL;
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}
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const struct adc_sequence_options *options = seq->options;
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uint32_t sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH,
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number_of_samplings = 1;
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if (options != NULL) {
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number_of_samplings = seq->buffer_size / (adc_pattern_len * sizeof(uint16_t));
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if (options->interval_us) {
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sample_freq_hz = MHZ(1) / options->interval_us;
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}
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}
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if (!number_of_samplings) {
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LOG_ERR("buffer_size insufficient to store at least one set of samples!");
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return -EINVAL;
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}
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if (sample_freq_hz < SOC_ADC_SAMPLE_FREQ_THRES_LOW ||
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sample_freq_hz > SOC_ADC_SAMPLE_FREQ_THRES_HIGH) {
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LOG_ERR("ADC sampling frequency out of range: %uHz", sample_freq_hz);
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return -EINVAL;
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}
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uint32_t number_of_adc_samples = number_of_samplings * adc_pattern_len;
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uint32_t number_of_adc_dma_data_bytes =
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number_of_adc_samples * SOC_ADC_DIGI_DATA_BYTES_PER_CONV;
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if (number_of_adc_dma_data_bytes > ADC_DMA_BUFFER_SIZE) {
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LOG_ERR("dma buffer size insufficient to store a complete sequence!");
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return -EINVAL;
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}
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err = adc_esp32_dma_start(dev, data->dma_buffer, number_of_adc_dma_data_bytes);
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if (err) {
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return err;
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}
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adc_esp32_digi_start(dev, &adc_digi_pattern_config, adc_pattern_len, number_of_samplings,
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sample_freq_hz, unit_attenuation);
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err = adc_esp32_wait_for_dma_conv_done(dev);
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if (err) {
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return err;
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}
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adc_esp32_digi_stop(dev);
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err = adc_esp32_dma_stop(dev);
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if (err) {
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return err;
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}
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|
||||
adc_esp32_fill_seq_buffer(seq->buffer, data->dma_buffer, number_of_adc_samples);
|
||||
|
||||
#endif /* !defined(CONFIG_ADC_ESP32_DMA) */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -284,6 +603,34 @@ static int adc_esp32_channel_setup(const struct device *dev, const struct adc_ch
|
|||
LOG_DBG("Using ADC calibration method %d", cal);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ADC_ESP32_DMA)
|
||||
|
||||
if (!SOC_ADC_DIG_SUPPORTED_UNIT(conf->unit)) {
|
||||
LOG_ERR("ADC2 dma mode is no longer supported, please use ADC1!");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int io_num = adc_channel_io_map[conf->unit][cfg->channel_id];
|
||||
|
||||
if (io_num < 0) {
|
||||
LOG_ERR("Channel %u not supported!", cfg->channel_id);
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
struct gpio_dt_spec gpio = {
|
||||
.port = conf->gpio_port,
|
||||
.dt_flags = 0,
|
||||
.pin = io_num,
|
||||
};
|
||||
|
||||
err = gpio_pin_configure_dt(&gpio, GPIO_DISCONNECTED);
|
||||
if (err) {
|
||||
LOG_ERR("Error disconnecting io (%d)", io_num);
|
||||
return err;
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_ADC_ESP32_DMA) */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -291,9 +638,41 @@ static int adc_esp32_init(const struct device *dev)
|
|||
{
|
||||
struct adc_esp32_data *data = (struct adc_esp32_data *) dev->data;
|
||||
|
||||
#if defined(CONFIG_ADC_ESP32_DMA)
|
||||
struct adc_esp32_conf *conf = (struct adc_esp32_conf *) dev->config;
|
||||
|
||||
if (!device_is_ready(conf->gpio_port)) {
|
||||
LOG_ERR("gpio0 port not ready");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (k_sem_init(&data->dma_conv_wait_lock, 0, 1)) {
|
||||
LOG_ERR("dma_conv_wait_lock initialization failed!");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data->adc_hal_dma_ctx.rx_desc = k_aligned_alloc(sizeof(uint32_t),
|
||||
sizeof(dma_descriptor_t));
|
||||
if (!data->adc_hal_dma_ctx.rx_desc) {
|
||||
LOG_ERR("rx_desc allocation failed!");
|
||||
return -ENOMEM;
|
||||
}
|
||||
LOG_DBG("rx_desc = 0x%08X", (unsigned int)data->adc_hal_dma_ctx.rx_desc);
|
||||
|
||||
data->dma_buffer = k_aligned_alloc(sizeof(uint32_t), ADC_DMA_BUFFER_SIZE);
|
||||
if (!data->dma_buffer) {
|
||||
LOG_ERR("dma buffer allocation failed!");
|
||||
k_free(data->adc_hal_dma_ctx.rx_desc);
|
||||
return -ENOMEM;
|
||||
}
|
||||
LOG_DBG("data->dma_buffer = 0x%08X", (unsigned int)data->dma_buffer);
|
||||
|
||||
#endif /* defined(CONFIG_ADC_ESP32_DMA) */
|
||||
|
||||
for (uint8_t i = 0; i < ARRAY_SIZE(data->resolution); i++) {
|
||||
data->resolution[i] = ADC_RESOLUTION_MAX;
|
||||
}
|
||||
|
||||
for (uint8_t i = 0; i < ARRAY_SIZE(data->attenuation); i++) {
|
||||
data->attenuation[i] = ADC_ATTEN_DB_0;
|
||||
}
|
||||
|
|
@ -316,11 +695,30 @@ static const struct adc_driver_api api_esp32_driver_api = {
|
|||
.ref_internal = ADC_ESP32_DEFAULT_VREF_INTERNAL,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ADC_ESP32_DMA)
|
||||
|
||||
#define ADC_ESP32_CONF_GPIO_PORT_INIT .gpio_port = DEVICE_DT_GET(DT_NODELABEL(gpio0)),
|
||||
|
||||
#define ADC_ESP32_CONF_DMA_INIT(n) .dma_dev = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
|
||||
(DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(n, 0))), \
|
||||
(NULL)), \
|
||||
.dma_channel = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
|
||||
(DT_INST_DMAS_CELL_BY_IDX(n, 0, channel)), \
|
||||
(0xff)),
|
||||
#else
|
||||
|
||||
#define ADC_ESP32_CONF_GPIO_PORT_INIT
|
||||
#define ADC_ESP32_CONF_DMA_INIT(inst)
|
||||
|
||||
#endif /* defined(CONFIG_ADC_ESP32_DMA) */
|
||||
|
||||
#define ESP32_ADC_INIT(inst) \
|
||||
\
|
||||
static const struct adc_esp32_conf adc_esp32_conf_##inst = { \
|
||||
.unit = DT_PROP(DT_DRV_INST(inst), unit) - 1, \
|
||||
.channel_count = DT_PROP(DT_DRV_INST(inst), channel_count), \
|
||||
ADC_ESP32_CONF_GPIO_PORT_INIT \
|
||||
ADC_ESP32_CONF_DMA_INIT(inst) \
|
||||
}; \
|
||||
\
|
||||
static struct adc_esp32_data adc_esp32_data_##inst = { \
|
||||
|
|
|
|||
Loading…
Reference in a new issue