From 1d3f5ac13d0ffebb189a45f0afe94c245d0d3d88 Mon Sep 17 00:00:00 2001
From: Andrew Featherstone <andrew.featherstone@gmail.com>
Date: Fri, 23 Aug 2024 10:28:44 +0100
Subject: [PATCH] drivers: hwinfo: rp2350: Add initial support for RP2350

Extend the existing driver to add some initial support for the new SoC,
whilst maintaining compatibility with the RP2040.

Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
---
 drivers/hwinfo/hwinfo_rpi_pico.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/hwinfo/hwinfo_rpi_pico.c b/drivers/hwinfo/hwinfo_rpi_pico.c
index 89d5cb5654c..b83078e4b49 100644
--- a/drivers/hwinfo/hwinfo_rpi_pico.c
+++ b/drivers/hwinfo/hwinfo_rpi_pico.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022 Yonatan Schachter
+ * Copyright (c) 2024 Andrew Featherstone
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,13 +8,23 @@
 #include <string.h>
 #include <zephyr/drivers/hwinfo.h>
 #include <hardware/flash.h>
+#if defined(CONFIG_SOC_SERIES_RP2040)
 #include <hardware/structs/vreg_and_chip_reset.h>
+#else
+#include <hardware/structs/powman.h>
+#endif
 
 #define FLASH_RUID_DATA_BYTES 8
 
+#if defined(CONFIG_SOC_SERIES_RP2040)
 #define HAD_RUN_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB)
 #define HAD_PSM_RESTART_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB)
 #define HAD_POR_BIT BIT(VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB)
+#else
+#define HAD_RUN_BIT BIT(POWMAN_CHIP_RESET_HAD_RUN_LOW_LSB)
+#define HAD_PSM_RESTART_BIT BIT(POWMAN_CHIP_RESET_HAD_DP_RESET_REQ_LSB)
+#define HAD_POR_BIT BIT(POWMAN_CHIP_RESET_HAD_POR_LSB)
+#endif
 
 ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
 {
@@ -41,7 +52,11 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
 int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
 {
 	uint32_t flags = 0;
+#if defined(CONFIG_SOC_SERIES_RP2040)
 	uint32_t reset_register = vreg_and_chip_reset_hw->chip_reset;
+#else
+	uint32_t reset_register = powman_hw->chip_reset;
+#endif
 
 	if (reset_register & HAD_POR_BIT) {
 		flags |= RESET_POR;
@@ -54,6 +69,18 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
 	if (reset_register & HAD_PSM_RESTART_BIT) {
 		flags |= RESET_DEBUG;
 	}
+#if defined(CONFIG_SOC_SERIES_RP2350)
+	if (reset_register & POWMAN_CHIP_RESET_HAD_BOR_BITS) {
+		flags |= RESET_BROWNOUT;
+	}
+
+	if (reset_register & (POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_RSM_BITS |
+			      POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_SWCORE_BITS |
+			      POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_BITS |
+			      POWMAN_CHIP_RESET_HAD_WATCHDOG_RESET_POWMAN_ASYNC_BITS)) {
+		flags |= RESET_WATCHDOG;
+	}
+#endif
 
 	*cause = flags;
 	return 0;
@@ -69,6 +96,9 @@ int z_impl_hwinfo_clear_reset_cause(void)
 int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
 {
 	*supported = RESET_PIN | RESET_DEBUG | RESET_POR;
+#if defined(CONFIG_SOC_SERIES_RP2350)
+	*supported |= RESET_BROWNOUT | RESET_WATCHDOG;
+#endif
 
 	return 0;
 }