drivers: counter: Reset timer using RCC before initialization
In multi-image environment, after jump to the image we can have running timer with interrupts enabled. If interrupt is triggered, the asserts in the driver can cause a crash. This patch also adds 'resets' property for all timer nodes. Signed-off-by: Patryk Duda <pdk@semihalf.com>
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2 changed files with 15 additions and 1 deletions
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@ -6,5 +6,6 @@ config COUNTER_TIMER_STM32
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default y
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depends on DT_HAS_ST_STM32_COUNTER_ENABLED
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select USE_STM32_LL_TIM
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select RESET
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help
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Enable the counter driver for STM32 family of processors.
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@ -8,6 +8,7 @@
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#include <zephyr/drivers/counter.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/drivers/reset.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/atomic.h>
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@ -86,6 +87,8 @@ struct counter_stm32_data {
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uint32_t guard_period;
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atomic_t cc_int_pending;
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uint32_t freq;
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/* Reset controller device configuration */
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const struct reset_dt_spec reset;
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};
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struct counter_stm32_ch_data {
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@ -473,6 +476,14 @@ static int counter_stm32_init_timer(const struct device *dev)
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}
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data->freq = tim_clk / (cfg->prescaler + 1U);
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if (!device_is_ready(data->reset.dev)) {
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LOG_ERR("reset controller not ready");
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return -ENODEV;
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}
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/* Reset timer to default state using RCC */
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reset_line_toggle_dt(&data->reset);
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/* config/enable IRQ */
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cfg->irq_config_func(dev);
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@ -617,7 +628,9 @@ void counter_stm32_irq_handler(const struct device *dev)
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BUILD_ASSERT(NUM_CH(TIM(idx)) <= TIMER_MAX_CH, \
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"TIMER too many channels"); \
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\
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static struct counter_stm32_data counter##idx##_data; \
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static struct counter_stm32_data counter##idx##_data = { \
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.reset = RESET_DT_SPEC_GET(TIMER(idx)), \
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}; \
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static struct counter_stm32_ch_data counter##idx##_ch_data[TIMER_MAX_CH]; \
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\
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static void counter_##idx##_stm32_irq_config(const struct device *dev) \
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