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boards: nucleo_h563zi: change pll1 pllq frequency to 160MHz

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In preparation for CAN support, this commit changes the q divier of PLL1
from 2 to 3 to result in a output frequency of 160MHz.
Using a can clk-divider of 2 a 80MHz Core clock frequency can be configured
which is recommended for can bit rates over 2MHz for good interoperability
between nodes.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit is contained in:
Thomas Stranger 2024-03-23 15:34:07 +01:00 committed by Anas Nashif
parent edbe34eaf2
commit 26f44a6d92
1 changed files with 1 additions and 1 deletions
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boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi
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@ -66,7 +66,7 @@
div-m = <2>; div-m = <2>;
mul-n = <120>; mul-n = <120>;
div-p = <2>; div-p = <2>;
div-q = <2>; div-q = <3>;
div-r = <2>; div-r = <2>;
clocks = <&clk_hse>; clocks = <&clk_hse>;
status = "okay"; status = "okay";