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drivers: reset: gd32: add initial support

Browse source 
Add a new reset driver for GD32 platforms. This driver controls the
reset registers from the RCU peripheral. It can be used to restore
peripherals to their initial state when initializing a device.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2022-08-22 23:41:37 +02:00 committed by Carles Cufí
parent aae94737ee
commit 28b59890a6
19 changed files with 734 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
drivers/reset/CMakeLists.txt
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@ -1,4 +1,5 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_library()
zephyr_library_sources_ifdef(CONFIG_RESET_GD32 reset_gd32.c)
zephyr_library_sources_ifdef(CONFIG_RESET_RPI_PICO reset_rpi_pico.c)

1
drivers/reset/Kconfig
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@ -28,5 +28,6 @@ config RESET_INIT_PRIORITY
comment "Reset Controller Drivers"
rsource "Kconfig.rpi_pico"
rsource "Kconfig.gd32"
endif # RESET

7
drivers/reset/Kconfig.gd32 Normal file
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@ -0,0 +1,7 @@
# Copyright (c) 2022 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
config RESET_GD32
bool "GD32 Reset Controller Driver"
default y
depends on DT_HAS_GD_GD32_RCTL_ENABLED

79
drivers/reset/reset_gd32.c Normal file
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@ -0,0 +1,79 @@
/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT gd_gd32_rctl
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/reset.h>
/** RCU offset (from id field) */
#define GD32_RESET_ID_OFFSET(id) (((id) >> 6U) & 0xFFU)
/** RCU configuration bit (from id field) */
#define GD32_RESET_ID_BIT(id) ((id) & 0x1FU)
struct reset_gd32_config {
uint32_t base;
};
static int reset_gd32_status(const struct device *dev, uint32_t id,
uint8_t *status)
{
const struct reset_gd32_config *config = dev->config;
*status = !!sys_test_bit(config->base + GD32_RESET_ID_OFFSET(id),
GD32_RESET_ID_BIT(id));
return 0;
}
static int reset_gd32_line_assert(const struct device *dev, uint32_t id)
{
const struct reset_gd32_config *config = dev->config;
sys_set_bit(config->base + GD32_RESET_ID_OFFSET(id),
GD32_RESET_ID_BIT(id));
return 0;
}
static int reset_gd32_line_deassert(const struct device *dev, uint32_t id)
{
const struct reset_gd32_config *config = dev->config;
sys_clear_bit(config->base + GD32_RESET_ID_OFFSET(id),
GD32_RESET_ID_BIT(id));
return 0;
}
static int reset_gd32_line_toggle(const struct device *dev, uint32_t id)
{
(void)reset_gd32_line_assert(dev, id);
(void)reset_gd32_line_deassert(dev, id);
return 0;
}
static const struct reset_driver_api reset_gd32_driver_api = {
.status = reset_gd32_status,
.line_assert = reset_gd32_line_assert,
.line_deassert = reset_gd32_line_deassert,
.line_toggle = reset_gd32_line_toggle,
};
static int reset_gd32_init(const struct device *dev)
{
return 0;
}
static const struct reset_gd32_config config = {
.base = DT_REG_ADDR(DT_INST_PARENT(0)),
};
DEVICE_DT_INST_DEFINE(0, reset_gd32_init, NULL, NULL, &config, PRE_KERNEL_1,
CONFIG_RESET_INIT_PRIORITY, &reset_gd32_driver_api);

13
dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi
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@ -9,6 +9,7 @@
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/reset/gd32e10x.h>
/ {
cpus {
@ -29,6 +30,18 @@
compatible = "mmio-sram";
};
rcu: reset-clock-controller@40021000 {
compatible = "gd,gd32-rcu";
reg = <0x40021000 0x400>;
status = "okay";
rctl: reset-controller {
compatible = "gd,gd32-rctl";
#reset-cells = <1>;
status = "okay";
};
};
fmc: flash-controller@40022000 {
compatible = "gd,gd32-flash-controller";
reg = <0x40022000 0x400>;

13
dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi
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@ -9,6 +9,7 @@
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/reset/gd32e50x.h>
/ {
cpus {
@ -29,6 +30,18 @@
compatible = "mmio-sram";
};
rcu: reset-clock-controller@40021000 {
compatible = "gd,gd32-rcu";
reg = <0x40021000 0x400>;
status = "okay";
rctl: reset-controller {
compatible = "gd,gd32-rctl";
#reset-cells = <1>;
status = "okay";
};
};
fmc: flash-controller@40022000 {
compatible = "gd,gd32-flash-controller";
reg = <0x40022000 0x400>;

13
dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi
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@ -8,6 +8,7 @@
#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/adc/gd32f3x0.h>
#include <zephyr/dt-bindings/reset/gd32f3x0.h>
/ {
cpus {
@ -26,6 +27,18 @@
compatible = "mmio-sram";
};
rcu: reset-clock-controller@40021000 {
compatible = "gd,gd32-rcu";
reg = <0x40021000 0x400>;
status = "okay";
rctl: reset-controller {
compatible = "gd,gd32-rctl";
#reset-cells = <1>;
status = "okay";
};
};
fmc: flash-controller@40022000 {
compatible = "gd,gd32-flash-controller";
reg = <0x40022000 0x400>;

14
dts/arm/gigadevice/gd32f403/gd32f403.dtsi
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@ -8,8 +8,8 @@
#include <freq.h>
#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/reset/gd32f403.h>
/ {
cpus {
@ -36,6 +36,18 @@
compatible = "mmio-sram";
};
rcu: reset-clock-controller@40021000 {
compatible = "gd,gd32-rcu";
reg = <0x40021000 0x400>;
status = "okay";
rctl: reset-controller {
compatible = "gd,gd32-rctl";
#reset-cells = <1>;
status = "okay";
};
};
fmc: flash-controller@40022000 {
compatible = "gd,gd32-flash-controller";
reg = <0x40022000 0x400>;

14
dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
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@ -7,8 +7,8 @@
#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/reset/gd32f4xx.h>
/ {
cpus {
@ -35,6 +35,18 @@
reg = <0x20000000 DT_SIZE_K(112)>;
};
rcu: reset-clock-controller@40023800 {
compatible = "gd,gd32-rcu";
reg = <0x40023800 0x400>;
status = "okay";
rctl: reset-controller {
compatible = "gd,gd32-rctl";
#reset-cells = <1>;
status = "okay";
};
};
fmc: flash-controller@40023c00 {
compatible = "gd,gd32-flash-controller";
reg = <0x40023c00 0x400>;

15
dts/bindings/mfd/gd,gd32-rcu.yaml Normal file
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@ -0,0 +1,15 @@
# Copyright (c) 2022, Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
description: |
Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
charge of reset control (RCTL) and clock control (CCTL) for all SoC
peripherals. Child nodes are used to represent each functional block.
compatible: "gd,gd32-rcu"
include: base.yaml
properties:
reg:
required: true

32
dts/bindings/reset/gd,gd32-rctl.yaml Normal file
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@ -0,0 +1,32 @@
# Copyright (c) 2022, Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0
description: |
Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
charge of reset control (RCTL) and clock control (CCTL) for all SoC
peripherals. This binding represents the reset controller (RCTL).
To specify the reset line in a peripheral, the standard resets property needs
to be used, e.g.:
gpioa: gpio@xxx {
...
/* cell encodes RCU register offset and control bit position */
resets = <&rctl GD32_RESET_GPIOA>;
...
}
Predefined RCU reset cells are available in
include/zephyr/dts-bindings/reset/gd32{xxx}.h header files, where {xxx}
corresponds to the SoC series, e.g. f4xx.
compatible: "gd,gd32-rctl"
include: [reset-controller.yaml, base.yaml]
properties:
"#reset-cells":
const: 1
reset-cells:
- id

14
dts/riscv/gigadevice/gd32vf103.dtsi
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@ -8,8 +8,8 @@
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/timer/nuclei-systimer.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/reset/gd32vf103.h>
/ {
#address-cells = <1>;
@ -56,6 +56,18 @@
0xd2001000 0x1000>;
};
rcu: reset-clock-controller@40021000 {
compatible = "gd,gd32-rcu";
reg = <0x40021000 0x400>;
status = "okay";
rctl: reset-controller {
compatible = "gd,gd32-rctl";
#reset-cells = <1>;
status = "okay";
};
};
fmc: flash-controller@40022000 {
compatible = "gd,gd32-flash-controller";
reg = <0x40022000 0x400>;

23
include/zephyr/dt-bindings/reset/gd32-common.h Normal file
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@ -0,0 +1,23 @@
/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_
/**
* Encode RCU register offset and configuration bit.
*
* - 0..5: bit number
* - 6..14: offset
* - 15: reserved
*
* @param reg RCU register name (expands to GD32_{reg}_OFFSET)
* @param bit Configuration bit
*/
#define GD32_RESET_CONFIG(reg, bit) \
(((GD32_ ## reg ## _OFFSET) << 6U) | (bit))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_ */

79
include/zephyr/dt-bindings/reset/gd32e10x.h Normal file
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@ -0,0 +1,79 @@
/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28U
#define GD32_ADDAPB1RST_OFFSET 0xE0U
/** @} */
/**
* @name Clock enable/disable definitions for peripherals
* @{
*/
/* APB2 peripherals */
#define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
#define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
#define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
#define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
#define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
#define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
#define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
#define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U)
#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
#define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U)
#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U)
#define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 19U)
#define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 20U)
#define GD32_RESET_TIMER10 GD32_RESET_CONFIG(APB2RST, 21U)
/* APB1 peripherals */
#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U)
#define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U)
#define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U)
#define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U)
#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
#define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U)
#define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 6U)
#define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U)
#define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U)
#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
#define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U)
#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
#define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U)
#define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U)
#define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U)
#define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
#define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U)
#define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U)
#define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U)
#define GD32_RESET_BKPI GD32_RESET_CONFIG(APB1RST, 27U)
#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
/* AHB peripherals */
#define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U)
/* APB1 additional peripherals */
#define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_ */

90
include/zephyr/dt-bindings/reset/gd32e50x.h Normal file
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@ -0,0 +1,90 @@
/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28U
#define GD32_ADDAPB1RST_OFFSET 0xE0U
/** @} */
/**
* @name Clock enable/disable definitions for peripherals
* @{
*/
/* APB2 peripherals */
#define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
#define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
#define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
#define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
#define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
#define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
#define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U)
#define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U)
#define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
#define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U)
#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
#define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U)
#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U)
#define GD32_RESET_ADC2 GD32_RESET_CONFIG(APB2RST, 15U)
#define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 19U)
#define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 20U)
#define GD32_RESET_TIMER10 GD32_RESET_CONFIG(APB2RST, 21U)
#define GD32_RESET_USART5 GD32_RESET_CONFIG(APB2RST, 28U)
#define GD32_RESET_SHRTIMER GD32_RESET_CONFIG(APB2RST, 29U)
#define GD32_RESET_CMP GD32_RESET_CONFIG(APB2RST, 31U)
/* APB1 peripherals */
#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U)
#define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U)
#define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U)
#define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 2U)
#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
#define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U)
#define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 6U)
#define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U)
#define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U)
#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
#define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U)
#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
#define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U)
#define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U)
#define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U)
#define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
#define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U)
#define GD32_RESET_I2C2 GD32_RESET_CONFIG(APB1RST, 24U)
#define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U)
#define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U)
#define GD32_RESET_BKPI GD32_RESET_CONFIG(APB1RST, 27U)
#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
/* AHB peripherals */
#define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U)
#define GD32_RESET_ENET GD32_RESET_CONFIG(AHBRST, 14U)
#define GD32_RESET_TMU GD32_RESET_CONFIG(AHBRST, 30U)
#define GD32_RESET_SQPI GD32_RESET_CONFIG(AHBRST, 31U)
/* APB1 additional peripherals */
#define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U)
#define GD32_RESET_CAN2 GD32_RESET_CONFIG(ADDAPB1RST, 31U)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_ */

65
include/zephyr/dt-bindings/reset/gd32f3x0.h Normal file
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@ -0,0 +1,65 @@
/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28U
#define GD32_ADDAPB1RST_OFFSET 0xE0U
/** @} */
/**
* @name Clock enable/disable definitions for peripherals
* @{
*/
/* APB2 peripherals */
#define GD32_RESET_CFGCMP GD32_RESET_CONFIG(APB2RST, 0U)
#define GD32_RESET_ADC GD32_RESET_CONFIG(APB2RST, 9U)
#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U)
#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U)
#define GD32_RESET_TIMER14 GD32_RESET_CONFIG(APB2RST, 16U)
#define GD32_RESET_TIMER15 GD32_RESET_CONFIG(APB2RST, 17U)
#define GD32_RESET_TIMER16 GD32_RESET_CONFIG(APB2RST, 18U)
/* APB1 peripherals */
#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U)
#define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U)
#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
#define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U)
#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
#define GD32_RESET_CEC GD32_RESET_CONFIG(APB1RST, 30U)
/* AHB peripherals */
#define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U)
#define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U)
#define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHBRST, 18U)
#define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHBRST, 19U)
#define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHBRST, 20U)
#define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHBRST, 22U)
#define GD32_RESET_TSI GD32_RESET_CONFIG(AHBRST, 24U)
/* APB1 additional peripherals */
#define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F3X0_H_ */

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/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28U
#define GD32_ADDAPB1RST_OFFSET 0xE0U
/** @} */
/**
* @name Clock enable/disable definitions for peripherals
* @{
*/
/* APB2 peripherals */
#define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
#define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
#define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
#define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
#define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
#define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
#define GD32_RESET_GPIOF GD32_RESET_CONFIG(APB2RST, 7U)
#define GD32_RESET_GPIOG GD32_RESET_CONFIG(APB2RST, 8U)
#define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
#define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U)
#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
#define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U)
#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U)
#define GD32_RESET_ADC2 GD32_RESET_CONFIG(APB2RST, 15U)
#define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 19U)
#define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 20U)
#define GD32_RESET_TIMER10 GD32_RESET_CONFIG(APB2RST, 21U)
/* APB1 peripherals */
#define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U)
#define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U)
#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
#define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U)
#define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 6U)
#define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U)
#define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U)
#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
#define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U)
#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
#define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U)
#define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U)
#define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U)
#define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
#define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U)
#define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U)
#define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U)
#define GD32_RESET_BKPI GD32_RESET_CONFIG(APB1RST, 27U)
#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
/* AHB peripherals */
#define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U)
/* APB1 additional peripherals */
#define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_ */

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/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHB1RST_OFFSET 0x10U
#define GD32_AHB2RST_OFFSET 0x14U
#define GD32_AHB3RST_OFFSET 0x18U
#define GD32_APB1RST_OFFSET 0x20U
#define GD32_APB2RST_OFFSET 0x24U
#define GD32_ADDAPB1RST_OFFSET 0xE0U
/** @} */
/**
* @name Clock enable/disable definitions for peripherals
* @{
*/
/* AHB1 peripherals */
#define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHB1RST, 0U)
#define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHB1RST, 1U)
#define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 2U)
#define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHB1RST, 3U)
#define GD32_RESET_GPIOE GD32_RESET_CONFIG(AHB1RST, 4U)
#define GD32_RESET_GPIOF GD32_RESET_CONFIG(AHB1RST, 5U)
#define GD32_RESET_GPIOG GD32_RESET_CONFIG(AHB1RST, 6U)
#define GD32_RESET_GPIOH GD32_RESET_CONFIG(AHB1RST, 7U)
#define GD32_RESET_GPIOI GD32_RESET_CONFIG(AHB1RST, 8U)
#define GD32_RESET_CRC GD32_RESET_CONFIG(AHB1RST, 12U)
#define GD32_RESET_BKPSRAM GD32_RESET_CONFIG(AHB1RST, 18U)
#define GD32_RESET_TCMSRAM GD32_RESET_CONFIG(AHB1RST, 20U)
#define GD32_RESET_DMA0 GD32_RESET_CONFIG(AHB1RST, 21U)
#define GD32_RESET_DMA1 GD32_RESET_CONFIG(AHB1RST, 22U)
#define GD32_RESET_IPA GD32_RESET_CONFIG(AHB1RST, 23U)
#define GD32_RESET_ENET GD32_RESET_CONFIG(AHB1RST, 25U)
#define GD32_RESET_ENETTX GD32_RESET_CONFIG(AHB1RST, 26U)
#define GD32_RESET_ENETRX GD32_RESET_CONFIG(AHB1RST, 27U)
#define GD32_RESET_ENETPTP GD32_RESET_CONFIG(AHB1RST, 28U)
#define GD32_RESET_USBHS GD32_RESET_CONFIG(AHB1RST, 29U)
#define GD32_RESET_USBHSULPI GD32_RESET_CONFIG(AHB1RST, 30U)
/* AHB2 peripherals */
#define GD32_RESET_DCI GD32_RESET_CONFIG(AHB2RST, 0U)
#define GD32_RESET_TRNG GD32_RESET_CONFIG(AHB2RST, 6U)
#define GD32_RESET_USBFS GD32_RESET_CONFIG(AHB2RST, 7U)
/* AHB3 peripherals */
#define GD32_RESET_EXMC GD32_RESET_CONFIG(AHB3RST, 0U)
/* APB1 peripherals */
#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U)
#define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U)
#define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U)
#define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U)
#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
#define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U)
#define GD32_RESET_TIMER11 GD32_RESET_CONFIG(APB1RST, 6U)
#define GD32_RESET_TIMER12 GD32_RESET_CONFIG(APB1RST, 7U)
#define GD32_RESET_TIMER13 GD32_RESET_CONFIG(APB1RST, 8U)
#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
#define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U)
#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
#define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U)
#define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U)
#define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U)
#define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
#define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U)
#define GD32_RESET_I2C2 GD32_RESET_CONFIG(APB1RST, 23U)
#define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U)
#define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U)
#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
#define GD32_RESET_UART6 GD32_RESET_CONFIG(APB1RST, 30U)
#define GD32_RESET_UART7 GD32_RESET_CONFIG(APB1RST, 31U)
#define GD32_RESET_RTC GD32_RESET_CONFIG(BDCTL, 15U)
/* APB2 peripherals */
#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 0U)
#define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 1U)
#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 4U)
#define GD32_RESET_USART5 GD32_RESET_CONFIG(APB2RST, 5U)
#define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 8U)
#define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 9U)
#define GD32_RESET_ADC2 GD32_RESET_CONFIG(APB2RST, 10U)
#define GD32_RESET_SDIO GD32_RESET_CONFIG(APB2RST, 11U)
#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
#define GD32_RESET_SPI3 GD32_RESET_CONFIG(APB2RST, 13U)
#define GD32_RESET_SYSCFG GD32_RESET_CONFIG(APB2RST, 14U)
#define GD32_RESET_TIMER8 GD32_RESET_CONFIG(APB2RST, 16U)
#define GD32_RESET_TIMER9 GD32_RESET_CONFIG(APB2RST, 17U)
#define GD32_RESET_TIMER10 GD32_RESET_CONFIG(APB2RST, 18U)
#define GD32_RESET_SPI4 GD32_RESET_CONFIG(APB2RST, 20U)
#define GD32_RESET_SPI5 GD32_RESET_CONFIG(APB2RST, 21U)
#define GD32_RESET_TLI GD32_RESET_CONFIG(APB2RST, 26U)
/* APB1 additional peripherals */
#define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U)
#define GD32_RESET_IREF GD32_RESET_CONFIG(ADDAPB1RST, 31U)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_ */

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/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0x0CU
#define GD32_APB1RST_OFFSET 0x10U
#define GD32_AHBRST_OFFSET 0x28U
/** @} */
/**
* @name Clock enable/disable definitions for peripherals
* @{
*/
/* APB2 peripherals */
#define GD32_RESET_AFIO GD32_RESET_CONFIG(APB2RST, 0U)
#define GD32_RESET_GPIOA GD32_RESET_CONFIG(APB2RST, 2U)
#define GD32_RESET_GPIOB GD32_RESET_CONFIG(APB2RST, 3U)
#define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U)
#define GD32_RESET_GPIOD GD32_RESET_CONFIG(APB2RST, 5U)
#define GD32_RESET_GPIOE GD32_RESET_CONFIG(APB2RST, 6U)
#define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
#define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
#define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U)
#define GD32_RESET_SPI0 GD32_RESET_CONFIG(APB2RST, 12U)
#define GD32_RESET_TIMER7 GD32_RESET_CONFIG(APB2RST, 13U)
#define GD32_RESET_USART0 GD32_RESET_CONFIG(APB2RST, 14U)
/* APB1 peripherals */
#define GD32_RESET_TIMER1 GD32_RESET_CONFIG(APB1RST, 0U)
#define GD32_RESET_TIMER2 GD32_RESET_CONFIG(APB1RST, 1U)
#define GD32_RESET_TIMER3 GD32_RESET_CONFIG(APB1RST, 2U)
#define GD32_RESET_TIMER4 GD32_RESET_CONFIG(APB1RST, 3U)
#define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U)
#define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U)
#define GD32_RESET_WWDGT GD32_RESET_CONFIG(APB1RST, 11U)
#define GD32_RESET_SPI1 GD32_RESET_CONFIG(APB1RST, 14U)
#define GD32_RESET_SPI2 GD32_RESET_CONFIG(APB1RST, 15U)
#define GD32_RESET_USART1 GD32_RESET_CONFIG(APB1RST, 17U)
#define GD32_RESET_USART2 GD32_RESET_CONFIG(APB1RST, 18U)
#define GD32_RESET_UART3 GD32_RESET_CONFIG(APB1RST, 19U)
#define GD32_RESET_UART4 GD32_RESET_CONFIG(APB1RST, 20U)
#define GD32_RESET_I2C0 GD32_RESET_CONFIG(APB1RST, 21U)
#define GD32_RESET_I2C1 GD32_RESET_CONFIG(APB1RST, 22U)
#define GD32_RESET_CAN0 GD32_RESET_CONFIG(APB1RST, 25U)
#define GD32_RESET_CAN1 GD32_RESET_CONFIG(APB1RST, 26U)
#define GD32_RESET_BKPI GD32_RESET_CONFIG(APB1RST, 27U)
#define GD32_RESET_PMU GD32_RESET_CONFIG(APB1RST, 28U)
#define GD32_RESET_DAC GD32_RESET_CONFIG(APB1RST, 29U)
/* AHB peripherals */
#define GD32_RESET_USBFS GD32_RESET_CONFIG(AHBRST, 12U)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_ */